JP7670277B2 - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Description

This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Conventionally, in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench gate structure that uses silicon carbide (SiC) as the semiconductor material, it is known that various processes carried out during trench formation or after trench formation and before the formation of the gate insulating film can cause damage layers, excess carbon (C) precipitate layers, and dopant precipitate layers to form on the inner walls of the trench.

For example, in a semiconductor substrate made of silicon carbide, a trench is formed by anisotropic etching using high-density plasma, but a damaged layer is formed on the inner wall of the trench due to collisions of ions and radicals generated from the plasma. When the inner wall of the trench is sacrificially oxidized to remove the damaged layer on the inner wall of the trench, a silicon oxide (SiO ₂ ) film is formed by sacrificially oxidizing the inner wall of the trench, and excess carbon is desorbed from the surface region (silicon carbide portion) of the inner wall of the trench and precipitated on the inner wall of the trench, forming an excess carbon precipitate layer.

When high-temperature annealing (heat treatment) is performed to round the corners of the trench, the dopant is redeposited on the inner wall surface of the trench, forming a highly-doped dopant precipitate layer. The damaged layer, excess carbon precipitate layer, and dopant precipitate layer on the inner wall of the trench are removed by subjecting the inner wall of the trench to chemical dry etching (CDE) or plasma etching (PE) using a gas containing carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ).

A conventional method for manufacturing a silicon carbide semiconductor device will be described using a MOSFET as an example. FIG. 7 is a flowchart showing an outline of the conventional method for manufacturing a silicon carbide semiconductor device. To form a MOS gate for a conventional silicon carbide semiconductor device, first, a trench is formed from the front surface of a semiconductor substrate to a predetermined depth by photolithography and etching (hereinafter referred to as trench etching) (step S101). This trench etching is, for example, anisotropic etching using high-density plasma.

The semiconductor substrate is formed by sequentially stacking epitaxial layers that become the n ^- type drift region and the p-type base region on the front surface of an n ⁺ type starting substrate using silicon carbide as a semiconductor material. The main surface of the semiconductor substrate that faces the p-type epitaxial layer that becomes the p-type base region is referred to as the front surface, and the main surface of the semiconductor substrate that faces the n ⁺ type starting substrate is referred to as the back surface. In the process of step S101, the trench extends from the front surface of the semiconductor substrate through the n ⁺ type source region and the p-type base region formed in the p-type epitaxial layer to reach the n ^- type drift region.

A damaged layer is formed on the inner wall of the trench due to trench etching. In addition, in the trench etching, the etching rate near the first boundary between the ^n- type drift region and the p-type base region and near the second boundary between the p-type base region and the n ⁺ type source region is slower than the etching rate of the portion of the epitaxial layer between the first and second boundaries. The portion of the epitaxial layer with the slow etching rate remains as a protrusion on the side wall of the trench. As a result, a step is formed on the side wall of the trench 7 due to the protrusion.

Next, the corners of the trench are rounded by plasma etching or high-temperature (e.g., 1500°C or higher) annealing (step S102). The process of step S102 simultaneously etches the inner wall of the trench and causes surface diffusion of silicon (Si) and carbon (C) on the inner wall of the trench, rounding the corners of the trench. Furthermore, if the process of step S102 is performed by high-temperature annealing, a precipitate layer of dopant with a high impurity concentration is formed on the inner wall of the trench, as described above.

Next, the inner wall of the trench is sacrificially oxidized to form a sacrificial oxide film (step S103), and the sacrificial oxide film is removed to remove the damaged layer and the dopant precipitate layer generated on the inner wall of the trench. As described above, the sacrificial oxidation in step S103 forms an excess carbon precipitate layer on the inner wall of the trench. The process in step S103 can be omitted. Next, the inner wall of the trench is chemically dry etched or plasma etched using a gas containing _CF4 and _O2 (step S104).

The process of step S104 removes the excess carbon precipitate layer on the inner wall of the trench. If the process of step S103 is omitted, the process of step S104 removes the damage layer and dopant precipitate layer on the inner wall of the trench. Next, a gate insulating film is deposited along the inner wall of the trench (step S105), and then a gate electrode is formed inside the trench (step S106). Then, each part other than the MOS gate (not shown) is formed at a predetermined timing using a general method to complete a conventional silicon carbide semiconductor device.

As a conventional method for manufacturing a silicon carbide semiconductor device, a method has been proposed in which, after forming a trench, the inner wall of the trench is deposited without sacrificially oxidizing the inner wall of the trench, or after removing a damaged layer on the inner wall of the trench by chemical dry etching using a gas containing _CF4 and _O2 (see, for example, Patent Document 1 below). In Patent Document 1 below, the inner wall of the trench is not sacrificially oxidized, thereby preventing accelerated oxidation of the inner wall of the trench in a portion where an n ⁺ type source region having a higher impurity concentration than a p-type base region is exposed.

Patent No. 6299102

However, when etching is performed using a gas containing _CF4 and _O2 , new problems arise, such as the inner wall of the trench being thinly oxidized and an excess carbon precipitate layer being formed on the inner wall of the trench, or a carbon-based polymer containing fluorine being generated and attached to the inner wall of the trench. The excess carbon precipitate layer formed on the inner wall of the trench reduces the channel mobility and increases the on-resistance. The carbon-based polymer containing fluorine formed on the inner wall of the trench reduces the reliability of the gate insulating film.

The present invention aims to provide a silicon carbide semiconductor device and a method for manufacturing the same that can prevent a decrease in channel mobility and a decrease in the reliability of the gate insulating film in order to solve the problems associated with the conventional technology described above.

In order to solve the above problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region.

The trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region. A gate insulating film is provided along the inner wall of the trench. A gate electrode is provided inside the trench on the gate insulating film. A first electrode is electrically connected to the third semiconductor region and the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. A protrusion height at the interface between the regions of different conductivity types on the sidewall of the trench is 3 nm or less.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. A first step is performed to form a first conductivity type silicon carbide layer on a first conductivity type starting substrate made of silicon carbide, the first conductivity type being a first semiconductor region having a lower impurity concentration than the starting substrate. A second step is performed to form a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer, the second conductivity type being a second semiconductor region. A third step is performed to selectively form a first conductivity type third semiconductor region in a surface region of the second conductivity type silicon carbide layer. A fourth step is performed to form a trench penetrating the third semiconductor region and the second conductivity type silicon carbide layer to reach the first conductivity type silicon carbide layer by first etching.

A fifth step is performed in which the corners of the trench are rounded by heat treatment. After the fifth step, a sixth step is performed in which the inner wall of the trench is second-etched in a plasma atmosphere. After the sixth step, a seventh step is performed in which a gate insulating film is deposited along the inner wall of the trench. An eighth step is performed in which a gate electrode is formed on the gate insulating film inside the trench. The etching gas for the second etching does not include a first element that causes a carbon-containing deposit to adhere to the inner wall of the trench, and a second element that oxidizes the inner wall of the trench.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first element is carbon.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second element is oxygen.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that the etching gas for the second etching is nitrogen trifluoride gas.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the etching gas for the second etching is chlorine trifluoride gas.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second etching is chemical dry etching.

The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the etching amount of the second etching is a thickness of 100 nm or less in a direction perpendicular to the sidewall of the trench from the sidewall of the trench.

In addition, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the sixth step, in the first etching of the fourth step, the etching rates of the boundary between the first conductivity type silicon carbide layer and the second conductivity type silicon carbide layer, the boundary between the second conductivity type silicon carbide layer and the third semiconductor region, and the surface between each boundary are different on the sidewall of the trench, so that the height of the protrusions generated at each boundary is reduced by the second etching to 3 nm or less.

According to the above-mentioned invention, since the etching gas used in the second etching does not contain the second element that oxidizes the inner wall of the trench, the inner wall of the trench is not oxidized during the second etching, and therefore an excess carbon precipitate layer is not re-formed on the inner wall of the trench. Since the etching gas used in the second etching does not contain the first element that causes carbon-containing deposits to adhere to the inner wall of the trench, a fluorine-containing carbon-based polymer does not adhere to the inner wall of the trench during the second etching.

The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the effect of preventing a decrease in channel mobility and preventing a decrease in the reliability of the gate insulating film.

1 is a cross-sectional view showing an example of a structure of a silicon carbide semiconductor device according to an embodiment; 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a perspective view showing a schematic result of detecting the surface shape of the portion surrounded by frame A in FIG. 3 by AFM. 5 is an enlarged cross-sectional view of a portion of the sidewall of the trench of FIG. 4. 3 is a cross-sectional view showing a schematic surface shape of a sidewall of a trench immediately after the processing of step S4 in FIG. 2. 1 is a flowchart outlining a conventional method for manufacturing a silicon carbide semiconductor device.

Preferred embodiments of the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in layers and regions marked with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - marked with n or p respectively indicate a higher impurity concentration and a lower impurity concentration than layers or regions not marked with that letter. In the following description of the embodiments and the attached drawings, similar configurations are marked with the same reference numerals, and duplicate explanations will be omitted.

(Embodiment)
The structure of a silicon carbide semiconductor device according to an embodiment will be described using a MOSFET as an example. Fig. 1 is a cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to an embodiment. A silicon carbide semiconductor device 10 according to the embodiment shown in Fig. 1 is a vertical MOSFET having a general trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material.

The semiconductor substrate 30 is formed by sequentially stacking epitaxial layers 32 to 34 that become an n ^- type buffer region 2, an n ^- -type drift region (first semiconductor region) 3, and a p-type base region (second semiconductor region) 4 on the front surface of an n + -type starting substrate 31 that uses silicon carbide as a semiconductor material. The main surface of the semiconductor substrate 30 on the p-type epitaxial layer 34 side is referred to as the front surface, and the main surface on the n ⁺ -type starting substrate 31 side (the back surface of the n ⁺ -type starting substrate 31) is referred to as the back surface. The n ⁺ -type starting substrate 31 is an n ⁺ -type drain region 1.

The n-type epitaxial layer 32 is the n-type buffer region 2. The n ^- type buffer region 2 does not necessarily have to be provided. The n -type drift region 3 is an ⁿ -type epitaxial layer 33 (a first conductivity type silicon carbide layer) and is in contact with the n-type buffer region 2 (or the n ⁺ -type drain region 1 when the n-type buffer region 2 is not provided) in the depth direction Z. The p-type base region 4 is provided between the front surface of the semiconductor substrate 30 and the n ^-type drift region 3, in contact with the n ^-type drift region 3.

An n ⁺ type source region (third semiconductor region) 5 and a p ⁺ type contact region 6 are selectively provided between the front surface of the semiconductor substrate 30 and the p type base region 4 in contact with the p type base region 4. The n ⁺ type source region 5 and the p ⁺ type contact region 6 are exposed at the front surface of the semiconductor substrate 30. A portion of the p type epitaxial layer (second conductivity type silicon carbide layer) 34 excluding the n ⁺ type source region 5 and the p ⁺ type contact region 6 constitutes the p type base region 4.

When the MOSFET is in an on-state, a channel (n-type inversion layer) 4a is formed in a portion of the p-type base region 4 that is sandwiched between the n ⁺ -type source region 5 and the n ^- -type drift region 3. The p-type base region 4 may be exposed on the front surface of the semiconductor substrate 30 without providing the p ⁺ -type contact region 6. The trench 7 penetrates the n ⁺ -type source region 5 and the p-type base region 4 in the depth direction Z from the front surface of the semiconductor substrate 30 to reach the n ^- -type drift region 3.

The trench 7 extends linearly in a first direction X parallel to the front surface of the semiconductor substrate 30, for example. The corners of the trench 7 are rounded. By rounding the corners of the trench 7, the electric field applied to the gate insulating film 8 at the corners of the trench 7 can be alleviated, and therefore the gate breakdown voltage can be ensured. The corners of the trench 7 are the boundaries between the sidewalls and the bottom surface of the trench 7.

A first boundary 41 between the n ⁻ type drift region 3 and the p type base region 4, and a second boundary 42 between the p type base region 4 and the n ⁺ type source region 5 terminate at the sidewall of the trench 7. The termination portions of the first and second boundaries 41, 42 are exposed at the sidewall of the trench 7. No step is generated on the sidewall of the trench 7 at the termination portions of the first and second boundaries 41, 42, and the sidewall of the trench 7 is substantially flat over the entire surface thereof.

The absence of steps on the sidewall of trench 7 means that the heights of the protrusions 41a, 42a (see FIG. 3 described later) that occur at the end portions of the first and second boundaries 41, 42 on the sidewall of trench 7 are approximately 3 nm or less. The height of the protrusions 41a, 42a on the sidewall of trench 7 is the distance d (see FIG. 3) from the apex of the protrusions 41a, 42a on the sidewall of trench 7 to the portion of the sidewall surface of trench 7 excluding the protrusions 41a, 42a.

The protrusions 41a, 42a on the sidewalls of the trench 7 protrude into the trench 7 in the second direction Y perpendicular to the sidewalls of the trench 7, and extend in the first direction X along the sidewalls of the trench 7. The protrusions 41a, 42a on the sidewalls of the trench 7 have their most protruding points (apexes) on the ends of the first and second boundaries 41, 42, respectively, and have a substantially triangular cross-sectional shape that becomes lower from the apexes toward both main surfaces of the semiconductor substrate 30.

A gate insulating film 8 is provided along the inner wall of the trench 7. The gate insulating film 8 is, for example, a deposited oxide film such as a high temperature oxide (HTO) film. Inside the trench 7, a gate electrode 9 is provided on the gate insulating film 8 so as to fill the inside of the trench 7. The trench 7, gate insulating film 8, and gate electrode 9 form a MOS gate.

Interlayer insulating film 11 is provided on the front surface of semiconductor substrate 30 and covers gate electrode 9. Source electrode 12 is provided on interlayer insulating film 11 so as to be embedded in a contact hole in interlayer insulating film 11. Source electrode 12 is in ohmic contact with n ⁺ type source region 5 and p ⁺ type contact region 6 via the contact hole, and is electrically connected to p type base region 4, n ⁺ type source region 5, and p ⁺ type contact region 6.

When the p ⁺ type contact region 6 is not provided, the source electrode 12 makes ohmic contact with the p type base region 4 instead of the p ⁺ type contact region 6. A drain electrode 13 is provided on the entire back surface of the semiconductor substrate 30 (the back surface of the n ⁺ type starting substrate 31). The drain electrode 13 contacts the n ⁺ type drain region 1 (n ⁺ type starting substrate 31) and is electrically connected to the n ⁺ type drain region 1.

Next, a method for manufacturing a silicon carbide semiconductor device 10 according to an embodiment will be described with reference to FIGS. 1 to 6. FIG. 2 is a flowchart showing an overview of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. 2 shows only the process for forming a MOS gate. FIG. 3 is a cross-sectional view showing a state during the manufacturing process of a silicon carbide semiconductor device according to an embodiment. FIG. 3 shows a cross-sectional structure of trench 7 immediately after the processing of step S4 in FIG. 2, cut along a cutting line parallel to the second direction Y.

Figure 4 is a perspective view showing the surface shape of the portion enclosed by frame A in Figure 3 (the sidewall of trench 7) as detected by an atomic force microscope (AFM). Figure 4 shows the surface shape of the sidewall of the trench immediately after processing in step S1 in Figure 2. Figure 5 is a plan view showing a portion of the sidewall of the trench in Figure 4. Figure 6 is a plan view showing the surface shape of the sidewall of the trench immediately after processing in step S4 in Figure 2.

Figures 5 and 6 show the sidewall of trench 7 viewed from the second direction Y, showing the same location (near protrusions 41a and 42a) on the sidewall of trench 7. On the graph axes (three axes) in Figure 4, distances x and y are the distances on parallel lines in the first and second directions X and Y, respectively, and depth z is the distance (depth) on a parallel line in the depth direction Z. On the graph axes (two axes) in Figures 5 and 6, distances x and y are the distances on parallel lines in the first and second directions X and Y, respectively. In Figures 4 to 6, the height difference in the second direction Y is shown by hatching.

First, an n ⁺ type starting substrate 31 is prepared, which will become the n ⁺ type drain region 1, using silicon carbide as a semiconductor material. Next, epitaxial layers 32 to 34 which will become the n ^type buffer region 2, the n ^- type drift region 3, and the p type base region 4 are epitaxially grown in order on the front surface of the n + type starting substrate 31, to produce a semiconductor substrate (semiconductor wafer) 30. The thickness of the n type epitaxial layer 32 may be, for example, about 1 μm.

Next, the n ⁺ type source region 5 and the p ⁺ type contact region 6 are selectively formed in the surface region of the p type epitaxial layer 34 by ion implantation. Next, a heat treatment is performed to activate the impurities introduced by ion implantation. This heat treatment may be performed once after all the diffusion regions (n ⁺ type source region 5 and p ⁺ type contact region 6) to be formed by ion implantation have been formed, or may be performed each time a diffusion region is formed by ion implantation.

Next, a trench 7 is formed by photolithography and etching (trench etching) from the front surface of the semiconductor substrate 30 through the n ⁺ source region 5 and the p base region 4 to reach the n ⁻ drift region 3 (step S1: fourth process). The trench etching is, for example, anisotropic etching using high-density plasma. A damaged layer (not shown) is formed on the inner wall of the trench 7 due to the trench etching.

During this trench etching, steps are formed on the sidewalls of the trench 7 due to the protrusions 41a', 42a' (Figures 4 and 5). This is presumably because the etching rate near the first and second boundaries 41, 42 of the epitaxial layers 33, 34 is slower than the etching rate of the portion between the first and second boundaries 41, 42 of the epitaxial layers 33, 34, and the portions of the epitaxial layers 33, 34 with the slower etching rate remain on the sidewalls of the trench 7 as protrusions 41a', 42a'.

Next, the corners of the trench 7 are rounded by plasma etching or high-temperature annealing, for example at 1500°C or higher (step S2: fifth process). The process of step S2 simultaneously etches the inner wall of the trench 7 and causes surface diffusion of silicon (Si) and carbon (C) on the inner wall of the trench 7, rounding the corners of the trench 7. When the process of step S2 is performed by high-temperature annealing, a precipitate layer (not shown) of dopant with a high impurity concentration is formed on the inner wall of the trench 7.

Next, the inner wall of the trench 7 is sacrificially oxidized (step S3), and then the sacrificial oxide film is removed to remove the damaged layer and dopant precipitate layer formed on the inner wall of the trench 7. The sacrificial oxidation in step S3 forms an excess carbon precipitate layer (not shown) on the inner wall of the trench 7. The process in step S3 can be omitted. Next, the inner wall of the trench 7 is etched using an etching gas that does not contain a first element that causes deposits that cause characteristic deterioration to adhere to the inner wall of the trench 7, and does not contain a second element that oxidizes the inner wall of the trench 7 (step S4: sixth process).

The first element is, for example, carbon (C) which generates a carbon-based polymer (for example, a CF-based polymer) containing fluorine. The second element is, for example, oxygen (O) which bonds with silicon (Si) in the silicon carbide portion on the inner wall of the trench 7 to generate excess carbon (C). The etching gas used in the process of step S4 may be any gas that contains a halogen element such as fluorine (F) or chlorine (Cl) which causes an etching reaction, and does not contain either of the first or second elements, and for example, nitrogen trifluoride (NF ₃ ) gas or chlorine trifluoride (ClF ₃ ) gas can be used.

The process of step S4 is preferably isotropic, low-damage dry etching using radicals (hereinafter referred to as low-damage etching), such as chemical dry etching or plasma etching. For example, low-damage etching can be achieved by using plasma etching that uses radicals generated from plasma generated in the chamber. Alternatively, even lower-damage etching can be achieved by using chemical dry etching that uses radicals generated from plasma generated elsewhere and transported into the chamber.

By carrying out the process of step S4 under the above conditions, the inner wall of trench 7 can be etched without using oxygen, and the SiC surface (etching surface) is not oxidized. The etching surface is the front surface of semiconductor substrate 30 and the inner wall surface of trench 7. In addition, when fluorine atoms are contained in the etching gas used in the process of step S4, fluorine atoms have a small bond energy and are easily decomposed into radicals at low power, making it possible to perform low-damage etching.

In addition, all reaction products generated in the processing furnace (chamber) of the etching apparatus during processing in step S4 are gasified and exhausted to the outside from the processing furnace, so there is little surface roughening of the SiC surface due to reaction products generated during processing in step S4. Fluorine atoms contained in the etching gas adhere to the SiC surface, but since fluorine adhered to the SiC surface is removed by a cleaning process (not shown) performed between each of the processing steps S1 to S6, the etching gas used in the processing in step S4 may contain fluorine.

The process of step S4 removes the excess carbon precipitate layer on the inner wall of trench 7. If the process of step S3 is omitted, the process of step S4 removes the damage layer and the precipitate layer of dopant generated on the inner wall of trench 7 in the processes of steps S1 and S2. Since the process of step S4 uses an etching gas that does not contain the first and second elements, problems such as the oxidation of the inner wall of trench 7 to reform the excess carbon precipitate layer or the adhesion of a carbon-based polymer containing fluorine to the inner wall of the trench do not occur, as in the conventional method (Figure 7).

Furthermore, the processing of step S4 reduces the height (distance d) of the protrusions 41a', 42a' (see Figures 4 and 5) on the sidewall of the trench 7 to 3 nm or less. As a result, the protrusions 41a, 42a on the sidewall of the trench 7 are no longer in steps, and the entire sidewall of the trench 7 becomes substantially flat (see Figure 6). In Figures 1, 3, and 6, the protrusions on the sidewall of the trench 7 after processing of step S4 are indicated by the symbols 41a and 42a. The amount of etching of the sidewall of the trench 7 by the processing of step S4 (thickness in the second direction Y from the sidewall) is 100 nm or less.

Next, an HTO film, for example, is deposited as a gate insulating film 8 along the front surface of the semiconductor substrate 30 and the inner wall of the trench 7 (step S5: seventh process). Next, polysilicon (poly-Si), for example, is embedded inside the trench 7 to form a gate electrode 9 (step S6: eighth process). A MOS gate is composed of the trench 7, gate insulating film 8, and gate electrode 9 formed in steps S1 to S6. Then, the silicon carbide semiconductor device 10 of FIG. 1 is completed by forming each part other than the MOS gate (not shown) at a predetermined timing using a general method.

As described above, according to the embodiment, after heat treatment for rounding the corners of the trench and before depositing a gate insulating film along the sidewall of the trench, the dopant precipitate layer formed on the inner wall of the trench by the heat treatment, or, if sacrificial oxidation is performed after the heat treatment, the excess carbon precipitate layer formed on the inner wall of the trench by the sacrificial oxidation, is removed by etching the inner wall of the trench. This etching is dry etching in a plasma atmosphere using an etching gas that does not contain a first element that causes carbon-containing deposits to adhere to the inner wall of the trench and a second element that oxidizes the inner wall of the trench. This enables low-damage etching of the inner wall of the trench.

In addition, according to the embodiment, the etching gas used in the etching to remove the dopant precipitate layer or excess carbon precipitate layer on the inner wall of the trench does not contain a second element that oxidizes the inner wall of the trench, so that the inner wall of the trench is not oxidized during the etching, and the excess carbon precipitate layer is not reformed on the inner wall of the trench. This makes it possible to suppress a decrease in channel mobility. In addition, the etching gas used in the etching does not contain a first element that causes carbon-containing deposits to adhere to the inner wall of the trench, so that a fluorine-containing carbon-based polymer does not adhere to the inner wall of the trench during the etching. This makes it possible to suppress a decrease in reliability of the gate insulating film.

According to the embodiment, the height of the protrusions generated on the sidewall of the trench during trench etching at the first boundary between the n ^- type drift region and the p-type base region and the second boundary between the p-type base region and the n ⁺ type source region can be lowered by etching to remove the dopant precipitate layer or the excess carbon precipitate layer on the inner wall of the trench. This makes it possible to eliminate the step caused by the protrusion on the sidewall of the trench and make the sidewall of the trench into a substantially flat surface. The step caused by the protrusion is 3 nm or less. Since there is no step on the sidewall of the trench, it is possible to reduce the interface roughness scattering at the interface ( _SiO2 /SiC interface) between the gate insulating film and the silicon carbide part on the inner wall of the trench, and thus it is possible to suppress the decrease in channel mobility.

The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention is applicable not only to MOSFETs but also to other MOS-type semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) that have a p-type collector layer formed on the back surface of a semiconductor substrate, as long as they have a trench gate structure.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for trench gate type semiconductor devices, and are particularly suitable for trench gate type MOSFETs.

REFERENCE SIGNS LIST 1 n ⁺ type drain region 2 n type buffer region 3 n ^- type drift region 4 p type base region 5 n ⁺ type source region 6 p ⁺ type contact region 7 trench 8 gate insulating film 9 gate electrode 10 silicon carbide semiconductor device 11 interlayer insulating film 12 source electrode 13 drain electrode 30 semiconductor substrate 31 n ⁺ type starting substrate 32 n type epitaxial layer 33 n ^- type epitaxial layer 34 ^p type epitaxial layer 41 first boundary between n - type drift region and p type base region 41a, 42a protrusions on side surface of trench after etching in step S4 of FIG. 2 41a', 42a' protrusions generated on side surface of trench by etching in step S1 of FIG. 2 42 second boundary between p type base region and n ⁺ type source region X first direction in which trench extends parallel to front surface of semiconductor substrate Y: A second direction perpendicular to the sidewall of the trench Z: A depth direction d: A distance from a top of a protrusion on the sidewall of the trench to a surface (exposed surface) of the epitaxial layer exposed on the sidewall of the trench between the protrusions

Claims (9)

a semiconductor substrate made of silicon carbide;
a first semiconductor region of a first conductivity type provided within the semiconductor substrate;
a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region;
a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region;
a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region;
a gate insulating film provided along an inner wall of the trench;
a gate electrode provided on the gate insulating film inside the trench;
a first electrode electrically connected to the third semiconductor region and the second semiconductor region;
a second electrode provided on a second main surface of the semiconductor substrate;
Equipped with
a protrusion height of 3 nm or less at the interface between the regions of different conductivity type on the sidewall of the trench; A first step of forming a first conductivity type silicon carbide layer on a first conductivity type starting substrate made of silicon carbide, the first conductivity type silicon carbide layer being a first semiconductor region of the first conductivity type having an impurity concentration lower than that of the starting substrate;
a second step of forming a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer, the second conductivity type silicon carbide layer being a second semiconductor region of a second conductivity type;
a third step of selectively forming a third semiconductor region of a first conductivity type in a surface region of the second conductivity type silicon carbide layer;
a fourth step of forming a trench penetrating the third semiconductor region and the second conductivity type silicon carbide layer to reach the first conductivity type silicon carbide layer by a first etching;
A fifth step of rounding corners of the trench by heat treatment;
a sixth step of performing a second etching on the inner wall of the trench in a plasma atmosphere after the fifth step;
a seventh step of depositing a gate insulating film along an inner wall of the trench after the sixth step;
an eighth step of forming a gate electrode on the gate insulating film inside the trench;
Including,
a second etching gas that does not contain a first element that causes a carbon-containing deposit to adhere to the inner wall of the trench, and a second element that oxidizes the inner wall of the trench. The method for manufacturing a silicon carbide semiconductor device according to claim 2, characterized in that the first element is carbon. The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, characterized in that the second element is oxygen. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 4, characterized in that the etching gas for the second etching is nitrogen trifluoride gas. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 4, characterized in that the etching gas for the second etching is chlorine trifluoride gas. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 6, characterized in that the second etching is chemical dry etching. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 7, characterized in that the amount of etching in the second etching is 100 nm or less from the sidewall of the trench in a direction perpendicular to the sidewall of the trench. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 8, characterized in that in the sixth step, the etching rates of the boundary between the first conductive type silicon carbide layer and the second conductive type silicon carbide layer on the sidewall of the trench, the boundary between the second conductive type silicon carbide layer and the third semiconductor region, and the surface between the boundaries are different in the first etching of the fourth step, and the height of the protrusions generated at each of the boundaries is reduced by the second etching to 3 nm or less.

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