JP7674656B2 - Silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a silicon carbide semiconductor device, which is a power semiconductor device, and in particular to one having a trench structure.

Semiconductor power elements are required to have high breakdown voltage, low on-resistance, and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude greater than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth as thin and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by three orders of magnitude or more. In addition, because the band gap is approximately three times larger than Si, high temperature operation is also possible. SiC semiconductor elements are expected to exceed the performance of Si semiconductor elements, and the development of SiC power devices is underway.

Patent document 1 (JP 2015-72999 A) describes a semiconductor device having an n-type substrate made of silicon carbide, an n-type drift layer on the substrate, multiple trenches formed in a stripe pattern on the drift layer, a gate electrode formed in the trench via an insulating film, and an n-type current spreading layer formed on the drift layer and having a higher impurity concentration than the drift layer. The gate electrode constitutes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the bottom of the trench is covered with a p-type bottom layer.

JP 2015-72999 A

A structure with a trench is expected to increase the channel area and reduce the on-resistance. However, in general, there is a trade-off between on-resistance and breakdown voltage. In particular, when the JFET region is included, narrowing the JFET width increases the breakdown voltage, but also increases the resistance. For this reason, the design of the JFET region is very important. Furthermore, SiC has a wider band gap and higher dielectric breakdown strength than Si, but the electric field applied to the insulating film is correspondingly larger, so technology to alleviate the electric field of the insulating film is very important. If the electric field in the insulating film is strong, a leakage current occurs in the gate insulating film, leading to a decrease in the gate insulating film life or device malfunction such as dielectric breakdown of the gate insulating film. Therefore, there are technologies to improve the breakdown voltage of the gate insulating film by devising a gate insulating film formation process, and design technologies to alleviate the electric field applied to the gate insulating film. For example, it is effective to cover the bottom of the trench with a p-type layer, and there is a structure shown in Patent Document 1.

The current spreading layer described in Patent Document 1 is formed to avoid the problem that the depletion layer extending from the p-type layer narrows the current path between each p-type layer, increasing the on-resistance. Here, the potential of the p-type layer at the bottom of the trench is floating, and another p-type layer is formed between the trenches to prevent the gate insulating film from being destroyed by a surge. The presence of this p-type layer increases the cell pitch of the semiconductor device, and furthermore, a depletion layer is formed, which causes the problem of increased on-resistance.

Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

A brief overview of the representative embodiments disclosed in this application is as follows:

In one embodiment of the silicon carbide semiconductor device, in a vertical MISFET with a gate electrode embedded in a trench, an accumulation layer formation region, which is a semiconductor region of the same conductivity type as the source region, is formed on the side of the trench below the lower end of the source region. Here, when the boundary between the region where the depletion layer extending from the body layer contacts the side of the trench when off and the region where the depletion layer is separated from the side of the trench is defined as a first point, and the point on the boundary surface between the accumulation layer formation region and the body layer that is closest to the first point is defined as a second point, a part of the body layer is located below the second point.

The effects achieved by the representative inventions disclosed in this application can be briefly explained as follows:

The present invention can improve the performance of silicon carbide semiconductor devices.

1 is a plan view showing a silicon carbide semiconductor device according to a first embodiment of the present invention; 2 is a cross-sectional view taken along line AA in FIG. 1. 1 is an enlarged cross-sectional view showing a silicon carbide semiconductor device according to a first embodiment of the present invention; 1 is an enlarged cross-sectional view showing a silicon carbide semiconductor device according to a first embodiment of the present invention; 1 is a conceptual cross-sectional view illustrating a shape of a semiconductor region of a silicon carbide semiconductor device according to a first embodiment of the present invention. 1 is a graph showing the relationship between the concentration of an accumulation layer formation region and the on-resistance and the breakdown voltage. 1 is a graph showing the relationship between breakdown voltage and on-resistance. 1 is an enlarged cross-sectional view showing a silicon carbide semiconductor device according to a modified example of the first embodiment of the present invention. FIG. 11 is a plan view showing a silicon carbide semiconductor device according to a second embodiment of the present invention. FIG. 11 is a perspective view showing a silicon carbide semiconductor device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view showing a silicon carbide semiconductor device according to a third embodiment of the present invention.

The following describes in detail the embodiments of the present invention with reference to the drawings. In all the drawings used to explain the embodiments, the same reference numerals are used for components having the same functions, and repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts are not repeated as a rule, unless particularly necessary. In the drawings explaining the embodiments, hatching may be used even in plan views or perspective views to make the configuration easier to understand. In the drawings explaining the embodiments, hatching may be omitted in cross-sectional views to make the configuration easier to understand.

Additionally, " ^- " and " ⁺ " are symbols that indicate the relative impurity concentrations of n-type and p-type conductivity. For example, the concentration of n-type impurities increases in the order of " ^n-- ", " ^n- ", "n", "n ⁺ ", and "n ⁺⁺ ".

(Embodiment 1)
Hereinafter, a silicon carbide semiconductor device will be described with reference to the drawings, taking as an example a SiC power MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a side surface of a trench (groove, recess) as a channel region, that is, a trench-type MOSFET.

<Structure of Silicon Carbide Semiconductor Device>
The structure of the silicon carbide semiconductor device according to the present embodiment 1 will be described with reference to Figures 1 to 5. In Figure 1, an extended portion that is a part of a source electrode is shown as a structure on a semiconductor substrate, but an insulating film and a part of a gate electrode that are other structures on the semiconductor substrate are not shown.

As shown in FIG. 1, the cell array constituting the silicon carbide semiconductor device of the present embodiment has a configuration in which a plurality of unit cells having a predetermined planar layout are arranged in a matrix. In FIG. 1, one unit cell is surrounded by a dashed line. The X direction and the Y direction shown in FIG. 1 are directions along the upper surface (main surface) of the semiconductor substrate. The X direction and the Y direction are orthogonal to each other in a planar view. The silicon carbide semiconductor device has a source electrode 1 formed on a semiconductor substrate and extending in the X direction. In FIG. 1, a plurality of source electrodes 1 extending in the X direction are arranged in the Y direction, but the source electrodes 1 are integrated through a source electrode 1 (not shown) covering the cell array on the plurality of source electrodes 1 arranged in a stripe shape, and are electrically connected to each other. The source electrode 1 is electrically connected to a potential fixing region 14 which is a p ⁺⁺ type semiconductor region formed on the upper surface of the semiconductor substrate. In the following description, when the term "source electrode" is used, the source electrode 1 refers to a portion (source plug) formed in a stripe shape in a planar view, except when otherwise specified, and does not include the source electrode 1 on the plurality of stripe-shaped source electrodes 1.

One unit cell has a source region 6, which is an n ⁺⁺ type semiconductor region formed on the upper surface of a semiconductor substrate, a potential fixing region 14 surrounding the periphery of the source region 6, and a trench 9 formed on the upper surface of the semiconductor substrate in contact with the source region 6 and the potential fixing region 14 in a plan view. A plurality of trenches 9 are formed in contact with the source region 6, aligned in the Y direction and the X direction. A gate electrode 2 is embedded inside each trench 9 via a gate insulating film 8. In the present application, the gate electrode 2 in the trench 9 may be referred to as a trench gate electrode. The source electrode 1 extends so as to straddle the source region 6 and the potential fixing region 14 surrounding the periphery of the source region 6. In other words, the source region 6 and the potential fixing region 14 are formed directly below the extending source electrode 1.

When the trench 9 and the potential fixing region 14 are spaced apart, the trench 9 is completely surrounded by the source region 6 in a planar view. In the structure shown in FIG. 1, one unit cell has both ends in the X direction in a planar view.

One unit cell includes one source region 6 and eight trenches 9 adjacent to the source region 6. That is, one unit cell has four trenches 9 aligned in the Y direction and four trenches 9 aligned in the Y direction in the X direction. A source electrode 1 extending in the X direction is disposed between the trenches 9 adjacent to each other in the Y direction in one unit cell. Here, an example in which eight trenches 9 are aligned is described above, but the number and arrangement of the trenches 9 formed in the unit cell are not limited to this. In a plan view, such unit cells are aligned in the Y direction and are aligned in the X direction while being inverted. In other words, the unit cells adjacent to each other in the X direction have a planar layout that is line-symmetrical with respect to the boundary line between them. In other words, the structures of the unit cells adjacent to each other in the X direction are line-symmetrical in a plan view.

Although the trench 9 here extends in the X direction, it does not necessarily have to extend in the X direction. However, by extending the trench 9 in the X direction, the channel width of the SiC power MISFET can be easily increased. In this embodiment, the island-shaped trench gate electrodes are arranged spaced apart from each other in the Y direction, so that by extending the trench 9 in the X direction, the channel width can be easily increased and the on-resistance of the SiC power MISFET can be reduced.

As shown in FIG. 2, the silicon carbide semiconductor device of the present embodiment has an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as a SiC epitaxial substrate or a semiconductor substrate). The SiC epitaxial substrate (semiconductor substrate) is a laminated substrate composed of an n ⁺ type silicon carbide substrate containing silicon carbide and an n-type epitaxial layer (semiconductor layer) formed on the silicon carbide substrate by an epitaxial growth method. The epitaxial layer is a semiconductor layer containing SiC. The upper surfaces of the silicon carbide substrate and the semiconductor substrate are parallel to each other. FIG. 2 shows a drift layer 4 which is an n-type semiconductor region that mainly constitutes the epitaxial layer, and shows a drain region 12 composed of a silicon carbide substrate of an n ⁺ type semiconductor region below the drift layer 4. That is, in FIG. 2, the portion shown as the drain region 12 is a silicon carbide substrate.

That is, a drain region 12 is formed in the semiconductor substrate, and a drift layer 4 is formed in the semiconductor substrate on and in contact with the drain region 12. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. The drift layer 4, the body layer 5, the source region 6, the accumulation layer formation region 7, the drain region 12, and the potential fixing region 14 are formed in the epitaxial layer. The drift layer 4, the source region 6, the accumulation layer formation region 7, and the drain region 12 are n-type semiconductor regions.

A drain electrode 3 is formed in contact with the lower surface of the drain region 12, i.e., the lower surface of the semiconductor substrate. That is, the lower surface of the semiconductor substrate is covered with the drain electrode 3, and the drain electrode 3 is electrically connected to the drain region 12. The drain electrode 3 is made of a laminated conductor film containing, for example, gold (Au). A source region 6 is formed on the upper surface of the semiconductor substrate (upper surface of the epitaxial layer), and a body layer 5, which is a p-type semiconductor region, is formed between the source region 6 and the drift layer 4 in contact with the lower surface of the source region 6. That is, the body layer 5 is formed from the lower end of the source region 6 to the mid-depth of the epitaxial layer (drift layer 4). The source region 6 has a higher n-type impurity concentration than both the drift layer 4 and the accumulation layer formation region 7 described below, and is electrically connected to the source electrode 1.

The lower surface of the body layer 5 and the upper surface of the drift layer 4 are in contact with each other. Here, the drift layer 4 is formed in the epitaxial layer below the body layer 5, extending from the lower surface of the body layer 5 to the lower surface of the epitaxial layer. In other words, the lower surface of the drift layer 4 is in contact with the drain region 12, i.e., the silicon carbide substrate.

Trench 9 is formed from the upper surface of the semiconductor substrate (upper surface of the epitaxial layer) to the middle depth of drift layer 4. In other words, trench 9 penetrates body layer 5 and reaches the upper surface of drift layer 4. Below source region 6, the side of trench 9 is covered by body layer 5, which is a p-type semiconductor region. Trench 9 is formed from the upper surface of the epitaxial layer (upper surface of semiconductor substrate) to the middle depth of the epitaxial layer below the lower end of source region 6.

The gate electrode 2 is completely buried in the trench 9 via the gate insulating film 8. The gate electrode 2 in the trench 9 is formed on the source region 6 via the insulating film 10 and the gate insulating film 8. The insulating film 10 is formed on the semiconductor substrate adjacent to the trench 9, and the gate insulating film 8 is formed so as to cover the inner surface of the trench 9 as well as the side and top surface of the insulating film 10. The gate electrode 2 is formed within the trench 9 and directly above the insulating film 10. On the semiconductor substrate, the insulating film 10, the gate insulating film 8 and the gate electrode 2 are covered with an insulating film 11. The gate electrode 2 is made of, for example, a polysilicon film, and the gate insulating film 8 and the insulating film 11 are made of, for example, a silicon oxide film.

A source electrode 1 is formed in a connection hole penetrating an insulating film 11 on a semiconductor substrate and on the insulating film 11. The source electrode 1 completely filling the connection hole and the source electrode 1 on the insulating film 11 are integrated with each other. At the bottom of the connection hole, the source electrode 1 is connected to a potential fixing region 14. The gate insulating film 8 and the insulating film 11 are made of, for example, a silicon oxide film. The insulating film 10 is a film used as a hard mask when forming the trench 9 by etching, and is made of, for example, a silicon nitride film.

The potential fixing region 14 is formed on the upper surface of the semiconductor substrate adjacent to the source region 6 in the Y direction. That is, the potential fixing region 14 and the source region 6 are formed from the upper surface of the semiconductor substrate to a predetermined depth. The lower surface of the potential fixing region 14 is in contact with the upper surface of the body layer 5. The potential fixing region 14 has a higher p-type impurity concentration than the body layer 5. The source electrode 1 embedded in the opening (connection hole) of the insulating film 11 is connected to the upper surface of the potential fixing region 14. Since the body layer 5 is electrically connected to the source electrode 1 through the potential fixing region 14, a source voltage can be applied from the source electrode 1 to the body layer 5. The source electrode 1 is formed on the insulating film 11 and in the opening of the insulating film 11. In addition, in a place not shown in FIG. 2, a gate pad electrically connected to the gate electrode (trench gate electrode) 2 is also formed on the insulating film 11 at a distance from the source electrode 1.

As one of the main features of this embodiment, an accumulation layer formation region 7, which is an n-type semiconductor region, is formed along the surface of the trench 9 in the epitaxial layer. The accumulation layer formation region 7 is continuously formed along the side and bottom surface of the trench 9 at a position separated from the source region 6. In other words, the accumulation layer formation region 7 is formed below the lower end of the source region 6. Here, the side of the trench 9 has a taper with respect to the upper surface of the semiconductor substrate. The accumulation layer formation region 7 is a semiconductor region formed by implanting n-type impurities, for example, from a vertical direction with respect to the upper surface of the semiconductor substrate in which the trench 9 is formed, so that the depth of the accumulation layer formation region 7 in a direction perpendicular to the side surface of the trench 9 is greater on the lower side than on the upper side of the trench 9. In other words, the formation depth of the accumulation layer formation region 7 increases from the upper side to the lower side of the trench 9. The accumulation layer formation region 7 is, for example, a semiconductor region having a width of 20 to 300 nm from the side surface of the trench 9. The width of the accumulation layer formation region 7 from the side of the trench 9 depends on the taper angle of the trench 9 and the formation depth of the accumulation layer formation region 7, but is preferably 300 nm or less.

The lower end of the accumulation layer formation region 7 reaches the drift layer 4. In other words, a portion of the accumulation layer formation region 7 is formed within the drift layer 4 and is in contact with the drift layer 4. Therefore, the accumulation layer formation region 7 and the drift layer 4 are electrically connected.

Next, the operation of the SiC power MISFET of this embodiment will be described. The SiC power MISFET has at least a drain region 12, a source region 6, a body layer 5, and a gate electrode 2. A plurality of trenches 9 are formed in a line along the upper surface of the semiconductor substrate, and the drain region 12, the source region 6, the body layer 5, and the gate electrode 2 in the vicinity of each of these trenches 9 constitute a SiC power MISFET. In this SiC power MISFET, a low on-resistance is achieved by closely arranging a plurality of trenches.

When the SiC power MISFET is in the off state (hereinafter, sometimes referred to as the off state), a depletion layer extends from the body layer 5, and this depletion layer reaches the side of the trench 9. In FIG. 3, the outline of the depletion layer extending from the body layer 5 in the off state is shown by a dashed line. The SiC power MISFET is in the off state when, for example, the gate voltage Vg is 0 V. Note that FIG. 3 shows the depletion layer near one side of the trench 9, but does not show the depletion layer near the other side of the trench 9. Also, FIG. 3 does not show the gate electrode 2 and the interlayer insulating film (insulating film 11).

Even if most of the side surface of trench 9 is covered with accumulation layer formation region 7 which is an n-type semiconductor region as in this embodiment, the depletion layer extending from body layer 5 reaches the side surface of trench 9 during off-state, so that the breakdown voltage is maintained and no current flows. In order for the depletion layer to reach the side surface of trench 9 in this manner, accumulation layer formation region 7 needs to be formed shallow and with a lower impurity concentration than source region 6. The n-type impurity concentration of accumulation layer formation region 7 is, for example, 10 ¹⁸ cm ^-3 or less.

On the other hand, when the SiC power MISFET is in an on state (hereinafter sometimes referred to as "on state"), a channel is formed in the body layer 5 adjacent to the trench 9. Specifically, the channel is mainly formed on the surface of the trench 9. As a result, a current flows from the drain region 12 to the source region 6 through the drift layer 4, the accumulation layer formation region 7, and the body layer 5 in this order. The accumulation layer formation region 7 is a region in which electrons, which are carriers, are accumulated when the SiC power MISFET is on. Therefore, compared to a case in which the accumulation layer formation region 7 is not formed on the side surface of the trench 9, a current flows more easily into the epitaxial layer when the SiC power MISFET is on.

As described above, the accumulation layer formation region 7 must be formed shallow and with a low impurity concentration so that the depletion layer extending from the body layer 5 when the device is off crosses the accumulation layer formation region 7 and reaches the side of the trench 9. The shape of the accumulation layer formation region 7 and its relationship to the way the depletion layer spreads will be explained with reference to Figures 3 to 5.

As shown in FIG. 3, the boundary point between the source region 6 and the body layer 5 on the side of the trench 9 is designated as CH1. Also, the boundary point between the region where the depletion layer extending from the body layer 5 contacts the side of the trench 9 when off and the region below that where the depletion layer is separated from the side of the trench 9 is designated as CH2. In other words, point CH2 is the lower end point of the region where the depletion layer extending from the body layer 5 contacts the side of the trench 9 when off.

Here, the point on the boundary surface between the body layer 5 and the drift layer 4 that is closest to point CH2 is designated as JC. At this time, the width of the accumulation layer formation region 7, which is the distance on the line connecting point CH2 and point JC, is distance d, which is the same as the width of the depletion layer on the line passing through point CH2. Point JC is a point on the junction surface between the accumulation layer formation region 7, which is an n-type semiconductor region, and the body layer 5, which is a p-type semiconductor region. Here, a part of the body layer 5 is also formed below point JC. In other words, the boundary between the body layer 5 and the drift layer 4 is located below point JC (on the drain region 12 side). In other words, the bottom surface of the body layer 5 is located below point JC.

If the accumulation layer formation region 7 is formed too deep or if the impurity concentration of the accumulation layer formation region 7 is high, the depletion layer extending from the body layer 5 during off-state does not reach the side of the trench 9, and point CH2 and point JC do not exist. In this case, the depletion layer does not reach the side of the trench 9, and the breakdown voltage of the SiC power MISFET cannot be maintained. In this embodiment, by setting the depth and impurity concentration of the accumulation layer formation region 7 so that a part of the body layer 5 is formed below point JC, it is possible to reduce the on-resistance of the SiC power MISFET while maintaining the breakdown voltage.

4, a surface S1 indicated by a dashed line and a surface S2 indicated by a two-dot dashed line are defined. The surface S1 is a surface along the channel formation region. For example, the surface S1 is a surface that passes through points CH1 and CH2 and is along the X direction. The surface S2 is a surface along the junction surface between the body layer 5 and the accumulation layer formation region 7 at point JC. In this case, the angle between the surface S1 and the surface S2 is θ1. In FIG. 4, in order to make the dashed line indicating the surface S1 easier to understand, the dashed line is shifted toward the accumulation layer formation region 7 side from the side surface of the trench 9 and point CH2, but in reality, the dashed line overlaps with the side surface of the trench 9 and point CH2. This is also true for FIG. 5. Note that FIG. 5 is a conceptual cross-sectional view, and in order to make the figure easier to understand, the gate electrode and the gate insulating film are omitted, and the hatching of the epitaxial layer is omitted.

As shown in FIG. 5, when angle θ1 is at its largest, trench 9 has a V-shape. Due to the nature of surface S2, angle θ2 between the silicon carbide substrate (or semiconductor substrate) and surface S2 is never an obtuse angle, and is at most 90 degrees. Therefore, consider the case when angle θ3 between surface S1 and silicon carbide substrate (or semiconductor substrate) is at its smallest. When angle θ3 is at its smallest and angle θ2 is at its largest, angle θ1 between surface S1 and surface S2 is at its largest. Here, angle θ2 is set to its maximum value of 90 degrees.

At this time, the ratio of the depth Z of the trench 9 to the width X of the trench 9 is depth Z:width X = 1:2. This is because reducing the depth of the trench 9 reduces the breakdown voltage of the SiC power MISFET, and widening the width of the trench 9 increases the on-resistance of the SiC power MISFET. When the side of the accumulation layer formation region 7 opposite the trench 9 side is perpendicular to the semiconductor substrate, the maximum value of the angle θ1 is θ1 = atan (1/(2 × 0.5)) = 45°. Therefore, for example, the value of the angle θ1 is 45 degrees or less. A large angle θ1 indicates a large width of the trench 9. In other words, if the angle θ1 is large, the cell pitch becomes large, and the number of trenches 9 that can be arranged in the semiconductor device becomes smaller, resulting in a high on-resistance.

<Method of Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. The polarities described below may be reversed between p-type and n-type.

First, a silicon carbide substrate (wafer), that is, a SiC bulk substrate, is prepared. The surface orientation of the upper surface of the silicon carbide substrate is the Si surface, the C surface, or another surface orientation, and the off-angle of the upper surface is 4 degrees. The silicon carbide substrate may be a substrate produced using a sublimation method, a substrate produced using a solution method, a substrate produced using a gas growth method, or a substrate on which an epitaxial layer has already been deposited. Chemical mechanical polishing (CMP) may be performed before the epitaxial growth step described later. The n-type impurity concentration of the silicon carbide substrate is, for example, 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ , and is set to, for example, 1×10 ¹⁸ cm ⁻³ here. The silicon carbide substrate crystal type may be 4H-SiC, 6H, or 3C. Here, it is preferable to use a wafer having an off-angle on the upper surface, but a just substrate may also be used.

Next, an epitaxial layer is formed on the silicon carbide substrate by an epitaxial growth process. That is, SiH ₄ and C ₃ H ₈ are heated at a temperature of 1500° C. or higher using H ₂ as a carrier gas to perform epitaxial growth. As a result, an epitaxial layer is formed on the silicon carbide substrate. The impurity concentration and film thickness of the epitaxial layer at this time vary depending on the device to be manufactured. The impurity concentration is, for example, about 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ , and the film thickness is, for example, several μm to several tens of μm. In addition, a high-concentration buffer layer may be formed in the silicon carbide substrate before forming the epitaxial layer. The impurity concentration of the buffer layer is about 1×10 ¹⁸ cm ⁻³ . This epitaxial layer is also called a drift layer 4.

Next, the process of forming the ion implantation region will be described. The p-type implantation ions are Al (aluminum) or B (boron). The n-type implantation ions are N (nitrogen) or P (phosphorus).

A p-type body layer, a p ^++- type potential fixing region 14, and an n ^++- type source region 6 are each formed by ion implantation from the upper surface of the drift layer 4 to a predetermined depth within the drift layer 4. The body layer 5 may be formed by an epitaxial growth method. The source region 6 and the potential fixing region 14 are in contact with the upper surface of the wafer (upper surface of the semiconductor substrate) which is a SiC epitaxial substrate.

The body layer 5 is in contact with the source region 6 and is formed deeper than the source region 6. The body layer 5 is also electrically connected to the potential fixing region 14. Note that, although the present embodiment describes the minimum configuration for operating the SiC power MISFET, a structure that adds functions such as a termination region may also be fabricated.

Next, a carbon film is deposited around the semiconductor substrate consisting of the silicon carbide substrate and the epitaxial layer as a cap material for the impurity activation anneal. Then, the impurity activation anneal is performed at a temperature of, for example, 1600 to 1800°C. The carbon layer of the cap material is then removed by oxygen plasma ashing. This annealing has the effect of preventing the surface of the semiconductor substrate from becoming rough. After this, in order to obtain an even cleaner surface, a thermal oxide film may be formed to cover the surface of the semiconductor substrate, and then the thermal oxide film may be removed using a diluted hydrofluoric acid solution.

Next, the process of forming the trench 9, the accumulation layer formation region 7, and the gate electrode 2 will be described.

Here, a trench 9 is formed on the upper surface of the semiconductor substrate by etching using the insulating film 10 as a hard mask, penetrating the source region 6 and the body layer 5 and having its bottom within the drift layer. After this, a process for cleaning the etched surface may be performed. For example, this process involves forming a thermal oxide film that covers the surface of the semiconductor substrate including the surface of the trench 9, and then removing the thermal oxide film using a diluted hydrofluoric acid solution.

Next, an n-type accumulation layer formation region 7 is formed. The formation method can be, for example, ion implantation. The accumulation layer formation region 7 is a semiconductor region having a width of 20 to 300 nm from the side of the trench 9.

Next, a carbon film is deposited inside and around the trench 9 as a cap material for impurity activation annealing. The thickness of the deposited film at this time is, for example, 50 to 2000 nm. Thereafter, impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. The carbon layer of the cap material is then removed by oxygen plasma ashing. After this, in order to obtain an even cleaner surface, a thermal oxide film may be formed to cover the surface of the semiconductor substrate, and then the thermal oxide film may be removed using a diluted hydrofluoric acid solution.

Next, a gate insulating film 8 is formed on the semiconductor substrate. The thickness of the gate insulating film 8 is, for example, about 10 to 100 nm. The gate insulating film is made of, for example, a deposited oxide insulating film. Next, a gate electrode 2 is formed, made of an n-type polycrystalline silicon film with a thickness of about 100 to 300 nm. After that, an insulating film 11, which is an interlayer film, is formed to cover the gate electrode 2.

Next, a contact hole for contacting the source region 6 and the potential fixing region 14 is opened in the insulating film 11. That is, the insulating film 11 is etched using a resist pattern formed on the insulating film 11 as a mask to form a contact hole (opening) exposing the upper surface of the semiconductor substrate. Next, a metal film for silicide is deposited on the semiconductor substrate, and silicide is performed by, for example, annealing at 700°C to 1000°C, thereby forming a silicide layer (not shown) that contacts the upper surface of the semiconductor substrate at the bottom of the contact hole over the upper surfaces of the source region 6 and the potential fixing region 14. The silicide layer is a source-base common contact. After that, a contact hole for contacting the gate electrode 2 is opened in the insulating film 11. That is, the insulating film 11 is etched using a resist pattern formed on the insulating film 11 as a mask to form a contact hole (opening) exposing the upper surface of the gate electrode 2.

Next, the source electrode 1 is formed by filling the connection hole above the source region 6 of the insulating film 11 and covering the upper surface of the insulating film 11. After that, the lower surface of the drain region 12 on the lower side of the semiconductor substrate is also silicided to form a drain contact, and then the drain electrode 3 is formed. Materials such as Ni (nickel) or Al (aluminum) are used for the silicide metal film, source electrode 1, and drain electrode 3. After that, the entire surface of the semiconductor substrate is covered with a surface protection film made of an insulator to protect the device. After that, the semiconductor device of this embodiment is completed through a process of wiring each electrode.

<Effects of this embodiment>
In the semiconductor device of this embodiment, when the SiC power MISFET is in an on-state, a channel is formed in the semiconductor substrate adjacent to the trench 9, and a current flows through the channel. At this time, the accumulation layer formation region 7 is formed in the channel formation region, and the accumulation layer formation region 7 forms a carrier accumulation layer when on, so that a current flows more easily through the epitaxial layer when on, compared with a case in which the accumulation layer formation region 7 is not formed. Therefore, the on-resistance of the SiC power MISFET can be reduced.

On the other hand, when the SiC power MISFET is in the off state, the depletion layer extending from the body layer 5 crosses the accumulation layer formation region 7 and reaches the side of the trench 9, so the breakdown voltage of the SiC power MISFET can be maintained. In addition, most of the trench 9 is formed in the body layer 5, so the electric field concentration in the gate insulating film 8 in the trench 9 can be alleviated. In addition, in this case, the upper end of the accumulation layer formation region 7 does not reach the source region 6, so the breakdown voltage can be increased compared to when the upper end of the accumulation layer formation region 7 reaches the source region 6.

Here, the relationship between on-resistance and breakdown voltage will be explained using Figures 6 and 7. Figure 6 is a graph showing the relationship between the concentration of the accumulation layer formation region and the on-resistance and breakdown voltage, with the horizontal axis showing the impurity concentration of the accumulation layer formation region and the vertical axis showing the respective reduction rates of on-resistance and breakdown voltage. Among the plots shown in Figure 6, the circular plots show the on-resistance values, and the triangular plots show the breakdown voltage values. Figure 7 is a graph showing the relationship between breakdown voltage and on-resistance, with the horizontal axis showing the breakdown voltage and the vertical axis showing on-resistance.

It is desirable for the SiC power MISFET to have a low on-resistance and a high breakdown voltage, but there is a trade-off between on-resistance and breakdown voltage. As shown in Fig. 6, when the impurity concentration in the accumulation layer formation region is greater than 10 ¹⁸ cm ^-3 , the rate of decrease in on-resistance does not change much even if the concentration increases, but on the other hand, the rate of decrease in breakdown voltage increases as the concentration increases. Therefore, it is preferable that the n-type impurity concentration in the accumulation layer formation region 7 shown in Fig. 2 is 10 ¹⁸ cm ^-3 or less.

Figure 7 shows a graph of the relationship between the breakdown voltage and on-resistance of the SiC power MISFET of the comparative example (plots indicated by x in Figure 7) and the relationship between the breakdown voltage and on-resistance of the SiC power MISFET of this embodiment (plots indicated by squares in Figure 7). The SiC power MISFET of the comparative example differs from the structure shown in Figure 2 in that it does not have an accumulation layer formation region and the bottom of the trench reaches the drift layer.

As shown in FIG. 7, basically, when the breakdown voltage increases, the on-resistance also increases. Here, in order to lower the on-resistance in the SiC power MISFET of the comparative example, it is necessary to significantly lower the breakdown voltage. In contrast, in the SiC power MISFET of this embodiment, when the breakdown voltage is close to 1, the on-resistance can be reduced by about 20% with almost no change in the breakdown voltage. In this way, with the silicon carbide semiconductor device of this embodiment, it is possible to achieve both a reduction in on-resistance and ensuring the breakdown voltage.

<Modification>
A modified example of the present embodiment will be described below with reference to Fig. 8. The structure of this modified example differs from the structure described with reference to Figs. 1 to 5 in that the bottom surface of trench 9 does not reach drift layer 4.

That is, here, the trench 9 is formed from the upper surface of the semiconductor substrate (the upper surface of the epitaxial layer) to the middle depth of the body layer 5. That is, the trench 9 does not penetrate the body layer 5 and does not reach the upper surface of the drift layer 4. In other words, the bottom surface (lowest surface) of the trench 9 and the upper surface (top surface) of the drift layer 4 are separated from each other in a direction perpendicular to the upper surface of the semiconductor substrate. That is, the position of the bottom surface of the trench 9 is higher than the position of the top surface of the drift layer 4. Therefore, under the source region 6, the side and bottom surfaces of the trench 9 are covered by the body layer 5, which is a p-type semiconductor region. In addition, the corners, which are the boundary portions between the side surfaces and the bottom surface of the trench 9, are also covered by the body layer 5.

The accumulation layer formation region 7 covering the side of the trench 9 is in contact with the drift layer 4. In other words, the accumulation layer formation region 7 and the drift layer 4 are electrically connected. A JFET (Junction Field Effect Transistor) region 13 is formed in the region between the accumulation layer formation region 7 and the drift layer 4. When on, a current flows from the drift layer 4 through the JFET region 13 in the accumulation layer formation region 7 and the accumulation layer of the accumulation layer formation region 7, in that order, through the inversion layer of the body layer 5, and to the source region 6.

In this modification, when the SiC power MISFET is on, a current passes through the accumulation layer formation region 7, thereby reducing the on-resistance of the SiC power MISFET. On the other hand, when the SiC power MISFET is off, the depletion layer extending from the body layer 5 crosses the accumulation layer formation region 7 and reaches the side of the trench 9, thereby maintaining the breakdown voltage of the SiC power MISFET.

In addition, since the width of the JFET region 13 can be made very narrow, the breakdown voltage is increased. Also, since the corners of the trench 9 are in the body layer 5, the electric field concentration at the corners is alleviated. The length W of the accumulation layer formation region 7 in the drift layer 4 is, for example, 0 to 500 nm. From the viewpoint of increasing the breakdown voltage, a smaller length W is preferable because the depletion layer extends under the gate insulating film 8, increasing the breakdown voltage.

(Embodiment 2)
The structure of the silicon carbide semiconductor device according to the second embodiment will be described with reference to Figures 9 and 10. In Figure 9, an extended portion that is a part of the source electrode is shown as a structure on the semiconductor substrate, but the insulating film and part of the gate electrode that are structures on the semiconductor substrate are omitted. In Figure 10, in order to make the drawing easier to understand, the insulating films (gate insulating film and interlayer insulating film) and the gate electrode are partially omitted.

As shown in FIG. 9, the cell array constituting the silicon carbide semiconductor device of the present embodiment has a configuration in which a plurality of unit cells having a predetermined planar layout are arranged in a matrix. In FIG. 9, one unit cell is surrounded by a dashed line. The silicon carbide semiconductor device has a source electrode 1 formed on a semiconductor substrate and extending in the Y direction. In FIG. 9, a plurality of source electrodes 1 extending in the Y direction are arranged in the X direction, but the source electrodes 1 are integrated through a source electrode 1 (not shown) covering the cell array on the plurality of source electrodes 1 arranged in a stripe shape, and are electrically connected to each other. The source electrode 1 is electrically connected to a potential fixing region 14, which is a p ⁺⁺ type semiconductor region formed on the upper surface of the semiconductor substrate. In the following description, when the term "source electrode" is used, the source electrode 1 refers to a portion (source plug) formed in a stripe shape in a plan view, except when otherwise specified, and does not include the source electrode 1 on the plurality of stripe-shaped source electrodes 1.

One unit cell has a source region 6, which is an n ⁺⁺ type semiconductor region formed on the upper surface of a semiconductor substrate, a potential fixing region 14 surrounding the periphery of the source region 6, and a trench 9 formed on the upper surface of the semiconductor substrate in contact with the source region 6 and the potential fixing region 14 in a plan view. A plurality of trenches 9 are formed in the Y direction at the boundary between the source region 6 and the potential fixing region 14 extending in the Y direction. In FIG. 9, the region in which the plurality of trenches 9 are arranged in the Y direction is surrounded by a dashed line. The region surrounded by the dashed line is a trench formation region in which the plurality of trenches 9 are arranged in a stripe shape. A gate electrode 2 is embedded inside each trench 9 via a gate insulating film 8. The source electrode 1 extends so as to straddle the source region 6 and the potential fixing region 14 surrounding the periphery of the source region 6. In other words, the source region 6 and the potential fixing region 14 are formed directly below the extending source electrode 1.

One unit cell includes regions 1A and 1B aligned in the Y direction. Region 1B is formed at the end of the unit cell in the Y direction. Region 1A is a portion in which an element operating as a MISFET is formed, and region 1B is a region that electrically connects a p-type semiconductor region and a source electrode 1 to apply a source voltage to the p-type semiconductor region that constitutes the element. Here, a source region 6 and a trench 9 are formed only in region 1A, and in region 1B, the source electrode 1 is electrically connected to a potential fixing region 14 that is a p ⁺⁺ type semiconductor region.

When the trench 9 and the potential fixing region 14 are spaced apart, the trench 9 is entirely surrounded by the source region 6 in a plan view, and, for example, the source regions 6 of unit cells adjacent in the X direction are connected to each other.

In the structure shown in FIG. 9, one unit cell has both ends in the X direction in plan view, the source electrode 1 is located at one of the ends, and a potential fixing region 14 is formed on the upper surface of the epitaxial layer at the other of the ends. In other words, in plan view, of both ends of the unit cell in the X direction, the end opposite the end where the source electrode 1 is formed is separated from the source region 6. Therefore, in the X direction, the source regions 6 are connected between the first unit cell and the second unit cell adjacent to it on one side, and the source regions 6 are separated from each other between the first unit cell and the third unit cell adjacent to it on the other side.

One unit cell occupies the range from the center of one of two source electrodes 1 adjacent to each other in the X direction to the middle between those source electrodes 1. One unit cell also occupies the range consisting of one adjacent source region 6 and one potential fixing region 14 among source regions 6 and potential fixing regions 14 arranged alternately in the Y direction. In plan view, multiple such unit cells are lined up in the Y direction, and are lined up while being inverted in the X direction. In other words, unit cells adjacent to each other in the X direction have a planar layout that is line-symmetrical with respect to the boundary line between them. In other words, the structures of unit cells adjacent to each other in the X direction are line-symmetrical in plan view.

Although the trench 9 here extends in the X direction, it does not necessarily have to extend in the X direction. However, by extending the trench 9 in the X direction, the channel width of the SiC power MISFET can be easily increased. Such an increase in channel width is difficult to achieve in a trench-type MOSFET in which the trench gate electrode extends in the Y direction like the source electrode 1. In contrast, in this embodiment, the island-shaped trench gate electrodes are arranged spaced apart from each other in the Y direction, so that the channel width can be easily increased by extending the trench 9 in the X direction, and the on-resistance of the SiC power MISFET can be reduced.

As shown in FIG. 10, the silicon carbide semiconductor device of this embodiment has an n-type silicon carbide (SiC) epitaxial substrate (semiconductor substrate). A drain region 12 is formed in the semiconductor substrate, and a drift layer 4 is formed on and in contact with the drain region 12 in the semiconductor substrate. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. The drift layer 4, the body layer 5, the source region 6, the accumulation layer formation region 7, the current diffusion region 17, the guard region 18, the drain region 12, the JFET region 13, and the potential fixing region 14 are formed in the epitaxial layer.

A drain electrode 3 is formed in contact with the underside of the drain region 12, i.e., the underside of the semiconductor substrate. A source region 6 is formed on the upper surface of the semiconductor substrate (the upper surface of the epitaxial layer), and a body layer 5, which is a p-type semiconductor region, is formed between the source region 6 and the drift layer 4 in contact with the underside of the source region 6. The source region 6 has a higher n-type impurity concentration than the current diffusion region 17 described below, and is electrically connected to the source electrode 1.

A current diffusion region 17, which is an n ⁺ -type semiconductor region, is formed below the body layer 5 in contact with the lower surface of the body layer 5. A drift layer 4 is formed below the source electrode 1, which is adjacent to the current diffusion region 17 in the X direction and extends in the Y direction. Here, in the epitaxial layer below the body layer 5, the drift layer 4 is formed from the lower surface of the body layer 5 to the lower surface of the epitaxial layer. That is, the lower surface of the drift layer 4 is in contact with the drain region 12, i.e., the silicon carbide substrate. In the unit cell, the current diffusion region 17 is formed to surround the trench 9 in a plan view.

The current diffusion region 17 is a low-resistance region that diffuses the current flowing in the drift layer 4 in the X direction, allowing the current to flow over a wide area. In other words, forming the current diffusion region 17 makes it possible to prevent the current from flowing locally. The current diffusion region 17 is formed in region 1A shown in FIG. 9, but is not formed in region 1B. In other words, region 1B is separated from the source region 6 and the current diffusion region 17 in a planar view. In other words, region 1B does not overlap with the source region 6 and the current diffusion region 17 in a planar view.

A guard region 18, which is a p-type semiconductor region, is formed below the current diffusion region 17 and in contact with the bottom surface of the current diffusion region 17. A trench 9 is formed from the top surface of the semiconductor substrate (top surface of the epitaxial layer), i.e., the top surface of the body layer 5 of the source region 6, to the middle depth of the guard region 18. In other words, the trench 9 penetrates the body layer 5 and does not reach the bottom surface (bottom end) of the guard region 18. In other words, the bottom surface of the trench 9 and the bottom surface (bottom end) of the guard region 18 are spaced apart from each other.

The bottom surface of trench 9 is located deeper than the top surface (upper end) of guard region 18, so the lower ends of the four side surfaces of trench 9, which has a rectangular planar shape, are in contact with guard region 18. In other words, the four sides and four corners of the bottom surface of trench 9 are all covered by guard region 18. In other words, the bottom surface and the four side surfaces of trench 9 are in continuous contact with guard region 18. That is, trench 9 is surrounded by guard region 18 in plan view. In this way, trench 9 is formed from the top surface of the epitaxial layer to a depth halfway down the epitaxial layer below body layer 5.

Between the guard region 18 and the body layer 5, the four sides of the trench 9 are in contact with the current diffusion region 17 via the accumulation layer formation region 7. Therefore, when the SiC power MISFET is in the on state, a channel can be formed on all four sides of the trench 9.

A drift layer 4 is formed in a region adjacent to the guard region 18 in the X direction and directly below the source electrode 1 extending in the Y direction. A part of the drift layer 4 formed in the region adjacent to the guard region 18 in the X direction overlaps with the current diffusion region 17 in a planar view. In other words, the drift layer 4 and the guard region 18 are arranged side by side in the X direction directly below the current diffusion region 17. In other words, in a planar view, the end of the current diffusion region 17 on the source electrode 1 side is located closer to the source electrode 1 than the end of the guard region 18 on the source electrode 1 side.

As a result, in the region adjacent to the drift layer 4 directly below the source electrode 1 in the X direction, a layer made of the current diffusion region 17 and a layer made of the guard region 18 are formed overlapping in the vertical direction. The guard region 18 has a higher p-type impurity concentration than the body layer 5. The current diffusion region 17 and the guard region 18 are in contact with each other. Therefore, the body layer 5 and the guard region 18 are electrically connected to each other. By covering the bottom surface and corners of the trench 9 with the guard region 18, which has a higher p-type impurity concentration than the body layer 5, the electric field concentration at the corners of the trench 9 can be further alleviated compared to the first embodiment.

The trenches 9 are formed in a line in the Y direction, and the gate electrode 2 is completely embedded in each trench 9 via the gate insulating film 8. The gate electrodes 2 in each trench 9 are formed on the source region 6 via the gate insulating film 8, and are connected to each other by the gate electrodes 2 extending in the Y direction. In other words, in a cross section along the Y direction, the gate electrodes 2 have a comb-like structure. In other words, the trench gate electrodes lined up in the Y direction are connected in parallel to each other by the gate electrodes 2 above them. The lower surface, side surfaces, and upper surface of the gate electrode 2 extending in the Y direction on the source region 6 are covered with an insulating film 11.

A source electrode 1 is formed in a connection hole penetrating an insulating film 11 on a semiconductor substrate and on the insulating film 11. The source electrode 1 completely filling the connection hole and the source electrode 1 on the insulating film 11 are integrated with each other. In FIG. 10, in order to make it easier to understand the shape of the source electrode 1 in the connection hole extending in the Y direction, a part of the source electrode 1 directly above the source electrode 1 extending in the Y direction and a part of the source electrode 1 on the insulating film 11 are not shown. At the bottom of the connection hole, the source electrode 1 is connected to a potential fixing region 14.

The potential fixing region 14 is formed adjacent to the source region 6 in the Y direction. The lower surface of the potential fixing region 14 is in contact with the upper surface of the body layer 5. The potential fixing region 14 has a higher p-type impurity concentration than both the body layer 5 and the guard region 18. The guard region 18 is electrically connected to the source electrode 1 via the body layer 5 and the potential fixing region 14, so that a source voltage can be applied from the source electrode 1 to the guard region 18. In addition, the body layer 5 is electrically connected to the source electrode 1 via the potential fixing region 14, so that a source voltage can be applied from the source electrode 1 to the body layer 5.

In this embodiment, the side of the trench 9 is formed at an angle with respect to the upper surface of the semiconductor substrate, and an accumulation layer formation region 7 that continuously covers the side and bottom of each trench 9 is formed in the epitaxial layer below the source region 6. Here, the bottom of the trench 9 is located below the bottom surface of the current diffusion region 17 and reaches into the guard region 18. The bottom surface of the accumulation layer formation region 7 is located in the guard region 18, and the accumulation layer formation region 7 does not reach the drift layer 4 below the guard region 18. However, the accumulation layer formation region 7 formed on the side of the trench 9 is in contact with the current diffusion region 17 and is electrically connected to the drift layer 4 and the drain region 12 via the current diffusion region 17.

In the present embodiment, as in the first embodiment, a point CH1 can be defined as the contact point between the trench 9 and the bottom surface of the source region 6, and a boundary point between the accumulation layer formation region 7 and the region where the depletion layer extending from the body layer 5 contacts the side surface of the trench 9 when the accumulation layer formation region 7 is off, and a boundary point between the region where the depletion layer is separated from the side surface of the trench 9 can be defined as CH2 (see FIG. 3). In addition, a point on the boundary surface between the body layer 5 and the accumulation layer formation region 7 that is closest to point CH2 can be defined as point JC (see FIG. 3). Here, point JC is located above the bottom surface of the body layer 5, although it is not shown in FIG. 10. In other words, the body layer 5, which is a p-type semiconductor region, is formed below point JC. In addition, a guard region 18, which is a p-type semiconductor region, is also formed below point JC.

Figure 9 shows four unit cells lined up in the X direction, with each unit cell surrounded by a dashed line. As shown in Figure 9, each of the unit cells adjacent in the X direction has a structure that is inverted with the boundary between the unit cells as an axis. One unit cell is composed of a drain electrode 3, a drift layer 4, a body layer 5, a source region 6, a current diffusion region 17, a guard region 18, a JFET region 13, a trench 9, an insulating film 11, a gate electrode 2, a source electrode 1, and a potential fixing region 14 (see Figure 9).

Unit cells adjacent in the X direction share a source electrode 1 extending in the Y direction. Therefore, when each of the striped source electrodes 1 is formed with the smallest possible width, the cell pitch of the unit cells in the X direction can be reduced compared to when all unit cells are arranged without being inverted in the X direction.

As shown in FIG. 10, in the drift layer 4 below the current diffusion region 17, the JFET region 13, which is an n-type or n-type semiconductor region, is formed alongside the guard region 18 in the X direction. Specifically, directly below the current diffusion region 17, the JFET region 13 is adjacent to the guard region 18, and a part of the JFET region 13 is adjacent to the current diffusion region 17 in the X direction. The JFET region 13 extends in the Y direction directly below the source electrode 1. That is, here, the source electrode 1, the trench formation region in which multiple trenches 9 are lined up (see FIG. 9), and the JFET region 13 extend in parallel to each other in the Y direction. In FIG. 10, the lower end of the JFET region 13 is indicated by a dashed line.

The n-type impurity concentration of the JFET region 13 is equal to or higher than the n-type impurity concentration of the drift layer 4. The n-type impurity concentration of the JFET region 13 is lower than the n-type impurity concentrations of the current diffusion region 17 and the source region 6. The JFET region 13 is a region between adjacent guard regions 18 in the X direction. In other words, the JFET region 13 is a region where depletion layers extend from the opposing side surfaces of adjacent guard regions 18 when the SiC power MISFET is in the off state, and these depletion layers contact each other. The presence of multiple guard regions 18 lined up in the X direction and the JFET region 13 between them makes it possible to maintain and control the breakdown voltage.

When the SiC power MISFET of this embodiment is on, the current flows in the following order: drain electrode 3, drain region 12, drift layer 4, JFET region 13, current diffusion region 17, accumulation layer formation region 7, inversion layer of body layer 5, source region 6, and source electrode 1. In FIG. 10, this current path is indicated by a thick arrow.

In this embodiment, the trench formation region, the source electrode 1 (conductive connection portion), and the JFET region 13 all extend in the same Y direction and are formed in a stripe shape in a plan view. Here, the source electrode 1 and the JFET region 13 are arranged so as to overlap in a plan view and extend in the Y direction. That is, in the unit cell, a trench 9 is not formed between the source electrode 1 and the JFET region 13 in a plan view. For this reason, it is easier to miniaturize the unit cell compared to when the source electrode, the trench, and the JFET region are arranged in order in a plan view. In this way, the SiC power MISFET of this embodiment has a trench formation region, a source electrode 1 (conductive connection portion), and the JFET region 13 all extending in the same Y direction, and is provided with a plurality of trenches, current diffusion regions, and guard regions arranged in a stripe shape in the trench formation region. With such a SiC power MISFET, the same effect as that of the first embodiment can be obtained.

(Embodiment 3)
11 , the accumulation layer formation region 7 formed along the side surface of the trench 9 may reach the lower surface of the source region 6. In this case, the entire side surface of the trench 9 between the source region 6 and the drift layer 4 is covered with the accumulation layer formation region 7. Therefore, the trench 9 and the body layer 5, which is a p-type semiconductor region, are separated from each other with the accumulation layer formation region 7 therebetween. However, even if the accumulation layer formation region 7 is in contact with the source region 6 and the drift layer 4 in this manner, as described in the first embodiment, when the SiC power MISFET is turned off, the depletion layer extending from the body layer 5 reaches the surface of the trench 9 via the accumulation layer formation region 7, so that the breakdown voltage is maintained.

In the semiconductor device of the third embodiment, when the SiC power MISFET is in the on state, a channel (inversion layer) is formed in the semiconductor substrate adjacent to the trench 9, and a current flows through the channel. At this time, the accumulation layer formation region 7 is formed on the side of the trench 9 excluding the channel, and since the accumulation layer formation region 7 forms a carrier accumulation layer when on, a current flows more easily into the epitaxial layer when on compared to when the accumulation layer formation region 7 is not formed. Therefore, the on-resistance of the SiC power MISFET can be reduced. Also, since the accumulation layer formation region 7 is in contact with the source region 6, the on-resistance can be reduced compared to the first embodiment.

On the other hand, when the SiC power MISFET is in the off state, the depletion layer extending from the body layer 5 crosses the accumulation layer formation region 7 and reaches the side of the trench 9, so that the breakdown voltage of the SiC power MISFET can be maintained. In addition, since most of the trench 9 is formed in the body layer 5, the electric field concentration in the gate insulating film 8 in the trench 9 can be alleviated.

The invention made by the inventors has been specifically described above based on the embodiments, but it goes without saying that the invention is not limited to the above embodiments and can be modified in various ways without departing from the gist of the invention.

For example, the materials, conductivity types, and manufacturing conditions of each part are not limited to those described in the above-mentioned embodiment, and it goes without saying that many variations are possible for each. Here, for convenience of explanation, the conductivity types of the semiconductor substrate and semiconductor film have been fixed, but they are not limited to the conductivity types described in the above-mentioned embodiment.

In addition, in the first to third embodiments, an n-type SiC power MISFET has been described, but the effects of the first to third embodiments can also be obtained with a p-type SiC power MISFET in which the conductivity type of each semiconductor region is inverted. In addition, the third embodiment may be combined with a modified example of the first embodiment.

REFERENCE SIGNS LIST 1 source electrode 2 gate electrode 3 drain electrode 4 drift layer 5 body layer 6 source region 7 accumulation layer forming region 8 gate insulation 9 trench 11 insulation film 12 drain region 13 JFET region 14 potential fixing region 17 current diffusion region 18 guard region

Claims (8)

a silicon carbide semiconductor substrate of a first conductivity type;
a semiconductor layer of the first conductivity type formed on the silicon carbide semiconductor substrate and containing silicon carbide;
a first semiconductor region of the first conductivity type formed on an upper surface of the semiconductor layer;
a second semiconductor region of a second conductivity type different from the first conductivity type, the second semiconductor region being formed in the semiconductor layer from a lower end of the first semiconductor region to a midway depth of the semiconductor layer;
a third semiconductor region of the first conductivity type formed in the semiconductor layer below the second semiconductor region;
a trench formed from the upper surface of the semiconductor layer to a depth of the semiconductor layer below the lower end of the first semiconductor region;
a gate electrode formed on the inner side of the trench via an insulating film;
a fourth semiconductor region of the first conductivity type formed in the silicon carbide semiconductor substrate;
a fifth semiconductor region of the first conductivity type formed in the semiconductor layer below the lower end of the first semiconductor region and continuously contacting a side surface and a bottom surface of the trench;
having
the first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor;
a first point is a boundary between a first region, in which a depletion layer extending from the second semiconductor region contacts the side of the trench when the field effect transistor is off, and a second region below the first region, in which the depletion layer is spaced from the side of the trench, and a second point is a point on a boundary surface between the second semiconductor region and the fifth semiconductor region that is closest to the first point, wherein a portion of the second semiconductor region is located below the second point. 2. The silicon carbide semiconductor device according to claim 1,
The fifth semiconductor region is in contact with the third semiconductor region. 2. The silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device, wherein the trench reaches into the third semiconductor region. 2. The silicon carbide semiconductor device according to claim 1,
The trench is spaced from the third semiconductor region. 2. The silicon carbide semiconductor device according to claim 1,
a conductive connection portion formed on the semiconductor layer, extending in a first direction in a plan view, and electrically connected to the first semiconductor region;
a sixth semiconductor region of the first conductivity type formed in the third semiconductor region and extending in the first direction;
a seventh semiconductor region of the second conductivity type formed in the third semiconductor region, covering a corner portion that is an end portion of the bottom surface of the trench in a region adjacent to the sixth semiconductor region;
an eighth semiconductor region of the first conductivity type formed in the third semiconductor region on the seventh semiconductor region so as to surround the trench in a plan view and having an impurity concentration higher than that of the third semiconductor region;
and
In a plan view, the trenches are arranged in a plurality of rows in the first direction,
Each of the plurality of trenches extends in a second direction intersecting the first direction in a plan view. 2. The silicon carbide semiconductor device according to claim 1,
A silicon carbide semiconductor device, wherein an upper end of the fifth semiconductor region is in contact with the first semiconductor region. 2. The silicon carbide semiconductor device according to claim 1,
a fifth semiconductor region having a lower impurity concentration of the first conductivity type than a first semiconductor region having a lower impurity concentration of the first conductivity type; 2. The silicon carbide semiconductor device according to claim 1,
a top end of the fifth semiconductor region does not reach the first semiconductor region.

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