JP7675245B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device.

In a switching device, for example, if an overcurrent continues to flow during a short circuit, thermal destruction may occur. To prevent this problem, for example, Patent Document 1 discloses a semiconductor device including a semiconductor switching element, a semiconductor drive circuit, a sense element formed in the semiconductor switching element, and an overcurrent detection unit formed in the semiconductor drive circuit. The sense element is composed of a sense terminal through which a current proportional to the main current of the semiconductor switching element flows, and a sense resistor connected between the main terminal and the sense terminal of the semiconductor switching element and converts the sense current into a voltage. In addition, the overcurrent detection unit detects the sense current flowing through the above-mentioned sense element, and when the sense current exceeds a predetermined value, turns off the semiconductor switching element to protect the semiconductor switching element from overcurrent.

JP 2013-247804 A

The overcurrent protection method of Patent Document 1 is a method in which the semiconductor switching element is turned off based on the sense current, so it is susceptible to the effects of noise, and sometimes a sense current containing noise may be mistakenly detected as an overcurrent. To prevent malfunctions caused by such noise, there is a method in which the semiconductor switching element is not turned off immediately when the sense current exceeds a predetermined threshold, but rather after a certain waiting time (mask time) has elapsed.

However, there are still issues with this method of setting a waiting time. A certain waiting time is necessary to take into account the effects of noise (for example, about 500 nsec), but as devices continue to develop with lower on-resistance, there are cases in which the time it takes for an overcurrent to destroy a device becomes shorter than this waiting time, and the overcurrent protection system itself does not work.

Therefore, one embodiment of the present invention provides a semiconductor device that can reduce malfunctions caused by current noise and effectively protect switching elements from overcurrent.

One embodiment of the present invention provides a semiconductor device that includes a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element that is provided on the front surface side of the semiconductor substrate independently of the switching element and has temperature-dependent characteristics.

In addition, one embodiment of the present invention provides a single-function semiconductor device that includes a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element that is provided on the front side of the semiconductor substrate independently of the switching element and has temperature-dependent characteristics, and that uses the switching element.

According to the above configuration, if a temperature change occurs on the surface side of the semiconductor substrate, the characteristics (voltage value, resistance value, etc.) of the temperature sensing element change accordingly. Therefore, by monitoring the change in the characteristics of the temperature sensing element, it is possible to detect the temperature change of the semiconductor substrate. By utilizing this relationship, when an overcurrent flows through a switching element due to, for example, a short circuit, it is possible to detect the temperature rise of the semiconductor substrate due to the overcurrent, and based on the detection result, it is possible to determine whether or not an overcurrent is flowing through the switching element. Moreover, since the object to be monitored is not the sense current flowing through the switching element, even if noise is introduced into the sense current and superimposed on it, it will not be mistakenly detected as an overcurrent due to the superimposed current. Therefore, malfunctions due to current noise can be reduced.

One embodiment of the present invention includes a pair of first and second electrodes on the semiconductor substrate, and the electrical circuit between the first and second electrodes includes only the temperature sensing element as a circuit element.

In one embodiment of the present invention, the temperature sensing element includes a pn diode made of a polysilicon layer formed on the semiconductor substrate.

Polysilicon can be easily formed in a desired shape and position by using already established semiconductor manufacturing technology. Therefore, by forming a polysilicon layer (pn diode) near the surface, which is the heat generating part of the semiconductor substrate, it is possible to detect temperature changes in the semiconductor substrate with high accuracy. For example, by constantly applying a constant current to the pn diode and monitoring the forward voltage _VF of the pn diode, it is possible to detect temperature changes in the semiconductor substrate.

In one embodiment of the present invention, the switching element includes a planar gate type MISFET having a gate electrode formed along the surface of the semiconductor substrate, and the polysilicon layer is formed in the same layer as the gate electrode.

With this configuration, the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, which prevents an increase in the number of processes involved in forming the pn diode. In addition, since the pn diode can be placed on the semiconductor substrate via a gate insulating film that is thinner than a relatively thick film such as an interlayer insulating film, the position of the pn diode can be brought close to the current path on the surface side of the semiconductor substrate. This improves the accuracy of detecting temperature changes in the semiconductor substrate.

In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region that surrounds the p-type region in a plan view.

With this configuration, the p-type and n-type regions do not overlap in a planar view, so no separate wiring is required and contact can be easily made to both the p-type and n-type regions.

In one embodiment of the present invention, the switching element includes a trench-gate type MISFET having a gate trench formed in the semiconductor substrate and a gate electrode embedded in the gate trench, and the polysilicon layer is embedded in a second trench formed in the semiconductor substrate independently of the gate trench.

With this configuration, the second trench can be formed in the same process as the gate trench, and the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, which makes it possible to suppress an increase in the number of processes involved in forming the pn diode. In addition, because the pn diode is embedded in the surface portion of the semiconductor substrate, the position of the pn diode can be brought close to the current path on the surface side of the semiconductor substrate. This improves the accuracy of detecting temperature changes in the semiconductor substrate.

In one embodiment of the present invention, the gate trench and the second trench are formed to have the same width.

With this configuration, the etching rates for forming the gate trench and the second trench can be made approximately the same, so that the gate trench and the second trench can ultimately be formed to approximately the same depth. By making the depth of the second trench approximately the same as that of the gate trench in which the MISFET channel is formed, a temperature rise in the semiconductor substrate due to an overcurrent can be quickly detected.

In one embodiment of the present invention, the temperature sensing element includes a pn diode made of an impurity region formed on the surface of the semiconductor substrate.

The impurity region can be easily formed at a desired position by the already established semiconductor manufacturing technology. Therefore, by forming the impurity region (pn diode) in the immediate vicinity of the current path on the front side, which is the heat generating portion of the semiconductor substrate, the temperature change of the semiconductor substrate can be detected with high accuracy. For example, by constantly applying a constant current to the pn diode and monitoring the forward voltage _VF of the pn diode, the temperature change of the semiconductor substrate can be detected. In addition, since the pn diode made of the impurity region operates well even in a high temperature region (for example, 200° C. or higher), it is particularly effective for power devices such as SiC and GaN.

In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region that surrounds the p-type region in a plan view.

With this configuration, the p-type and n-type regions do not overlap in a planar view, so no separate wiring is required and contact can be easily made to both the p-type and n-type regions.

In one embodiment of the present invention, the temperature sensing element includes a series-connected unit in which multiple pn diodes are connected in series.

With this configuration, the amount of change in the forward voltage _VF due to temperature increases in proportion to the number of connected pn diodes, thereby improving the sensitivity of temperature change detection. For example, if the forward voltage _VF swing per pn diode is XmV/°C, then by connecting five such pn diodes in series to form a series-connected unit, the swing of the series-connected unit in total can be made 5XmV/°C.

In one embodiment of the present invention, the temperature sensing element includes a configuration in which at least a pair of the series connection units are connected in parallel in opposite directions.

With this configuration, there is no distinction between the anode and cathode polarities of the terminals of the pn diode assembly, which improves the freedom of wiring such as bonding wires when assembling modules, etc.

In one embodiment of the present invention, the temperature sensing element includes an anti-series connection unit in which at least a pair of the pn diodes are connected in series in the opposite directions.

With this configuration, a reverse bias is applied to at least one of the pair of pn diodes, increasing the total resistance of the reverse series connection unit. This makes it possible to reduce the current required to monitor temperature changes, thereby achieving power savings.

In one embodiment of the present invention, the temperature sensing element includes a configuration in which a plurality of the anti-series connection units are connected in series.

This configuration allows for even greater power savings.

In one embodiment of the present invention, the temperature sensing element includes at least a pair of the pn diodes connected in parallel in opposite directions.

With this configuration, there is no distinction between the anode and cathode polarities of the terminals of a pair of pn diodes, which improves the freedom of wiring such as bonding wires when assembling modules, etc.

In one embodiment of the present invention, the temperature sensing element is disposed on the periphery of the semiconductor substrate.

This configuration allows a relatively large area to be secured in areas other than the area where the temperature sensing element is installed, allowing the area of the terminals for the switching element to be large. Therefore, even if the chip size is small, wiring members such as bonding plates and relatively thick bonding wires can be connected to the terminals.

In one embodiment of the present invention, the semiconductor substrate includes a SiC semiconductor substrate.

This configuration provides excellent protection for low on-resistance SiC switching elements from overcurrent.

One embodiment of the present invention provides a semiconductor module including the semiconductor device and a second semiconductor device having a circuit electrically connected to the switching element and the temperature sensing element, the circuit cutting off the current path of the switching element when it is determined that an overcurrent is flowing through the switching element based on a change in the characteristics of the temperature sensing element.

With this configuration, since it is equipped with the above-mentioned semiconductor device, it is possible to realize a semiconductor module that can reduce malfunctions caused by current noise and effectively protect switching elements from overcurrent.

FIG. 1 is a schematic external view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a semiconductor module including the semiconductor device of FIG. FIG. 3 is a diagram showing a more specific planar structure of the semiconductor device of FIG. FIG. 4A is a schematic plan view showing the structure of a cell region of the semiconductor device of FIG. FIG. 4B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 4A. FIG. 5A is a schematic plan view showing the structure of the temperature sensing region of the semiconductor device of FIG. FIG. 5B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 5A. FIG. 5C shows a variation of the structure of FIG. 5B. FIG. 6 is a flow diagram of the manufacturing process of the semiconductor device. FIG. 7A is a diagram showing a part of the manufacturing process of the semiconductor device. FIG. 7B is a diagram showing the next step of FIG. 7A. FIG. 7C is a diagram showing the next step of FIG. 7B. FIG. 7D is a diagram showing the next step of FIG. 7C. FIG. 7E is a diagram showing the next step of FIG. 7D. FIG. 7F is a diagram showing the next step of FIG. 7E. FIG. 7G is a diagram showing the next step of FIG. 7F. FIG. 7H is a diagram showing the next step of FIG. 7G. FIG. 7I is a diagram showing the next step of FIG. 7H. FIG. 7J is a diagram showing the next step of FIG. 7I. FIG. 7K is a diagram showing the next step of FIG. 7J. FIG. 7L is a diagram showing the next step of FIG. 7K. FIG. 8 is a graph illustrating how the forward voltage of the temperature sensing diode changes with temperature. FIG. 9A is a schematic plan view showing the structure of the temperature sensing region of the semiconductor device of FIG. FIG. 9B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 9A. FIG. 10 is a diagram showing an example of a connection form of the temperature sensing diode. FIG. 11 is a diagram showing an example of a connection form of the temperature sensing diode. FIG. 12 is a diagram showing an example of a connection form of the temperature sensing diode. FIG. 13 is a diagram showing an example of a connection form of the temperature sensing diode. FIG. 14 is a diagram showing an example of a connection form of the temperature sensing diode. 4 is a schematic plan view showing a structure of a cell region of the semiconductor device of FIG. 3. FIG. 15B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 15A. 16A is a schematic plan view showing the structure of the temperature sensing region of the semiconductor device of FIG. 3. FIG. FIG. 16B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 16A. FIG. 16C is a cross-sectional view (cross-sectional view taken along line CC) of FIG. 16A.

The following describes in detail an embodiment of the present invention with reference to the attached drawings.

Figure 1 is a schematic external view of a semiconductor device 1 according to one embodiment of the present invention.

The semiconductor device 1 is a discrete semiconductor device and has a single function provided by a switching element SW. The switching element SW may be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), a bipolar transistor, a thyristor, or the like. In this embodiment, the switching element SW is a MISFET. A source pad 2 and a gate pad 3 are formed on the surface of the semiconductor device 1 formed as a square chip in a plan view. The source pad 2 covers almost the entire surface, and the gate pad 3 is disposed in an inner region of the source pad 2. Although not shown, a drain electrode is formed on the back surface of the semiconductor device 1.

In addition to the switching element SW described above, the semiconductor device 1 is provided with a temperature sensing element TS. The temperature sensing element TS is disposed on the front side of the semiconductor device 1. The temperature sensing element TS is independent of the switching element SW and does not directly contribute to the switching operation of the switching element SW.

Next, an overview of the overcurrent protection method in the semiconductor module 4 including the semiconductor device 1 will be described. Figure 2 is a circuit diagram of the semiconductor module 4 including the semiconductor device 1 of Figure 1.

The semiconductor module 4 includes the semiconductor device 1 and a gate driver G/D as an example of a second semiconductor device of the present invention having a short circuit protection circuit 5. The semiconductor module 4 may include semiconductor chips (ICs, discrete chips, etc.) other than those shown in FIG. 2.

The short-circuit protection circuit 5 is electrically connected independently to the gate G of the switching element SW and the temperature sensing element TS. The short-circuit protection circuit 5 constantly monitors the characteristics of the temperature sensing element TS. For example, if a short circuit occurs in the switching element SW and an overcurrent flows, the characteristics of the temperature sensing element TS change due to the associated heat generation. The short-circuit protection circuit 5 detects this change in characteristics as the occurrence of a short circuit in the switching element SW and turns off the gate G of the switching element SW. This blocks the drain current Id flowing between the source and drain (S-D) of the switching element SW, protecting the switching element SW.

Figure 3 is a diagram showing the planar structure of the semiconductor device 1 in Figure 1 in more detail.

The semiconductor device 1 includes a semiconductor substrate 6 that defines its external shape, and has a structure in which a switching element SW and a temperature sensing element TS are formed on the semiconductor substrate 6.

The semiconductor substrate 6 has a rectangular shape in plan view, and almost the entire surface is covered by the source pad 2, which is roughly rectangular in plan view. A cell region 7 constituting the switching element SW is formed in a large part below the source pad 2. The gate pad 3 is disposed on at least one side of the outer periphery of the semiconductor substrate 6. The gate finger 8 is connected to the gate pad 3. The gate finger 8 extends to the center of the semiconductor substrate 6 to divide the cell region 7 into one side and the other side, and also extends to the periphery of the semiconductor substrate 6 to surround the cell region 7.

A temperature sensing region 9 constituting the temperature sensing element TS is formed in the inner region of the cell region 7. The temperature sensing region 9 is surrounded by the cell region 7. The position of the temperature sensing region 9 may be, for example, the peripheral portion of the semiconductor substrate 6. If the temperature sensing region 9 is disposed on the peripheral portion of the semiconductor substrate 6, a relatively large area can be secured on the semiconductor substrate 6 other than the temperature sensing region 9, so that the area of the source pad 2 can be made large. Therefore, even if the chip size is reduced, wiring members such as a bonding plate or a relatively thick bonding wire can be connected to the source pad 2.

In plan view, the first electrode 10 and the second electrode 11 are provided so as to sandwich the temperature sensing region 9. That is, the pair of the first electrode 10 and the second electrode 11 are arranged on the semiconductor substrate 6 with a gap between them, and the temperature sensing region 9 is formed in the region between the first electrode 10 and the second electrode 11. The first electrode 10 and the second electrode 11 are arranged, for example, side by side along one side of the semiconductor substrate 6 on which the gate pad 3 is arranged. This makes it easier to draw wiring members such as bonding wires from each of the gate pad 3, the first electrode 10, and the second electrode 11 in the same direction (the left direction of the paper in FIG. 3). In addition, the first electrode 10 and the second electrode 11, as well as the source pad 2, the gate pad 3, and the gate finger 8 are made of an electrode film of the same material, and can be formed simultaneously by, for example, forming the electrode film on the semiconductor substrate 6 and then patterning the electrode film.
<Cell structure>
Fig. 4A is a schematic plan view showing the structure (planar gate structure) of the cell region 7 of the semiconductor device 1 of Fig. 3. Fig. 4B is a cross-sectional view (cross-sectional view taken along line BB) of Fig. 4A.

The semiconductor substrate 6 may be, for example, a SiC substrate, or may be, for example, a GaN substrate, a Si substrate, or the like. The semiconductor substrate 6 may be an epitaxial substrate including a base substrate and an epitaxial layer crystal-grown thereon. In this embodiment, the semiconductor substrate 6 is an n-type SiC epitaxial substrate. The n-type SiC epitaxial substrate may include an n ⁺ type base substrate and an n ^- type epitaxial layer on the n ⁺ type base substrate. The impurity concentration of the ^{n +} type base substrate may be, for example, 1.0×10 ¹⁸ cm ^-3 to 1.0×10 ²⁰ cm ^-3 , and the impurity concentration of the n ^- type epitaxial layer may be, for example, 5.0×10 ¹⁴ cm ^-3 to 5.0×10 ¹⁶ cm ^-3 . Examples of n-type impurities include N (nitrogen), As (arsenic), and P (phosphorus).

As shown in Figures 4A and 4B, a plurality of p-type body regions 12 are formed in the surface portion of the semiconductor substrate 6 in the cell region 7. The plurality of p-type body regions 12 may be formed in a matrix shape (row and column shape) in plan view as shown in Figure 4A, or may be formed in a stripe shape or honeycomb shape. Lines are set between adjacent p-type body regions 12 to partition each unit cell 13 of the switching element SW. The p-type impurity concentration of the p-type body region 12 may be, for example, 1 x ^{1015cm -3} to 1 x ^{1020cm -3} . Examples of p-type impurities include B (boron) and Al (aluminum).

An n ⁺ type source region 14 is formed at a distance from the periphery of the p type body region 12 in the surface portion of the inner region of the p type body region 12. The n type impurity concentration of the n ⁺ type source region 14 is higher than the impurity concentration of the n type semiconductor substrate 6 and may be, for example, 1×10 ¹⁸ cm ^-3 to 5×10 ²¹ cm ^-3 .

A p ⁺ type body contact region 15 is formed in an inner region of the n ⁺ type source region 14. The p ⁺ type body contact region 15 is formed to penetrate the n ⁺ type source region 14 in the depth direction. The p-type impurity concentration of the p ⁺ type body contact region 15 is higher than that of the p-type body region 12, and may be, for example, 1×10 ¹⁸ cm ^-3 to 5×10 ²¹ cm ^-3 .

A gate insulating film 16 is formed on the surface of the semiconductor substrate 6. The gate insulating film 16 may be made of, for example, silicon oxide (SiO ₂ ). The thickness of the gate insulating film 16 may be, for example, 300 Å to 600 Å.

A gate electrode 17 is formed on the gate insulating film 16. The gate electrode 17 faces the peripheral portion of the p-type body region 12 (the portion surrounding the n ⁺ -type source region 14 in a plan view) with the gate insulating film 16 in between. The gate electrode 17 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may be made of p-type polysilicon. The thickness of the gate electrode 17 may be, for example, 6000 Å to 12000 Å.

An interlayer insulating film 18 is formed on the entire surface of the semiconductor substrate 6 to cover the gate electrode 17. The interlayer insulating film 18 may be made of, for example, silicon oxide (SiO ₂ ), or may have a structure in which a plurality of films made of silicon oxide are stacked as described later (see FIGS. 7I to 7L). The thickness of the interlayer insulating film 18 (the total thickness when it is made of a plurality of films) may be, for example, 1000 Å to 2000 Å. Although not shown, wiring electrically connecting the source pad 2 to the n ⁺ type source region 14 and the p ⁺ type body contact region 15, and wiring electrically connecting the gate pad 3 to the gate electrode 17 are formed to penetrate the interlayer insulating film 18.
<Temperature sensing element structure>
Fig. 5A is a schematic plan view showing the structure of the temperature sensing region 9 of the semiconductor device 1 of Fig. 3. Fig. 5B is a cross-sectional view (cross-sectional view taken along line B-B) of Fig. 5A. Fig. 5C is a diagram showing a modified example of the structure of Fig. 5B.

As shown in Figures 5A and 5B, a p-type region 19 is formed in the surface portion of the semiconductor substrate 6 in the temperature sensing region 9. The p-type region 19 may be an impurity region of the same conductivity type as the p-type body region 12, and may also have the same p-type impurity concentration and depth as the p-type body region 12.

On the surface of the semiconductor substrate 6, the gate insulating film 16 of the cell region 7 is formed, extending to the temperature sensing region 9. In the temperature sensing region 9, a temperature sensing diode 20 (pn diode) as an example of a temperature sensing element TS is formed on the gate insulating film 16. The temperature sensing diode 20 faces the semiconductor substrate 6 across the gate insulating film 16. For example, as shown in FIG. 5B, the entire temperature sensing diode 20 may face a single impurity region (in this embodiment, the p-type region 19) of the semiconductor substrate 6.

The temperature sensing diode 20 is made of, for example, a single polysilicon layer 21. The temperature sensing diode 20 made of the polysilicon layer 21 may be formed in the same layer as the gate electrode 17 by being formed in the same process as the gate electrode 17. In other words, the polysilicon layer 21 may be formed to a thickness of 6000 Å to 12000 Å, like the gate electrode 17. Of course, the polysilicon layer 21 may be formed in a process separate from the gate electrode 17, and may have a thickness different from that of the gate electrode 17.

The temperature sensing diode 20 includes a p-type region 22 and an n ⁺ -type region 23 surrounding the p-type region 22. If the p-type region 22 is surrounded by the n ⁺ -type region 23, the p-type region 22 and the n ⁺ -type region 23 do not overlap in a planar view, so that no separate wiring or the like is required and contact can be easily made to both the p-type region 22 and the n ⁺ -type region 23.

The p-type region 22 and the n ⁺ -type region 23 may be formed so as to reach the back surface of the polysilicon layer 21 as shown in FIG. 5B, or may be selectively formed on the surface of the polysilicon layer 21, although not shown. The p-type region 22 does not have to be surrounded by the n ⁺ -type region 23, and for example, the p-type region 22 and the n ⁺ -type region 23 may be formed adjacent to each other, thereby having a portion of the periphery that is not shared. The p-type impurity concentration of the p-type region 22 may be, for example, 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ (the same as the p-type body region 12). The n-type impurity concentration of the n ⁺ -type region 23 may be, for example, 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ (the same as the n ⁺ -type source region 14).

The temperature sensing diode 20 may further include a p ⁺ type contact region 24 and a p type peripheral region 25. The p ⁺ type contact region 24 may be formed in an inner region of the p type region 22 with a gap between it and the periphery of the p type region 22, and the p type peripheral region 25 may be formed to surround the n ⁺ type region 23. The p ⁺ type contact region 24 and the p type peripheral region 25 may be formed so as to reach the back surface of the polysilicon layer 21 as shown in FIG. 5B, or may be selectively formed in the surface portion of the polysilicon layer 21, although not shown. The p type impurity concentration of the p ⁺ type contact region 24 may be, for example, 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ (the same as the p ⁺ type body contact region 15). The p-type impurity concentration of p-type peripheral region 25 may be, for example, 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ (the same as p-type body region 12 ).

As shown in FIG. 5C , the temperature sensing diode 20 may have a configuration including a p-type base layer 26 made of p-type polysilicon (p-type doped polysilicon) of the opposite conductivity type to the gate electrode 17, and an n ⁺ type region 23 and a p ⁺ type contact region 24 selectively formed on the surface portion of the p-type base layer 26.

The temperature sensing diode 20 is covered with an interlayer insulating film 18 on the semiconductor substrate 6. The first electrode 10 is connected to the p ⁺ type contact region 24 as an anode electrode through a contact hole 27 in the interlayer insulating film 18. The second electrode 11 is connected to the n ⁺ type region 23 as a cathode electrode through a contact hole 28 in the interlayer insulating film 18. The first electrode 10 and the second electrode 11 connected to both ends of the temperature sensing diode 20 are formed separately from the source pad 2 and the gate pad 3 for the switching element SW, as described above. Therefore, the temperature sensing diode 20 is electrically independent from the switching element SW.

Polysilicon can be easily formed in a desired shape and position by using already established semiconductor manufacturing technology. Therefore, the temperature sensing diode 20 can be formed near the switching element SW and near the surface of the semiconductor substrate 6, which is a heat generating portion, to detect temperature changes in the semiconductor substrate 6 with high accuracy. For example, a constant current is applied to the temperature sensing diode 20 and the forward voltage _VF of the temperature sensing diode 20 is monitored, thereby detecting temperature changes in the semiconductor substrate 6. For example, a constant current of 1 μA may be applied and the forward voltage _VF may be monitored. The current may be a constant current in the range of 1 μA to 100 μA.

The second electrode 11 is integral with the interlayer insulating film 18 and includes a ring-shaped contact portion 30 having an open portion 29 in one portion, and a linear extraction portion 31 extending from the contact portion 30. The contact portion 30 surrounds the p-type region 22 in a plan view. The contact hole 28 is formed in a ring shape with a portion open along the contact portion 30.

The first electrode 10 integrally includes, on the interlayer insulating film 18, a contact portion 32 surrounded by the contact portion 30 of the second electrode 11, and a linear extraction portion 33 extending from the contact portion 32 through the opening 29. The contact portion 32 is disposed on the p ⁺ type contact region 24. The contact hole 27 is formed so as to overlap below the contact portion 32.

Next, a method for manufacturing the semiconductor device 1 will be described. Figure 6 is a flow diagram of the manufacturing process of the semiconductor device 1. Figures 7A to 7L are diagrams showing some of the manufacturing process of the semiconductor device 1 in the order of steps. Note that Figures 7A to 7L do not correspond to each of the steps in Figure 6. Below, the manufacturing process of the semiconductor device 1 will be described according to the flow in Figure 6, and Figures 7A to 7L will be referred to as necessary.

To manufacture the semiconductor device 1, for example, an ^n- type epitaxial layer is formed on an n ⁺ type base substrate by epitaxial growth (step S1), thereby forming a semiconductor substrate 6.

Next, the p-type body region 12 and the p-type region 19 are formed by selectively injecting p-type impurities into the semiconductor substrate 6 (step S2). Similarly, the n ⁺ type source region 14 and the p+ type body contact region 15 are formed by selectively injecting n-type impurities and p ^- type impurities into the semiconductor substrate 6 (steps S3 and S4).

7A, the semiconductor substrate 6 is thermally oxidized to form a gate insulating film 16 on the surface of the semiconductor substrate 6 (step S5). Next, the gate electrode 17 and the polysilicon layer 21 serving as the base of the temperature sensing diode 20 are formed by, for example, CVD (step S6). Next, a hard mask 34 (e.g., with a thickness of about 9000 Å) made of silicon oxide (SiO ₂ ) is formed by, for example, CVD (step S7).

7B, a resist film 35 for lithography of the hard mask 34 is formed (step S8). The resist film 35 is formed so as to cover the hard mask 34 on a region 36 where the p-type region 22 and the n ⁺ -type region 23 are to be formed.

Next, as shown in FIG. 7C, the hard mask 34 is selectively etched through the resist film 35 (step S9). The etching may be performed by wet etching using hydrofluoric acid, for example. After etching, the resist film 35 is removed.

Next, as shown in FIG. 7D, n-type impurities (e.g., phosphorus) are deposited in region 37 (region other than region 36 of polysilicon layer 21) exposed from hard mask 34 of polysilicon layer 21, and are diffused at about 1000° C., for example, to introduce n-type impurities into region 37 (step S10). As a result, region 37 including gate electrode 17 of polysilicon layer 21 becomes n-type polysilicon, while region 36 remains undoped.

Next, as shown in FIG. 7E, the hard mask 34 remaining on the polysilicon layer 21 is removed by etching (step S11). The etching may be performed by wet etching using hydrofluoric acid, for example.

Next, as shown in FIG. 7F, while the gate electrode 17 portion of the polysilicon layer 21 is selectively covered with a mask (not shown), boron, which is a p-type impurity, is implanted into the entire surface of the polysilicon layer 21 (step S12). As a result, the region from the surface of the polysilicon layer 21 to the middle of the thickness direction becomes a p-type region 38.

Next, as shown in Fig. 7G, a mask (not shown) is formed by lithography to selectively expose the region of the polysilicon layer 21 where the n ⁺ type region 23 is to be formed, and then n-type impurities are implanted into the region 36 through the mask (step S13). This forms the n ⁺ type region 23. At this time, the n ⁺ type region 23 may be formed only halfway through the thickness direction from the surface of the polysilicon layer 21 as shown in Fig. 7G.

Next, as shown in Fig. 7H, a mask (not shown) is formed by lithography to selectively expose the region of the polysilicon layer 21 where the p ⁺ type contact region 24 is to be formed, and then p-type impurities are implanted into the region 36 through the mask (step S14). This forms the p ⁺ type contact region 24. At this time, the p ⁺ type contact region 24 may be formed only halfway through the thickness direction from the surface of the polysilicon layer 21, as shown in Fig. 7H.

Next, as shown in FIG. 7I, a hard mask 39 is formed to selectively cover the regions of the polysilicon layer 21 where the temperature sensing diode 20 and the gate electrode 17 are to be formed, and then the polysilicon layer 21 is selectively etched through the hard mask 39. This forms the temperature sensing diode 20 and the gate electrode 17 (not shown in FIG. 7I).

Next, as shown in FIG. 7J, multiple insulating films are formed by, for example, CVD while leaving the hard mask 39. For example, as shown in FIG. 7J, the multiple insulating films may include a lower silicon oxide film 40 (for example, a non-doped silicate glass (NSG) film) and an upper silicon oxide film 41 (for example, a phosphorus silicate glass (PSG) film, a boron phosphorus silicate glass (BPSG) film, etc.). This forms an interlayer insulating film 18 consisting of the hard mask 39, the silicon oxide film 40, and the silicon oxide film 41 (step S15).

Next, as shown in FIG. 7K, contact holes 27 and 28 are formed by selectively etching the interlayer insulating film 18 (step S16).

7L, the semiconductor substrate 6 is subjected to a heat treatment (reflow) (step S17). The heat treatment is performed, for example, in a nitrogen (N ₂ ) atmosphere at 900° C. to 1200° C. for 5 to 15 minutes. As a result, the p-type region 38, the n ⁺ -type region 23, and the p ⁺ -type contact region 24 that remained in the surface portion of the polysilicon layer 21 diffuse until they reach the rear surface of the polysilicon layer 21.

After that, various wirings, a source pad 2, a gate pad 3, a first electrode 10, a second electrode 11, a passivation film, etc. are formed to obtain a semiconductor device 1.

Next, we will explain in more detail the operation of the semiconductor device 1 in the semiconductor module 4 and the overcurrent protection method.

The electrical circuit configuration of the semiconductor module 4 is as shown in FIG. 2. A voltage is applied to the semiconductor device 1 connected in this manner by the gate driver G/D. Specifically, referring mainly to FIG. 3 and FIG. 4B, a bias voltage is applied between the source pad 2 and the drain electrode (not shown) such that the drain electrode side is positive. As a result, a reverse voltage is applied to the pn junction at the interface between the n-type semiconductor substrate 6 and the p-type body region 12, and as a result, a state is cut off between the n ⁺ type source region 14 and the semiconductor substrate 6, that is, between the source and the drain. In this state, when a predetermined voltage is applied between the source pad 2 and the gate pad 3 such that the gate pad 3 side is positive, a bias is applied to the gate electrode 17 with respect to the p-type body region 12. As a result, electrons are induced in the periphery of the p-type body region 12, and an inversion channel is formed. Through this inversion channel, the n ⁺ type source region 14 and the semiconductor substrate 6 are electrically connected. Thus, the source and the drain are electrically connected, and a drain current Id flows.

5A and 5B, a constant current is applied to the temperature sensing diode 20 by the gate driver G/D. Also, the short circuit protection circuit 5 of the gate driver G/D constantly monitors the forward voltage _VF of the temperature sensing diode 20. Normally, the I-V characteristic of the temperature sensing diode 20 is, for example, as shown by the solid line in FIG.

4A and 4B, when a short circuit occurs in the switching element SW (MISFET) and an overcurrent flows, a temperature rise occurs on the surface side of the semiconductor substrate 6. This temperature rise is also transmitted to the temperature sense region 9 (see FIG. 5B) formed on the semiconductor substrate 6 common to the cell region 7, and in the temperature sense region 9, the forward voltage _VF of the temperature sense diode 20 decreases with the temperature rise. For example, as shown by the curve shown by the dashed line in FIG. 8, the rise voltage of the temperature sense diode 20 shifts to the low voltage side. The short circuit protection circuit 5 detects this decrease in the forward voltage _VF as the occurrence of a short circuit in the switching element SW, and turns off the voltage applied to the gate pad 3. This blocks the drain current Id flowing between the source and drain (S-D) of the switching element SW, and the switching element SW is protected.

In this way, when an overcurrent flows through the switching element SW due to, for example, a short circuit, the temperature rise of the semiconductor substrate 6 caused by the overcurrent is detected based on the drop in the forward voltage _VF of the temperature sensing diode 20, and it is possible to determine whether or not an overcurrent flows through the switching element SW according to the detection result. Moreover, since the object to be monitored is not the sense current flowing through the switching element SW, even if noise is superimposed on the sense current, the sense current is not erroneously detected as an overcurrent due to the superimposed current. Therefore, it is possible to reduce malfunctions caused by current noise. Also, unlike conventional overcurrent protection methods, a certain waiting time (mask time) is not required, or if it is required, it is only required for a short time, so that it is very effective for low on-resistance devices (SiC, GaN, etc.) in which the time it takes for the device to be destroyed by an overcurrent is relatively short.

In addition, in this embodiment, as shown in FIG. 5B, the temperature sensing diode 20 is made of the polysilicon layer 21 in the same layer as the gate electrode 17, so that an increase in the number of steps involved in forming the temperature sensing diode 20 can be suppressed. In addition, the temperature sensing diode 20 can be disposed on the semiconductor substrate 6 via a thin gate insulating film 16 compared to a relatively thick film such as the interlayer insulating film 18. Therefore, the position of the temperature sensing diode 20 can be brought close to the current path on the surface side of the semiconductor substrate 6. This improves the accuracy of detecting temperature changes in the semiconductor substrate 6.

Figure 9A is a schematic plan view showing the structure of the temperature sensing region 9 of the semiconductor device 1 of Figure 3. Figure 9B is a cross-sectional view (cross-sectional view along line B-B) of Figure 9A. Figures 9A and 9B show another example of the structure of the temperature sensing region 9. In Figures 9A and 9B, the same components as those shown in Figures 5A and 5B described above are given the same reference numerals, and descriptions thereof will be omitted.

In Figures 5A and 5B, the temperature sensing diode 20 is made of a polysilicon layer 21 on the semiconductor substrate 6, but the temperature sensing diode 42 (pn diode) in Figures 9A and 9B is made of an impurity region selectively formed on the surface of the semiconductor substrate 6. Specifically, the temperature sensing diode 42 includes a p-type region 43 and an n ⁺ type region 44 surrounding the p-type region 43 in a planar view. If the p-type region 43 is surrounded by the n ⁺ type region 44, the p-type region 43 and the n ⁺ type region 44 do not overlap in a planar view, so that no separate wiring is required and contact can be easily made with both the p-type region 43 and the n ⁺ type region 44.

The p-type region 43 is made of a part of the p-type region 19. On the other hand, the n ⁺ -type region 44 is formed in a floating state on the surface portion of the p-type region 19. This n ⁺ -type region 44 may be formed in the same process as the n ⁺ -type source region 14 (see FIG. 4B). That is, the n ⁺ -type region 44 may have an n-type impurity concentration of 1×10 ¹⁸ cm ^-3 to 5×10 ²¹ cm ^-3 like the n ⁺ -type source region 14, and may be formed to the same depth.

The temperature sensing diode 42 may further include a p ⁺ type contact region 45 and a p-type peripheral region 46. The p ⁺ type contact region 45 is formed in an inner region of the p-type region 43 with a gap between it and the periphery of the p-type region 43, and the p-type peripheral region 46 may be formed to surround the n ⁺ type region 44. The p-type peripheral region 46 is made of a part of the p-type region 19 and is electrically connected to the p-type region 43 via the p-type region 19 below the n ⁺ type region 44. On the other hand, the p ⁺ type contact region 45 is formed in a floating state on the surface portion of the p-type region 19. This p ⁺ type contact region 45 may be formed in the same process as the p ⁺ type body contact region 15 (see FIG. 4B). That is, the p ⁺ type contact region 45 may have a p-type impurity concentration of 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ like the p ⁺ type body contact region 15, and may be formed to the same depth.

The first electrode 10 is connected to the p ⁺ type contact region 45 as an anode electrode through a contact hole 27 in the interlayer insulating film 18. The second electrode 11 is connected to the n ⁺ type region 44 as a cathode electrode through a contact hole 28 in the interlayer insulating film 18.

As described above, the temperature sensing diode 42 can perform the same function as the temperature sensing diode 20 described above. Furthermore, since the temperature sensing diode 42 is formed in the semiconductor substrate 6 itself, the pn junction can be brought closer to the current path on the front side, which is the heat generating part of the semiconductor substrate 6, than in the case of the temperature sensing diode 20. This allows the temperature change of the semiconductor substrate 6 to be detected with high accuracy. Furthermore, a pn diode made of an impurity region operates well even in high temperature regions (e.g., 200°C or higher), and is therefore particularly effective for power devices such as SiC and GaN.

Next, variations in the connection configuration when multiple temperature sensing diodes 20, 42 are provided will be described. Figures 10 to 14 are diagrams each showing an example of the connection configuration of the temperature sensing diodes 20, 42. Note that in Figures 10 to 14, reference symbols are given only to the components shown in Figures 5A and 9A above that are necessary for the explanation.

First, as shown in FIG. 10, the multiple temperature sensing diodes 20, 42 may include a series-connected unit 47 configured by connecting the first electrode 10 (anode) of one side and the second electrode 11 (cathode) of the other side in series. The series-connected unit 47 may be configured with two temperature sensing diodes 20, 42 as shown in FIG. 10, or may be configured with three or more temperature sensing diodes 20, 42, although not shown.

10, it is possible to improve the sensitivity of detecting temperature changes because the amount of change (shift) in the forward voltage _VF shown in FIG. 8 increases in proportion to the number of connected temperature sense diodes 20, 42. For example, when the amplitude of the forward voltage _VF per one of the temperature sense diodes 20, 42 is XmV/°C, if five temperature sense diodes 20, 42 are connected in series to form a series-connected unit 47, it is possible to make the amplitude of the series-connected unit 47 in total 5XmV/°C.

Next, as shown in FIG. 11, at least a pair of series-connected units 47 may be connected in parallel in the opposite directions. That is, the terminal first electrode 10 of one series-connected unit 47 may be connected to the terminal second electrode 11 of the other series-connected unit 47 to form a terminal 48, and the terminal second electrode 11 of one series-connected unit 47 may be connected to the terminal first electrode 10 of the other series-connected unit 47 to form a terminal 49.

According to the configuration of FIG. 11, the terminals 48, 49 of the assembly of temperature sensing diodes 20, 42, which are made up of multiple series-connected units 47, do not have to be differentiated between anode and cathode polarities, which improves the degree of freedom of wiring such as bonding wires when assembling a semiconductor module 4 (see FIG. 2) or the like. In other words, even if a reverse bias is applied to one series-connected unit 47, a forward bias is applied to the other series-connected unit 47 at that time, so that at least one of them can function as a temperature sensing diode.

Next, as shown in FIG. 12, the multiple temperature sensing diodes 20, 42 may include an anti-series connection unit 50 configured by connecting one and the other first electrodes 10 (anodes) in series, or one and the other second electrodes 11 (cathodes) in series. The anti-series connection unit 50 may be configured with two temperature sensing diodes 20, 42 as shown in FIG. 12, or may be configured with three or more temperature sensing diodes 20, 42, although not shown. Furthermore, multiple anti-series connection units 50 may be connected in anti-series as shown in FIG. 13.

According to the configurations of Figures 12 and 13, a reverse bias is applied to at least one of the temperature sensing diodes 20, 42 that make up the reverse series connection unit 50, so the total resistance of the reverse series connection unit 50 increases. Therefore, the current required to monitor the temperature change of the temperature sensing diodes 20, 42 can be kept small, and power saving can be achieved.

Next, as shown in FIG. 14, the temperature sensing diodes 20, 42 may include a configuration in which at least one pair is connected in parallel in the opposite directions. In other words, the first electrode 10 of one temperature sensing diode 20, 42 may be connected to the second electrode 11 of the other temperature sensing diode 20, 42 to form a terminal 51, and the second electrode 11 of one temperature sensing diode 20, 42 may be connected to the first electrode 10 of the other temperature sensing diode 20, 42 to form a terminal 52.

According to the configuration of FIG. 14, as in the configuration of FIG. 11, there is no distinction between the anode and cathode polarities of the terminals 51, 52 of the assembly of the temperature sense diodes 20, 42, so that the degree of freedom of wiring such as bonding wires can be improved when assembling a semiconductor module 4 (see FIG. 2) or the like. In other words, even if a reverse bias is applied to one of the temperature sense diodes 20, 42, a forward bias is applied to the other temperature sense diode 20, 42 at that time, so that at least one of them can function as a temperature sense diode.

As described above, the connection configuration of the multiple temperature sensing diodes 20, 42 is not limited to the configurations in Figures 10 to 14, and any suitable configuration can be adopted. In addition, the concepts of the connection configurations shown above (series, series + anti-parallel, anti-series, multiple anti-series, anti-parallel, etc.) can also be applied to the temperature sensing diode 66 in Figures 16A to 16C described below.

Figure 15A is a schematic plan view showing the structure (trench gate structure) of the cell region 7 of the semiconductor device 1 of Figure 3. Figure 15B is a cross-sectional view (cross-sectional view taken along line B-B) of Figure 15A. Figures 15A and 15B show another example of the structure of the cell region 7. In Figures 15A and 15B, the same components as those shown in Figures 4A and 4B above are given the same reference numerals, and descriptions thereof will be omitted.

As shown in Figures 15A and 15B, gate trenches 53 are formed in the semiconductor substrate 6 in the cell region 7. The gate trenches 53 partition each unit cell 54 of the switching element SW. The gate trenches 53 may be formed, for example, in a lattice shape in a plan view as shown in Figure 15A, or may be formed in a stripe shape or honeycomb shape.

A p-type body region 55 is formed in a surface portion of each unit cell 54, and an n ⁺ -type source region 56 is formed in a surface portion of the p-type body region 55. The p-type impurity concentration of the p-type body region 55 may be, for example, 1×10 ¹⁵ cm ^-3 to 1×10 ²⁰ cm ^-3 . The n-type impurity concentration of the n ⁺ -type source region 56 is higher than the impurity concentration of the n-type semiconductor substrate 6, and may be, for example, 1×10 ¹⁸ cm ^-3 to 5×10 ²¹ cm ^-3 .

A p ⁺ type body contact region 57 is formed in an inner region of the n ⁺ type source region 56. The p ⁺ type body contact region 57 is formed to penetrate the n ⁺ type source region 56 in the depth direction. The p-type impurity concentration of the p ⁺ type body contact region 57 is higher than that of the p-type body region 55, and may be, for example, 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ .

A gate insulating film 58 is formed on the inner surface of the gate trench 53 and on the surface of the semiconductor substrate 6. The gate insulating film 58 may be made of, for example, silicon oxide (SiO ₂ ). The thickness of the gate insulating film 58 may be, for example, 300 Å to 600 Å.

A gate electrode 59 is embedded in the gate trench 53. The gate electrode 59 faces the p-type body region 55 on the side of the gate trench 53 across the gate insulating film 58. The gate electrode 59 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may also be made of p-type polysilicon.

Next, the structure of the temperature sensing region 9 when the cell region 7 is as shown in Figures 15A and 15B will be described. Figure 16A is a schematic plan view showing the structure of the temperature sensing region 9 of the semiconductor device 1 of Figure 3. Figure 16B is a cross-sectional view (cross-sectional view taken along line B-B) of Figure 16A. Figure 16C is a cross-sectional view (cross-sectional view taken along line C-C) of Figure 16A. In Figures 16A to 16C, components that are the same as those shown in the previously described Figures 5A and 5B are given the same reference numerals and will not be described.

16A to 16C, the temperature sensing region 9 is defined by and surrounded by the gate trench 53. As shown in FIG. 16A, the temperature sensing region 9 may be, for example, a square in plan view surrounded on all four sides by the gate trench 53.

In the temperature sensing region 9, an n ⁺ type region 60 is formed in the surface portion of the semiconductor substrate 6, and a p type region 61 is formed below ^the n ⁺ type region 60. The p type region 61 is in contact with the n ⁺ type region 60. The n + type region 60 may have the same n type impurity concentration and depth as the n ⁺ type source region 56. The p type region 61 may have the same p type impurity concentration and depth as the p type body region 55, but may have a protruding portion 62 that is deeper than the p type body region 55 and selectively protrudes downward as shown in Figures 16B and 16C.

A temperature sense trench 63, which is an example of the second trench of the present invention, is formed in the inner region of the temperature sense region 9. In other words, the temperature sense trench 63 is independent of the gate trench 53 that surrounds the temperature sense region 9. The temperature sense trench 63 may be formed with the same width as the gate trench 53, for example.

The temperature sensing trench 63 may be formed so as to penetrate the p-type region 61, but as shown in Figures 16B and 16C, it may be formed on the protruding portion 62 so as not to penetrate the p-type region 61, and its bottom may be located inside the p-type region 61 (protruding portion 62).

The temperature sense trench 63 is formed in a ring shape in a plan view, and a closed region 64 is defined inside the temperature sense trench 63. A p ⁺ type contact region 65 is formed in the closed region 64. The p ⁺ type contact region 65 may be formed on the entire surface of the closed region 64 as shown in FIG. 16A, or may be selectively formed only in a part of the closed region 64, although not shown. The p ⁺ type contact region 65 may have the same p-type impurity concentration and depth as the p ⁺ type body contact region 57.

The gate insulating film 58 of the cell region 7 is formed on the inner surface of the temperature sensing trench 63, extending to the temperature sensing region 9. A temperature sensing diode 66 (pn diode) as an example of a temperature sensing element TS is formed inside the gate insulating film 58.

The temperature sensing diode 66 is made of a buried polysilicon layer 67 buried in the temperature sensing trench 63. The temperature sensing diode 66 made of the buried polysilicon layer 67 may be formed in the same process as the gate electrode 59, or may be formed in a separate process from the gate electrode 59.

The temperature sense diode 66 includes a p-type region 68 and an n ⁺ -type region 69 adjacent to the p-type region 68 in the lateral direction. In other words, the p-type region 68 may be buried to the bottom in a certain region of the annular temperature sense trench 63, and the n ⁺ -type region 69 may be buried to the bottom in another region of the temperature sense trench 63 so as to be adjacent to the p-type region 68. If the p-type region 68 and the n ⁺ -type region 69 are configured to be adjacent to each other in the lateral direction, the p-type region 68 and the n ⁺ -type region 69 do not overlap in a plan view, so that no separate wiring or the like is required, and contact can be easily made to both the p-type region 68 and the n ⁺ -type region 69.

The p-type region 68 may have a p-type impurity concentration of, for example, 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ (the same as the p-type body region 55). The n-type impurity concentration of the n ⁺ region 69 may have a n-type impurity concentration of, for example, 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ (the same as the n ⁺ source region 56).

The temperature sense diode 66 may further include a p ⁺ type contact region 70. The p ⁺ type contact region 70 is formed so as to be in contact with the p type region 68, but is separated from the n ⁺ type region 69 by the p type region 68. The p ⁺ type contact region 70 may be embedded to the bottom of the temperature sense trench 63 and be adjacent to the p type region 68 in the lateral direction as shown in FIG. 16C, or may be selectively formed in the surface portion of the p type region 68 at a position away from the boundary between the p type region 68 and the n ⁺ type region 69, although not shown. The p type impurity concentration of the p ⁺ type contact region 70 may be, for example, 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ (the same as the p ⁺ type body contact region 57).

It should be noted that the first electrode 10 in FIG. 3 is connected to the p ⁺ type contact region 70 as an anode electrode, and the second electrode 11 in FIG. 3 is connected to the n ⁺ type region 69 as a cathode electrode.

As described above, the above-mentioned temperature sensing diode 66 can also perform the same function as the previously described temperature sensing diode 20. Furthermore, since the temperature sensing diode 66 (pn diode) is embedded in the surface portion of the semiconductor substrate 6, the pn junction can be brought closer to the current path on the surface side, which is the heat generating portion of the semiconductor substrate 6, than in the case of the temperature sensing diode 20. This makes it possible to detect temperature changes in the semiconductor substrate 6 with high accuracy.

Although one embodiment of the present invention has been described above, the present invention can also be implemented in other forms.

For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 is inverted may be adopted. That is, in the semiconductor device 1, the p-type portion may be n-type, and the n-type portion may be p-type.

In addition to the aforementioned temperature sensing diodes 20 and 42 (pn diodes), Schottky barrier diodes, etc. can also be used as the temperature sensing element TS.

In addition, various design changes may be made within the scope of the claims.

LIST OF SYMBOLS 1 semiconductor device 2 source pad 3 gate pad 4 semiconductor module 5 short circuit protection circuit 6 semiconductor substrate 7 cell region 9 temperature sensing region 10 first electrode 11 second electrode 12 p-type body region 13 unit cell 14 n ⁺ type source region 16 gate insulating film 17 gate electrode 20 temperature sensing diode 21 polysilicon layer 22 p-type region 23 n ⁺ type region 24 p ⁺ type contact region 25 p-type peripheral region 26 p-type base layer 42 temperature sensing diode 43 p-type region 44 n ⁺ type region 45 p ⁺ type contact region 46 p-type peripheral region 47 series connection unit 48 terminal 49 terminal 50 reverse series connection unit 51 terminal 52 terminal 53 gate trench 54 unit cell 55 p-type body region 56 n ⁺ type source region 58 Gate insulating film 59 Gate electrode 63 Temperature sensing trench 66 Temperature sensing diode 67 Buried polysilicon layer 68 p type region 69 n ⁺ type region 70 p ⁺ type contact region SW Switching element TS Temperature sensing element G/D Gate driver

Claims (17)

a semiconductor chip having a rectangular shape in a plan view and made of a semiconductor substrate having a front surface and a back surface opposite to the front surface;
a switching element formed on the semiconductor substrate, the switching element performing a switching operation between a first electrode provided on the front surface side and a second electrode provided on the back surface side of the semiconductor substrate in response to a signal input to a control electrode formed on the front surface side of the semiconductor substrate;
a gate finger extending from the control electrode along an outer periphery of the semiconductor chip and extending across a central portion of the semiconductor chip;
a temperature sensing element provided on the front surface side and capable of outputting a signal dependent on temperature;
a third electrode and a fourth electrode electrically connected to the temperature sensing element;
the control electrode, the third electrode, and the fourth electrode have the same size and shape as each other,
the control electrode is disposed at a center portion of one side of the semiconductor chip, and the third electrode and the fourth electrode are disposed side by side on one side of the control electrode along the side on which the control electrode is disposed,
The temperature sensing element is disposed adjacent to the gate finger . 2. The semiconductor device according to claim 1 , further comprising a diode element capable of outputting a signal dependent on temperature as said temperature sensing element. The semiconductor device according to claim 2, wherein the anode and cathode of the diode element are connected to the third electrode and the fourth electrode, respectively. the switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode;
the source electrode has two regions separated by the gate finger that crosses a central portion of the semiconductor chip;
2 . The semiconductor device according to claim 1 , wherein said third electrode and said fourth electrode are disposed adjacent to a periphery of one of said two separated regions of said source electrode. The semiconductor device according to any one of claims 1 to 3, wherein the switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode. The semiconductor device according to any one of claims 1 to 5, wherein the third electrode and the fourth electrode are connected to terminals that are electrically independent from the terminals to which the first electrode and the second electrode of the switching element are respectively connected. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element includes a series-connected unit in which at least a pair of pn diodes are connected in series or in reverse series. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element comprises at least a pair of pn diodes connected in antiparallel. The semiconductor device according to claim 1 or 2, wherein the temperature sensing element is a series-connected unit in which at least a pair of pn diodes are connected in series and connected in parallel in the opposite directions to each other. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor substrate includes a SiC semiconductor layer. The semiconductor device according to claim 10, wherein the temperature sensing element is formed in a polysilicon layer on the SiC semiconductor layer. The semiconductor device according to claim 11, wherein the polysilicon layer forming the temperature sensing element has the same thickness as the gate electrode of the switching element. The semiconductor device according to claim 11 or 12, wherein the polysilicon layer forming the temperature sensing element includes a first conductivity type impurity region and a second conductivity type impurity region selectively introduced. The semiconductor device according to claim 11 or 12, wherein the polysilicon layer forming the temperature sensing element includes a base layer of a second conductivity type and an impurity region of a first conductivity type selectively introduced into the surface of the base layer. The semiconductor device according to any one of claims 1 to 14, wherein the switching element includes a trench-gate type MISFET having a gate trench formed in the semiconductor chip and partitioning a unit cell, a gate electrode embedded in the gate trench, a body region of a first conductivity type formed in a surface portion of the unit cell, a source region of a second conductivity type formed in a surface portion of the body region, and a drain region of the second conductivity type formed on the opposite side of the source region with respect to the body region. 16. The semiconductor device according to claim 1, wherein the temperature sensing element is disposed in a temperature sensing region between the third electrode and the fourth electrode. The semiconductor device according to any one of claims 1 to 10, wherein the temperature sensing element is composed of a first conductivity type region formed in the semiconductor substrate and a second conductivity type region surrounding the first conductivity type region.

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