JP7675357B2 - Electronic Control Unit - Google Patents

Description

This disclosure relates to an electronic control device that communicates using a differential transmission method.

Electronic control devices that use the in-vehicle communication standard CAN (Controller Area Network) are known. CAN employs a differential transmission method that transmits data using the potential difference between two communication lines. To transmit data safely, noise countermeasures and overvoltage protection measures are required. Patent Document 1 discloses an electronic control device equipped with a common mode noise filter and a Zener diode to implement noise countermeasures and overvoltage protection measures.

Patent No. 6498096

However, in conventional electronic control devices, communication errors can occur when a large voltage is input to the communication lines.

The present disclosure is intended to solve the above problems and aims to provide an electronic control device that can suppress the occurrence of communication errors.

An electronic control device according to one aspect of the present disclosure includes a first input/output terminal and a second input/output terminal for inputting and outputting a differential signal, a transceiver IC for transmitting and receiving the differential signal, a first line which is a line connecting the first input/output terminal and the transceiver IC, and a second line which is a line connecting the second input/output terminal and the transceiver IC, wherein a first capacitance which is a capacitance between the first line and ground is 80 pF or more and 220 pF or less, and a second capacitance which is a capacitance between the second line and the ground is 80 pF or more and 220 pF or less. the first capacitance is a total capacitance of the first varistor element and the first capacitor element, and the second capacitance is a total capacitance of the second varistor element and the second capacitor element, and the first capacitance is a total capacitance of the second varistor element and the second capacitor element, and the second capacitance is a total capacitance of the second varistor element and the second capacitor element.
An electronic control device according to one aspect of the present disclosure includes a first input/output terminal and a second input/output terminal for inputting and outputting a differential signal, a transceiver IC for transmitting and receiving the differential signal, a first line which is a line connecting the first input/output terminal and the transceiver IC, and a second line which is a line connecting the second input/output terminal and the transceiver IC, wherein a first capacitance which is a capacitance between the first line and ground is not less than 80 pF and not more than 220 pF, and a second capacitance which is a capacitance between the second line and the ground is not less than 80 pF and not more than 220 pF, and further includes a first varistor element provided on a first ground line connecting the first line and the ground, and a second varistor element provided on a second ground line connecting the second line and the ground, wherein the first capacitance is a capacitance of the first varistor element, and the second capacitance is a capacitance of the second varistor element.

The electronic control device disclosed herein can prevent communication errors from occurring.

FIG. 2 is a circuit diagram showing an electronic control device of a first comparative example. 1 is a circuit diagram showing an electronic control device according to a first embodiment; FIG. 11 is a circuit diagram showing an electronic control device of a second comparative example. 11 is a diagram showing the passing characteristics of a common mode signal in the electronic control device of the first embodiment and the second comparative example. FIG. 13 is a diagram showing the passing characteristics of a differential mode signal in the electronic control device of the first embodiment and the electronic control device of the second comparative example. FIG. FIG. 11 is a diagram showing the capacitance between a differential signal line and ground in an electronic control device, and the cutoff frequency of the insertion loss of a differential mode signal. 11 is a diagram showing the pass characteristics of a common-differential mode conversion signal in the electronic control device of the first embodiment and the second comparative example. FIG. 13 is a diagram showing another example of the pass characteristics of the common-differential mode conversion signal in the electronic control devices of the first embodiment and the second comparative example. FIG. FIG. 2 is a diagram illustrating an electronic control device according to a first modified example of the first embodiment. FIG. 13 is a diagram illustrating an electronic control device according to a second modified example of the first embodiment. FIG. 11 is a plan view showing an electronic control device according to a second embodiment. 11 is a plan view showing a portion of a multilayer board of an electronic control device according to a second embodiment. FIG. 11 is a cross-sectional view showing a portion of a multilayer board of an electronic control device according to a second embodiment. FIG. FIG. 11 is a plan view showing a multilayer substrate according to an embodiment of the present invention, which is an example of a second embodiment. FIG. 2 is a cross-sectional view showing a multilayer substrate according to an embodiment of the present invention. FIG. 11 is a plan view showing a multilayer substrate of Comparative Example 3. FIG. 11 is a cross-sectional view showing a multilayer substrate of Comparative Example 3. FIG. 13 is a diagram showing the transmission characteristics of a differential mode signal in the multilayer substrates of the example and the comparative example 3. FIG. 13 is a diagram showing the transmission characteristics of a common mode signal in the multilayer substrates of the example and the comparative example 3. 13 is a cross-sectional view showing a portion of a multilayer board of an electronic control device according to a first modified example of the second embodiment. FIG. 13 is a plan view showing a portion of a multilayer board of an electronic control device according to a second modification of the second embodiment. FIG.

(Background to this disclosure)
First, an electronic control device according to a first comparative example that uses communication based on a differential transmission method will be described.

Figure 1 is a circuit diagram showing an electronic control device 101 of Comparative Example 1.

The electronic control device 101 of Comparative Example 1 includes a transceiver IC 150 that transmits and receives communication signals via a first line 121 and a second line 122 that are differential signal lines, a Zener diode 177 that protects the transceiver IC 150 from disturbance surges, a common mode choke coil 176 that attenuates common mode noise, and a microprocessor 160 that transmits control signals to the transceiver IC 150 via a control signal line 125. The electronic control device 101 of Comparative Example 1 also includes a Zener diode 179 that protects the transceiver IC 150 when a back electromotive force is generated in the common mode choke coil 176.

The common mode choke coil 176 is inserted into the first line 121 and the second line 122, passes the signal current, and attenuates the common mode noise current. Most of the noise superimposed on the differential signal lines is common mode noise, and the common mode choke coil 176 can attenuate the common mode noise.

For example, if an external bus line connected to the first line 121 is shorted to a battery and the voltage of the first line 121 is raised high, a back electromotive force is generated in the common mode choke coil 176. In the electronic control device 101 of Comparative Example 1, even if a back electromotive force is generated, the Zener diode 179 operates to protect the transceiver IC 150. However, when the potential of the first line 121 returns to its original state, a reverse recovery current flows through the Zener diode 179, which disrupts communication of the transceiver IC 150 and causes a communication error.

The electronic control device of this embodiment has the following configuration to prevent communication errors from occurring.

The following describes the embodiment in detail with reference to the drawings.

Note that each of the embodiments described below shows a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement positions, connection forms, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in an independent claim are described as optional components.

In addition, in this specification, the numerical ranges are not expressions that express only a strict meaning, but expressions that include a substantially equivalent range, for example, a difference of about a few percent.

In addition, each figure is a schematic diagram in which emphasis, omissions, or adjustments to the ratio have been made as appropriate to illustrate the present disclosure, and is not necessarily an exact illustration, and may differ from the actual shape, positional relationship, and ratio. In each figure, the same reference numerals are used for substantially the same configuration, and duplicate explanations may be omitted or simplified.

(Embodiment 1)
[Configuration of electronic control device]
The configuration of the electronic control device according to the first embodiment will be described with reference to FIG.

Figure 2 is a circuit diagram showing the electronic control device 1 according to the first embodiment. As shown in Figure 2, the electronic control device 1 includes a connector 10, a transceiver IC 50, a microprocessor 60, and a protection circuit 5.

The electronic control device 1 also includes a first line 21 and a second line 22, which are differential signal lines, and a control signal line 25. The first line 21 is a line that connects the first input/output terminal 11 of the connector 10 and the transceiver IC 50. The second line 22 is a line that connects the second input/output terminal 12 of the connector 10 and the transceiver IC 50. The control signal line 25 is a line that connects the transceiver IC 50 and the microprocessor 60.

In other words, the connector 10 and the transceiver IC 50 are connected via the first line 21 and the second line 22. The transceiver IC 50 and the microprocessor 60 are connected via the control signal line 25.

The electronic control unit 1 is installed, for example, in a vehicle and communicates with other electronic control units in the vehicle via an in-vehicle network. A harness 90, which is a bus line for communicating with other electronic control units, is connected to the electronic control unit 1. When a CAN (Controller Area Network) is used as the in-vehicle network, for example, an STP (Shielded Twisted Pair) cable or a UTP (Unshielded Twisted Pair) cable is used as the harness 90.

The microprocessor 60 executes various application processes according to the in-vehicle device. For example, if the in-vehicle device is an infotainment device (e.g., a car navigation device, a display audio), the microprocessor 60 executes image signal processing or audio signal processing.

The transceiver IC 50 converts the differential signal received via the harness 90 into a digital signal that is processed by the microprocessor 60. The transceiver IC 50 also converts the digital signal processed by the microprocessor 60 into a differential signal, and transmits the converted differential signal to another electronic control device via the harness 90.

The connector 10 has a first input/output terminal 11 and a second input/output terminal 12. A harness 90 is connected to the first input/output terminal 11 and the second input/output terminal 12, and differential signals are input and output. The input impedance of the first input/output terminal 11 and the second input/output terminal 12, i.e., the input impedance of the transceiver IC 50, is, for example, 12 kΩ or more and 100 kΩ or less.

A termination resistor (not shown) defined in ISO11898-2 is provided between the differential signal lines. The termination resistor is a circuit in which two 60 Ω resistors are connected in series between the differential signal lines and a 4.7 nF to 100 nF capacitor is connected between the node to which the two 60 Ω resistors are connected and ground G, and is provided between the first line 21 and second line 22, which are the differential signal lines, or in the harness 90.

In the electronic control device 1 of this embodiment, a common mode choke coil (common mode noise filter) is not provided between the first input/output terminal 11 and the second input/output terminal 12 and the transceiver IC 50, and a protection circuit 5 is connected. The protection circuit 5 is connected to the first line 21 and the second line 22.

The protection circuit 5 is composed of a first varistor element ZNR1, a second varistor element ZNR2, a first capacitor element C1, and a second capacitor element C2.

The first varistor element ZNR1 is provided on the first ground line 31 that connects the first line 21 and ground G. Specifically, one terminal of the first varistor element ZNR1 is connected to a node n1 on the first line 21 between the first input/output terminal 11 and the transceiver IC 50, and the other terminal of the first varistor element ZNR1 is connected to ground G. Ground G is the reference potential of the electronic control device 1, and is realized by, for example, electrically connecting it to the body earth of the vehicle.

The second varistor element ZNR2 is provided on the second ground line 32 that connects the second line 22 and ground G. Specifically, one terminal of the second varistor element ZNR2 is connected to a node n2 on the second line 22 between the second input/output terminal 12 and the transceiver IC 50, and the other terminal of the second varistor element ZNR2 is connected to ground G.

The first capacitor element C1 is provided on the third ground line 33 connecting the first line 21 and the ground G. Specifically, one terminal of the first capacitor element C1 is connected to a node n3 on the first line 21 between the first input/output terminal 11 and the transceiver IC 50, and the other terminal of the first capacitor element C1 is connected to the ground G. That is, the first capacitor element C1 is connected in parallel to the first varistor element ZNR1. The node n3 is provided on the first line 21 between the node n1 and the transceiver IC 50, but is not limited thereto and may be provided on the first line 21 between the first input/output terminal 11 and the node n1. No other electronic components are connected to the line between the node n1 and the node n3.

The second capacitor element C2 is provided on the fourth ground line 34 that connects the second line 22 and the ground G. Specifically, one terminal of the second capacitor element C2 is connected to a node n4 on the second line 22 between the second input/output terminal 12 and the transceiver IC 50, and the other terminal of the second capacitor element C2 is connected to the ground G. That is, the second capacitor element C2 is connected in parallel to the second varistor element ZNR2. The node n4 is provided on the second line 22 between the node n2 and the transceiver IC 50, but is not limited thereto and may be provided on the second line 22 between the second input/output terminal 12 and the node n2. No other electronic components are connected to the line between the node n2 and the node n4.

The first varistor element ZNR1 and the second varistor element ZNR2 are conductive under certain voltage conditions, and can extract current from the nodes n1 and n2 to ground G. Therefore, even if a large current flows through the first line 21 and the second line 22, the current can be prevented from flowing into the transceiver IC 50, and the transceiver IC 50 can be protected.

The first capacitance CP1, which is the total capacitance of the first varistor element ZNR1 and the first capacitor element C1, is 80 pF or more and 220 pF or less. The second capacitance CP2, which is the total capacitance of the second varistor element ZNR2 and the second capacitor element C2, is also 80 pF or more and 220 pF or less. In other words, the capacitance between the first line 21 and ground G is 80 pF or more and 220 pF or less, and the capacitance between the second line 22 and ground G is also 80 pF or more and 220 pF or less.

In this way, the electronic control device 1 of this embodiment does not have a common mode choke coil as shown in Comparative Example 1. Therefore, it is possible to suppress the occurrence of a back electromotive force due to the common mode choke coil. This makes it possible to suppress the occurrence of communication errors caused by the back electromotive force in the electronic control device 1.

In addition, in the electronic control device 1, the capacitance between the first line 21 and ground G and the capacitance between the second line 22 and ground G are both 80 pF or more and 220 pF or less. This makes it possible to attenuate the common mode signal input/output to the electronic control device 1 and suppress distortion of the square wave of the differential signal, which is a differential mode signal. This point will be explained below.

[Effects, etc.]
The effects of the electronic control device 1 having the above configuration will be described in comparison with Comparative Example 2. In addition, the numerical ranges of the first capacitance CP1 and the second capacitance CP2 described above will also be described here.

Figure 3 is a circuit diagram showing the electronic control device 102 of Comparative Example 2.

The electronic control device 102 of Comparative Example 2 includes a connector 10, a transceiver IC 50, a microprocessor 60, and a protection circuit 105, and further includes a common mode choke coil 176.

The common mode choke coil 176 of Comparative Example 2 is inserted in series in the lines between the first and second input/output terminals 11 and 12 and the transceiver IC 50. The protection circuit 105 is connected to the lines between the first and second input/output terminals 11 and 12 and the common mode choke coil 176. The protection circuit 105 is composed of a first varistor element ZNR1 and a second varistor element ZNR2. The inductance of the common mode choke coil 176 is, for example, 100 μH. As the actual common mode choke coil 176, a product manufactured by TDK Corporation (product number: ACT1210-101-2P-TL00) was used.

Figure 4 shows the pass characteristics of a common mode signal in the electronic control device of the first embodiment and the second comparative example. The horizontal axis of the figure is the frequency of the common mode signal. The vertical axis of the figure is the attenuation amount Scc21 of the common mode signal, with the attenuation amount increasing toward the bottom.

The figure also shows the pass characteristics when the first capacitance CP1 and the second capacitance CP2 are changed in the electronic control device 1, i.e., when the capacitance between the differential signal line and ground G is changed. The first capacitance CP1 is changed by setting the capacitance of the first varistor element ZNR1 to 15 pF and changing the capacitance of the first capacitor element C1 from 55 pF to 225 pF. The second capacitance CP2 is changed by setting the capacitance of the second varistor element ZNR2 to 15 pF and changing the capacitance of the second capacitor element C2 in the same way as the first capacitor element C1.

In addition, "xxpF" in the figure means that "first capacitance CP1 = second capacitance CP2 = xxpF" (x is a numerical value). The same applies to the following figures.

As shown in FIG. 4, when the first capacitance CP1 and the second capacitance CP2 in the first embodiment are each 70 pF, the attenuation Scc21 is smaller than that in the second comparative example at a frequency of around 50 MHz. In contrast, when the first capacitance CP1 and the second capacitance CP2 are each 80 pF or more, the attenuation Scc21 is larger than that in the second comparative example over the entire frequency range shown in FIG. 4. In other words, in order to make the attenuation Scc21 of the common mode signal larger than that in the second comparative example, it is desirable to set the first capacitance CP1 and the second capacitance CP2 in the first embodiment to 80 pF or more.

Figure 5 shows the pass characteristics of a differential mode signal in the electronic control device of embodiment 1 and comparative example 2. The horizontal axis of the figure is the frequency of the differential mode signal. The vertical axis of the figure is the insertion loss Sdd21 of the differential mode signal, with the loss increasing downward. The figure also shows the pass characteristics when the first capacitance CP1 and the second capacitance CP2 are changed in the electronic control device 1. The method of changing the capacitance is the same as the example shown in Figure 4.

As shown in FIG. 5, when the first capacitance CP1 and the second capacitance CP2 in the first embodiment are each 240 pF, a loss of 3 dB or more occurs at a frequency of 12.5 MHz. In contrast, when the first capacitance CP1 and the second capacitance CP2 are each 220 pF or less, a loss of 3 dB or more does not occur at a frequency of 12.5 MHz. Note that the frequency of 12.5 MHz is the upper limit of the frequency required to reliably transmit and receive differential mode signals, and here, for example, is set to 5 times the frequency of 2.5 MHz used when communicating at a communication speed of 5 Mbps that conforms to CAN FD (CAN with Flexible Data Rate) communication.

Figure 6 shows the capacitance between the differential signal lines in the electronic control device 1 and ground G, and the cutoff frequency fc of the insertion loss Sdd21 of the differential mode signal. The cutoff frequency fc is the frequency at which a loss of 3 dB occurs.

As shown in FIG. 6, when the first capacitance CP1 and the second capacitance CP2 in the first embodiment are 240 pF or 230 pF, respectively, the cutoff frequency fc is equal to or lower than the 12.5 MHz set above. In contrast, when the first capacitance CP1 and the second capacitance CP2 are equal to or lower than 220 pF, respectively, the cutoff frequency fc is greater than 12.5 MHz. In other words, to make the cutoff frequency fc greater than 12.5 MHz, it is desirable to set the first capacitance CP1 and the second capacitance CP2 in the first embodiment to equal to or lower than 220 pF.

In other words, based on the results of Figures 4 to 6, it is desirable to set the first capacitance CP1 and the second capacitance CP2 in the first embodiment to 80 pF or more and 220 pF or less, respectively. This makes it possible to attenuate the common mode signal and suppress distortion of the square wave of the differential signal, which is a differential mode signal, even if the electronic control device 1 does not have a common mode choke coil.

Next, a more desirable configuration of the electronic control device 1 will be described in comparison with Comparative Example 2. The capacitance difference between the first capacitance CP1 and the second capacitance CP2 will also be described.

Figure 7 is a diagram showing the pass characteristics of the common-differential mode conversion signal in the electronic control devices of embodiment 1 and comparative example 2. The horizontal axis of the figure is the frequency of the common-differential mode conversion signal. The vertical axis of the figure is the attenuation amount Sds21 of the common-differential mode conversion signal, with the attenuation amount increasing toward the bottom.

The figure also shows the pass characteristics when the capacitance difference between the first capacitance CP1 and the second capacitance CP2 in the electronic control device 1 is changed. The capacitance difference between the first capacitance CP1 and the second capacitance CP2 is changed, for example, by fixing the first capacitance CP1 at 220 pF and changing the second capacitance CP2. The capacitance difference is a value calculated by the formula "Capacitance difference (%) = ((first capacitance CP1 - second capacitance CP2) / first capacitance CP1) x 100". In this example, the first capacitance CP1 is set to be greater than the second capacitance CP2.

As shown in FIG. 7, when the capacitance difference is 20% or 15%, the attenuation Sds21 is smaller than that of Comparative Example 2 at frequencies from 1 MHz to 3 MHz and from 10 MHz to 60 MHz. In contrast, when the capacitance difference is 10% or less, the attenuation Sds21 is larger than that of Comparative Example 2 across the entire frequency band shown in FIG. 7. In other words, in order to make the attenuation Sds21 of the common-differential mode conversion signal larger than that of Comparative Example 2, it is desirable to set the capacitance difference between the first capacitance CP1 and the second capacitance CP2 of embodiment 1 to 10% or less.

Figure 8 shows another example of the pass characteristics of the common-differential mode conversion signal in the electronic control device of embodiment 1 and comparative example 2.

The figure also shows the pass characteristics when the difference in capacitance value between the first capacitance CP1 and the second capacitance CP2 is changed in the electronic control device 1. The difference in capacitance value between the first capacitance CP1 and the second capacitance CP2 is changed by changing the first capacitance CP1 from 70 pF to 240 pF so that the difference in capacitance value is 10%.

For example, if the first capacitance CP1 is 80 pF, the difference in capacitance between the first capacitance CP1 and the second capacitance CP2 is Δ8 pF. For example, if the first capacitance CP1 is 220 pF, the difference in capacitance between the first capacitance CP1 and the second capacitance CP2 is Δ22 pF. Note that in this example, the first capacitance CP1 is greater than the second capacitance CP2.

As shown in FIG. 8, when the difference in capacitance value is 10%, the attenuation Sds21 when the first capacitance CP1 and the second capacitance CP2 of the first embodiment are between 70 pF and 240 pF is greater than that of the second comparative example across the entire frequency band. In other words, by setting the first capacitance CP1 and the second capacitance CP2 of the first embodiment described above to between 80 pF and 220 pF and the capacitance difference between the first capacitance CP1 and the second capacitance CP2 to 10%, the attenuation Sds21 of the common-differential mode conversion signal can be made greater than that of the second comparative example.

The BCI (Bulk Current Injection) test method is a standard for evaluating the noise resistance of in-vehicle electronic devices. This test method evaluates the immunity (electromagnetic susceptibility) of electronic devices by injecting a high-frequency interference current into the harness using a current injection probe (BCI probe), and the conditions are set by automobile manufacturers and ISO11452-4. ISO11452-4 requires the injection of interference current in the frequency range of 1MHz to 400MHz as a test condition.

This test checks for malfunctions or problems that occur when the harness of an electronic device is excited by an electromagnetic field radiated by other electronic devices such as wireless devices, inducing strong magnetic field noise in the harness. Since large amplitude current noise/voltage noise is injected into the twisted pair cable used in the harness of the electronic control device 1 in common mode, it is desirable for the varistor element provided in the electronic control device 1 to attenuate common mode noise and also to significantly suppress the amount of common-differential mode conversion.

As described above, by reducing the capacitance difference of the electrostatic capacitance, it is possible to prevent a common mode noise signal input to the electronic control device 1 due to, for example, the induction of strong magnetic field noise from being converted into a differential mode noise signal by the varistor element. This makes it possible to prevent communication errors from occurring in the electronic control device 1.

[First Modification of First Embodiment]
A description will be given of an electronic control device 1A according to a first modification of the first embodiment. In the first modification, an example will be described in which a protection circuit 5A is composed only of a varistor element.

Figure 9 is a circuit diagram showing an electronic control device 1A according to a first modified example of the first embodiment. The electronic control device 1A of the first modified example includes a connector 10, a transceiver IC 50, a microprocessor 60, and a protection circuit 5A.

In the electronic control device 1A, a common mode choke coil is not provided between the first input/output terminal 11 and the second input/output terminal 12 and the transceiver IC 50, and a protection circuit 5A is connected between them. The protection circuit 5A is composed of a first varistor element ZNR1 and a second varistor element ZNR2.

The first varistor element ZNR1 is provided on the first ground line 31 that connects the first line 21 and ground G. The second varistor element ZNR2 is provided on the second ground line 32 that connects the second line 22 and ground G.

The first capacitance CP1, which is the capacitance of the first varistor element ZNR1, is 80 pF or more and 220 pF or less. The second capacitance CP2, which is the capacitance of the second varistor element ZNR2, is also 80 pF or more and 220 pF or less. In other words, the capacitance between the first line 21 and ground G is 80 pF or more and 220 pF or less, and the capacitance between the second line 22 and ground G is also 80 pF or more and 220 pF or less.

The electronic control device 1A of the first modification does not have a common mode choke coil as shown in the second comparative example. Therefore, it is possible to suppress the occurrence of a back electromotive force due to the common mode choke coil. This makes it possible to suppress the occurrence of communication errors caused by the back electromotive force in the electronic control device 1A.

In addition, in the electronic control device 1A, the capacitance between the first line 21 and ground G and the capacitance between the second line 22 and ground G are each 80 pF or more and 220 pF or less. This attenuates the common mode signal input/output to the electronic control device 1A and suppresses distortion of the rectangular wave of the differential signal, which is a differential mode signal.

[Modification 2 of the First Embodiment]
A description will now be given of an electronic control device 1B according to Modification 2 of Embodiment 1. In Modification 2, an example will be described in which two varistor elements of a protection circuit 5B are provided in one multilayer varistor component.

Figure 10 is a circuit diagram showing an electronic control device 1B according to a second modification of the first embodiment. The electronic control device 1B of the second modification includes a connector 10, a transceiver IC 50, a microprocessor 60, and a protection circuit 5B.

In the electronic control device 1B, a common mode choke coil is not provided between the first input/output terminal 11 and the second input/output terminal 12 and the line of the transceiver IC 50, and a protection circuit 5B is connected. The protection circuit 5B is composed of a laminated varistor component 40 provided with a first varistor element ZNR1 and a second varistor element ZNR2.

The laminated varistor component 40 is composed of a first signal terminal 41 which is one terminal of the first varistor element ZNR1, a second signal terminal 42 which is one terminal of the second varistor element ZNR2, and a ground terminal 43 which is a common terminal of the other terminal of the first varistor element ZNR1 and the other terminal of the second varistor element ZNR2.

The first signal terminal 41 is connected to node n1 of the first line 21, and the second signal terminal 42 is connected to node n2 of the second line 22. The ground terminal 43 is a common terminal in which the other terminal of the first varistor element ZNR1 and the other terminal of the second varistor element ZNR2 are commonized, and is connected to ground G. Since the other terminal of the first varistor element ZNR1 and the other terminal of the second varistor element ZNR2 are commonized, it is possible to reduce the difference in capacitance between the first varistor element ZNR1 and the second varistor element ZNR2.

The laminated varistor component 40 is formed by laminating multiple ceramic layers and multiple ceramic layers with internal electrodes, and then providing external terminals. The internal electrodes are precisely formed on the ceramic layers by a printing method or the like, and the ceramic layers with internal electrodes have a substantially uniform thickness within the component, so that it is possible to reduce the difference in capacitance between the first varistor element ZNR1 and the second varistor element ZNR2 to, for example, 5% or less.

The electronic control device 1B of the second modification does not have a common mode choke coil as shown in the second comparative example. Therefore, it is possible to prevent the occurrence of a back electromotive force due to the common mode choke coil. This makes it possible to prevent the occurrence of communication errors caused by the back electromotive force in the electronic control device 1B.

Furthermore, in the electronic control device 1B, the difference in capacitance between the first varistor element ZNR1 and the second varistor element ZNR2 can be reduced. This makes it possible to reduce the difference in capacitance between the first line 21 and ground G and between the second line 22 and ground G. This makes it possible to prevent, for example, a common mode noise signal input to the electronic control device 1B due to the induction of strong magnetic field noise from being converted into a differential mode noise signal by the varistor element. This makes it possible to prevent communication errors from occurring in the electronic control device 1B.

[Summary of the First Embodiment]
The electronic control device 1 according to this embodiment includes a first input/output terminal 11 and a second input/output terminal 12 for inputting and outputting differential signals, a transceiver IC 50 for transmitting and receiving the differential signals, a first line 21 which is a line connecting the first input/output terminal 11 and the transceiver IC 50, and a second line 22 which is a line connecting the second input/output terminal 12 and the transceiver IC 50. A first capacitance CP1 which is a capacitance between the first line 21 and the ground G is not less than 80 pF and not more than 220 pF, and a second capacitance CP2 which is a capacitance between the second line 22 and the ground G is not less than 80 pF and not more than 220 pF.

In this way, by setting each of the first capacitance CP1 and the second capacitance CP2 to be between 80 pF and 220 pF, it is possible to attenuate the common mode signal input/output to the electronic control device 1 and suppress distortion of the rectangular wave of the differential signal, which is a differential mode signal. Therefore, it is no longer necessary to provide a common mode choke coil in the electronic control device 1, and it is possible to suppress the generation of back electromotive force by the common mode choke coil. This makes it possible to suppress the occurrence of communication errors in the electronic control device 1. Furthermore, because a common mode choke coil is not provided, it is possible to reduce the size of the electronic control device 1.

The electronic control device 1 further includes a first varistor element ZNR1 provided on a first ground line 31 connecting the first line 21 and ground G, a second varistor element ZNR2 provided on a second ground line 32 connecting the second line 22 and ground G, a first capacitor element C1 connected in parallel to the first varistor element ZNR1, and a second capacitor element C2 connected in parallel to the second varistor element ZNR2, and the first capacitance CP1 may be the total capacitance of the first varistor element ZNR1 and the first capacitor element C1, and the second capacitance CP2 may be the total capacitance of the second varistor element ZNR2 and the second capacitor element C2.

In this way, by providing the electronic control device 1 with the first varistor element ZNR1 and the second varistor element ZNR2, for example, even if a large current flows through the first line 21 and the second line 22, the current can be prevented from flowing into the transceiver IC 50. This makes it possible to protect the transceiver IC 50 and prevent communication errors from occurring. Also, for example, even if strong magnetic field noise is induced in the harness 90 connected to the first input/output terminal 11 and the second input/output terminal 12, and large amplitude current/voltage noise is input to the electronic control device 1, the first varistor element ZNR1 and the second varistor element ZNR2 do not generate a reverse recovery current like the Zener diode shown in Comparative Example 1, so that communication errors can be prevented from occurring.

The electronic control device 1A further includes a first varistor element ZNR1 provided on a first ground line 31 connecting the first line 21 and ground G, and a second varistor element ZNR2 provided on a second ground line 32 connecting the second line 22 and ground G, and the first capacitance CP1 may be the capacitance of the first varistor element ZNR1, and the second capacitance CP2 may be the capacitance of the second varistor element ZNR2.

In this way, by providing the electronic control device 1A with the first varistor element ZNR1 and the second varistor element ZNR2, for example, even if a large current flows through the first line 21 and the second line 22, the current can be prevented from flowing into the transceiver IC 50. This makes it possible to protect the transceiver IC 50 and prevent communication errors from occurring. Also, for example, even if strong magnetic field noise is induced in the harness 90 connected to the first input/output terminal 11 and the second input/output terminal 12 and a large amplitude current/voltage noise is input to the electronic control device 1, the first varistor element ZNR1 and the second varistor element ZNR2 do not generate a reverse recovery current like the Zener diode shown in Comparative Example 1, so that communication errors can be prevented from occurring. Also, since no capacitor element is provided, the electronic control device 1 can be made smaller.

The first varistor element ZNR1 and the second varistor element ZNR2 may also be provided in one laminated varistor component 40.

This makes it possible to reduce the difference in capacitance between the first varistor element ZNR1 and the second varistor element ZNR2. This makes it possible to reduce the difference in capacitance between the first line 21 and ground G and between the second line 22 and ground G. This makes it possible to prevent a common mode noise signal input to the electronic control device 1B from being converted into a differential mode noise signal by the first varistor element ZNR1 and the second varistor element ZNR2. This makes it possible to prevent communication errors from occurring in the electronic control device 1B.

The laminated varistor component 40 may also include a first signal terminal 41 which is one terminal of the first varistor element ZNR1 and connected to the first line 21, a second signal terminal 42 which is one terminal of the second varistor element ZNR2 and connected to the second line 22, and a ground terminal 43 which is a common terminal in which the other terminal of the first varistor element ZNR1 and the other terminal of the second varistor element ZNR2 are commonized and connected to ground G.

This makes it possible to equalize the ground potential of the first varistor element ZNR1 and the second varistor element ZNR2 and reduce the difference in capacitance. This makes it possible to reduce the difference in capacitance between the first line 21 and ground G and between the second line 22 and ground G. This makes it possible to prevent a common mode noise signal input to the electronic control device 1B from being converted into a differential mode noise signal by the first varistor element ZNR1 and the second varistor element ZNR2. This makes it possible to prevent communication errors from occurring in the electronic control device 1B.

Furthermore, the difference between the first capacitance CP1 and the second capacitance CP2 may be 10% or less.

This reduces the amount of common mode noise signal input to the electronic control device 1 that is converted into a differential mode noise signal by the first varistor element ZNR1 and the second varistor element ZNR2. This makes it possible to prevent communication errors from occurring in the electronic control device 1.

In addition, no common mode noise filter is provided between the first input/output terminal 11 and the second input/output terminal 12 and the transceiver IC 50.

This configuration makes it possible to prevent the occurrence of back electromotive force by the common mode choke coil. This makes it possible to prevent communication errors from occurring in the electronic control device 1. In addition, because a common mode choke coil is not provided, the electronic control device 1 can be made smaller.

(Embodiment 2)
[Configuration of electronic control device]
The configuration of an electronic control device 1C according to a second embodiment will be described with reference to Figures 11 to 13. In the second embodiment, an example will be described in which a region that suppresses the passage of common mode noise signals is provided in a part of a multilayer substrate 500 constituting the electronic control device 1C.

Figure 11 is a plan view showing an electronic control device 1C according to embodiment 2. Note that in Figure 11, signal lines are represented by line segments.

As shown in FIG. 11, the electronic control device 1C includes a connector 10, a transceiver IC 50, a microprocessor 60, and a protection circuit 5B (see FIG. 10). The electronic control device 1C also includes a first line 21 and a second line 22 that are differential signal lines 20, and a control signal line 25. The first line 21 is a line that connects the first input/output terminal 11 of the connector 10 and the transceiver IC 50. The second line 22 is a line that connects the second input/output terminal 12 of the connector 10 and the transceiver IC 50. The control signal line 25 is a line that connects the transceiver IC 50 and the microprocessor 60.

The electronic control device 1C also includes a multi-layer substrate 500. The differential signal lines 20 are formed on the multi-layer substrate 500. The connector 10, the transceiver IC 50, the microprocessor 60, and the protection circuit 5B are mounted on the multi-layer substrate 500. The protection circuit may be the protection circuit 5A shown in FIG. 9 or the protection circuit 5 shown in FIG. 2.

Figure 12 is a plan view showing a portion of the multilayer substrate 500 of the electronic control device 1C. Figure 13 is a cross-sectional view showing a portion of the multilayer substrate 500 of the electronic control device 1C. Figure 12 shows part C, which is a portion of the multilayer substrate 500 shown in Figure 11. Figure 13 (a) shows a cross section of the multilayer substrate 500 taken along line XIIIa-XIIIa in Figure 12, and Figure 13 (b) shows a cross section of the multilayer substrate 500 taken along line XIIIb-XIIIb in Figure 12.

The multilayer board 500 shown in Figs. 12 and 13 has a laminated structure in which a plurality of dielectric layers 510 and a plurality of conductor layers 530 are laminated. The multilayer board 500 has a first line 21 and a second line 22, which are differential signal lines 20. Fig. 13 shows an example in which the multilayer board 500 has three dielectric layers 510 and two conductor layers 530, but is not limited thereto, and the multilayer board 500 may have four or more dielectric layers 510 and three or more conductor layers 530. The multilayer board 500 may have another wiring layer 535 different from the first line 21 and the second line 22.

Here, the line width direction of the first line 21 and the second line 22 is the first direction d1, the direction in which the first line 21 and the second line 22 extend is the second direction d2, and the direction perpendicular to both the first direction d1 and the second direction d2 is the third direction d3. The third direction d3 is a direction perpendicular to the multilayer substrate 500.

The dielectric layer 510 is a layer containing a dielectric material. As shown in FIG. 13, the multiple dielectric layers 510 include a dielectric layer 511 which is the top layer of the multilayer substrate 500, a dielectric layer 512 which is an intermediate layer, and a dielectric layer 513 which is the bottom layer. Note that the multilayer substrate 500 may have other dielectric layers different from the dielectric layers 511 to 513. The number of dielectric layers in the multilayer substrate 500 is not limited to three layers, and may be four or more layers.

The conductor layer 530 is a layer containing a conductive material such as a metal. The conductor layer 530 is, for example, an electrode having a planar pattern shape. As shown in FIG. 13, the multiple conductor layers 530 include a conductor layer 531 disposed between the dielectric layer 511 and the dielectric layer 512, and a conductor layer 532 disposed between the dielectric layer 512 and the dielectric layer 513. Of the multiple conductor layers 530, the conductor layer 531 is the conductor layer closest to the differential signal line 20, and the conductor layer 532 is the conductor layer second closest to the differential signal line 20.

The conductor layer 531 is a ground conductor layer that is set to ground potential. The conductor layer 531 is connected to the other terminal of the first varistor element ZNR1 and the other terminal of the second varistor element ZNR2, for example, through a via conductor (not shown) provided in the dielectric layer 510. The conductor layer 532 is a power supply conductor layer that supplies power to the transceiver IC 50 and the microprocessor 60. The conductor layer 532 is connected to the transceiver IC 50 and the microprocessor 60, for example, through another via conductor (not shown) provided in the dielectric layer 510.

Here, when viewed from both main surfaces of the dielectric layer 510, the main surface located on the side of the differential signal line 20 is called one main surface of the dielectric layer 510, and the main surface located on the opposite side to the differential signal line 20 is called the other main surface of the dielectric layer 510. The above-mentioned conductor layer 531 is provided on a part of the other main surface 511b of the dielectric layer 511 and on a part of one main surface 512a of the dielectric layer 512. The conductor layer 532 is provided on a part of the other main surface 512b of the dielectric layer 512 and on a part of one main surface 513a of the dielectric layer 513.

The multilayer substrate 500 of this embodiment has regions T2 and T3 where the conductor layer 530 is not formed directly below a region T1 of the differential signal line 20. Directly below the differential signal line 20 refers to at least the range from one main surface 511a of the dielectric layer 511 to one main surface 512a of the dielectric layer 512. Note that directly below the differential signal line 20 may also include the range from one main surface 512a of the dielectric layer 512 to one main surface 513a of the dielectric layer 513.

The partial region T1 of the differential signal line 20 is located on the input side of the transceiver IC 50, i.e., on the path connecting the connector 10 and the transceiver IC 50. Specifically, the partial region T1 of the differential signal line 20 is provided between the transceiver IC 50 and a node n1 (see FIG. 10) of the first line 21 to which one end of the first varistor element ZNR1 is connected, and between the transceiver IC 50 and a node n2 of the second line 22 to which one end of the second varistor element ZNR2 is connected. In the partial region T1 of the differential signal line 20, the first line 21 and the second line 22 are arranged parallel to each other.

The regions T2 and T3 where the conductor layer 530 is not formed are formed, for example, by etching. The regions T2 and T3 where the conductor layer 530 is not formed are rectangular when viewed from the third direction d3. The width of the regions T2 and T3 along the first direction d1 is a length that includes at least the width of the first line 21, the width of the second line 22, and the distance (gap) between the first line 21 and the second line 22. The length of the regions T2 and T3 along the second direction d2 is predetermined by the pass stop band of the high-frequency signal. The length of the regions T2 and T3 is, for example, 0.5 times or more and 2 times or less than the width of the regions T2 and T3. When viewed from the third direction d3, the regions T2 and T3 where the conductor layer 530 is not formed and the region T1, which is a part of the differential signal line 20, overlap each other.

In the other main surface 511b of the dielectric layer 511, in a region T2 corresponding to the region T1, the conductor layer 531 is not formed, and in a peripheral region o2 located on the outer periphery of the region T2, the conductor layer 531 is provided. The region T2 is provided with a dielectric layer 512. Note that a part of the dielectric layer 512 and a part of the dielectric layer 511 may be embedded in the region T2.

In the other main surface 512b of the dielectric layer 512, a conductor layer 532 is not provided in a region T3 corresponding to the region T1, and a conductor layer 532 is provided in a peripheral region o3 located on the periphery of the region T3. A dielectric layer 513 different from the dielectric layer 512 is provided in the region T3. Note that a part of the dielectric layer 513 and a part of the dielectric layer 512 may be embedded in the region T3.

In this manner, in the multilayer substrate 500 of the present embodiment, regions T2 and T3 in which the conductor layer 530 is not formed are provided directly below the region T1 of the differential signal line 20. With this configuration, the common mode impedance can be increased in the region T1 of the differential signal line 20, and the passage of a common mode noise signal can be suppressed. The effects of the multilayer substrate 500 having the above configuration will be described below.

[Effects, etc.]
The effects of the multilayer substrate 500 included in the electronic control device 1C of the second embodiment will be described while comparing a working example, which is one example of the second embodiment, with a third comparative example.

Figure 14 is a plan view showing a multilayer substrate 500 according to an embodiment of the present invention, which is an example of the second embodiment. Figure 15 is a cross-sectional view showing the multilayer substrate 500 according to the embodiment. Figure 15(a) shows a cross-section of the multilayer substrate 500 taken along line XVa-XVa in Figure 14, and Figure 15(b) shows a cross-section of the multilayer substrate 500 taken along line XVb-XVb in Figure 14.

The multilayer substrate 500 of the embodiment includes a dielectric layer 511 and a conductor layer 530. The first line 21 and the second line 22 are provided on one main surface 511a of the dielectric layer 511. The conductor layer 530 is provided on a portion of the other main surface 511b of the dielectric layer 511.

The thickness of the dielectric layer 511 is 0.1 mm. The relative dielectric constant of the dielectric layer 511 is 4.2, and the dielectric tangent is 0.019. The thickness of each of the first line 21 and the second line 22 is 18 μm, the width (length in the first direction d1) is 0.1 mm, and the length in the second direction d2 is 10 mm. The distance between the first line 21 and the second line 22 is 0.1 mm.

The multilayer substrate 500 of the embodiment has a region T2 where the conductor layer 530 is not formed. The region T2 is rectangular, the width (length in the first direction d1) of the region T2 is 1.0 mm, and the length in the second direction d2 of the region T2 is 2.0 mm. The region T2 is provided directly below the region T1 of a part of the differential signal line 20. The conductor layer 530 is provided in the region o2 located on the outer periphery of the region T2. The resist 520 is formed on the other main surface 511b of the dielectric layer 511 in the region T2. Although FIG. 15 illustrates a state in which the resist 520 is formed only in the region T2, in reality, the resist is formed on the entire surface of the multilayer substrate 500 (not shown). For example, the resist has a thickness of 20 μm, a relative dielectric constant of 4.2, and a dielectric loss tangent of 0.019.

Next, we will explain the multilayer board 1500 provided in the electronic control device of Comparative Example 3.

Figure 16 is a plan view showing multilayer substrate 1500 of Comparative Example 3. Figure 17 is a cross-sectional view showing multilayer substrate 1500 of Comparative Example 3. Figure 17(a) shows a cross section of multilayer substrate 1500 taken along line XVIIa-XVIIa shown in Figure 16, and Figure 17(b) shows a cross section of multilayer substrate 1500 taken along line XVIIb-XVIIb shown in Figure 16.

The multilayer substrate 1500 of Comparative Example 3 includes a dielectric layer 511 and a conductor layer 1530. The first line 21 and the second line 22 are provided on one main surface 511a of the dielectric layer 511. The conductor layer 1530 is provided on the other main surface 511b of the dielectric layer 511. The multilayer substrate 1500 of Comparative Example 3 does not have a region T2 where the conductor layer 530 is not formed. That is, in Comparative Example 3, the conductor layer 1530 is formed on the entire surface of the other main surface 511b of the dielectric layer 511. Note that in Comparative Example 3 as well, a resist is formed on the entire surface of the multilayer substrate 500 (not shown).

Figure 18 shows the transmission characteristics of differential mode signals in the multilayer boards of the example and comparative example 3. The horizontal axis of the figure is the frequency of the differential mode signal. The vertical axis of the figure is Sdd21 of the differential mode signal, and indicates that the signal transmission is more suppressed toward the bottom.

As shown in FIG. 18, in the embodiment, the transmission characteristics of the differential mode signal are equivalent to those of Comparative Example 3. Even when the region T2 where the conductor layer 530 is not formed is provided in the multilayer substrate 500 as in the embodiment, the transmission characteristics of the differential mode signal are hardly deteriorated. Note that, if Sdd21 is to be equal to or greater than that of Comparative Example 3, it is necessary to adjust the width and spacing of the first line 21 and the second line 22 according to the relative dielectric constant, dielectric loss tangent, and thickness of the dielectric layer 510 used in the multilayer substrate 500, and the thickness of the conductor layer.

Figure 19 shows the common mode signal passing characteristics of the multilayer boards of the example and comparative example 3. The horizontal axis of the figure is the frequency of the common mode signal. The vertical axis of the figure is the Scc21 of the common mode signal, and indicates that the passage of the signal is more suppressed toward the bottom.

As shown in FIG. 19, in the embodiment, the passage of signals is suppressed, for example, in frequency bands of 2 GHz to 10 GHz and 13 GHz or higher, compared to Comparative Example 3. By utilizing this passing characteristic, it is possible to block the passage of common mode noise signals, for example, in frequency bands of 2 GHz to 10 GHz and 13 GHz or higher. The noise signal blocking band can be adjusted by using a dielectric having a relative dielectric constant or dielectric tangent different from that of the dielectric 510 used in this embodiment for the multilayer substrate 500, or by changing the length of region T2.

According to the electronic control device 1C equipped with the multilayer substrate 500 of the embodiment, even if the protection circuit 5B cannot completely remove the common mode noise signal, a portion of the multilayer substrate 500 can be used to suppress the passage of the common mode noise signal. This makes it possible to suppress communication errors from occurring in the electronic control device 1C.

[First Modification of the Second Embodiment]
A configuration of an electronic control device 1C according to a first modification of the second embodiment will be described. In this first modification, an example will be described in which a conductor layer 530 is not provided directly below the differential signal lines 20 but is provided at a position away from the differential signal lines 20.

Figure 20 is a cross-sectional view showing a portion of a multilayer substrate 500A of an electronic control device 1C according to Variation 1 of Embodiment 2.

The multilayer substrate 500A of the first modification has a laminated structure in which a plurality of dielectric layers 510 and a plurality of conductor layers 530 are laminated. The multilayer substrate 500A has a first line 21 and a second line 22, which are differential signal lines 20, formed therein.

The multilayer substrate 500A of the first modified example also has regions T2 and T3 directly below a portion of the differential signal line 20, region T1, where the conductor layer 530 is not formed.

The multilayer substrate 500A of the first modified example is provided with a conductor layer 533 in a region further away from directly below the region T1 of the differential signal line 20. The region further away from directly below the differential signal line 20 is, for example, a position further away from the other main surface 513b of the dielectric layer 513. The conductor layer 533 is provided on the other main surface 513b of the dielectric layer 513, which is the bottom layer of the multilayer substrate 500A. The conductor layer 533 is, for example, a conductor layer for grounding.

Even in the multilayer substrate 500A of the first modification, regions T2 and T3 in which the conductor layer 530 is not formed are provided directly below a portion of region T1 of the differential signal line 20. With this configuration, the common mode impedance can be increased in the differential signal line 20, and the passage of common mode noise signals can be suppressed. This makes it possible to suppress the occurrence of communication errors in the electronic control device 1C.

[Modification 2 of the Second Embodiment]
A configuration of an electronic control device 1C according to a second modification of the second embodiment will be described. In this second modification, an example will be described in which the differential signal lines 20 are meander wiring.

Figure 21 is a plan view showing a portion of the multilayer board 500B of the electronic control device 1C according to the second modification of the second embodiment.

The multilayer substrate 500B of the second modification also has a layered structure in which a plurality of dielectric layers 510 and a plurality of conductor layers 530 are layered. The multilayer substrate 500B has a first line 21 and a second line 22, which are the differential signal line 20. Each of the first line 21 and the second line 22 has a meandering shape in a region T1 of the differential signal line 20. The meandering shape may be a triangular wave, a square wave, or a sine wave.

In the multilayer board 500B of the second modification, regions T2 and T3 in which the conductor layer 530 is not formed are provided directly below a region T1 of the differential signal line 20. In addition, in the second modification, the first line 21 and the second line 22 have a meandering shape, so that the length of each line can be increased and the common mode impedance can be increased. This makes it possible to suppress the passage of common mode noise signals and suppress the occurrence of communication errors in the electronic control device 1C.

[Summary of the second embodiment]
The electronic control device 1C according to the second embodiment further includes a multilayer substrate 500 having a plurality of dielectric layers 510 and a plurality of conductor layers 530. The multilayer substrate 500 is provided with a differential signal line 20 including a first line 21 and a second line 22. The multilayer substrate 500 has a region T2 where the conductor layer 530 is not formed, directly below a region T1 of the differential signal line 20.

In this way, by providing a region T2 where the conductor layer 530 is not formed directly below a portion of the region T1 of the differential signal line 20, the common mode impedance can be increased in the portion of the region T1 of the differential signal line 20. This makes it possible to suppress the passage of common mode noise signals and suppress the occurrence of communication errors in the electronic control device 1C. In addition, since the passage of common mode noise signals can be suppressed without providing additional components such as a common mode choke coil, the electronic control device 1C can be made smaller.

The conductor layer 530 may also be formed in the region o2 on the outer periphery of the region T2 where the conductor layer 530 is not formed.

Accordingly, the conductor layer 530 can be used, for example, to apply a ground potential or supply power to electronic components mounted on the multilayer substrate 500.

In addition, a dielectric layer 510 may be provided in the region T2 where the conductor layer 530 is not formed.

In this way, by providing the dielectric layer 510 in the region T2 where the conductor layer 530 is not formed, the common mode impedance in the region T1 of the differential signal line 20 can be increased. This makes it possible to prevent common mode noise signals from passing through, and to prevent communication errors from occurring in the electronic control device 1C.

The conductor layer 530 provided in the outer peripheral region o2 may be a conductor layer for grounding or a conductor layer for power supply.

This makes it possible, for example, to apply a ground potential or supply power to electronic components mounted on the multilayer substrate 500.

In addition, a conductor layer 533 may be provided in a region further away from directly below the region T1 of the differential signal line 20.

As a result, the conductor layer 533 in an area further away from directly below the area T1 can be used to, for example, apply a ground potential or supply power to electronic components mounted on the multilayer substrate 500A.

Furthermore, each of the first line 21 and the second line 22 may have a meandering shape in a portion of the region T1 of the differential signal line 20.

In this way, by making the first line 21 and the second line 22 meandering, the line length of the first line 21 and the second line 22 can be increased, and the common mode impedance can be increased. This makes it possible to suppress the passage of common mode noise signals, and to suppress the occurrence of communication errors in the electronic control device 1C.

(Other embodiments, etc.)
Although the electronic control device according to the embodiment and each modification of the present disclosure has been described above, the present disclosure is not limited to the above-mentioned embodiment and each modification. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by a person skilled in the art to the embodiment and each modification, as well as other forms constructed by combining some of the components in the embodiment and each modification, are also included in the scope of the present disclosure.

The electronic control device according to the present disclosure is useful as an electronic control device used in various electronic devices and communication systems.

REFERENCE SIGNS LIST 1, 1A, 1B, 1C Electronic control device 5, 5A, 5B Protection circuit 10 Connector 11 First input/output terminal 12 Second input/output terminal 20 Differential signal line 21 First line 22 Second line 25 Control signal line 31 First ground line 32 Second ground line 33 Third ground line 34 Fourth ground line 40 Multilayer varistor component 41 First signal terminal 42 Second signal terminal 43 Ground terminal 50 Transceiver IC
60 Microprocessor 90 Harness 500, 500A, 500B Multilayer board 510, 511, 512, 513 Dielectric layer 511a, 512a, 513a One main surface 511b, 512b, 513b Other main surface 520 Resist 530, 531, 532, 533 Conductor layer 535 Wiring layer C1 First capacitor element C2 Second capacitor element CP1 First capacitance CP2 Second capacitance d1 First direction d2 Second direction d3 Third direction G Ground n1, n2, n3, n4 Node o2, o3 Outer periphery region T1, T2, T3 Region ZNR1 First varistor element ZNR2 Second varistor element

Claims (12)

a first input/output terminal and a second input/output terminal for inputting and outputting a differential signal;
a transceiver IC for transmitting and receiving the differential signal;
a first line connecting the first input/output terminal and the transceiver IC;
a second line connecting the second input/output terminal and the transceiver IC;
Equipped with
a first capacitance between the first line and ground is equal to or greater than 80 pF and equal to or less than 220 pF;
a second capacitance between the second line and the ground is equal to or greater than 80 pF and equal to or less than 220 pF;
moreover,
a first varistor element provided on a first ground line connecting the first line and the ground;
a second varistor element provided on a second ground line connecting the second line and the ground;
a first capacitor element connected in parallel to the first varistor element;
a second capacitor element connected in parallel to the second varistor element;
Equipped with
the first capacitance is a total capacitance of the first varistor element and the first capacitor element,
The second capacitance is a total capacitance of the second varistor element and the second capacitor element.
Electronic control unit. a first input/output terminal and a second input/output terminal for inputting and outputting a differential signal;
a transceiver IC for transmitting and receiving the differential signal;
a first line connecting the first input/output terminal and the transceiver IC;
a second line connecting the second input/output terminal and the transceiver IC;
Equipped with
a first capacitance between the first line and ground is equal to or greater than 80 pF and equal to or less than 220 pF;
a second capacitance between the second line and the ground is equal to or greater than 80 pF and equal to or less than 220 pF;
moreover,
a first varistor element provided on a first ground line connecting the first line and the ground;
a second varistor element provided on a second ground line connecting the second line and the ground;
Equipped with
the first capacitance is a capacitance of the first varistor element,
The second capacitance is the capacitance of the second varistor element.
Electronic control unit. 3. The electronic control device according to claim 1 , wherein the first varistor element and the second varistor element are provided in one laminated varistor component. The laminated varistor component comprises:
a first signal terminal which is one terminal of the first varistor element and is connected to the first line;
a second signal terminal which is one terminal of the second varistor element and is connected to the second line;
a common terminal which is a common terminal formed by combining the other terminal of the first varistor element and the other terminal of the second varistor element, and which is connected to the ground; and
The electronic control device according to claim 3 . 5. The electronic control device according to claim 1, wherein a difference between the first capacitance and the second capacitance is 10% or less. 6. The electronic control device according to claim 1 , wherein no common mode noise filter is provided between the first input/output terminal and the transceiver IC and between the second input/output terminal and the transceiver IC. The present invention further includes a multilayer substrate having a plurality of dielectric layers and a plurality of conductor layers,
a differential signal line including the first line and the second line is provided on the multilayer substrate;
7. The electronic control device according to claim 1, wherein the multilayer substrate has an area where the conductor layer is not formed immediately below a portion of the differential signal lines. The electronic control device according to claim 7 , wherein the conductor layer is formed in an area surrounding the area where the conductor layer is not formed. The electronic control device according to claim 8 , wherein the dielectric layer is provided in an area where the conductor layer is not formed. The electronic control device according to claim 8 or 9 , wherein the conductor layer provided in the outer peripheral region is a conductor layer for grounding or a conductor layer for power supply. The electronic control device according to claim 7, wherein the conductor layer is provided in an area spaced apart from directly below the partial area of the differential signal lines. 12. The electronic control device according to claim 7 , wherein each of the first line and the second line has a meandering shape in a partial region of the differential signal line.

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