JP7679066B2 - Signal processing circuit and electronic device - Google Patents

Description

The present invention relates to a signal processing circuit and an electronic device.

In general, wireless communication systems are configured to be limited to one of two types: for example, wireless communication systems such as automated ticket gate systems at stations and keyless entry systems are configured so that wireless communication is only possible when IC tickets or remote controls are in close proximity to automated ticket gates or cars, or as in other cases such as CDMA (Code Division Multiple Access) communication (see Patent Documents 1 and 2), where wireless communication is possible even when the devices are far apart.

Therefore, a wireless communication system has been proposed that can control the range in which wireless communication is possible, maintains good communication quality even when the communication distance varies, and enables high-quality communication even with weak power (see Patent Document 3). Patent Document 3 discloses a communication device that enables high-quality communication even with weak power by adding (integrating) multiple pieces of the same data.

U.S. Pat. No. 04,811,421 Patent No. 2653421 Patent No. 5247888

To enable high-quality communication even with weak power, the received signal needs to be amplified at the receiving end in order to recognize the contents of the signal.

The present invention has been made in consideration of the above points, and aims to provide a signal processing circuit and electronic device that appropriately amplifies a received signal at the receiving end.

In order to achieve the above object, a signal processing circuit according to one aspect of the present invention includes an analog signal processing section in which multiple analog signal processing circuits are connected in series, each of which includes a low-pass filter that passes an analog signal having a first frequency or less, a high-pass filter that passes the analog signal having a second frequency or more, a clamp circuit that limits the voltage of the analog signal to a predetermined range, and a low-noise amplifier that amplifies the analog signal.

The signal processing circuit may further include a comparator that compares the voltage of the analog signal output by the analog signal processing unit with a predetermined voltage.

The predetermined voltage may be 0 volts.

In order to achieve the above object, a wireless communication device according to another aspect of the present invention includes the above signal processing circuit.

The present invention provides a signal processing circuit and a wireless communication device that can appropriately amplify a received signal on the receiving side by connecting multiple analog signal processing circuits in series.

1 is a diagram illustrating a schematic configuration of a signal processing circuit according to an embodiment of the disclosed technique. 1 is a diagram illustrating a schematic configuration of a signal processing circuit according to an embodiment of the disclosed technique. 1 is a diagram illustrating a communication device in which a signal processing circuit according to an embodiment is used. FIG. 2 illustrates an example of a functional configuration of a communication device. 1A and 1B are diagrams illustrating a structure of a packet communicated by a communication device.

Below, an example of an embodiment of the present disclosure will be described with reference to the drawings. Note that the same reference symbols are used in each drawing to identify identical or equivalent components and parts. Also, the dimensional ratios in the drawings have been exaggerated for the convenience of explanation and may differ from the actual ratios.

Figure 1 is a diagram showing the schematic configuration of a signal processing circuit according to this embodiment.

The signal processing circuit shown in FIG. 1 is composed of an analog signal processing circuit 100 and a comparator 110.

The analog signal processing circuit 100 is composed of a high-pass filter (HPF) 101, a low-pass filter (LPF) 102, a clamp circuit 103, and a low-noise amplifier (LNA) 104. Note that in FIG. 1, the high-pass filter 101, the low-pass filter 102, the clamp circuit 103, and the low-noise amplifier 104 are connected in this order, but the connection order is not limited to this example.

High-pass filter 101 is a filter that passes analog signals below a predetermined first frequency and attenuates analog signals that exceed the first frequency. As shown in Figure 1, high-pass filter 101 consists of a resistor in parallel with the input signal and a capacitor in series with the input signal.

Low-pass filter 102 is a filter that passes analog signals with a predetermined second frequency or higher and attenuates analog signals with a frequency lower than the second frequency. As shown in FIG. 1, low-pass filter 102 is composed of a capacitor in parallel with the input signal and a resistor in series with the input signal.

The clamp circuit 103 is a circuit that limits the voltage of the analog signal to a predetermined range. As shown in FIG. 1, the clamp circuit 103 consists of a resistor in series with the input signal and a Zener diode in parallel with the input signal.

The low noise amplifier 104 is a circuit that amplifies an analog signal by a predetermined amount, and is primarily used to amplify weak analog signals.

The comparator 110 is a circuit that compares the voltage of the analog signal output from the analog signal processing circuit 100 with a predetermined reference voltage. The predetermined reference voltage is, for example, 0 volts.

In order to accurately detect the state of a weak analog signal, the low-noise amplifier 104 needs to have sufficient gain. If the analog signal is too small compared to the noise with an S/N ratio of -100db to -160db, the dynamic range required for the low-noise amplifier 104 is very large, and a minimum of 100db to 160db or more is required.

If the minimum voltage required by the comparator 110 is 1 μV, then the maximum noise is 100 V, and a typical low-noise amplifier 104 requires an amplifier with a power supply voltage of 100 V or more and a dynamic range of 160 db. It is extremely difficult to realize a low-noise amplifier 104 that meets these specified conditions.

Therefore, in this embodiment, a signal processing circuit is shown in which multiple analog signal processing circuits shown in FIG. 1 are connected in series. By connecting multiple analog signal processing circuits shown in FIG. 1 in series, it is possible to ensure a gain that is sufficient to detect small signals.

Figure 2 is a diagram showing the schematic configuration of a signal processing circuit according to an embodiment of the present invention.

The signal processing circuit shown in FIG. 2 is composed of an analog signal processing unit 10 and a comparator 110.

The analog signal processing unit 10 has a configuration in which multiple analog signal processing circuits 100 are connected in series. For example, if a gain of 160 db is required to output to the comparator 110 and a gain of 20 db can be obtained with one analog signal processing circuit 100, the analog signal processing unit 10 can obtain the desired gain by connecting eight analog signal processing circuits 100 in series.

Next, we will explain a communication device that uses the signal processing circuit shown in Figure 2.

Figure 3 shows communication devices 200A and 200B. The communication devices 200A and 200B shown in Figure 3 perform wireless communication with each other. The communication devices 200A and 200B according to this embodiment transmit a data packet to the other device, and the communication devices 200A and 200B that receive the data packet from the other device transmit one response packet to the other device.

In the following description, communication devices 200A and 200B may be collectively referred to simply as communication device 200. In addition, in the following description, in a wireless communication system using communication devices 200A and 200B, data packets and response packets are encoded and decoded based on the Manchester encoding method. Of course, the encoding method is not limited to this example.

Figure 4 is a diagram showing an example of the functional configuration of the communication device 200.

The communication device 200 is composed of a receiving antenna 201, a receiving circuit 202, an AD converter 203, a periodic integration circuit 210, a decoding/synchronization detection circuit 204, an error detection circuit 205, a receiving buffer 206, a periodic integration circuit 210, a clock recovery circuit 220, a transmitting buffer 221, an error detection code addition circuit 222, an encoding circuit 223, a DA converter 224, a transmitting circuit 225, and a transmitting antenna 226.

The receiving antenna 201 receives a transmission packet sent from a wireless communication partner. The transmission packet received by the receiving antenna 201 is sent to the receiving circuit 202.

The receiving circuit 202 performs reception processing on the transmission packets received by the receiving antenna 201, such as amplification processing and noise filtering processing to remove noise generated on the transmission path. The receiving circuit 202 sends the signal after the reception processing on the transmission packets to the AD converter 203.

The AD converter 203 converts the signal sent from the receiving circuit 202 into a digital signal. Specifically, the AD converter 203 outputs 1 if the signal exceeds a reference value, and outputs 0 if the signal does not meet the reference value.

The periodic integration circuit 210 performs periodic integration processing on the digital signal sent from the AD converter 203 and the digital signal sent from the encoding circuit 223. The periodic integration circuit 210 includes a plurality of registers 211, 213, an adder 212, and a selector 214.

The registers 211 and 213 are provided in a number corresponding to the number required for sampling the bits forming the data packet. Specifically, the digital signal sent from the AD converter 203 is sampled according to the number of registers 211, and the value at each sampling point is integrated in each of the multiple registers 211. In addition, the data sent from the encoding circuit 223 is sampled according to the number of registers 213, and the value at each sampling point is integrated in each of the multiple registers 213.

The adder 212 adds the digital signal sent from the AD converter 203 and the signal output from the final register 211 among the multiple registers 211, and outputs the result.

The decoding and synchronization detection circuit 204 decodes the signal output from the periodic integration circuit 210, detects a specific pattern, and achieves synchronization.

The error detection circuit 205 performs an error inspection process on the decoded signal. Specifically, if the data output from the decoding/synchronization detection circuit 204 satisfies a CRC (Cyclic Redundancy Check), the error detection circuit 205 determines that a correct data packet has been received, and if it does not satisfy the CRC, the error detection circuit 205 determines that a correct data packet has not been received.

The receiving buffer 206 buffers the data output from the error detection circuit 205 and outputs it to a control circuit (not shown) at a predetermined timing.

The clock recovery circuit 220 has an internal PLL (Phase Locked Loop) and supplies clocks to the decoding/synchronization detection circuit 204, the error detection circuit 205, the reception buffer 206, the periodic integration circuit 210, the transmission buffer 221, the error detection code addition circuit 222, and the encoding circuit 223.

The transmit buffer 221 buffers data from a control circuit (not shown).

The error detection code addition circuit 222 adds an error detection code to perform error detection in the communication device 200 of the communication partner.

The encoding circuit 223 Manchester encodes the data sent from the error detection code addition circuit 222 and sends it to the periodic integration circuit 210.

The DA converter 224 converts the data sent from the periodic integration circuit 210 into an analog signal.

The transmission circuit 225 performs signal processing on the analog signal sent from the DA converter 224.

The transmitting antenna 26 transmits the signal sent from the transmitting circuit 225.

Figure 5 shows the structure of a packet communicated by communication device 200.

The packet 300 shown in FIG. 5 is composed of a preamble section 301, a synchronization code section 302, a payload length section 303, a payload section 304, a CRC section 305, and a postamble section 306. The length of each block can be set to any length.

The preamble section 301 is a block that stores a code indicating the start of the packet 300.

The synchronization code section 302 is a block in which a synchronization code for synchronizing multiple packets 300 on the receiving side is stored. Note that a violation code that does not exist in the normal data stored in the payload section 304 may be used for the synchronization code. For example, data that is not used in a data conversion method such as the 8b/10b method may be used for the violation code.

The payload length section 303 is a block that stores information about the length of the following payload section 304.

The payload section 304 is a block in which data to be sent from the sender to the receiver is stored.

The CRC section 305 is a block where data for CRC on the receiving side is stored.

The postamble section 306 is a block that stores a code indicating the end of the packet 300.

The communication device 200 on the receiving side of the transmitting side according to this embodiment receives packets 300 in which the same data is stored in the payload section 304, and is therefore able to receive data with high quality even if the communication distance varies. Furthermore, the communication device 200 according to this embodiment enables high-quality communication even with weak power when transmitting the same data.

In addition, the signal processing circuit according to this embodiment can be used in the communication device 200 shown in FIG. 4 to ensure a gain sufficient to detect small signals.

The present invention can be applied to space communications, military communications, card payments, keyless entry systems and other civilian digital communications, as well as any other communications system.

REFERENCE SIGNS LIST 10 Analog signal processing unit 100 Analog signal processing circuit 101 High-pass filter 102 Low-pass filter 103 Clamp circuit 104 Low-noise amplifier 110 Comparator 200 Communication device 201 Receiving antenna 202 Receiving circuit 203 AD converter 204 Decoding/synchronization detection circuit 205 Error detection circuit 206 Receiving buffer 210 Periodic integration circuit 220 Clock recovery circuit 221 Transmission buffer 222 Error detection code addition circuit 223 Encoding circuit 224 DA converter 225 Transmission circuit 226 Transmission antenna

Claims (4)

a low pass filter that passes analog signals having a frequency equal to or lower than a first frequency;
a high-pass filter that passes the analog signal having a second frequency or higher;
a clamp circuit for limiting the voltage of the analog signal to a predetermined range;
a low noise amplifier for amplifying the analog signal;
A signal processing circuit comprising an analog signal processing section in which a plurality of analog signal processing circuits each comprising: The signal processing circuit according to claim 1, further comprising a comparator that compares the voltage of the analog signal output by the analog signal processing unit with a predetermined voltage. The signal processing circuit of claim 2, wherein the predetermined voltage is 0 volts. An electronic device comprising the signal processing circuit according to any one of claims 1 to 3.