JP7679654B2 - Semiconductor device and method for manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

2. Description of the Related Art Conventionally, semiconductor devices having a chip identification portion for identifying a chip have been known (see, for example, Japanese Patent Application Laid-Open No. 2003-233663).
Patent Document 1: Japanese Patent Application Laid-Open No. 9-45593

In the manufacture of semiconductor devices, it is preferable to reduce the number of steps.

In order to solve the above problem, one aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include an insulating film. The insulating film may be provided on the semiconductor substrate. The semiconductor device may include metal wiring. The metal wiring may be provided on the insulating film. The metal wiring may contain silicon elements. The semiconductor device may include a chip identification portion. The chip identification portion may be provided on the insulating film. The chip identification portion may be mainly composed of silicon elements.

The chip identification portion may be a collection of silicon particles. In the chip identification portion, each silicon particle may be separate. The silicon particles may be embedded in the upper surface of the insulating film.

The chip identification portion may include a metal element contained in the metal wiring. The height of the chip identification portion may be 60% or less of the height of the metal wiring.

The semiconductor device may include an adjacent portion. The adjacent portion may be provided adjacent to the metal wiring. The adjacent portion may be mainly composed of silicon elements. The height of the adjacent portion may be the same as the height of the chip identification portion.

The chip identification portion may include polycrystalline silicon. The chip identification portion may include amorphous silicon.

The semiconductor device may include a protective film. The protective film may cover the chip identification portion.

The height of the metal wiring may be 0.5 μm or more and 5 μm or less. The mass percentage concentration of silicon element contained in the metal wiring may be 0.5% or more and 10% or less.

In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include a step of forming an insulating film on a semiconductor substrate. The method for manufacturing a semiconductor device may include a step of forming a metal film containing silicon elements on the insulating film. The method for manufacturing a semiconductor device may include a step of etching the metal film to form metal wiring. The method for manufacturing a semiconductor device may include a step of etching silicon residue generated in the step of forming the metal wiring to form a chip identification portion.

In the step of forming the chip identification part, the chip identification part may be formed while the metal wiring is protected by resist.

In the step of forming the metal wiring, the metal film may be wet etched. In the step of forming the chip identification portion, the silicon residue may be dry etched.

Note that the above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions.

1 is a diagram showing an example of a semiconductor device 100 according to an embodiment of the present invention. 2A to 2C are diagrams illustrating a part of a manufacturing method of the semiconductor device 100. FIG. 2 is a diagram showing an example of a semiconductor device 200 according to another embodiment of the present invention. 2A to 2C are diagrams illustrating a part of a manufacturing method of the semiconductor device 200. FIG. 13 is a diagram showing an example of a semiconductor device 300 according to another embodiment of the present invention. FIG. 4 is a diagram showing an example of a semiconductor device 400 according to another embodiment of the present invention. FIG. 1 is a diagram showing an example of a semiconductor device 500 according to a comparative example. 1A to 1C are diagrams illustrating a part of a manufacturing method of the semiconductor device 500. 1A to 1C are diagrams illustrating a part of a manufacturing method of the semiconductor device 500.

The present invention will be described below through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements that have substantially the same function and configuration are given the same reference numerals to avoid repeated explanation, and elements that are not directly related to the present invention are not shown. Furthermore, in one drawing, elements that have the same function and configuration may be given the same reference numerals as a representative, and the reference numerals may be omitted for the others.

In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. Also, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Also, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

When terms such as "same" or "equal" are used in this specification, this may include cases in which there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

Figure 1 is a diagram showing an example of a semiconductor device 100 according to one embodiment of the present invention. In this example, the semiconductor device 100 includes a semiconductor substrate 10, an insulating film 20, metal wiring 30, and a chip identification section 40. In Figure 1, the configuration of the semiconductor device 100 other than the semiconductor substrate 10, the insulating film 20, the metal wiring 30, and the chip identification section 40 is omitted.

As an example, the semiconductor device 100 functions as a power conversion device such as an inverter. The semiconductor device 100 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), or a combination of these, such as an RC (Reverse Conducting)-IGBT, as well as a MOS transistor. As an example, the semiconductor device 100 functions as a pressure sensor. The semiconductor device 100 is not limited to these examples.

The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

The insulating film 20 is provided on the semiconductor substrate 10. The insulating film 20 may be a so-called interlayer insulating film. One example of the insulating film 20 is a silicon oxide film. The insulating film 20 may contain boron or phosphorus elements. The insulating film 20 may have a contact hole that connects the semiconductor substrate 10 and the metal wiring 30. The upper surface of the insulating film 20 is referred to as the upper surface 21.

The metal wiring 30 is a wiring that connects to the semiconductor substrate 10. The metal wiring 30 is provided on the insulating film 20. In this example, the metal wiring 30 is an aluminum silicon alloy (AlSi). That is, the metal wiring 30 contains silicon elements. The mass percentage concentration of the silicon elements contained in the metal wiring 30 is, for example, 0.5% or more and 1.5% or less. In this specification, the metal wiring 30 and the metal film are indicated by hatching. The upper surface of the metal wiring 30 is also referred to as the upper surface 31.

The chip identification section 40 may be patterned with identifiable characters, symbols, etc. when viewed from above. Identifiable characters, symbols, etc. include, for example, characters, regular shapes, straight lines, and curved lines. Specifically, the chip identification section 40 is patterned with numbers, etc., assigned to each semiconductor device 100 so that the multiple semiconductor devices 100 can be identified. For example, the chip identification section 40 may be patterned with numbers numbered for each semiconductor device 100. The chip identification section 40 may also be patterned with numbers assigned to each type of the multiple semiconductor devices 100. The chip identification section 40 may be patterned with numbers assigned to each performance of the multiple semiconductor devices 100. By providing the chip identification section 40, the multiple semiconductor devices 100 can be identified.

The chip identification portion 40 is provided on the insulating film 20. The chip identification portion 40 may be provided in an area where the metal wiring 30 is not provided. The chip identification portion 40 may be provided away from the metal wiring 30. The chip identification portion 40 is composed of silicon particles 44, which will be described later.

Figure 2 is a diagram illustrating a part of the manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 includes an insulating film forming step S101, a metal film forming step S102, a resist forming step S103 for metal wiring, a metal wiring forming step S104, a resist forming step S105 for a chip identification part, and a chip identification part forming step S106.

First, in the insulating film formation step S101, an insulating film 20 is formed on the semiconductor substrate 10. The insulating film 20 may be formed by wet chemical oxidation. The insulating film 20 may be formed by chemical vapor deposition. The insulating film 20 may be formed by thermal oxidation of silicon. The insulating film 20 may be formed by other known methods. Note that an IGBT, a MOS transistor, etc. may be formed on the semiconductor substrate 10 before the insulating film formation step S101.

Next, in the metal film formation step S102, a metal film 32 is formed on the upper surface 21 of the insulating film 20. In this example, the metal film 32 is formed by sputtering. As an example, the metal film 32 is an aluminum silicon alloy (AlSi). That is, the metal film 32 is formed of the same material as the metal wiring 30. The metal film 32 may contain silicon elements. The metal wiring 30 is formed by processing the metal film 32. The thickness of the formed metal film 32 may be 1.0 μm or less. As an example, the height (thickness) of the metal film 32 is 0.5 μm.

In the metal wiring resist formation step S103, photolithography is performed. That is, a pattern of resist 60 is formed on the upper surface 33 of the metal film 32. In the photolithography in the metal wiring resist formation step S103 in this example, a reduction mask is used. In this specification, a mask that reduces and exposes a mask pattern is referred to as a reduction mask. Specifically, the reduction mask is exposed with a lens reduction ratio of 5 times. That is, the mask pattern can be reduced to 1/5 and exposed. By using a reduction mask, fine metal wiring 30 can be formed. When a reduction mask is used, multiple exposures may be performed on the wafer-shaped semiconductor substrate 10.

In the metal wiring formation step S104, the metal wiring 30 is formed. In this example, the metal film 32 is etched to form the metal wiring 30. In this example, the metal film 32 is wet-etched in the metal wiring formation step S104. In this example, the solution used for the wet etching is acetic acid. The solution used for the wet etching is not limited to acetic acid. After the metal wiring 30 is formed, the resist 60 is removed.

The metal film 32 contains silicon elements. Therefore, by wet etching the metal film 32, silicon residues 42 are formed on the upper surface 21 of the insulating film 20. The silicon residues 42 are a collection of silicon particles 44. If silicon residues 42 remain on the upper surface 21 of the insulating film 20, they may connect the metal wirings 30 together and cause a short circuit between the metal wirings 30. Therefore, it is preferable to remove the silicon residues 42. The silicon residues 42 formed near the metal wirings 30 are referred to as silicon residues 42-1, and the silicon residues 42 in the region where the chip identification unit 40 is provided are referred to as silicon residues 42-2.

In the resist formation step S105 for chip identification parts, photolithography is performed. That is, a pattern of resist 62 is formed on silicon residue 42-2. In the photolithography in the resist formation step S105 for chip identification parts in this example, a normal mask is used. In this specification, a mask that is exposed with a lens reduction ratio of 1 is defined as a normal mask. Specifically, the normal mask is exposed with a lens reduction ratio of 1. That is, the mask pattern is exposed without being reduced. When a normal mask is used, a single exposure may be performed on the wafer-like semiconductor substrate 10. When a reduced mask is used, the chip recognition part is repeatedly formed for each exposure, so chip identification is not possible. By using a normal mask, individual chip recognition parts can be formed for multiple semiconductor devices 100 with a single exposure. In addition, in order to protect the metal wiring 30, a pattern of resist 62 is also formed on the upper surface 31 of the metal wiring 30. On the other hand, in order to remove the silicon residue 42-1, the pattern of resist 62 is not formed on the silicon residue 42-1.

Then, in chip identification part formation step S106, the chip identification part 40 is formed. In this example, the silicon residue 42-2 generated in the metal wiring formation step S104 is etched to form the chip identification part 40. In this example, in chip identification part formation step S106, the silicon residue 42-2 is dry etched. Dry etching is performed using, for example, a gas or plasma containing fluorine or chlorine. Dry etching may be performed by a known method. After the chip identification part 40 is formed, the resist 62 is removed.

In the chip identification part formation step S106, the chip identification part 40 is formed while the metal wiring 30 is protected by the resist 62. By protecting the metal wiring 30 with the resist 62, damage to the metal wiring 30 caused by dry etching can be suppressed. In addition, since the pattern of the resist 62 is not formed on the silicon residue 42-1, the silicon residue 42-1 can be removed.

In this example, in chip identification part formation step S106, the chip identification part 40 is formed using silicon residue 42-2. Therefore, the formation of the chip identification part 40 and the removal of silicon residue 42-1 between the metal films 32 can be performed in the same process. This allows the number of processes to be reduced. In other words, in the process of removing silicon residue 42-1 between the metal wiring 30, the chip identification part 40 can be formed using silicon residue 42-2.

After the chip identification part formation step S106, the metal wiring 30 may be activated by heat treatment. In addition, a passivation film such as an interlayer insulating film, a metal film, or a polyimide film may be provided separately on the metal wiring 30.

The chip identification section 40 is formed by the silicon residue 42-2. Therefore, the chip identification section 40 is mainly composed of silicon elements. The main component of the chip identification section 40 may be silicon elements at 50% or more of the mass percent concentration of the chip identification section 40. The main component of the chip identification section 40 may be silicon elements at 90% or more of the mass percent concentration of the chip identification section 40. Furthermore, the main component of the chip identification section 40 may be silicon elements at 95% or more of the mass percent concentration of the chip identification section 40. In this example, the chip identification section 40 is a collection of silicon particles 44. In other words, the chip identification section 40 is formed almost entirely of silicon elements. As shown in FIG. 1, each silicon particle 44 is separated. Some silicon particles 44 may be in contact with other silicon particles 44.

The chip identification portion 40 may also contain a metal element contained in the metal wiring 30. In this example, the chip identification portion 40 may contain an aluminum element. As another example, the chip identification portion 40 may contain a copper element or other metal element that constitutes the metal wiring. The chip identification portion 40 is formed from silicon residue 42-2, and therefore contains a metal element contained in the metal wiring 30.

The chip identification section 40 may contain polycrystalline silicon (polysilicon). That is, the silicon residue 42 may contain polycrystalline silicon. The chip identification section 40 may contain amorphous silicon (non-crystalline silicon). That is, the silicon residue 42 may contain amorphous silicon. Even if the silicon residue 42 is polycrystalline silicon or amorphous silicon, the chip identification section 40 can be formed by appropriate etching. Furthermore, the formed silicon residue 42 may contain oxygen by being oxidized in a later process or oxidized at room temperature.

Also, as shown in FIG. 1, the height T1 of the silicon residue 42 is smaller than the height T2 of the metal wiring 30. That is, the height T1 of the chip identification portion 40 may be smaller than the height T2 of the metal wiring 30. Here, the height T1 of the chip identification portion 40 may be the maximum height of the chip identification portion 40. Also, the height T2 of the metal wiring 30 may be the maximum height of the metal wiring 30. The height T1 of the chip identification portion 40 may be 60% or less of the height T2 of the metal wiring 30. The height T1 of the chip identification portion 40 may be 10% or less of the height T2 of the metal wiring 30. The height T1 of the chip identification portion 40 may be 5% or less of the height T2 of the metal wiring 30. The height T1 of the chip identification portion 40 may be 1% or less of the height T2 of the metal wiring 30. Since the chip identification portion 40 is formed of the silicon residue 42, the height T1 of the chip identification portion is smaller than the height T2 of the metal wiring 30.

In this example, the height T2 of the metal film 32 (i.e., the metal wiring 30) is described as 0.5 μm, but the height of the metal wiring 30 may be 1 μm or more. By increasing the height T2 of the metal wiring 30, the height T1 of the silicon residue 42 formed can be increased. By increasing the height T1 of the silicon residue 42, it becomes easier to recognize the chip identification portion 40. In this case, it is preferable that the height T2 of the metal wiring 30 is 5 μm or less.

In this example, the mass percent concentration of silicon elements contained in the metal wiring 30 is described as being 0.5% or more and 1.5% or less, but the mass percent concentration of silicon elements contained in the metal wiring 30 may be 2% or more. By increasing the mass percent concentration of silicon elements contained in the metal wiring 30, the height T1 of the silicon residue 42 formed can be increased. Therefore, it becomes easier to recognize the chip identification portion 40. Furthermore, if the mass percent concentration of silicon elements contained in the metal wiring 30 is made too large, the characteristics of the metal wiring 30 may deteriorate. Therefore, it is preferable that the mass percent concentration of silicon elements contained in the metal wiring 30 be 10% or less.

Figure 3 is a diagram showing an example of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 in Figure 3 differs from the semiconductor device 100 in Figure 1 in that it includes an adjacent portion 50. Other configurations of the semiconductor device 200 in Figure 3 may be the same as those of the semiconductor device 100 in Figure 1. Note that, for the sake of explanation, in the semiconductor device 200 in Figure 3, a portion of the metal wiring 30 is omitted from the semiconductor device 100 in Figure 1.

In the step S105 of forming a resist for the chip identification part in FIG. 2, it has been explained that the pattern of resist 62 is formed on the upper surface 31 of the metal wiring 30, and the pattern of resist 62 is not formed on the silicon residue 42-1. The metal wiring 30 is a fine pattern formed using a reduced mask, and if the pattern of resist 62 is provided only on the upper surface 31 of the metal wiring 30 using a normal mask in the step S105 of forming a resist for the chip identification part, there is a possibility that the pattern of resist 62 will be misaligned. If the pattern of resist 62 is misaligned, the metal wiring 30 will be damaged during etching. Therefore, it is preferable that the resist 62 is also provided on the silicon residue 42-1 adjacent to the metal wiring 30.

In this example, the adjacent portion 50 is provided adjacent to the metal wiring 30. The adjacent portion 50 is preferably provided within a range where the distance from the metal wiring 30 is 5 μm or less. In other words, the longest distance D1 between the adjacent portion 50 and the metal wiring 30 closest to the adjacent portion 50 is 5 μm or less. In this case, even if the distance D2 between the metal wirings 30 is 10 μm, for example, the adjacent portions 50 will not be connected to each other, and it is possible to prevent short circuits between the metal wirings 30.

The adjacent portion 50 may be formed by the same process as the chip identification portion 40. That is, the adjacent portion 50 may also be formed from silicon residue 42. Therefore, the adjacent portion 50 may be mainly composed of silicon element. That is, the adjacent portion 50 may be a collection of silicon particles 44.

The height T3 of the adjacent portion 50 may be the same as the height T1 of the chip identification portion. The height T3 of the adjacent portion 50 may be the maximum height of the adjacent portion 50. The height T3 of the adjacent portion 50 and the height T1 of the chip identification portion being the same may include an error of 50% or more.

Figure 4 is a diagram illustrating a part of the manufacturing method of the semiconductor device 200. Figure 4 shows another example of the resist formation step S105 for the chip identification portion in Figure 2.

In this example, unlike the resist formation step S105 for the chip identification portion in FIG. 2, the resist 62 is also formed on the silicon residue 42-1 adjacent to the metal wiring 30. By forming the resist 62 in this manner, the adjacent portion 50 can be provided.

Figure 5 is a diagram showing an example of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 in Figure 5 differs from the semiconductor device 100 in Figure 1 in that silicon particles 44 penetrate into the upper surface 21 of the insulating film 20. Other configurations of the semiconductor device 300 in Figure 5 may be the same as those of the semiconductor device 100 in Figure 1.

In this example, the silicon particles 44 penetrate into the upper surface 21 of the insulating film 20. As in this example, all of the silicon particles 44 forming the chip identification portion 40 may penetrate into the upper surface 21 of the insulating film 20. A portion of the silicon particles 44 forming the chip identification portion 40 may penetrate into the upper surface 21 of the insulating film 20, and another portion of the silicon particles 44 may be provided on the upper surface 21 of the insulating film 20 as shown in FIG. 1.

FIG. 6 is a diagram showing an example of a semiconductor device 400 according to another embodiment of the present invention. The semiconductor device 400 in FIG. 6 differs from the semiconductor device 100 in FIG. 1 in that it includes a protective film 70 that covers the chip identification unit 40. Other configurations of the semiconductor device 400 in FIG. 6 may be the same as those of the semiconductor device 100 in FIG. 1.

In this example, the semiconductor device 400 includes a protective film 70 that covers the chip identification portion 40. The protective film 70 may cover the insulating film 20 and the metal wiring 30. The protective film 70 may include an opening that exposes a bonding pad portion (not shown) that is electrically connected to the metal wiring 30. The protective film 70 may be a polyimide film or the like. By including the protective film 70, the chip identification portion 40 can be protected. The protective film 70 may have projections and recesses that follow the shape of the chip identification portion 40. Furthermore, by including the protective film 70, the visibility of the chip identification portion 40 can be improved.

FIG. 7 is a diagram showing an example of a semiconductor device 500 according to a comparative example. The semiconductor device 500 in FIG. 7 differs from the semiconductor device 100 in FIG. 1 in that the chip identification portion 80 is formed of a metal film 32 (the chip identification portion 80 is shown hatched). Other configurations of the semiconductor device 500 in FIG. 7 may be the same as those of the semiconductor device 100 in FIG. 1.

8 and 9 are diagrams for explaining a part of the manufacturing method of the semiconductor device 500. The manufacturing method of the semiconductor device 500 includes an insulating film forming step S201, a metal film forming step S202, a resist forming step S203 for metal wiring, a metal wiring forming step S204, a resist forming step S205 for a chip identification part, a chip identification part forming step S206, a resist forming step S207 for removing silicon residue, and a silicon residue removing step S208. FIG. 8 shows an insulating film forming step S201, a metal film forming step S202, a resist forming step S203 for metal wiring, and a metal wiring forming step S204. FIG. 9 also shows a resist forming step S205 for a chip identification part, a chip identification part forming step S206, a resist forming step S207 for removing silicon residue, and a silicon residue removing step S208.

The insulating film formation step S201 of FIG. 8 may be the same as the insulating film formation step S101 of FIG. 2. The metal film formation step S202 of FIG. 8 may be the same as the metal film formation step S102 of FIG. 2.

In the metal wiring resist formation step S203 of FIG. 8, photolithography is performed. That is, a pattern of resist 60 is created on the upper surface 33 of the metal film 32. In the photolithography in the metal wiring resist formation step S203 of this example, a reduction mask is used. By using a reduction mask, fine metal wiring 30 can be formed. Also, in this example, unlike the metal wiring resist formation step S103 of FIG. 2, the area where the chip identification part 80 is to be formed is also covered with resist 60.

In the metal wiring formation step S204 of FIG. 8, the metal wiring 30 is formed. In this example, the metal film 32 is etched to form the metal wiring 30. In this example, the metal film 32 is wet-etched in the metal wiring formation step S204. In this example, the solution used for the wet etching is acetic acid. The solution used for the wet etching is not limited to acetic acid. Also, in this example, unlike the metal wiring formation step S104 of FIG. 2, the metal film 32 is also provided in the area where the chip identification section 80 is to be formed. In this example, the metal film 32 in the area where the chip identification section 80 is to be formed is referred to as metal film 32-1. Note that after the metal wiring 30 is formed, the resist 60 is removed.

In the chip identification part resist formation step S205 in FIG. 9, photolithography is performed. In this example, a resist 62 pattern is formed on the upper surface 33 of the metal film 32-1. In this example, a mask is normally used for the photolithography in the chip identification part resist formation step S205. In addition, to protect the metal wiring 30, a resist 62 pattern is also created on the upper surface 31 of the metal wiring 30.

Then, in the chip identification part formation step S206 of FIG. 9, the chip identification part 80 is formed. In this example, similar to the metal wiring formation step S204, the metal film 32-1 is etched to form the metal wiring 30. In this example, in the metal wiring formation step S206, the metal film 32-1 is wet-etched. In this example, the solution used for the wet etching is acetic acid. The solution used for the wet etching is not limited to acetic acid. After the chip identification part 80 is formed, the resist 62 is removed.

In the step S207 of forming a resist for the chip identification part in FIG. 9, photolithography is performed. In this example, a pattern of resist 64 is formed on the upper surface 31 of the metal wiring 30 and the upper surface 41 of the chip identification part 80. In the photolithography in the step S207 of forming a resist for the chip identification part in this example, a normal mask or a reduced mask is used.

In the silicon residue removal step S208, the silicon residue 42 generated in the metal wiring formation step S204 and the chip identification portion formation step S206 is etched. In this example, in the silicon residue removal step S208, the silicon residue 42 is dry etched. Dry etching is performed using, for example, a gas or plasma containing fluorine or chlorine. Dry etching may be performed by a known method.

Comparing the manufacturing method of semiconductor device 100 and the manufacturing method of semiconductor device 500, the manufacturing method of semiconductor device 500 has a greater number of steps. This is because the manufacturing method of semiconductor device 500 performs two photolithography steps to perform chip identification portion formation step S206 and silicon residue removal step S208. On the other hand, in the manufacturing method of semiconductor device 100, in chip identification portion formation step S106, the formation of chip identification portion 40 and the removal of silicon residue 42 are performed in the same step. Therefore, it is possible to reduce the number of photolithography steps and the number of steps.

If the metal wiring resist formation step S203 and the chip identification part resist formation step S205 are performed in the same process, the number of steps can be reduced, but while the pattern of the resist 60 is common to multiple semiconductor devices 100, the pattern of the resist 62 is different for each semiconductor device 100. For this reason, a mask for the resist 60 and a mask for the resist 62 must be prepared and photolithography must be performed for each. In addition, the lens reduction ratios for exposure are different between the reduction mask used in the metal wiring resist formation step S203 and the normal mask used in the chip identification part resist formation step S205. Therefore, if the metal wiring resist formation step S203 and the chip identification part resist formation step S205 are performed in the same process using a normal mask, the processing accuracy of the metal wiring 30 will decrease. In the manufacturing method of the semiconductor device 100 of this example, it is possible to reduce the number of steps without decreasing the processing accuracy of the metal wiring 30.

The present invention has been described above using an embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiment. It is clear from the claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

10: semiconductor substrate, 20: insulating film, 21: upper surface, 30: metal wiring, 31: upper surface, 32: metal film, 33: upper surface, 40, 80: chip identification part, 41: upper surface, 42: silicon residue, 44: silicon particles, 50: adjacent part, 60: resist, 62: resist, 64: resist, 70: protective film, 100: semiconductor device, 200: semiconductor device, 300: semiconductor device, 400: semiconductor device, 500: semiconductor device

Claims (15)

A semiconductor substrate;
an insulating film provided on the semiconductor substrate;
a metal wiring including silicon element provided on the insulating film;
a chip identification part provided on the insulating film and mainly composed of silicon elements ;
The chip identification portion is a collection of silicon particles.
Semiconductor device. The semiconductor device according to claim 1 , wherein the silicon particles are spaced apart from each other in the chip identification portion. The semiconductor device according to claim 1 , wherein the silicon particles are embedded in an upper surface of the insulating film. The semiconductor device according to claim 1 , wherein the chip identification portion includes a metal element contained in the metal wiring. The semiconductor device according to claim 1 , wherein the height of the chip identification portion is 60% or less of the height of the metal wiring. Further comprising an adjacent portion provided adjacent to the metal wiring and mainly composed of silicon element,
The semiconductor device according to claim 1 , wherein a height of the adjacent portion is the same as a height of the chip identification portion. The semiconductor device according to claim 1 , wherein the chip identification portion includes polycrystalline silicon. The semiconductor device according to claim 1 , wherein the chip identification portion includes amorphous silicon. The semiconductor device according to claim 1 , further comprising a protective film covering the chip identification portion. The semiconductor device according to claim 1 , wherein the height of the metal wiring is not less than 0.5 μm and not more than 5 μm. The semiconductor device according to claim 1 , wherein a mass percent concentration of silicon contained in the metal wiring is 0.5% or more and 10% or less. forming an insulating film on a semiconductor substrate;
forming a metal film containing silicon on the insulating film;
etching the metal film to form a metal wiring;
and forming a chip identification portion by etching silicon residue generated in the step of forming the metal wiring. The method for manufacturing a semiconductor device according to claim 12 , wherein in the step of forming the chip identification portion, the chip identification portion is formed in a state in which the metal wiring is protected by a resist. The method for manufacturing a semiconductor device according to claim 12 or 13 , wherein in the step of forming the metal wiring, the metal film is wet-etched. The method for manufacturing a semiconductor device according to claim 12 , wherein in the step of forming the chip identification portion, the silicon residue is dry etched.

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