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JP7680252B2 - Method for manufacturing a circuit board and a semiconductor module - Google Patents
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JP7680252B2 - Method for manufacturing a circuit board and a semiconductor module - Google Patents

Method for manufacturing a circuit board and a semiconductor module Download PDF

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JP7680252B2
JP7680252B2 JP2021071990A JP2021071990A JP7680252B2 JP 7680252 B2 JP7680252 B2 JP 7680252B2 JP 2021071990 A JP2021071990 A JP 2021071990A JP 2021071990 A JP2021071990 A JP 2021071990A JP 7680252 B2 JP7680252 B2 JP 7680252B2
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copper foil
circuit board
manufacturing
heat sink
bonding
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JP2022166640A (en
JP2022166640A5 (en
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秀樹 松永
政之 植谷
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NGK Insulators Ltd
NGK Electronics Devices Inc
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NGK Electronics Devices Inc
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Description

本発明は、窒化ケイ素絶縁放熱回路基板の構成に関する。 The present invention relates to the configuration of a silicon nitride insulating heat dissipation circuit board.

半導体チップ等の電子部品が搭載されるセラミックス絶縁放熱回路基板として、窒化ケイ素絶縁放熱回路基板やアルミナ系絶縁放熱回路基板などが広く知られている。セラミックス絶縁放熱回路基板は、搭載された電子部品が発する熱を外部へと逃がす役割を有するとともに、当該電子部品と外部との電気的接続も担っている。 Silicon nitride insulating heat dissipation circuit boards and alumina insulating heat dissipation circuit boards are widely known as ceramic insulating heat dissipation circuit boards on which electronic components such as semiconductor chips are mounted. Ceramic insulating heat dissipation circuit boards have the role of dissipating heat generated by the mounted electronic components to the outside, and also serve as an electrical connection between the electronic components and the outside.

窒化ケイ素絶縁放熱回路基板は、窒化ケイ素セラミックス基板の両面に、金属銅を主成分とする銅箔(銅板、銅回路板、銅放熱板など称されることもある)を活性金属を含むろう材などを用いて接合してなるものである。通常、一方の銅箔表面には半導体チップが銀焼結接合により接合(搭載)され、他方の銅箔表面には、例えば金属製の放熱板(ヒートシンク)がはんだ接合される。 A silicon nitride insulating heat dissipation circuit board is made by bonding copper foil (sometimes called copper plate, copper circuit plate, copper heat sink, etc.) whose main component is metallic copper to both sides of a silicon nitride ceramic substrate using a brazing material containing active metals. Typically, a semiconductor chip is bonded (mounted) to one of the copper foil surfaces by silver sintering bonding, and a metal heat sink, for example, is soldered to the other copper foil surface.

窒化ケイ素絶縁放熱回路基板は、アルミナ系セラミックス基板を用いたアルミナ系絶縁放熱回路基板に比較して、放熱性と信頼性に優れているため、車載用途に適用されることが多い。その場合、半導体チップと窒化ケイ素絶縁放熱回路基板との銀焼結接合の接合信頼性を向上させる目的で、窒化ケイ素絶縁放熱回路基板をなす銅箔の表面に銀めっきが付与されることが多い。例えば、窒化ケイ素絶縁放熱回路基板の一方面に備わる銅回路板の表面に銀めっきを施す態様が、すでに公知である(例えば、特許文献1参照)。 Silicon nitride insulating heat dissipation circuit boards have superior heat dissipation properties and reliability compared to alumina-based insulating heat dissipation circuit boards using alumina-based ceramic substrates, and are therefore often used in automotive applications. In such cases, silver plating is often applied to the surface of the copper foil constituting the silicon nitride insulating heat dissipation circuit board in order to improve the reliability of the silver sintered bond between the semiconductor chip and the silicon nitride insulating heat dissipation circuit board. For example, a form in which silver plating is applied to the surface of a copper circuit board provided on one side of a silicon nitride insulating heat dissipation circuit board is already known (see, for example, Patent Document 1).

国際公開第2020/218193号International Publication No. 2020/218193

窒化ケイ素絶縁放熱回路基板に対する銀めっきには、主に無電解銀めっきが適用される。なかでも、めっきに要する時間が短い置換銀めっきが採用されることが多い。還元銀めっきは、反応速度が遅いため、通常は採用されない。 Electroless silver plating is mainly used for silver plating on silicon nitride insulating heat dissipation circuit boards. Of these, displacement silver plating, which requires a short plating time, is often used. Reduction silver plating is not usually used because of its slow reaction rate.

また、窒化ケイ素絶縁放熱回路基板の銅箔には、厚みが300μm以上と大きいものを用いることも多い。そのような銅箔としては、通常、圧延銅箔が採用される。 The copper foil used for silicon nitride insulating heat dissipation circuit boards is often as thick as 300 μm or more. Rolled copper foil is usually used for such copper foil.

ただし、そのような厚みの大きい圧延銅箔の表面に対する置換銀めっきのめっき速度(銀の析出速度)は、プリント回路基板などで回路に使用されている電解銅箔の表面に対する置換銀めっきのめっき速度よりも遅いという問題がある。 However, there is a problem in that the plating speed (silver deposition speed) of displacement silver plating on the surface of such thick rolled copper foil is slower than the plating speed of displacement silver plating on the surface of electrolytic copper foil used in circuits on printed circuit boards, etc.

しかも、圧延銅箔の表面に置換銀めっきを行う場合、係るめっき速度の遅さに起因して、銀めっき膜が成長する一方でその下では圧延銅箔の腐食が進行して銀めっき膜と圧延銅箔との間に空隙が発生する。係る空隙が存在する状態で銀めっきが施された圧延銅箔の表面に対し放熱板をはんだ接合した場合、銀めっき膜ははんだ内に拡散するものの、はんだ層と圧延銅箔との間には、依然として空隙が存在したままとなる。 Furthermore, when displacement silver plating is performed on the surface of rolled copper foil, the slow plating speed causes the silver plating film to grow while corrosion of the rolled copper foil progresses underneath, resulting in the formation of voids between the silver plating film and the rolled copper foil. If a heat sink is soldered to the silver-plated rolled copper foil surface with such voids present, the silver plating film will diffuse into the solder, but voids will still remain between the solder layer and the rolled copper foil.

これはすなわち、銀めっきが施された圧延銅箔を備える窒化ケイ素絶縁放熱回路基板において、圧延銅箔の表面に対し放熱板をはんだ接合する場合、十分な接合信頼性を確保することは難しいことを意味する。ただし、はんだ接合の前と後では、空隙の存在箇所や大きさ、形状、個数などは異なる。 This means that in a silicon nitride insulating heat dissipation circuit board with silver-plated rolled copper foil, it is difficult to ensure sufficient joint reliability when soldering a heat sink to the surface of the rolled copper foil. However, the location, size, shape, and number of voids differ before and after soldering.

窒化ケイ素絶縁放熱回路基板の両面に備わる圧延銅箔のうち、半導体チップが搭載される圧延銅箔にのみ銀めっきを施す態様も想定されるが、工程が煩雑となるため、現実的ではない。 It is also possible to apply silver plating only to the rolled copper foil on both sides of the silicon nitride insulating heat dissipation circuit board where the semiconductor chip is mounted, but this is not realistic because the process becomes complicated.

本発明は上記課題に鑑みてなされたものであり、放熱板とのはんだ接合の信頼性に優れた窒化ケイ素絶縁放熱回路基板を提供することを目的とする。 The present invention was made in consideration of the above problems, and aims to provide a silicon nitride insulating heat dissipation circuit board with excellent reliability of solder joint with a heat sink.

上記課題を解決するため、本発明の第の態様は、半導体チップ搭載用の回路基板の製造方法であって、窒化ケイ素セラミックス基板の2つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、両方の前記ペースト膜に圧延銅箔を重畳させ、かつ、少なくとも一方の前記圧延銅箔に電解銅箔を重畳させて積層体を得る積層工程と、前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記圧延銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記電解銅箔を前記圧延銅箔に接合する、加熱加圧工程と、を備えることを特徴とする。 In order to solve the above problems, a first aspect of the present invention is a method for manufacturing a circuit board for mounting a semiconductor chip, comprising: a coating step of coating each of two main surfaces of a silicon nitride ceramic substrate with an active metal paste to form a paste film; a lamination step of superimposing rolled copper foils on both of the paste films and superimposing an electrolytic copper foil on at least one of the rolled copper foils to obtain a laminate; and a heating and pressurizing step of heating the laminate in a vacuum or in an inert gas while pressurizing the laminate according to a predetermined surface pressure profile, thereby bonding the rolled copper foil to the silicon nitride ceramic substrate and bonding the electrolytic copper foil to the rolled copper foil.

本発明の第の態様は、第の態様に係る回路基板の製造方法であって、前記積層工程においては、両方の前記圧延銅箔に前記電解銅箔を重畳させる、ことを特徴とする。 A second aspect of the present invention is the method for producing a circuit board according to the first aspect, characterized in that in the laminating step, the electrolytic copper foil is superimposed on both of the rolled copper foils.

本発明の第の態様は、半導体チップ搭載用の回路基板の製造方法であって、窒化ケイ素セラミックス基板の2つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、両方の前記ペースト膜に第1の銅箔を重畳させ、かつ、少なくとも一方の前記第1の銅箔に、前記第1の銅箔の銅粒子よりも平均粒径が小さい第2の銅箔を重畳させて積層体を得る積層工程と、前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記第1の銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記第2の銅箔を前記第1の銅箔に接合する、加熱加圧工程と、を備えることを特徴とする。 A third aspect of the present invention is a method for manufacturing a circuit board for mounting a semiconductor chip, comprising: a coating step of coating each of two main surfaces of a silicon nitride ceramic substrate with an active metal paste to form a paste film; a lamination step of superposing a first copper foil on both of the paste films and superposing a second copper foil having an average particle size smaller than the copper particles of the first copper foil on at least one of the first copper foils to obtain a laminate; and a heating and pressurizing step of heating the laminate in a vacuum or in an inert gas while pressurizing the laminate according to a predetermined surface pressure profile, thereby bonding the first copper foil to the silicon nitride ceramic substrate and bonding the second copper foil to the first copper foil.

本発明の第の態様は、第の態様に係る回路基板の製造方法であって、前記積層工程においては、両方の前記第1の銅箔に前記第2の銅箔を重畳させる、ことを特徴とする。 A fourth aspect of the present invention is a method for manufacturing a circuit board according to the third aspect, characterized in that in the lamination step, the second copper foil is superimposed on both of the first copper foils.

本発明の第の態様は、第ないし第の態様のいずれかに係る回路基板の製造方法であって、前記活性金属ペーストが、チタン及びジルコニウムからなる群より選択される少なくとも1種の金属である活性金属の粉末と、銀粉末とを、金属粉末として少なくとも含み、かつ、有機成分としてバインダ及び溶剤を含む、ことを特徴とする。 A fifth aspect of the present invention is a method for manufacturing a circuit board according to any one of the first to fourth aspects, characterized in that the active metal paste contains at least a powder of an active metal which is at least one metal selected from the group consisting of titanium and zirconium, and a silver powder as metal powders, and contains a binder and a solvent as organic components.

本発明の第の態様は、半導体モジュールの製造方法であって、第または第の態様に係る製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、を備え、前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記電解銅箔に対して前記放熱板をはんだにて接合する、ことを特徴とする。
本発明の第の態様は、半導体モジュールの製造方法であって、第または第の態様に係る製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、を備え、前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記第2の銅箔に対して前記放熱板をはんだにて接合する、ことを特徴とする。
A sixth aspect of the present invention is a method for manufacturing a semiconductor module, comprising: a plating step of forming a silver plating film by displacement silver plating on a circuit board manufactured by the manufacturing method according to the first or second aspect; a chip mounting step of mounting a semiconductor chip by silver sintering bonding on a main surface of the circuit board opposite to a main surface to which a heat sink is bonded, the circuit board having undergone the plating step; and a heat sink bonding step of bonding the heat sink to one main surface of the circuit board having undergone the plating step by soldering, wherein in the heat sink bonding step, the heat sink is bonded by solder to the electrolytic copper foil on which the silver plating film is formed.
A seventh aspect of the present invention is a method for manufacturing a semiconductor module, comprising: a plating step of forming a silver plating film by displacement silver plating on a circuit board manufactured by the manufacturing method according to the third or fourth aspect; a chip mounting step of mounting a semiconductor chip by silver sintering bonding on a main surface of the circuit board opposite to a main surface to which a heat sink is bonded, the circuit board having undergone the plating step; and a heat sink bonding step of bonding the heat sink to one main surface of the circuit board having undergone the plating step by soldering, wherein in the heat sink bonding step, the heat sink is bonded by solder to the second copper foil on which the silver plating film is formed.

本発明の第1ないし第の態様によれば、置換銀めっきにより銀めっき膜を設けたうえで回路基板の一方主面に半導体チップを搭載し、他方主面には放熱板をはんだ接合することによって、半導体モジュールを得る場合において、回路基板との銀焼結結合の接合信頼性については従来と同等に確保しつつ、回路基板と放熱板との接合信頼性について、従来よりも向上させることができる。

According to the first to seventh aspects of the present invention, in a semiconductor module obtained by forming a silver plating film by displacement silver plating, mounting a semiconductor chip on one main surface of a circuit board, and soldering a heat sink to the other main surface, the bonding reliability of the silver sintered bond with the circuit board can be ensured to be equal to that of the conventional method, while the bonding reliability between the circuit board and the heat sink can be improved compared to the conventional method.

第1の実施の形態に係る回路基板10の構成を示す模式断面図である。1 is a schematic cross-sectional view showing a configuration of a circuit board 10 according to a first embodiment. 回路基板10の製造プロセスを説明するための模式断面図である。5A to 5C are schematic cross-sectional views for explaining a manufacturing process of the circuit board 10. 第2の実施の形態に係る回路基板20の構成を示す模式断面図である。FIG. 11 is a schematic cross-sectional view showing a configuration of a circuit board 20 according to a second embodiment.

<第1の実施の形態>
<窒化ケイ素絶縁放熱回路基板の構成>
図1は、本発明の第1の実施の形態に係る窒化ケイ素絶縁放熱回路基板(以下、単に回路基板とも称する)10の構成を示す模式断面図である。回路基板10は、半導体チップが搭載される基板であり、一方主面側に搭載された当該半導体チップと外部との電気的接続を担う。例えば車載用途のパワー半導体モジュールに使用される場合であれば、パワー半導体素子が搭載される。加えて、回路基板10は、他方主面側に接合された放熱板を通じて半導体チップが発する熱を外部へと逃がす役割も有してなる。
First Embodiment
<Configuration of Silicon Nitride Insulating Heat Dissipation Circuit Board>
1 is a schematic cross-sectional view showing the configuration of a silicon nitride insulating heat dissipation circuit board (hereinafter, simply referred to as a circuit board) 10 according to a first embodiment of the present invention. The circuit board 10 is a board on which a semiconductor chip is mounted, and serves to electrically connect the semiconductor chip mounted on one main surface side to the outside. For example, when used in a power semiconductor module for in-vehicle use, a power semiconductor element is mounted. In addition, the circuit board 10 also serves to release heat generated by the semiconductor chip to the outside through a heat sink bonded to the other main surface side.

回路基板10は、窒化ケイ素(Si)セラミックス基板(以下、窒化ケイ素基板とも称する)1の両主面上に、圧延銅箔2(2a、2b)と電解銅箔3(3a、3b)とがこの順に積層され接合により一体化された構成を有する。以降においては、一方主面側の圧延銅箔2aとこれに積層された電解銅箔3aとを回路面側銅箔4aと称し、他方主面側の圧延銅箔2bとこれに積層された電解銅箔3bとをはんだ接合面側銅箔4bと称する。 The circuit board 10 has a configuration in which rolled copper foils 2 (2a, 2b) and electrolytic copper foils 3 (3a, 3b) are laminated in this order and integrated by bonding on both main surfaces of a silicon nitride ( Si3N4 ) ceramic substrate (hereinafter also referred to as silicon nitride substrate) 1. Hereinafter, the rolled copper foil 2a on one main surface side and the electrolytic copper foil 3a laminated thereon will be referred to as the circuit surface side copper foil 4a, and the rolled copper foil 2b on the other main surface side and the electrolytic copper foil 3b laminated thereon will be referred to as the solder bonding surface side copper foil 4b.

窒化ケイ素基板1は、高い熱伝導性及び高い絶縁性を有する窒化ケイ素セラミックスからなる基板である。窒化ケイ素基板1の平面形状やサイズに特段の制限はないが、パワー半導体モジュールの小型化を図るという観点からは、一辺の長さLが100mm~250mm程度で厚みWが0.20mm~0.40mmの平面視矩形状の窒化ケイ素基板1が例示される。 The silicon nitride substrate 1 is a substrate made of silicon nitride ceramics, which has high thermal conductivity and high insulation properties. There are no particular limitations on the planar shape or size of the silicon nitride substrate 1, but from the perspective of miniaturizing the power semiconductor module, an example of a silicon nitride substrate 1 is one that is rectangular in plan view, with a side length L of approximately 100 mm to 250 mm and a thickness W of 0.20 mm to 0.40 mm.

圧延銅箔2は、銅インゴットを圧延することにより製造された銅箔である。圧延銅箔2を構成する銅粒子の、当該圧延銅箔2が回路基板10として一体化された状態における平均粒径は概ね100μm~1000μm程度である。また、回路基板10における圧延銅箔2aの厚みRC1と圧延銅箔2bの厚みRC2はいずれも、300μm~2500μm程度であるのが好適である。ただし、両者が同じ値である必要はない。 The rolled copper foil 2 is a copper foil produced by rolling a copper ingot. The average particle size of the copper particles that make up the rolled copper foil 2 when the rolled copper foil 2 is integrated into the circuit board 10 is approximately 100 μm to 1000 μm. In addition, it is preferable that the thickness RC1 of the rolled copper foil 2a and the thickness RC2 of the rolled copper foil 2b in the circuit board 10 are both approximately 300 μm to 2500 μm. However, the two do not need to be the same value.

なお、上記の厚み範囲をみたす限りにおいて、銅「箔」ではなく銅「板」が用いられてもよいが、本実施の形態においてはこれらを区別することなく圧延銅箔2と称することとする。 As long as the thickness falls within the above range, a copper "plate" may be used instead of a copper "foil," but in this embodiment, the two will be referred to as rolled copper foil 2 without distinction.

一方、電解銅箔3は、硫酸銅の槽に通電し、陰極回転ドラムに銅を析出させることにより製造された銅箔である。電解銅箔3を構成する銅粒子の、当該電解銅箔3が回路基板10として一体化された状態における平均粒径は概ね100μm未満であり、好ましくは10μm未満であり、より好ましくは5μm未満である。電解銅箔3aの厚みEC1と電解銅箔3bの厚みEC2とはいずれも5μm~50μm程度であるのが好適である。ただし、両者が同じ値である必要はない。なお、回路基板10における電解銅箔3の表面の十点平均高さRzは1μm~5μmであり、最大高さRmaxは1μm~10μmである。 On the other hand, the electrolytic copper foil 3 is a copper foil produced by passing electricity through a copper sulfate bath and depositing copper on a rotating cathode drum. The average particle size of the copper particles constituting the electrolytic copper foil 3 when the electrolytic copper foil 3 is integrated into the circuit board 10 is generally less than 100 μm, preferably less than 10 μm, and more preferably less than 5 μm. It is preferable that the thickness EC1 of the electrolytic copper foil 3a and the thickness EC2 of the electrolytic copper foil 3b are both about 5 μm to 50 μm. However, it is not necessary that the two have the same value. The ten-point average height Rz of the surface of the electrolytic copper foil 3 on the circuit board 10 is 1 μm to 5 μm, and the maximum height Rmax is 1 μm to 10 μm.

窒化ケイ素基板1と圧延銅箔2とは、図示しない接合層にて接合されてなる。係る接合は、活性金属法により実現されてなる。一方、圧延銅箔2と電解銅箔3とは直接に接合されてなる。それゆえ、これらの接合の仕方に起因して、少なくとも圧延銅箔2には、場合によっては電解銅箔3にまで、接合に際して使用される活性金属ペーストに含まれていた元素が拡散している場合がある。回路基板10の製法については後述する。 The silicon nitride substrate 1 and the rolled copper foil 2 are bonded together by a bonding layer (not shown). Such bonding is achieved by an active metal method. On the other hand, the rolled copper foil 2 and the electrolytic copper foil 3 are bonded together directly. Therefore, depending on the method of bonding, elements contained in the active metal paste used for bonding may diffuse into at least the rolled copper foil 2, and in some cases even into the electrolytic copper foil 3. The manufacturing method of the circuit board 10 will be described later.

圧延銅箔2と電解銅箔3とはいずれも銅粒子からなるが、上述のように粒径が顕著に相違することから、両者は、例えば回路基板10の断面SEM(走査電子顕微鏡)像において明確に識別される。 Both the rolled copper foil 2 and the electrolytic copper foil 3 are made of copper particles, but because the particle sizes are significantly different as described above, the two can be clearly distinguished from each other, for example, in a cross-sectional SEM (scanning electron microscope) image of the circuit board 10.

係る粒径の相違に着目すると、回路基板10は、窒化ケイ素基板1に隣接する、相対的に粒径が大きい第1の部分(圧延銅箔2)と、銅箔主面の表層部分をなしており第1の部分に隣接する、相対的に粒径が小さい第2の部分(電解銅箔3)との2層構造を有する銅箔を、窒化ケイ素基板1の両主面上に備えるものであると、捉えることもできる。 Focusing on the difference in grain size, the circuit board 10 can be considered to have copper foil on both main surfaces of the silicon nitride substrate 1, which has a two-layer structure consisting of a first portion (rolled copper foil 2) with a relatively large grain size adjacent to the silicon nitride substrate 1, and a second portion (electrolytic copper foil 3) with a relatively small grain size that forms the surface layer of the copper foil main surface and is adjacent to the first portion.

なお、図1に示すように、回路面側銅箔4aに隙間があり、係る隙間は、窒化ケイ素基板1が露出する溝部Gとなっている。これは、回路面側銅箔4aが、その上に搭載される半導体チップに応じた回路パターンにパターニングされていることによる。すなわち、回路パターンの隙間が溝部Gとなっている。 As shown in FIG. 1, there are gaps in the copper foil 4a on the circuit surface side, which serve as grooves G through which the silicon nitride substrate 1 is exposed. This is because the copper foil 4a on the circuit surface side is patterned into a circuit pattern that corresponds to the semiconductor chip to be mounted thereon. In other words, the gaps in the circuit pattern serve as grooves G.

<回路基板の製造プロセス>
次に、回路基板10の製造プロセスについて説明する。図2は、係る製造プロセスを説明するための、模式断面図である。
<Circuit board manufacturing process>
Next, a description will be given of a manufacturing process for the circuit board 10. FIG 2 is a schematic cross-sectional view for explaining the manufacturing process.

回路基板10の製造に際しては、活性金属法による接合を利用する。まず、窒化ケイ素基板1の両主面の略全面に、活性金属ペーストがスクリーン印刷法などの公知の塗布法にて塗布され、ペースト膜7(7a、7b)が形成される。ペースト膜7は、0.5μm~3.0μm程度の厚みに形成されるのが好適である。 When manufacturing the circuit board 10, bonding using the active metal method is used. First, active metal paste is applied to substantially the entire surface of both main surfaces of the silicon nitride substrate 1 using a known application method such as screen printing to form paste films 7 (7a, 7b). It is preferable that the paste film 7 be formed to a thickness of approximately 0.5 μm to 3.0 μm.

活性金属ペーストは、チタン及びジルコニウムからなる群より選択される少なくとも1種の金属である活性金属の粉末と、銀粉末とを、金属粉末として少なくとも含み、かつ、有機成分としてバインダ及び溶剤を含んでなるペーストである。加えて、銅、インジウム及びスズからなる群より選択される少なくとも1種の金属の粉末を任意的に含み得る。さらには、分散剤、消泡剤等を含んでいてもよい。チタンを活性金属として含む活性金属ペーストを用いるのが、好適な一例である。 The active metal paste is a paste that contains at least a powder of an active metal, which is at least one metal selected from the group consisting of titanium and zirconium, and silver powder as metal powder, and also contains a binder and a solvent as organic components. In addition, it may optionally contain a powder of at least one metal selected from the group consisting of copper, indium, and tin. It may also contain a dispersant, an antifoaming agent, etc. One suitable example is to use an active metal paste that contains titanium as the active metal.

次いで、ペースト膜7aに対して圧延銅箔2a、電解銅箔3aを重畳し、ペースト膜7bに対して圧延銅箔2b、電解銅箔3bを重畳する。これにより、両主面にペースト膜7a、7bが塗布された窒化ケイ素基板1を圧延銅箔2a、2bが挟み込み、さらにその外側を電解銅箔3a、3bが挟み込んだ積層体が得られる。なお、この時点では、圧延銅箔2aおよび電解銅箔3aに対するパターニングは行われておらず、それゆえ、溝部Gは形成されていない。 Next, rolled copper foil 2a and electrolytic copper foil 3a are superimposed on paste film 7a, and rolled copper foil 2b and electrolytic copper foil 3b are superimposed on paste film 7b. This results in a laminate in which silicon nitride substrate 1, with paste films 7a and 7b applied to both main surfaces, is sandwiched between rolled copper foils 2a and 2b, and further sandwiched on the outside by electrolytic copper foils 3a and 3b. At this point, the rolled copper foil 2a and electrolytic copper foil 3a have not been patterned, and therefore no grooves G have been formed.

続いて、得られた積層体に対し、加熱・加圧処理(ホットプレス)を行う。例えば、積層体を真空中または不活性ガス中で最高温度が800℃以上900℃以下となる所定の温度プロファイルにて加熱しながら、最高面圧が5MPa以上30MPa以下となる面圧プロファイルに従って、図2において矢印ARにて示すように積層体を加圧する。 Then, the obtained laminate is subjected to a heating and pressurizing treatment (hot pressing). For example, the laminate is heated in a vacuum or in an inert gas with a predetermined temperature profile in which the maximum temperature is 800°C or more and 900°C or less, while the laminate is pressurized according to a surface pressure profile in which the maximum surface pressure is 5 MPa or more and 30 MPa or less, as shown by the arrow AR in Figure 2.

係るホットプレスにより、ペースト膜7に存在していた活性金属(例えばチタン)が窒化ケイ素基板1の窒素と反応する一方で、同じくペースト膜7に存在していた銀は圧延銅箔2へと拡散する。その際には、活性金属ペーストに含まれる他の金属成分の圧延銅箔2への拡散や、窒化ケイ素基板1に含まれるケイ素の活性金属ペーストへの拡散なども起こり得る。また、電解銅箔3は圧延銅箔2に対し圧着される。 By this hot pressing, the active metal (e.g. titanium) present in the paste film 7 reacts with the nitrogen of the silicon nitride substrate 1, while the silver also present in the paste film 7 diffuses into the rolled copper foil 2. At that time, other metal components contained in the active metal paste may diffuse into the rolled copper foil 2, and the silicon contained in the silicon nitride substrate 1 may diffuse into the active metal paste. In addition, the electrolytic copper foil 3 is pressed against the rolled copper foil 2.

また、ホットプレスを実行することで、圧延銅箔2および電解銅箔3を構成する銅粒子の粒成長も生じる。それゆえ、上述した100μm~1000μmという圧延銅箔2(2a、2b)を構成する銅粒子の平均粒径の範囲、および、100μm未満という電解銅箔3(3a、3b)を構成する銅粒子の平均粒径の範囲はあくまで、ホットプレスを経て最終的に得られる(完成品である)回路基板10においてみたされればよい。換言すれば、少なくとも積層体が得られた時点までは、圧延銅箔2(2a、2b)および電解銅箔3(3a、3b)を構成する銅粒子の平均粒径は必ずしも、それらの範囲を充足している必要はなく、せいぜい、電解銅箔3(3a、3b)を構成する銅粒子の平均粒径が圧延銅箔2(2a、2b)を構成する銅粒子の平均粒径よりも小さいという関係がみたされていればよい。 In addition, the hot pressing also causes grain growth of the copper particles constituting the rolled copper foil 2 and the electrolytic copper foil 3. Therefore, the above-mentioned range of the average particle size of the copper particles constituting the rolled copper foil 2 (2a, 2b) of 100 μm to 1000 μm and the range of the average particle size of the copper particles constituting the electrolytic copper foil 3 (3a, 3b) of less than 100 μm only need to be satisfied in the circuit board 10 finally obtained (the finished product) through the hot pressing. In other words, at least until the laminate is obtained, the average particle size of the copper particles constituting the rolled copper foil 2 (2a, 2b) and the electrolytic copper foil 3 (3a, 3b) does not necessarily need to satisfy these ranges, and at most, it is sufficient that the relationship that the average particle size of the copper particles constituting the electrolytic copper foil 3 (3a, 3b) is smaller than the average particle size of the copper particles constituting the rolled copper foil 2 (2a, 2b) is satisfied.

例えば、上記の積層体の作製に用いた(接合前の)圧延銅箔2における銅粒子の平均粒径が10μm~100μm程度であった場合には、ホットプレスを経て最終的に得られる回路基板10において圧延銅箔2を構成する銅粒子の平均粒径は300μm~1000μm程度となる。また、上記の積層体の作製に用いた(接合前の)電解銅箔3における銅粒子の平均粒径が1μm未満であった場合には、ホットプレスを経て最終的に得られる回路基板10において電解銅箔3を構成する銅粒子の平均粒径は2μm~15μm程度となる。 For example, if the average particle size of the copper particles in the rolled copper foil 2 (before bonding) used to produce the laminate is about 10 μm to 100 μm, the average particle size of the copper particles constituting the rolled copper foil 2 in the circuit board 10 finally obtained after hot pressing will be about 300 μm to 1000 μm. Also, if the average particle size of the copper particles in the electrolytic copper foil 3 (before bonding) used to produce the laminate is less than 1 μm, the average particle size of the copper particles constituting the electrolytic copper foil 3 in the circuit board 10 finally obtained after hot pressing will be about 2 μm to 15 μm.

同様に、上述した300μm~2500μm程度という圧延銅箔2(2a、2b)の厚みおよび5μm~50μm程度という電解銅箔3(3a、3b)の厚みの範囲も、最終的に得られる回路基板10について充足されていればよく、積層体が構成された時点ではまだ、それぞれの銅箔の厚みはともに、当該範囲よりも大きくてよい。 Similarly, the thickness range of the rolled copper foil 2 (2a, 2b) of about 300 μm to 2500 μm and the thickness range of the electrolytic copper foil 3 (3a, 3b) of about 5 μm to 50 μm described above need only be satisfied for the circuit board 10 that is ultimately obtained, and the thickness of each copper foil may still be greater than this range when the laminate is constructed.

最終的に、活性金属の窒化物を主成分とする図示しない接合層にて窒化ケイ素基板1と圧延銅箔2とが接合され、かつ、電解銅箔3は圧延銅箔2に接合される。すなわち、パターニングを行っていない状態の回路基板10が形成される。 Finally, the silicon nitride substrate 1 and the rolled copper foil 2 are bonded together by a bonding layer (not shown) whose main component is an active metal nitride, and the electrolytic copper foil 3 is bonded to the rolled copper foil 2. In other words, a circuit board 10 is formed in an unpatterned state.

その後、回路面側銅箔4aに対しエッチングなどの公知のパターニング手法でパターニングがなされることで、図1に示したような、溝部Gが存在する回路基板10が得られる。例えば、溝部Gが設けられている箇所で回路面側銅箔4aの側面を観察すると、回路面側銅箔4aが圧電銅箔2aと電解銅箔3aの2層構造になっていることがわかる。 Then, the circuit surface side copper foil 4a is patterned by a known patterning method such as etching to obtain a circuit board 10 having a groove portion G as shown in FIG. 1. For example, when observing the side of the circuit surface side copper foil 4a at the location where the groove portion G is provided, it can be seen that the circuit surface side copper foil 4a has a two-layer structure of a piezoelectric copper foil 2a and an electrolytic copper foil 3a.

<窒化ケイ素絶縁放熱回路基板の使用態様>
次に、回路基板10の使用態様について説明する。回路基板10においては、回路面側銅箔4aの(より詳細には電解銅箔3aの)表面5aに半導体チップが搭載され、はんだ接合面側銅箔4bの(より詳細には電解銅箔3bの)表面5bには金属製の放熱板が接合される。
<Use of silicon nitride insulating heat dissipation circuit board>
Next, a description will be given of a mode of use of the circuit board 10. In the circuit board 10, a semiconductor chip is mounted on the surface 5a of the circuit surface side copper foil 4a (more specifically, the electrolytic copper foil 3a), and a metal heat sink is joined to the surface 5b of the solder bonding surface side copper foil 4b (more specifically, the electrolytic copper foil 3b).

表面5aに対する半導体チップの搭載は、公知の銀焼結接合により行われる。概略的にいえば、回路面側銅箔4aの表面に銀ペーストを塗布したうえで該銀ペースト上に半導体チップを配置し、その後、所定の温度および圧力のもとで銀ペーストを焼結させることで、半導体チップが回路基板10に固定される。 The semiconductor chip is mounted on the surface 5a by the well-known silver sintering bonding method. In general terms, silver paste is applied to the surface of the circuit side copper foil 4a, and the semiconductor chip is placed on the silver paste. The silver paste is then sintered under a specified temperature and pressure, thereby fixing the semiconductor chip to the circuit board 10.

一方、表面5aに対する半導体チップの搭載に続き、表面5bに対しては、放熱板がはんだにて接合される。それゆえ、はんだ接合面側銅箔4bは窒化ケイ素基板1の略全面に設けられてなる。はんだとしては従来公知の製品(例えば、6成分系のSn-Ag-Cu-Ni-Sb-Biはんだ)を使用可能である。 After mounting the semiconductor chip on surface 5a, a heat sink is soldered to surface 5b. Therefore, the copper foil 4b on the solder joint side is provided over almost the entire surface of the silicon nitride substrate 1. As the solder, a conventionally known product (for example, a six-component Sn-Ag-Cu-Ni-Sb-Bi solder) can be used.

ただし、通常は、半導体チップの銀焼結接合および放熱板のはんだ接合に先立ち、回路面側銅箔4aおよびはんだ接合面側銅箔4bの表面に対し、すなわち、それぞれの電解銅箔3a、3bの表面5a、5bに対し、置換銀めっきにて銀めっきが施される。めっき浴としては、MacDermid社製のスターリングシステムが例示される。 However, typically, prior to silver sintering of the semiconductor chip and soldering of the heat sink, the surfaces of the copper foil 4a on the circuit side and the copper foil 4b on the solder bonding side, i.e., the surfaces 5a and 5b of the electrolytic copper foils 3a and 3b, are silver plated by displacement silver plating. An example of a plating bath is the Stirling System manufactured by MacDermid.

電解銅箔3に対する置換銀めっきは、従来行われていた圧延銅箔2に対する置換銀めっきよりも速く進行する。そのため、従来とは異なり、めっき速度の遅さに起因して銅箔の腐食が進行して銀めっきと銅箔との間に空隙が発生するようなことはない。 The displacement silver plating of the electrolytic copper foil 3 proceeds faster than the displacement silver plating of the rolled copper foil 2 that was conventionally performed. Therefore, unlike the conventional method, the slow plating speed does not cause corrosion of the copper foil to progress and gaps to form between the silver plating and the copper foil.

むしろ、空隙が生じないことによって電解銅箔3a、3bの表面5a、5bに対する銀めっきの密着性が十分に確保されるので、本実施の形態においては、従来は必ずしも十分ではなかったはんだ接合面側銅箔4bに対する放熱板のはんだ接合の信頼性が、好適に確保される。 In fact, the lack of voids ensures sufficient adhesion of the silver plating to the surfaces 5a, 5b of the electrolytic copper foils 3a, 3b, so in this embodiment, the reliability of the solder joint of the heat sink to the solder joint side copper foil 4b, which was not necessarily sufficient in the past, is suitably ensured.

なお、はんだ接合の信頼性は例えば、低温雰囲気への曝露と高温雰囲気への曝露とを交互に繰り返す温度サイクル試験を行ったときの、クラックの発生時点のサイクル数の多少により、評価することが出来る。銀めっき膜の下(銅箔との間)における空隙が存在する場合、クラックは係る空隙を通って進行するため、温度サイクル試験におけるクラックの発生のしやすさによってはんだ接合の信頼性を評価することができる。 The reliability of the solder joint can be evaluated, for example, by the number of cycles at which cracks occur when a temperature cycle test is performed in which exposure to a low temperature atmosphere and a high temperature atmosphere are alternately repeated. If there is a gap under the silver plating film (between the copper foil), the crack will progress through the gap, so the reliability of the solder joint can be evaluated by the ease with which cracks occur in the temperature cycle test.

一方、回路面側銅箔4aと半導体チップとの銀焼結接合の場合も、表面5aに銀めっき膜が形成された電解銅箔3aの上に銀ペーストが塗布されることになる。そもそも、銀焼結接合は高温の加圧雰囲気で行われるので、仮に接合開始の時点で銀めっきと回路面側銅箔4aとの間に空隙があったとしても、最終的には空隙は残存せず、それゆえ、接合の信頼性は確保される。 On the other hand, in the case of silver sinter bonding between the circuit side copper foil 4a and the semiconductor chip, silver paste is applied onto the electrolytic copper foil 3a with a silver plating film formed on the surface 5a. Since silver sinter bonding is performed in a high-temperature pressurized atmosphere, even if there is a gap between the silver plating and the circuit side copper foil 4a at the start of bonding, no gap will remain in the end, and therefore the reliability of the bond is ensured.

従って、本実施の形態のように電解銅箔3aの表面5aに銀めっき膜が形成されることによって空隙が存在しない場合には、回路面側銅箔4aと半導体チップとの接合信頼性がさらに好適に確保される。 Therefore, when no voids exist due to the formation of a silver plating film on the surface 5a of the electrolytic copper foil 3a as in this embodiment, the bonding reliability between the circuit surface side copper foil 4a and the semiconductor chip is more appropriately ensured.

以上、説明したように、本実施の形態によれば、窒化ケイ素セラミックス基板の両主面に銅箔を接合してなり、一方主面に対する半導体チップの搭載と他方主面に対する放熱板の接合とが行われる窒化ケイ素絶縁放熱回路基板において、両主面に備わる銅箔を、相対的に粒径が大きい第1の部分(圧延銅箔)と、第1の部分に隣接する、相対的に粒径が小さい第2の部分(電解銅箔)との2層構造とする。これにより、一方主面における銀焼結接合による半導体チップの搭載と他方主面における放熱板のはんだ接合とを行うべくそれぞれの銅箔の表面に置換銀めっきにより銀めっきを施した際の、銀めっき膜と銅箔との間における空隙の発生が抑制される。結果として、半導体チップおよび放熱板と回路基板との接合信頼性が好適に確保される。特に、放熱板と回路基板との接合信頼性については、従来よりも向上する。 As described above, according to this embodiment, in a silicon nitride insulating heat dissipation circuit board formed by bonding copper foil to both main surfaces of a silicon nitride ceramic substrate, in which a semiconductor chip is mounted on one main surface and a heat sink is bonded to the other main surface, the copper foil on both main surfaces has a two-layer structure consisting of a first portion (rolled copper foil) having a relatively large grain size and a second portion (electrolytic copper foil) adjacent to the first portion and having a relatively small grain size. This suppresses the occurrence of voids between the silver plating film and the copper foil when silver plating is applied to the surface of each copper foil by displacement silver plating in order to mount a semiconductor chip by silver sintering bonding on one main surface and solder bond a heat sink on the other main surface. As a result, the bonding reliability between the semiconductor chip and the heat sink and the circuit board is suitably ensured. In particular, the bonding reliability between the heat sink and the circuit board is improved compared to the conventional case.

<第2の実施の形態>
図3は、本発明の第2の実施の形態に係る回路基板20の構成を示す模式断面図である。回路基板20も、第1の実施の形態に係る回路基板10と同様に、一方主面側に半導体チップが搭載される基板である。すなわち、他方主面側に接合される放熱板によって半導体チップが発する熱を外部へと逃がす役割を有するとともに、当該半導体チップと外部との電気的接続も担っている。
Second Embodiment
3 is a schematic cross-sectional view showing the configuration of a circuit board 20 according to a second embodiment of the present invention. Like the circuit board 10 according to the first embodiment, the circuit board 20 is also a board having a semiconductor chip mounted on one main surface side. That is, the heat sink bonded to the other main surface side has a role of releasing heat generated by the semiconductor chip to the outside, and also serves as an electrical connection between the semiconductor chip and the outside.

回路基板20は、電解銅箔3aを備えていない点を除いて、回路基板10と同じ構成を有する。換言すれば、圧延銅箔2aのみが回路面側銅箔として用いられるようになっている。 The circuit board 20 has the same configuration as the circuit board 10, except that it does not have electrolytic copper foil 3a. In other words, only the rolled copper foil 2a is used as the copper foil on the circuit side.

係る回路基板20は、ホットプレスに先立つ積層体の作成に際して、電解銅箔3aを重畳させないようにするほかは、第1の実施の形態にて示した回路基板10の製造プロセスと同じプロセスにて作成が可能である。 The circuit board 20 can be produced by the same manufacturing process as the circuit board 10 shown in the first embodiment, except that the electrolytic copper foil 3a is not overlapped when producing the laminate prior to hot pressing.

回路基板20も、回路基板10と同様に、通常は、置換銀めっきによる銀めっきが施されたうえで使用される。銀めっきは、圧延銅箔2aの表面6aと電解銅箔3bの表面5bに対し施される。そして、放熱板は、回路基板10の場合と同様、銀めっきが施された電解銅箔3bの表面5bに対しはんだ接合される。 As with circuit board 10, circuit board 20 is usually plated with silver by displacement silver plating before use. Silver plating is applied to surface 6a of rolled copper foil 2a and surface 5b of electrolytic copper foil 3b. Then, as with circuit board 10, the heat sink is soldered to surface 5b of electrolytic copper foil 3b that has been plated with silver.

従って、回路基板20に対する放熱板の接合態様は、第1の実施の形態における回路基板10に対する放熱板の接合態様と同じである。それゆえ、回路基板20を用いる場合も、回路基板10を用いる場合と同様、はんだ接合面側銅箔4bに対する放熱板のはんだ接合の信頼性は、好適に確保される。 The joining mode of the heat sink to the circuit board 20 is therefore the same as the joining mode of the heat sink to the circuit board 10 in the first embodiment. Therefore, when the circuit board 20 is used, as when the circuit board 10 is used, the reliability of the solder joining of the heat sink to the solder joining surface side copper foil 4b is suitably ensured.

一方、半導体チップの搭載は、第1の実施の形態とは異なり、銀めっきが施された圧延銅箔2aの表面6aに対する銀焼結接合にて実現される。係る接合態様は、従来技術と同様である。それゆえ、銀めっきの際にはめっき膜と圧延銅箔2aとの間に空隙が生じ得るが、上述のように、銀焼結接合は高温の加圧雰囲気で行われるので、仮に接合開始の時点で銀めっきと圧延銅箔2aとの間に空隙があったとしても、最終的には空隙は残存せず、それゆえ、接合の信頼性は確保される。 On the other hand, unlike the first embodiment, the mounting of the semiconductor chip is achieved by silver sintering bonding to the surface 6a of the silver-plated rolled copper foil 2a. This bonding mode is the same as that of the conventional technology. Therefore, during silver plating, gaps may occur between the plating film and the rolled copper foil 2a, but as described above, silver sintering bonding is performed in a high-temperature pressurized atmosphere, so even if there are gaps between the silver plating and the rolled copper foil 2a at the start of bonding, no gaps will remain in the end, and therefore the reliability of the bond is ensured.

すなわち、本実施の形態によれば、半導体チップと回路基板との銀焼結結合の接合信頼性については従来と同等に確保しつつ、放熱板と回路基板とのはんだ接合の接合信頼性について、従来よりも向上させることができる。 In other words, according to this embodiment, the reliability of the silver sintered bond between the semiconductor chip and the circuit board can be maintained at the same level as in the past, while the reliability of the soldered bond between the heat sink and the circuit board can be improved compared to the past.

回路面側銅箔4aおよびはんだ接合面側銅箔4bのそれぞれを構成する電解銅箔3a、3bの銅粒子の平均粒径を違えた2種類の回路基板10(実施例1、実施例2)と、はんだ接合面側銅箔4bを構成する電解銅箔3bの平均粒径を違えた2種類の回路基板20(実施例3,実施例4)とを、上述した拡散接合法にて作製した。 Two types of circuit boards 10 (Examples 1 and 2) in which the average particle size of the copper particles in the electrolytic copper foils 3a and 3b constituting the circuit side copper foil 4a and the solder joint side copper foil 4b, respectively, are different, and two types of circuit boards 20 (Examples 3 and 4) in which the average particle size of the electrolytic copper foil 3b constituting the solder joint side copper foil 4b are different, were produced by the diffusion bonding method described above.

回路基板10および20における銅箔の平均粒径は以下のようにして特定した。まず、回路基板10および20を切断し、切断面を研磨した。そして、この研磨面をSEMで観察した。得られた観察画像に複数の銅粒子を横切る直線を引き、当該直線の、個々の銅粒子を横切っている部分(線分)の長さをそれぞれ測定し、銅粒子50個についての当該線分の長さの平均値を、銅粒子の平均粒径とした。 The average particle size of the copper foil in circuit boards 10 and 20 was determined as follows. First, circuit boards 10 and 20 were cut and the cut surfaces were polished. The polished surfaces were then observed with an SEM. Straight lines were drawn across multiple copper particles in the obtained observation image, and the lengths of the straight line segments that crossed each individual copper particle were measured. The average length of the line segments for 50 copper particles was determined as the average particle size of the copper particles.

得られたそれぞれの回路基板に対し置換銀めっきを行い、めっき膜形成後のそれぞれの回路基板について、SEMによる断面観察を行い、銀めっきと銅箔との間の空隙の発生数を評価した。 Each of the resulting circuit boards was subjected to displacement silver plating, and the cross-section of each circuit board after the plating film was formed was observed using an SEM to evaluate the number of voids that occurred between the silver plating and the copper foil.

また、めっき膜形成後のそれぞれの回路基板の電解銅箔3bの表面5bに対し放熱板をはんだ接合した。そして、係るはんだ接合の信頼性を評価するべく、温度サイクル寿命試験を行った。 In addition, a heat sink was soldered to the surface 5b of the electrolytic copper foil 3b of each circuit board after the plating film was formed. A temperature cycle life test was then performed to evaluate the reliability of the solder joint.

一方、比較例として、圧延銅箔2(2a、2b)のみを窒化ケイ素基板1に接合し電解銅箔3a、3bのいずれも備えない回路基板を、圧延銅箔2(2a、2b)の銅粒子の平均粒径を違えて2種類作製した(比較例1、比較例2)。 On the other hand, as comparative examples, two types of circuit boards were produced in which only rolled copper foil 2 (2a, 2b) was bonded to silicon nitride substrate 1 and neither electrolytic copper foil 3a nor 3b was included, with the average particle size of the copper particles in rolled copper foil 2 (2a, 2b) being different (Comparative Example 1, Comparative Example 2).

具体的には、それぞれの回路基板に用いた窒化ケイ素基板1、圧延銅箔2、電解銅箔3の平面サイズおよび厚みは以下の通りである。 Specifically, the planar size and thickness of the silicon nitride substrate 1, rolled copper foil 2, and electrolytic copper foil 3 used in each circuit board are as follows:

窒化ケイ素基板:140mm×190mm、0.320mm;
圧延銅箔:130mm×185mm、0.500mm(比較例2のみ0.700mm);
電解銅箔:130mm×185mm、0.035mm。
Silicon nitride substrate: 140 mm x 190 mm, 0.320 mm;
Rolled copper foil: 130 mm × 185 mm, 0.500 mm (0.700 mm only in Comparative Example 2);
Electrolytic copper foil: 130mm x 185mm, 0.035mm.

また、実施例1~実施例4における電解銅箔の銅粒子の平均粒径は、3μmと10μmの2水準に違えた。 The average particle size of the copper particles in the electrolytic copper foils in Examples 1 to 4 was varied to two levels: 3 μm and 10 μm.

拡散接合時の活性金属ペーストの厚みは平均で1μmとした。さらには、置換銀めっきにより形成しためっき膜の厚みは平均で0.2μmとした。 The average thickness of the active metal paste used for diffusion bonding was 1 μm. Furthermore, the average thickness of the plating film formed by displacement silver plating was 0.2 μm.

銀めっきと銅箔との間の空隙の評価においては、基板断面における銀めっきとはんだ接合面側銅箔4bの電解銅箔3bとの界面長さ1mmあたりに存在する、1μm以上のサイズの空隙をカウントした。 When evaluating the voids between the silver plating and the copper foil, the number of voids of 1 μm or more in size that exist per 1 mm of interface length between the silver plating on the cross section of the board and the electrolytic copper foil 3b of the solder joint side copper foil 4b were counted.

温度サイクル寿命試験は、-40℃と150℃との間での昇降温を1時間あたり2サイクルのペースで500サイクル繰り返し、50サイクル毎に、接合部分における、銀めっき膜の下(銅箔との間)における空隙を通って進行するクラックの有無を確認することにより行った。 The temperature cycle life test was performed by repeating 500 cycles of heating and cooling between -40°C and 150°C at a rate of two cycles per hour, and checking every 50 cycles for the presence or absence of cracks that progress through the gaps under the silver plating film (between the copper foil) at the joint.

実施例1~実施例4および比較例1~比較例2に係る回路基板の回路面およびはんだ接合面における表層銅箔材料と、当該材料における銅粒子の平均粒径と、銀めっき膜形成後に当該銀めっき膜の下(銅箔との間)における空隙の発生数と、はんだ接合信頼性の指標としての温度サイクル寿命とを表1に一覧にして示す。 Table 1 shows the surface copper foil material on the circuit surface and solder joint surface of the circuit boards for Examples 1 to 4 and Comparative Examples 1 and 2, the average particle size of the copper particles in the material, the number of voids that occurred under the silver plating film (between the copper foil) after the silver plating film was formed, and the temperature cycle life as an index of solder joint reliability.

なお、「回路面」とは回路基板10および20において半導体チップが搭載される主面であって、具体的には、実施例1~実施例2では表面5aであり、実施例3~実施例4および比較例1~比較例3では表面6aである。一方、「はんだ接合面」とは回路基板10および20において放熱板がはんだ接合される主面であって、具体的には、実施例1~実施例4では表面5bであり、比較例1~比較例2では圧延銅箔2bの表面である。 The "circuit surface" refers to the main surface of the circuit boards 10 and 20 on which the semiconductor chip is mounted, specifically, surface 5a in Examples 1 and 2, and surface 6a in Examples 3 and 4 and Comparative Examples 1 and 3. On the other hand, the "solder joint surface" refers to the main surface of the circuit boards 10 and 20 on which the heat sink is soldered, specifically, surface 5b in Examples 1 to 4, and the surface of the rolled copper foil 2b in Comparative Examples 1 and 2.

また、「表層銅箔材料」とは、銅箔において最表位置に存在し、銀めっきの対象とされる銅箔の種類である。具体的には、電解銅箔が備わる回路基板においては当該電解銅箔が表層銅箔材料となり、電解銅箔が設けられていない銅箔においては圧延銅箔が表層電極材料となる。 In addition, the "surface copper foil material" is the type of copper foil that is present at the outermost position of the copper foil and is the target of silver plating. Specifically, in a circuit board that has electrolytic copper foil, the electrolytic copper foil is the surface copper foil material, and in a copper foil that does not have electrolytic copper foil, rolled copper foil is the surface electrode material.

Figure 0007680252000001
Figure 0007680252000001

表1からわかるように、はんだ接合面における表層銅箔材料が電解銅箔である実施例1~実施例4においてはいずれも、銀めっき膜の下に空隙は観察されなかった。一方で、比較例1および比較例2ではそれぞれ、80個/mm、85個/mmの空隙が確認された。 As can be seen from Table 1, in all of Examples 1 to 4, in which the surface copper foil material on the solder joint surface was electrolytic copper foil, no voids were observed under the silver plating film. On the other hand, in Comparative Example 1 and Comparative Example 2, voids were confirmed at 80 voids/mm and 85 voids/mm, respectively.

また、温度サイクル寿命試験についてみれば、実施例1~実施例4では500サイクル終了後までクラックの発生は確認されなかった。一方、比較例1および比較例2においてはいずれも、50サイクル終了時点でクラックの発生が確認された。 In addition, in the temperature cycle life test, no cracks were observed in Examples 1 to 4 until 500 cycles had been completed. On the other hand, in both Comparative Examples 1 and 2, cracks were observed at the end of 50 cycles.

以上の結果は、銅粒子の粒径が小さい電解銅箔を回路基板の銅箔の表層とすることは、銀めっきを施した後に当該表層に対してはんだにより放熱板を接合する場合の接合信頼性を向上させる効果があることを、指し示している。 These results indicate that using electrolytic copper foil with small copper particle size as the surface layer of copper foil on a circuit board has the effect of improving the bonding reliability when a heat sink is bonded to the surface layer by soldering after silver plating.

1 窒化ケイ素(セラミックス)基板
2(2a、2b) 圧延銅箔
3(3a、3b) 電解銅箔
4a 回路面側銅箔
4b はんだ接合面側銅箔
7(7a、7b) ペースト膜
10、20 (窒化ケイ素絶縁放熱)回路基板
REFERENCE SIGNS LIST 1 Silicon nitride (ceramic) substrate 2 (2a, 2b) Rolled copper foil 3 (3a, 3b) Electrolytic copper foil 4a Copper foil on circuit side 4b Copper foil on solder joint side 7 (7a, 7b) Paste film 10, 20 (Silicon nitride insulating heat dissipating) circuit board

Claims (7)

半導体チップ搭載用の回路基板の製造方法であって、
窒化ケイ素セラミックス基板の2つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、
両方の前記ペースト膜に圧延銅箔を重畳させ、かつ、少なくとも一方の前記圧延銅箔に電解銅箔を重畳させて積層体を得る積層工程と、
前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記圧延銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記電解銅箔を前記圧延銅箔に接合する、加熱加圧工程と、
を備えることを特徴とする、回路基板の製造方法。
A method for manufacturing a circuit board for mounting a semiconductor chip, comprising the steps of:
a coating step of coating an active metal paste on each of two main surfaces of a silicon nitride ceramic substrate to form a paste film;
a lamination step of overlapping rolled copper foils on both of the paste films and overlapping an electrolytic copper foil on at least one of the rolled copper foils to obtain a laminate;
a heating and pressing step in which the laminate is heated in a vacuum or in an inert gas and pressed according to a predetermined surface pressure profile, thereby bonding the rolled copper foil to the silicon nitride ceramic substrate and bonding the electrolytic copper foil to the rolled copper foil;
A method for manufacturing a circuit board, comprising:
請求項に記載の回路基板の製造方法であって、
前記積層工程においては、両方の前記圧延銅箔に前記電解銅箔を重畳させる、
ことを特徴とする、回路基板の製造方法。
A method for manufacturing a circuit board according to claim 1 ,
In the lamination step, the electrolytic copper foil is laminated on both of the rolled copper foils.
A method for manufacturing a circuit board.
半導体チップ搭載用の回路基板の製造方法であって、
窒化ケイ素セラミックス基板の2つの主面のそれぞれに活性金属ペーストを塗布してペースト膜を形成する塗布工程と、
両方の前記ペースト膜に第1の銅箔を重畳させ、かつ、少なくとも一方の前記第1の銅箔に、前記第1の銅箔の銅粒子よりも平均粒径が小さい第2の銅箔を重畳させて積層体を得る積層工程と、
前記積層体を真空中または不活性ガス中で加熱しながら所定の面圧プロファイルに従って前記積層体を加圧することにより前記第1の銅箔を前記窒化ケイ素セラミックス基板に接合するとともに前記第2の銅箔を前記第1の銅箔に接合する、加熱加圧工程と、
を備えることを特徴とする、回路基板の製造方法。
A method for manufacturing a circuit board for mounting a semiconductor chip, comprising the steps of:
a coating step of coating an active metal paste on each of two main surfaces of a silicon nitride ceramic substrate to form a paste film;
a lamination step of superposing a first copper foil on both of the paste films and a second copper foil having an average particle size smaller than that of the copper particles of the first copper foil on at least one of the first copper foils to obtain a laminate;
a heating and pressing step of heating the laminate in a vacuum or in an inert gas and pressing the laminate according to a predetermined surface pressure profile, thereby bonding the first copper foil to the silicon nitride ceramic substrate and bonding the second copper foil to the first copper foil;
A method for manufacturing a circuit board, comprising:
請求項に記載の回路基板の製造方法であって、
前記積層工程においては、両方の前記第1の銅箔に前記第2の銅箔を重畳させる、
ことを特徴とする、回路基板の製造方法。
A method for manufacturing a circuit board according to claim 3 , comprising the steps of:
In the lamination step, the second copper foil is laminated on both of the first copper foils.
A method for manufacturing a circuit board.
請求項ないし請求項のいずれかに記載の回路基板の製造方法であって、
前記活性金属ペーストが、チタン及びジルコニウムからなる群より選択される少なくとも1種の金属である活性金属の粉末と、銀粉末とを、金属粉末として少なくとも含み、かつ、有機成分としてバインダ及び溶剤を含む、
ことを特徴とする、回路基板の製造方法。
A method for manufacturing a circuit board according to any one of claims 1 to 4 , comprising the steps of:
The active metal paste contains at least a powder of an active metal which is at least one metal selected from the group consisting of titanium and zirconium, and a silver powder as metal powders, and contains a binder and a solvent as organic components.
A method for manufacturing a circuit board.
半導体モジュールの製造方法であって、
請求項または請求項に記載の製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、
前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、
前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、
を備え、
前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記電解銅箔に対して前記放熱板をはんだにて接合する、
ことを特徴とする、半導体モジュールの製造方法。
A method for manufacturing a semiconductor module, comprising the steps of:
a plating step of forming a silver plating film by displacement silver plating on the circuit board manufactured by the manufacturing method according to claim 1 or 2 ;
a chip mounting process in which a semiconductor chip is mounted by silver sintering bonding on a main surface of the circuit board that has been subjected to the plating process, the main surface being opposite to the main surface to which a heat sink is bonded;
a heat sink joining step of joining the heat sink to one main surface of the circuit board that has been subjected to the plating step by soldering;
Equipped with
In the heat sink joining step, the heat sink is joined to the electrolytic copper foil on which the silver plating film is formed by soldering.
A method for manufacturing a semiconductor module.
半導体モジュールの製造方法であって、
請求項または請求項に記載の製造方法にて製造された回路基板に置換銀めっきにて銀めっき膜を形成するめっき工程と、
前記めっき工程を経た前記回路基板の放熱板が接合される主面と反対側の主面に対し銀焼結接合にて半導体チップを搭載するチップ搭載工程と、
前記めっき工程を経た前記回路基板の一方の主面に対し前記放熱板をはんだにて接合する放熱板接合工程と、
を備え、
前記放熱板接合工程においては、前記銀めっき膜が形成されてなる前記第2の銅箔に対して前記放熱板をはんだにて接合する、
ことを特徴とする、半導体モジュールの製造方法。
A method for manufacturing a semiconductor module, comprising the steps of:
a plating step of forming a silver plating film by displacement silver plating on the circuit board manufactured by the manufacturing method according to claim 3 or 4 ;
a chip mounting process in which a semiconductor chip is mounted by silver sintering bonding on a main surface of the circuit board that has been subjected to the plating process, the main surface being opposite to the main surface to which a heat sink is bonded;
a heat sink joining step of joining the heat sink to one main surface of the circuit board that has been subjected to the plating step by soldering;
Equipped with
In the heat sink joining step, the heat sink is joined by soldering to the second copper foil on which the silver plating film is formed.
A method for manufacturing a semiconductor module.
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JP2014096545A (en) 2012-11-12 2014-05-22 Mitsubishi Materials Corp Power module and method of manufacturing power module
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WO2021059693A1 (en) 2019-09-27 2021-04-01 株式会社村田製作所 Antenna substrate, antenna module, and antenna substrate manufacturing method

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JP2014096545A (en) 2012-11-12 2014-05-22 Mitsubishi Materials Corp Power module and method of manufacturing power module
JP2017112277A (en) 2015-12-17 2017-06-22 三菱マテリアル株式会社 Bonded body, substrate for power module with cooler, method of manufacturing substrate for power module with cooler
JP2018022882A (en) 2016-07-26 2018-02-08 Jx金属株式会社 Printed wiring boards, electronic equipment, catheters and metal materials
JP2020053501A (en) 2018-09-26 2020-04-02 株式会社ケーヒン Power module
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