JP7683256B2 - Reference voltage generation circuit - Google Patents

Description

This invention relates to a reference voltage generating circuit that generates a reference voltage that is stable over temperature.

Figure 2 is a circuit diagram showing the configuration of the reference voltage generating circuit 2 disclosed in Patent Document 1. This reference voltage generating circuit 2 is composed of P-channel MOS (Metal Oxide Semiconductor) transistors MP1, MP2, and MP3, diodes D1 and D2 having a size ratio of 1:m, and resistors R10, R20, R11A, and R11B. Here, resistors R11A and R11B have the same resistance value R11.

In this reference voltage generating circuit 2, the MOS transistor MP1 and the diode D1 constitute a first voltage generating section, and the MOS transistor MP2, the resistor R10 and the diode D2 constitute a second voltage generating section. In the reference voltage generating circuit 2, feedback control is performed via the operational amplifier OA0 and the MOS transistors MP1 and MP2, and feedback control is performed via the operational amplifier OA0, the MOS transistor MP3 and the resistors R11A and R11B. As a result, the same current I0 flows through both the diode D1 and the series circuit consisting of the resistor R10 and the diode D2, so as to match the first voltage and the second voltage, which are the voltage drops across both. As a result, the reference voltage VREF shown in the following formula is obtained from both ends of the resistor R20.
VREF
=(3・R20/(R11+3・R20))
・((R10・VT・ln(m)/(3・R10))+VF) ...(1)
Here, VT is the thermal voltage kT/q (k is the Boltzmann constant, T is the temperature, and q is the charge of one electron), and VF is the forward voltage of the diode D1.

In this way, the reference voltage generating circuit 2 obtains a stable reference voltage VREF with respect to temperature T.

JP 2011-181045 A

However, in the conventional reference voltage generating circuit 2 described above, an operational amplifier is used for control to obtain the reference voltage VREF, so when the reference voltage generating circuit 2 is designed with a small area, there is a problem that mismatch variations in which the voltage or current values of each part of the operational amplifier deviate from the design value become large. Here, in order to improve the mismatch variations of the operational amplifier, the area of the operational amplifier needs to be increased, which is unsuitable for a small-area reference voltage generating circuit. Furthermore, when the reference voltage generating circuit is manufactured by a process in which the threshold voltage Vth of the MOS transistor is equal to or greater than the forward voltage VF of the diode, the operating point becomes large if an operational amplifier is used in the reference voltage generating circuit. For this reason, it is necessary to secure the operating point of the operational amplifier using a charge pump circuit or the like, and in that case, the problem occurs that the input voltage is determined by the operating point of the operational amplifier.

This invention was made in consideration of the above-described circumstances, and aims to provide a reference voltage generating circuit that has low mismatch variation, has a small number of components, and can operate at low voltages.

The present invention provides a reference voltage generating circuit including a first voltage generating unit that generates a first voltage and includes a first bipolar transistor having a base and a collector connected thereto and an emitter connected to a reference power supply; a second voltage generating unit that generates a second voltage and includes a second bipolar transistor having a base connected to the base and collector of the first bipolar transistor and an emitter connected to the reference power supply via a resistor; and a control unit that controls a reference voltage by controlling the first voltage and the second voltage based on the collector-emitter voltage of the third bipolar transistor and including a third bipolar transistor having a base and emitter connected to the collector of the second bipolar transistor and the reference power supply.

This invention makes it possible to realize a reference voltage generating circuit that does not use an operational amplifier, has little mismatch variation, requires a small number of components, and can operate at low voltages.

1 is a circuit diagram showing a configuration of a reference voltage generating circuit according to an embodiment of the present invention; FIG. 1 is a circuit diagram showing a configuration of a conventional reference voltage generating circuit.

The following describes an embodiment of the invention with reference to the drawings.

Figure 1 is a circuit diagram showing the configuration of a reference voltage generating circuit 1 according to one embodiment of the present invention. This reference voltage generating circuit 1 is composed of P-channel MOS transistors M0-M2 and M7-M9, N-channel MOS transistors M5 and M6, first to third NPN-type bipolar transistors Q1-Q3, and resistors R1, R2, R3A, and R3B.

Here, the sources and n-wells formed in the MOS transistors M0 to M2 and M7 to M9 are connected to the power supply VCC. The sources and p-wells formed in the MOS transistors M5 and M6 are connected to a reference power supply VSS, which has a lower potential than the power supply VCC.

The first bipolar transistor Q1 and the MOS transistor M7 constitute a first voltage generating section 11 that generates a first voltage V1. Here, the first bipolar transistor Q1 has its base and collector connected, and its emitter connected to a reference power supply VSS. The drain of the MOS transistor M7 is connected to the collector of the first bipolar transistor Q1. The MOS transistor M7 is a first current supply section that supplies a first current I1 to the first bipolar transistor Q1.

The second bipolar transistor Q2 has a base connected to the base and collector of the first bipolar transistor Q1, and an emitter connected to the reference power supply VSS via resistor R1. This second bipolar transistor Q2, resistor R1, and MOS transistor M9 constitute a second voltage generating unit 12 that generates a second voltage V2. Here, the gate of MOS transistor M9 is commonly connected to the gate of MOS transistor M7, and the drain is connected to the collector of second bipolar transistor Q2. This MOS transistor M9 is a second current supply unit that supplies the second bipolar transistor Q2 with a second current I2 that is proportional to the first current I1 supplied to the first bipolar transistor Q1.

In this embodiment, the transistor sizes of MOS transistors M7 and M9 are the same. Therefore, the first and second current supply units supply currents I1 and I2 of the same magnitude to bipolar transistors Q1 and Q2.

The third bipolar transistor Q3, MOS transistors M0 to M2, M5, M6, M8, and resistors R2, R3A, and R3B constitute the control unit 20. This control unit 20 is a circuit that includes the third bipolar transistor Q3 and controls the reference voltage VREF by controlling the first voltage V1 and the second voltage V2 based on the collector-emitter voltage Vce3 of the third bipolar transistor Q3. The configuration of this control unit 20 will be described below.

The collector of the third bipolar transistor Q3 is connected to the drain of the MOS transistor M0 and to the gates of the MOS transistors M0 and M2. The drain of the MOS transistor M2 is connected to the drain of the MOS transistor M5 and the gates of the MOS transistors M7, M9, M8, and M1.

The drain of MOS transistor M8 is connected to the drain of MOS transistor M6 and the gates of MOS transistors M5 and M6. The drain of MOS transistor M1 is connected to the reference power supply VSS via resistor R2.

The connection point between the drain of MOS transistor M1 and resistor R2 is an output node that outputs a reference voltage VOUT. One end of resistors R3A and R3B is connected to this output node. The other end of resistor R3A is connected to the collector of the first bipolar transistor Q1, and the other end of resistor R3B is connected to the collector of the second bipolar transistor Q2.

In this control unit 20, MOS transistors M0, M2, M8, M6, and M5 function as a current control unit that controls the first current I1 and the second current I2 based on the collector-emitter voltage Vce3 of the third bipolar transistor Q3. Specifically, when the second voltage V2 decreases and the collector-emitter voltage Vce3 of the third bipolar transistor Q3 increases, the gate-source voltage Vgs0 of MOS transistor M0 decreases, the drain voltage of MOS transistor M2 decreases, the gate-source voltage of MOS transistor M8 increases, the gate-source voltage of MOS transistor M5 increases, the drain voltage of MOS transistor M2 further decreases, the first current I1 and the second current I2 increase, and the first voltage V1 and the second voltage V2 increase.

In addition, MOS transistors M0, M2, M8, M6, M5, M1 and resistors R2, R3A and R3B function as a circuit that controls a reference voltage VOUT based on the collector-emitter voltage Vce3 of the third bipolar transistor Q3, and feeds back a third current I3 and a fourth current I4 corresponding to this reference voltage VOUT to the first transistor Q1 and the second transistor Q2. Specifically, when the second voltage V2 decreases and the collector-emitter voltage Vce3 of the third bipolar transistor Q3 increases, the gate-source voltage Vgs0 of the MOS transistor M0 decreases, the drain voltage of the MOS transistor M2 decreases, the drain current of the MOS transistor M1 increases, the reference voltage VOUT is determined by the current obtained by subtracting the third current I3 and the fourth current I4 from this drain current, and the first voltage V1 and the second voltage V2 increase as a result of the third current I3 and the fourth current I4 being added to the first current I1 and the second current I2.

Next, the operation of this embodiment will be described. In the reference voltage generating circuit 1, control is performed to make the first voltage V1 and the second voltage V2 equal while making the current flowing through the first bipolar transistor Q1 and the current flowing through the second bipolar transistor Q2 equal. As a result of this control, the reference voltage VOUT shown in the following formula is output from the reference voltage generating circuit 1.
VOUT
=(3・R2/(R3+3・R2))・((R3・VT・In(m)/(3・R1))
+Vbe) ...(2)
Here, R3=R3A=R3B, m is the size ratio of the bipolar transistors Q1 and Q2 (that is, Q1:Q2=1:m), VT is the thermal voltage, and Vbe is the base-emitter voltage Vbe1 of the first bipolar transistor Q1.

In the conventional technology (Figure 2), the operational amplifier OA0 is used to control the first voltage generated in the diode D1 to match the second voltage generated in the series circuit consisting of the resistor R10 and the diode D2.

In contrast, in this embodiment, control is performed to match the first voltage V1 and the second voltage V2 using current feedback, as described below.

In the following, it is assumed that the sizes of MOS transistors M0 to M2 and M7 to M9 are the same, and that the sizes of MOS transistors M5 and M6 are the same.

1, the collector voltage Vc1 (i.e., the first voltage V1) of the first bipolar transistor Q1 is equal to the base-emitter voltage Vbe1 of the bipolar transistor Q1. Therefore, the emitter current Ie1 flowing through the bipolar transistor Q1 is expressed by the following equation.
Ie1
=(VT・ln(m)/R1)-((VOUT-Vbe)/R3)+Ib1+Ib2
… (3)
Here, Ib1 is the base current of the first bipolar transistor Q1, and Ib2 is the base current of the second bipolar transistor Q2.

The collector voltage Vc2 (i.e., the second voltage V2) of the second bipolar transistor Q2 coincides with the base-emitter voltage Vbe3 of the bipolar transistor Q3. Therefore, the emitter current Ie2 flowing through the bipolar transistor Q2 is expressed by the following equation.
Ie2
=(VT・ln(m)/R1)-((VOUT-Vbe)/R3)+Ib3
… (4)

In the above expressions (3) and (4), the base currents Ib1, Ib2, and Ib3 of the bipolar transistors Q1, Q2, and Q3 are very small, so Ie1=Ie2, Vbe1=Vbe2, and Vc1=Vc2 (i.e., V1=V2).
As a result, equation (2) holds for the reference voltage VOUT.

Next, mismatch variation will be explained. In general, the base-emitter voltage Vbe of a bipolar transistor has smaller variation than that of an operational amplifier. In particular, low-voltage bipolar transistors have a lower degree of mismatch variation than operational amplifiers when their area is reduced. According to this embodiment, an operational amplifier is not used, and control is performed to match the first voltage V1 and the second voltage V2 by current feedback using the third bipolar transistor Q3 described above, thereby reducing mismatch variation.

Next, the operating point of the reference voltage generating circuit will be described. In the above-mentioned conventional reference voltage generating circuit 2 (FIG. 2), the operating point of the operational amplifier OA0 is as follows. In FIG. 2, the diodes D1 and D2 are diode-connected bipolar transistors, the base-emitter voltage of the bipolar transistors is Vbe, the overdrive voltage of the MOS transistors MP1 and MP2 is Vov, and the gate-source voltage of the P-channel MOS transistor used in the differential pair of the operational amplifier OA0 is Vgs. In this case, the power supply voltage VCC must satisfy the condition VCC>Vbe+Vgs+Vov. For example, if Vbe=Vgs=0.7V and Vov=0.1V, the lower limit of the power supply voltage VCC at which the reference voltage generating circuit can operate is 1.5V. In this way, when an operational amplifier is used in the reference voltage generating circuit, it is difficult to operate it at a low voltage, and in order to operate it at a low voltage, it is necessary to combine the operational amplifier with a boost circuit such as a charge pump circuit, which is expected to increase the area of the circuit.

In addition, if N-channel MOS transistors are used instead of the P-channel MOS transistors in the differential pair of operational amplifier OA0, the condition Vov>Vbe-Vgs must be satisfied due to the limitations on the input range of this N-channel MOS transistor. Here, if Vbe<Vgs, it is impossible to pass current through diode D1 and the MOS transistor. Also, in order for the reference voltage generation circuit to operate normally at low voltages, it must be designed using a process with a small Vth, but the design is subject to process limitations.

In this embodiment, when the overdrive voltages of MOS transistors M7 and M1 are Vov7 and Vov1, in order for the reference voltage generation circuit to operate normally, it is sufficient to satisfy the conditions VCC>Vbe1+Vov7, Vce3>VCC-Vgs0, and VCC>VOUT+Vov1, and other blocks such as a charge pump circuit are not required, making low-voltage operation possible independent of the process.

<Other embodiments>
Although the embodiments of the present invention have been described above, other embodiments are also possible.

(1) In the above embodiment, the first current supply unit that supplies the first current I1 to the first bipolar transistor Q1 and the second current supply unit that supplies the second current I2 to the second bipolar transistor Q2 are configured with MOS transistors, but they may also be configured with bipolar transistors.

(2) In the above embodiment, a reference voltage generating circuit that generates a negative reference voltage may be configured by replacing the P-channel MOS transistors with N-channel MOS transistors, replacing the N-channel MOS transistors with P-channel MOS transistors, replacing the NPN bipolar transistors with PNP bipolar transistors, and replacing the power supply VCC with a negative power supply with respect to the reference power supply VSS.

(3) In the above embodiment, for simplicity, a configuration in which I1 = I2 and I3 = I4 has been described, but I1 ≠ I2 and I3 ≠ I4 may also be true.

Q1...first bipolar transistor, Q2...second bipolar transistor, Q3...third bipolar transistor, 11...first voltage generating unit, 12...second voltage generating unit, 20...control unit, M0 to M2, M5 to M9, MP1 to MP3...MOS transistors, R1, R1, R3A, R3B, R10, R20, R11A, R11B...resistors, OA0...op-amp, D1, D2...diodes.

Claims (1)

a first voltage generating section including a first bipolar transistor having a base connected to a collector and an emitter connected to a reference power supply, the first voltage generating section generating a first voltage;
a second voltage generating section including a second bipolar transistor having a base connected to the base and collector of the first bipolar transistor and an emitter connected to the reference power supply via a resistor, the second voltage generating section generating a second voltage;
a control unit including a third bipolar transistor having a base connected to the collector of the second bipolar transistor and an emitter connected to the reference power supply, the control unit controlling a reference voltage by controlling the first voltage and the second voltage based on a collector-emitter voltage of the third bipolar transistor;
Including,
the first voltage generating unit and the second voltage generating unit each include a first current supply unit and a second current supply unit that supply a first current and a second current, which are proportional to the first bipolar transistor and the second bipolar transistor, respectively;
the control unit includes a current control unit that controls the first current and the second current based on a collector-emitter voltage of the third bipolar transistor;
the control unit controls the reference voltage based on a collector-emitter voltage of the third bipolar transistor, and feeds back a third current and a fourth current corresponding to the reference voltage to the first bipolar transistor and the second bipolar transistor.
Reference voltage generation circuit.

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