JP7683453B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device having a trench gate structure and a method for manufacturing the same.

Conventionally, semiconductor devices in which semiconductor elements such as MOSFETs (short for metal oxide semiconductor field effect transistors) are formed have been proposed. Specifically, this semiconductor device includes a semiconductor substrate having a drift layer, a base layer formed on one surface side of the semiconductor substrate, and a source region formed on the surface layer of the base layer. In addition, the semiconductor substrate is formed with a plurality of trenches that penetrate the source region and the base layer and extend along one direction in the surface direction of the semiconductor substrate. A gate insulating film and a gate electrode are disposed in the trenches to form a trench gate structure. The opening of the trench has a shape with a corner where the side surface of the trench and one surface of the semiconductor substrate are approximately perpendicular.

A drain region is disposed on the other side of the semiconductor substrate. A first electrode is disposed on one side of the semiconductor substrate so as to be electrically connected to the source region and the base layer. A second electrode is disposed on the other side of the semiconductor substrate so as to be electrically connected to the drain region. Also, a connection wiring is formed on one side of the semiconductor substrate so as to be connected to the gate electrode.

In the semiconductor device described above, the gate voltage is likely to concentrate in the portion where the gate electrode and the connection wiring are connected and located above the opening of the trench. For this reason, in such a semiconductor device, there is a concern that the characteristics of the gate insulating film located at the opening of the trench, where the gate electrode and the connection wiring are connected, may deteriorate. Note that a deterioration in the characteristics of the gate insulating film means an increase in the leakage current of the gate insulating film, a decrease in the breakdown voltage of the gate insulating film, or a decrease in the lifespan of the gate insulating film.

For this reason, for example, Patent Document 1 proposes a structure in which the opening of the trench is rounded so that voltage concentration is less likely to occur near the opening of the trench. In this structure, the entire area of the opening of the trench is rounded.

Japanese Patent Application Publication No. 5-226324

In the semiconductor device described above, it has been considered to increase the current capacity by shortening the distance between adjacent trenches. In this case, if the entire area of the trench opening is rounded, the source region formed in contact with the trench will have a smaller area exposed from one surface of the semiconductor substrate. This can reduce the connectivity between the first electrode and the source region, resulting in a connection failure.

In view of the above, the present invention aims to provide a semiconductor device and a manufacturing method thereof that can suppress the occurrence of connection defects in the first electrode while suppressing the deterioration of the characteristics of the gate insulating film.

Claim 1 for achieving the above object provides a semiconductor device having a plurality of trench gate structures formed therein, the semiconductor substrate having a first conductivity type drift layer (12), a second conductivity type base layer (13) formed on the drift layer, a first conductivity type impurity region (14) formed in a surface layer portion of the base layer, and a first conductivity type or second conductivity type high concentration layer (11) formed on the opposite side of the base layer with the drift layer sandwiched therebetween and having a higher impurity concentration than the drift layer, a plurality of trench gate structures in which a gate electrode (18) is disposed via a gate insulating film (17) in a trench (16) extending through the impurity region and the base layer to reach the drift layer and extending in a predetermined direction, a connection wiring (180) formed on the semiconductor substrate and electrically connected to the gate electrode, a first electrode (20) electrically connected to the base layer and the impurity region, and a second electrode (22) electrically connected to the high concentration layer. The trench has a rounded portion (161) formed at a connection opening (160a) that is covered by the connection portion between the gate electrode and the connection wiring, and if the portion of the trench opening that is different from the connection opening is an unconnected opening (160b), the unconnected opening has a portion whose radius of curvature is smaller than the radius of curvature of the connection opening , and the connection opening is in a direction intersecting the longitudinal direction, and if the length between adjacent trenches in a direction along the surface direction of the semiconductor substrate is L, the radius of curvature of the rounded portion is less than L/2.

According to this, the trench has a rounded portion formed at the connection opening. This makes it possible to prevent voltage concentration on the connection opening and to prevent the characteristics of the gate insulating film from deteriorating.

The unconnected opening has a portion where the radius of curvature is smaller than the radius of curvature of the connection opening. In other words, the unconnected opening has a portion where the opening width is narrower than the connection opening. Therefore, in the portion between adjacent trenches located between the unconnected openings where the curvature is smaller, it is easier to ensure the connection area between the first electrode and the base layer or impurity region. This makes it possible to suppress the occurrence of connection defects in the first electrode.

Claim 2 is a manufacturing method for the semiconductor device of claim 1, which includes the steps of preparing a semiconductor substrate having a drift layer, a base layer, and an impurity region, forming a trench in the semiconductor substrate, placing a mask (30) that exposes a portion of the trench opening that will become a connection opening while covering a portion that will become an unconnected opening, and forming a rounded portion of the base layer at the connection opening with the mask in place.

By forming a rounded portion at the connection opening of the trench, it is possible to suppress voltage concentration at the connection opening, and to manufacture a semiconductor device that suppresses deterioration of the characteristics of the gate insulating film.

The unconnected opening is formed to have a portion where the radius of curvature is smaller than the radius of curvature of the connection opening. Therefore, in the portion between adjacent trenches located between the unconnected openings where the curvature is smaller, it is easier to ensure the connection area between the first electrode and the base layer or impurity region. Therefore, it is possible to manufacture a semiconductor device in which the occurrence of connection defects in the first electrode is suppressed.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

1 is a plan view of a semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 2 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. 2 . 5B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5A. 5C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5B. 4A to 4C are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. 3. 6B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 6A. 6C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 6B. 5A to 5C are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. 7B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 7A. 7B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 7B. 7D is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 7C. FIG. 11 is a plan view of a semiconductor device according to a modified example of the first embodiment. FIG. 11 is a plan view of a semiconductor device according to a modified example of the first embodiment. FIG. 11 is a plan view of a semiconductor device according to a modified example of the first embodiment. FIG. 11 is a plan view of a semiconductor device according to a modified example of the first embodiment. FIG. 11 is a plan view of a semiconductor device according to a modified example of the first embodiment.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
The first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is preferably applied as a device for driving various electronic devices for a vehicle, for example, mounted on a vehicle such as an automobile. In the present embodiment, a semiconductor device in which a trench gate structure is formed on a semiconductor substrate 10 made of silicon carbide (hereinafter also referred to as SiC) will be described.

As shown in FIG. 1, the semiconductor device of this embodiment has a cell region 1 in which a MOSFET with a trench gate structure is formed, and a peripheral region 2 surrounding this cell region 1. Although the configuration of the peripheral region 2 will not be described in detail, in this embodiment, a frame-shaped FLR (abbreviation of Field Limiting Ring) portion 2a is formed in the peripheral region 2 so as to surround the cell region 1. FIG. 1 is a plan view in which an interlayer insulating film 19 and an upper electrode 20, which will be described later, are omitted as appropriate. Furthermore, although FIG. 1 is not a cross-sectional view, a gate insulating film 17 and a gate electrode 18, which will be described later, are hatched to make it easier to understand.

As shown in FIG. 2 to FIG. 4, the semiconductor device is configured using a semiconductor substrate 10 made of SiC. Specifically, the semiconductor substrate 10 has an n ⁺ type substrate 11 made of SiC. An n ^- type drift layer 12 and a p type base layer 13, both made of SiC, are epitaxially grown in this order on the surface of the substrate 11. An n ⁺ type source region 14 and a p ⁺ type contact region 15 are formed in the surface layer of the base layer 13. As will be described later in detail, the source region 14 is formed so as to contact the side of a trench 16, which will be described later, and the contact region 15 is formed on the opposite side of the trench 16, which will be described later, with the source region 14 sandwiched therebetween. In this embodiment, the substrate 11 corresponds to a high concentration layer, and the source region 14 corresponds to an impurity region.

The substrate 11 has, for example, an n-type impurity concentration of 1.0×10 ¹⁹ /cm ³ and a (0001) Si surface. The drift layer 12 has, for example, an n-type impurity concentration of 0.5 to 2.0×10 ¹⁶ /cm ³ and a thickness of 5 to 14 μm. In this embodiment, the substrate 11 constitutes a drain layer in a MOSFET.

The base layer 13 is a portion where a channel region is formed, and has, for example, a p-type impurity concentration of about 3.0×10 ¹⁷ /cm ³ and a thickness of 0.5 to 2 μm. The source region 14 has a higher impurity concentration than the drift layer 12, and has, for example, an n-type impurity concentration in the surface layer of 2.5×10 ¹⁸ to 1.0×10 ¹⁹ /cm ³ and a thickness of 0.5 to 2 μm. The contact region 15 has a higher impurity concentration than the base layer 13, and has a p-type impurity concentration of 1.0×10 ¹⁸ /cm ³ to 1.0×10 ²⁰ /cm ^3. The impurity concentrations and film thicknesses of the drift layer 12, the base layer 13, the source region 14, and the contact region 15 are arbitrary and are not limited to the above.

Then, a plurality of trenches 16 are formed in the semiconductor substrate 10 so as to penetrate the base layer 13 and the source region 14 and reach the drift layer 12. Therefore, the source region 14 is formed so as to contact the side surface of each trench 16.

The multiple trenches 16 extend in one direction on the surface of the semiconductor substrate 10 as the longitudinal direction, and are formed in stripes arranged at equal intervals in a direction intersecting the longitudinal direction. In this embodiment, the multiple trenches 16 extend in the left-right direction of the paper in FIG. 1 and are arranged in the up-down direction of the paper. Hereinafter, the arrangement direction of the multiple trenches 16 is also simply referred to as the arrangement direction. The source region 14 and the contact region 15 are formed to terminate inside the trench 16 in the longitudinal direction of the trench 16.

A gate insulating film 17 is formed on the inner wall surface of the trench 16. A gate electrode 18 made of doped polysilicon is formed on the surface of the gate insulating film 17. The trench 16 is filled with the gate insulating film 17 and the gate electrode 18. In this embodiment, the trench gate structure is configured in this manner.

The gate insulating film 17 is also formed on surfaces other than the inner wall surface of the trench 16. Specifically, as shown in FIG. 2, the gate insulating film 17 is formed so as to cover a portion of one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 17 is formed so as to cover a portion of the surface of the source region 14. In other words, the gate insulating film 17 has a contact hole 17a that exposes the source region 14 and the contact region 15. However, in this embodiment, as shown in FIG. 3 and FIG. 4, the gate insulating film 17 is formed so as to cover the base layer 13, the source region 14, and the contact region 15 at the end side in the longitudinal direction of the trench 16.

In this embodiment, at the end of the trench 16 in the longitudinal direction, the gate electrode 18 is pulled out onto one surface 10a of the semiconductor substrate 10, and the pulled out portion serves as a connection wiring 180. Note that the connection wiring 180 in this embodiment extends along the arrangement direction so as to connect adjacent gate electrodes 18 along the arrangement direction.

3 and 4, the opening of the trench 16 (i.e., the shoulder opposite the bottom) is covered with the connection between the gate electrode 18 and the connection wiring 180 as the connection opening 160a. In other words, the part of the opening of the trench 16 that overlaps with the connection wiring 160 is the connection opening 160a. Also, as shown in FIG. 2, the part of the opening of the trench 16 that is different from the connection opening 160a is the unconnected opening 160b. In this case, as shown in FIG. 3 and 4, in this embodiment, the connection opening 160a has a rounded portion 161 that rounds the opening. On the other hand, as shown in FIG. 2, the unconnected opening 160b does not have the rounded portion 161, and the angle between the side of the trench 16 and one surface 10a of the semiconductor substrate 10 is approximately perpendicular.

For this reason, the unconnected opening 160b has a smaller radius of curvature than the connection opening 160a. In other words, the unconnected opening 160b has a narrower opening width than the connection opening 160a. And, on one surface 10a of the semiconductor substrate 10, in the length between adjacent trenches 16 along the arrangement direction, the length L1 of the portion located between the connection openings 160a is shorter than the length L2 of the portion located between the unconnected openings 160b. Hereinafter, adjacent trenches 16 along the arrangement direction are also simply referred to as adjacent trenches 16.

In addition, in this embodiment, the rounded portion 161 is formed so that the radius of curvature of the rounded portion 161 is less than L/2, where L is the length between adjacent trenches 16. In other words, the rounded portion 161 is formed so that at least the length L1 is not 0. In other words, the rounded portion 161 is formed so that no sharp portion is formed between adjacent trenches 16.

An interlayer insulating film 19 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the source region 14, the contact region 15, the gate electrode 18, the connection wiring 180, and the like. As shown in FIG. 2, the interlayer insulating film 19 is formed with a contact hole 19a that communicates with the contact hole 17a and exposes the source region 14 and the contact region 15. As shown in FIG. 4, the interlayer insulating film 19 is formed with a contact hole 19b that exposes the connection wiring 180. In this embodiment, the contact hole 19a for exposing the source region 14 and the contact region 15 is not formed on the end side in the longitudinal direction of the trench 16.

2, an upper electrode 20 is formed on the interlayer insulating film 19, which is electrically connected to the source region 14 and the contact region 15 through the contact holes 17a and 19a. In this embodiment, the upper electrode 20 is made of a plurality of metals, such as Ni/Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 14) is made of a metal that can make ohmic contact with the n-type SiC. The portion of the plurality of metals that contacts at least the p-type SiC (i.e., the contact region 15) is made of a metal that can make ohmic contact with the p-type SiC. In this embodiment, the upper electrode 20 corresponds to the first electrode.

Also, as shown in FIG. 4, a gate wiring 21 is formed on the interlayer insulating film 19, and is connected to the connection wiring 180 through a contact hole 19b. The gate wiring 21 may be made of the same material as the upper electrode 20, or may be made of a different material.

As described above, the interlayer insulating film 19 does not have a contact hole 19a formed on the end side of the trench 16 in the longitudinal direction. Therefore, the source region 14 and the contact region 15 on the end side of the trench 16 in the longitudinal direction are not directly connected to the upper electrode 20.

A lower electrode 22, which corresponds to a second electrode electrically connected to the substrate 11, is formed on the back surface side of the substrate 11. In this embodiment, this structure constitutes an n-channel type inversion type trench gate structure MOSFET.

The above is the configuration of the semiconductor device in this embodiment. In this embodiment, n ⁺ type and n ^- type correspond to the first conductivity type, and p ^- type, p type, and p ⁺ type correspond to the second conductivity type. As described above, the semiconductor substrate 10 in this embodiment is configured to include the substrate 11, drift layer 12, base layer 13, source region 14, contact region 15, etc.

Next, the operation and effects of the semiconductor device will be described. In such a semiconductor device, a gate voltage equal to or greater than a predetermined threshold voltage is applied to the gate electrode 18, forming an n-type inversion layer (i.e., a channel region) in the portion of the base layer 13 that contacts the trench 16. Then, electrons are supplied from the source region 14 through the inversion layer to the drift layer 12, causing a current to flow between the upper electrode 20 and the lower electrode 22.

At this time, voltage concentration of the gate voltage is likely to occur at the portion where the gate electrode 18 and the connection wiring 180 are connected and located above the opening of the trench 16. For this reason, in this embodiment, a rounded portion 161 is formed at the connection opening 160a of the trench 16. This makes it possible to prevent voltage concentration from occurring above the connection opening 160a, and to prevent the characteristics of the gate insulating film 17 from deteriorating.

In addition, in the trench 16 of this embodiment, the rounded portion 161 is not formed in the unconnected opening 160b, and the length L2 is longer than the length L1. Therefore, in the portion located between the unconnected openings 160b of adjacent trenches 16, it is easier to ensure the connection area between the upper electrode 20 and the source region 14 and contact region 15. Therefore, it is possible to suppress the occurrence of connection failure between the upper electrode 20 and the source region 14 and contact region 15.

Next, the manufacturing method of the semiconductor device will be described with reference to Figures 5A to 5C, 6A to 6C, and 7A to 7D. Note that Figures 5A to 5C are cross-sectional views corresponding to Figure 2, Figures 6A to 6C are cross-sectional views corresponding to Figure 3, and Figures 7A to 7D are cross-sectional views corresponding to Figure 4.

First, as shown in Figures 5A, 6A, and 7A, a semiconductor substrate 10 is prepared in which a substrate 11, a drift layer 12, a base layer 13, a source region 14, a contact region 15, etc. are formed. Then, a mask (not shown) is placed on one surface 10a of the semiconductor substrate 10, and dry etching or the like is performed to form multiple trenches 16 of the above shape.

Next, as shown in Figs. 5B and 7B, a mask 30 is placed to cover the portion of the trench 16 that will become the unconnected opening 160b while exposing the portion of the trench 16 that will become the connection opening 160a. The mask 30 is made of a heat-resistant material, such as a carbon film.

Next, as shown in Figures 6B and 7C, a rounding process is performed so that rounded portions 161 are formed in the portions that will become the connection openings 160a. In this embodiment, rounding process is performed by heating in a hydrogen atmosphere or an argon atmosphere, thereby forming rounded portions 161 in the portions that will become the connection openings 160a. In this process, since a heating process is performed, damage to the side surfaces of the trenches 16 is also reduced.

After that, as shown in Figures 5C, 6C, and 7D, a typical semiconductor manufacturing process is performed, and although detailed explanations are omitted, the gate insulating film 17, gate electrode 18, connection wiring 180, interlayer insulating film 19, upper electrode 20, lower electrode 22, etc. are formed in that order. Note that when forming the gate electrode 18 and connection wiring 180, polysilicon is formed in the trench 16 by a CVD (short for Chemical Vapor Deposition) method or the like to form the gate electrode 18. Then, the polysilicon formed on one surface 10a of the semiconductor substrate 10 is patterned to form the connection wiring 180 connected to the gate electrode 18.

According to the present embodiment described above, the trench 16 has a rounded portion 161 formed at the connection opening 160a. This makes it possible to prevent voltage concentration from occurring on the connection opening 160a, and to prevent the characteristics of the gate insulating film 17 from deteriorating.

In addition, the trench 16 does not have a rounded portion 161 formed in the unconnected opening 160b, and the length L2 is longer than the length L1. Therefore, in the portion located between the unconnected openings 160b of adjacent trenches 16, it is easy to ensure the connection area between the upper electrode 20 and the source region 14 and contact region 15. Therefore, it is possible to suppress the occurrence of connection failures between the upper electrode 20 and the source region 14 and contact region 15.

(1) In this embodiment, the radius of curvature of the connection opening 160a is less than L/2. This makes it possible to prevent sharp portions from being formed between the connection openings 160a of adjacent trenches 16 on one surface 10a of the semiconductor substrate 10. This makes it possible to prevent stress from concentrating at a specific location of the gate insulating film 17 disposed between the connection openings 160a of adjacent trenches 16, thereby making it possible to prevent the gate insulating film 17 from being destroyed.

(Modification of the first embodiment)
A modified example of the first embodiment will be described. In the first embodiment, the position where the connection wiring 180 is formed can be changed as appropriate. In other words, in the first embodiment, the positional relationship between the portion that becomes the connection opening 160a and the portion that becomes the unconnected opening 160b can be changed as appropriate.

For example, as shown in FIG. 8A, the connection wiring 180 may be formed so that both ends and a middle part in the longitudinal direction of the opening of the trench 16 become the connection openings 160a. Also, as shown in FIG. 8B, the connection wiring 180 may be formed so that the connection openings 160a are not formed at both ends in the longitudinal direction of the opening of the trench 16, but only in the middle part. In this case, as shown in FIG. 8C, the connection wiring 180 may be formed in a plurality of pieces so that the connection openings 160a are formed at a plurality of places in the middle part of the opening of the trench 16. Furthermore, as shown in FIG. 8D, the connection wiring 180 may not be formed so as to connect adjacent gate electrodes 18 to each other, but may be divided in the arrangement direction. And, as shown in FIG. 8E, the connection wiring 180 may be formed so that only one end of both ends in the longitudinal direction of the opening of the trench 16 becomes the connection opening 160a.

Other Embodiments
Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in the first embodiment, a semiconductor device is described in which a MOSFET of a trench gate structure of an n-channel type in which the first conductivity type is n-type and the second conductivity type is p-type is formed. However, the semiconductor device may be configured, for example, by forming a MOSFET of a trench gate structure of a p-channel type in which the conductivity type of each component is inverted with respect to the n-channel type. Furthermore, the semiconductor device may be configured to have an IGBT of a similar structure formed therein in addition to the MOSFET. In the case of the IGBT, it is the same as the vertical MOSFET described in the first embodiment, except that the n ⁺ type substrate 11 in the first embodiment is changed to a P ⁺ type collector layer. Furthermore, the semiconductor device may be configured to have other semiconductor elements such as a diode formed therein in addition to the MOSFET.

In the above first embodiment, a semiconductor device in which the semiconductor substrate 10 is made of SiC has been described as an example, but the semiconductor substrate 10 may be made of a silicon substrate, a compound substrate, or the like. In addition, when the semiconductor substrate 10 is made of a silicon substrate or the like, the portion that will become the drain region may be formed by ion implantation or the like after the semiconductor substrate 10 is prepared.

Furthermore, in the above first embodiment, an example was described in which the rounded portion 161 is formed in the connection opening 160a, and the rounded portion 161 is not formed in the unconnected opening 160b. However, for example, the rounded portion 161 may be formed in the portion of the unconnected opening 160b on the connection opening 160a side. That is, the unconnected opening 160b may be formed so as to have a portion whose radius of curvature is smaller than the radius of curvature of the connection opening 160a. In this way, the rounded portion 161 is not formed in the portion of the unconnected opening 160b where the radius of curvature is smaller, so that the occurrence of poor connection of the upper electrode 20 can be suppressed.

In the above first embodiment, an example was described in which the upper electrode 20 is not connected to the source region 14, etc., at the end side in the longitudinal direction of the trench 16. However, the upper electrode 20 may be arranged so as to be connected to the source region 14, etc., even at the end side in the longitudinal direction of the trench 16.

Furthermore, in the first embodiment, the rounding process for forming the rounded portion 161 may be performed by an isotropic CDE (i.e., chemical dry etching) method or dry etching method, etc., after forming the trench 16 and placing the mask 30. When the rounding process is performed by such a method, it is possible to suppress unnecessary diffusion of impurities constituting the source region 14 and the contact region 15, compared to the case of performing a heat treatment, particularly when the semiconductor substrate 10 is a silicon substrate.

11 Substrate (high concentration layer)
12 Drift layer 13 Base layer 14 Source region (impurity region)
16 Trench 17 Gate insulating film 18 Gate electrode 20 Upper electrode (first electrode)
22 Lower electrode (second electrode)
160a: Connection opening 160b: Unconnected opening 161: Rounded portion 180: Connection wiring

Claims (4)

A semiconductor device having a plurality of trench gate structures formed therein,
A drift layer (12) of a first conductivity type;
a base layer (13) of a second conductivity type formed on the drift layer;
a first conductivity type impurity region (14) formed in a surface layer portion of the base layer;
a high-concentration layer (11) of a first conductivity type or a second conductivity type formed on the opposite side of the drift layer from the base layer and having a higher impurity concentration than the drift layer;
the plurality of trench gate structures each having a gate electrode (18) disposed via a gate insulating film (17) in a trench (16) extending in a predetermined direction, the trench (16) penetrating the impurity region and the base layer to reach the drift layer, and the trench (16) extending in a predetermined direction;
A connection wiring (180) formed on the semiconductor substrate and electrically connected to the gate electrode;
a first electrode (20) electrically connected to the base layer and the impurity region;
a second electrode (22) electrically connected to the high concentration layer;
The trench has a rounded portion (161) formed in a connection opening (160a) that is covered with a connection portion between the gate electrode and the connection wiring,
When a portion of the trench opening that is different from the connection opening is defined as an unconnected opening (160b), the unconnected opening has a portion whose radius of curvature is smaller than the radius of curvature of the connection opening ,
The connection opening is in a direction intersecting the longitudinal direction, and the length between adjacent trenches in a direction along the surface direction of the semiconductor substrate is L, where L is the length between the adjacent trenches, and the radius of curvature of the rounded portion is less than L/2 . A drift layer (12) of a first conductivity type;
a base layer (13) of a second conductivity type formed on the drift layer;
a first conductivity type impurity region (14) formed in a surface layer portion of the base layer;
a high-concentration layer (11) of a first conductivity type or a second conductivity type formed on the opposite side of the drift layer from the base layer and having a higher impurity concentration than the drift layer;
a plurality of trench gate structures in which a gate electrode (18) is disposed via a gate insulating film (17) in a trench (16) extending in a predetermined direction, the trench (16) penetrating the impurity region and the base layer to reach the drift layer, and the gate electrode (18) is disposed in the trench (16) with the gate insulating film (17) interposed therebetween;
A connection wiring (180) formed on the semiconductor substrate and electrically connected to the gate electrode;
a first electrode (20) electrically connected to the base layer and the impurity region;
a second electrode (22) electrically connected to the high concentration layer;
The trench has a rounded portion (161) formed in a connection opening (160a) that is covered with a connection portion between the gate electrode and the connection wiring,
A method for manufacturing a semiconductor device, comprising the steps of: assuming that a portion of the trench opening different from the connection opening is an unconnected opening (160b), the unconnected opening has a portion having a radius of curvature smaller than the radius of curvature of the connection opening,
preparing a semiconductor substrate having the drift layer, the base layer, and the impurity region;
forming the trench in the semiconductor substrate;
disposing a mask (30) that exposes a portion of the trench opening that will become the connection opening and covers a portion of the trench opening that will become the unconnected opening;
and forming a rounded portion in the connection opening with the mask in place. The method for manufacturing a semiconductor device according to claim 2 , wherein the step of forming the rounded portion comprises forming the rounded portion in the connection opening portion by performing a heat treatment. 3. The method for manufacturing a semiconductor device according to claim 2 , wherein the rounded portion is formed in the connection opening by an isotropic chemical dry etching method or a dry etching method.

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