JP7685738B2 - Waveform generation circuit - Google Patents

Description

The present invention relates to a waveform generating circuit, and more specifically, to a waveform generating circuit that outputs an arbitrary waveform.

A waveform generation circuit that can generate an arbitrary waveform is known to be one that uses the Digital Direct Synthesis (DDS) method. This type of waveform generation circuit can output a periodic signal having a desired waveform by, for example, storing one cycle's worth of waveform data in a waveform memory, sequentially reading out the waveform data for each clock cycle, and outputting the read data as an analog signal via a DA converter.

Regarding such signal generators, for example, the synthesizer disclosed in Patent Document 1 realizes a synthesizer that can perform accurate, high-resolution edge placement without requiring a system clock with a frequency much higher than the frequency of the synthesized clock signal.

JP 2004-229326 A

In conventional DDS-type waveform generation circuits, the output frequency is changed by setting an increment for each clock using a phase adder. However, in the case of a waveform that has a portion where the signal magnitude changes suddenly, such as a square wave, it is inevitable that jitter will occur at the point where the waveform suddenly changes depending on the output frequency. In response to the problems with such conventional waveform generation circuits, the invention in Patent Document 1 aims to reduce jitter by using a comparator on a sine wave that has passed through a bandpass filter, for example, when generating a signal such as a square wave, which is represented by a clock. However, there is a problem in that the low-jitter output waveform obtained by this method is limited to specific waveforms such as a square wave, and is not effective for waveforms of arbitrary shapes.

The present invention aims to provide a faster, less expensive waveform generation circuit that has the effect of low jitter when generating arbitrary waveforms.

In order to achieve the above object, the waveform generation circuit of the present invention is a DDS type waveform generation circuit comprising: an accumulator which adds and outputs a phase addition value for each clock; a waveform memory which stores waveform data of a digitized waveform output and uses the upper bits of the output of the accumulator as an address input ; a data processing section which uses the output of the accumulator and the data output of the waveform memory as inputs, reads the waveform data from the waveform memory for each clock, and generates and outputs waveform processed data corrected at sudden changes in the waveform data based on the read waveform data and the lower bits excluding the upper bits of the output of the accumulator; a DA converter which receives the waveform processed data as a data input and converts the data input into an analog signal; and a low pass filter which smooths the analog signal output waveform from the DA converter to produce an output signal , and is characterized in reducing jitter .

In the above configuration, when the period of the output signal is TO _and the period of the clock is _TACLK , a positive integer N is selected to satisfy N≦TO _/ TACLK _, the number of data points of the waveform data is N, the N pieces of waveform data are written to the waveform memory, and the phase addition value is Δθ, where Δθ is expressed as Δθ=N· _TACLK / _To and its value is 1 or less, and when the value of the upper bit of the output of the accumulator exceeds N, it is preferable that the operation is performed by returning to 0, and the operation is performed using consecutive adjacent waveform data .

a waveform memory storing waveform data of a digitized waveform output; a configuration for generating a waveform memory clock to be supplied to the waveform memory each time the value of the upper bits of the output of the accumulator increases, and supplying the clock to the waveform memory when the value of the upper bits of the output of the accumulator exceeds the number of data points of the waveform data; and a data processing section having an input of the output of the accumulator and the data output of the waveform memory, reading out the waveform data from the waveform memory for each clock for the waveform memory, and generating and outputting waveform processed data corrected at locations where the waveform data changes suddenly, based on the read waveform data and the lower bits of the output of the accumulator other than the upper bits; a D/A converter having the waveform processed data as a data input and converting the data input into an analog signal; and a low pass filter smoothing the analog signal output waveform from the D/A converter to produce an output signal, thereby reducing jitter.

In the above configuration, it is preferable that the data processing unit is configured to add correction necessity information to the waveform data read out from the waveform memory, and to determine whether or not to correct the waveform data based on the correction necessity information.

In the above configuration, it is preferable that, for the waveform data that does not require correction , numerical information of the waveform output is written also in the data portion of the correction necessity information.

Furthermore, when the phase addition value is Δθ, the value obtained by replacing the lower-order bit data with a decimal point is D _U , the correction coefficient k is k=(1-D _U )/Δθ, the clock period is T _ACLK , the waveform data at time T _X is Da(T _X ), and the waveform data at the sampling time immediately preceding that is Da(T _X -T _ACLK ), it is preferable that a data generation section included in the data processing section outputs data of k·Da(T _X )+(1-k)·Da(T _X -T _ACLK ) based on the correction coefficient k.

The present invention reduces jitter compared to conventional waveform generation circuits, and also makes it possible to create a faster and cheaper waveform generation circuit.

FIG. 2 is a diagram illustrating a configuration example of a waveform generating circuit according to the first embodiment; FIG. 13 is a diagram illustrating an example of an accumulator output. 1A and 1B are diagrams illustrating examples of input and output signals of a low-pass filter. FIG. 2 illustrates an example of the configuration of a data processing unit. FIG. 4 illustrates an example of the configuration of a data generating unit; FIG. 13 is a diagram illustrating an example of a square wave output. FIG. 13 is a diagram illustrating a configuration example of a waveform generating circuit according to a third embodiment. FIG. 13 illustrates an example of a configuration of a correction determination unit according to a fourth embodiment; FIG. 13 illustrates an example of a configuration of a correction determination unit according to a fifth embodiment;

The following describes the embodiments of the present invention. However, the present invention is not limited to the following description, and various modifications and changes are possible for those skilled in the art based on the gist of the invention described in the claims or disclosed in the description for carrying out the invention. Such modifications and changes are also included in the scope of the present invention.

First Embodiment
The first embodiment is an example of a waveform generating circuit based on a basic configuration.
1 to 6 show an example according to the first embodiment.
Fig. 1 is a diagram showing an example of the configuration of a waveform generating circuit according to a first embodiment. Fig. 2 is a diagram showing an example of an accumulator output. Fig. 3 is a diagram showing an example of input/output signals of a low-pass filter. Fig. 4 is a diagram showing an example of the configuration of a data processing unit. Fig. 5 is a diagram showing an example of the configuration of a data generating unit. Fig. 6 is a diagram showing an example of a square wave output.

Figure 1 shows an example of the configuration of a waveform generating circuit 10 according to the first embodiment. The waveform generating circuit 10 includes an accumulator 11, a waveform memory 12, a data processing unit 13, a DA converter 14, and a low-pass filter 15.

The accumulator 11 is a component that adds a phase addition value Δθ corresponding to the period T _O of the output signal for each clock in accordance with a period setting based on the period T _O (=the reciprocal of frequency f _O ) of the output signal, and outputs the result.

The phase addition value Δθ is given by the following (Equation 1-1), where T _O is the period of the output signal, the register of the accumulator 11 is D bits, and the period of the clock of the accumulator 11 is T _ACLK (the reciprocal of which is the frequency f _ACLK ).

The D-bit accumulator 11 adds Δθ for each clock period T _ACLK of the accumulator 11, and when the value exceeds 2 ^D −1, the carry to the 2 ^D digit is ignored and the operation is repeated in sequence.

The waveform memory 12 is a storage medium for storing not only periodic waveforms having typical shapes such as sine waves, square waves, and triangular waves, but also one period of a waveform having any other shape as digitized waveform data. The waveform memory 12 is a digital memory such as a ROM (Read Only Memory), a RAM (Random Access Memory), or a sequential memory. The waveform memory 12 sequentially outputs waveform data for each clock. If the waveform memory 12 is a randomly accessible memory, the output data is data at an address specified by the output of the accumulator 11 from among the waveform data written in the waveform memory 12. If the waveform memory 12 is a sequential memory, the output data is sequentially output by repeating the operation of outputting the waveform data written in advance in the waveform memory 12 from the first data for each clock input to the waveform memory 12, returning to the first data after the last data.

The data processing unit 13 performs various processes according to the input from the waveform memory 12 and the input from the accumulator 11, and generates and outputs waveform processing data. The details of the processing in this data processing unit 13 will be described later.

The DA converter 14 receives the output of the data processing unit 13 as waveform processing data input, and outputs a signal that converts the waveform processing data, which is numerical data, into an analog signal for each clock of the DA converter 14.

Each unit repeats such an operation for each clock input, thereby obtaining as an output signal an analog periodic signal having a frequency of _fO and the waveform written in the waveform memory 12. The analog signal that is the output signal of this DA converter 14 has a stepped waveform with a flat portion for each clock period _TACLK .

The low-pass filter 15 is disposed to smooth the stepped waveform of the output signal from the DA converter 14. The characteristics of the low-pass filter 15 may be such that it has a cutoff frequency that has an attenuation amount relative to the clock frequency f _ACLK .

2 is a diagram showing the output value of accumulator 11, with the horizontal axis representing time and the vertical axis representing the output value of accumulator 11. Over time, the output value of accumulator 11 behaves like a sawtooth wave, repeating values between 0 and 2 ^D −1 with a frequency of f _O (with a period of T _O =1/f _O ).

The ^2D values that accumulator 11 can take as output values correspond to the phase of one cycle of the waveform. For example, if the horizontal axis of one cycle of a periodic signal is represented by a phase of 360 deg, then phase 0 deg is 0, phase 180 deg is 2 ^D-1 , and just before phase 360 deg is 2 ^D -1. The most significant D1 bits (D1 is a positive integer equal to or less than D) of the output of accumulator 11 are input to the address bus of waveform memory 12.

Figure 3 (A) shows an example of the input and output signals of the low-pass filter 15. The horizontal direction represents time, and the vertical direction represents the signal magnitude. The stepped waveform output from the DA converter 14 is shown by a solid line, and the waveform smoothed by the low-pass filter 15 is shown by a dotted line. The output of the low-pass filter 15 to which the stepped waveform is input shows a transient response as shown by the dotted line, depending on the time constant of the low-pass filter 15, etc. This transient response becomes a waveform that monotonically increases or decreases to the output value of the next step over time. For the sake of concise explanation, in the following, unless otherwise specified, the sampling points are described as being connected by straight lines as shown in Figure 3 (B).

Figure 4 shows an example of the configuration of the data processing unit 13. The data processing unit 13 includes a data generation unit 21 and a correction determination unit 22. In the data processing unit 13, waveform data that is the output of the waveform memory 12 is input to the data generation unit 21 and the correction determination unit 22, respectively.

The correction determination unit 22 determines whether or not to perform correction processing on the waveform processing data to be output to the DA converter 14 based on the input waveform data, and when it determines that correction is necessary, it outputs a correction command signal to the data generation unit 21. This determination may be made by comparing a certain threshold value with the absolute value of the difference between adjacent waveform data, such as when there is a change of 10% or more with respect to the full range of the waveform data between adjacent waveform data. To specifically express the conditions in this example as an equation, when a certain threshold value is A _th , the waveform data at time T _X is Da(T _X ), and the waveform data at the sampling time immediately preceding that is Da(T _X -T _ACLK ), the following (Equation 1-2) is the condition for outputting the correction command signal.

The threshold value _Ath may be set arbitrarily with respect to the full range of the waveform data, and may be set to 30% or 50% of the full range, or may be set to an operation equivalent to 0%, where correction is always active.

The data generating unit 21 performs the following process depending on whether or not there is a correction command signal from the correction determining unit 22.
(1) When no correction command signal is received: The input waveform data is output as waveform processed data in the order in which it was received.
(2) When a correction command signal is present, in the portion of the waveform data where there is a change of more than the threshold value _Ath based on the input direct waveform data A and past waveform data via a delay unit 31 (described later), corrected waveform processing data is output instead of the data output in (1).

5 shows an example of the configuration of the data generating unit 21. The data generating unit 21 includes a delay unit 31, a subtraction unit 32, a multiplication unit 33, and an addition unit 34. In the data generating unit 21, the subtraction unit 32 calculates the difference between the waveform data Da (T _X ) input at a certain time T _X and the waveform data Da (T _X -T _ACLK ) input at the immediately preceding clock time via the delay unit 31, and the multiplication unit 33 multiplies the result by a correction coefficient k from the correction determination unit 22. The addition unit 34 calculates the sum of the multiplied value and the waveform data Da (T _X -T _ACLK ) that is the output of the delay unit 31, and outputs the result. Through such internal calculations, the data output from the data generating unit 21 becomes as shown in the following (Equation 1-3).

The correction coefficient k is in the range of 0≦k≦1. From (Equation 1-3), the output of the data generation unit 21 is Da(T _X - T _ACLK ) when k=0, and is Da(T _X ) when k=1. When 0<k<1, a weighted average is obtained using the correction coefficient k of the input signal Da(T _X ) and the input signal Da(T _X - T _ACLK ) at the immediately preceding sampling time T _X - T _ACLK .

The value of the correction coefficient k is determined, for example, as follows.
(1) When there is no correction command signal, k = 0. At this time, the output of the data generating unit 21 becomes Da (T _X - T _ACLK ).
(2) When a correction command signal is present, k is calculated using the following (Equation 1-4) based on the fraction _DU , which is the value obtained by replacing the lower D2 bits of the accumulator 11 with a numerical value after the decimal point, and the phase addition value Δθ.

The calculation of the value of this correction coefficient k may be performed by the correction determination unit 22. Furthermore, there is no need to prepare a separate signal as a correction command signal; if the correction coefficient k is 0, the operation is equivalent to the case without the correction command signal described above, and by setting the correction coefficient k to k>0, the operation is equivalent to the case with the correction command signal. The correction determination unit 22 may be configured in this way.

6 is a diagram showing an example of a rectangular wave output. A specific example of the operation according to the first embodiment will be described using a simplified model in which the address length of the waveform memory 12 is 8 bits and the waveform is a rectangular wave. For the sake of simplicity, the output of the accumulator 11 will be described in a form expressed in decimal notation with the upper D1 bit portion, which is the portion corresponding to the address length of the waveform memory 12, corresponding to the integer portion and the value corresponding to the fraction _DU of the lower D2 bit portion of the accumulator 11 being a decimal point. In correspondence with the example of phases shown, address 0 corresponds to phase 0 deg, address 128 (=2 ⁷ ) corresponds to phase 180 deg, and address 255 (=2 ⁸ -1) corresponds to immediately before phase 360 deg. 6A, the maximum value of a rectangular wave is A _MAX and the minimum value is A _MIN , with A MAX written from addresses 0 to 127 (= ² -1) of waveform memory 12 and _{A MIN written} from addresses 128 (= ² ) to 255 (= ² -1) of waveform memory 12. However, the address length of waveform memory 12 is not limited to 8 bits, and the number of addresses of waveform memory 12 is not limited to 2 ⁿ (n is a positive integer).

Here, the period of the accumulator 11 is set so that the clock period _TACLK is 1 ns (frequency _fACLK = 1 GHz) and the frequency _fO of the output signal of the waveform generating circuit 10 is 3 MHz. In other words, this period setting is a period in which exactly three rectangular waves are output in 1 μs (= 1000 ns, 1000 clock waves).

At this time, the phase addition value Δθ is:

となる。

It becomes.

The initial value of the accumulator 11 is set to 0, and this time is set to time 0. The value of the accumulator 11 is incremented by the phase addition value Δθ for each clock input, so

より、３３４クロックの入力後、すなわち３３４ｎｓ後に位相０の出力に戻る。
また、

Therefore, the output returns to phase 0 after 334 clocks are input, that is, after 334 ns.
Also,

より、時刻０から数えて６６７クロックの入力後、すなわち６６７ｎｓ後に再度位相０に戻る。
そして、

Therefore, after 667 clocks are input counting from time 0, that is, after 667 ns, the phase returns to 0 again.
and,

となり、時刻０から数えて１０００クロックで、ちょうど位相０となり、以降は１０００クロック間に３回位相０に戻るサイクルを繰り返す。

Then, at 1000 clocks counted from time 0, the phase becomes 0, and thereafter, the cycle of returning to phase 0 is repeated three times within 1000 clocks.

The length of one period of the square wave is 334 ns from time 0 until it first returns to phase 0, 333 ns from this point until it returns to phase 0 for the second time, and 333 ns from this point until it returns to phase 0 again, and this cycle is repeated. That is, even if the period is set in the accumulator 11 so that the frequency _f0 of the output signal is 3 MHz, the output signal is output with one period of 333 ns and 334 ns, as shown in FIG. 6B. In this way, jitter occurs in the conventional DDS method. The same is true for the falling edge.

Figure 6 (C) is an example showing the rising portion of the output signal when correction is performed by the correction determination unit 22 under similar setting conditions.

When the phase returns from just before 360 deg (address 255) to phase 0, the value of the waveform data suddenly changes from A _MIN to A _MAX .

を満たすしきい値Ａ_ｔｈであれば、補正判定部２２が波形データを補正するように動作する。

If the threshold value A _th satisfies the above, the correction determination unit 22 operates to correct the waveform data.

Normally, the waveform processing data output from the data generation unit 21 to the DA converter 14 is sent after a delay of one clock. If the correction determination unit 22 determines that correction is required, it generates waveform processing data that has been corrected based on the calculated k between the waveform data delayed by one clock and the waveform data without delay.

For example, between the 333rd and 334th clocks from time 0, the value of the waveform data suddenly changes from _AMIN to _AMAX and becomes equal to or greater than the threshold value _Ath . If k at this time is substituted into (Equation 1-4), the fraction D _U , which is the value after the decimal point of the accumulator 11 at the input of the 333rd clock, is 0.744 as shown in (Equation 1-6), and Δθ=0.768, so

を、補正した波形処理データとしてＤＡ変換器１４に出力する。補正判定部２２が動作しない場合では３３３ｎｓだった矩形波の１周期の時間が、この補正により１クロックの１／３程度遅くなる方向にずれることがわかる。

is output as the corrected waveform processing data to the DA converter 14. It can be seen that the time for one period of the rectangular wave, which was 333 ns when the correction determination unit 22 did not operate, is shifted in the direction of being delayed by about ⅓ of one clock due to this correction.

Similarly, between the 666th clock and the 667th clock from time 0, the value of the waveform data suddenly changes from _AMIN to _AMAX .

If k in this case is found based on (Equation 1-4), the fraction _DU of the accumulator 11 at the time of input of 666 clocks is 0.488 as shown in (Equation 1-7), so

From this, we can see that this correction causes the end of one period of the square wave to be delayed by 2/3 of a clock. Because the start of the period is delayed by about 1/3, the period of the square wave in this period has also become 1/3 of a clock longer overall.

And because the start of the third rectangular wave is shifted 2/3 clock later, the period that was 334 ns becomes approximately 333.3 ns.

In this way, it can be seen that the operation of the correction determination unit 22 suppresses the occurrence of jitter for one clock, and each section of one cycle becomes approximately the same period.

(Summary of effects)
In the example according to the first embodiment, a waveform generating circuit 10 is provided with an accumulator 11 that adds and outputs a phase addition value Δθ for each clock in accordance with an input period setting, a waveform memory 12 that stores waveform data of a digitized waveform output, a data processing unit 13 that reads waveform data from the waveform memory 12 for each clock and outputs waveform processing data corrected at abrupt change points of the waveform data based on the read waveform data, a DA converter 14 that converts the waveform processing data into an analog signal, and a low-pass filter 15 that smooths and outputs the analog signal from the DA converter 14, thereby correcting the waveform data in accordance with data of two consecutive points of sudden change points of the waveform data, the fraction _DU of the accumulator 11, and the phase addition value Δθ. This provides an excellent effect of suppressing jitter even at abrupt change points of the waveform where jitter is likely to be noticeable in the conventional DDS method.

Second Embodiment
The second embodiment is an example in which the number of waveform data points stored in the waveform memory 12 is limited to a number that satisfies a condition according to the setting of the output period.

The phase addition value Δθ can be calculated by (Equation 1-1). In the example according to the first embodiment, the smaller the period setting _T0 is, in other words, the higher the frequency of the output waveform is, the larger the phase addition value Δθ becomes, and may exceed 1.

In such a case, the waveform data stored in the waveform memory 12 may have more than one address specified as the output of the waveform memory 12. Therefore, adjacent waveform data are not used sequentially, and the output waveform is generated from waveform data at discrete addresses. Even in such a case, correction is performed using the waveform data used and a waveform is output, but the waveform generation circuit 10 in this embodiment ensures that correction is performed between adjacent waveform data.

To achieve this, first determine in advance the number of waveform data points, a positive integer N that satisfies the following (Equation 2-1).

The phase addition value Δθ is calculated using the following (Equation 2-2).

These calculations can be easily performed using known values. The data to be written to the waveform memory 12 is generated based on data prepared in advance as arbitrary waveform data, using spline approximation, linear approximation, moving average of the data in the included section, and other function approximations.

In this way, one period is divided into N equal parts, and the resulting N points of waveform data are written to the waveform memory 12. The number of data points of the waveform data written to the waveform memory 12 is limited so that the phase addition value Δθ is 1 or less. The accumulator 11 then performs phase addition so that it returns to 0 when it exceeds N. This type of processing allows operation using consecutive adjacent waveform data, making it possible to obtain a stable waveform for each period.

If N is selected so that Δθ is close to 1, the number of data points required to generate one cycle of the output waveform increases, improving the quality of the waveform, and making this a more suitable selection of the number of data points N. A waveform data generating unit (not shown) that generates waveform data with a limited number of data points so that the phase addition value Δθ is 1 or less and writes the waveform data to the waveform memory 12 is provided inside or outside the waveform generating circuit 10.

(Summary of effects)
In the example according to the second embodiment, an example was described in which data written to the waveform memory 12 is generated by spline approximation, linear approximation, moving average of data in the included section, or other function approximation based on data prepared in advance as arbitrary waveform data according to the period setting. By using such processing, the waveform data written to the waveform memory 12 is configured to include waveform data with the number of data points limited so that the phase addition value Δθ is 1 or less, which not only provides the excellent effect of suppressing jitter, but also provides the excellent effect of enabling operation using consecutive adjacent waveform data, thereby enabling a stable waveform to be obtained for each period.

Third embodiment
The third embodiment is an example of a waveform generating circuit 10 configured such that a clock signal for reading waveform data from a waveform memory 12 is supplied from a data processing unit 13 and no address is specified from an accumulator 11.

Figure 7 shows an example of a waveform generation circuit 10 according to the third embodiment. The waveform generation circuit 10 includes an accumulator 11, a waveform memory 12, a data processing unit 13, a DA converter 14, and a low-pass filter 15. In the case of the example of the second embodiment in which waveform data is read out sequentially from adjacent data, the waveform memory 12 does not need to be a randomly accessible memory that outputs data at a specified address, and may be a sequential memory.

This embodiment is an example of a configuration for such a case, in which the data processing unit 13 performs processing to generate a waveform memory clock that outputs waveform data sequentially each time the integer part of the output value from the accumulator 11 increases. Waveform data is output from the waveform memory 12 based on this waveform memory clock. If the number of data points in the waveform data is N, a reset signal can be added so that the sequential memory is read from the beginning when the number of data points exceeds N. In this way, it is not necessary for the sequential memory to use all of the memory.

As processing speeds have increased in recent years, configurations that can use sequential memory, which allows for inexpensive high-speed processing, can also achieve faster processing and cost reductions. Some sequential memories also achieve high-speed operation by reading multiple words of data at once using burst access. In this type of operation, multiple adjacent waveform data are loaded in advance, which is convenient for generating waveform processing data based on the waveform data, making this a suitable configuration example.

(Summary of effects)
In the example according to the third embodiment, the waveform memory 12 does not need to be a random-access memory that outputs data at a specified address, and as an example of a configuration that can be implemented using a sequential memory, a waveform generating circuit 10 has been described in which the data processing unit 13 is configured to read waveform data from the waveform memory 12 using a waveform memory clock generated in response to the addition of the integer part of the output from the accumulator 11. This processing not only provides the excellent effect of suppressing jitter, but also provides the effects of speeding up processing and reducing costs by allowing the use of a sequential memory that is inexpensive and capable of high-speed processing.

Fourth embodiment
The fourth embodiment is an example of an embodiment in which unique information that predefines whether output correction is required or not is inserted into the waveform data stored in the waveform memory 12.

Figure 8 shows an example of the configuration of the correction determination unit 22 according to the fourth embodiment. The correction determination unit 22 determines whether or not to perform correction on the waveform processing data to be output to the DA converter 14 based on information on correction-required signal bits that are not used as amplitude data for the waveform output, among the waveform data output from the waveform memory 12, and includes a correction coefficient processing unit 41 that calculates a correction coefficient k that serves as a correction command signal when it is determined that correction is necessary, and outputs this correction coefficient k to the data generation unit 21.

In this embodiment, any bit of the waveform data, for example the least significant bit, is set as a bit for a signal requiring correction. This information is not used as amplitude data for the waveform output, and if this bit is 1, the data generating unit 21 corrects the amplitude data for the waveform output based on the correction coefficient k calculated by the correction coefficient processing unit 41, and if it is 0, the data generating unit 21 outputs the amplitude data for the waveform output as is. In the data processing unit 13, by specifying the part of the waveform to be corrected depending on the presence or absence of this information, it is possible to apply correction to any part of the waveform without finding the difference between the data and judging whether it is larger or smaller than a threshold value. Data other than the bit for a signal requiring correction is used as amplitude data for the waveform output, and the data is processed depending on whether correction is performed, and the processed amplitude data is output to the DA converter 14.

(Summary of effects)
In the example of the fourth embodiment, as an example of an embodiment in which unique information that predetermines whether output correction is required is inserted into the waveform data, the waveform generating circuit 10 that configures the data processing unit 13 is described as adding information on the correction required signal bit, which is correction required information, to the waveform data read from the waveform memory 12, and determining whether or not to correct the waveform data based on this information on the correction required signal bit. With such a waveform data configuration, the excellent effect of suppressing jitter can be reliably obtained in the intended waveform portion.

Fifth embodiment
The fifth embodiment is another example of an embodiment in which inherent information that predefines whether output correction is required is inserted into the waveform data stored in the waveform memory 12 .

Figure 9 shows an example of the configuration of the correction determination unit 22 according to the fifth embodiment. The correction determination unit 22 is provided with a correction coefficient processing unit 41 that determines whether or not to perform correction processing on the waveform processing data to be output to the DA converter 14 based on information on the bit string for a signal requiring correction, which can also be used as amplitude data for the waveform output, among the waveform data output from the waveform memory 12, and calculates a correction coefficient k that serves as a correction command signal when it is determined that correction is necessary, and outputs this correction coefficient k to the data generation unit 21.

In this embodiment, specific bits of the waveform data are not reserved as bits for signals requiring correction, but rather, for example, the number of bits in the waveform data is 16 bits, and a specific value of the lower 6 bits is defined as a bit pattern for signals requiring correction. Specifically, if the lower 6 bits are all in the pattern "111111", the correction coefficient processing unit 41 determines that this data portion is the part to be corrected, and the data generating unit 21 corrects the amplitude data of the waveform output based on the correction coefficient k calculated by the correction coefficient processing unit 41, and if the pattern is other than that, the data generating unit 21 outputs the amplitude data of the waveform output as is. Here, the upper 10 bits are used as the amplitude data of the output waveform, but the number of upper and lower bits is arbitrary and is not limited to these values.

In an example such as this embodiment, it is necessary that a value in which the lower-order bits are defined as a bit pattern for a signal requiring correction is not used in waveform data in locations where correction is not required. Therefore, when generating waveform data to be written to waveform memory 12, amplitude data that happens to match this pattern in locations where correction is not required can be processed so that it is set to a value of +1 or -1 relative to the defined value.

By adopting this configuration, it is possible to configure a waveform generating circuit 10 that uses waveform data that includes information on whether correction is required, with almost no reduction in resolution in the amplitude direction.

(Summary of effects)
In the example of the fifth embodiment, as an example of another embodiment in which unique information that predefines whether output correction is required is inserted into the waveform data, a waveform generating circuit 10 has been described in which amplitude data that is quantified information of the waveform output is written even in the data portion of the information for the correction-required signal bit that is correction-required information for waveform data that does not require correction. With such a waveform data configuration, the excellent effect of suppressing jitter can be obtained reliably in the intended waveform portion, and with little sacrifice of waveform resolution.

Sixth embodiment
The sixth embodiment is yet another example of an embodiment in which unique information that predefines whether output correction is required or not is inserted into the waveform data stored in the waveform memory 12.

This is an embodiment in which data in the time axis direction, rather than the amplitude direction, is added to the remaining data portion to be embedded in the waveform data having the bit pattern for the signal to be corrected in the fifth embodiment.

For example, the number of bits in the waveform data is 16 bits, and a specific value in the lowest 6 bits is defined as the bit pattern for a signal requiring correction. Specifically, if the lowest 6 bits are all in the pattern "111111", the data used for the remaining 10 bits is set as data that specifies the position on the time axis between two pieces of data, such as the midpoint of the amplitude data of the waveform output before and after a signal requiring correction passes through. Note that while the midpoint is a suitable example, it is up to the design to decide which position to pass through, such as a 1:2 or 3:1 position between the two amplitude data.

The correction of waveform data can be realized by function approximation such as linear approximation, spline approximation, or sinusoidal waveform as in the example of the first embodiment. Furthermore, in the configuration example of the data generation unit 21 shown in FIG. 5, the value of the correction coefficient k can be found by performing an inverse function calculation so as to obtain a value based on these interpolations or approximations. By determining the function used for correction, the two ends of the correction interval, and the time positions of the points passing between them, corrected waveform data at the clock output point when the output waveform is updated can be generated by an inverse function calculation.

Straight-line approximation is a linear approximation and can be realized with relatively simple calculation processing, but for calculations of function approximations such as spline approximation and sinusoidal waveforms, including such interpolation, a function table can be prepared and the function value can be output based on a value based on the phase addition value Δθ. It is also possible to avoid directly performing processes that impose a heavy calculation load (time-consuming processes) such as power calculations and trigonometric function calculations, which is a suitable example of a configuration.

(Summary of effects)
In the example of the sixth embodiment, as yet another example of an embodiment in which unique information that predetermines whether output correction is required is inserted into the waveform data, a waveform generating circuit 10 has been described in which, for waveform data that requires correction , information specifying the time position between amplitude data that serves as numerical information of the waveform output in the preceding and following waveform data including that waveform data is written in the remaining data portion other than the information for the correction-required signal bit. With such a waveform data configuration, the excellent effect of suppressing jitter can be obtained reliably in the intended waveform portion without a decrease in waveform resolution.

(Overall summary)
In the example according to the first embodiment, a waveform generating circuit 10 is provided with an accumulator 11 that adds and outputs a phase addition value Δθ for each clock in accordance with an input period setting, a waveform memory 12 that stores waveform data of a digitized waveform output, and a data processing unit 13 that reads waveform data from the waveform memory 12 for each clock and outputs waveform data corrected at abrupt change points of the waveform data based on the read waveform data, thereby correcting the waveform data in accordance with data of two consecutive points of sudden change points of the waveform data, the fraction _DU of the accumulator 11, and the phase addition value Δθ. This provides an excellent effect of suppressing jitter even at abrupt change points of the waveform where jitter is likely to be noticeable in the conventional DDS method.

In the example of the second embodiment, the data written to the waveform memory 12 is generated by spline approximation, linear approximation, moving average of data in the included section, and other function approximations based on data prepared in advance as arbitrary waveform data according to the period setting. By using such processing, the waveform data written to the waveform memory 12 includes waveform data with the number of data points limited so that the phase addition value Δθ is 1 or less, which not only has the excellent effect of suppressing jitter, but also has the excellent effect of enabling operation using consecutive adjacent waveform data, making it possible to obtain a stable waveform for each period.

In the example of the third embodiment, the waveform memory 12 does not need to be a random-access memory that outputs data at a specified address, and as an example of a configuration that can be implemented using sequential memory, a waveform generation circuit 10 has been described in which the data processing unit 13 is configured to read waveform data from the waveform memory 12 using a waveform memory clock generated in response to the addition of the integer part of the output from the accumulator 11. This processing not only provides the excellent effect of suppressing jitter, but also provides the effect of speeding up processing and reducing costs by allowing the use of a sequential memory that is inexpensive and capable of high-speed processing.

In the example of the fourth embodiment, as an example of an embodiment in which unique information that predetermines whether output correction is required is inserted into the waveform data, the waveform generating circuit 10 that configures the data processing unit 13 is described as adding information on the correction required signal bit, which is correction required information, to the waveform data read from the waveform memory 12, and determining whether or not to correct the waveform data based on this information on the correction required signal bit. With such a waveform data configuration, the excellent effect of suppressing jitter can be reliably obtained in the intended waveform portion.

In the example of the fifth embodiment, as an example of another embodiment in which unique information that predefines whether output correction is required is inserted into the waveform data, a waveform generating circuit 10 has been described in which amplitude data that is quantified information of the waveform output is written even in the data portion of the information for the correction-required signal bit that is correction-required information for waveform data that does not require correction. With such a waveform data configuration, the excellent effect of suppressing jitter can be obtained reliably in the intended waveform portion, and with little sacrifice of waveform resolution.

In the example of the sixth embodiment, as yet another example of an embodiment in which unique information that predetermines whether output correction is required is inserted into the waveform data, a waveform generating circuit 10 has been described in which, for waveform data that requires correction , information specifying the time position between amplitude data that serves as numerical information of the waveform output in the preceding and following waveform data including that waveform data is written in the remaining data portion other than the information for the correction-required signal bit. With such a waveform data configuration, the excellent effect of suppressing jitter can be obtained reliably in the intended waveform portion without a decrease in waveform resolution.

These findings demonstrate the advantages of the present invention over conventional technology, such as reduced jitter.

The above describes the most preferred embodiment of the present invention, but the present invention is not limited to the above description. Various modifications and changes are possible for those skilled in the art based on the gist of the invention described in the claims or disclosed in the description for carrying out the invention. Such modifications and changes are included in the scope of the present invention.

The waveform generating circuit of the present invention can be used and is advantageously used in the following applications, for example.
(1) Generation of test signals for testing the operation of electronic circuits (2) Simulation signal source of standard signals conforming to various standards (3) Signal source for modulation in the field of communications, etc.

11 accumulator 12 waveform memory 13 data processing unit 14 DA converter 15 LPF (low pass filter)
21 Data generation unit 22 Correction determination unit 31 Delay unit 32 Subtraction unit 33 Multiplication unit 34 Addition unit 41 Correction coefficient processing unit

Claims (6)

A DDS type waveform generating circuit,
an accumulator that adds and outputs a phase addition value for each clock;
a waveform memory for storing waveform data of a digitized waveform output, the waveform memory using the most significant bits of the output of the accumulator as an address input;
a data processing unit which receives the output of the accumulator and the data output of the waveform memory, reads out the waveform data from the waveform memory for each clock, and generates and outputs waveform processing data corrected at abrupt change points of the waveform data based on the read out waveform data and lower bits of the output of the accumulator other than the upper bits;
a digital-to-analog converter that receives the waveform processed data as a data input and converts the data input into an analog signal;
a low-pass filter for smoothing the waveform of an analog signal output from the DA converter to produce an output signal;
13. A waveform generating circuit comprising: When the phase addition value is Δθ and the value obtained by replacing the data of the lower bits with a decimal point is D _U , the correction coefficient k is k=(1−D _U )/Δθ,
2. The waveform generating circuit according to claim 1, wherein, when the period of the clock is T _ACLK , the waveform data at time T _X is Da(T _X ), and the waveform data at the sampling time immediately before that is Da(T _X -T _ACLK ), a data generating section included in the data processing section outputs data of k·Da(T _X )+(1-k)·Da(T _X -T _ACLK ) based on the correction coefficient k. a positive integer N is selected so as to satisfy N≦T _O /T _ACLK , where T _O is a period of the output signal and T _ACLK is a period of the clock;
The number of data points of the waveform data is set to N, and the N pieces of waveform data are written into the waveform memory;
When the phase addition value is Δθ, Δθ is expressed as Δθ=N·T _ACLK /T _o, and the value is 1 or less.
When the value of the most significant bit of the output of the accumulator exceeds N, the most significant bit returns to 0;
3. The waveform generating circuit according to claim 1, wherein the waveform generating circuit operates based on adjacent waveform data that are consecutive. A DDS type waveform generating circuit,
an accumulator that adds and outputs a phase addition value for each clock;
a waveform memory using a sequential memory for storing waveform data of a digitized waveform output;
a data processing unit having a configuration for generating a waveform memory clock to be supplied to the waveform memory each time the value of the upper bits of the output of the accumulator increases, and supplying the clock to the waveform memory, a configuration for supplying a reset signal to the waveform memory when the value of the upper bits of the output of the accumulator exceeds the number of data points of the waveform data, and a configuration for receiving the output of the accumulator and the data output of the waveform memory as inputs, reading out the waveform data from the waveform memory for each waveform memory clock, and generating and outputting waveform processing data corrected at locations where the waveform data suddenly changes, based on the read waveform data and the lower bits of the output of the accumulator other than the upper bits;
a digital-to-analog converter that receives the waveform processed data as a data input and converts the data input into an analog signal;
a low-pass filter for smoothing the waveform of an analog signal output from the DA converter to produce an output signal;
13. A waveform generating circuit comprising: adding correction necessity information to the waveform data read from the waveform memory;
5. The waveform generating circuit according to claim 1, wherein the data processing section is configured to determine whether or not to correct the waveform data based on the correction necessity information. The waveform generating circuit according to claim 5, characterized in that for the waveform data that does not require correction, numerical information on the waveform output is also written in the data portion of the correction necessity information.

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