JP7686543B2 - POWER CONVERSION DEVICE, CONTROL METHOD FOR POWER CONVERSION DEVICE, AND PROGRAM - Google Patents

Description

Embodiments of the present invention relate to a power conversion device, a control method for a power conversion device, and a program.

In recent years, modular multilevel converters (MMCs) have been put to practical use as power converters. MMCs are power converters that have arm units containing multiple unit converters (hereinafter referred to as "cells") connected in series, and can handle high voltages and large capacity by adding up the voltages output by each cell. Power converters are used, for example, in DC transmission systems and reactive power compensation devices. For example, a power converter for a DC transmission system is connected between an AC system and a DC system, and converts the power of each system between the two. For example, a power converter for a reactive power compensation device is connected to an AC system, and adjusts the reactive power at the interconnection point.

When a power converter performs mutual power conversion or adjusts reactive power, the switching elements of the power converter are controlled. One known method of switching control in a power converter is the phase-shift PWM (Pulse Width Modulation) method, which synthesizes multiple stepped sine waves across the entire arm unit by evenly shifting the phase of a triangular wave carrier assigned to each cell. However, with the phase-shift PWM method, the frequency of the triangular wave carrier must be made higher than the frequency of the AC system, which results in large losses in switching control (switching losses).

In this regard, for example, Patent Documents 1 and 2 disclose a technique for one-pulse control in which each cell is switched once during one cycle of the voltage of an AC system. However, with conventional switching control, there is an issue that the variation in the voltage of the capacitors in each cell increases when the switching frequency decreases. For this reason, methods have been proposed in power converters to equalize the voltage of the capacitors in each cell during switching control, such as a method of adjusting the phases of the rise and fall of the output voltage of each cell, and a method of changing the order of the rise and fall of the output voltage depending on the magnitude relationship of the voltage of the capacitors in each cell.

The method of changing the order of rise and fall of the output voltage according to the magnitude relationship of the voltage of the capacitor of each cell can be realized by acquiring the voltage of the capacitor of each cell equipped in the arm unit at regular intervals and selecting the cell to be subjected to switching control by comparing the magnitude relationship. However, in this method, the time required for the process of sorting the acquired capacitor voltage of each cell based on the magnitude relationship (so-called sorting process) may be longer than the time interval required for the process of performing switching control. In this case, it becomes difficult to control the capacitors equipped in each cell to reduce the difference in the charge amount (to balance the charge amount so that it is relatively uniform). For this reason, if the cell to be subjected to switching control is selected after the sorting process is completed, sufficient balancing performance cannot be obtained to balance the capacitor voltage, and it is considered that this may be a factor in increasing the fluctuation range of the capacitor voltage. If the fluctuation range of the capacitor voltage increases, the voltage that can be output by each cell will decrease, and the operation of the power conversion device will be restricted. Furthermore, the maximum value of the capacitor voltage will increase due to the increase in the fluctuation range of the capacitor voltage, which may be a factor in the failure of the capacitor or switching element. In this case, the reliability of the power converter will be significantly reduced.

JP 2014-233126 A JP 2015-159687 A

The problem that the present invention aims to solve is to provide a highly reliable power conversion device, a control method for a power conversion device, and a program by controlling a unit converter included in the power converter.

The power conversion device of the embodiment has a power converter and a converter control unit. The power converter has at least one arm unit in which a plurality of unit converters having an energy storage element for storing power and a plurality of switching elements capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element are connected in series. The converter control unit controls the power conversion operation in the power converter by switching at least one of a first control state in which the terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited. The converter control unit has a state number calculation unit, a list calculation unit, and a unit converter selection unit. The state number calculation unit calculates a state number representing the number of unit converters to be assigned to any of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit. The list calculation unit generates list information representing a magnitude relationship of the inter-terminal voltages at every predetermined second time interval longer than the first time interval, based on the inter-terminal voltages of the energy storage element detected at a predetermined first time interval. The unit converter selection unit selects the unit converter for changing the current control state, based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the inter-terminal voltage of the energy storage element. In the case of a charging period in which the polarity of the arm current becomes a charging polarity for storing power in the energy storage element possessed by the unit converter in the first control state, the unit converter selection unit changes the first unit converter to the second control state when the inter-terminal voltage of the energy storage element possessed by a first unit converter that is the unit converter in the first control state, detected at the first time interval, exceeds a first threshold value higher than a rated voltage, and selects other unit converters, of the unit converters in the second control state, the same number as the first unit converter, as the unit converters to be changed to the first control state. In the case of a discharge period in which the polarity of the arm current becomes a discharge polarity that discharges power from the energy storage element of the unit converter in the first control state, when the terminal-to-terminal voltage of the energy storage element of the second unit converter, which is the unit converter in the first control state and is detected in the first time interval, exceeds a second threshold value lower than a rated voltage, the second unit converter is changed to the second control state, and among the unit converters in the second control state, other unit converters, the same number as the second unit converter, are selected as the unit converters to be changed to the first control state.

1 is a diagram showing an example of the configuration of a power conversion device according to a first embodiment; FIG. 2 is a diagram showing an example of a configuration of cells in a leg included in a power converter. FIG. 2 is a diagram showing an example of the configuration of a converter control unit included in the power conversion device. 4 is a timing chart illustrating an example of operation timing of a first operation in the power conversion device. 10 is a timing chart illustrating an example of operation timing of a second operation in the power conversion device. FIG. 13 is a diagram showing an example of the configuration of a power conversion device according to a second embodiment. FIG. 2 is a diagram showing an example of a configuration of cells in a leg included in a power converter. 13 is a timing chart illustrating an example of operation timing of a third operation in the power conversion device. 13 is a timing chart illustrating an example of operation timing of a fourth operation in the power conversion device.

The power conversion device, the control method for the power conversion device, and the program of the embodiment will be described below with reference to the drawings.

(First embodiment)
[Configuration of power conversion device]
Fig. 1 is a diagram showing an example of a configuration of a power conversion device according to a first embodiment. Fig. 1 shows an example of a power conversion device 1 that is provided at an interconnection point between an AC system and a DC system, and converts AC power supplied by the AC system into DC power supplied by the DC system, and vice versa. The AC system may be, for example, an AC power source or an AC load. The DC system may be, for example, a DC power source or a DC load. The power conversion device 1 includes a power converter 10 and a converter control unit 50.

The power converter 10 is a double star-connected modular multilevel converter (MMC) that converts AC power and DC power mutually in response to control from the converter control unit 50. The power converter 10 has a plurality of legs 12 between a positive terminal P of the DC system and a negative terminal N of the DC system. The number of legs 12 included in the power converter 10 corresponds to the number of phases of AC power supplied by the AC system. FIG. 1 shows a case where the AC system supplies three-phase AC power, namely, a first phase (R phase), a second phase (S phase), and a third phase (T phase). For this reason, FIG. 1 shows the configuration of the power converter 10 that has three legs 12, namely, a leg 12-R, a leg 12-S, and a leg 12-T. Each of the legs 12-R, the leg 12-S, and the leg 12-T has the same configuration.

In each leg 12, the AC terminal CA is connected to a terminal of the corresponding phase of the AC system. More specifically, in leg 12-R corresponding to the R phase, the AC terminal CA-R is connected to the AC terminal R of the R phase of the AC system, in leg 12-S corresponding to the S phase, the AC terminal CA-S is connected to the AC terminal S of the S phase of the AC system, and in leg 12-T corresponding to the T phase, the AC terminal CA-T is connected to the AC terminal T of the T phase of the AC system. Figure 1 shows a case where the AC terminal CA of each leg 12 is connected to a terminal of the corresponding phase of the AC system via a transformer TR.

In each leg 12, the terminal opposite the AC terminal CA is connected to the respective DC terminal of the DC system. More specifically, in each leg 12, the terminal having the same potential as the positive pole of the DC voltage output by the power converter 10 is connected to the positive terminal P, and the terminal having the same potential as the negative pole of the DC voltage output by the power converter 10 is connected to the negative terminal N. In the following description, the terminal of leg 12 connected to the positive terminal P is also referred to as the DC terminal CP of leg 12, and the terminal of leg 12 connected to the negative terminal N is also referred to as the DC terminal CN of leg 12.

Each leg 12 includes, for example, two reactors 14 and two arm units 16. Each arm unit 16 includes, for example, n cells 162 (cells 162-1 to 162-n) connected in series (n is a natural number). In FIG. 1, in order to distinguish whether each component of the leg 12 corresponds to the positive or negative side of the DC system or to which phase of the AC system, a "- (hyphen)" and the letter "P" representing the positive side or the letter "N" representing the negative side are added after each reference symbol, followed by a hyphen and the letter "R" representing the R phase, the letter "S" representing the S phase, or the letter "T" representing the T phase. In the following description, when it is not necessary to distinguish whether each component corresponds to the positive or negative side of the DC system or to which phase of the AC system, the hyphen and the identifying letter following the hyphen are omitted.

In each leg 12, the positive reactor 14-P and the positive arm unit 16-P are connected in series, and the negative reactor 14-N and the negative arm unit 16-N are connected in series. In each leg 12, the connection point between the reactor 14-P and the reactor 14-N is the DC terminal CP. In each leg 12, the terminal of the arm unit 16-P opposite the reactor 14-P is the DC terminal CP of the leg 12, and the terminal of the arm unit 16-N opposite the reactor 14-N is the DC terminal CN of the leg 12. In other words, in each leg 12, the cells 162-1 to 162-n and the reactor 14-P are connected in series in this order from the DC terminal CP side to the AC terminal CA side and connected to the AC terminal CA. Furthermore, in each leg 12, cells 162-n to 162-1 and reactor 14-N are connected in series in this order from the DC terminal CN side toward the AC terminal CA side and connected to the AC terminal CA.

Leg 12 is an example of a "phase unit" in the claims. Arm unit 16-P (which may include reactor 14-P) is an example of a "first arm unit" in the claims, and arm unit 16-N (which may include reactor 14-N) is an example of a "second arm unit" in the claims. Cell 162 is an example of a "unit converter" in the claims. Reactor 14 is an example of an "inductance element" in the claims.

In FIG. 1, the reactor 14 is shown to be disposed on the AC terminal CA side of the arm unit 16 in each leg 12, but the reactor 14 may be disposed on the opposite side of the AC terminal CA side of the arm unit 16 (i.e., on the DC terminal CP side or the DC terminal CN side) or at any position within the arm unit 16 (i.e., between any two cells 162 connected in series in the arm unit 16). The reactor 14 may be replaced with a transformer with a special winding structure that has a leakage reactance sufficient to replace the function of the reactor. In this case, the reactor 14 may be integrated with the transformer TR.

Each arm unit 16 generates an AC voltage with a multi-level waveform, which is a stepped sine wave representing the AC waveform to be supplied to the corresponding phase of the AC system, in response to control from the converter control unit 50 for each of the series-connected cells 162.

Here, an example of the configuration of the cell 162 included in the arm unit 16 will be described. The cell 162 is, for example, a half-bridge circuit. FIG. 2 is a diagram showing an example of the configuration of the cell 162 in the leg 12 included in the power converter 10. The cell 162 includes two switching elements Q (switching element Q1 and switching element Q2), two diodes D (diode D1 and diode D2), and a capacitor C. The switching element Q is, for example, an insulated gate bipolar transistor (IGBT). The switching element Q is not limited to an IGBT. The switching element Q may be any element as long as it is a self-extinguishing semiconductor switching element capable of realizing a converter or inverter.

In cell 162, switching element Q1 and switching element Q2 are connected in series. In cell 162, the series circuit of switching element Q1 and switching element Q2 and capacitor C are connected in parallel. In cell 162, each switching element Q and its corresponding diode D are connected in parallel. In cell 162, the connection point between the emitter of switching element Q1 and the collector of switching element Q2 is the positive terminal TP(+) connected to the positive terminal P of leg 12, and the connection point between the emitter of switching element Q2 and capacitor C is the negative terminal TN(-) connected to the negative terminal N of leg 12.

A control signal from the converter control unit 50 is input to the gates of the switching element Q1 and the switching element Q2 of the cell 162 (a control voltage is applied or a control current is supplied). A gate signal gtp is input to the gate of the switching element Q1 as a control signal from the converter control unit 50, and a gate signal gtn is input to the gate of the switching element Q2 as a control signal from the converter control unit 50. As a result, each of the switching elements Q1 and Q2 is switched to either an on state or an off state by the converter control unit 50. In the following description, when a control signal (gate signal gtp, gate signal gtn) of "1 ("High" level)" is input, each switching element Q is in an on state, and when a control signal (gate signal gtp, gate signal gtn) of "0 ("Low" level)" is input, each switching element Q is in an off state.

The capacitor C is charged or discharged depending on the state of each switching element Q. In the cell 162, the terminal voltage of the capacitor C (hereinafter referred to as "capacitor voltage Vc") is generated as the terminal voltage between the positive terminal TP and the negative terminal TN of the cell 162 (hereinafter referred to as "cell voltage Vo"). More specifically, when the converter control unit 50 sets the control signal (gtp, gtn) = (1, 0), for example, a current flows in the order of the positive terminal TP, the switching element Q1, the capacitor C, and the negative terminal TN, and the cell voltage Vo of the cell 162 coincides with the capacitor voltage Vc. In other words, when the converter control unit 50 sets the control signal (gtp, gtn) = (1, 0), the capacitor C is inserted between the positive terminal TP and the negative terminal TN of the cell 162, and the capacitor voltage Vc is output as the cell voltage Vo. In the following description, the converter control unit 50 setting the control signals (gtp, gtn) = (1, 0) is referred to as "insertion", and the state of the cell 162 in this case is referred to as "insertion state". On the other hand, when the converter control unit 50 sets the control signals (gtp, gtn) = (0, 1), for example, current flows in the order of the positive terminal TP, the switching element Q2, and the negative terminal TN, and the cell voltage Vo of the cell 162 becomes 0 [V]. In other words, when the converter control unit 50 sets the control signals (gtp, gtn) = (0, 1), the positive terminal TP and the negative terminal TN of the cell 162 are short-circuited, and the current flows without passing through the capacitor C, and the cell voltage Vo of the cell 162 becomes 0 [V]. In the following description, the converter control unit 50 setting the control signals (gtp, gtn) = (0, 1) is referred to as "bypass", and the state of the cell 162 in this case is referred to as "bypass state".

Cell 162 is not limited to the configuration shown in FIG. 2, and may have any configuration that achieves the same function as cell 162.

The switching element Q1 and the diode D1 are an example of a "switching element" and a "first switching element" in the claims, and the switching element Q2 and the diode D2 are an example of a "switching element" and a "second switching element" in the claims. The on state is an example of a "conductive state" in the claims, and the off state is an example of a "non-conductive state" in the claims. The capacitor C is an example of an "energy storage element" in the claims. The positive terminal TP is an example of a "first end" in the claims, and the negative terminal TN is an example of a "second end" in the claims. The insert state is an example of a "first control state" in the claims, and the bypass state is an example of a "second control state" in the claims.

By connecting multiple cells 162 with this configuration in series, the arm unit 16 outputs a voltage that is the sum of the cell voltages Vo of each cell 162 controlled to the inserted state. Therefore, the arm unit 16 outputs a voltage according to the number of cells 162 controlled to the inserted state by the converter control unit 50. In this way, the arm unit 16 generates a multi-level waveform according to the control from the converter control unit 50.

By the way, in the cell 162, it should be prohibited to set the control signal (gtp, gtn) = (1, 1). This is because if the control signal (gtp, gtn) = (1, 1), both the switching element Q1 and the switching element Q2 will be in the on state, and both ends of the capacitor C will be short-circuited. For this reason, when changing the control signal (gtp, gtn) = (1, 0) from the control signal (gtp, gtn) = (0, 1) or vice versa, the converter control unit 50 controls so as to provide a period during which the control signal (gtp, gtn) = (0, 0) is transiently in a very short period of time, a so-called dead time. When the converter control unit 50 stops the operation of the cell 162, it may fix the control signal (gtp, gtn) = (0, 0). In the following description, the converter control unit 50 fixing all control signals (gtp, gtn) to (0, 0) and stopping the operation of all cells 162 in the arm unit 16 of the power converter 10 is referred to as "gate block," and the state of the cells 162 in this case is referred to as the "gate block state."

Returning to FIG. 1, the converter control unit 50 calculates an AC voltage command value and a DC voltage command value, including the frequency of the AC system, based on the operating state of the power conversion device 1 and the detection values (current value, current flow direction (polarity), voltage value) at each position in the power conversion device 1. For this purpose, the converter control unit 50 acquires detection values output by a detector (described later) provided at a desired position inside or outside the power conversion device 1 at a predetermined (constant) acquisition period TS1. Then, the converter control unit 50 calculates a voltage command value for each arm unit 16, including the voltage component represented by the calculated AC voltage command value or DC voltage command value. Based on the calculated voltage command value, the converter control unit 50 generates a control signal for controlling (switching control) the switching element Q in the cell 162 provided in each arm unit 16. Then, the converter control unit 50 outputs the generated control signal to the corresponding cell 162. For example, when controlling arm unit 16-P-R, which is an arm unit 16 corresponding to the R phase of the AC system and connected to the positive pole side of the DC system, the converter control unit 50 calculates an arm voltage command value Varm* to be output from arm unit 16-P-R based on mainly an AC voltage component to be output to AC terminal CA-R and mainly a DC voltage component to be output between DC terminal CP-R and DC terminal CN-R. In the following description, the positive polarity of the arm voltage Varm and the arm voltage command value Varm* is defined as a direction in which the potential on the cell 162-1 side becomes higher when viewed from the cell 162-n side. Then, the converter control unit 50 generates gate signals gtp (gate signals gtp-1-P-R to gtp-n-P-R) and gate signals gtn (gate signals gtn-1-P-R to gtn-n-P-R) for controlling the switching elements Q in each cell 162 (cells 162-1-P-R to 162-n-P-R) included in the arm unit 16-P-R based on the calculated arm voltage command value Varm*. The converter control unit 50 outputs the generated gate signals gtp and gtn to the corresponding cells 162. The same applies when the converter control unit 50 controls other arm units 16. The converter control unit 50 includes, for example, an insert number calculation unit 52, a sort list calculation unit 54, a cell selection control unit 56, and a gate signal generation unit 58.

The converter control unit 50 controls the operation of the power converter 10 by, for example, a hardware processor such as a CPU (Central Processing Unit) executing a program (software). The converter control unit 50 may be realized by hardware (including circuitry) such as an LSI (Large Scale Integration), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a GPU (Graphics Processing Unit), or may be realized by cooperation between software and hardware. The converter control unit 50 may be realized by a dedicated LSI. The program may be stored in advance in a storage device (storage device having a non-transient storage medium) such as an HDD (Hard Disk Drive) or flash memory provided in the converter control unit 50 or the power conversion device 1, or may be stored in a removable storage medium (non-transient storage medium) such as a DVD or CD-ROM, and the storage medium may be installed in the HDD or flash memory provided in the converter control unit 50 or the power conversion device 1 by attaching the storage medium to a drive device provided in the converter control unit 50 or the power conversion device 1.

In the power conversion device 1, a current detector and a voltage detector are provided at desired positions to detect the current value, the polarity of the current, and the voltage value. In the example of FIG. 1, a current detector for detecting the positive arm current Ip flowing from the positive terminal P side to the AC terminal CA side and a current detector for detecting the negative arm current In flowing from the AC terminal CA side to the negative terminal N side are provided in each leg 12. More specifically, in the leg 12-R, a current detector for detecting the positive arm current Ipr flowing from the positive terminal P side to the AC terminal CA-R side is provided between the arm unit 16-P-R and the reactor 14-P-R, and a current detector for detecting the negative arm current Inr flowing from the AC terminal CA-R side to the negative terminal N side is provided between the arm unit 16-N-R and the reactor 14-N-R. The other legs 12 are similar. Although not shown in FIG. 2, a voltage detector for detecting the capacitor voltage Vc is also provided in each cell 162. The R-phase AC current Isr, the S-phase AC current Iss, and the T-phase AC current Ist may be directly detected by providing current detectors at the AC terminals R, S, and T, respectively, or may be indirectly detected by calculating the positive arm current Ip and the negative arm current In detected in each leg 12. For example, the R-phase AC current Isr may be indirectly detected by calculating the difference between the positive arm current Ipr and the negative arm current Inr (i.e., Inr-Ipr). Furthermore, although voltage detectors are not shown in FIG. 1, the case where the R-phase AC voltage Vsr, the S-phase AC voltage Vss, and the T-phase AC voltage Vst are detected is shown.

Figure 3 shows an example of the configuration of the converter control unit 50 provided in the power conversion device 1.

The insert number calculation unit 52 receives at least the arm voltage command value Varm* to be output by the arm unit 16. The arm voltage command value Varm* is a value (real value) obtained by distributing the voltage components to be output to the AC system and the DC system, which are obtained as a result of calculations such as the operating state of the power conversion device 1 and voltage/current control based on each detection value in the power conversion device 1, for each arm unit 16. The insert number calculation unit 52 calculates (calculates) an insert number Ncells representing the number (integer value) of cells 162 to be assigned to the insert state (put into the insert state) among the cells 162 included in each arm unit 16, for each arm unit 16, according to the arm voltage command value Varm*. The insert number calculation unit 52 outputs the calculated insert number Ncells to the cell selection control unit 56.

There are various methods for the insert number calculation unit 52 to calculate (calculate) the insert number Ncells. For example, the insert number calculation unit 52 calculates the insert number Ncells, which represents the number of cells 162 to be inserted, by approximating the value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 162 belonging to the arm unit 16 to an integer. In this case, the converter control unit 50 performs one-pulse control, controlling (putting the cells 162 belonging to the arm unit 16 into the insert state and bypass state) each time within one period of the AC voltage in the AC system. For example, the insert number calculation unit 52 compares the modulated wave based on the arm voltage command value Varm* with each of the triangular wave carriers, the number of which is the same as the number of cells 162 belonging to the arm unit 16 ("n" in FIG. 1) and has phases shifted from each other, and calculates the number of triangular wave carrier waves for which the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier (becomes larger than the value of the triangular wave carrier) as the insert number Ncells, which represents the number of cells 162 to be put into the inserted state. In this case, the converter control unit 50 performs multi-pulse control, controlling the cells 162 belonging to the arm unit 16 multiple times (putting them into the inserted state and bypass state) within one period of the AC voltage in the AC system. For example, the insert number calculation unit 52 compares the modulated wave based on the arm voltage command value Varm* with each triangular wave carrier whose level is shifted from each other by the same number as the number of cells 162 belonging to the arm unit 16 ("n" in FIG. 1), and calculates the number of triangular wave carrier waves whose arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier (becomes larger than the value of the triangular wave carrier) as the insert number Ncells representing the number of cells 162 to be inserted. In this case, the converter control unit 50 also performs multi-pulse control. The method by which the insert number calculation unit 52 calculates the insert number Ncells is not limited to the above-mentioned method, and any method may be used as long as it can express the value (real value) distributed to each arm unit 16 as the number of cells 162 to be inserted (integer value).

The number of inserts calculation unit 52 is an example of a "number of states calculation unit" in the claims. The number of inserts Ncells is an example of a "number of states" in the claims.

The sort list calculation unit 54 calculates (generates) a sort list representing the magnitude relationship of the capacitor voltage Vc of each cell 162 included in the power converter 10 for each arm unit 16. The sort list calculation unit 54 generates a sort list for each predetermined (constant) calculation period TS2, for example. The sort list is a sort list in which the capacitor voltages Vc of at least two or more cells 162 belonging to the same arm unit 16 (in FIG. 3, the capacitor voltages Vc-1 to Vc-n of cells 162-1 to 162-n) are rearranged in descending or ascending order based on the magnitude relationship of the voltage values. The calculation period TS2 in which the sort list calculation unit 54 generates the sort list is a period (TS2>TS1) with a longer time interval than the acquisition period TS1 in which each detection value in the power conversion device 1 is acquired. This is because it is considered that the process of rearranging the voltage values of the multiple capacitor voltages Vc acquired in the sort list calculation unit 54 takes time. For this reason, the sort list calculation unit 54 generates a sort list based on the voltage value of the capacitor voltage Vc acquired in the acquisition period TS1 that matches the timing of generating the next sort list in the calculation period TS2, that is, the timing of updating the sort list. For example, the sort list calculation unit 54 generates a sort list by rearranging the voltage values of the capacitor voltage Vc acquired in the acquisition period TS1 immediately before the timing of starting to generate the sort list after securing the time required for the process of rearranging the voltage values of the capacitor voltage Vc. The voltage value of the capacitor voltage Vc used by the sort list calculation unit 54 when generating the sort list is not limited to the voltage value acquired immediately before the timing of starting to generate the sort list described above, and may be, for example, the average value or maximum value of the voltage values of the capacitor voltage Vc corresponding to the same capacitor C acquired in multiple acquisition periods TS1. In the following description, it is assumed that the sort list calculation unit 54 generates a sort list in which the voltage values of the capacitor voltage Vc are rearranged in descending order. The sort list calculation unit 54 outputs the generated sort list to the cell selection control unit 56.

The sort list calculation unit 54 is an example of a "list calculation unit" in the claims. The sort list is an example of "list information" in the claims.

The cell selection control unit 56 selects a cell 162 for which the current control state is to be changed at least each time the insert number Ncells output by the insert number calculation unit 52 changes, that is, each time the cell 162 is controlled (put into the insert state or the bypass state). More specifically, the cell selection control unit 56 starts selecting a cell 162 when the insert number Ncells changes. Then, the cell selection control unit 56 refers to the polarity of the arm current Iarm (i.e., the positive arm current Ip and the negative arm current In) flowing through the arm unit 16 to be controlled and the sort list of the arm unit 16 to be controlled output by the sort list calculation unit 54, and selects a cell 162 to be changed to the insert state or the bypass state.

When the number of inserts Ncells increases, during a period (charging period) in which the polarity of the arm current Iarm is a charging polarity that accumulates power in the capacitor C of the cell 162 in the inserted state and increases the charge amount of the entire arm unit 16, the cell selection control unit 56 selects, from among the cells 162 currently in the bypass state, a cell 162 having a capacitor C with less accumulated power as a cell 162 to be changed to the inserted state. In this case, the cell selection control unit 56 refers to the sort list and selects cells 162 in order starting from the cell 162 having a capacitor C with a relatively low voltage value of the capacitor voltage Vc. The charging polarity is the polarity in which the arm current Iarm flows in the same direction as the positive arm current Ip and the negative arm current In shown in FIG. 1. On the other hand, when the number of inserts Ncells increases, during a period (discharge period) in which the polarity of the arm current Iarm is a discharge polarity that discharges the power stored in the capacitor C of the cell 162 in the inserted state and increases the discharge amount of the entire arm unit 16, the cell selection control unit 56 preferentially selects the cell 162 having the capacitor C with the most stored power from among the cells 162 currently in the bypass state as the cell 162 to be changed to the inserted state. In this case, the cell selection control unit 56 refers to the sort list and selects the cell 162 having the capacitor C with the relatively high voltage value of the capacitor voltage Vc in order. The discharge polarity is the polarity in which the arm current Iarm flows in the opposite direction to the positive arm current Ip and the negative arm current In shown in FIG. 1.

When the number of inserts Ncells is decreased, the cell selection control unit 56, during a period (charging period) in which the polarity of the arm current Iarm is a charging polarity that accumulates power in the capacitor C of the cell 162 in the inserted state and increases the charge amount of the entire arm unit 16, selects the cell 162 having the capacitor C with the most accumulated power from among the cells 162 currently in the inserted state as the cell 162 to be changed to the bypass state. In this case, the cell selection control unit 56 refers to the sort list and selects the cells 162 in order from the cells 162 having the capacitor C with the relatively high voltage value of the capacitor voltage Vc. On the other hand, when the number of inserts Ncells is decreased, the cell selection control unit 56, during a period (discharging period) in which the polarity of the arm current Iarm is a discharging polarity that accumulates power in the capacitor C of the cell 162 in the inserted state and increases the discharge amount of the entire arm unit 16, selects the cell 162 having the capacitor C with the least accumulated power from among the cells 162 currently in the inserted state as the cell 162 to be changed to the bypass state. In this case, the cell selection control unit 56 refers to the sort list and selects cells 162 in order starting from the cell 162 that has a capacitor C with a relatively low voltage value of the capacitor voltage Vc.

As a result, the cells 162 including capacitors C whose capacitor voltage Vc has a relatively high voltage value are preferentially charged and discharged for a short time, resulting in equalization of the capacitor voltage Vc in each of the cells 162 included in the arm unit 16. On the other hand, the cells 162 including capacitors C whose capacitor voltage Vc has a relatively low voltage value are preferentially charged and discharged for a long time, resulting in equalization of the capacitor voltage Vc in each of the cells 162 included in the arm unit 16.

Furthermore, the cell selection control unit 56 controls the cells 162 in the arm unit 16 to reduce the difference in the charge amount of the capacitor C (to balance the charge amount so that it is relatively uniform). Hereinafter, the control in the cell selection control unit 56 to balance the charge amount of the capacitor C (more specifically, the capacitor voltage Vc) so that it is uniform is referred to as "balance control". In the balance control in the cell selection control unit 56, the voltage value of the capacitor voltage Vc (capacitor voltage Vc-1 to capacitor voltage Vc-n of cells 162-1 to 162-n in FIG. 3) of the cells 162 belonging to the same arm unit 16 is acquired for each acquisition period TS1, that is, in a period shorter than the calculation period TS2 in which the sort list calculation unit 54 generates the sort list. Then, the cell selection control unit 56 compares the voltage value of each acquired capacitor voltage Vc with the upper threshold value Vc-max and the lower threshold value Vc-min of the capacitor voltage Vc in the capacitor C. As a result of this comparison, if the capacitor voltage Vc of the cell 162 in the inserted state during the charging period exceeds the threshold Vc-max, the cell selection control unit 56 controls the cell 162 to the bypass state so that the cell 162 is not charged any more (i.e., overcharged), and instead, from among the cells 162 in the bypass state, the same number of other cells 162 having capacitors C with lower capacitor voltage Vc values are preferentially selected and changed to the inserted state. On the other hand, if the capacitor voltage Vc of the cell 162 in the inserted state during the discharging period exceeds the threshold Vc-min, the cell selection control unit 56 controls the cell 162 to the bypass state so that the cell 162 is not discharged any more (i.e., overdischarged), and instead, from among the cells 162 in the bypass state, the same number of other cells 162 having capacitors C with higher capacitor voltage Vc values are preferentially selected and changed to the inserted state. The threshold Vc-max and threshold Vc-min are set to values that take into account the allowable fluctuation width of the capacitor C with respect to the rated capacitor voltage command value Vc*, for example. More specifically, the threshold value Vc-max is set to, for example, the upper limit of the fluctuation range of the capacitor voltage Vc during normal operation of the power converter 10, and is set to about Vc-max=Vc*×1.1, which is higher than the rated capacitor voltage command value Vc*. The threshold value Vc-min is set to, for example, the lower limit of the fluctuation range of the capacitor voltage Vc during normal operation of the power converter 10, and is set to about Vc-min=Vc*×0.9, which is lower than the rated capacitor voltage command value Vc*. The threshold values Vc-max and Vc-min may be set based on the average voltage Vc-ave (fluctuation value) of the capacitor voltage Vc in the capacitor C provided in the arm unit 16. The threshold value Vc-max is set to, for example, about Vc-max=Vc-ave×1.1, which is higher than the average voltage Vc-ave, so that the capacitor voltage Vc of the capacitor C does not vary from the average voltage Vc-ave by a certain amount or more. The threshold value Vc-min is set to, for example, approximately Vc-min = Vc-ave x 0.9, which is lower than the average voltage Vc-ave, so that the capacitor voltage Vc of the capacitor C does not vary more than a certain amount from the average voltage Vc-ave.

The cell selection control unit 56 generates a cell control state CL* for each cell 162. At this time, the cell selection control unit 56 may generate the cell control state CL* at any timing that matches the timing of the calculation (generation) of the sort list in the sort list calculation unit 54, the timing of the balance control in the sort list calculation unit 54, and the timing of the operation cycle (so-called operation clock or calculation clock) of the converter control unit 50 and the components included in the converter control unit 50. The cell control state CL* includes information indicating whether the corresponding cell 162 is controlled to at least the insert state or the bypass state. The cell selection control unit 56 outputs the cell control state CL* corresponding to each cell 162 to the gate signal generation unit 58. FIG. 3 shows cell control states CL*-1 to CL*-n corresponding to cells 162-1 to 162-n, respectively.

The cell selection control unit 56 is an example of a "unit converter selection unit" in the claims. The acquisition period TS1 is an example of a "first time interval" in the claims, and the calculation period TS2 is an example of a "second time interval" in the claims. The threshold value Vc-max is an example of a "first threshold value" in the claims, and the threshold value Vc-min is an example of a "second threshold value" in the claims.

The gate signal generating unit 58 generates a control signal (gate signal) to be output to all the cells 162 of each arm unit 16 according to each cell control state CL* output by the cell selection control unit 56. More specifically, the gate signal generating unit 58 generates a gate signal gtp corresponding to the switching element Q1 of each cell 162 and a gate signal gtn corresponding to the switching element Q2. FIG. 3 shows gate signals gtp-1 to gtp-n and gate signals gtn-1 to gtn-n corresponding to cells 162-1 to 162-n, respectively. At this time, the gate signal generating unit 58 may generate the gate signal gtn by, for example, logically inverting the gate signal gtp. However, even in this case, as described above, a short dead time is provided to prevent both ends of the capacitor C of the cell 162 from being short-circuited. The gate signal generating unit 58 outputs each generated gate signal to the corresponding cell 162 (more specifically, the switching element Q of the cell 162).

In FIG. 3, the gate signal generating unit 58 generates a gate signal corresponding to each cell 162 and outputs it to the corresponding cell 162. However, for example, the cell selection control unit 56 may output the cell control state CL* to each cell 162, and generate a gate signal corresponding to the cell control state CL* in each cell 162. In this case, each cell 162 is configured to include a component having a function equivalent to that of the gate signal generating unit 58.

With this configuration, the converter control unit 50 controls the cells 162 in each arm unit 16 of the power converter 10 to cause the power converter 10 to convert between AC power in the AC system and DC power in the DC system.

In the conventionally widely known phase shift PWM method, an individual triangular wave carrier and a voltage command value (modulation wave) are assigned to each cell, and a control signal (gate signal) is calculated for each cell. In contrast, in the converter control unit 50, the insert number calculation unit 52 calculates (calculates) the insert number Ncells representing the number of cells 162 to be inserted based on, for example, a triangular wave carrier not assigned to each cell 162 and a modulation wave based on the arm voltage command value Varm* of each arm unit 16. Then, in the converter control unit 50, the cell selection control unit 56 selects the cell 162 to be changed to the insert state or bypass state by referring to the polarity of the arm current Iarm and the sort list output by the sort list calculation unit 54, triggered by at least a change in the insert number Ncells. As a result, the gate signal generation unit 58 generates a gate signal for turning on or off the switching element Q equipped in each cell 162. In other words, in the converter control unit 50, there is no triangular wave carrier and voltage command value (modulation wave) assigned individually to each cell.

Furthermore, in the conventional phase shift PWM method, the amplitude of the voltage command value (modulation wave) for each cell is adjusted to manipulate the relatively long-cycle average power flowing in and out of the cell, thereby equalizing the capacitor voltage. For this reason, in the conventional phase shift PWM method, it takes a long time to balance the charge amount of the capacitors in each cell so that they are relatively uniform. In contrast, in the converter control unit 50 of the embodiment, the cell selection control unit 56 can perform balance control so that the charge amount of the capacitor C in the cell 162 is relatively uniform at each timing of switching control of the switching element Q in the cell 162. For this reason, in the converter control unit 50 of the embodiment, it is possible to equalize the charge amount of the capacitor C in a shorter time than in the conventional phase shift PWM method. As a result, in the power converter 10, the fluctuation range of the capacitor voltage Vc is suppressed by the balance control of the capacitor voltage Vc by the converter control unit 50 of the embodiment, and the voltage that can be output for each cell 162 can be secured, thereby reducing the constraints on operation. In the power converter 10, the maximum value of the capacitor voltage Vc is suppressed by the balance control of the capacitor voltage Vc by the converter control unit 50 of the embodiment, and the risk of failure of the capacitor C and the switching element Q of the cell 162 can be reduced.

As a result, the power conversion device 1 can simultaneously obtain high capacitor voltage balancing performance in the power converter 10 and high reliability with reduced risk of failure. Moreover, in the power conversion device 1, the balance control by the converter control unit 50 (more specifically, the cell selection control unit 56) is performed when the capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min. Therefore, in the power converter 10, even when the fluctuation range of the capacitor voltage Vc is narrow, such as during low-power operation, the cycle of the switching control for the cell 162 is short, that is, the switching frequency can be prevented from becoming high. Furthermore, in the power conversion device 1, even when, for example, a system accident occurs, the balance control by the converter control unit 50 operates to prevent the capacitor voltage Vc from deviating from the normal voltage range, so that the risk of the capacitor voltage Vc reaching an overvoltage or undervoltage and causing the protection device of the power converter 10 to operate and stop operation can be reduced. Therefore, in the power conversion device 1, the continuity of operation when a system accident occurs can be improved.

[First Operation of Power Conversion Apparatus]
Next, an example of the operation of the power conversion device 1, that is, the control of the cells 162 in the converter control unit 50 will be described. In the following description, the control over the arm unit 16-P-R included in the leg 12-R will be described as a representative of each of the legs 12-R, 12-S, and 12-T included in the power converter 10. In the following description, for ease of explanation, the operation of each of the components included in the converter control unit 50 will be described as being performed by the converter control unit 50 itself.

Figure 4 is a timing chart for explaining an example of the operation timing of the first operation in the power conversion device 1. The example of the operation of the power conversion device 1 shown in Figure 4 is an example of the operation when the arm unit 16-P-R (hereinafter simply referred to as "arm unit 16") has six cells 162 (n = 6). Figure 4 shows an example of balance control by the converter control unit 50 when the capacitor voltage Vc-5 of the cell 162-5 of the arm unit 16 exceeds the threshold value Vc-min (when it falls below the threshold value Vc-min). Figure 4 shows the temporal changes of the arm voltage command value Varm*, the arm current Iarm, the arm voltage Varm generated by the arm unit 16 based on the arm voltage command value Varm*, and the gate signals gtp-1 to gtp-6 output by the converter control unit 50 to the switching elements Q1 of the cells 162-1 to 162-6 on the same time axis. FIG. 4 also shows, on the same time axis, a schematic change in the capacitor voltage Vc (Vc-5) of cell 162-5, which is balanced by the converter control unit 50. Furthermore, FIG. 4 shows an example of a sort list calculated (generated) by the converter control unit 50 (more specifically, the sort list calculation unit 54). In the first operation shown in FIG. 4, the sort list is generated (updated) for each cycle of the arm voltage command value Varm*. FIG. 4 also shows an example of an acquisition cycle TS1 for acquiring the voltage value of the capacitor voltage Vc-5, and an example of a calculation cycle TS2 for creating the sort list.

The arm voltage command value Varm* includes the frequency of the AC system and a DC component. As described above, the converter control unit 50 (more specifically, the insert number calculation unit 52) calculates (calculates) the insert number Ncells, which is expressed as a stepped pseudo-sine wave, based on the arm voltage command value Varm*. In FIG. 4, the insert number Ncells is an integer value with a minimum value of "0" and a maximum value of "n (here, "6")". The insert number Ncells is calculated by approximating the value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 162 belonging to the arm unit 16 to an integer. In other words, the operation timing of the power conversion device 1 shown in FIG. 4 is the operation timing when the converter control unit 50 performs one-pulse control. The insert number Ncells represents something equivalent to the arm voltage Varm shown in FIG. 4.

The converter control unit 50 (more specifically, the cell selection control unit 56 and the gate signal generation unit 58) controls the gate signal gtp output to each cell 162 so that the number of cells 162 in the insert state belonging to the arm unit 16 matches the number (integer value) of cells 162 to be put into the insert state represented by the insert number Ncells at each timing when the insert number Ncells changes. Each gate signal gtp turns the switching element Q1 on when it is "1 ("High" level)" and turns the switching element Q1 off when it is "0 ("Low" level). Here, the gate signal gtn output to the switching element Q2 of the cell 162 can be generated by logically inverting the gate signal gtp as described above. For this reason, the gate signal gtn is omitted in FIG. 4. Therefore, in FIG. 4, the cell 162 is in the insert state when the gate signal gtp is "1" and in the bypass state when the gate signal gtp is "0". Furthermore, in Fig. 4, the dead time is omitted for ease of explanation. When the capacitor voltage Vc of the cells 162 is uniformly controlled, the arm voltage Varm is roughly the voltage value obtained by multiplying the number of cells 162 (integer value) to be inserted, which is represented by the number of inserts Ncells, by the capacitor voltage Vc.

The arm current Iarm contains the frequency of the AC system and a DC component. In the arm unit 16, when the arm current Iarm is positive (Iarm>0), the capacitor C of the cell 162 in the inserted state is charged, and the capacitor voltage Vc rises during this charging period. In the arm unit 16, when the arm current Iarm is negative (Iarm<0), the capacitor C of the cell 162 in the inserted state is discharged, and the capacitor voltage Vc falls during this discharging period. In the arm unit 16, regardless of the polarity of the arm current Iarm, the capacitor C of the cell 162 in the bypass state is neither charged nor discharged, and the current capacitor voltage Vc is maintained.

At time t0 shown in FIG. 4, the number of inserts Ncells is "3". Since the polarity of the arm current Iarm at this time is negative, the converter control unit 50 determines that it is a discharge polarity. For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C with the most stored power as the cell 162 to be inserted. More specifically, the converter control unit 50 selects cells 162-1, 162-2, and 162-3, which have the three highest capacitor voltages Vc (Vc-1, Vc-2, and Vc-3) in the sort list. For this reason, at time t0 shown in FIG. 4, the converter control unit 50 sets each of the gate signals gtp-1, gtp-2, and gtp-3 to "1" in order to insert the three selected cells 162. Here, cell 162-5 is in the bypass state because the gate signal gtp-5 is "0". As a result, capacitor C-5 in cell 162-5 is neither charged nor discharged, and maintains the current capacitor voltage Vc-5.

After that, when the number of inserts Ncells changes (increases) to "4" at time t1, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has the capacitor C with the second largest amount of stored power as the cell 162 to be inserted. Here, the converter control unit 50 has already selected three cells 162 with the third highest capacitor voltages Vc in the sort list, so it selects cell 162-4 with the next highest capacitor voltage Vc (i.e., the fourth highest Vc-4). Then, at time t1, the converter control unit 50 sets the gate signal gtp-4 to "1" in order to further insert the selected cell 162-4. At this time, cell 162-5 is still in the bypass state, so cell 162-5 continues to maintain the current capacitor voltage Vc-5.

After that, when the number of inserts Ncells changes (increases) to "5" at time t2, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive polarity (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a small amount of stored power as the cell 162 to be inserted. Here, the converter control unit 50 selects the cell 162-6, which is the cell with the lowest capacitor voltage Vc in the sort list (i.e., Vc-6). Then, at time t2, the converter control unit 50 sets the gate signal gtp-6 to "1" to further insert the selected cell 162-6. At this time, the cell 162-5 is still in the bypass state, so the cell 162-5 continues to maintain the current capacitor voltage Vc-5.

After that, when the number of inserts Ncells changes (increases) to "6" at time t3, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive polarity (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has the capacitor C with the next lowest stored power as the cell 162 to be inserted. Here, the converter control unit 50 has already selected one cell 162 with the first lowest capacitor voltage Vc in the sort list, so it selects the cell 162-5 with the next lowest capacitor voltage Vc (i.e., the second lowest Vc-5). Then, at time t3, the converter control unit 50 sets the gate signal gtp-5 to "1" to further insert the selected cell 162-5. As a result, the capacitor C-5 of the cell 162-5 is charged, and the capacitor voltage Vc-5 rises (increases) as it is charged.

After that, at time t4, when the number of inserts Ncells changes (decreases) to "5", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive polarity (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a large amount of stored power as the cell 162 to be placed in the bypass state. Here, the converter control unit 50 selects the cell 162-1, which is the first cell in the sort list with the highest capacitor voltage Vc (i.e., Vc-1). Then, at time t4, the converter control unit 50 sets the gate signal gtp-1 to "0" to place the selected cell 162-1 in the bypass state. At this time, since the cell 162-5 is still in the insert state, the capacitor C-5 continues to be charged and the capacitor voltage Vc-5 rises.

After that, at time t5, when the number of inserts Ncells changes (decreases) to "4", the converter control unit 50 selects cell 162-2, which has the second highest capacitor voltage Vc in the sort list (i.e., Vc-2), just as at time t4, and sets gate signal gtp-2 to "0" to put the selected cell 162-2 into a bypass state. At this time, cell 162-5 is still in the insert state, so capacitor C-5 continues to charge and capacitor voltage Vc-5 rises.

After that, at time t6, when the polarity of the arm current Iarm becomes negative (discharge polarity), cell 162-5, which is in the inserted state, begins to discharge the power stored in capacitor C-5. As a result, capacitor voltage Vc-5 drops (decreases) as it is discharged.

After that, at time t7, when the number of inserts Ncells changes (decreases) to "3", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a small amount of stored power as the cell 162 to be placed in the bypass state. Here, the converter control unit 50 selects the cell 162-6, which is the first cell in the sort list with the lowest capacitor voltage Vc (i.e., Vc-6). Then, at time t6, the converter control unit 50 sets the gate signal gtp-6 to "0" to place the selected cell 162-6 in the bypass state. At this time, the cell 162-5 is still in the insert state, so it continues to discharge the power stored in the capacitor C-5, and the capacitor voltage Vc-5 decreases.

After that, when the capacitor voltage Vc-5 of cell 162-5 exceeds the threshold Vc-min at time t8, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 162 to be inserted in place of the bypassed cell 162-5, with the sort list, in order to put the cell 162-5 in the bypass state. Here, the converter control unit 50 selects the cell 162-1, which is the first cell in the sort list with the highest capacitor voltage Vc (i.e., Vc-1). Then, at time t8, the converter control unit 50 sets the gate signal gtp-5 to "0" in order to put the cell 162-5 in the bypass state. As a result, the discharge from the cell 162-5 is stopped, and the discharge from the capacitor C-5 of the cell 162-5 is continued, so that the capacitor voltage Vc-5 does not fall significantly below the threshold Vc-min, as shown by the dashed line in FIG. 4. That is, the capacitor voltage Vc-5 is maintained at a voltage value close to the threshold value Vc-min, as shown by the solid line in FIG. 4. Furthermore, at time t8, the converter control unit 50 sets the gate signal gtp-1 to "1" to put the selected cell 162-1 into the insert state. This causes the capacitor voltage of cell 162-1 to be output as a substitute, and prevents the arm voltage Varm from deviating (including an error) from the ideal stepped waveform according to the arm voltage command value Varm*.

After that, when the number of inserts Ncells changes (decreases) to "2" at time t9, the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a small amount of stored power as the cell 162 to be placed in the bypass state. Here, the converter control unit 50 has already selected two cells 162 with the first and second lowest capacitor voltages Vc in the sort list, so it selects the cell 162-4 with the next lowest capacitor voltage Vc (i.e., the third lowest Vc-4). Then, at time t9, the converter control unit 50 sets the gate signal gtp-4 to "0" in order to place the selected cell 162-4 in the bypass state. Note that at time t9, the converter control unit 50 may select the cell 162-1 that was placed in the insert state instead of the cell 162-5 that was placed in the bypass state at time t8, and place it in the bypass state. At this time, cell 162-5 is still in a bypass state, so the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, from time t10 to time t11, each time the number of inserts Ncells changes (decreases) from "1" to "0", the converter control unit 50, like at time t7, sequentially selects the cells 162 with the fourth and sixth lowest capacitor voltages Vc in the sort list (i.e., Vc-3, Vc-1), and sets the gate signal gtp to "0" to put the selected cells 162 into a bypass state. More specifically, at time t10, the converter control unit 50 selects cell 162-3 and sets the gate signal gtp-3 to "0", and at time t11, it selects cell 162-1 and sets the gate signal gtp-1 to "0". At this time, cell 162-5 is still in a bypass state, so the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold value Vc-min.

Then, at time t12, the sort list is updated. Here, the order of the voltage values of the capacitor voltage Vc, rearranged in descending order, in the updated sort list is assumed to be the same as that in the sort list before the update.

After that, at time t13, when the number of inserts Ncells changes (increases) to "1", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 162 to be inserted. Here, the converter control unit 50 selects the cell 162-1, which is the first cell in the sort list with the highest capacitor voltage Vc (i.e., Vc-1). Then, at time t13, the converter control unit 50 sets the gate signal gtp-1 to "1" to insert the selected cell 162-1. At this time, the cell 162-5 is still in the bypass state, so the capacitor voltage Vc-5 of the cell 162-5 continues to be maintained at a voltage value close to the current threshold value Vc-min.

After that, from time t14 to time t15, each time the number of inserts Ncells changes (increases) sequentially to "2" and "3", the converter control unit 50 sequentially selects the cells 162 with the second and third highest capacitor voltages Vc in the sort list (i.e., Vc-2 and Vc-3) in the same manner as at time t13, and sets the gate signal gtp to "1" to put the selected cells 162 into the insert state. More specifically, the converter control unit 50 selects cell 162-2 at time t14 and sets the gate signal gtp-2 to "1", and at time t15 selects cell 162-3 and sets the gate signal gtp-3 to "1". At this time, cell 162-5 is still in the bypass state, so the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold value Vc-min.

In this way, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm each time the number of inserts Ncells changes (increases or decreases), and selects a cell 162 whose control state is to be changed to the insert state or bypass state by referring to the sort list, and controls the gate signal gtp of the selected cell 162. At this time, if the capacitor voltage Vc in any of the cells 162 exceeds the threshold value Vc-max (exceeds the threshold value Vc-max) or exceeds the threshold value Vc-min (falls below the threshold value Vc-min), the converter control unit 50 performs balance control. In other words, the converter control unit 50 performs balance control when the capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min, regardless of the timing of calculation (generation) of the sort list or the timing of switching control. In balance control, the converter control unit 50 causes the cell 162 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min to be in the bypass state. As a result, the cell 162 in the bypass state stops charging to the capacitor C or discharging from the capacitor C. Then, the converter control unit 50 refers to the sort list and selects a cell 162 to replace the cell 162 in the bypass state from among the cells 162 currently in the bypass state and inserts the cell 162 into the insert state. As a result, in the power converter 10, the capacitor C of the cell 162 is prevented from being charged or discharged more than it is now (without overcharging or overdischarging), and the charge amount of the capacitor C can be balanced so that it is relatively uniform. In the first operation of the power conversion device 1 shown in FIG. 4, a case where the capacitor voltage Vc-5 of the cell 162-5 exceeds the threshold value Vc-min at time t8 is shown, but the balance control in the converter control unit 50 is similar for the other cells 162. In the first operation of the power conversion device 1 shown in FIG. 4, a case where the cell 162-1 is selected as a replacement for the cell 162-5 at time t8 is shown, but the selection as a replacement is similar for the other cells 162. In the first operation of the power conversion device 1 shown in FIG. 4, the balance control in the converter control unit 50 shows the balance control when the capacitor voltage Vc-5 of cell 162-5 exceeds the threshold value Vc-min, but the balance control when the capacitor voltage Vc of any of the cells 162 in the arm unit 16 exceeds the threshold value Vc-max can also be equivalent to the balance control of the first operation described above.

[Second Operation of Power Conversion Apparatus]
In the first operation described above, the converter control unit 50 performs single-pulse control, but the converter control unit 50 can also perform multi-pulse control. Next, an operation in which the converter control unit 50 performs multi-pulse control will be described as another operation of the power conversion device 1 (another example of balance control in the converter control unit 50).

Figure 5 is a timing chart for explaining an example of the operation timing of the second operation in the power conversion device 1. The second operation shown in Figure 5 is also an operation in the case where the arm unit 16 has six cells 162 (n = 6), like the first operation shown in Figure 4. The number of inserts Ncells is calculated as the number of triangular wave carrier waves whose value of the arm voltage command value Varm* (modulation wave) exceeds the value of the triangular wave carrier, for example, by comparing the modulated wave based on the arm voltage command value Varm* with each triangular wave carrier whose phase and level are shifted from each other and whose number is the same as the number of cells 162 belonging to the arm unit 16 (here, "6"). In the second operation, the converter control unit 50 performs multi-pulse control to control the cells 162 belonging to the arm unit 16 multiple times within one period of the arm voltage command value Varm*, so the operation timing of the power conversion device 1 shown in Figure 5 is shown by enlarging a part of the range within one period of the arm voltage command value Varm*.

The second operation shown in FIG. 5 is an example of a case where balance control is performed during a period in which the number of cells 162 in the inserted state represented by the number of inserts Ncells is "2" before changing from "2" to "1" during a discharge polarity (discharge period) in which the polarity of the arm current Iarm is negative (Iarm<0), that is, during a period in which the number of cells 262 in the inserted state remains unchanged at "2". In the second operation shown in FIG. 5, the sort list calculation unit 54 generates a sort list in a calculation period TS2 that is shorter than that in the first operation shown in FIG. 4. However, even in the second operation shown in FIG. 5, the calculation period TS2 is a period (TS2>TS1) with a longer time interval than the acquisition period TS1. FIG. 5 shows an example of balance control by the converter control unit 50 when the capacitor voltage Vc-3 of the cell 162-3 included in the arm unit 16 exceeds the threshold value Vc-min (below the threshold value Vc-min).

At time t0 shown in FIG. 5, the number of inserts Ncells is "2". Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C with the most stored power as the cell 162 to be inserted. More specifically, the converter control unit 50 selects cells 162-1 and 162-3, which have the two highest capacitor voltages Vc (Vc-1 and Vc-3) in the sort list. Therefore, at time t0 shown in FIG. 5, the converter control unit 50 sets each of the gate signals gtp-1 and gtp-3 to "1" in order to insert the two selected cells 162. Therefore, in cell 162-3, the power stored in capacitor C-3 is discharged, and the capacitor voltage Vc-3 drops (decreases) as it is discharged.

After that, when the capacitor voltage Vc-3 of the cell 162-3 exceeds the threshold value Vc-min at time t1, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 162 to be inserted in place of the cell 162-3 that has been placed in the bypass state, in order to place the cell 162-3 in the bypass state. Here, the converter control unit 50 selects the cell 162-2, which has the third highest capacitor voltage Vc in the sort list (i.e., Vc-2). Then, at time t1, the converter control unit 50 sets the gate signal gtp-3 to "0" in order to place the cell 162-3 in the bypass state. As a result, the discharge from the cell 162-3 is stopped, and the discharge from the capacitor C-3 of the cell 162-3 is continued, so that the capacitor voltage Vc-3 does not fall significantly below the threshold value Vc-min, as shown by the dashed line in FIG. 5 (when balance control is performed only in accordance with the sort list update). That is, the capacitor voltage Vc-3 is maintained at a voltage value close to the threshold value Vc-min, as shown by the solid line in FIG. 5. Furthermore, at time t1, the converter control unit 50 sets the gate signal gtp-2 to "1" to put the selected cell 162-2 into the insert state. This causes the capacitor voltage of cell 162-2 to be output as a substitute, and the arm voltage Varm is maintained.

Then, at time t2, the sort list is updated. Here, the sort list is updated to one in which the capacitor voltage Vc-3 of cell 162-3 has the lowest capacitor voltage Vc.

After that, at time t3, when the number of inserts Ncells changes (decreases) to "1", the converter control unit 50 refers to the sort list and selects the cell 162 that is currently in the insert state and has a capacitor C with a small amount of stored power as the cell 162 to be placed in the bypass state. Here, the converter control unit 50 selects cell 162-2, which has the lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from among cells 162-1 and 162-2 that are in the insert state. Then, at time t3, the converter control unit 50 sets the gate signal gtp-2 to "0" to place the selected cell 162-2 in the bypass state. At this time, cell 162-3 is still in the bypass state, so the capacitor voltage Vc-3 of cell 162-3 continues to be maintained at a voltage value close to the current threshold value Vc-min.

In this way, in the second operation (multiple pulse control), as in the first operation (single pulse control) shown in FIG. 4, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (increases or decreases), refers to the sort list, selects the cell 162 whose control state is to be changed to the insert state or bypass state, and controls the gate signal gtp of the selected cell 162. At this time, in the second operation, if the capacitor voltage Vc in any of the cells 162 exceeds the threshold value Vc-max (exceeds the threshold value Vc-max) or exceeds the threshold value Vc-min (falls below the threshold value Vc-min), the converter control unit 50 performs balance control. In other words, in the second operation, the converter control unit 50 performs balance control when the capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min, regardless of the timing of calculation (generation) of the sort list or the timing of switching control. In the balance control of the second operation, the converter control unit 50 also puts the cell 162 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min into a bypass state. As a result, in the second operation, the cell 162 put into the bypass state stops charging to the capacitor C or discharging from the capacitor C. Then, in the second operation, the converter control unit 50 also refers to the sort list and selects a cell 162 to replace the cell 162 put into the bypass state from among the cells 162 currently in the bypass state and puts it into the insert state. As a result, in the power converter 10, in the second operation, the capacitor C included in the cell 162 is not charged or discharged more than it is now (without overcharging or overdischarging), and the charge amount of the capacitor C can be balanced to be relatively uniform. In the second operation of the power conversion device 1 shown in FIG. 5, a case is shown in which the capacitor voltage Vc-3 of the cell 162-3 exceeds the threshold value Vc-min at time t1, but the balance control in the converter control unit 50 is similar for the other cells 162. In the second operation of the power conversion device 1 shown in FIG. 5, the case where the cell 162-2 is selected as a replacement for the cell 162-3 at time t1 is shown, but the selection as a replacement is similar for the other cells 162. In the second operation of the power conversion device 1 shown in FIG. 5, the balance control in the converter control unit 50 is shown as a balance control when the capacitor voltage Vc-3 of the cell 162-3 exceeds the threshold value Vc-min, but the balance control when the capacitor voltage Vc of any of the cells 162 included in the arm unit 16 exceeds the threshold value Vc-max may also be equivalent to the balance control of the second operation described above.

With such a configuration and operation, in the power conversion device 1, the converter control unit 50 judges whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm for each timing when the number of inserted cells 162 Ncells changes (increases or decreases) for each arm unit 16 equipped in the power converter 10. Then, in the power conversion device 1, the converter control unit 50 refers to the sort list calculated (generated) for each arm unit 16, selects a cell 162 whose control state is to be changed to an insert state or a bypass state, and changes the control state of the selected cell 162. At this time, if the capacitor voltage Vc of any cell 162 exceeds the threshold value Vc-max or threshold value Vc-min, the converter control unit 50 puts that cell 162 into the bypass state, and refers to the sort list to select an alternative cell 162 from among the cells 162 currently in the bypass state and puts it into the insert state. As a result, the power conversion device 1 can prevent overcharging or overdischarging of the capacitor C of the cell 162 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min, and can balance the charge amount of the capacitor C so that it is relatively uniform. As a result, the power conversion device 1 can reduce the risk of failure of the capacitor C or the switching element Q of the cell 162 in the power converter 10, and can reduce the risk of a state in which the protection device of the power converter 10 operates and stops operation due to the capacitor voltage Vc reaching an overvoltage or undervoltage even when a system accident occurs. As a result, the power conversion device 1 can realize a highly reliable power conversion device with improved performance for continuing operation when a system accident occurs.

As described above, in the power conversion device 1 of the first embodiment, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm for each arm unit 16 equipped in the power converter 10 at each timing when the number of inserted cells 162 Ncells changes (increases or decreases). Then, in the power conversion device 1 of the first embodiment, the converter control unit 50 refers to the sort list calculated (generated) for each arm unit 16, selects the cell 162 whose control state is to be changed to the insert state or bypass state, and changes the control state of the selected cell 162. At this time, in the power conversion device 1 of the first embodiment, if the capacitor voltage Vc in any of the cells 162 exceeds the threshold value Vc-max or threshold value Vc-min, the converter control unit 50 puts the cell 162 into the bypass state, and refers to the sort list to select an alternative cell 162 from among the cells 162 currently in the bypass state and puts it into the insert state. As a result, in the power conversion device 1 of the first embodiment, it is possible to prevent overcharging or overdischarging of the capacitor C of the cell 162 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min, and to balance the charge amount of the capacitor C so that it is relatively uniform. As a result, in the power conversion device 1 of the first embodiment, it is possible to reduce the risk of failure of the capacitor C or the switching element Q of the cell 162 in the power converter 10, and for example, even when a system accident occurs, it is possible to reduce the risk of a state in which the protection device of the power converter 10 operates and stops operation due to the capacitor voltage Vc reaching an overvoltage or undervoltage. As a result, in the power conversion device 1 of the first embodiment, it is possible to realize a highly reliable power conversion device with improved continuity of operation when a system accident occurs.

In the power conversion device 1 of the first embodiment described above, the power converter 10 is, for example, provided at the interconnection point between an AC system and a DC system, and is a double star-connected MMC that converts AC power supplied by the AC system and DC power supplied by the DC system in response to control from the converter control unit 50. However, the power converter 10 may be a power converter of another configuration.

Second Embodiment
[Configuration of power conversion device]
The second embodiment will be described below. FIG. 6 is a diagram showing an example of the configuration of a power conversion device according to the second embodiment. FIG. 6 shows an example of a power conversion device 2 that is connected to an AC system and adjusts the reactive power of the AC system. The power conversion device 2 can adjust the active power of the AC system when, for example, a cell 262 described later is configured to include an energy storage element such as a storage battery. The AC system may be, for example, an AC power source or an AC load, as in the first embodiment. The power conversion device 2 includes a power converter 20 and a converter control unit 50a. In FIG. 6, components having the same functions as those of the power conversion device 1 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

The power converter 20 is a single delta-connected modular multilevel converter (MMC) that converts AC power in response to control from the converter control unit 50a. The power converter 20 has multiple legs 22 between the lines of the AC system. The number of legs 22 included in the power converter 20 corresponds to the number of lines of the AC power supplied by the AC system. FIG. 6 shows a case in which the AC system supplies three-phase AC power, namely, a first phase (R phase), a second phase (S phase), and a third phase (T phase). For this reason, FIG. 6 shows the configuration of the power converter 20 that has three legs 22, namely, a leg 22-RS, a leg 22-ST, and a leg 22-TR. Each of the legs 22-RS, the leg 22-ST, and the leg 22-TR has the same configuration.

In each leg 22, the AC terminal CA is connected to a terminal of any phase of the AC system, and the AC terminal CB is connected to a terminal of any other phase in the AC system that is different from the phase connected to the AC terminal CA. More specifically, in the leg 22-RS corresponding to the R-phase and S-phase, the AC terminal CA-R is connected to the R-phase AC terminal R of the AC system, and the AC terminal CB-S is connected to the S-phase AC terminal S of the AC system. In the leg 22-ST corresponding to the S-phase and T-phase, the AC terminal CA-S is connected to the S-phase AC terminal S of the AC system, and the AC terminal CB-T is connected to the T-phase AC terminal T of the AC system. In the leg 22-TR corresponding to the T-phase and R-phase, the AC terminal CA-T is connected to the T-phase AC terminal T of the AC system, and the AC terminal CB-R is connected to the R-phase AC terminal R of the AC system. FIG. 6 shows a case where the AC terminal CA of each leg 22 is connected to a terminal of the corresponding phase of the AC system via a transformer TR.

Each leg 22 includes, for example, a reactor 14 and an arm unit 26. Each arm unit 26 includes, for example, n cells 262 (cells 262-1 to 262-n) connected in series (n is a natural number). In FIG. 6, in order to distinguish which phase or interphase of the AC system each component included in the leg 22 corresponds to, a "- (hyphen)" and the letter "R" representing the R phase, the letter "S" representing the S phase, the letter "T" representing the T phase, the letter "RS" representing the interphase between the R phase and the S phase, the letter "ST" representing the interphase between the S phase and the T phase, or the letter "TR" representing the interphase between the T phase and the R phase are added after each reference symbol. In the following description, when it is not necessary to distinguish which phase or interphase of the AC system each component corresponds to, the hyphen and the identifying letter following the hyphen are omitted.

In each leg 22, the reactor 14 is connected in series to the AC terminal CA side of the arm unit 26. In each leg 22, the end of the reactor 14 that is not connected to the arm unit 26 serves as the AC terminal CA. In each leg 22, the terminal of the arm unit 26 opposite the reactor 14 serves as the AC terminal CB of the leg 22. In other words, in each leg 22, the reactor 14 and cells 262-1 to 262-n are connected in series in this order from the AC terminal CA side toward the AC terminal CB side, and are connected to the AC terminal CA.

The leg 22 is an example of a "phase unit" in the claims. The arm unit 26 (which may include the reactor 14) is an example of an "arm unit" in the claims. The cell 262 is an example of a "unit converter" in the claims. The reactor 14 is an example of an "inductance element" in the claims.

In FIG. 6, the reactor 14 is shown arranged on the AC terminal CA side of the arm unit 26 in each leg 22, but the reactor 14 may be arranged on the opposite side of the AC terminal CA side of the arm unit 26 (i.e., on the AC terminal CB side) or at any position within the arm unit 26 (i.e., between any two cells 262 connected in series in the arm unit 26). The reactor 14 may be replaced with a transformer with a special winding structure that has a leakage reactance sufficient to replace the function of the reactor. In this case, the reactor 14 may be integrated with the transformer TR.

Each arm unit 26 generates a stepped sine wave (multi-level waveform) AC voltage representing the AC waveform to be supplied between the corresponding phases of the AC system in response to control from the converter control unit 50a for each of the series-connected cells 262.

Here, an example of the configuration of the cell 262 included in the arm unit 26 will be described. The cell 262 is, for example, a full bridge circuit. FIG. 7 is a diagram showing an example of the configuration of the cell 262 in the leg 22 included in the power converter 20. The cell 262 includes four switching elements Q (switching elements Q1 to Q4), four diodes D (diodes D1 to D4), and a capacitor C. The switching elements Q are, for example, insulated gate bipolar transistors (IGBTs), similar to the switching elements Q included in the cell 162 of the first embodiment. Therefore, the switching elements Q are not limited to IGBTs, and may be any element as long as they are self-extinguishing semiconductor switching elements capable of realizing a converter or inverter.

In cell 262, switching element Q1 and switching element Q2 are connected in series, and switching element Q3 and switching element Q4 are connected in series. In cell 262, the series circuit of switching element Q1 and switching element Q2, the series circuit of switching element Q3 and switching element Q4, and capacitor C are connected in parallel. In cell 262, each switching element Q and its corresponding diode D are connected in parallel. In cell 262, the connection point between the emitter of switching element Q1 and the collector of switching element Q2 is the positive terminal TP(+) connected to the AC terminal CA side in leg 22, and the connection point between the emitter of switching element Q3 and the collector of switching element Q4 is the negative terminal TN(-) connected to the AC terminal CB side in leg 22.

A control signal from the converter control unit 50a is input to the gates of each of the switching elements Q1 to Q4 of the cell 262 (a control voltage is applied or a control current is supplied). A gate signal gta is input to the gate of the switching element Q1 as a control signal from the converter control unit 50a, a gate signal gtb is input to the gate of the switching element Q2 as a control signal from the converter control unit 50a, a gate signal gtc is input to the gate of the switching element Q3 as a control signal from the converter control unit 50a, and a gate signal gtd is input to the gate of the switching element Q4 as a control signal from the converter control unit 50a. As a result, each of the switching elements Q1 to Q4 is switched to either an on state or an off state by the converter control unit 50a. In the following explanation, when a control signal (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) of "1 (High level)" is input, each switching element Q is turned on, and when a control signal (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) of "0 (Low level)" is input, each switching element Q is turned off.

The capacitor C is charged or discharged depending on the state of each switching element Q. In the cell 262, the terminal voltage (capacitor voltage Vc) of the capacitor C is generated as the terminal voltage (cell voltage Vo) between the positive terminal TP and the negative terminal TN of the cell 262. More specifically, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd) = (1, 0, 0, 1), for example, a current flows in the order of the positive terminal TP, the switching element Q1, the capacitor C, the switching element Q4, and the negative terminal TN, and the cell voltage Vo of the cell 262 coincides with the capacitor voltage Vc. In other words, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd) = (1, 0, 0, 1), the capacitor C is inserted between the positive terminal TP and the negative terminal TN of the cell 262, and the capacitor voltage Vc is output as the cell voltage Vo. In the following description, the converter control unit 50a setting the control signals (gta, gtb, gtc, gtd) = (1, 0, 0, 1) is referred to as "positive voltage insertion", and the state of the cell 262 in this case is referred to as "positive voltage insertion state". On the other hand, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd) = (0, 1, 1, 0), for example, a current flows in the order of the positive terminal TP, the switching element Q2, the capacitor C, the switching element Q3, and the negative terminal TN, and the cell voltage Vo of the cell 262 coincides with the inversion of the capacitor voltage Vc. In other words, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd) = (0, 1, 1, 0), the capacitor C is inserted in the reverse direction between the positive terminal TP and the negative terminal TN of the cell 262, and the negative capacitor voltage Vc is output as the cell voltage Vo. In the following description, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(0, 1, 1, 0), this is referred to as "negative voltage insertion," and the state of the cell 262 in this case is referred to as "negative voltage insertion state." Furthermore, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd)=(1, 0, 1, 0) or (0, 1, 0, 1), for example, a current flows in the order of the positive terminal TP, diode D1, switching element Q3, and negative terminal TN, or in the order of the positive terminal TP, switching element Q2, diode D4, and negative terminal TN, and the cell voltage Vo of the cell 262 becomes 0 [V]. In other words, when the converter control unit 50a sets the control signals (gta, gtb, gtc, gtd) = (1, 0, 1, 0) or (0, 1, 0, 1), the positive terminal TP and the negative terminal TN of the cell 262 are shorted, and the current flows without passing through the capacitor C, so that the cell voltage Vo of the cell 262 becomes 0 [V]. In the following description, the converter control unit 50a setting the control signals (gta, gtb, gtc, gtd) = (1, 0, 1, 0) or (0, 1, 0, 1) is referred to as "bypass", and the state of the cell 262 in this case is referred to as the "bypass state".

Cell 262 is not limited to the configuration shown in FIG. 7, and may have any configuration that achieves the same function as cell 262.

The switching element Q1 and the diode D1 are an example of the "switching element" and the "first switching element" in the claims, the switching element Q2 and the diode D2 are an example of the "switching element" and the "second switching element" in the claims, the switching element Q3 and the diode D3 are an example of the "switching element" and the "third switching element" in the claims, and the switching element Q4 and the diode D4 are an example of the "switching element" and the "fourth switching element" in the claims. The parallel circuit of the switching element Q1 and the diode D1 and the parallel circuit of the switching element Q2 and the diode D2 are an example of the "first series circuit" in the claims, and the parallel circuit of the switching element Q3 and the diode D3 and the parallel circuit of the switching element Q4 and the diode D4 are an example of the "second series circuit" in the claims. The on state is an example of the "conductive state" in the claims, and the off state is an example of the "non-conductive state" in the claims. The capacitor C is an example of an "energy storage element" in the claims. The positive terminal TP is an example of a "first end" in the claims, and the negative terminal TN is an example of a "second end" in the claims. The positive voltage insert state is an example of a "first first control state" in the claims, the negative voltage insert state is an example of a "second first control state" in the claims, and the bypass state is an example of a "second control state" in the claims.

By connecting multiple cells 262 of this configuration in series, the arm unit 26 outputs a voltage obtained by adding the cell voltages Vo of the cells 262 controlled to the insert state (positive voltage insert state or negative voltage insert state). Therefore, the arm unit 26 outputs a voltage according to the number of cells 262 controlled to the insert state (positive voltage insert state or negative voltage insert state) by the converter control unit 50a. As a result, the arm unit 26 generates a multi-level waveform according to the control from the converter control unit 50a. The cells 262 may be provided in each arm unit 16 provided in the power converter 10 of the first embodiment, instead of the cells 162 of the first embodiment.

By the way, in cell 262, it should be prohibited to set the control signal (gta, gtb) = (1, 1) or the control signal (gtc, gtd) = (1, 1). This is because when the control signal (gta, gtb) = (1, 1) is set, both switching elements Q1 and Q2 are turned on, and when the control signal (gtc, gtd) = (1, 1) is set, both switching elements Q3 and Q4 are turned on, and in either case, both ends of the capacitor C are short-circuited. For this reason, when switching (changing) the control signals (gta, gtb, gtc, gtd) between (1, 0, 0, 1), (0, 1, 1, 0), (1, 0, 1, 0), and (0, 1, 0, 1), the converter control unit 50a performs control so as to provide a period (so-called dead time) in which the control signals (gta, gtb) = (0, 0) or the control signals (gtc, gtd) = (0, 0) for a very short period of time. When the converter control unit 50a stops the operation of the cell 262, the control signals (gta, gtb, gtc, gtd) may be fixed to (0, 0, 0, 0). In the following description, the converter control unit 50a fixes all control signals (gta, gtb, gtc, gtd) to (0, 0, 0, 0) to stop the operation of all cells 262 in the arm unit 26 of the power converter 20, which is referred to as "gate block," and the state of the cells 262 in this case is referred to as the "gate block state."

Returning to FIG. 6, the converter control unit 50a, like the converter control unit 50 included in the power conversion device 1 of the first embodiment, calculates an AC voltage command value including the frequency of the AC system based on the operating state of the power conversion device 2 and the detection values (current value, current flow direction (polarity), voltage value) at each position in the power conversion device 2. For this reason, like the converter control unit 50, the converter control unit 50a acquires detection values output by a detector (described later) provided at a desired position inside or outside the power conversion device 2 at a predetermined (constant) acquisition period TS1. Then, the converter control unit 50a calculates a voltage command value for each arm unit 26 including a voltage component represented by the calculated AC voltage command value. The converter control unit 50a generates a control signal for controlling the switching of the switching element Q in the cell 262 included in each arm unit 26 based on the calculated voltage command value. The converter control unit 50a then outputs the generated control signal to the corresponding cell 262. For example, when the converter control unit 50a controls the arm unit 26-RS, which is the arm unit 26 between the R phase and the S phase of the AC system, the converter control unit 50a calculates an arm voltage command value Varm* corresponding to an arm voltage Varm-R to be output between the AC terminals CA-R and CB-S. In the following description, the positive polarity of the arm voltage Varm and the arm voltage command value Varm* is defined as the direction in which the potential on the cell 262-1 side becomes higher when viewed from the cell 262-n side. Then, the converter control unit 50a generates gate signals gta (gate signals gta-1-RS to gta-n-RS), gate signals gtb (gate signals gtb-1-RS to gtb-n-RS), gate signals gtc (gate signals gtc-1-RS to gtc-n-RS), and gate signals gtd (gate signals gtd-1-RS to gtd-n-RS) for controlling the switching elements Q in the respective cells 262 (cells 262-1-RS to 262-n-RS) included in the arm unit 26-RS based on the calculated arm voltage command value Varm*. The converter control unit 50a outputs the generated gate signals gta, gtb, gtc, and gtd to the corresponding cells 262. The same applies when the converter control unit 50a controls the other arm units 16. The converter control unit 50a includes, for example, an insert number calculation unit 52a, a sort list calculation unit 54a, a cell selection control unit 56a, and a gate signal generation unit 58a.

The converter control unit 50a controls the operation of the power converter 20 by, for example, a hardware processor such as a CPU executing a program (software). The converter control unit 50a may be realized by hardware (including circuitry) such as an LSI, ASIC, FPGA, or GPU, or may be realized by collaboration between software and hardware. The converter control unit 50a may be realized by a dedicated LSI. The program may be stored in advance in a storage device (storage device with a non-transient storage medium) such as an HDD or flash memory provided in the converter control unit 50a or the power conversion device 2, or may be stored in a removable storage medium (non-transient storage medium) such as a DVD or CD-ROM, and the storage medium may be installed in the HDD or flash memory provided in the converter control unit 50a or the power conversion device 2 by attaching the storage medium to a drive device provided in the converter control unit 50a or the power conversion device 2.

In the power conversion device 2, similarly to the power conversion device 1 of the first embodiment, a current detector and a voltage detector are provided at desired positions to detect the current value, the polarity of the current, and the voltage value. In the example of FIG. 6, a current detector for detecting the arm current I flowing from the AC terminal CA side to the AC terminal CB side is provided in each leg 22. More specifically, a current detector for detecting the arm current Irs flowing from the AC terminal CA-R side to the AC terminal CB-S side is provided between the reactor 14-RS and the arm unit 26-RS in the leg 22-RS. The other legs 22 are similar. Although not shown in FIG. 7, each cell 262 is also provided with a voltage detector for detecting the capacitor voltage Vc. The R-phase AC current Ir, the S-phase AC current Is, and the T-phase AC current It may be directly detected by providing a current detector at the AC terminal R, the AC terminal S, and the AC terminal T, or may be indirectly detected by calculating the arm current I detected in each leg 22. For example, the R-phase AC current Ir may be indirectly detected by calculating the difference between the R-phase and S-phase arm current Irs and the T-phase and R-phase arm current Itr (i.e., Irs-Itr). Furthermore, although the voltage detector is not shown in FIG. 6, the case where the R-phase AC voltage Vsr, the S-phase AC voltage Vss, and the T-phase AC voltage Vst are detected is shown.

The converter control unit 50a outputs control signals (gate signals) corresponding to the respective cells 262 of the arm unit 26, since the arm unit 16 of the power conversion device 1 of the first embodiment is replaced by the arm unit 26 of the power conversion device 2. However, the configuration of the converter control unit 50a is similar to the configuration of the converter control unit 50 of the power conversion device 1 of the first embodiment shown in FIG. 3. Therefore, an example of the configuration of the converter control unit 50a of the power conversion device 2 is not illustrated, and the following describes the different operations of the respective components of the converter control unit 50 of the first embodiment and the respective components of the converter control unit 50a.

The insert number calculation unit 52a performs the same processing as the insert number calculation unit 52 of the first embodiment. The insert number calculation unit 52a calculates (calculates) the number of inserts Ncells for each arm unit 26 based on the arm voltage command value Varm*. However, unlike the insert number calculation unit 52, the insert number calculation unit 52a calculates (calculates) the number of inserts Ncells including information indicating whether the insert state is a positive voltage insert state or a negative voltage insert state for each arm unit 26. More specifically, for example, the insert number calculation unit 52a calculates (calculates) the number (integer value, absolute value) of cells 162 to be assigned to the insert state (to be put into the insert state) among the cells 262 included in the arm unit 26, and the signed number of inserts Ncells indicating whether the insert state is a positive voltage insert state or a negative voltage insert state (polarity, sign). Like the insert number calculation unit 52, the insert number calculation unit 52a performs one-pulse control and multi-pulse control by calculating the insert number Ncells. The insert number calculation unit 52a outputs the calculated insert number Ncells to the cell selection control unit 56a. The insert number calculation unit 52a is an example of a "state number calculation unit" in the claims.

The sort list calculation unit 54a performs the same processing as the sort list calculation unit 54 of the first embodiment. The sort list calculation unit 54a calculates (generates) a sort list representing the magnitude relationship of the capacitor voltage Vc of each cell 262 included in the power converter 20 for each arm unit 26. The sort list calculation unit 54a also generates a sort list for each predetermined (constant) calculation period TS2 (TS2>TS1) that is longer than the acquisition period TS1. The method of generating a sort list in the sort list calculation unit 54a is also the same as that of the sort list calculation unit 54. The sort list calculation unit 54a outputs the generated sort list to the cell selection control unit 56a. The sort list calculation unit 54a is an example of a "list calculation unit" in the claims.

The cell selection control unit 56a performs the same processing as the cell selection control unit 56 of the first embodiment. The cell selection control unit 56a refers to the sort list and selects a cell 262 for which the current cell control state CL* is to be changed at least each time the insert number Ncells output by the insert number calculation unit 52a changes, that is, each time the cell 262 is controlled (put into the positive voltage insert state, negative voltage insert state, or bypass state).

When the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a stores power in the capacitor C of the cell 262 in the insert state (positive voltage insert state or negative voltage insert state) based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, and during the charging polarity period (charging period) in which the charge amount of the entire arm unit 26 is increased, the cell selection control unit 56a selects, from among the cells 262 currently in the bypass state, the cell 262 having a capacitor C with less stored power as the cell 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cells 262 having capacitors C with relatively low voltage values of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cell 262. The charging polarity corresponds to (1) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 6 is higher than that on the cell 262-n side, and the arm current Iarm flows in the same direction as the arm current I shown in FIG. 6, or (2) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 6 is lower than that on the cell 262-n side, and the arm current Iarm flows in the opposite direction to the arm current I shown in FIG. 6. On the other hand, when the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a, in a period (discharge period) in which the power stored in the capacitor C of the cell 262 in the insert state (positive voltage insert state or negative voltage insert state) is discharged based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm to increase the discharge amount of the entire arm unit 26, selects, from among the cells 262 currently in the bypass state, the cell 262 having the capacitor C with the largest amount of stored power as the cell 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cells 262 having the capacitor C with the relatively high voltage value of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cell 262. The discharge polarity corresponds to (1) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 6 is higher than that on the cell 262-n side, and the arm current Iarm flows in the opposite direction to the arm current I shown in FIG. 6, or (2) a case where the arm voltage command value Varm* has a polarity such that the potential on the cell 262-1 side shown in FIG. 6 is lower than that on the cell 262-n side, and the arm current Iarm flows in the direction of the arm current I shown in FIG. 6.

When the absolute value of the number of inserts Ncells decreases, the cell selection control unit 56a stores power in the capacitor C of the cell 262 in the insert state based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, and during the charging polarity period (charging period) in which the charge amount of the entire arm unit 26 is increased by storing power in the capacitor C of the cell 262 in the insert state, the cell selection control unit 56a selects the cell 262 having the capacitor C with the most stored power from among the cells 262 currently in the insert state (positive voltage insert state or negative voltage insert state) as the cell 262 to be changed to the bypass state. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 in order starting from the cells 262 having the capacitor C with the relatively high voltage value of the capacitor voltage Vc, and generates a cell control state CL* representing the selected cell 262. On the other hand, when the absolute value of the number of inserts Ncells decreases, the cell selection control unit 56a, in a period (discharge period) in which the power stored in the capacitor C of the cell 262 in the inserted state is discharged from the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm to increase the discharge amount of the entire arm unit 26, selects the cell 262 having the capacitor C with the least amount of stored power from among the cells 262 currently in the inserted state (positive voltage insert state or negative voltage insert state) as the cell 262 to be changed to the bypass state. In this case, the cell selection control unit 56a refers to the sort list and selects the cells 262 having the capacitor C with the relatively low voltage value of the capacitor voltage Vc in order, and generates a cell control state CL* representing the selected cell 262.

As a result, the cells 262 including capacitors C whose capacitor voltage Vc has a relatively high voltage value are preferentially charged and discharged for a short time, resulting in equalization of the capacitor voltage Vc in each of the cells 262 included in the arm unit 26. On the other hand, the cells 262 including capacitors C whose capacitor voltage Vc has a relatively low voltage value are preferentially charged and discharged for a long time, resulting in equalization of the capacitor voltage Vc in each of the cells 262 included in the arm unit 26.

The cell selection control unit 56a, like the cell selection control unit 56 of the first embodiment, also performs balance control to reduce the difference in the charge amount of the capacitor C in each cell 262 provided in the arm unit 26 (balancing so that the charge amount is relatively uniform). In the balance control in the cell selection control unit 56a, like the cell selection control unit 56, the voltage value of the capacitor voltage Vc of the cell 262 belonging to the same arm unit 26 is acquired for each acquisition period TS1, that is, in a period shorter than the calculation period TS2 in which the sort list calculation unit 54 generates the sort list, and each acquired voltage value of the capacitor voltage Vc is compared with the threshold value Vc-max and the threshold value Vc-min. Then, like the cell selection control unit 56, the cell selection control unit 56a also controls the cell 262 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min to a bypass state based on the result of the comparison, and selects the same number of other cells 162 from among the cells 162 in the bypass state instead and changes them to the insert state (positive voltage insert state or negative voltage insert state). In this case, the cell selection control unit 56a generates a cell control state CL* that represents the cell 262 to be placed in the bypass state and the cell 262 to be placed in the insert state (positive voltage insert state or negative voltage insert state).

The cell selection control unit 56a outputs the cell control state CL* corresponding to each cell 262 to the gate signal generation unit 58a. The cell selection control unit 56a is an example of a "unit converter selection unit" in the claims. The acquisition period TS1 is an example of a "first time interval" in the claims, and the calculation period TS2 is an example of a "second time interval" in the claims. The threshold value Vc-max is an example of a "first threshold value" in the claims, and the threshold value Vc-min is an example of a "second threshold value" in the claims.

The gate signal generating unit 58a performs the same process as the gate signal generating unit 58 of the first embodiment. The gate signal generating unit 58a generates control signals (gate signals) to be output to all the cells 262 of each arm unit 26 according to the respective cell control states CL* output by the cell selection control unit 56a. More specifically, the gate signal generating unit 58a generates a combination of gate signals, including a gate signal gta corresponding to the switching element Q1 of each cell 262, a gate signal gtb corresponding to the switching element Q2, a gate signal gtc corresponding to the switching element Q3, and a gate signal gtd corresponding to the switching element Q4, in order to realize the cell control state CL*. At this time, the gate signal generating unit 58a also provides a short dead time to prevent both ends of the capacitor C of the cell 262 from being short-circuited. The gate signal generating unit 58a outputs each generated gate signal to the corresponding cell 262 (more specifically, the switching element Q of the cell 262).

In the power conversion device 2, for example, the cell selection control unit 56a may be configured to output the cell control state CL* to each cell 262, and generate a gate signal in each cell 262 according to the cell control state CL*. In this case, each cell 262 is configured to include a component having a function equivalent to that of the gate signal generation unit 58a.

With this configuration, the converter control unit 50a controls the cells 262 in each arm unit 26 of the power converter 20 to cause the power converter 20 to adjust the reactive power (which may be active power) of the AC system.

[Third Operation of Power Conversion Apparatus]
Next, an example of the operation of the power conversion device 2, that is, the control of the cell 262 in the converter control unit 50a will be described. In the following description, the control over the arm unit 26-RS included in the leg 22-RS will be described as a representative of each of the legs 22-RS, 22-ST, and 22-TR included in the power converter 20. In the following description, for ease of explanation, the operation of each of the components included in the converter control unit 50a will be described as being performed by the converter control unit 50a itself.

Figure 8 is a timing chart illustrating an example of the operation timing of the third operation in the power conversion device 2. The example of the operation of the power conversion device 2 shown in Figure 8 is an example of the operation when the arm unit 26-RS (hereinafter simply referred to as "arm unit 26") has three cells 262 (n = 3). Figure 8 shows an example of balance control of the converter control unit 50a when the capacitor voltage Vc-2 of the cell 262-2 of the arm unit 26 exceeds the threshold value Vc-min (when it falls below the threshold value Vc-min). Figure 8 shows the temporal changes in the arm voltage command value Varm*, the arm current Iarm, and the arm voltage Varm generated by the arm unit 26 based on the arm voltage command value Varm* on the same time axis, similar to the respective operations in the power conversion device 1 of the first embodiment. In FIG. 8, instead of the gate signal gtp shown in each operation of the power conversion device 1, the time-dependent changes in the cell control states CL*-1 to CL*-3 of the cells 262-1 to 262-3 changed by the converter control unit 50a are shown on the same time axis. FIG. 8 also shows a schematic change in the capacitor voltage Vc (Vc-2) of the cell 262-2, which is balanced by the converter control unit 50a, on the same time axis. In FIG. 8, as in each operation of the power conversion device 1, dead time is omitted for ease of explanation. Furthermore, FIG. 8 shows an example of a sort list calculated (generated) by the converter control unit 50a (more specifically, the sort list calculation unit 54a). In the third operation shown in FIG. 8, as in the first operation of the power conversion device 1 of the first embodiment shown in FIG. 4, the sort list is generated (updated) for each period of the arm voltage command value Varm*. FIG. 8 also shows an example of an acquisition period TS1 during which the voltage value of the capacitor voltage Vc-2 is acquired, and an example of a calculation period TS2 during which a sort list is created.

In the power converter 20, the arm voltage command value Varm* includes the frequency of the AC system. The converter control unit 50a (more specifically, the insert number calculation unit 52a) calculates (calculates) the insert number Ncells, which is expressed as a stepped pseudo-sine wave, based on the arm voltage command value Varm*. In FIG. 8, the insert number Ncells is an integer value with a minimum value of "-n (here, "-3")" and a maximum value of "n (here, "3")". The insert number Ncells represents the number of cells 262 to be put into a positive voltage insert state when it is positive (i.e., "0" to "3"), and represents the number of cells 262 to be put into a negative voltage insert state when it is negative (i.e., "-1" to "-3"). The insert number Ncells is calculated by, for example, approximating the value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 262 belonging to the arm unit 26 to an integer. In other words, the operation timing of the power conversion device 2 shown in FIG. 8 is the operation timing when the converter control unit 50a performs one-pulse control, similar to the first operation of the power conversion device 1 of the first embodiment. Therefore, the number of inserts Ncells represents the equivalent of the arm voltage Varm shown in FIG. 8, similar to the first operation of the power conversion device 1.

The converter control unit 50a (more specifically, the cell selection control unit 56a) generates a cell control state CL* for each cell 262 in the insert state (positive voltage insert state or negative voltage insert state) belonging to the arm unit 26 so that the number (integer value) of cells 262 to be put into the insert state (positive voltage insert state or negative voltage insert state) represented by the insert number Ncells matches the number of cells 262 to be put into the insert state (positive voltage insert state or negative voltage insert state) represented by the insert number Ncells each time the insert number Ncells changes. When the arm voltage command value Varm* is positive polarity (Varm*>0), the insert number Ncells is a value equal to or greater than "0", so the converter control unit 50a generates a cell control state CL* that puts each cell 262 into the positive voltage insert state or bypass state. On the other hand, when the arm voltage command value Varm* is negative (Varm*<0), the number of inserts Ncells is a value of "0" or less, so the converter control unit 50a generates a cell control state CL* that puts each cell 262 into a negative voltage insert state or bypass state. Each cell control state CL* represents a positive voltage insert state when it is "1," a bypass state when it is "0," and a negative voltage insert state when it is "-1."

The converter control unit 50a (more specifically, the gate signal generating unit 58a) generates control signals (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) to be output to all cells 262 in each arm unit 26 according to the cell control state CL* generated by the cell selection control unit 56a. Then, each arm unit 26 outputs an arm voltage Varm by putting each cell 262 into a positive voltage insert state, a bypass state, or a negative voltage insert state by the gate signal output by the gate signal generating unit 58a. When the capacitor voltages Vc of the cells 262 are uniformly controlled, the arm voltage Varm is approximately a voltage value obtained by multiplying the number (integer value) of cells 262 to be put into the insert state (positive voltage insert state or negative voltage insert state) represented by the insert number Ncells by the capacitor voltage Vc.

The arm current Iarm includes the frequency of the AC system. In the arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is positive (Iarm>0), the capacitor C of the cell 262 in the positive voltage insert state is charged, and the capacitor voltage Vc rises during this charging period. In the arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is negative (Iarm<0), the capacitor C of the cell 262 in the negative voltage insert state is charged, and the capacitor voltage Vc rises during this charging period. In the arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), the capacitor C of the cell 262 in the positive voltage insert state is discharged, and the capacitor voltage Vc falls during this discharging period. In the arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is positive (Iarm>0), the capacitor C of the cell 262 in the negative voltage insertion state is discharged, and the capacitor voltage Vc drops during this discharge period. Thus, in the arm unit 26, the charging period occurs when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are equal, and the discharging period occurs when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are different. In the arm unit 26, regardless of the polarity of the arm voltage command value Varm* or the polarity of the arm current Iarm, the capacitor C of the cell 262 in the bypass state is neither charged nor discharged, and the current capacitor voltage Vc is maintained.

At time t0 shown in FIG. 8, the number of inserts Ncells is "0". The polarity of the arm current Iarm at this time is positive. The converter control unit 50a may arbitrarily determine whether to determine the polarity as charge polarity or discharge polarity when the number of inserts Ncells or the arm current Iarm is "0". In any case, the converter control unit 50a generates a cell control state CL* that indicates that all cells 262 are in a bypass state so as to match the number of inserts Ncells. Here, cell 262-2 is in a bypass state because the cell control state CL*-2 is "0". Therefore, the capacitor C-2 provided in cell 262-2 is neither charged nor discharged, and maintains the current capacitor voltage Vc-2.

After that, at time t1, when the number of inserts Ncells changes to "1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive polarity and the polarity of the arm current Iarm is positive polarity (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a small amount of stored power as the cell 262 to be put into the positive voltage insert state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t1, the converter control unit 50a sets the cell control state CL*-3 to "1" to put the selected cell 262-3 into the positive voltage insert state. At this time, the cell 262-2 is still in the bypass state, so the cell 262-2 continues to maintain the current capacitor voltage Vc-2.

After that, from time t2 to time t3, each time the number of inserts Ncells changes sequentially to "2" and "3" (the absolute value increases), the converter control unit 50a, like at time t1, sequentially selects the cells 262 with the second and third lowest capacitor voltages Vc in the sort list (i.e., Vc-2 and Vc-1), and sets the cell control state CL* to "1" to place the selected cells 262 in a positive voltage insert state. More specifically, the converter control unit 50a selects cell 262-2 at time t2 and sets the cell control state CL*-2 to "1", and selects cell 262-1 at time t3 and sets the cell control state CL*-1 to "1". By the converter control unit 50a setting the cell control state CL*-2 to "1" at time t2, the capacitor C-2 of cell 262-2 is charged, and the capacitor voltage Vc-2 rises (increases) as it is charged.

After that, at time t4, when the polarity of the arm current Iarm becomes negative (discharge polarity), cell 262-2, which is in the positive voltage insertion state, begins to discharge the power stored in capacitor C-2. As a result, capacitor voltage Vc-2 drops (decreases) as it is discharged.

After that, at time t5, when the number of inserts Ncells changes to "2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive polarity and the polarity of the arm current Iarm is negative polarity (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with a small amount of stored power as the cell 262 to be placed in the bypass state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t5, the converter control unit 50a sets the cell control state CL*-3 to "0" to place the selected cell 262-3 in the bypass state. At this time, the cell 262-2 is still in the positive voltage insert state, so it continues to discharge the power stored in the capacitor C-2, and the capacitor voltage Vc-2 decreases.

After that, at time t6, when the capacitor voltage Vc-2 of cell 262-2 exceeds the threshold value Vc-min, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 262 to be placed in the positive voltage insert state instead of the cell 262-2 that has been placed in the bypass state, in order to place the cell 262-2 in the bypass state. Here, the only cell 262 in the positive voltage insert state is cell 262-3. Therefore, the converter control unit 50a selects cell 262-3, which has the lowest capacitor voltage Vc in the sort list (i.e., Vc-3) but is currently in the bypass state. Then, at time t6, the converter control unit 50a sets the cell control state CL*-2 to "0" in order to place the cell 262-2 in the bypass state. As a result, discharging from cell 262-2 is stopped, and discharging from capacitor C-2 included in cell 262-2 continues, so that the capacitor voltage Vc-2 does not fall significantly below the threshold value Vc-min, as shown by the dashed line in FIG. 8. In other words, the capacitor voltage Vc-2 is maintained at a voltage value close to the threshold value Vc-min, as shown by the solid line in FIG. 8. Furthermore, at time t6, the converter control unit 50a sets the cell control state CL*-3 to "1" to put the selected cell 262-3 into a positive voltage insertion state. As a result, the capacitor voltage of cell 262-3 is output as a substitute, and the arm voltage Varm does not deviate (contains an error) from the ideal stepped waveform according to the arm voltage command value Varm*.

After that, at time t7, when the number of inserts Ncells changes to "1" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive polarity and the polarity of the arm current Iarm is negative polarity (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with a small amount of stored power as the cell 262 to be placed in the bypass state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t7, the converter control unit 50a sets the cell control state CL*-3 to "0" to place the selected cell 262-3 in the bypass state. At this time, the cell 262-2 is still in the bypass state, so the capacitor voltage Vc-2 of the cell 262-2 continues to be maintained at a voltage value close to the current threshold value Vc-min.

After that, at time t8, when the number of inserts Ncells changes to "0" (its absolute value decreases), the converter control unit 50a selects the cell 262 with the lowest capacitor voltage Vc in the sort list, as at time t5, and sets the cell control state CL* to "0" to put the selected cell 262 into the bypass state. Here, the only cell 262 in the positive voltage insert state is cell 262-1, so the converter control unit 50a selects cell 262-1, which has the highest capacitor voltage Vc in the sort list (i.e., Vc-1) but is currently in the positive voltage insert state. At this time, cell 262-2 is also in the bypass state, so the capacitor voltage Vc-2 of cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, at time t9, when the number of inserts Ncells changes to "-1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative polarity and the polarity of the arm current Iarm is negative polarity (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a small amount of stored power as the cell 262 to be placed in the negative voltage insert state. Here, the converter control unit 50a selects the cell 262-3 with the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t9, the converter control unit 50a sets the cell control state CL*-3 to "-1" in order to place the selected cell 262-3 in the negative voltage insert state. At this time, the cell 262-2 is still in the bypass state, so the capacitor voltage Vc-2 of the cell 262-2 continues to be maintained at a voltage value close to the current threshold value Vc-min.

After that, from time t10 to time t11, each time the number of inserts Ncells changes (the absolute value increases) to "-2" and "-3", the converter control unit 50a sequentially selects the cells 262 with the second and third lowest capacitor voltages Vc in the sort list (i.e., Vc-2 and Vc-1) in the same way as at time t9, and sets the cell control state CL* to "-1" to put the selected cells 262 into a negative voltage insert state. More specifically, the converter control unit 50a selects the cell 262-2 at time t10 and sets the cell control state CL*-2 to "-1", and selects the cell 262-1 at time t11 and sets the cell control state CL*-1 to "-1". By the converter control unit 50a setting the cell control state CL*-2 to "-1" at time t10, the capacitor C-2 of the cell 262-2 is charged, and the capacitor voltage Vc-2 rises (increases) as it is charged.

Then, at time t12, the sort list is updated. Also, when the polarity of the arm current Iarm becomes positive (discharge polarity), cell 262-2, which is in the negative voltage insertion state, begins to discharge the power stored in capacitor C-2. As a result, capacitor voltage Vc-2 drops (decreases) as it is discharged.

After that, at time t13, when the number of inserts Ncells changes to "-2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative polarity and the polarity of the arm current Iarm is positive polarity (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the negative voltage insert state and has a capacitor C with a small amount of stored power as the cell 262 to be placed in the bypass state. Here, the converter control unit 50a selects the cell 262-1 with the lowest capacitor voltage Vc (i.e., Vc-1) in the sort list. Then, at time t13, the converter control unit 50a sets the cell control state CL*-1 to "0" in order to place the selected cell 262-1 in the bypass state. At this time, since the cell 262-2 is still in the negative voltage insert state, the capacitor C-2 continues to discharge and the capacitor voltage Vc-2 decreases.

After that, from time t14 to time t15, each time the number of inserts Ncells changes sequentially from "-1" to "0" (the absolute value decreases), the converter control unit 50a, like at time t13, sequentially selects the cells 262 with the second and third lowest capacitor voltages Vc in the sort list (i.e., Vc-2 and Vc-3) and sets the cell control state CL* to "0" to put the selected cells 262 into a bypass state. More specifically, the converter control unit 50a selects cell 262-2 at time t14 and sets the cell control state CL*-2 to "0", and selects cell 262-3 at time t15 and sets the cell control state CL*-3 to "0". By the converter control unit 50a setting the cell control state CL*-2 to "0" at time t14, the discharge from the capacitor C-2 of cell 262-2 is stopped, and the capacitor voltage Vc-2 is maintained at the current voltage value.

In this way, the converter control unit 50a determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm each time the number of inserts Ncells changes (the absolute value increases or decreases), and refers to the sort list to select a cell 262 whose control state (cell control state CL*) is to be a positive voltage insert state, a bypass state, or a negative voltage insert state, and controls the control state of the selected cell 262, that is, the gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd. At this time, if the capacitor voltage Vc in any of the cells 262 exceeds the threshold value Vc-max (exceeds the threshold value Vc-max) or exceeds the threshold value Vc-min (falls below the threshold value Vc-min), the converter control unit 50a performs balance control. That is, the converter control unit 50a performs balance control when the capacitor voltage Vc exceeds the threshold value Vc-max or Vc-min, regardless of the timing of calculation (generation) of the sort list or the timing of switching control. In the balance control, the converter control unit 50a puts the cell 262 whose capacitor voltage Vc exceeds the threshold value Vc-max or Vc-min into a bypass state. As a result, the cell 262 put into the bypass state stops charging the capacitor C or discharging from the capacitor C. Then, the converter control unit 50a refers to the sort list and selects a cell 262 to replace the cell 262 put into the bypass state from among the cells 262 currently in the bypass state, and puts the selected cell into the insert state (positive voltage insert state or negative voltage insert state). As a result, in the power converter 10, the capacitor C included in the cell 262 is not charged or discharged more than it is now (without overcharging or overdischarging), and the charge amount of the capacitor C can be balanced to be relatively uniform. In the third operation of the power conversion device 2 shown in FIG. 8, the case where the capacitor voltage Vc-2 of the cell 262-2 exceeds the threshold value Vc-min at time t6 is shown, but the balance control in the converter control unit 50a is similar for the other cells 262. In the third operation of the power conversion device 2 shown in FIG. 8, the case where the cell 262-3 is selected as a replacement for the cell 262-2 at time t6 is shown, but the selection as a replacement is similar for the other cells 262. In the third operation of the power conversion device 2 shown in FIG. 8, the balance control in the converter control unit 50a shows the balance control when the capacitor voltage Vc-2 of the cell 262-2 exceeds the threshold value Vc-min, but the balance control when the capacitor voltage Vc of any of the cells 262 included in the arm unit 26 exceeds the threshold value Vc-max may be equivalent to the balance control in the first operation described above.

[Fourth Operation of Power Conversion Apparatus]
In the third operation described above, the converter control unit 50a performs one-pulse control, but the converter control unit 50a can also perform multi-pulse control. Next, an operation in which the converter control unit 50a performs multi-pulse control will be described as another operation of the power conversion device 2 (another example of balance control in the converter control unit 50a).

9 is a timing chart for explaining an example of the operation timing of the fourth operation in the power conversion device 2. The fourth operation shown in FIG. 9 is also an operation in the case where the arm unit 26 has three cells 262 (n=3), like the third operation shown in FIG. 8. In the fourth operation, the number of inserts Ncells is calculated as the number of triangular wave carrier waves in which the value of the arm voltage command value Varm* (modulation wave) exceeds the value of the triangular wave carrier, for example, by comparing the modulated wave based on the arm voltage command value Varm* with each triangular wave carrier that is the same number as the number of cells 262 belonging to the arm unit 26 (here, "3") and has a phase and level shifted from each other. In other words, the fourth operation shown in FIG. 9 is the operation timing when the converter control unit 50a performs multi-pulse control. For this reason, the operation timing of the fourth operation shown in FIG. 9 is shown by enlarging a part of the range within one period of the arm voltage command value Varm*.

The fourth operation shown in FIG. 9 is an example of a case where balance control is performed during a period in which the number of cells 262 in the positive voltage insert state represented by the insert number Ncells is "2" before changing from "2" to "1" in a discharge polarity (discharge period) in which the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), that is, during a period in which the number of cells 262 in the positive voltage insert state remains unchanged at "2". In the fourth operation shown in FIG. 9, the sort list calculation unit 54a generates a sort list with a calculation period TS2 that is shorter than that of the third operation shown in FIG. 8. However, even in the fourth operation shown in FIG. 9, the calculation period TS2 is a period (TS2>TS1) with a time interval longer than the acquisition period TS1. FIG. 9 shows an example of balance control by the converter control unit 50a when the capacitor voltage Vc-3 of the cell 262-3 in the arm unit 26 exceeds the threshold Vc-min (falls below the threshold Vc-min).

At time t0 shown in FIG. 9, the number of inserts Ncells is "2". Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 having the capacitor C with the most stored power as the cell 262 to be placed in the positive voltage insert state. More specifically, the converter control unit 50a selects cells 262-1 and 262-3, which have the two highest capacitor voltages Vc (Vc-1 and Vc-3) in the sort list. Therefore, at time t0 shown in FIG. 9, the converter control unit 50a sets each of the cell control state CL*-1 and cell control state CL*-3 to "1" in order to place the two selected cells 262 in the positive voltage insert state. Therefore, in cell 262-3, the power stored in capacitor C-3 is discharged, and the capacitor voltage Vc-3 drops (decreases) as it is discharged.

After that, when the capacitor voltage Vc-3 of cell 262-3 exceeds the threshold value Vc-min at time t1, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the bypass state and has a capacitor C with a large amount of stored power as the cell 262 to be placed in the positive voltage insert state instead of the cell 262-3 that has been placed in the bypass state, in order to place the cell 262-3 in the bypass state. Here, the only cell 262 in the bypass state is cell 262-2. Therefore, the converter control unit 50a selects cell 262-2, which is third from the highest capacitor voltage Vc in the sort list (i.e., Vc-2) but is currently in the bypass state. Then, at time t1, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to place the cell 262-3 in the bypass state. As a result, discharging from cell 262-3 is stopped, and discharging from capacitor C-3 included in cell 262-3 continues, so that the capacitor voltage Vc-3 does not fall significantly below the threshold Vc-min, as shown by the dashed line in FIG. 9 (when balance control is performed only in accordance with sort list updates). In other words, the capacitor voltage Vc-3 is maintained at a voltage value close to the threshold Vc-min, as shown by the solid line in FIG. 9. Furthermore, at time t1, the converter control unit 50a sets the cell control state CL*-2 to "1" to put the selected cell 262-2 into a positive voltage insert state. As a result, the capacitor voltage of cell 262-2 is output as a substitute, and the arm voltage Varm is maintained.

Then, at time t2, the sort list is updated. Here, the sort list is updated to include the capacitor voltage Vc-3 of cell 262-3, which has the lowest capacitor voltage Vc.

After that, at time t3, when the number of inserts Ncells changes (decreases) to "1", the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insert state and has a capacitor C with a small amount of stored power as the cell 262 to be placed in the bypass state. Here, the converter control unit 50a selects cell 262-2, which has the lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from cell 262-1 and cell 262-2 that are in the positive voltage insert state. Then, at time t3, the converter control unit 50a sets the cell control state CL*-2 to "0" to place the selected cell 262-2 in the bypass state. At this time, cell 262-3 is still in the bypass state, so the capacitor voltage Vc-3 of cell 262-3 continues to be maintained at a voltage value close to the current threshold value Vc-min.

In this way, in the fourth operation (multiple pulse control), as in the third operation (single pulse control) shown in FIG. 8, the converter control unit 50a determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (the absolute value increases or decreases), and selects a cell 262 whose control state (cell control state CL*) is to be a positive voltage insert state, a bypass state, or a negative voltage insert state by referring to the sort list, and controls the control state of the selected cell 262, that is, the gate signal gta, the gate signal gtb, the gate signal gtc, and the gate signal gtd. At this time, in the fourth operation, if the capacitor voltage Vc in any of the cells 262 exceeds the threshold value Vc-max (exceeds the threshold value Vc-max) or exceeds the threshold value Vc-min (falls below the threshold value Vc-min), the converter control unit 50a performs balance control. That is, in the fourth operation, the converter control unit 50a also performs balance control when the capacitor voltage Vc exceeds the threshold value Vc-max or Vc-min, regardless of the timing of calculation (generation) of the sort list or the timing of switching control. In the balance control in the fourth operation, the converter control unit 50a also puts the cell 262 whose capacitor voltage Vc exceeds the threshold value Vc-max or Vc-min into a bypass state. As a result, in the fourth operation, the cell 262 put into the bypass state stops charging to the capacitor C or discharging from the capacitor C. Then, in the fourth operation, the converter control unit 50a also refers to the sort list, selects a cell 262 to replace the cell 262 put into the bypass state from among the cells 262 currently in the bypass state, and puts the selected cell into the insert state (positive voltage insert state or negative voltage insert state). As a result, in the power converter 10, the capacitor C included in the cell 262 is not charged or discharged more than it is now (without being overcharged or overdischarged), and balance can be performed so that the charge amount of the capacitor C is relatively uniform. In the fourth operation of the power conversion device 2 shown in FIG. 9, the case where the capacitor voltage Vc-3 of the cell 262-3 exceeds the threshold value Vc-min at time t1 is shown, but the balance control in the converter control unit 50a is similar for the other cells 262. In the fourth operation of the power conversion device 2 shown in FIG. 9, the case where the cell 262-2 is selected as a replacement for the cell 262-3 at time t1 is shown, but the selection as a replacement is similar for the other cells 262. In the fourth operation of the power conversion device 2 shown in FIG. 9, the balance control in the converter control unit 50a shows the balance control when the capacitor voltage Vc-3 of the cell 262-3 exceeds the threshold value Vc-min, but the balance control when the capacitor voltage Vc of any of the cells 262 included in the arm unit 26 exceeds the threshold value Vc-max may be equivalent to the balance control in the fourth operation described above.

With such a configuration and operation, in the power conversion device 2, the converter control unit 50a judges whether the polarity is discharge polarity or charge polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm for each timing when the number of inserts Ncells of the cells 262 changes (increases or decreases) for each arm unit 26 provided in the power converter 20. Then, in the power conversion device 2, the converter control unit 50a refers to the sort list calculated (generated) for each arm unit 26, selects the cell 262 whose control state is to be changed to a positive voltage insert state, a bypass state, or a negative voltage insert state, and changes the control state of the selected cell 262. At this time, if the capacitor voltage Vc in any of the cells 262 exceeds the threshold value Vc-max or threshold value Vc-min, the converter control unit 50a puts the cell 262 into the bypass state, and refers to the sort list to select an alternative cell 262 from among the cells 262 currently in the bypass state and puts it into the insert state (positive voltage insert state or negative voltage insert state). As a result, even in the power conversion device 2, it is possible to prevent overcharging or overdischarging of the capacitor C of the cell 262 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min, and to balance the charge amount of the capacitor C so that it is relatively uniform. As a result, in the power conversion device 2, it is possible to reduce the risk of failure of the capacitor C or the switching element Q of the cell 262 in the power converter 20, and for example, even in the event of a system accident, it is possible to reduce the risk of a state in which the protection device of the power converter 10 operates and stops operation due to the capacitor voltage Vc reaching an overvoltage or undervoltage. As a result, even in the power conversion device 2, it is possible to realize a highly reliable power conversion device with improved performance for continuing operation when a system accident occurs.

As described above, in the power conversion device 2 of the second embodiment, similarly to the power conversion device 1 of the first embodiment, the converter control unit 50a determines whether the polarity is discharge polarity or charge polarity for each arm unit 26 of the power converter 20 based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm each time the number of inserts Ncells of the cells 262 changes (increases or decreases). Then, in the power conversion device 2 of the second embodiment, the converter control unit 50a refers to the sort list calculated (generated) for each arm unit 26, selects the cell 262 whose control state is to be changed to a positive voltage insert state, a bypass state, or a negative voltage insert state, and changes the control state of the selected cell 262. At this time, in the power conversion device 2 of the second embodiment, when the capacitor voltage Vc of any of the cells 262 exceeds the threshold value Vc-max or threshold value Vc-min, the converter control unit 50a puts the cell 262 into a bypass state, refers to the sort list, selects an alternative cell 262 from the cells 262 currently in the bypass state, and puts it into an insert state (positive voltage insert state or negative voltage insert state). As a result, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, it is possible to prevent overcharging or overdischarging of the capacitor C included in the cell 262 whose capacitor voltage Vc exceeds the threshold value Vc-max or threshold value Vc-min, and to balance the charge amount of the capacitor C so that it is relatively uniform. As a result, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, the risk of failure of the capacitor C and switching element Q of the cell 262 in the power converter 20 can be reduced, and for example, even in the event of a system accident, the risk of the capacitor voltage Vc reaching an overvoltage or undervoltage, causing the protection device of the power converter 10 to operate and stop operation, can be reduced. As a result, the power conversion device 2 of the second embodiment can also realize a highly reliable power conversion device with improved performance for continuing operation in the event of a system accident.

As described above, in the power conversion device of each embodiment, the converter control unit that changes the control state of the unit converter in the arm unit equipped with the power converter acquires the capacitor voltage of the capacitor equipped with the power converter at each predetermined (fixed) acquisition period TS1. Then, in the power conversion device of each embodiment, when the capacitor voltage of any unit converter exceeds a threshold (upper threshold Vc-max or lower threshold Vc-min), the converter control unit changes the control state of the unit converter whose capacitor voltage exceeds the threshold, regardless of the timing of controlling each unit converter, to stop charging to the capacitor or discharging from the capacitor. In other words, in the power conversion device of each embodiment, the converter control unit stops charging and discharging of the unit converter whose capacitor voltage exceeds the threshold, and excludes it from the unit converters that output the capacitor voltage in the arm unit. Then, in the power conversion device of each embodiment, as a replacement for the unit converter whose charging and discharging has been stopped because the capacitor voltage has exceeded the threshold, the control state of the same number of other unit converters from among the unit converters that did not output the capacitor voltage in the arm unit is changed to start charging and discharging. As a result, in the power conversion device of each embodiment, the charge amount of the capacitors provided in the unit converters is balanced so that it is relatively uniform, and the risk of failure of the capacitors and switching elements provided in the unit converters can be reduced. As a result, in the power conversion device of each embodiment, when a system accident or the like occurs in an AC system to which the power conversion device is connected, for example, the risk of the capacitor voltage reaching an overvoltage or undervoltage, causing the protection device of the power converter to operate and stop operation, can be reduced. As a result, in the power conversion device of each embodiment, a highly reliable power conversion device can be realized with improved performance for continuing operation when a system accident occurs.

In the power conversion device of each embodiment described above, the insert number calculation unit of the converter control unit calculates (calculates) the insert number Ncells representing the number of cells to be put into the insert state (integer value), and the cell selection control unit of the converter control unit selects the cell to be changed to the insert state or bypass state in response to a change in the insert number Ncells. However, the trigger for the cell selection control unit to select a cell is not limited to a change in the insert number Ncells. For example, the cell selection control unit may select a cell to be changed to the insert state or bypass state in response to a change in the number of cells to be put into the bypass state (integer value) instead of the insert number Ncells representing the number of cells to be put into the insert state. In this case, the operation and processing of the power conversion device and the converter control unit may be equivalent to the operation and processing of the power conversion device and the converter control unit of each embodiment described above.

According to at least one of the embodiments described above, a power converter (10) includes an arm unit (16) having an energy storage element (C) for storing power, and a plurality of unit converters (162) having a plurality of switching elements (Q, D) capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element, and the arm unit (16) is connected in series, and the power converter (10) is configured to operate by switching between at least one of a first control state (insertion state) in which the terminal voltage (Vc) of the energy storage element is output between a first end (TP) and a second end (TN) of the unit converter, and a second control state (bypass state) in which the first end and the second end of the unit converter are short-circuited. and a converter control unit (50) for controlling a power conversion operation in the arm unit, the converter control unit comprising: a state number calculation unit (52) for calculating a state number (insertion number Ncells) representing the number of unit converters belonging to the arm unit, the control state of which is switched, according to an arm voltage command value (Varm*) which is a target value of an arm voltage (Varm) to be output from the arm unit; a list calculation unit (54) for generating list information (sort list) representing a magnitude relationship of the inter-terminal voltages, for each predetermined second time interval (TS2) longer than the first time interval, based on the inter-terminal voltages of the energy storage element detected in a predetermined first time interval (TS1); and a unit converter selection unit (56) that selects a unit converter for changing the current control state based on the polarity, the number of states, the list information, and the terminal-to-terminal voltage of the energy storage element, and the unit converter selection unit changes the first unit converter to the second control state when the terminal-to-terminal voltage of the energy storage element of the first unit converter, which is the unit converter in the first control state and is detected at a first time interval, exceeds a first threshold value (Vc-max) higher than a rated voltage, in a charging period in which the polarity of the arm current becomes a charging polarity for storing power in the energy storage element of the unit converter in the first control state, and changes other unit converters, of the unit converters in the second control state, which are the same number as the first unit converter, to the first control state. In the case of a discharge period in which the polarity of the arm current becomes a discharge polarity that discharges power from the energy storage element of the unit converter in the first control state, when the terminal-to-terminal voltage of the energy storage element of the second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold (Vc-min) lower than the rated voltage, the second unit converter is changed to the second control state, and the same number of other unit converters as the second unit converter are selected from among the unit converters in the second control state as unit converters to be changed to the first control state, thereby suppressing an increase in the fluctuation range of the terminal-to-terminal voltage of the energy storage element of the unit converter, and realizing a highly reliable power conversion device.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are within the scope of the invention and its equivalents as set forth in the claims, as well as the scope and gist of the invention.

1, 2... Power conversion device, 10... Power converter, 12, 12-R, 12-S, 12-T... Leg, 14, 14-P-R, 14-N-R, 14-P-S, 14-N-S, 14-P-T, 14-N-T, 14-RS, 14-ST, 14-TR... Reactor, 16, 16-P-R, 16-N-R, 16-P-S, 16-N-S, 16-P-T, 16-N-T... Arm unit, 162, 162-1, 162- n. 2-n-PT, 162-1-NT, 162-n-NT... Cell, 20... Power converter, 22, 22-RS, 22-ST, 22-TR... Leg, 26, 26-RS, 26-ST, 26-TR... A unit, 262, 262-1, 262-n, 262-1-RS, 262-n-RS, 262-1-ST, 262-n-ST, 262-1-TR, 262-n-TR...cell, 50, 50a...converter control unit, 52, 52a...insert number calculation unit, 54, 54a...sort list calculation unit, 56, 56a...cell selection control unit, 58, 58a...gate signal generation unit, Q, Q1, Q2, Q3, Q4... Switching element, D, D1, D2, D3, D4...Diode, C...Capacitor, TR...Transformer, R, S, T...AC terminal, P...Positive side terminal, N...Negative side terminal, CA, CA-R, CA- S, CA-T, CB, CB-R, CB-S, CB-T...AC terminal, CP, CP-R, CP-S, CP-T, CN, CN-R, CN-S, CN-T...DC terminal, TP...Positive terminal, TN...Negative terminal

Claims (18)

a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
a converter control unit that controls a power conversion operation of the power converter by switching between at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited;
Equipped with
The converter control unit includes:
a state number calculation unit that calculates a state number representing the number of the unit converters that belong to the arm unit and are assigned to any one of the control states according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
a list calculation unit that generates list information representing a magnitude relationship between terminal voltages of the energy storage element detected at a predetermined first time interval, for each predetermined second time interval that is longer than the first time interval;
a unit converter selection unit that selects the unit converter for changing a current control state based on a polarity of an arm current flowing through the arm unit, the number of states, the list information, and a terminal-to-terminal voltage of the energy storage element;
Equipped with
The unit converter selection unit is
In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state,
when the inter-terminal voltage of the energy storage element of a first unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a first threshold value higher than a rated voltage, the first unit converter is changed to the second control state, and at the same time, based on the list information generated at each second time interval, other unit converters, the same number as the first unit converter, are selected from the unit converters in the second control state as the unit converters to be changed to the first control state;
In a discharge period in which the polarity of the arm current becomes a discharge polarity for discharging power from the energy storage element of the unit converter in the first control state,
when the terminal-to-terminal voltage of the energy storage element of a second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold value lower than a rated voltage, the second unit converter is changed to the second control state, and at the same time, based on the list information generated at each second time interval, other unit converters, the same number as the second unit converter, are selected from among the unit converters in the second control state as the unit converters to be changed to the first control state.
Power conversion equipment. The unit converter selection unit is
When selecting the converter unit to be changed to the first control state from the converter unit in the second control state,
During the charging period, the unit converter having the energy storage element included in the list information with a relatively low inter-terminal voltage is selected preferentially;
During the discharge period, the unit converter having the energy storage element included in the list information and having a relatively high inter-terminal voltage of the energy storage element is selected preferentially;
When selecting the converter unit to be changed to the second control state from the converter unit in the first control state,
During the charging period, the unit converter having the energy storage element included in the list information and having a relatively high inter-terminal voltage of the energy storage element is selected preferentially;
during the discharge period, preferentially selecting the unit converter having the energy storage element whose inter-terminal voltage included in the list information is relatively low;
The power conversion device according to claim 1 . The unit converter selection unit is
When the number of states is changed, selection of the unit converter for changing the control state is started;
when an absolute value of the number of states to be assigned to the first control state increases, selecting the unit converter to be changed to the first control state from among the unit converters in the second control state; when an absolute value of the number of states to be assigned to the first control state decreases, selecting the unit converter to be changed to the second control state from among the unit converters in the first control state.
The power conversion device according to claim 1 or 2. the state number calculation unit approximates a value obtained by dividing the arm voltage command value by an average value or a rated value of the inter-terminal voltage of the energy storage element of the unit converter belonging to the arm unit to an integer, and calculates the resultant value approximated to the integer as the state number to be assigned to the first control state;
The power conversion device according to any one of claims 1 to 3. The state number calculation unit
a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers, the number of which is the same as the number of the unit converters belonging to the arm unit and which are phase-shifted from each other, and the number of the triangular wave carriers, in which the value of the modulation wave is greater than the value of the triangular wave carrier, is calculated as the number of states to be assigned to the first control state;
The power conversion device according to any one of claims 1 to 3. The state number calculation unit
a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers whose levels are shifted from each other and whose number is the same as the number of the unit converters belonging to the arm unit; and the number of the triangular wave carriers whose value of the modulation wave is greater than the value of the triangular wave carrier is calculated as the number of states to be assigned to the first control state;
The power conversion device according to any one of claims 1 to 3. the unit converter is a half-bridge circuit in which a series circuit in which two switching elements, a first switching element and a second switching element, are connected in series and the energy storage element are connected in parallel, a connection point between the first switching element and the second switching element is the first end, and a connection point between the second switching element and the energy storage element is the second end,
The converter control unit includes:
putting the first switching element into a conductive state and the second switching element into a non-conductive state to put the unit converter into the first control state;
putting the first switching element into a non-conductive state and the second switching element into a conductive state, thereby putting the unit converter into the second control state;
The power conversion device according to any one of claims 1 to 6. the unit converter is a full bridge circuit in which a first series circuit in which two switching elements, a first switching element and a second switching element, are connected in series, a second series circuit in which two switching elements, a third switching element and a fourth switching element, are connected in series, and the energy storage element are connected in parallel, a connection point between the first switching element and the second switching element being the first end, and a connection point between the third switching element and the fourth switching element being the second end;
The converter control unit includes:
by setting the first switching element in a conductive state, the second switching element in a non-conductive state, the third switching element in a non-conductive state, and the fourth switching element in a conductive state, the unit converter is set in a first control state, which is the first control state in which a positive voltage is output;
by setting the first switching element to a non-conductive state, the second switching element to a conductive state, the third switching element to a conductive state, and the fourth switching element to a non-conductive state, the unit converter is set to a second first control state, which is the first control state in which a negative voltage is output;
the unit converter is put into the second control state by setting the first switching element in a conductive state, the second switching element in a non-conductive state, the third switching element in a conductive state, and the fourth switching element in a non-conductive state, or by setting the first switching element in a non-conductive state, the second switching element in a conductive state, the third switching element in a non-conductive state, and the fourth switching element in a conductive state;
determining the first control state or the second control state according to a polarity of the valve branch voltage represented by the valve branch voltage command value;
The power conversion device according to any one of claims 1 to 6. the power converter is a double star-connected modular multilevel converter having a phase unit for each AC phase, in which two arm units, a first arm unit and a second arm unit, are connected in series, a connection point between the first arm unit and the second arm unit belonging to each of the phase units is an AC terminal connected to the corresponding AC phase, an inductance element is connected to one end of each of the first arm unit and the second arm unit or to an arbitrary position between each of the unit converters connected in series, and a terminal on the opposite side to the AC terminal in each of the first arm unit and the second arm unit is a DC terminal;
The converter control unit includes:
Distributing an AC voltage command value and a DC voltage command value to the first arm unit and the second arm unit belonging to each of the phase units to obtain the arm voltage command values,
changing the control state for each of the arm units in accordance with the distributed arm voltage command value;
The power conversion device according to any one of claims 1 to 8. the power converter is a single delta-connection modular multilevel converter in which the arm units are connected between AC terminals of the AC phases, and inductance elements are connected to one end of each of the arm units or at any position between the unit converters connected in series,
The converter control unit includes:
Distributing an AC voltage command value to each of the arm units between the AC terminals to obtain each of the arm voltage command values;
changing the control state for each of the arm units in accordance with the distributed arm voltage command value;
The power conversion device according to any one of claims 1 to 8. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
A control method for a power conversion device including: a converter control unit that controls a power conversion operation of the power converter by switching to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited,
The computer of the converter control unit
calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
generating list information representing a magnitude relationship between the terminal voltages of the energy storage element detected at a predetermined first time interval for each second time interval that is longer than the first time interval;
When selecting the unit converter for changing the current control state based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the terminal voltage of the energy storage element,
In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state,
when the inter-terminal voltage of the energy storage element of a first unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a first threshold value higher than a rated voltage, the first unit converter is changed to the second control state, and at the same time, based on the list information generated at each second time interval, other unit converters, the same number as the first unit converter, are selected from the unit converters in the second control state as the unit converters to be changed to the first control state;
In a discharge period in which the polarity of the arm current becomes a discharge polarity for discharging power from the energy storage element of the unit converter in the first control state,
when the terminal-to-terminal voltage of the energy storage element of a second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold value lower than a rated voltage, the second unit converter is changed to the second control state, and at the same time, based on the list information generated at each second time interval, other unit converters, the same number as the second unit converter, are selected from among the unit converters in the second control state as the unit converters to be changed to the first control state.
A method for controlling a power conversion device. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
A program for controlling a power conversion device including: a converter control unit that controls a power conversion operation in the power converter by switching to either a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, or a second control state in which the first end and the second end of the unit converter are short-circuited,
The computer of the converter control unit
Calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
generating list information representing a magnitude relationship between the terminal voltages of the energy storage element detected at a predetermined first time interval for each second time interval that is longer than the first time interval;
When the unit converter for changing the current control state is selected based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the terminal voltage of the energy storage element,
In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state,
when the inter-terminal voltage of the energy storage element of a first unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a first threshold value higher than a rated voltage, the first unit converter is changed to the second control state, and at the same time, other unit converters, the same number as the first unit converter, are selected from the unit converters in the second control state based on the list information generated for each second time interval , as unit converters to be changed to the first control state;
In a discharge period in which the polarity of the arm current becomes a discharge polarity for discharging power from the energy storage element of the unit converter in the first control state,
when the terminal-to-terminal voltage of the energy storage element of the second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold value lower than a rated voltage, the second unit converter is changed to the second control state, and at the same time, based on the list information generated at each second time interval, other unit converters, the same number as the second unit converter, are selected from the unit converters in the second control state as the unit converters to be changed to the first control state.
program. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
a converter control unit that controls a power conversion operation of the power converter by switching between at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited;
Equipped with
The converter control unit includes:
a state number calculation unit that calculates a state number representing the number of converter units belonging to the arm unit to be assigned to any one of the control states according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit, compares a modulated wave based on the arm voltage command value with each of triangular wave carriers that are the same in number as the number of converter units belonging to the arm unit and are phase-shifted from each other, and calculates, as the state number to be assigned to the first control state, the number of triangular wave carriers for which the value of the modulated wave is greater than the value of the triangular wave carrier;
Equipped with
Power conversion equipment. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
a converter control unit that controls a power conversion operation of the power converter by switching between at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited;
Equipped with
The converter control unit includes:
a state number calculation unit that calculates a state number representing the number of converter units belonging to the arm unit to be assigned to any one of the control states according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit, compares a modulated wave based on the arm voltage command value with each of triangular wave carriers whose levels are shifted from each other and whose number is the same as the number of converter units belonging to the arm unit, and calculates, as the state number to be assigned to the first control state, the number of triangular wave carriers whose value of the modulated wave is greater than the value of the triangular wave carrier;
Equipped with
Power conversion equipment. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
A control method for a power conversion device including: a converter control unit that controls a power conversion operation of the power converter by switching to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited,
The computer of the converter control unit
calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers, the number of which is the same as the number of the unit converters belonging to the arm unit and which are phase-shifted from each other, and the number of the triangular wave carriers, in which the value of the modulation wave is greater than the value of the triangular wave carrier, is calculated as the number of states to be assigned to the first control state;
A method for controlling a power conversion device. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
A control method for a power conversion device including: a converter control unit that controls a power conversion operation of the power converter by switching to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited,
The computer of the converter control unit
calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers whose levels are shifted from each other and whose number is the same as the number of the unit converters belonging to the arm unit; and the number of the triangular wave carriers whose value of the modulation wave is greater than the value of the triangular wave carrier is calculated as the number of states to be assigned to the first control state;
A method for controlling a power conversion device. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
A program for controlling a power conversion device including: a converter control unit that controls a power conversion operation in the power converter by switching to either a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, or a second control state in which the first end and the second end of the unit converter are short-circuited,
The computer of the converter control unit
Calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers, the number of which is the same as the number of the converter units belonging to the arm unit and which are phase-shifted from each other, and the number of the triangular wave carriers, the value of which is greater than the value of the triangular wave carrier, is calculated as the number of states to be assigned to the first control state;
Program. a power converter including at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of the power stored in the energy storage element;
A program for controlling a power conversion device including: a converter control unit that controls a power conversion operation in the power converter by switching to either a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, or a second control state in which the first end and the second end of the unit converter are short-circuited,
The computer of the converter control unit
Calculating a state number representing the number of the unit converters to be assigned to any one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit;
a modulation wave based on the arm voltage command value is compared with each of the triangular wave carriers whose levels are shifted from each other and whose number is the same as the number of the unit converters belonging to the arm unit; and the number of the triangular wave carriers whose value of the modulation wave is greater than the value of the triangular wave carrier is calculated as the number of states to be assigned to the first control state;
Program.

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