JP7686987B2 - MOTOR DRIVE APPARATUS, MOTOR DRIVE METHOD, AND MOTOR DRIVE PROGRAM - Google Patents

Description

The present invention relates to a motor drive device, a motor drive method, and a motor drive program.

An electric system having a motor and an inverter for driving the motor is used in electric vehicles such as hybrid cars and electric cars. In such an electric system, a technique is known in which, when an abnormality occurs, all upper arm side switching elements or all lower arm side switching elements in the inverter are turned on to short-circuit the motor (Patent Documents 1 to 4). For example, Patent Document 3 describes that "in a motor that uses a permanent magnet in a field magnet and operates at high speeds, if an abnormality occurs in the inverter at high speeds, the induced voltage generated by the rotation of the motor becomes an excessive voltage" (paragraph 0004), and therefore "the motor is normally driven by PWM, but when some abnormality occurs in the inverter, the three-phase switching elements are switched from PWM drive to three-phase short-circuit drive to suppress the DC power supply voltage to a predetermined voltage range" (paragraph 0009).
Furthermore, Patent Documents 5 to 7 disclose that when the motor is short-circuited, all the upper arm switching elements and all the lower arm switching elements are alternately turned on.
[Prior art documents]
[Patent Documents]
[Patent Document 1] JP 2000-14184 A [Patent Document 2] JP 2017-147806 A [Patent Document 3] JP 2015-198503 A [Patent Document 4] JP 2009-284747 A [Patent Document 5] WO 2016/136815 A [Patent Document 6] JP 2012-65425 A [Patent Document 7] JP 2018-152986 A

When the motor is under high load, if the motor winding is short-circuited by shorting all phases of the upper arm switching elements or the lower arm switching elements, a current that exceeds the current that flows during normal motor operation may transiently flow through the switching elements. Switching between the upper arm full-phase short circuit and the lower arm full-phase short circuit in this state may generate a large surge voltage.

In a first aspect of the present invention, a motor drive device is provided. The motor drive device may include a gate drive unit that drives a plurality of upper arm side switching elements and a plurality of lower arm side switching elements of an inverter for driving a motor. The motor drive device may include a fail-safe unit that performs fail-safe control including at least one of turning on all of the plurality of upper arm side switching elements or turning on all of the plurality of lower arm side switching elements. The gate drive unit may reduce the on-resistance of at least one switching element that is turned on among the plurality of upper arm side switching elements and the plurality of lower arm side switching elements during at least a portion of a period during which the fail-safe control is performed, below the on-resistance during at least a portion of a period during which the fail-safe control is not performed.

Each of the multiple upper arm switching elements and the multiple lower arm switching elements may be turned on in response to a gate drive voltage exceeding a threshold voltage being supplied to the gate. The gate drive unit may make the gate drive voltage supplied to the gate of at least one switching element higher during at least a portion of the period during which fail-safe control is performed than the gate drive voltage during at least a portion of the period during which fail-safe control is not performed.

The motor drive device may include a first power supply and a second power supply that outputs a power supply voltage higher than that of the first power supply. The gate drive unit may supply a gate drive voltage to be supplied to the gate of at least one switching element using the power supply voltage from the second power supply during at least a portion of a period in which fail-safe control is performed. The gate drive unit may supply a gate drive voltage to be supplied to the gate of at least one switching element using the power supply voltage from the first power supply during at least a portion of a period in which fail-safe control is not performed.

The second power source may be connected to the DC bus of the inverter.

The fail-safe unit may perform fail-safe control in response to the power supply voltage output by the first power supply becoming equal to or lower than a threshold voltage.

The gate driver may reduce the on-resistance of at least one switching element during at least a portion of the period during which fail-safe control is performed below the on-resistance during the period during which fail-safe control is not performed.

The gate drive unit may reduce the on-resistance of at least one switching element during at least a portion of the period during which fail-safe control is performed to be lower than the on-resistance during at least a portion of the period during which fail-safe control is not performed, provided that the current flowing through at least one switching element exceeds a threshold current.

The fail-safe section may alternately turn on all of the multiple upper arm switching elements and all of the multiple lower arm switching elements during fail-safe control.

The gate drive unit may reduce the on-resistance of each of the multiple upper arm switching elements and the multiple lower arm switching elements that are all turned on during at least a portion of the period during which fail-safe control is performed to be lower than the on-resistance during at least a portion of the period during which fail-safe control is not performed.

The gate driver may reduce the switching speed of at least one switching element during at least a portion of the period during which fail-safe control is performed below the switching speed during at least a portion of the period during which fail-safe control is not performed.

The gate driver may make the gate resistance connected to the gate of at least one switching element larger during at least a portion of the period in which fail-safe control is performed than the gate resistance during at least a portion of the period in which fail-safe control is not performed.

In a second aspect of the present invention, a motor drive device is provided. The motor drive device may include a gate drive unit that drives a plurality of upper arm side switching elements and a plurality of lower arm side switching elements of an inverter for driving a motor. The motor drive device may include a fail-safe unit that performs fail-safe control including at least one of turning on all of the plurality of upper arm side switching elements or turning on all of the plurality of lower arm side switching elements. The gate drive unit may reduce the switching speed of at least one switching element to be turned on among the plurality of upper arm side switching elements and the plurality of lower arm side switching elements during at least a portion of a period during which the fail-safe control is performed, below the switching speed during at least a portion of a period during which the fail-safe control is not performed.

The gate driver may make the gate resistance connected to the gate of at least one switching element larger during at least a portion of the period in which fail-safe control is performed than the gate resistance during at least a portion of the period in which fail-safe control is not performed.

Note that the above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions.

2 shows the configuration of an electrical system 200 according to the present embodiment. 2 shows an example of the configuration of a second fail-safe circuit 14 according to the present embodiment. 2 shows an example of the configuration of a lower arm gate drive circuit 21a according to the present embodiment. 4 shows an example of a gate drive signal waveform according to the present embodiment. 1 shows an example of a drain-source voltage characteristic according to a gate voltage of a switching element. 1 shows the configuration of an electric system 600 according to a modified example of the present embodiment. 1 shows an example of the configuration of an upper arm gate drive circuit 12a according to a modified example of this embodiment. 13 shows an example of a waveform of a gate drive signal according to a modified example of the present embodiment.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

Figure 1 shows the configuration of an electric system 200 according to this embodiment. Even when a current that exceeds the current that flows when the motor is driven flows transiently when all phases of the upper arm switching elements 4a-c or the lower arm switching elements 5a-c are short-circuited, the electric system 200 reduces power loss due to the switching elements by reducing the on-voltage generated between the main terminals of the switching elements that are turned on. As a result, the electric system 200 can keep power loss within the allowable range even when a large current flows through the switching elements that are turned on.

The electric system 200 includes a main battery 1, a switch 2, a DC bus capacitor 3, an auxiliary battery 6, a power supply circuit 13, a motor PM, one or more current sensors 100, an angle sensor 101, an inverter 210, and a motor drive device 220. The main battery 1 is, for example, a 400V power supply, and is connected between the positive and negative sides of the DC bus of the inverter 210 to generate power to be supplied to the motor PM.

The switch 2 is provided between the main battery 1 and the DC bus capacitor 3 and inverter 210, and switches whether or not the main battery 1 is connected to the DC bus capacitor 3 and inverter 210. As an example, the switch 2 may be switched to an ON state in response to the start of the electric system 200 or the vehicle equipped with the electric system 200, and may be switched to an OFF state in response to the occurrence of a failure or abnormality in the electric system 200 or the vehicle equipped with the electric system 200, or the voltage between the DC buses exceeding an upper limit voltage due to regeneration from the motor PM side. The switch 2 may also be switched to an OFF state in response to the interruption of the power supply from the auxiliary battery 6, i.e., in response to the voltage supplied from the auxiliary battery 6 becoming equal to or lower than a predetermined lower limit voltage, for example.

The DC bus capacitor 3 is connected between the positive and negative DC buses on the inverter 210 side of the switch 2. The DC bus capacitor 3 stabilizes the DC bus voltage and absorbs fluctuations in the current supplied to the inverter 210 side.

The auxiliary battery 6 is, for example, a 12V power source, and generates power to be supplied to the motor drive device 220. The auxiliary battery 6 may be connected to other devices (such as a starter motor and electrical equipment) provided in the vehicle in which the electric system 200 is mounted, and may supply power to these devices. The negative side of the auxiliary battery 6, ground GND_N1, may be grounded to the body of the vehicle, and is insulated from the main battery 1 and the DC bus capacitor 3.

The power supply circuit 13 is connected to the DC bus of the inverter 210, receives power from the DC bus capacitor 3, and outputs a power supply voltage VHV_2 obtained by lowering the voltage of the positive DC bus. The power supply circuit 13 is an example of a second power supply, and may be included in the motor drive device 220. Here, the power supply voltage VHV_2 has the potential of the negative DC bus (i.e., the potential of ground GND_N2 in the figure) as the reference potential, and may have a potential of, for example, the potential of ground GND_N2 + 16 V. The power supply circuit 13 is, for example, a DC voltage converter such as a DC/DC converter, and may be non-insulated from the main battery 1 and the DC bus capacitor 3.

As an example, the motor PM is a three-phase permanent magnet (PM) motor. Alternatively, the motor PM may have a different number of phases and may be another type of motor that rotates when supplied with electric power. In this embodiment, the motor PM rotates the wheels of a vehicle equipped with the electric system 200.

One or more current sensors 100 are provided on some or all of one or more wirings connected to the motor PM, and detect the current flowing through the corresponding wirings. The current sensor 100 may be a current sensor that measures the current without contacting the wiring to be measured, such as a CT (Current Transformer) type. The angle sensor 101 receives power supply from the auxiliary battery 6 and detects the rotation of the motor PM. The angle sensor 101 may be a rotation angle sensor, such as a resolver type, that detects the rotation angle of the motor PM.

The inverter 210 is connected between the DC busbars, converts the DC busbar voltage into an AC voltage (three-phase AC voltage in this embodiment) that drives the motor PM, and supplies it to the motor PM. The inverter 210 has a plurality of upper arm side switching elements 4a to c (hereinafter also referred to as "upper arm side switching elements 4") and a plurality of lower arm side switching elements 5a to c (hereinafter also referred to as "lower arm side switching elements 5") corresponding to each phase of the motor PM. Each upper arm side switching element 4 and each lower arm side switching element 5 may be a power semiconductor element, and as an example, is an IGBT (insulated gate bipolar transistor) having a collector and an emitter as main terminals and a gate as a control terminal. Alternatively, each upper arm side switching element 4 and each lower arm side switching element 5 may be a MOSFET having a drain and a source as main terminals and a gate as a control terminal. In this embodiment, each of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c is turned on in response to a gate drive voltage exceeding a threshold voltage being supplied to the gate.

The upper arm switching element 4a and the lower arm switching element 5a are connected in this order between the positive DC bus and the negative DC bus in parallel with the DC bus capacitor 3, and the first phase terminal (U-phase terminal) of the motor PM is connected between the upper arm switching element 4a and the lower arm switching element 5a. The upper arm switching element 4b and the lower arm switching element 5b, and the upper arm switching element 4c and the lower arm switching element 5c are connected between the DC bus in the same manner as the upper arm switching element 4a and the lower arm switching element 5a, and the second phase terminal (V-phase terminal) of the motor PM is connected between the upper arm switching element 4b and the lower arm switching element 5b, and the third phase terminal (W-phase terminal) of the motor PM is connected between the upper arm switching element 4c and the lower arm switching element 5c.

Each upper arm switching element 4 and each lower arm switching element 5 may have a freewheel diode reverse-connected to the switching element body. Here, when each upper arm switching element 4 and each lower arm switching element 5 are MOSFETs, the freewheel diode may be a parasitic diode.

The motor drive device 220 is connected to the inverter 210 and receives power from the power supply circuit 13 and the auxiliary battery 6 to control the inverter 210. The motor drive device 220 has a control circuit 7, a first fail-safe circuit 8, a fault detection circuit 15, a plurality of upper arm power supply circuits 9a-c, a plurality of upper arm gate drive circuits 12a-c, a lower arm power supply circuit 10, an insulation circuit 17, a second fail-safe circuit 14, and a plurality of lower arm gate drive circuits 21a-c. The circuit configuration including the plurality of upper arm power supply circuits 9a-c, the plurality of upper arm gate drive circuits 12a-c, and the plurality of lower arm gate drive circuits 21a-c is also referred to as the "gate drive section." The circuit configuration including the first fail-safe circuit 8 and the second fail-safe circuit 14 is also referred to as the "fail-safe section."

The control circuit 7 receives power from the auxiliary battery 6, with the potential of the negative ground GND_N1 of the auxiliary battery 6 as a reference potential. The control circuit 7 may be realized by executing a motor drive program using a CPU such as a microcontroller or processor for motor control, or a computer including a CPU. Alternatively, the control circuit 7 may be realized by a hardware circuit. The control circuit 7 receives a torque command τ* that specifies the torque to drive the motor PM from a computer (not shown) such as an ECU (Electric Control Unit) of the vehicle, and generates and outputs gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1 for driving the motor PM to generate a torque according to the torque command τ*. Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1 are gate drive commands corresponding to the upper arm switching element 4a, the upper arm switching element 4b, the upper arm switching element 4c, the lower arm switching element 5a, the lower arm switching element 5b, and the lower arm switching element 5c, respectively. In this embodiment, the control circuit 7 outputs a gate drive command that instructs the inverter 210 to generate a three-phase AC current for rotating the motor PM with the torque specified by the torque command τ*.

The first fail-safe circuit 8 receives power from the auxiliary battery 6, with the potential of the ground GND_N1 as a reference potential. The first fail-safe circuit 8 may be realized by a computer or the like, as with the control circuit 7, or may be realized by a hardware circuit. The first fail-safe circuit 8 performs fail-safe control on at least one of the upper arm gate drive circuits 12a-c or the lower arm gate drive circuits 21a-c, using at least one of the detection signal from the angle sensor 101 and the signal from the fault detection circuit 15. The first fail-safe circuit 8 obtains the rotation speed of the motor PM by time-differentiating the detection signal from the angle sensor 101. The first fail-safe circuit 8 may perform fail-safe control in response to the rotation speed of the motor PM exceeding a predetermined upper limit speed. The first fail-safe circuit 8 may also perform fail-safe control in response to receiving a signal from the fault detection circuit 15 indicating that an abnormality or fault in the control circuit 7 has been detected. In this embodiment, the first fail-safe circuit 8 performs both fail-safe control of the upper arm gate drive circuits 12a-c and fail-safe control of the lower arm gate drive circuits 21a-c.

Specifically, the first fail-safe circuit 8 inputs the gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1 from the control circuit 7, and in normal operation outputs the gate drive commands Gu_LV2, Gv_LV2, Gw_LV2, Gx_LV2, Gy_LV2, and Gz_LV2 without changing the values of the gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1. As a result, the inverter 210 drives the motor PM according to the control of the control circuit 7.

In the fail-safe operation, the first fail-safe circuit 8 may perform fail-safe control on the inverter 210, including turning off all of the upper-arm switching elements 4a-c using the upper-arm gate drive circuits 12a-c by setting the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 to logic L (low), and turning on all of the lower-arm switching elements 5a-c using the lower-arm gate drive circuits 21a-c by setting the gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 and the lower-arm short-circuit command Short_ON to logic H (high).

The fault detection circuit 15 is connected to the control circuit 7 and receives power from the auxiliary battery 6. The fault detection circuit 15 monitors the control circuit 7 to detect a fault or abnormality in the control circuit 7, and resets and restarts the control circuit 7 depending on the type of fault or abnormality. Depending on the type of fault or abnormality, the fault detection circuit 15 also instructs the first fail-safe circuit 8 to perform fail-safe control.

Each of the upper arm power supply circuits 9a to c receives power from the auxiliary battery 6 and converts the power supply voltage from the auxiliary battery 6 into a power supply voltage for controlling each of the upper arm switching elements 4a to c. Here, the upper arm power supply circuit 9a outputs a voltage with the main terminal (the emitter terminal of the upper arm switching element 4a in this embodiment) of the upper arm switching element 4a on the lower arm switching element 5a side as a reference potential (ground GND_U) as a power supply voltage for controlling the upper arm switching element 4a (for example, the potential of GND_U + 12V). Similarly, the upper arm power supply circuit 9b outputs a voltage with the ground GND_V as a reference potential as a power supply voltage for controlling the upper arm switching element 4b. The upper arm power supply circuit 9c outputs a voltage with the ground GND_W as a reference potential as a power supply voltage for controlling the upper arm switching element 4c. Each of the upper arm power supply circuits 9a to c may be an insulated DC/DC converter including an insulating transformer, for example.

The upper arm gate drive circuits 12a-c are connected to the first fail-safe circuit 8 and receive power from the auxiliary battery 6 and the upper arm power supply circuits 9a-c. The upper arm gate drive circuits 12a-c drive the gates of the upper arm switching elements 4a-c based on the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 from the first fail-safe circuit 8. More specifically, the upper arm gate drive circuit 12a includes an insulating element such as a photocoupler that transmits signals while providing electrical insulation, and converts the gate drive command Gu_LV2, which has the reference potential (ground GND_N1) of the auxiliary battery 6 as its reference potential, into a gate drive command GuO_HV, which has the reference potential of the ground GND_U, and outputs it to the gate of the upper arm switching element 4a. The same is true for the upper arm gate drive circuit 12b and the upper arm gate drive circuit 12c.

The lower arm power supply circuit 10 receives power from the auxiliary battery 6 and converts the power supply voltage of the auxiliary battery 6, which has a ground GND_N1 as a reference potential, into a power supply voltage VHV_1 (for example, the potential of ground GND_N2 + 12 V) which has a ground GND_N2 as a reference potential. The lower arm power supply circuit 10 is an example of a first power supply. Here, the power supply voltage VHV_2 output by the power supply circuit 13 as the second power supply is higher than the power supply voltage VHV_1 output by the lower arm power supply circuit 10 as the first power supply. The lower arm power supply circuit 10 may be an insulating type DC/DC converter including an insulating transformer. In a mode in which power from the DC bus capacitor 3 is not supplied to the motor drive device 220, the lower arm power supply circuit 10 may receive power from the auxiliary battery 6 and generate both the power supply voltage VHV_1 and the power supply voltage VHV_2.

The power supply voltage VHV_1 from the lower arm power supply circuit 10 and the power supply voltage VHV_2 from the power supply circuit 13 are joined via rectifying elements such as rectifying diodes to become the power supply voltage VHV. Here, the power supply voltage VHV_2 from the power supply circuit 13 is input to the rectifying element via a semiconductor switch FET1 such as a MOSFET. The semiconductor switch FET1 is turned on when the boost signal VHV_2_ON from the second fail-safe circuit 14 instructs the power supply voltage VHV_2 to be on (e.g., logic L), and is turned off when the boost signal VHV_2_ON from the second fail-safe circuit 14 instructs the power supply voltage VHV_2 to be off (e.g., logic H).

The insulation circuit 17 is connected to the first fail-safe circuit 8 and receives the lower arm short-circuit command Short_ON output by the first fail-safe circuit 8. The insulation circuit 17 includes an insulation element such as a photocoupler, and converts the lower arm short-circuit command Short_ON, which has the reference potential of the auxiliary battery 6 (ground GND_N1) as its reference potential, into a lower arm short-circuit command Short_HV, which has ground GND_N2 as its reference potential.

The second fail-safe circuit 14 is connected to the insulating circuit 17 and is provided with redundancy so as to receive power from the junction of the power supply voltages from the first power source and the second power source. The second fail-safe circuit 14 cooperates with the first fail-safe circuit 8 to perform fail-safe control including at least one of turning on all of the multiple upper arm switching elements 4a-c or turning on all of the multiple lower arm switching elements 5a-c. In this embodiment, the first fail-safe circuit 8 and the second fail-safe circuit 14 perform fail-safe control by turning off all of the multiple upper arm switching elements 4a-c and turning on all of the multiple lower arm switching elements 5a-c.

In this embodiment, the first fail-safe circuit 8 and the second fail-safe circuit 14 perform fail-safe control when the power supply from the auxiliary battery 6 is lost, when the rotation speed of the motor PM exceeds the upper limit speed, and when a failure or abnormality in the control circuit 7 is detected by the failure detection circuit 15. The second fail-safe circuit 14 performs fail-safe control on the lower arm gate drive circuits 21a-c using the power supply voltage VHV_1 from the lower arm power supply circuit 10 and the lower arm short-circuit command Short_HV from the insulation circuit 17.

In this embodiment, the second fail-safe circuit 14 detects that the power supply from the auxiliary battery 6 has been lost in response to the power supply voltage VHV_1 from the lower arm power supply circuit 10 becoming equal to or lower than the lower limit voltage. When the power supply from the auxiliary battery 6 is lost, the second fail-safe circuit 14 performs fail-safe control on the lower arm gate drive circuits 21a-c that receive power from the DC bus capacitor 3 via the power supply circuit 13. In this embodiment, the second fail-safe circuit 14 sets the gate drive command Gxyz_HV to logic L during normal operation. In fail-safe control when the power supply from the auxiliary battery 6 is lost, the second fail-safe circuit 14 sets the gate drive command Gxyz_HV to logic H and turns on all of the lower arm switching elements 5a-c.

When the second fail-safe circuit 14 performs fail-safe control in response to a loss of power supply from the auxiliary battery 6 or a lower arm short-circuit command Short_HV of logic H being received, the second fail-safe circuit 14 outputs a boost signal VHV_2_ON (e.g., logic L) that instructs the power supply voltage VHV_2 to be turned on. As a result, when performing fail-safe control, the second fail-safe circuit 14 changes the power supply voltage VHV supplied to the lower arm gate drive circuits 21a-c from power supply voltage VHV_1 to power supply voltage VHV_2.

The lower arm gate drive circuits 21a-c are connected to the first fail-safe circuit 8 and the second fail-safe circuit 14, and receive power from the auxiliary battery 6 and the power supply voltage VHV. The lower arm gate drive circuits 21a-c drive the gates of the lower arm switching elements 5a-c based on the gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 from the first fail-safe circuit 8 and the second fail-safe circuit 14. The lower arm gate drive circuit 21a switches the lower arm switching element 5a on or off based on the gate drive command Gx_LV2 from the first fail-safe circuit 8 when the gate drive command Gxyz_HV from the second fail-safe circuit 14 is logical L, and outputs a gate drive command GxO_HV to the lower arm switching element 5a to turn the lower arm switching element 5a on when the gate drive command Gxyz_HV from the second fail-safe circuit 14 is logical H. Here, the gate drive command GxO_HV is a signal whose reference potential is the reference potential (ground GND_N2) of the main battery 1 and the DC bus capacitor 3. The lower arm gate drive circuit 21a generates the gate drive voltage of the gate drive command GxO_HV, which is supplied to the gate when the lower arm switching element 5a is turned on, using the power supply voltage VHV. The lower arm gate drive circuit 21b and the lower arm gate drive circuit 21c also have the same function.

2 shows an example of the configuration of the second fail-safe circuit 14 according to this embodiment. The second fail-safe circuit 14 includes a reference voltage source 250, a comparator 260, and a logic element 270. The reference voltage source 250 generates a reference voltage. In this embodiment, the reference voltage source 250 generates a threshold voltage Vref that is a reference for whether the auxiliary battery 6 is normal or not. The comparator 260 has a negative input terminal (inverting input terminal) that inputs the power supply voltage VHV_1 from the lower arm power supply circuit 10, and a positive input terminal (non-inverting input terminal) that inputs the threshold voltage Vref of the reference voltage source 250. As a result, the comparator 260 outputs a logic L as the gate drive command Gxyz_HV when the power supply voltage VHV_1 is higher than the threshold voltage Vref, and a logic H when the power supply voltage VHV_1 becomes equal to or lower than the threshold voltage Vref (i.e., when it is determined that the auxiliary battery 6 has been lost). This allows the second fail-safe circuit 14 to perform fail-safe control in response to the power supply voltage VHV_1 output by the lower arm power supply circuit 10 becoming equal to or lower than the threshold voltage Vref. The comparator 260 may have hysteresis.

The logic element 270 is, for example, a NOR element. The logic element 270 outputs logic H when the gate drive command Gxyz_HV output by the comparator 260 is logic L and the lower arm short-circuit command Short_HV from the insulation circuit 17 is logic L. The logic element 270 outputs logic L when the gate drive command Gxyz_HV output by the comparator 260 becomes logic H or the lower arm short-circuit command Short_HV from the insulation circuit 17 becomes logic H. As a result, when the power supply from the auxiliary battery 6 is lost or when a failure or abnormality in the control circuit 7 is detected by the failure detection circuit 15, the logic element 270 turns on FET1 and increases the power supply voltage VHV from the power supply voltage VHV_1 output by the lower arm power supply circuit 10 to the power supply voltage VHV_2 output by the power supply circuit 13.

As a result, during the period when fail-safe control is being performed, the lower-arm gate drive circuits 21a-c can supply the gate drive voltage to the gates of the lower-arm switching elements 5a-c using the power supply voltage VHV_2 from the power supply circuit 13. Also, during the period when fail-safe control is not being performed, the lower-arm gate drive circuits 21a-c can supply the gate drive voltage to the gates of the lower-arm switching elements 5a-c using the power supply voltage VHV_1 from the lower-arm power supply circuit 10.

Figure 3 shows an example of the configuration of the lower arm gate drive circuit 21a according to this embodiment. The lower arm gate drive circuit 21a includes an insulation circuit 300, an OR element 310, resistors R31-R32, transistors 320a-b, and a resistor R33. The insulation circuit 300 converts the gate drive command Gx_LV2 based on the ground GND_N1 to a gate drive command Gx_HV based on the ground GND_N2. The OR element 310 outputs the OR of the gate drive command Gx_HV from the insulation circuit 300 and the gate drive command Gxyz_HV from the second fail-safe circuit 14. The resistors R31-R32 are connected between the output terminal of the OR element 310 and the gates of the transistors 320a-b, and function as gate resistors for the transistors 320a-b.

The main terminals of the transistors 320a-b are connected in series in this order between a node where the power supply voltage VHV_2 from the power supply circuit 13 and the power supply voltage VHV_1 from the lower arm power supply circuit 10 join, and ground GND_N2. The control terminal of the transistor 320a is connected to the terminal of the resistor R31 opposite the logical sum element 310, and the control terminal of the transistor 320b is connected to the terminal of the resistor R32 opposite the logical sum element 310.

When the output of the logical sum element 310 is logic H, the transistors 320a-b drive the intermediate node between the transistors 320a-b to the power supply voltage VHV, and when the output of the logical sum element 310 is logic L, the transistors 320a-b drive the intermediate node to the voltage of ground GND_N2. Resistor R33 is provided between the intermediate node between the transistors 320a-b and the gate of the lower arm switching element 5a, and outputs the voltage of the intermediate node driven by the transistors 320a-b as the gate drive voltage of the lower arm switching element 5a.

As a result, the lower arm gate drive circuit 21a can set the gate drive voltage of the lower arm switching element 5a to the voltage of ground GND_N2 when the gate drive command Gx_LV2 from the first fail-safe circuit 8 and the gate drive command Gxyz_HV from the second fail-safe circuit 14 are logic L, and can raise the gate drive voltage of the lower arm switching element 5a to the power supply voltage VHV when at least one of the gate drive command Gx_LV2 or the gate drive command Gxyz_HV becomes logic H. The lower arm gate drive circuits 21b-c may have a configuration similar to that of the lower arm gate drive circuit 21a.

Figure 4 shows an example of a gate drive signal (gate drive command) waveform according to this embodiment. More specifically, this figure shows the change over time in the upper arm gate drive commands GuO_HV, GvO_HV, and GwO_HV output by the multiple upper arm gate drive circuits 12a-c, and the lower arm gate drive commands GxO_HV, GyO_HV, and GzO_HV output by the multiple lower arm gate drive circuits 21a-c.

While the control circuit 7 is operating normally, it outputs gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1 for driving the motor PM to rotate by PWM control. While the fault detection circuit 15 detects that the control circuit 7 is operating normally, the first fail-safe circuit 8 outputs the gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1 as gate drive commands Gu_LV2, Gv_LV2, Gw_LV2, Gx_LV2, Gy_LV2, and Gz_LV2 without changing the values of the gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV2, Gy_LV2, and Gz_LV2, and sets the lower arm short-circuit command Short_ON to logic L.

The upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c supply three-phase AC current to the motor PM in response to the gate drive commands Gu_LV2, Gv_LV2, Gw_LV2, Gx_LV2, Gy_LV2, and Gz_LV2 to drive and rotate the motor PM. Here, during normal operation, the power supply voltage VHV_1 of the auxiliary battery 6 exceeds the threshold voltage Vref of the reference voltage source 250, and the lower arm short-circuit command Short_HV is logic L, so the second fail-safe circuit 14 sets the boost signal VHV_2_ON to logic H and turns off FET1. As a result, the motor drive device 220 sets the power supply voltage VHV to the power supply voltage VHV_1 from the lower arm power supply circuit 10 during a period in which fail-safe control is not performed. Therefore, when the lower arm gate drive circuits 21a-c turn on the lower arm switching elements 5a-c, the gate drive voltage VHV of the lower arm gate drive commands GxO_HV, GyO_HV, and GzO_HV during the period when fail-safe control is not being performed is set to the power supply voltage VHV_1.

When the rotation speed of the motor PM exceeds the upper limit speed, or when the fault detection circuit 15 detects an abnormality or fault in the control circuit 7, the first fail-safe circuit 8 performs fail-safe control to short-circuit the windings of the motor PM. In fail-safe control, the first fail-safe circuit 8 sets the upper arm gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 to logic L (low). In response, the upper arm gate drive circuits 12a-c turn off all of the upper arm switching elements 4a-c.

In addition, the first fail-safe circuit 8 sets the lower arm gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 to logic H in fail-safe control. In response to this, the lower arm gate drive circuits 21a-c turn on all of the lower arm switching elements 5a-c. Here, the first fail-safe circuit 8 sets the lower arm short circuit command Short_ON to logic H in such fail-safe control. In response to this, the second fail-safe circuit 14 receives the lower arm short circuit command Short_HV of logic H, sets the boost signal VHV_2_ON to logic L, and turns on FET1. Therefore, the power supply voltage VHV is boosted from the power supply voltage VHV_1 to the power supply voltage VHV_2. As a result, during the period when fail-safe control is being performed, the lower arm gate drive circuits 21a-c supply a gate drive voltage VHV to the gates of the lower arm switching elements 5a-c, which is a gate drive voltage VHV_2 that is higher than the gate drive voltage VHV_1 during the period when fail-safe control is not being performed.

Here, if the power supply from the auxiliary battery 6 is lost, the power supply voltage VLV supplied to the control circuit 7 and the first fail-safe circuit 8 is lost, and the control circuit 7 and the first fail-safe circuit 8 do not operate. In this case, the second fail-safe circuit 14 detects that the power supply voltage VHV_1 is equal to or lower than the threshold voltage Vref, sets the gate drive command Gxyz_HV to logic H, and sets the boost signal VHV_2_ON to logic L to turn on FET1. Accordingly, the power supply voltage VHV is boosted from the power supply voltage VHV_1 to the power supply voltage VHV_2. As a result, the lower arm gate drive circuits 21a-c turn on all of the lower arm switching elements 5a-c even if the power supply from the auxiliary battery 6 is lost. During the period when fail-safe control is being performed, the lower arm gate drive circuits 21a-c supply a gate drive voltage VHV to the gates of the lower arm switching elements 5a-c, which is a gate drive voltage VHV_2 that is higher than the gate drive voltage VHV_1 during the period when fail-safe control is not being performed.

Figure 5 shows an example of the drain-source voltage characteristics according to the gate voltage of a switching element. This figure shows the relationship between the current flowing through a MOSFET (drain current) and the voltage generated between the main terminals of the MOSFET (drain-source voltage) when the gate voltage (gate-source voltage) is changed to 10 V, 12 V, ..., 20 V in a certain MOSFET.

For n-type switching elements such as IGBTs and MOSFETs that turn on when the gate voltage exceeds a threshold, the higher the gate voltage, the smaller the voltage generated between the main terminals when the same current flows. Since the power consumed by a switching element is the product of the current flowing through the switching element and the voltage between the main terminals, in the case of n-type switching elements, the higher the gate voltage, the smaller the power consumption (i.e., the smaller the loss) and the less heat is generated.

One of the characteristics of an n-type switching element is the maximum gate-source voltage (or gate-emitter voltage) that may be applied, as specified (for example, the maximum rated gate-source voltage). In general, in order to reduce failures and extend the life of the switching element, the drive circuit for the switching element does not drive the switching element at the maximum rated gate-source voltage, but rather provides a certain amount of margin.

For example, suppose a switching element with the characteristics shown in this diagram has a maximum rated gate-source voltage of 20V. If the drive circuit drives this switching element with a gate-source voltage of 12V to turn it on, a potential difference of about 4.7 to 4.8V will be generated between the main terminals when a current of 50A flows through the switching element. In this case, the on-resistance of the switching element will be 4.7 to 4.8V/50A = 0.094 to 0.096Ω, and the power consumption of the switching element will be 50A x 4.7 to 4.8V = 235 to 240W.

In contrast, if the drive circuit drives this switching element with a gate-source voltage of 16V to turn it on, a potential difference of about 1.4 to 1.5V will be generated between the main terminals when a current of 50A flows through the switching element. In this case, the on-resistance of the switching element will be 1.4 to 1.5V/50A = 0.028 to 0.03Ω, and the power consumption of the switching element will be 50A x 1.4 to 1.5V = 70 to 75W.

As described in relation to FIG. 4, the lower arm gate drive circuits 21a-c according to this embodiment supply a gate drive voltage to the gates of the lower arm switching elements 5a-c that are turned on during the period when fail-safe control is being performed that is higher than the gate drive voltage during the period when fail-safe control is not being performed. As a result, the lower arm gate drive circuits 21a-c reduce the on-resistance of the multiple lower arm switching elements 5a-c that are turned on during the period when fail-safe control is being performed to be lower than the on-resistance during the period when fail-safe control is not being performed, reducing power consumption (on-loss) and protecting the lower arm switching elements 5a-c from breakdowns due to heat generation, etc.

The lower arm gate drive circuits 21a-c may further reduce the on-resistance by increasing the gate drive voltage supplied to the gates of the lower arm switching elements 5a-c that are turned on only during a portion of the period during which fail-safe control is performed, compared to the gate drive voltage during the period during which fail-safe control is not performed. For example, the motor drive device 220 may boost the power supply voltage VHV to power supply voltage VHV_2 for a predetermined period from the start of fail-safe control, and after the predetermined period has elapsed, return it to power supply voltage VHV_1 even during fail-safe control. According to this method, the lower arm gate drive circuits 21a-c can reduce the on-resistance of the lower arm switching elements 5a-c immediately after the start of fail-safe control while the rotation speed of the motor PM is high, and can protect the lower arm switching elements 5a-c from failures due to heat generation, etc.

Conversely, the motor drive device 220 may maintain the power supply voltage VHV at power supply voltage VHV_1 for a predetermined period from the start of fail-safe control, and may boost the power supply voltage VHV to power supply voltage VHV_2 if fail-safe control is still in progress after the predetermined period has elapsed. According to this method, if fail-safe control continues beyond a predetermined period after the start of fail-safe control, the lower arm gate drive circuits 21a-c can reduce the on-resistance of the lower arm switching elements 5a-c at that point, and can suppress further heat generation of the lower arm switching elements 5a-c to some extent.

The motor drive device 220 may also increase the power supply voltage VHV to the power supply voltage VHV_2 on the condition that, during at least a portion of the period during which the fail-safe control is performed, the current flowing through at least one lower-arm switching element 5 exceeds a threshold current, or the rotation speed of the motor PM exceeds a threshold. As a result, the lower-arm gate drive circuits 21a-c reduce the on-resistance of the lower-arm switching elements 5a-c to less than the on-resistance during the period during which the fail-safe control is not performed, in response to such conditions being met during at least a portion of the period during which the fail-safe control is performed. According to this method, the motor drive device 220 can increase the gate drive voltage and suppress heat generation in the lower-arm switching element 5 on the condition that the current flowing through the lower-arm switching element 5 is excessive due to, for example, a high rotation speed of the motor PM.

The lower arm gate drive circuits 21a-c may also reduce the on-resistance of the lower arm switching elements 5a-c that are turned on during at least a portion of the above-mentioned period in which fail-safe control is performed, below the on-resistance during at least a portion of the period in which fail-safe control is not performed. For example, the lower arm gate drive circuits 21a-c may further have a function of reducing the on-resistance of the switching elements that are turned on among the lower arm switching elements 5a-c even during a portion of the period in which fail-safe control is not performed. In such a configuration, the resistance value of the on-resistance of the lower arm switching element 5 that the lower arm gate drive circuits 21a-c turn on during a portion of the period in which fail-safe control is not performed may be equal to or less than the resistance value of the on-resistance of the lower arm switching elements 5a-c during the period in which fail-safe control is performed.

In addition, during the period when fail-safe control is performed, the motor drive device 220 does not have to reduce the on-resistance of all of the lower-arm switching elements 5a-c, and may reduce the on-resistance of at least one lower-arm switching element 5. For example, the motor drive device 220 may measure the temperature of each lower-arm switching element 5 and reduce the on-resistance of only the lower-arm switching element 5 whose temperature exceeds a threshold value.

The electric system 200 may use p-type MOSFETs or the like as the lower-arm switching elements 5a-c, which are turned on in response to a gate drive voltage less than the threshold voltage being supplied to the gate. In this case, the motor drive device 220 may reduce the on-resistance of the lower-arm switching elements 5a-c by lowering the gate drive voltage supplied to the gate of the lower-arm switching elements 5a-c that are turned on during at least a portion of the period during which fail-safe control is performed, compared to the gate drive voltage during at least a portion of the period during which fail-safe control is not performed.

Figure 6 shows the configuration of an electric system 600 according to a modified example of this embodiment. The electric system 600 includes a main battery 1, a switch 2, a DC bus capacitor 3, an auxiliary battery 6, a motor PM, one or more current sensors 100, an angle sensor 101, an inverter 210, and a motor drive device 220. Here, the components other than the motor drive device 220 have the same functions and configurations as the components with the same reference numerals in the electric system 200 shown in Figure 1, and therefore will not be described except for the differences.

The motor drive device 220 has a control circuit 7, a first fail-safe circuit 8, a fault detection circuit 15, a plurality of upper arm power supply circuits 9a-c, a plurality of upper arm gate drive circuits 12a-c, a gate drive power supply circuit 617, and a plurality of lower arm gate drive circuits 21a-c. Each of these components has the same or similar function and configuration as the components with the same reference numerals in the electric system 200 shown in FIG. 1, so the following description will be omitted except for the differences.

The first fail-safe circuit 8 performs fail-safe control on the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c using at least one of the detection signal from the angle sensor 101 and the signal from the fault detection circuit 15. In the fail-safe control, the first fail-safe circuit 8 alternates between an operation of turning on all of the upper arm switching elements 4a-c with the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 set to logic H and the gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 set to logic L, and an operation of turning on all of the lower arm switching elements 5a-c with the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 set to logic L and the gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 set to logic H. In addition, the first fail-safe circuit 8 sets the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L to logic L when fail-safe control is not performed, and sets the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L to logic H when fail-safe control is performed.

Each of the upper arm power supply circuits 9a-c receives power from the auxiliary battery 6 and converts the power supply voltage from the auxiliary battery 6 into a power supply voltage (VHV_u, VHV_v, and VHV_w) for controlling each of the upper arm switching elements 4a-c. In this modified example, each of the upper arm power supply circuits 9a-c outputs a power supply voltage VHV_1 as a power supply voltage for controlling each of the upper arm switching elements 4a-c when the upper arm short circuit command Short_U is logical L, and outputs a power supply voltage VHV_2 when the upper arm short circuit command Short_U is logical H.

The upper arm gate drive circuits 12a-c are connected to the first fail-safe circuit 8 and receive power from the auxiliary battery 6 and the upper arm power supply circuits 9a-c. The upper arm gate drive circuits 12a-c drive the gates of the upper arm switching elements 4a-c based on the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 from the first fail-safe circuit 8 and the upper arm short-circuit command Short_U. In this modified example, the upper arm gate drive circuits 12a-c reduce the switching speed of the upper arm switching elements 4a-c during at least a portion of the period during which fail-safe control is performed based on the upper arm short-circuit command Short_U, below the switching speed during at least a portion of the period during which fail-safe control is not performed.

The gate drive power supply circuit 617 receives power supply from the auxiliary battery 6 and converts the power supply voltage of the auxiliary battery 6, which has ground GND_N1 as a reference potential, into a power supply voltage VHV_xyz, which has ground GND_N2 as a reference potential. Here, the gate drive power supply circuit 617 sets the power supply voltage VHV_xyz to power supply voltage VHV_1 when the upper arm short-circuit command Short_U from the first fail-safe circuit 8 is logical L, and sets the power supply voltage VHV_xyz to power supply voltage VHV_2 when the upper arm short-circuit command Short_U from the first fail-safe circuit 8 is logical H.

The lower arm gate drive circuits 21a-c are connected to the first fail-safe circuit 8 and receive power from the auxiliary battery 6 and the gate drive power supply circuit 617. The lower arm gate drive circuits 21a-c drive the gates of the lower arm switching elements 5a-c based on the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 from the first fail-safe circuit 8. In this modified example, the lower arm gate drive circuits 21a-c reduce the switching speed of the lower arm switching elements 5a-c during at least a portion of the period in which fail-safe control is performed based on the lower arm short-circuit command Short_L, below the switching speed during at least a portion of the period in which fail-safe control is not performed.

Figure 7 shows an example of the configuration of an upper arm gate drive circuit 12a according to a modified example of this embodiment. The upper arm gate drive circuit 12a includes a gate driver 700, an insulating element 710, a logical NOT element 720, a number of switches 730a-b, and a number of resistors 740a-b.

The gate driver 700 receives the power supply voltage VLV from the auxiliary battery 6 and the power supply voltage VHV_u from the upper arm power supply circuit 9a. The gate driver 700 is connected to the first fail-safe circuit 8 and receives the gate drive command Gu_LV2 output by the first fail-safe circuit 8. The gate driver 700 includes an insulating circuit such as the insulating circuit 300 shown in FIG. 3 as an example, and converts the gate drive command Gu_LV2, which has the reference potential (ground GND_N1) of the auxiliary battery 6 as a reference potential, into a gate drive command based on ground GND_U. The gate driver 700 also includes a drive circuit such as the transistors 320a-b shown in FIG. 3 as an example, and outputs the gate drive command GuO_HV for driving the gate of the upper arm switching element 4a based on the gate drive command converted based on ground GND_U.

The insulating element 710 is connected to the first fail-safe circuit 8 and receives the upper arm short-circuit command Short_U output by the first fail-safe circuit 8. The insulating element 710 includes an insulating element such as a photocoupler, and converts the upper arm short-circuit command Short_U, which has the reference potential (ground GND_N1) of the auxiliary battery 6 as a reference potential, into an upper arm short-circuit command based on ground GND_U. The logical NOT element 720 inverts the logical value of the upper arm short-circuit command Short_U converted by the insulating element 710.

The switch 730a is connected between the gate driver 700 and the resistor 740a, and switches whether or not the gate drive command GuO_HV output by the gate driver 700 is output to the upper arm switching element 4a via the resistor 740a. Here, the switch 730a is turned on when the output of the logical NOT element 720 is logic H, i.e., when the upper arm short-circuit command Short_U is logic L, and is turned off when the upper arm short-circuit command Short_U is logic H.

The switch 730b is connected between the gate driver 700 and the resistor 740b, and switches whether or not the gate drive command GuO_HV output by the gate driver 700 is output to the upper arm switching element 4a via the resistor 740b. Here, the switch 730b is turned on when the output of the insulating element 710 is logic H, i.e., when the upper arm short-circuit command Short_U is logic H, and is turned off when the upper arm short-circuit command Short_U is logic L.

Each of the resistors 740a-b is connected between a corresponding switch 730 of the switches 730a-b and the upper arm switching element 4a. Each of the resistors 740a-b is connected between the gate driver 700 and the upper arm switching element 4a when the corresponding switch 730 is turned on, and functions as a gate resistor for the upper arm switching element 4a.

Resistor 740a functions as a gate resistor for the upper arm switching element 4a when switch 730a is on during a period when fail-safe control is not being performed (when the upper arm short-circuit command Short_U is logic L). Resistor 740b functions as a gate resistor for the upper arm switching element 4a when switch 730b is on during a period when fail-safe control is being performed (when the upper arm short-circuit command Short_U is logic H).

The resistor 740b used during the period when fail-safe control is performed has a resistance value greater than that of the resistor 740a used during the period when fail-safe control is not performed. Therefore, the upper arm gate drive circuit 12a can make the gate resistance (i.e., resistor 740b) connected to the gate of the upper arm switching element 4a during the period when fail-safe control is performed greater than the gate resistance (i.e., resistor 740a) during the period when fail-safe control is not performed.

Here, the larger the gate resistance, the smaller the gate current becomes, and the slower the rise and fall speed of the gate voltage of the upper arm switching element 4a becomes. Therefore, the upper arm gate drive circuit 12a can reduce the switching speed of the upper arm switching element 4a during the period when fail-safe control is performed to be lower than the switching speed during the period when fail-safe control is not performed.

In this modified example, the upper arm gate drive circuits 12b-c may have the same function and configuration as the upper arm gate drive circuit 12a. Similarly to the upper arm gate drive circuit 12a, the lower arm gate drive circuits 21a-c may also reduce the switching speed of the lower arm switching elements 5a-c during the period when fail-safe control is performed below the switching speed during the period when fail-safe control is not performed.

As described above, according to the motor drive device 220 of this modified example, during fail-safe control, the on-resistance of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c is reduced compared to the on-resistance when fail-safe control is not performed. This allows the motor drive device 220 to suppress heat generation from the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c during fail-safe control.

In addition, according to the motor drive device 220 of this modified example, when the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c are alternately all turned on in fail-safe control, the gate resistances connected to each of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c are made larger than the gate resistances when fail-safe control is not performed. As a result, even when a current that exceeds the current that flows in normal motor driving flows through the motor PM, the motor drive device 220 can reduce the switching speed of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c when switching between all phases of the upper and lower arms short-circuited, thereby preventing the generation of a large surge voltage.

Figure 8 shows an example of the waveform of a gate drive signal according to a modified example of this embodiment. More specifically, this figure shows the change over time in the upper arm gate drive commands GuO_HV, GvO_HV, and GwO_HV output by the multiple upper arm gate drive circuits 12a-c, and the lower arm gate drive commands GxO_HV, GyO_HV, and GzO_HV output by the multiple lower arm gate drive circuits 21a-c in the electrical system 600.

While the control circuit 7 is operating normally, it outputs gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1 for driving the motor PM to rotate by PWM control. While the fault detection circuit 15 detects that the control circuit 7 is operating normally, the first fail-safe circuit 8 outputs the gate drive commands Gu_LV2, Gv_LV2, Gw_LV2, Gx_LV2, Gy_LV2, and Gz_LV2 without changing the values of the gate drive commands Gu_LV1, Gv_LV1, Gw_LV1, Gx_LV1, Gy_LV1, and Gz_LV1, and sets the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L to logic L.

The upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c supply three-phase AC current to the motor PM in response to the gate drive commands Gu_LV2, Gv_LV2, Gw_LV2, Gx_LV2, Gy_LV2, and Gz_LV2 to rotate and drive the motor PM. Here, during normal operation, the upper arm power supply circuits 9a-c supply the power supply voltage VHV_1 based on the reference potentials GND_U, GND_V, and GND_W for each phase to the upper arm gate drive circuits 12a-c in response to the upper arm short circuit command Short_U being logical L. Also, during normal operation, the gate drive power supply circuit 617 supplies the power supply voltage VHV_1 based on the reference potential GND_N2 to the lower arm gate drive circuits 21a-c in response to the lower arm short circuit command Short_L being logical L. Therefore, when the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c turn on the upper arm switching elements 4a-c and the lower arm switching elements 5a-c, the gate drive voltages of the upper arm gate drive commands GuO_HV, GvO_HV, and GwO_HV and the gate drive voltages of the lower arm gate drive commands GxO_HV, GyO_HV, and GzO_HV during the period when fail-safe control is not being performed are set to the power supply voltage VHV_1.

Here, the upper arm gate drive circuit 12a selects the resistor 740a having the smaller resistance value from among the multiple resistors 740a-b as the gate resistance of the upper arm switching element 4a in response to the upper arm short circuit command Short_U being logical L. Similarly, the upper arm gate drive circuits 12b-c and the lower arm gate drive circuits 21a-c also select the resistor having the smaller resistance value from among the multiple resistors as the gate resistance of the upper arm switching elements 4b-c and the lower arm switching elements 5a-c.

When the rotation speed of the motor PM exceeds the upper limit speed, or when the fault detection circuit 15 detects an abnormality or fault in the control circuit 7, the first fail-safe circuit 8 performs fail-safe control to short-circuit the windings of the motor PM. In the fail-safe control, the first fail-safe circuit 8 alternates between an operation in which the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 are logic H and the gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 are logic L to turn on the multiple upper arm switching elements 4a-c, and an operation in which the gate drive commands Gu_LV2, Gv_LV2, and Gw_LV2 are logic L and the gate drive commands Gx_LV2, Gy_LV2, and Gz_LV2 are logic H to turn on the multiple lower arm switching elements 5a-c.

In fail-safe control, the first fail-safe circuit 8 sets the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L to logic H. In response to the upper arm short-circuit command Short_U being logic H, the upper arm power supply circuits 9a-c supply a power supply voltage VHV_2 based on the reference potentials GND_U, GND_V, and GND_W for each phase to the upper arm gate drive circuits 12a-c. In addition, in response to the lower arm short-circuit command Short_L being logic H, the gate drive power supply circuit 617 supplies a power supply voltage VHV_2 based on the reference potential GND_N2 to the lower arm gate drive circuits 21a-c. Therefore, during the period when fail-safe control is performed, the multiple upper arm gate drive circuits 12a-c and the multiple lower arm gate drive circuits 21a-c boost the gate drive voltages of the upper arm gate drive commands GuO_HV, GvO_HV, and GwO_HV and the gate drive voltages of the lower arm gate drive commands GxO_HV, GyO_HV, and GzO_HV to the power supply voltage VHV_2 when the multiple upper arm switching elements 4a-c are all turned on and when the multiple lower arm switching elements 5a-c are all turned on.

In addition, in response to the upper arm short-circuit command Short_U being logical H, the upper arm gate drive circuit 12a selects resistor 740b, which has the greater resistance value, from among the multiple resistors 740a-b as the gate resistor of the upper arm switching element 4a. Similarly, the upper arm gate drive circuits 12b-c and the lower arm gate drive circuits 21a-c also select resistors, which have the greater resistance value, from among the multiple resistors as the gate resistors of the upper arm switching elements 4b-c and the lower arm switching elements 5a-c.

In this way, the motor drive device 220 according to this modified example can reduce the on-resistance of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c during fail-safe control compared to the on-resistance when fail-safe control is not performed. In addition, the motor drive device 220 can increase the gate resistance connected to each of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c compared to the gate resistance when fail-safe control is not performed.

In this modified example, the first fail-safe circuit 8 sets the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L to logic H during fail-safe control. Alternatively, the first fail-safe circuit 8 may set the upper arm short-circuit command Short_U to logic H from the start of turn-on to the end of turn-off of the multiple upper arm switching elements 4a-c, and set the upper arm short-circuit command Short_U to logic L from the end of turn-off of the multiple upper arm switching elements 4a-c to the start of the next turn-on. Similarly, the first fail-safe circuit 8 may set the lower arm short-circuit command Short_L to logic H from the start of turn-on to the end of turn-off of the multiple lower arm switching elements 5a-c, and set the upper arm short-circuit command Short_L to logic L from the end of turn-off of the multiple lower arm switching elements 5a-c to the start of the next turn-on.

Motor drive device 220 may have only one of the functions of further reducing the on-resistance of the switching element in fail-safe control and the function of further increasing the gate resistance of the switching element in fail-safe control. For example, motor drive device 220 may have only the function of further increasing the gate resistance of the switching element in fail-safe control.

Motor drive device 220 may also employ various alternatives described in relation to FIG. 4 for the function of further reducing the on-resistance of the switching element in fail-safe control. Motor drive device 220 may also employ alternatives similar to or similar to the various alternatives described in relation to FIG. 4 for the function of further increasing the gate resistance of the switching element in fail-safe control.

For example, the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c may reduce the switching speed of the switching elements to be turned on among the multiple upper arm side switching elements 4a-c and the multiple lower arm side switching elements 5a-c during at least a part of the period during which the fail-safe control is performed, below the switching speed during the period during which the fail-safe control is not performed. For example, the motor drive device 220 may increase the gate resistance of the multiple upper arm side switching elements 4a-c and the multiple lower arm side switching elements 5a-c by using, for example, the switch 730b, during a predetermined period from the start of the fail-safe control, with the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L set to logic H, and after the predetermined period has elapsed, the upper arm short-circuit command Short_U and the lower arm short-circuit command Short_L may be set to logic L, and the gate resistance of the multiple upper arm side switching elements 4a-c and the multiple lower arm side switching elements 5a-c may be returned to, for example, the switch 730a, even during the fail-safe control. According to this method, the lower arm gate drive circuits 21a-c can reduce the switching speed of the upper arm switching elements 4a-c and the lower arm switching elements 5a-c immediately after starting the fail-safe control while the rotation speed of the motor PM is high and a large surge voltage is likely to occur, thereby preventing overvoltage from being applied to the upper arm switching elements 4a-c and the lower arm switching elements 5a-c.

In addition, during the period during which fail-safe control is performed, the motor drive device 220 may increase the gate resistance of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c during the turn-on or turn-off period during which the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c are switched on and off, and may return the gate resistance of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c to their original state even during fail-safe control during a steady period during which the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c are not switched on and off.

The motor drive device 220 may increase the gate resistance of the upper arm switching elements 4a-c and the lower arm switching elements 5a-c on the condition that the current flowing through at least one lower arm switching element 5 exceeds a threshold current or the rotation speed of the motor PM exceeds a threshold during at least a part of the period during which the fail-safe control is performed. As a result, the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c reduce the switching speed of the upper arm switching elements 4a-c and the lower arm switching elements 5a-c to a value lower than the switching speed during the period during which the fail-safe control is not performed, in response to the satisfaction of such conditions during at least a part of the period during which the fail-safe control is performed. According to this method, the motor drive device 220 can reduce the switching speed of the upper arm switching elements 4a-c and the lower arm switching elements 5a-c, and suppress the surge voltage, on the condition that the current flowing through the lower arm switching element 5 is excessive due to the high rotation speed of the motor PM, etc.

In addition, the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c may increase the gate resistance of the upper arm switching elements 4a-c and the lower arm switching elements 5a-c during at least a portion of the period in which the fail-safe control is performed, as described above, compared to the gate resistance during at least a portion of the period in which the fail-safe control is not performed. For example, the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c may further have a function of increasing the gate resistance of the switching elements during another portion of the period in which the fail-safe control is not performed. In such a configuration, the upper arm gate drive circuits 12a-c and the lower arm gate drive circuits 21a-c may increase the resistance value of the gate resistance of the switching elements during another portion of the period in which the fail-safe control is not performed, to be equal to or greater than the resistance value of the gate resistance of the switching elements increased during the period in which the fail-safe control is performed.

In addition, during the period when fail-safe control is being performed, the motor drive device 220 does not have to increase the gate resistance of all of the multiple upper arm switching elements 4a-c and the multiple lower arm switching elements 5a-c, and may increase the gate resistance of only at least one switching element. For example, the motor drive device 220 may measure the current flowing through each switching element, and increase the gate resistance of only the switching element through which a current exceeding a threshold flows before turning it off.

Various embodiments of the present invention may be described with reference to flow charts and block diagrams, where a block may represent (1) a stage of a process in which an operation is performed or (2) a section of an apparatus responsible for performing an operation. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer readable instructions stored on a computer readable medium, and/or a processor provided with computer readable instructions stored on a computer readable medium. Dedicated circuitry may include digital and/or analog hardware circuitry and may include integrated circuits (ICs) and/or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry including logical AND, logical OR, logical XOR, logical NAND, logical NOR, and other logical operations, memory elements such as flip-flops, registers, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

A computer-readable medium may include any tangible device capable of storing instructions that are executed by a suitable device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture that includes instructions that can be executed to create means for performing the operations specified in the flowchart or block diagram. Examples of computer-readable media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), Blu-ray disks, memory sticks, integrated circuit cards, and the like.

The computer readable instructions may include either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages.

The computer-readable instructions may be provided to a processor or programmable circuitry of a programmable data processing apparatus, such as a general-purpose computer, special-purpose computer, or other computer, either locally or over a wide area network (WAN) such as a local area network (LAN), the Internet, etc., to execute the computer-readable instructions to create means for performing the operations specified in the flowcharts or block diagrams. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

The present invention has been described above using an embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiment. It is clear from the claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before" or "prior to," and it should be noted that the processes may be performed in any order, unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is necessary to perform the processes in this order.

1 Main battery 2 Switch 3 DC bus capacitor 4a-c Upper arm side switching element 5a-c Lower arm side switching element 6 Auxiliary battery 7 Control circuit 8 First fail-safe circuit 9a-c Upper arm power supply circuit 10 Lower arm power supply circuit 12a-c Upper arm gate drive circuit 13 Power supply circuit 14 Second fail-safe circuit 15 Fault detection circuit 17 Insulation circuit 21a-c Lower arm gate drive circuit 100 Current sensor 101 Angle sensor 200 Electric system 210 Inverter 220 Motor drive device 250 Reference voltage source 260 Comparator 270 Logic element 300 Insulation circuit 310 Logical OR element 320a-b Transistor 600 Electric system 617 Gate drive power supply circuit 700 Gate driver 710 Insulation element 720 Logical NOT element 730a-b Switch 740a-b Resistor

Claims (9)

a gate driver that drives a plurality of upper arm switching elements and a plurality of lower arm switching elements of an inverter for driving a motor;
a fail-safe unit that performs fail-safe control including at least one of turning on all of the plurality of upper arm side switching elements or turning on all of the plurality of lower arm side switching elements ;
A first power source;
a second power supply that outputs a power supply voltage higher than that of the first power supply;
Equipped with
the gate driver reduces an on-resistance of at least one of the plurality of upper-arm switching elements or the plurality of lower-arm switching elements that is all turned on during at least a portion of a period during which the fail-safe control is performed, to a value lower than an on-resistance during at least a portion of a period during which the fail-safe control is not performed ;
The gate driver includes:
supplying a gate drive voltage to be supplied to a gate of the at least one switching element using a power supply voltage from the second power supply during at least a part of a period during which the fail-safe control is performed;
supplying a gate drive voltage to be supplied to a gate of the at least one switching element using a power supply voltage from the first power supply during at least a part of a period in which the fail-safe control is not performed;
The fail-safe unit performs the fail-safe control in response to a power supply voltage output by the first power supply becoming equal to or lower than a threshold voltage.
Motor drive device. each of the upper arm switching elements and the lower arm switching elements is turned on in response to a gate drive voltage exceeding a threshold voltage being supplied to a gate;
2. The motor drive device according to claim 1, wherein the gate drive section makes a gate drive voltage supplied to the gate of the at least one switching element during at least a portion of a period in which the fail-safe control is performed higher than a gate drive voltage during at least a portion of a period in which the fail-safe control is not performed. The motor drive device according to claim 1 , wherein the second power source is connected to a DC bus of the inverter. 4. The motor drive device according to claim 1, wherein the gate drive unit reduces an on-resistance of the at least one switching element during at least a portion of a period in which the fail-safe control is performed to a value lower than an on-resistance during a period in which the fail-safe control is not performed. 5. The motor drive device according to claim 1, wherein the gate drive unit reduces the on-resistance of the at least one switching element during at least a portion of a period in which the fail-safe control is performed to be lower than the on-resistance during at least a portion of a period in which the fail-safe control is not performed, on condition that a current flowing through the at least one switching element exceeds a threshold current. The motor drive device according to claim 1 , wherein the fail-safe unit alternately turns on all of the upper arm switching elements and all of the lower arm switching elements in the fail-safe control. 7. The motor drive device according to claim 6, wherein the gate drive unit reduces an on-resistance of each of the plurality of upper arm side switching elements and the plurality of lower arm side switching elements that is all turned on during at least a portion of a period in which the fail-safe control is performed, below an on-resistance during at least a portion of a period in which the fail-safe control is not performed. 7. The motor drive device according to claim 1, wherein the gate drive unit reduces a switching speed of the at least one switching element during at least a portion of a period in which the fail-safe control is performed to a speed lower than a switching speed during at least a portion of a period in which the fail-safe control is not performed. 9. The motor drive device according to claim 8, wherein the gate drive unit makes a gate resistance connected to the gate of the at least one switching element larger during at least a portion of a period in which the fail-safe control is performed than a gate resistance during at least a portion of a period in which the fail-safe control is not performed.

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