JP7687084B2 - Non-volatile semiconductor memory performance evaluation device - Google Patents

Description

The present invention relates to a performance evaluation device for non-volatile semiconductor memory such as SD memory cards.

SD memory cards (see, for example, Patent Document 1) are used as recording devices for in-vehicle devices and the like. Conventional access performance evaluations of SD memory cards involve simply measuring the command response time when the address location to be accessed is changed continuously or randomly through an SD memory card interface, and the measurement results vary even for the same individual device, making it impossible to perform a highly accurate evaluation.

The main purpose of evaluating the access performance of an SD memory card is to find the performance limits specific to the SD memory card, and thereby to clarify that no abnormalities occur in reading and writing data from the perspective of the system using the SD memory card. For example, when an operating system (hereinafter referred to as OS) is placed on the SD memory card, when the SD memory card is used as a temporary storage destination for OS system resources, or when multiple applications are executed in parallel to read and write data on the SD memory card, data is frequently read and written to random address locations, making highly accurate evaluation of random access performance more important.

JP 2003-076952 A

However, conventional random access performance evaluations could not quantify the internal processing of an SD memory card, and even when the same pattern of random access was performed on SD memory cards of the same model number and from the same manufacturer, the results of the performance evaluation varied. Furthermore, conventional evaluations using a PC were affected by the overhead of the PC's OS, and similarly, even when the same pattern was written to SD memory cards of the same model number and from the same manufacturer, the results of the performance evaluation varied.

As such, with conventional evaluation methods, it was not possible to clearly determine the maximum processing time when writing to a specific SD memory card, and it was not possible to clearly grasp the limits of access performance based on this processing time. Therefore, when using an SD memory card in a system, command response times longer than expected by the system could occur. As a result, unexpected problems could occur due to writing errors or processing delays. Similar phenomena could also occur with non-volatile semiconductor memory other than SD memory cards, including NAND flash memory.

This embodiment was made in consideration of these circumstances, and its purpose is to provide a technology for evaluating the access performance of non-volatile semiconductor memory with high accuracy.

In order to solve the above problem, a nonvolatile semiconductor memory performance evaluation device of one aspect of the present embodiment is a nonvolatile semiconductor memory performance evaluation device including a NAND flash memory and a controller, and is equipped with a command execution unit that issues a descending write command that instructs writing data to all areas of the nonvolatile semiconductor memory in an access pattern that accesses the entire area in descending address order, and issues an ascending write command before or after that that instructs writing data to all areas of the nonvolatile semiconductor memory in an access pattern that accesses the entire area in ascending address order, and a host controller that acquires a command response time to the write command and generates performance evaluation data for the nonvolatile semiconductor memory based on the command response time . The command execution unit issues the descending write command a first set number of times or more and issues the ascending write command a second set number of times or more, and the host controller extracts as an access direction switching processing time a difference between a command response time for the first descending write command after the ascending write command is switched to the descending write command and a command response time for the next descending write command, or extracts as an access direction switching processing time a difference between a command response time for the first ascending write command after the descending write command is switched to the ascending write command and a command response time for the next ascending write command, and generates performance evaluation data of the non-volatile semiconductor memory further based on the extracted access direction switching processing time .

Another aspect of this embodiment is a performance evaluation method for a nonvolatile semiconductor memory. This method is a performance evaluation method for a nonvolatile semiconductor memory including a NAND flash memory and a controller, and includes a first step of issuing a write command in descending order that instructs writing data to an entire area of the nonvolatile semiconductor memory in an access pattern that accesses the entire area in descending address order, and a second step of acquiring a command response time to the write command. The first step issues the descending write command a set number of times or more, and the second step generates performance evaluation data for the nonvolatile semiconductor memory based on the command response time to the set number of or more descending write commands.

In addition, any combination of the above components, and conversions of the expressions of this embodiment between methods, devices, systems, recording media, computer programs, etc., are also valid aspects of this embodiment.

According to this embodiment, the access performance of non-volatile semiconductor memory can be evaluated with high accuracy.

1 is a diagram showing the configuration of an evaluation system for an SD memory card using a performance evaluation device according to an embodiment; FIG. 1 is a diagram illustrating a schematic diagram of a forward access continuous write operation to pages 3-5 in block 1 of a NAND flash memory. FIG. 1 is a diagram illustrating a schematic diagram of a reverse access write operation to pages 3-5 in block 1 of a NAND flash memory. 1 is a diagram showing an example of an access pattern when data is continuously written to an SD memory card by forward access; 11 is a diagram showing an example of an access pattern when data is continuously written to an SD memory card by reverse access; FIG. 13 is a diagram illustrating an example of a table in which command response times are plotted for each command issue number. 4 is a flowchart showing the flow of a method for evaluating an SD memory card using a performance evaluation device according to an embodiment. FIG. 13 is a diagram showing a subroutine of forward access data processing. FIG. 13 is a diagram showing a subroutine of data processing for reverse access. FIG. 13 is a diagram showing an example of a table in which evaluation data of a plurality of SD memory cards are plotted.

This embodiment relates to a performance evaluation device and a performance evaluation method for evaluating the limits of the access performance of SD memory cards (including micro SD cards) that are generally available on the market, by measuring the access time from an external interface based on the SD memory card standard.

Figure 1 is a diagram showing the configuration of an evaluation system for an SD memory card 10 using a performance evaluation device 20 according to an embodiment. The SD memory card 10 includes a NAND flash memory 11 and a controller 12. The NAND flash memory 11 is a memory that stores information based on the charge state of the floating gate of a transistor.

In the NAND flash memory 11, the source line is shared by multiple cells, so data is written/read in units of pages. Erasing is done in units of blocks containing multiple pages. Erasing is done by extracting electrons from the floating gate, and writing is done by injecting electrons into the floating gate. By sharing the source line with multiple cells, the NAND flash memory 11 achieves a higher level of integration than NOR flash memory, which has a source line for each cell.

The controller 12 controls the writing, reading, and erasing of data, conversion between logical and physical addresses, wear leveling, error correction, management of bad blocks, and interfacing with the host.

In the NAND flash memory 11, data cannot be overwritten; it must first be erased before being written. As described above, erasure must be done on a block-by-block basis. Therefore, the data in the entire block, including the write area, must first be read into a buffer, the entire block must be erased, and the data in the buffer and new data must be written to the block.

In addition to the NAND flash memory, SSDs have a volatile internal cache memory that can be used as a buffer when writing. DRAM is usually used for this internal cache memory. By using this DRAM in SSDs, high-speed writing is possible. In contrast, SD memory cards generally do not have a volatile internal cache memory in addition to the NAND flash memory 11 due to space constraints.

Therefore, the SD memory card 10 uses the surplus capacity of the NAND flash memory 11 to perform writing. The NAND flash memory 11 actually has a larger memory capacity than the recording capacity stated in the specifications. The difference between this specified memory capacity and the actual memory capacity is the surplus capacity. The surplus capacity is often set to about 10-25% of the actual memory capacity.

The SD memory card 10 utilizes this excess capacity for writing and wear leveling. When rewriting data, the controller 12 evacuates the data in the block that contains the page to be written (hereafter referred to as the target block) to an excess block and erases the data in the target block. The controller 12 writes the evacuated data (excluding the data in the page to be written) and new data to the target block.

When writing data larger than the block size, the controller 12 may write the new data to a surplus block and change the status of the surplus block to a normal block, and change the status of the block containing the old data to a surplus block.

The NAND flash memory 11 basically has no physical performance difference depending on the write address location, as in a HDD. Therefore, if the same data is written when the surplus capacity used as the internal cache is full, the command response time should be the same no matter which address it is written to.

However, when the surplus capacity used as the internal cache is full, it is common for there to be a difference in command response time between when data is written continuously in the forward direction to a specific address range of the SD memory card 10 and when data is written randomly to that address range. This is because, in the NAND flash memory 11, although it is possible to write multiple pages in a block continuously in the ascending address direction (hereafter also referred to as forward access), it is not possible to write continuously in the descending address direction (hereafter also referred to as reverse access). In other words, in the NAND flash memory 11, it is necessary to write multiple pages in a block in ascending address order.

Figure 2 is a schematic diagram showing the operation of continuously writing to pages 3-5 in block 1 of a NAND flash memory using forward access. Figure 3 is a schematic diagram showing the operation of continuously writing to pages 3-5 in block 1 of a NAND flash memory using reverse access. With forward access, data can be written to pages 3-5 in one write operation, but with reverse access, three write operations are required, for example, to pages 5, 4, and 3. In this way, continuous writing with reverse access requires more processing than continuous writing with forward access.

The above-mentioned processes are performed by the controller 12 as internal processes in the SD memory card 10. The physical address of the NAND flash memory 11 is converted to a logical address by the controller 12, and data is written to the NAND flash memory 11 based on the converted address.

As shown in Figure 2, writing to the NAND flash memory 11 is generally performed on a page-by-page basis, but because writing pages in descending order is prohibited, attempting to write pages in descending order as reverse access increases the number of write steps as shown in Figure 3. The writing method in Figure 3 is a conceptual diagram and a simple example. In reality, the internal processing method of the controller 12 when continuously writing data to the SD memory card 10 by reverse access through the SD memory card interface differs depending on the manufacturer of the SD memory card 10, and this ultimately manifests itself as a difference in the access performance of the SD memory card 10. Previous performance evaluations have not had a way to clearly grasp the internal processing time that differs depending on the manufacturer.

If the command response time when the same data is continuously written to the SD memory card 10 using forward access and the command response time when the data is continuously written using reverse access are added together based on the amount of data written, this should be the command response time per amount of data written. However, in reality, the command response time may take longer than this.

This is because the access direction of the NAND flash memory 11 is switched inside the SD memory card 10, as in the case where continuous writing with forward access as shown in Figure 2 is changed to continuous writing with reverse access as shown in Figure 3. This access direction switching process also differs depending on the manufacturer of the SD memory card 10, and this ultimately manifests itself as a difference in the access performance of the SD memory card 10. In previous performance evaluations, there was no way to clearly grasp the time required for this process.

As described above, the command response time during writing by each actual access includes the forward access write processing time, the reverse access write processing time, and the access direction switching processing time as components. In this embodiment, a method for evaluating the access performance of the SD memory card 10 with high accuracy is provided by quantitatively measuring and adding up each of these components.

The performance evaluation device 20 is a dedicated tester for measuring the pure performance of the SD memory card 10. The performance evaluation device 20 includes a command execution unit 21 and a host controller 22. The host controller 22 specifies an arbitrary address range and issues write commands/read commands of forward access or reverse access patterns. The host controller 22 can also specify the power supply voltage and transfer speed during data transfer.

In general, in benchmark tests of storage devices using a PC or smartphone, a specific LBA of an SD memory card 10, which is one of the storage devices, is repeatedly accessed from the PC or smartphone through the OS of the PC or smartphone to measure the access time. Such benchmark tests are subject to restrictions such as non-standardized access patterns, different transfer frequencies for each hardware configuration, and the presence of OS overhead. Due to these restrictions, it has been common to plot command response times for each measurement system environment and perform relative evaluations. Therefore, even if it has been possible to confirm that the SD memory card 10 being evaluated can be used in the measurement system without problems under normal usage methods, it has not been possible to accurately grasp the access performance of each individual SD memory card 10.

In contrast, in this embodiment, a dedicated tester environment is configured that does not involve OS overhead, and data with a specific access pattern is directly written to the entire area of the SD memory card 10 at the maximum transfer volume and maximum transfer frequency.

The command execution unit 21 outputs the write command/read command issued by the host controller 22 and executes data transfer processing between the SD memory card 10. The data transfer processing by the write command/read command is completed when a response is output from the SD memory card 10.

The host controller 22 determines the command response time and the processing time of each component based on the response to the write command/read command. The host controller 22 registers the acquired command response time and the processing time of each component as performance evaluation data in the database 30. It is preferable that the performance evaluation data is measured for each individual SD memory card and registered in an identifiable manner. The database 30 may be composed of, for example, an information device such as a PC, server, or tablet (not shown). The performance evaluation device 20 and the information device are connected, for example, by a USB cable, and the performance evaluation data is output from the performance evaluation device 20 to the database 30.

Figure 4 is a diagram showing an example of an access pattern when data is continuously written to an SD memory card by forward access. The vertical axis shows LBA (Logical Block Address) consisting of a logical address, and the horizontal axis shows command issue numbers (numbers indicating the command issue order). Write commands are issued in ascending order of command issue numbers. In the forward access shown in Figure 4, data is written to the entire area of the SD memory card 10 in 256 block units from 0 LBA to the maximum LBA. Any data may be written. For example, when the command execution unit 21 issues an n-th write command, it issues an n+1-th write command immediately after receiving a response to the n-th write command from the controller 12. Here, the time from issuing the n-th command to receiving the response is the n-th command response time. Note that writing in 256 block units is one example, and writing in other block units such as 512 block units may also be performed.

Figure 5 shows an example of an access pattern when data is continuously written to an SD memory card using reverse access. Write commands are issued in ascending order of command issue number. In the reverse access shown in Figure 5, data is written to the entire area of the SD memory card 11 in units of 256 blocks from the maximum LBA to 0 LBA. Any data can be written.

Figure 6 shows an example of a table that plots command response times for each command issue number n. A table that plots command response times is generated for both forward access and reverse access.

The write processing time for each type of access is described in detail below. The write processing time for forward access is calculated as the processing time per capacity from the write time required when writing to the entire area of the SD memory card 10 with a fixed access pattern, for example, as shown in FIG. 4. The write processing time for the reverse access is calculated as the processing time per capacity from the write time required when writing to the entire area of the SD memory card 10 with a fixed access pattern, for example, as shown in FIG. 5.

When the controller 12 of the SD memory card 10 continuously writes to the entire area in capacity units determined by each unidirectional access pattern, the same process is repeated internally, so the time required for each write is similar. However, the write time that involves switching the access direction is generally longer than the normal access process time.

The processing time for switching the access direction is included in the write time required to write to the entire area of the SD memory card 10, for example, in a forward access write process, and then in the first reverse access. Therefore, the processing time for switching the access direction can be found by taking the difference between the write time required to write to the entire area in the second reverse access and the previous write time.

Figure 7 is a flowchart showing the flow of a method for evaluating an SD memory card 10 using a performance evaluation device 20 according to an embodiment. The example shown in Figure 7 is an example in which forward access is performed five times and reverse access is performed five times.

The host controller 22 resets the forward access evaluation count parameter n to 1 (S10). The command execution unit 21 writes data continuously in the forward direction to the SD memory card 10 in an access pattern such as that shown in FIG. 4. The host controller 22 acquires the command response time and the write time for the entire area of the SD memory card 10 (S11). Any type of data can be written to the SD memory card 10, and the objective is to acquire the command response time for each access pattern such as that shown in FIG. 6.

The host controller 22 performs data processing to obtain the maximum command response time m and full area write time k for each forward access evaluation (S12).

Figure 8 shows a subroutine for forward access data processing. If the evaluation count parameter n is 1 (YES in S120), no data is entered in the maximum command response time parameter m, so the host controller 22 stores the value of the command response time [n] as is in the maximum value parameter m (S122).

If the evaluation count parameter n is other than 1 (NO in S120), the host controller 22 compares the value of the maximum value parameter m with the value of the command response time [n] (S121). If the value of the command response time [n] is greater (YES in S121), the host controller 22 updates the maximum value parameter m to the value of the command response time [n] (S122). If the value of the command response time [n] is not greater (NO in S121), the processing of step S122 is skipped.

If the evaluation count parameter n is 1 (YES in S123), since no data is stored in the maximum all-area write time parameter k, the host controller 22 stores the value of the all-area write time [n] directly in the maximum value parameter k (S125).

If the evaluation count parameter n is other than 1 (NO in S123), the host controller 22 compares the value of the maximum value parameter k with the value of the all-area write time [n] (S124). If the value of the all-area write time [n] is greater (YES in S124), the host controller 22 updates the maximum value parameter k to the value of the all-area write time [n] (S125). If the value of the all-area write time [n] is not greater (NO in S124), the processing of step S125 is skipped. Return to FIG. 7.

If the evaluation count parameter n is less than 5 (YES in S13), the host controller 22 counts up the evaluation count parameter n by 1 (S14). The process proceeds to step S11.

When the evaluation count parameter n reaches 5 (NO in S13), the host controller 22 records the maximum forward command response time m and the maximum all-area write time k obtained by performing five forward accesses in the database 30 (S15). The maximum all-area write time k converted into the access time per unit transfer amount becomes the forward access write processing time.

The reason for performing five forward accesses is to fill up the surplus capacity used as the internal cache. Therefore, as long as it is possible to ensure that the surplus capacity used as the internal cache is filled up, it does not have to be limited to five times and another setting may be used.

The host controller 22 resets the forward access evaluation count parameter n to 1 (S16). The command execution unit 21 writes data continuously in the reverse direction to the SD memory card 10 in the access pattern shown in FIG. 5. The host controller 22 acquires the command response time and the write time for the entire area of the SD memory card 10 (S17). Any type of data can be written to the SD memory card 10, and the objective is to acquire the command response time for each access pattern as shown in FIG. 6.

The host controller 22 performs data processing to obtain the maximum command response time p, the maximum total area write time q, and the maximum write time t during the access direction switching process during each reverse access evaluation (S18).

Figure 9 shows a subroutine for reverse access data processing. If the evaluation count parameter n is 1 (YES in S180), no data is entered in the maximum command response time parameter p, so the host controller 22 stores the value of the command response time [n] as is in the maximum value parameter p (S182).

If the evaluation count parameter n is other than 1 (NO in S180), the host controller 22 compares the value of the maximum value parameter p with the value of the command response time [n] (S181). If the value of the command response time [n] is greater (YES in S181), the host controller 22 updates the maximum value parameter p to the value of the command response time [n] (S182). If the value of the command response time [n] is not greater (NO in S181), the processing of step S182 is skipped.

If the evaluation count parameter n is 1 (YES in S183), since no data is stored in the maximum value parameter q of the total area write time, the host controller 22 stores the value of the total area write time [n] in the maximum value parameter q as is (S187).

If the evaluation count parameter n is 2 (NO in S183, YES in S184), the host controller 22 subtracts the value of the all-area write time [2] from the maximum value parameter q (the value of the all-area write time [1]) to calculate the write time t during the access direction switching process (S185). The first all-area write time includes the write time during the access direction switching process, but the second all-area write time does not. Therefore, by calculating the difference between the two, the write time during the access direction switching process can be calculated. If the evaluation count parameter n is other than 2 (NO in S184), the process of step S185 is skipped.

The host controller 22 compares the value of the maximum value parameter q with the value of the all-area write time [n] (S186). If the value of the all-area write time [n] is greater (YES in S186), the host controller 22 updates the maximum value parameter q to the value of the all-area write time [n] (S187). If the value of the all-area write time [n] is not greater (NO in S186), the processing of step S187 is skipped. Return to FIG. 7.

If the evaluation count parameter n is less than 5 (YES in S19), the host controller 22 increments the evaluation count parameter n by 1 (S20). The process proceeds to step S17. When reverse access is performed, five forward accesses have already been performed, so the surplus capacity used as the internal cache is full. Therefore, the number of reverse accesses performed may be less than five. The surplus capacity used as the internal cache uses part of the non-volatile NAND flash memory 11, so some data remains in the surplus capacity used as the internal cache.

When the evaluation count parameter n reaches 5 (NO in S19), the host controller 22 records the maximum value p of the command response time in the reverse direction and the maximum value q of the all-area write time obtained by performing five reverse accesses in the database 30 (S21). The maximum value q of the all-area write time is converted into the access time per unit transfer amount, which becomes the reverse access write processing time.

The host controller 22 records the write time t during the access direction switching process in the database 30 (S22).

Furthermore, the host controller 22 may calculate the write time per unit transfer amount of the SD memory card 10 as the random access performance of the SD memory card 10 by adding the write time t during the access direction switching process of the reverse access write process time to the forward access write process time.

Furthermore, the host controller 22 may determine the maximum command response time of the SD memory card 10 as the command response performance of the SD memory card 10 based on the maximum command response time m when writing in the forward direction and the maximum command response time p when writing in the reverse direction, including the access direction switching processing time.

To determine the system timeout during writing, the designer of a system that uses the SD memory card 10 requires the write time per unit transfer amount of the SD memory card 10 and the maximum command response time as random access performance. The maximum command response time may be the maximum value of the command response time for all accesses. The command response time during writing in reverse access may include the access direction switching processing time. The host controller 22 compares the maximum command response time m during forward writing with the maximum command response time p during reverse writing including the access direction switching processing time, and registers the larger one in the database 30 as the maximum command response time of the SD memory card 10.

Figure 10 shows an example of a table that plots evaluation data for multiple SD memory cards 10. The table shown in Figure 10 records the maximum command response time, forward access write time, reverse access write time, and access direction switching processing time for each individual SD memory card 10.

By recording such evaluation data of processing time, it is possible to determine the time required to write the data in each access direction based on the amount of data transferred during random access and the forward access write time or reverse access write time. By adding to this time the access direction switching processing time according to the number of times the access direction is switched, it is possible to estimate the random access performance during actual use in a system that uses the SD memory card 10. It is also possible to calculate the maximum command response time at this time.

According to this embodiment, the access processing time is obtained when the excess capacity of the internal cache is full. In SD memory cards 10 of the same type, in which the controller 12 and NAND flash memory 11 are configured in the same way, when the excess capacity of the internal cache is full, the internal processing of the controller 12 operates in the same way, so the maximum command response time and the maximum value of the time required to write to the entire area show similar results, and the random access performance calculated from these is also similar. In this embodiment, it is possible to more accurately estimate various access performances of SD memory cards 10 of the same type.

Conventionally, when evaluating the random access performance of the SD memory card 10, a write process was performed multiple times with an unspecified data capacity to an unspecified address based on pseudo-random numbers, etc., and the total processing time was used as the evaluation result. According to this embodiment, the unspecified method used in the past is not used, and by continuously performing evaluations for each access pattern a specified number of times, processing times for each access with little variation can be obtained, and by recording the processing times, the performance specific to the SD memory card 10 under load can be clarified.

As described above, according to this embodiment, the access performance of the SD memory card 10 can be evaluated with high accuracy. A designer of a system that uses the SD memory card 10 can appropriately determine the threshold setting for the timeout time of the system's processing based on the evaluation data such as that shown in FIG. 10. Furthermore, in a system in which the timeout time threshold has already been determined, an SD memory card 10 with sufficient margin in the specifications can be selected.

The performance evaluation of the SD memory card 10 according to this embodiment is effective for pre-evaluation in applications that require reliability, such as in-vehicle devices (e.g., drive recorders). It is possible to accurately extract SD memory cards 10 that meet the required writing speed. In addition, the performance evaluation of the SD memory card 10 according to this embodiment can also be used to evaluate the performance of second-hand SD memory cards 10 in circulation whose origins are unclear.

The present invention has been described above based on an embodiment. This embodiment is merely an example, and those skilled in the art will understand that various modifications are possible in the combination of each component and each processing process, and that such modifications are also within the scope of the present invention. Furthermore, substitutions of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also valid aspects of the present invention.

In the above embodiment, n forward accesses were performed, and then n reverse accesses were performed. In this regard, n reverse accesses may be performed first, and then n forward accesses may be performed. In this case, the write time during the access direction switching process is included in the full area write time of the first forward access. The write time during the access direction switching process is calculated from the difference between the full area write time of the first forward access and the full area write time of the second forward access.

In the above embodiment, the performance evaluation of the SD memory card 10 has been described as an example. In this respect, the SD memory card 10 is an example of a non-volatile semiconductor memory that does not include a volatile cache memory inside. It is also applicable to the performance evaluation of other non-volatile semiconductor memories that do not include a volatile cache memory inside. For example, it is also applicable to the performance evaluation of eMMC and USB memory.

10 SD memory card, 11 NAND flash memory, 12 controller, 20 performance evaluation device, 21 command execution unit, 22 host controller, 30 database.

Claims (3)

A performance evaluation device for a non-volatile semiconductor memory including a NAND flash memory and a controller,
a command execution unit that issues a write command in descending order to instruct writing of data in an access pattern that accesses all areas of the nonvolatile semiconductor memory in descending address order, and issues an ascending order write command before or after that to instruct writing of data in an access pattern that accesses all areas of the nonvolatile semiconductor memory in ascending address order;
a host controller that acquires a command response time to the write command and generates performance evaluation data of the nonvolatile semiconductor memory based on the command response time ;
the command execution unit issues the write command in the descending order a first set number of times or more and issues the write command in the ascending order a second set number of times or more;
The host controller
extracting, as an access direction switching processing time, a difference between a command response time for a first write command in the descending order after switching from the ascending order write command to the descending order write command and a command response time for a next write command in the descending order;
or
extracting, as an access direction switching processing time, a difference between a command response time for a first ascending order write command after switching from the descending order write command to the ascending order write command and a command response time for a next ascending order write command;
generating performance evaluation data of the nonvolatile semiconductor memory further based on the extracted access direction switching processing time;
A performance evaluation device for non-volatile semiconductor memories. the host controller estimates a maximum command response time of the non-volatile semiconductor memory by adding up a maximum command response time for the write commands in the ascending order and a maximum command response time for the write commands in the descending order, the maximum command response time including the access direction switching processing time;
2. The performance evaluation apparatus for a nonvolatile semiconductor memory according to claim 1 . The non-volatile semiconductor memory is an SD memory card.
3. A performance evaluation apparatus for a nonvolatile semiconductor memory according to claim 1 .

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