JP7689293B2 - Abnormal condition detection circuit and electrical equipment - Google Patents

Description

This disclosure relates to an abnormal condition detection circuit and an electrical device.

Patent Document 1 discloses an AC/DC converter used in electrical equipment such as air conditioners. The AC/DC converter disclosed in Patent Document 1 includes first and second rectifiers connected in parallel to an AC power source via a reactor, two capacitors connected in series between the output terminals of the first rectifier to a DC load, two switching elements connected in series between the output terminals of the second rectifier, the connection point of which is connected to the connection point of the two capacitors, and a control unit that determines whether the two switching elements have a fault based on the voltages across the two capacitors when boost control is being performed, and when it is determined that one of the two switching elements has a fault, turns off the two switching elements to stop the boost control and stop the DC load. The control unit is realized by a microcomputer.

JP 2015-70644 A

Patent Document 1 uses an abnormal state of a capacitor series circuit to determine whether two switching elements have a fault. This fault determination is performed by a control unit, which is a microcomputer. The fault determination is realized by software processing, and it may take some time for the fault determination result to be obtained. Furthermore, if the microcomputer goes out of control, it may become impossible to perform the fault determination itself, and circuit operation may not be stopped normally even when an abnormality occurs.

This disclosure provides an abnormal condition detection circuit and electrical equipment that enables faster and more stable response to the detection of an abnormal condition in a capacitor series circuit.

The abnormal state detection circuit according to one aspect of the present disclosure includes a first voltage detection circuit, a second voltage detection circuit, a voltage imbalance detection circuit, and an output circuit. The first voltage detection circuit detects a first voltage across both ends of a series circuit of two capacitors, and outputs a first detection voltage indicating the first voltage. The second voltage detection circuit detects a second voltage at a connection point between the two capacitors of the series circuit, and outputs a second detection voltage indicating the second voltage. The voltage imbalance detection circuit has a comparator. The comparator compares the difference between the first voltage indicated by the first detection voltage output from the first voltage detection circuit and the second voltage indicated by the second detection voltage output from the second voltage detection circuit with a predetermined judgment value. The output circuit outputs an abnormal state detection signal when the comparator of the voltage imbalance detection circuit determines that the difference is equal to or greater than the predetermined judgment value.

An electrical device according to one aspect of the present disclosure includes the abnormal state detection circuit described above, a series circuit of the two capacitors, a DC power supply circuit that outputs a predetermined DC voltage across the series circuit based on power from a power source, and a DC load that operates using the predetermined DC voltage.

Aspects of the present disclosure enable faster and more stable response to the detection of an abnormal state in a capacitor series circuit.

FIG. 1 is a circuit diagram of an example of the configuration of an electrical device including an abnormal state detection circuit according to an embodiment; FIG. 2 is a circuit diagram of a configuration example of a DC power supply circuit of the electric device of FIG. 1. FIG. 2 is a circuit diagram showing an example of the configuration of an abnormal state detection circuit for the electrical device shown in FIG. 2 is a graph showing a relationship between a difference between a first voltage across both ends of a series circuit of capacitors in the electric device of FIG. 1 and a second voltage at a connection point between the capacitors, and the second voltage. FIG. 2 is a timing diagram showing an example of the operation of the voltage imbalance detection circuit of the abnormal state detection circuit of FIG. FIG. 2 is a timing diagram showing an example of the operation of the overvoltage detection circuit of the abnormal state detection circuit of FIG.

Below, the embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed explanation than necessary may be omitted. For example, detailed explanation of already well-known matters or duplicate explanation of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily redundant and to facilitate understanding by those skilled in the art. Note that the inventor(s) provide the attached drawings and the following explanation so that those skilled in the art can fully understand this disclosure, and do not intend for them to limit the subject matter described in the claims.

In the circuit configuration of the present disclosure, "connected" includes not only direct connection by a connection terminal and/or wiring conductor, but also electrical connection via other circuit components. Also, "connected between A and B" means connected to both A and B between A and B.

1. Embodiment
1.1 Configuration
Fig. 1 is a block diagram of an example of the configuration of an electric device 1 according to an embodiment. The electric device 1 in Fig. 1 includes a DC load 11, a DC power supply circuit 12, a series circuit 13 of two capacitors C1 and C2, and a microcomputer 14.

The DC load 11 operates with a predetermined DC voltage. In the electric device 1 of FIG. 1, the predetermined DC voltage is output between both ends of the series circuit 13 by the DC power supply circuit 12. The DC load 11 has, for example, a mechanical structure that realizes a predetermined function in the electric device 1. The function realized by the DC load 11 mainly differs depending on the type of the electric device 1. In this embodiment, the electric device 1 is a heat pump type hot water heater. The heat pump type hot water heater has, for example, an air heat exchanger, a compressor, a water heat exchanger, and an expansion valve, and performs heating by transferring heat of the refrigerant to the circulating liquid of the hot water panel heater by water heat exchange. In the heat pump type hot water heater, the DC load 11 includes, for example, a compressor.

The DC power supply circuit 12 outputs a predetermined DC voltage between both ends of the series circuit 13 based on the power from the power supply 20. The power supply 20 is, for example, an AC power supply. Examples of AC power supplies include commercial AC power supplies such as three-phase AC power supplies. The DC power supply circuit 12 is configured to generate a DC voltage higher than the effective value of the commercial AC power supply (for example, 200 V) and output it to the series circuit 13 of the two capacitors C1 and C2.

Figure 2 is a circuit diagram of an example configuration of the DC power supply circuit 12. The DC power supply circuit 12 in Figure 2 has the functions of an AC-DC converter and a boost circuit, and functions as a power factor correction circuit. The DC power supply circuit 12 in Figure 2 has two diode bridges 121, 122, two switching elements 123, 124, four diodes 125a to 125d, and a coil 126.

A switching element 123 is connected between the positive terminal 121a and the negative terminal 121b of the diode bridge 121. The positive terminal 121a of the diode bridge 121 is connected to the high potential terminal of the series circuit 13 (the terminal of the capacitor C11 opposite the capacitor C12) via a diode 125a for a reverse current element. The negative terminal 121b of the diode bridge 121 is connected to the low potential terminal of the series circuit 13 (the terminal of the capacitor C12 opposite the capacitor C11) via a diode 125b for a reverse current element. The first AC terminal 121c of the diode bridge 121 is connected to the first terminal of the power source 20 via a coil 126. The second AC terminal 121d of the diode bridge 121 is connected to the connection point P1 of the capacitors C1 and C2.

A switching element 124 is connected between the positive terminal 122a and the negative terminal 122b of the diode bridge 122. The positive terminal 122a of the diode bridge 122 is connected to the high potential terminal of the series circuit 13 via a diode 125c for a reverse current element. The negative terminal 122b of the diode bridge 122 is connected to the low potential terminal of the series circuit 13 via a diode 125d for a reverse current element. The first AC terminal 122c of the diode bridge 122 is connected to the second terminal of the power source 20. The second AC terminal 122d of the diode bridge 122 is connected to the connection point P1 of the capacitors C1 and C2.

The operation of the DC power supply circuit 12 will be briefly described. In the first case where the potential of the first AC end 121c of the diode bridge 121 is higher than the potential of the first AC end 122c of the diode bridge 122, when the switching elements 123 and 124 are each in the on state, a current path is formed from the power supply 20 through the first AC end 121c, positive terminal 121a, switching element 123, negative terminal 121b, second AC end 121d of the diode bridge 121, the second AC end 122d, positive terminal 122a, switching element 124, negative terminal 122b, and first AC end 122c of the diode bridge 122. In this case, energy is stored in the coil 126. When the switching element 123 is in an ON state and the switching element 124 is in an OFF state, a current path is formed from the power source 20 through the first AC terminal 121c, the positive terminal 121a, the switching element 123, the negative terminal 121b, the second AC terminal 121d, the capacitor C2, the diode 125d, the negative terminal 122b, and the first AC terminal 122c of the diode bridge 122. In this case, energy is released from the coil 126, and the capacitor C2 is charged with the boosted voltage. When the switching element 123 is in an OFF state and the switching element 124 is in an ON state, a current path is formed from the power source 20 through the first AC terminal 121c, the positive terminal 121a, the diode 125a, the capacitor C1, the second AC terminal 122d, the positive terminal 122a, the switching element 124, the negative terminal 122b, and the first AC terminal 122c of the diode bridge 122. In this case, energy is released from the coil 126, and the capacitor C1 is charged with the boosted voltage. When the switching elements 123 and 124 are each in the off state, a current path is formed from the power source 20 through the first AC terminal 121c of the diode bridge 121, the positive terminal 121a, the diode 125a, the capacitors C1 and C2, the diode 125d, the negative terminal 122b of the diode bridge 122, and the first AC terminal 122c. In this case, energy is released from the coil 126, and the capacitors C1 and C2 are charged with the boosted voltage.

In the second case where the potential of the first AC end 121c of the diode bridge 121 is lower than the potential of the first AC end 122c of the diode bridge 122, when the switching elements 123 and 124 are each in the on state, a current path is formed from the power source 20 through the first AC end 122c, positive terminal 122a, switching element 124, negative terminal 122b, second AC end 122d of the diode bridge 122, second AC end 121d, positive terminal 121a, switching element 123, negative terminal 121b, and first AC end 121c of the diode bridge 121. In this case, energy is stored in the coil 126. When the switching element 123 is in an off state and the switching element 124 is in an on state, a current path is formed from the power source 20 through the first AC terminal 122c, the positive terminal 122a, the switching element 124, the negative terminal 122b, the second AC terminal 122d, the capacitor C2, the diode 125b, the negative terminal 121b, and the first AC terminal 121c of the diode bridge 121. In this case, energy is released from the coil 126, and the capacitor C2 is charged with the boosted voltage. When the switching element 123 is in an on state and the switching element 124 is in an off state, a current path is formed from the power source 20 through the first AC terminal 121c, the positive terminal 121a, the diode 125c, the capacitor C1, the second AC terminal 121d, the positive terminal 121a, the switching element 123, the negative terminal 121b, and the first AC terminal 121c of the diode bridge 122. In this case, energy is released from the coil 126, and the capacitor C1 is charged with the boosted voltage. When the switching elements 123 and 124 are each in the off state, a current path is formed from the power source 20 through the first AC terminal 122c of the diode bridge 122, the positive terminal 122a, the diode 125c, the capacitors C1 and C2, the diode 125b, the negative terminal 121b of the diode bridge 121, and the first AC terminal 121c. In this case, energy is released from the coil 126, and the capacitors C1 and C2 are charged with the boosted voltage.

In this way, the DC power supply circuit 12 outputs a predetermined DC voltage across the series circuit 13 by the switching operation of the switching elements 123 and 124. The switching operation of the switching elements 123 and 124 is controlled by the microcomputer 14.

The series circuit 13 in FIG. 1 has two capacitors C1 and C2 connected in series. In FIG. 1, the capacitor C2 is connected to ground. The two capacitors C1 and C2 are, for example, electrolytic capacitors. In this embodiment, the capacitances of the two capacitors C1 and C2 are equal to each other.

The microcomputer 14 in FIG. 1 is a control circuit that controls the operation of the electrical device 1. In particular, the microcomputer 14 controls the DC load 11 and the DC power supply circuit 12. The microcomputer 14 can be realized, for example, by one or more processors (microprocessors) and one or more memories. In other words, the one or more processors execute one or more programs stored in one or more memories to realize the function of controlling the operation of the electrical device 1. Here, the programs are pre-recorded in the memory of the microcomputer 14, but they may also be provided via a telecommunications line such as the Internet, or recorded on a non-transitory recording medium such as a memory card.

The electrical device 1 in FIG. 1 further includes an abnormal state detection circuit 10. The abnormal state detection circuit 10 is provided to detect an abnormal state of the series circuit 13 of the two capacitors C1 and C2.

Figure 3 is a circuit diagram of an example configuration of the abnormal state detection circuit 10. The abnormal state detection circuit 10 in Figure 3 includes a first voltage detection circuit 2, a second voltage detection circuit 3, a voltage imbalance detection circuit 4, an overvoltage detection circuit 5, and an output circuit 6.

The first voltage detection circuit 2 detects a first voltage V1 between both ends of a series circuit 13 of two capacitors C1 and C2, and outputs a first detection voltage indicating the first voltage V1. The first voltage detection circuit 2 is a voltage divider circuit connected in parallel to the series circuit 13, and generates a voltage proportional to the first voltage V1. In FIG. 3, the first voltage detection circuit 2 is composed of a series circuit of three resistors R21, R22, and R23. The first voltage detection circuit 2 outputs the voltage at the connection point between the resistors R22 and R23 as the first detection voltage.

The second voltage detection circuit 3 detects the second voltage V2 at the connection point P1 of the two capacitors C1 and C2 of the series circuit 13, and outputs a second detection voltage indicating the second voltage V2. The second voltage detection circuit 3 is a voltage divider circuit connected in parallel to the capacitor C2 of the series circuit 13, and generates a voltage proportional to the second voltage V2. In FIG. 3, the second voltage detection circuit 3 is composed of a series circuit of two resistors R31 and R32. The second voltage detection circuit 3 outputs the voltage at the connection point between the resistors R21 and R32 as the second detection voltage.

The voltage imbalance detection circuit 4 is provided to detect an abnormal state of the series circuit 13 of the capacitors C1 and C2 based on whether the voltages of the capacitors C1 and C2 are unbalanced. When the voltage across the capacitor C2 drops due to an abnormality such as a short circuit of the capacitor C2, it is considered that an imbalance in the voltages of the two capacitors C1 and C2 has occurred. However, the voltage across the capacitor C2 may also drop when the predetermined DC voltage output from the DC power supply circuit 12 to the series circuit 13 drops. Therefore, the voltage imbalance detection circuit 4 uses the difference between the first voltage V1 indicated by the first detection voltage output from the first voltage detection circuit 2 and the second voltage V2 indicated by the second detection voltage output from the second voltage detection circuit 3 to determine whether an imbalance in the voltages of the two capacitors C1 and C2 has occurred.

Figure 4 is a graph showing the relationship between the difference between the first voltage V1 across the series circuit 13 of the capacitors C1 and C2 and the second voltage V2 at the connection point P1 between the capacitors C1 and C2, and the second voltage V2. In Figure 4, G1 is a graph when the voltage across the capacitor C1 is at a minimum value. G2 is a graph when the voltage across the capacitor C1 is at a representative value. G3 is a graph when the voltage across the capacitor C1 is at a maximum value. As is clear from the graph in Figure 4, when the second voltage V2 decreases, the difference between the first voltage V1 and the second voltage V2 increases. Whether the second voltage V2 has decreased by a predetermined value or more can be detected depending on whether the difference between the first voltage V1 and the second voltage V2 has become a predetermined judgment value or more.

The voltage imbalance detection circuit 4 has a comparator 41. The comparator 41 is provided to compare the difference between the first voltage V1 indicated by the first detection voltage output from the first voltage detection circuit 2 and the second voltage V2 indicated by the second detection voltage output from the second voltage detection circuit 3 with a predetermined judgment value. The magnitude of the predetermined judgment value is appropriately set to determine whether or not a voltage imbalance has occurred between the capacitors C1 and C2. As an example, when the predetermined DC voltage output from the DC power supply circuit 12 to the series circuit 13 is 600 V, if the series circuit 13 is not in an abnormal state, the difference between the first voltage V1 and the second voltage V2 will be about 300 V. In this example, the predetermined judgment value may be set to, for example, 400 V.

The comparator 41 outputs a high-level signal from the output terminal when the voltage input to the non-inverting input terminal is equal to or greater than the voltage input to the inverting input terminal. The comparator 41 outputs a low-level signal from the output terminal when the voltage input to the non-inverting input terminal is less than the voltage input to the inverting input terminal. In FIG. 3, the non-inverting input terminal of the comparator 41 is connected to the connection point of the resistors R22 and R23 of the first voltage detection circuit 2 via a resistor R41. The inverting input terminal of the comparator 41 is connected to the connection point of the resistors R31 and R32 of the second voltage detection circuit 3 via a resistor R42. The inverting input terminal of the comparator 41 is connected to a series circuit of resistors R43 and R44 connected between the internal power supply Vcc and ground. More specifically, the inverting input terminal of the comparator 41 is connected to the connection point of the resistors R43 and R44 via a resistor R45. In the series circuit of resistors R43, R45, R42, and R32, the potential at the connection point between resistors R44 and R42 is input to the inverting input terminal of the comparator 41. Therefore, a voltage that is greater than the second detection voltage (the voltage at the connection point between resistors R31 and R32) by the voltage across resistor R42 is input to the inverting input terminal of the comparator 41. The resistance values of resistors R42 to R45 are set so that the voltage across resistor R42 becomes a voltage corresponding to a predetermined judgment value. As a result, the first detection voltage output from the first voltage detection circuit 2 is input to the non-inverting input terminal of the comparator 41. A voltage obtained by adding a voltage corresponding to a predetermined judgment value to the second detection voltage output from the second voltage detection circuit 3 is input to the inverting input terminal of the comparator 41. Here, assuming that the magnitude of the first voltage V1 is v1, the magnitude of the second voltage V2 is v2, and the predetermined judgment value is vd, the comparator 41 judges whether v1 ≧ v2 + vd is satisfied, that is, whether v1-v2 ≧ vd is satisfied. In other words, the comparator 41 compares the difference between the first voltage V1 and the second voltage V2 with the predetermined judgment value. A feedback resistor R46 is connected between the non-inverting input terminal and the output terminal of the comparator 41. A pull-up resistor R47 is connected between the output terminal of the comparator 41 and the internal power supply Vcc.

Figure 5 is a timing diagram showing an example of the operation of the voltage imbalance detection circuit 4. In Figure 5, V11 indicates the voltage at the non-inverting input terminal of the comparator 41. The voltage input to the non-inverting input terminal of the comparator 41 corresponds to the first voltage V1 detected by the first voltage detection circuit 2. In Figure 5, V12 indicates the voltage at the inverting input terminal of the comparator 41. The voltage input to the inverting input terminal of the comparator 41 corresponds to the voltage obtained by adding a voltage corresponding to a predetermined judgment value to the second voltage V2 detected by the second voltage detection circuit 3. In Figure 5, V13 indicates the voltage at the output terminal of the comparator 41.

In FIG. 5, from time t10 to time t11, the series circuit 13 of the capacitors C1 and C2 is not in an abnormal state. In this case, the difference between the first voltage V1 and the second voltage V2 is less than a predetermined judgment value. Therefore, the voltage V11 at the non-inverting input terminal of the comparator 41 is smaller than the voltage V12 at the inverting input terminal of the comparator 41. As a result, the voltage V13 at the output terminal of the comparator 41 becomes L (low level), and a low-level signal is output from the comparator 41. In FIG. 5, it is assumed that at time t11, the capacitor C2 is short-circuited, and the series circuit 13 of the capacitors C1 and C2 becomes in an abnormal state. In this case, after time t11, the difference between the first voltage V1 and the second voltage V2 becomes equal to or greater than the predetermined judgment value. As a result, the voltage V11 at the non-inverting input terminal of the comparator 41 becomes equal to or greater than the voltage V12 at the inverting input terminal of the comparator 41. Therefore, the voltage V13 at the output terminal of the comparator 41 becomes H (high level), and a high level signal is output from the comparator 41. In this way, in the voltage imbalance detection circuit 4, if the series circuit 13 of the capacitors C1 and C2 is in an abnormal state, the comparator 41 outputs a high level signal, and if the series circuit 13 of the capacitors C1 and C2 is not in an abnormal state, the comparator 41 outputs a low level signal.

The overvoltage detection circuit 5 is provided to detect an abnormal state of the series circuit 13 of the capacitors C1 and C2 based on whether the voltage at the connection point P1 between the capacitors C1 and C2 has risen excessively. The state in which the voltage at the connection point P1 between the capacitors C1 and C2 has risen excessively is, for example, a state in which an excessive voltage is applied to the capacitor C2 due to an abnormality such as a short circuit of the capacitor C1. The overvoltage detection circuit 5 has a comparator 51. The comparator 51 is provided to compare the second voltage V2 indicated by the second detection voltage output from the second voltage detection circuit 3 with a predetermined threshold voltage. The magnitude of the predetermined threshold voltage is appropriately set to determine whether an excessive rise in the voltage at the connection point P1 has occurred. As an example, when the predetermined DC voltage output from the DC power supply circuit 12 to the series circuit 13 is 600V, if the series circuit 13 is not in an abnormal state, the second voltage V2 will be about 300V. In this example, the predetermined threshold voltage may be set to, for example, 400V.

3, the non-inverting input terminal of the comparator 51 is connected to a series circuit of resistors R51 and R52 connected between the internal power supply Vcc and ground. More specifically, the non-inverting input terminal of the comparator 51 is connected to the connection point of the resistors R51 and R52. The resistance values of the resistors R51 and 52 are set so that the voltage at the connection point of the resistors R51 and R52 corresponds to a predetermined threshold voltage. The inverting input terminal of the comparator 51 is connected to the connection point of the resistors R31 and R32 of the second voltage detection circuit 3. As a result, a voltage corresponding to a predetermined threshold voltage is input to the non-inverting input terminal of the comparator 51. The second detection voltage output from the second voltage detection circuit 3 is input to the inverting input terminal of the comparator 51. A feedback resistor R53 is connected between the non-inverting input terminal and the output terminal of the comparator 51.

The comparator 51 outputs a high-level signal from the output terminal when the voltage input to the non-inverting input terminal is equal to or greater than the voltage input to the inverting input terminal. The comparator 51 outputs a low-level signal from the output terminal when the voltage input to the non-inverting input terminal is less than the voltage input to the inverting input terminal. In the case of FIG. 3, the voltage input to the non-inverting input terminal of the comparator 51 corresponds to a predetermined threshold voltage. The voltage input to the inverting input terminal of the comparator 51 corresponds to the second voltage V2 detected by the second voltage detection circuit 3. Therefore, the comparator 51 compares the second voltage V2 with the predetermined threshold voltage.

Figure 6 is a timing diagram showing an example of the operation of the overvoltage detection circuit 5. In Figure 6, V21 indicates the voltage at the non-inverting input terminal of the comparator 51. The voltage input to the non-inverting input terminal of the comparator 51 corresponds to a predetermined threshold voltage. In Figure 6, V22 indicates the voltage at the inverting input terminal of the comparator 51. The voltage input to the inverting input terminal of the comparator 51 corresponds to the second voltage V2 detected by the second voltage detection circuit 3. In Figure 6, V23 indicates the voltage at the output terminal of the comparator 51.

6, the series circuit 13 of the capacitors C1 and C2 is not in an abnormal state from time t20 to time t21. In this case, the second voltage V2 is less than a predetermined threshold voltage. Therefore, the voltage V21 of the non-inverting input terminal of the comparator 51 is greater than the voltage V22 of the inverting input terminal of the comparator 51. As a result, the voltage V23 of the output terminal of the comparator 51 becomes H (high level), and a high level signal is output from the comparator 51. In FIG. 6, it is assumed that at time t21, the capacitor C1 is short-circuited, and the series circuit 13 of the capacitors C1 and C2 becomes abnormal. In this case, after time t21, the second voltage V2 becomes equal to or greater than a predetermined threshold voltage. As a result, the voltage V21 of the non-inverting input terminal of the comparator 51 becomes equal to or less than the voltage V22 of the inverting input terminal of the comparator 51. Therefore, the voltage V23 of the output terminal of the comparator 51 becomes L (low level), and a low level signal is output from the comparator 51. Thus, in the overvoltage detection circuit 5, if the series circuit 13 of the capacitors C1 and C2 is in an abnormal state, the comparator 51 outputs a low-level signal, and if the series circuit 13 of the capacitors C1 and C2 is not in an abnormal state, the comparator 51 outputs a high-level signal.

In the overvoltage detection circuit 5 of FIG. 3, when the second voltage V2 is equal to or greater than a predetermined threshold voltage, a low-level signal is output from the comparator 51. In the overvoltage detection circuit 5 of FIG. 3, when the second voltage V2 is less than the predetermined threshold voltage, a high-level signal is output from the comparator 51. In other words, when the series circuit 13 of the capacitors C1 and C2 is in an abnormal state, a low-level signal is output from the comparator 51, and when the series circuit 13 of the capacitors C1 and C2 is not in an abnormal state, a high-level signal is output from the comparator 51.

The output circuit 6 outputs the result of detection of an abnormal state of the series circuit 13 of the capacitors C1 and C2. In this embodiment, the output circuit 6 outputs an abnormal state detection signal S1 when the comparator 41 of the voltage imbalance detection circuit 4 determines that the difference between the first voltage indicated by the first detection voltage output from the first voltage detection circuit 2 and the second voltage indicated by the second detection voltage output from the second voltage detection circuit 3 is equal to or greater than a predetermined judgment value. The output circuit 6 outputs an abnormal state detection signal S1 when the comparator 51 of the overvoltage detection circuit 5 determines that the second voltage indicated by the second detection voltage output from the second voltage detection circuit 3 is equal to or greater than a predetermined threshold voltage.

The output circuit 6 in FIG. 3 includes a switch 61 and a latch circuit 62.

The switch 61 has a first terminal, a second terminal, and a control terminal. The switch 61 switches between an on state in which the first terminal and the second terminal are electrically connected and an off state in which the first terminal and the second terminal are not electrically connected, depending on the voltage input to the control terminal. The switch 61 is, for example, a semiconductor switch. In this embodiment, the switch 61 is an NPN transistor. The first terminal, the second terminal, and the control terminal of the switch 61 correspond to the collector, the emitter, and the base of the NPN transistor, respectively. In FIG. 3, the first terminal of the switch 61 is connected to the output terminal of the comparator 51 of the overvoltage detection circuit 5. The first terminal of the switch 61 is connected to the internal power supply Vcc via a pull-up resistor R61. The second terminal of the switch 61 is connected to ground. The control terminal of the switch 61 is connected to the output terminal of the comparator 41 of the voltage imbalance detection circuit 4.

The switch 61 is in an off state while a low-level output signal is being output from the comparator 41 of the voltage imbalance detection circuit 4. In other words, when the voltage imbalance detection circuit 4 does not detect an abnormal state of the series circuit 13, the switch 61 is in an off state, and the first terminal of the switch 61 is not connected to ground. In this case, the voltage of the first terminal of the switch 61 is determined by the voltage of the output terminal of the comparator 51 of the overvoltage detection circuit 5. When the voltage imbalance detection circuit 4 does not detect an abnormal state of the series circuit 13, the signal output from the output terminal of the comparator 51 of the overvoltage detection circuit 5 is at a high level, so that the voltage of the first terminal of the switch 61 is at a high level. When the voltage imbalance detection circuit 4 detects an abnormal state of the series circuit 13, the signal output from the output terminal of the comparator 51 of the overvoltage detection circuit 5 is at a low level, so that the voltage of the first terminal of the switch 61 is at a low level. Therefore, if the voltage imbalance detection circuit 4 does not detect an abnormal state of the series circuit 13, the output circuit 6 outputs a low-level signal output from the output terminal of the comparator 51 of the overvoltage detection circuit 5 as the abnormal state detection signal S1.

The switch 61 is in the on state while a high-level output signal is being output from the comparator 41 of the voltage imbalance detection circuit 4. In other words, when the voltage imbalance detection circuit 4 does not detect an abnormal state of the series circuit 13, the switch 61 is in the on state, and the first terminal of the switch 61 is connected to ground. In this case, the voltage of the first terminal of the switch 61 becomes low level. Therefore, when the voltage imbalance detection circuit 4 detects an abnormal state of the series circuit 13, the output circuit 6 outputs a low-level signal as the abnormal state detection signal S1.

The abnormal state detection signal S1 output from the output circuit 6 is a low-level signal regardless of whether an abnormal state of the series circuit 13 is detected by the voltage imbalance detection circuit 4 or an abnormal state of the series circuit 13 is detected by the overvoltage detection circuit 5.

The latch circuit 62 is provided to maintain the output of the abnormal state detection signal S1. The latch circuit 62 in FIG. 3 has first to fourth NAND circuits 62a, 62b, 62c, and 62d. The first input terminal of the first NAND circuit 62a is connected to the first terminal of the switch 61 via a resistor R62. The output terminal of the first NAND circuit 62a is connected to the first input terminal of the second NAND circuit 62b. The output terminal of the second NAND circuit 62b is connected to the second input terminal of the first NAND circuit 62a and the first input terminal of the fourth NAND circuit 62d. The first and second input terminals of the third NAND circuit 62c are connected to the internal power supply Vcc via resistors R63 and R64. The connection point of the resistors R63 and R64 is connected to the microcomputer 14. The output terminal of the third NAND circuit 62c is connected to the second input terminal of the second NAND circuit 62b and the second input terminal of the fourth NAND circuit 62d. In the latch circuit 62, the first input terminal of the first NAND circuit 62a is the set terminal of the latch circuit 62. The first and second input terminals of the third NAND circuit 62c are the reset terminal of the latch circuit 62. The output terminal of the fourth NAND circuit 62d is the output terminal of the latch circuit 62.

A low-level signal is normally input from the microcomputer 14 to the reset terminal of the latch circuit 62. When a low-level signal is input to the set terminal of the latch circuit 62 in this state, a low-level signal is output from the output terminal of the latch circuit 62. The low-level signal from the latch circuit 62 is used as the abnormal condition detection signal S1. Even if a high-level signal is subsequently input to the set terminal of the latch circuit 62, the state in which a low-level signal is output from the output terminal of the latch circuit 62, that is, the state in which the abnormal condition detection signal S1 is output, is maintained. When a high-level signal is input from the microcomputer 14 to the reset terminal of the latch circuit 62, the latch circuit 62 is reset and the output of the abnormal condition detection signal S1 is stopped.

As shown in FIG. 3, the output circuit 6 outputs an abnormal state detection signal S1 to the DC power supply circuit 12 and the microcomputer 14. In FIG. 3, a first terminal of a switch 61 of the output circuit 6 is connected to the microcomputer 14. An output terminal of a latch circuit 62 of the output circuit 6 is connected to the microcomputer 14 and the DC power supply circuit 12.

The DC power supply circuit 12 is configured to stop operation of the DC power supply circuit 12 when it receives the abnormal state detection signal S1 from the output circuit 6 of the abnormal state detection circuit 10. In other words, even if the microcomputer 14 does not control the DC power supply circuit 12, the DC power supply circuit 12 stops operation by receiving the abnormal state detection signal S1. This allows the DC power supply circuit 12 to stop operation in response to an abnormal state of the series circuit 13 of the capacitors C1 and C2 even if the microcomputer 14 fails.

When the microcomputer 14 receives the abnormal state detection signal S1 from the output circuit 6 of the abnormal state detection circuit 10, it executes an operation to deal with the abnormal state. In particular, in this embodiment, when the microcomputer 14 receives the abnormal state detection signal S1 from the first end of the switch 61 of the output circuit 6 of the abnormal state detection circuit 10, it executes an operation to deal with the abnormal state. Examples of the operation to deal with the abnormal state include an operation to notify an external circuit that an abnormal state has occurred, an operation to stop the DC load 11, and an operation of the microcomputer 14 to stop its own operation. The microcomputer 14 can confirm the latch state of the latch circuit 62 based on the presence or absence of the abnormal state detection signal S1 from the output terminal of the latch circuit 62 of the output circuit 6. When the abnormal state of the series circuit 13 of the capacitors C1 and C2 is resolved, the microcomputer 14 outputs a high-level signal to the reset terminal of the latch circuit 62 to reset the latch circuit 62.

In the electrical device 1 of FIG. 1, the abnormal state detection circuit 10 detects the abnormal state of the capacitors C1 and C2 of the series circuit 13. The abnormal state detection circuit 10 detects the abnormal state of the capacitors C1 and C2 without using the microcomputer 14, using the circuit composed of the comparator 41 of the voltage imbalance detection circuit 4, the comparator 51 of the overvoltage detection circuit 5, and the switch 61 and latch circuit 62 of the output circuit 6. In other words, the abnormal state detection circuit 10 determines the occurrence of an abnormal state not by software processing in the microcomputer 14, but by hardware processing using a circuit including the comparators 41 and 51. Therefore, compared to the case where the microcomputer 14 is used, the time required from the detection of the abnormal state to the response to the abnormal state (for example, the stop of the operation of the DC power supply circuit 12, etc.) can be shortened. This enables the response to the detection of the abnormal state of the series circuit 13 of the capacitors C1 and C2 to be accelerated. Therefore, it is possible to prevent the destruction of the circuit components of the electrical device 1. Furthermore, since the abnormal state detection circuit 10 does not use the microcomputer 14, the abnormal state detection is not prevented from being impossible due to the microcomputer going out of control. This makes it possible to improve the stability of the abnormal state detection operation of the series circuit 13 of the capacitors C1 and C2. In particular, in the electrical device 1, the abnormal state detection signal S1 from the abnormal state detection circuit 10 is input to the DC power supply circuit 12 without passing through the microcomputer 14, so that even if the microcomputer 14 goes out of control and does not operate normally, the operation of the DC power supply circuit 12 can be stopped.

[1.2 Effects, etc.]
As described above, the abnormal state detection circuit 10 includes the first voltage detection circuit 2 that detects the first voltage V1 across the series circuit 13 of the two capacitors C1 and C2 and outputs a first detection voltage indicating the first voltage V1, the second voltage detection circuit 3 that detects the second voltage V2 at the connection point P1 between the two capacitors C1 and C2 of the series circuit 13 and outputs a second detection voltage indicating the second voltage V2, the voltage unbalance detection circuit 4 having a comparator 41 that compares the difference between the first voltage V1 indicated by the first detection voltage output from the first voltage detection circuit 2 and the second voltage V2 indicated by the second detection voltage output from the second voltage detection circuit 3 with a predetermined judgment value, and the output circuit 6 that outputs an abnormal state detection signal S1 when the comparator 41 of the voltage unbalance detection circuit 4 judges that the difference is equal to or greater than the predetermined judgment value. This configuration enables faster response to detection of an abnormal state of the series circuit 13 of the capacitors C1 and C2 and improved stability of the detection operation.

In the abnormal state detection circuit 10, the first detection voltage output from the first voltage detection circuit 2 is input to the non-inverting input terminal of the comparator 41 of the voltage imbalance detection circuit 4. A voltage obtained by adding a voltage corresponding to a predetermined judgment value to the second detection voltage output from the second voltage detection circuit 3 is input to the inverting input terminal of the comparator 41 of the voltage imbalance detection circuit 4. This configuration makes it possible to simplify the circuit configuration of the abnormal state detection circuit 10.

The abnormal state detection circuit 10 further includes an overvoltage detection circuit 5 having a comparator 51 that compares the second voltage V2 indicated by the second detection voltage output from the second voltage detection circuit 3 with a predetermined threshold voltage. The output circuit 6 is configured to output an abnormal state detection signal S1 when the comparator 51 of the overvoltage detection circuit 5 determines that the second voltage V2 is equal to or greater than the predetermined threshold voltage. This configuration can detect an excessive increase in the voltage at the connection point between the capacitors C1 and C2 as an abnormal state of the series circuit 13 of the capacitors C1 and C2.

In the abnormal state detection circuit 10, the second detection voltage output from the second voltage detection circuit 3 is input to the inverting input terminal of the comparator 51 of the overvoltage detection circuit 5. A voltage corresponding to a predetermined threshold voltage is input to the non-inverting input terminal of the comparator 51 of the overvoltage detection circuit 5. This configuration allows the circuit configuration of the abnormal state detection circuit 10 to be simplified.

In the abnormal state detection circuit 10, the output circuit 6 has a switch 61. The switch 61 has a first terminal connected to the output terminal of the comparator 51 of the overvoltage detection circuit 5, a second terminal connected to ground, and a control terminal connected to the output terminal of the comparator 41 of the voltage imbalance detection circuit 4. The switch 61 switches between an off state in which there is no conduction between the first terminal and the second terminal and an on state in which there is conduction between the first terminal and the second terminal according to the voltage input to the control terminal. The output circuit 6 is in an off state while the signal output from the output terminal of the comparator 41 of the voltage imbalance detection circuit 4 is at a low level, and outputs a low-level signal output from the output terminal of the comparator 51 of the overvoltage detection circuit 5 as the abnormal state detection signal S1. The output circuit 6 is in an on state while the signal output from the output terminal of the comparator 41 of the voltage imbalance detection circuit 4 is at a high level, and outputs a low-level signal as the abnormal state detection signal S1. This configuration allows for a simplification of the circuit configuration of the abnormal state detection circuit 10.

In the abnormal state detection circuit 10, the output circuit 6 further includes a latch circuit 62 that maintains the output of the abnormal state detection signal S1. This configuration can improve the reliability of notification that the series circuit 13 of the capacitors C1 and C2 is in an abnormal state.

The electrical device 1 described above includes an abnormal state detection circuit 10, a series circuit 13 of two capacitors C1 and C2, a DC power supply circuit 12 that outputs a predetermined DC voltage across the series circuit 13 based on power from a power source 20, and a DC load 11 that operates on the predetermined DC voltage. This configuration enables faster response to detection of an abnormal state in the series circuit 13 of the capacitors C1 and C2 and improved stability of the detection operation.

In the electrical device 1, the DC power supply circuit 12 is configured to stop operation of the DC power supply circuit 12 when it receives an abnormal state detection signal S1 from the output circuit 6 of the abnormal state detection circuit 10. When the microcomputer 14 receives the abnormal state detection signal S1 from the output circuit 6 of the abnormal state detection circuit 10, it executes an operation to deal with the abnormal state. This configuration enables faster response to detection of an abnormal state of the series circuit 13 of the capacitors C1 and C2 and improved stability of the detection operation.

2. Modifications
The embodiments of the present disclosure are not limited to the above-mentioned embodiments. The above-mentioned embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved. Below, modified examples of the above-mentioned embodiments are listed. The modified examples described below can be applied in appropriate combination.

In one modified example, the first voltage detection circuit 2 and the second voltage detection circuit 3 may have a configuration different from that of the above embodiment. The configurations of the first voltage detection circuit 2 and the second voltage detection circuit 3 may be conventionally known configurations.

In one modified example, the voltage imbalance detection circuit 4 may have a configuration different from that of the above embodiment. The voltage imbalance detection circuit 4 may output a low-level signal to the output circuit 6 instead of a high-level signal when an abnormal state is detected. Whether a high-level signal or a low-level signal is used as a signal indicating an abnormal state of the series circuit 13 of the capacitors C1 and C2 may be appropriately determined depending on the configuration of the output circuit 6, etc.

In one modified example, the overvoltage detection circuit 5 may have a configuration different from that of the above embodiment. The overvoltage detection circuit 5 may output a high-level signal to the output circuit 6 instead of a low-level signal when an abnormal state is detected. Whether a high-level signal or a low-level signal is used as the signal indicating an abnormal state of the series circuit 13 of the capacitors C1 and C2 may be appropriately determined depending on the configuration of the output circuit 6, etc. The abnormal state detection circuit 10 may not have an overvoltage detection circuit 5.

In one modified example, the output circuit 6 may have a configuration different from that of the above embodiment. The output circuit 6 does not need to output the same abnormal state detection signal S1 when the voltage imbalance detection circuit 4 detects an abnormal state and when the overvoltage detection circuit 5 detects an abnormal state. The output circuit 6 may output the abnormal state detection signal S1 separately when the voltage imbalance detection circuit 4 detects an abnormal state and when the overvoltage detection circuit 5 detects an abnormal state. If the abnormal state detection circuit 10 does not have the overvoltage detection circuit 5, the output circuit 6 may not have the switch 61. The output circuit 6 may not have the latch circuit 62. The output circuit 6 may be a terminal or wiring for inputting the output from the voltage imbalance detection circuit 4 to an external circuit. In other words, the output circuit 6 does not necessarily have an active element.

In one modified example, the electric device 1 is not limited to a heat pump type hot water heater. Examples of the electric device 1 include sensor-related devices, air conditioning-related devices, housing and equipment-related devices, cooking and housekeeping-related devices, health management-related devices, management and operation-related devices, and AV-related devices. Examples of sensor-related devices include fire sensors, human body detection sensors, temperature sensors, _CO2 sensors, and current sensors. Examples of air conditioning-related devices include air conditioners, electric fans, ventilation fans, air purifiers, hot carpets, oil fan heaters, and heat pump type hot water heaters. Examples of housing and equipment-related devices include electric blinds, electric curtains, water heaters, electric locks, smart meters, solar power generation equipment, storage batteries, fuel cells, general lighting, single-function lighting, and emergency lights. Examples of cooking and housekeeping-related devices include microwave ovens, dishwashers, dish dryers, washing machines, clothes dryers, and automatic vacuum cleaners. Examples of health management-related devices include weight scales, body fat scales, thermometers, blood pressure gauges, and blood glucose meters. Examples of management/operation related devices include controllers and switches (HA devices), and examples of AV related devices include TVs and displays.

3. Aspects
As is clear from the above-mentioned embodiment and modified examples, the present disclosure includes the following aspects. In the following, symbols are given in parentheses only to clarify the correspondence with the embodiment. Note that, in consideration of the readability of the text, the description of symbols in parentheses from the second time onwards may be omitted.

The first aspect is an abnormal state detection circuit (10) comprising: a first voltage detection circuit (2) that detects a first voltage (V1) between both ends of a series circuit (13) of two capacitors (C1, C2) and outputs a first detection voltage indicative of the first voltage (V1); a second voltage detection circuit (3) that detects a second voltage (V2) at a connection point (P1) between the two capacitors (C1, C2) of the series circuit (13) and outputs a second detection voltage indicative of the second voltage (V2); a voltage imbalance detection circuit (4) having a comparator (41) that compares a difference between a first voltage (V1) indicated by the first detection voltage output from the first voltage detection circuit (2) and a second voltage (V2) indicated by the second detection voltage output from the second voltage detection circuit (3) with a predetermined judgment value; and an output circuit (6) that outputs an abnormal state detection signal (S1) when the comparator (41) of the voltage imbalance detection circuit (4) determines that the difference is equal to or greater than the predetermined judgment value. This aspect enables faster response to detection of an abnormal state in the series circuit (13) of capacitors (C1, C2) and improved stability of the detection operation.

The second aspect is an abnormal state detection circuit (10) based on the first aspect. In the second aspect, the first detection voltage output from the first voltage detection circuit (2) is input to the non-inverting input terminal of the comparator (41) of the voltage imbalance detection circuit (4). A voltage obtained by adding a voltage corresponding to the predetermined judgment value to the second detection voltage output from the second voltage detection circuit (3) is input to the inverting input terminal of the comparator (41) of the voltage imbalance detection circuit (4). This aspect makes it possible to simplify the circuit configuration of the abnormal state detection circuit (10).

The third aspect is an abnormal state detection circuit (10) based on the first or second aspect. In the third aspect, the abnormal state detection circuit (10) further includes an overvoltage detection circuit (5) having a comparator (51) that compares a second voltage (V2) indicated by the second detection voltage output from the second voltage detection circuit (3) with a predetermined threshold voltage. The output circuit (6) is configured to output an abnormal state detection signal (S1) when the comparator (51) of the overvoltage detection circuit (5) determines that the second voltage (V2) is equal to or greater than the predetermined threshold voltage. This aspect can detect an excessive increase in the voltage at the connection point between the capacitors (C1, C2) as an abnormal state of the series circuit (13) of the capacitors (C1, C2).

The fourth aspect is an abnormal state detection circuit (10) based on the third aspect. In the fourth aspect, the second detection voltage output from the second voltage detection circuit (3) is input to the inverting input terminal of the comparator (51) of the overvoltage detection circuit (5). A voltage corresponding to the predetermined threshold voltage is input to the non-inverting input terminal of the comparator (51) of the overvoltage detection circuit (5). This aspect makes it possible to simplify the circuit configuration of the abnormal state detection circuit (10).

The fifth aspect is an abnormal state detection circuit (10) based on the third or fourth aspect. In the fifth aspect, the output circuit (6) has a switch (61). The switch (61) has a first terminal connected to the output terminal of the comparator (51) of the overvoltage detection circuit (5), a second terminal connected to ground, and a control terminal connected to the output terminal of the comparator (41) of the voltage imbalance detection circuit (4). The switch (61) switches between an off state in which there is no conduction between the first terminal and the second terminal and an on state in which there is conduction between the first terminal and the second terminal, depending on the voltage input to the control terminal. The output circuit (6) outputs a low-level signal output from the output terminal of the comparator (41) of the voltage imbalance detection circuit (4) as the abnormal state detection signal (S1) while the switch (61) is in an off state and outputs a low-level signal output from the output terminal of the comparator (51) of the overvoltage detection circuit (5) as the abnormal state detection signal (S1) while the signal output from the output terminal of the comparator (41) of the voltage imbalance detection circuit (4) is at a high level, and the output circuit (6) outputs a low-level signal as the abnormal state detection signal (S1). This aspect makes it possible to simplify the circuit configuration of the abnormal state detection circuit (10).

The sixth aspect is an abnormal state detection circuit (10) based on the fifth aspect. In the sixth aspect, the output circuit (6) further includes a latch circuit (62) that maintains the output of the abnormal state detection signal (S1). This aspect can improve the reliability of notification that the series circuit (13) of the capacitors (C1, C2) is in an abnormal state.

The seventh aspect is an electrical device (1) that includes an abnormal state detection circuit (10) based on any one of the first to sixth aspects, a series circuit (13) of the two capacitors (C1, C2), a DC power supply circuit (12) that outputs a predetermined DC voltage between both ends of the series circuit (13) based on power from a power source (20), and a DC load (11) that operates on the predetermined DC voltage. This aspect enables faster response to detection of an abnormal state in the series circuit (13) of the capacitors (C1, C2) and improved stability of the detection operation.

The eighth aspect is an electric device (1) based on the seventh aspect. In the eighth aspect, the DC power supply circuit (12) is configured to stop operation of the DC power supply circuit (12) when it receives the abnormal state detection signal (S1) from the output circuit (6) of the abnormal state detection circuit (10). The microcomputer (14) executes an operation to deal with the abnormal state when it receives the abnormal state detection signal (S1) from the output circuit (6) of the abnormal state detection circuit (10). This aspect enables faster response to detection of an abnormal state of the series circuit (13) of capacitors (C1, C2) and improved stability of the detection operation.

The above second to sixth and eighth aspects are not essential.

The present disclosure is applicable to an abnormal state detection circuit and an electrical device. Specifically, the present disclosure is applicable to an abnormal state detection circuit for detecting an abnormal state of a capacitor series circuit and an electrical device equipped with an abnormal state detection circuit.

REFERENCE SIGNS LIST 1 Electrical equipment 10 Abnormal state detection circuit 2 First voltage detection circuit 3 Second voltage detection circuit 4 Voltage imbalance detection circuit 41 Comparator 5 Overvoltage detection circuit 51 Comparator 6 Output circuit 61 Switch 62 Latch circuit 11 DC load 12 DC power supply circuit 13 Series circuit C1, C2 Capacitor P1 Connection point 14 Microcomputer V1 First voltage V2 Second voltage S1 Abnormal state detection signal

Claims (7)

a first voltage detection circuit that detects a first voltage across a series circuit of two capacitors and outputs a first detection voltage indicative of the first voltage;
a second voltage detection circuit that detects a second voltage at a connection point between the two capacitors of the series circuit and outputs a second detection voltage indicative of the second voltage;
a voltage imbalance detection circuit having a comparator that compares a difference between a first voltage indicated by a first detection voltage output from the first voltage detection circuit and a second voltage indicated by a second detection voltage output from the second voltage detection circuit with a predetermined judgment value;
an output circuit that outputs an abnormal state detection signal when a comparator of the voltage imbalance detection circuit determines that the difference is equal to or greater than the predetermined determination value;
Equipped with
a first detection voltage output from the first voltage detection circuit is input to a non-inverting input terminal of a comparator of the voltage imbalance detection circuit;
a voltage obtained by adding a voltage corresponding to the predetermined determination value to the second detection voltage output from the second voltage detection circuit is input to an inverting input terminal of a comparator of the voltage imbalance detection circuit;
Abnormal condition detection circuit. an overvoltage detection circuit having a comparator that compares a second voltage indicated by a second detection voltage output from the second voltage detection circuit with a predetermined threshold voltage;
the output circuit is configured to output an abnormal state detection signal when a comparator of the overvoltage detection circuit determines that the second voltage is equal to or higher than the predetermined threshold voltage.
2. The abnormal condition detection circuit of claim 1 . a first voltage detection circuit that detects a first voltage across a series circuit of two capacitors and outputs a first detection voltage indicative of the first voltage;
a second voltage detection circuit that detects a second voltage at a connection point between the two capacitors of the series circuit and outputs a second detection voltage indicative of the second voltage;
a voltage imbalance detection circuit having a comparator that compares a difference between a first voltage indicated by a first detection voltage output from the first voltage detection circuit and a second voltage indicated by a second detection voltage output from the second voltage detection circuit with a predetermined judgment value;
an output circuit that outputs an abnormal state detection signal when a comparator of the voltage imbalance detection circuit determines that the difference is equal to or greater than the predetermined determination value;
an overvoltage detection circuit having a comparator that compares a second voltage indicated by a second detection voltage output from the second voltage detection circuit with a predetermined threshold voltage;
Equipped with
the output circuit is configured to output an abnormal state detection signal when a comparator of the overvoltage detection circuit determines that the second voltage is equal to or higher than the predetermined threshold voltage;
the output circuit has a first terminal connected to an output terminal of a comparator of the overvoltage detection circuit, a second terminal connected to ground, and a control terminal connected to the output terminal of the comparator of the voltage imbalance detection circuit, and has a switch that switches between an off state in which no conduction is established between the first terminal and the second terminal and an on state in which conduction is established between the first terminal and the second terminal in response to a voltage input to the control terminal,
the output circuit is configured such that while the signal output from the output terminal of the comparator of the voltage imbalance detection circuit is at a low level, the switch is in an off state, and the output circuit outputs a low-level signal output from the output terminal of the comparator of the overvoltage detection circuit as the abnormal state detection signal;
the output circuit, while the signal output from the output terminal of the comparator of the voltage imbalance detection circuit is at a high level, outputs a low-level signal as the abnormal state detection signal, with the switch being in an on state;
Abnormal condition detection circuit. the second detection voltage output from the second voltage detection circuit is input to an inverting input terminal of a comparator of the overvoltage detection circuit;
A voltage corresponding to the predetermined threshold voltage is input to a non-inverting input terminal of a comparator of the overvoltage detection circuit.
4. The abnormal state detection circuit according to claim 2 or 3 . the output circuit further includes a latch circuit that maintains the output of the abnormal state detection signal.
4. The abnormal condition detection circuit according to claim 3 . An abnormal state detection circuit according to any one of claims 1 to 5 ;
A series circuit of the two capacitors;
a DC power supply circuit that outputs a predetermined DC voltage across both ends of the series circuit based on power from a power supply;
A DC load that operates on the predetermined DC voltage;
Equipped with
Electrical equipment. The power supply circuit further includes a microcomputer for controlling the power supply circuit.
the DC power supply circuit is configured to stop operation of the DC power supply circuit when the DC power supply circuit receives the abnormal state detection signal from the output circuit of the abnormal state detection circuit;
the microcomputer executes an operation to deal with the abnormal condition when it receives the abnormal condition detection signal from the output circuit of the abnormal condition detection circuit.
7. An electrical device according to claim 6 .

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