JP7689342B2 - Optical Switch - Google Patents

Description

The present invention relates to an optical switch used in optical communication networks.

Optical switches are key devices in optical communication networks. In order to process the rapidly increasing communication traffic in recent years, larger-scale optical switches are required. An important performance index of an optical switch is the number of inputs and outputs that can be controlled by one switch, i.e., the number of input ports and output ports. A large-scale optical switch with a large number of ports makes it possible to switch the paths of many optical signals at the same time.

In order to increase the scale of optical switches, a multi-input, multi-output optical switch using a waveguide is considered to be promising. An optical switch is composed of many element switch circuits (hereinafter referred to as element SW circuits) with two inputs and two outputs (2x2). Since a silica ( _SiO2 )-based waveguide has a small propagation loss of optical signals, an optical switch using a silica-based waveguide can obtain good characteristics even if the signal light passes through many element SW circuits (Non-Patent Document 1).

One of the important functions required for optical switches is to maintain a non-blocking state even when they become large-scale and have multiple inputs and multiple outputs. Non-blocking means that when signal light from an arbitrary input port is switched to an unused output port, there is no effect on the path between the already connected input port and output port, or on the optical signal passing through this path.

In the actual manufacturing process of optical switches, there is a limit to the number of element SW circuits that can be placed on one wafer. In order to realize larger-scale optical switches, it is important to develop new circuit topologies and implementation configurations that realize larger-scale multi-input multi-output optical switches with fewer element SW circuits while maintaining the non-blocking function described above.

Takashi Goh, Mitsuho Yasu, Kuninori Hattori, Akira Himeno, Masayuki Okuno, and Yasuji Ohmori, “Low Loss and High Extinction Ratio Strictly Nonblocking 16×16 Thermooptic Matrix Switch on 6-in Wafer Using Silica-Based Planar Lightwave Circuit Technology”, IEEE J. Lightwave Technol., vol. 19, no. 3, pp.371-379, 2001 S. Sohma, T. Watanabe, N. Ooba, M. Itoh, T. Shibata and H. Takahashi, “Silica-based PLC Type 32x32 Optical Matrix Switch,” 2006 European Conference on Optical Communications, 2006, pp. 1-2, doi: 10.1109/ECOC.2006.4801113 C. Clos, “A study of non-blocking switching networks,” in The Bell System Technical Journal, vol. 32, no. 2, pp. 406-424, March 1953, doi: 10.1002/j.1538-7305.1953.tb01433.x Ai Yanagihara, Keita Yamaguchi, Takashi Goh, Kenya Suzuki, Surface Mount Technology for Silica based Planar Lightwave Circuit and Its Application to Compact 16×16 Multicast Switch, IEICE Transactions on Electronics 2020 T. Shibata et al., “Silica-Based Waveguide-Type 16x16 Optical Switch Module Incorporating Driving Circuits”, in IEEE Photonics Technology Letters, vol. 15, no. 9, pp. 1300-1302, Sept. 2003 Yohei Sakamaki, Takashi Saida, Toshikazu Hashimoto, Shin Kamei, and Hiroshi Takahashi, “Loss Reduction of Waveguide Crossings by Wavefront Matching Method and Their Application to Integrated Optical Circuits,” J. Lightwave Technol., vol. 27, no. 13, pp. 2257-2263, July 2009

The present invention provides a circuit topology and implementation that realizes a non-blocking, large-scale optical switch with an efficient manufacturing process while reducing the number of element SW circuits in a wafer.

One embodiment of the present invention is a three-stage Clos-type optical switch having M input ports and N output ports, comprising: a first stage consisting of a plurality of sub-switches, the first stage including a sub-switch of a first configuration having m input ports and a sub-switch of a second configuration having a number of input ports different from m; a second stage including a plurality of sub-switches to which output ports of the plurality of sub-switches of the first stage are connected; and a third stage consisting of a plurality of sub-switches to which output ports of the plurality of sub-switches of the second stage are connected, the third stage including a sub-switch of a third configuration having n output ports and a sub-switch of a fourth configuration having a number of output ports different from n, each of the sub-switches including a plurality of element switch circuits, the element switch circuits being cascaded. The optical switch includes two or more connected Mach-Zehnder interferometers and a heater formed on one arm waveguide of each Mach-Zehnder interferometer, all of the sub-switches in the first stage, the second stage, and the third stage are arranged on a single wafer, the element switch circuit is formed in one or more switch regions in each stage, a waveguide region consisting only of a waveguide connecting adjacent switch regions is arranged alternately with the switch region, the switch region and the waveguide region are arranged in a zigzag pattern from the input side of the optical switch to the output side in the order of the first stage, the second stage, and the third stage, and a connector that collects the electrical wiring that drives the heater and connects it to the outside is arranged across the switch regions in different stages.

By reducing the number of elemental SW circuits on a wafer, it is possible to efficiently realize large-scale non-blocking optical switches.

FIG. 1 is a diagram showing a circuit configuration of a three-stage Clos type optical switch according to the prior art; 1 is a graph showing the relationship between the number of ports of a sub-SW and the number S of required element SW circuits. This is a diagram comparing S when the number of ports n of a sub-SW is changed in a 64×64 configuration. FIG. 13 is a diagram showing an example of a configuration in which sub-SWs having different configurations are mixed in the first and third stages. FIG. 13 is a diagram showing another example in which sub-SWs of different configurations are mixed in a symmetrical configuration. FIG. 13 is a diagram showing another example in which sub-SWs of different configurations are mixed in an asymmetric configuration; FIG. 1 is a diagram showing a circuit configuration of an optical switch in which different sub-SWs according to the present disclosure are mixed. 1 is a diagram illustrating the layout of element SW circuits on a wafer of an optical switch according to the present disclosure. 2 is an enlarged view showing the configuration of a waveguide region of an optical switch according to the present disclosure; FIG. 1 is a diagram illustrating the electrical connector arrangement on a wafer of the disclosed optical switch. 1 is a diagram showing a configuration of an element SW circuit in an optical switch according to the present disclosure.

The optical switch disclosed herein provides a circuit topology and implementation form that realizes a large-scale non-blocking optical switch with fewer element SW circuits compared to conventional optical switches. In terms of circuit topology, sub-switches (sub-SWs) of different configurations are mixed in the first and third stage blocks of a three-stage Clos type optical switch. In terms of implementation form, all element SW circuits of the optical switch are fabricated on one wafer, multiple switch regions and multiple waveguide regions are alternately arranged in a zigzag pattern, and electrical wiring to the heaters of each element SW circuit is concentrated to a connector arranged on the inner side of the wafer surface. It is also possible to reduce manufacturing costs by increasing the utilization efficiency of the wafer. Below, the configuration of the optical switch disclosed herein will be explained in comparison with the optical switch of the conventional technology.

As already mentioned, excellent optical characteristics can be obtained with a waveguide device using a quartz substrate. On the other hand, it is difficult to miniaturize the element SW circuit compared to a waveguide device using Si photonics that forms a waveguide on a Si substrate. When the element SW circuit described later is created using a Mach-Zehnder Interferometer (MZI), as described in Non-Patent Document 2, the maximum switch size on a quartz substrate is about 32 x 32 on one chip.

Non-Patent Document 3 reports that by making the optical switch a three-stage Clos type, it is possible to reduce the number of element switch circuits that make up a large-scale switch. In this three-stage Clos type optical switch, a large-scale multi-input multi-output optical switch is divided into smaller multi-input multi-output optical switches. The small-scale multi-input multi-output switches that are the smallest units that make up a large-scale optical switch are called sub-switches (hereinafter, sub-SWs).

Fig. 1 is a diagram showing the circuit configuration of a three-stage Clos type optical switch of the prior art. The optical switch 100 has M input ports and N output ports, and is composed of a first stage block 101, a second stage block 102, and a third stage block 103. In the optical switch 100 of Fig. 1, the first stage block 101 is composed of p sub-SWs 104-1 of m x k size, the second stage block 102 is composed of k sub-SWs 104-2 of p x q size, and the third stage block 103 is composed of q sub-SWs 104-3 of k x n size. It is known that the condition for non-blocking in the three-stage Clos type optical switch 100 of Fig. 1 is expressed by the following formula.
k≧m+n+1 Formula (1)

The sub-SW contains element SW circuits whose number is (number of input ports) x (number of output ports). The relationship between the number of ports M, N of the optical switch, the number of sub-SWs in each stage p, k, q, and the number of ports m, n of the sub-SW, and the required number of element SW circuits S is calculated using the following formula.

If the number of input ports and output ports of the optical switch is the same, that is, M = N, and furthermore, m = n and p = q, then the number of element SW circuits S is given by the following formula.

For example, in silica-based waveguides, MZIs are often used as element SW circuits, and a double-gate configuration is also used to improve crosstalk characteristics in optical switches. In a double-gate configuration, one element SW circuit is composed of two 2x2 SWs (or 1x2 SWs, 2x1 SWs), and the number of element SW circuits required is 2S, which is obtained by further doubling S in equation (3).

Figure 2 is a graph showing the relationship between the number of ports of the sub-SW in a three-stage Clos type optical switch and the number S of required element SW circuits. In the three-stage Clos type optical switch shown in Figure 1, consider the case where the number of input ports and output ports are equal and the optical switch has a symmetrical structure, i.e., M = N, m = n, p = q. The number S of required element SW circuits is as shown in formula (2).

FIG. 2A shows the relationship between the number of ports n of the sub-SW and the number of element SW circuits S when the number of ports n of the sub-SW is a divisor of the number of ports N of the optical switch. FIG. 2B shows the relationship between the number of ports n of the sub-SW and the index S/ ^N2 . In both cases, the overall scale of the optical switch is shown as a parameter (N×N, N=16, 32, 64, 128). The index S/N2 in FIG. ^2B represents the ratio between the number of element SW circuits S and the square of the number of ports N of the entire optical switch, and corresponds to the ratio of the number of element SW circuits to the overall scale of the optical switch. If the index S/ ^N2 is small, the optical switch can be efficiently configured with a relatively smaller number of element SW circuits. In an optical switch having a normal PILOSS configuration, rather than a Clos type in which the optical switch is divided into multiple blocks, the index S/ ^N2 is 1.

Referring to FIG. 2(a), when the number of ports N of the optical switch is fixed, the required number of element SW circuits S is minimized at a certain value of the number of ports n of the sub-SW. For example, in a 128 x 128 optical switch configuration, the number of ports n of the sub-SW is minimal at 8. In a 16 x 16 optical switch, the number of element switch circuits S does not decrease even if a three-stage Clos type configuration is adopted, and even in a 32 x 32 optical switch, the effect of reducing the number of element SW circuits S is limited.

Also, referring to FIG. 2B, a decrease in the index S/ ^N2 can be confirmed in optical switches larger than 32×32. In order to adopt a three-stage Clos type configuration instead of a normal PILOSS configuration, it is necessary that the index S/ ^N2 is at least below 1. In order to accommodate a large-scale optical switch circuit, the wafer diameter should be large, for example, 6 inches or more. As an example of accommodating all element SW circuits of a 64×64 three-stage Clos type optical switch shown in FIG. 1 on such a large-diameter wafer, while taking into consideration a realistic manufacturing process for optical integrated circuits, the following will describe the case where all element SW circuits are accommodated on such a large-diameter wafer.

Fig. 3 shows a table comparing the number of element SW circuits S in a 64x64 size optical switch with different configuration patterns for different sub-SW port numbers n. In Fig. 1, the number of input and output ports is equal (M=N=64) and the optical switch has a symmetrical structure, and shows the number of element SW circuits in each stage when the number of ports n of the sub-SW (2, 4, 8, 16, 32) is changed. The configurations shown in the table in Fig. 3 correspond to the plot points of the 64x64 curve shown in Fig. 2. When n=4, S/ ^N2 =0.6563 for ^N2 =4096, which has the effect of reducing the number of element SW circuits by about 35% compared to an optical switch with a PILOSS configuration.

The inventors have investigated an optical switch configuration that further reduces the number of element SW circuits, compared to the PILOSS configuration, by reducing the number of element SW circuits by 35% through the above-mentioned optimization of the 64 x 64 optical switch. By combining this with a new implementation configuration, a large-scale optical switch can be realized with an efficient manufacturing process. The inventors focused first on improving the number of element SW circuits in the circuit topology, and second on improving the area occupied by electrical wiring in the implementation.

In the optimization of the three-stage Clos type optical switch shown in Figs. 1 to 3, the configuration of the optical switch was limited to an N x N symmetrical structure having the same number of ports on the input side and the output side. In addition, the number of ports n of the sub-SWs in the first stage block and the third stage block was set as a divisor of the number of ports N of the optical switch, and all the sub-SWs were made to have the same configuration. In the table of Fig. 3, even in the case of n = 4 where the number of element SW circuits and the index S/ ^N2 are the smallest, the total number of element SW circuits is 2688. As will be described later, each of the many element SW circuits requires electrical wiring to control the respective heaters. In order to efficiently connect the heaters to the external control signal source of the optical switch chip, a multi-pin connector that collects electrical wiring for the number of element SW circuits is essential. If the number of element SW circuits can be reduced while the number of connectors can be reduced, the manufacturing cost of the optical switch can also be reduced.

Therefore, we investigated a 64x64 optical switch that mixed a sub-SW with a port number n of 4 and a sub-SW with a port number n' different from 4 in each of the first and third stage blocks. We compared the combination of sub-SWs with different configurations in each of the first and third stage blocks with the configuration of the conventional technology that used sub-SWs with the same configuration in each stage shown in Figure 3. For simplicity, we considered that the sub-SWs in the first and third stage blocks have a symmetrical optical switch circuit topology. For example, if the first stage sub-SW has an nxp configuration, the corresponding third stage sub-SW has a pxn configuration.

Figure 4 shows an example of an optical switch configuration in which sub-SWs of different configurations are mixed in the first and third stage blocks. When the number of input ports M and output ports N are 64, the first stage block of a three-stage Clos type mixes one sub-SW with the number of input ports n=4 (first configuration) with 12 sub-SWs with the number of input ports n'=5 (second configuration). The third stage block of a three-stage Clos type mixes one sub-SW with the number of output ports n=4 (third configuration) with 12 sub-SWs with the number of output ports n'=5 (fourth configuration).

In an optical switch that has a sub-SW with n ports and a sub-SW with n' ports of a different configuration, the condition for non-blocking is given by the following formula: Here, MAX(n) is the larger value of n and n'.
k≧n+MAX(n)-1 Formula (4)

Referring to Figure 1, the number of ports of the sub-SW is the number of ports on the input side of the optical switch for the sub-SW of the first stage block 101 (corresponding to m in Figure 1), and the number of ports on the output side of the optical switch for the sub-SW 103 of the third stage block (corresponding to n in Figure 1). The sub-SW of the first stage block and the sub-SW of the third stage block have a symmetrical structure.

As shown in FIG. 4, the total number of element SW circuits is S=2640 due to the configuration in which sub-SWs of different configurations are mixed in the first and third stage blocks. Compared to the case in which all sub-SWs in the first and third stage blocks have the same configuration with port number n=4 (4×7, 7×4) as shown in the table in FIG. 3, the total number of element SW circuits can be reduced by 48. The effect of mixing sub-SWs of different configurations in the first and third stage blocks can also be confirmed in other configuration patterns in which sub-SWs are mixed.

FIG. 5 shows another example of a configuration pattern of an optical switch in which sub-SWs of different configurations are mixed in the first and third stage blocks in a symmetrical configuration of M=N=64. Each parameter in the table of FIG. 5 is as defined in FIG. 8 described later, with M=N. The table shown in FIG. 5 shows a configuration pattern in which two types of sub-SWs, _m1 × _k1 and _m2 × _k2, are mixed in the first stage block, and two types of sub-SWs, _k1 × _n1 and _k2 × _n2, are mixed in the third stage block. The number of element SW circuits is compared with the case in FIG. 3 where m=n=4 and k=7 are provided with only sub-SWs of the same configuration (4×7, 7×4). It can be seen that there are various configuration patterns in which sub-SWs of different configurations are mixed, which can reduce the total number of element SW circuits.

FIG. 6 shows an example of an optical switch configuration pattern in which sub-SWs of different configurations are mixed in the first and third stage blocks in the case of an asymmetric configuration with M=64 and N=128. The parameters in the table in the figure are as defined in FIG. 8 described later. In the above-mentioned FIG. 4 and FIG. 5, the effect of mixing sub-SWs in an optical switch with a symmetric structure with M ₌ N=64 and the same number of input ports and output ports is shown. In FIG. 6, two types of sub-SWs, p1 _m1 × _k1 and _{p2 m2} × _k2 , are mixed in the first stage block with the number of input ports M=64 (where _m1 > _m2 ). Also, two types of sub-SWs, _{q1 k1} × _n1 and _{q2 k2} × _n2 , are mixed in the third stage block with the number of output ports N=128 (where _n1 > _n2 ). It can be seen that even in an asymmetric optical switch having a different number of input ports and output ports, there are various configuration patterns in which sub-SWs of different configurations are mixed, which can reduce the total number of element SW circuits.

FIG. 7 is a diagram showing the circuit configuration of a three-stage Clos type optical switch in which sub-SWs of different configurations are mixed according to the present disclosure. The optical switch 10 has M input ports and N output ports, and is composed of a first stage block 11, a second stage block 12, and a third stage block 13. The difference in configuration from the conventional optical switch shown in FIG. 1 is that sub-SWs of different configurations are mixed in the first and third stages. The first stage block includes two types of sub-SWs: a sub-SW 11-1 with a configuration of m ₁ ×k ₁ and a sub-SW 11-2 with a configuration of m ₂ ×k _2. The third stage block 13 includes two types of sub-SWs: a sub-SW 13-1 with a configuration of k ₁ ×n ₁ and a sub-SW 13-2 with a configuration of k ₂ ×n _2. The number of input ports M is m ₁ ×p ₁ +m ₂ ×p ₂ , and the number of output ports N is n ₁ ×q ₁ +n ₂ ×q ₂ . The numbers of ports k ₁ and k ₂ of the sub-SWs and the numbers of ports m ₁ , m ₂ , n ₁ and n ₂ are assumed to satisfy the following formula.

The second-stage block 12 also includes sub-SWs of different configurations to accommodate a configuration in which sub-SWs of different configurations from the first and third stages are mixed.

It will be understood that the reduction in the number of element SW circuits in the optical switches of each configuration shown in Figures 4 to 6, combined with the features of the implementation form of the optical switch disclosed herein described below, has the effect of increasing the scale of the optical switch and reducing manufacturing costs. Below, various features of the implementation form of the optical switch disclosed herein shown in Figure 7, in which sub-SWs of different structures are mixed, are described.

Figure 8 is a diagram showing the layout configuration of the optical switch of the present disclosure on a wafer. As an example, the rough layout of the element SW circuits of the optical switch on a wafer 200 made of a quartz substrate is shown. The optical switch of the present disclosure differs from the conventional three-stage Clos type optical switch 100 shown in Figure 1 only in that sub-SWs of different configurations are mixed in each of the first stage block 101 and the third stage block 103. There is no difference in the rough layout of the three-stage blocks of the three-stage Clos type optical switch.

In the optical switch disclosed herein, all element SW circuits of the 64x64 optical switch are arranged in a zigzag pattern (a zigzag pattern) between the input point 221-1 indicated by the arrow at the top of FIG. 8 and the output point 221-2 indicated at the bottom. In the six switch (SW) regions 211-1, 211-2, 212-1, 212-2, 213-1, and 213-2 hatched with diagonal lines, multiple element SW circuits constituting the sub-SW are arranged in a roughly matrix pattern. Details will be described later with reference to FIG. 11, but the element SW circuits include at least MZIs, waveguides connecting the MZIs, and heaters. The seven waveguide regions 214a to 214g, including bent portions, on the input or output side of each SW region are composed only of waveguides connecting the element SW circuits at the respective ends of adjacent SW regions. Therefore, in the optical switch disclosed herein, the element SW circuit of the Clos-type optical switch is divided into multiple SW regions in the order of the constituent stages (first stage, second stage, third stage). Waveguide regions consisting only of waveguides connecting adjacent SW regions are arranged alternately with the SW regions, and these SW regions and waveguide regions are arranged in a zigzag pattern from the input side to the output side.

Referring again to FIG. 8, the details of the zigzag arrangement are as follows: in the two SW regions 211-1 and 211-2 sandwiching the U-shaped folded waveguide region 214b, sub-SWs of the first stage block of the three-stage Clos type optical switch with a mixture of different configurations are arranged. Following the SW region 211-2, a waveguide region 214c is arranged in a U-shaped folded shape to connect the first and second stage blocks. Similarly, in the two SW regions 212-1 and 212-2 sandwiching the waveguide region 214d, sub-SWs of the second stage block are arranged. Following the SW region 212-2, a waveguide region 214e is arranged in a U-shaped folded shape to connect the second and third stage blocks. Similarly, sub-SWs with different configurations of the third stage block are arranged in the two SW regions 213-1 and 213-2 that sandwich the waveguide region 214f.

In the wafer configuration of Figure 8, the sub-SWs of each stage are arranged in two separate SW regions, but this is one example of an optical circuit arrangement, and the division of the SW regions is not limited to that shown in Figure 8. The number of SW regions in each stage can be one or three or more, and the number of SW regions can differ depending on the stage.

The optical switch disclosed herein further includes a waveguide region with a folded structure that connects between SW regions arranged in a zigzag pattern, thereby realizing a configuration that suppresses signal crosstalk. In a three-stage Clos-type optical switch configuration, as shown in FIG. 1, paths cross between each stage. If this path crossing is realized with a two-dimensional waveguide on the wafer surface, the waveguides will cross, and crosstalk will occur due to signal light leaking between the paths. In order to suppress crosstalk at the crossing, it is necessary to make the crossing angle of the two waveguides as large as possible (Non-Patent Document 6).

Figure 9 is a diagram showing an enlarged configuration of the waveguide region of the optical switch of the present disclosure. Only a part of the wafer 200 shown in Figure 8 is shown, and the waveguide region 231 connecting the two SW regions 230-1 and 230-2 is shown enlarged on the right side. All of the multiple waveguides connecting the two SW regions have a U-shaped folded structure. In general, in order to propagate an optical signal with low loss in an optical waveguide, it is necessary to have a bending radius of a predetermined value or more, and in order to make the crossing angle large, the area in the wafer used for the crossing becomes wide. According to the arrangement of the optical switch of the present disclosure, the necessary large bending angle can be realized by the folding back that the waveguide region 231 inherently has. And, by arranging the crossing portion 232 in the waveguide region 231, the crossing angle can be maximized without increasing the circuit area to reduce crosstalk. As is clear from the enlarged view of Figure 9, it is possible to arrange the two waveguides so that they are orthogonal at 90 degrees at all crossing portions, and the optical switch of the present disclosure hardly generates crosstalk of the signal light between the paths.

The optical switch of the present disclosure also has features in its electrical wiring and extraction configuration. Referring again to FIG. 8, the wafer 200 including the optical switch is cut at dicing lines 223-1 and 223-2, and mounted on another substrate of the device. On the device, a bundle of 64 optical fibers is connected at the end faces cut by the dicing lines at input point 221-1 and output point 221-2. Although not shown in FIG. 8, electrical wiring for control is configured for the heaters of each element SW circuit on a layer separate from the waveguides of the MZIs of the element SW circuits on the wafer.

In an optical switch, each element switch circuit must be controlled independently. To achieve this, each element SW circuit must be electrically connected to a control device that sends out a control signal via electrical wiring on the wafer and a cable or flexible printed circuit board (FPC). The connection to the electrical wiring on the wafer is generally made by wire bonding to pads provided on the periphery of the chip. However, this method requires that the electrical wiring be extended from each element switch circuit to the periphery of the chip, and a large area on the chip is used for the electrical wiring. If the optical switch becomes larger and the number S of element switch circuits increases, the area used just for electrical wiring also increases (Non-Patent Document 4). Electrical wiring reduces the utilization efficiency of the wafer and increases the chip size and wafer diameter. It also increases the cost of the wafer and the cost of the manufacturing process.

In the optical switch of the present disclosure shown in Fig. 8, surface mount (SMT) type electrical connectors are mounted on the six SW regions 211-1, 211-2, 212-1, 212-2, 213-1, and 213-2 in which element SW circuits are fabricated, and electrical connections are made between each element switch circuit and an external control device, etc. This mounting method can eliminate or reduce the increase in chip size and wafer diameter due to electrical wiring, and the waste of wafer utilization efficiency.
FIG. 10 is a diagram for explaining the electrical connector arrangement on the wafer of the optical switch of the present disclosure. The six SW regions and seven waveguide regions on the wafer 220 are the same as those shown in FIG. 8. In order to collect the electrical wiring to each element SW circuit, an SMT type connector is arranged on the surface of the wafer, and the outer shape of the connector is shown by nine dotted line regions 2301- to 230-9. The connector is mounted by carrying out a process such as reflow soldering on the wafer 200. The electrode pads created on the wafer surface and the connector pins are soldered near the dotted lines showing the outer shape of the connector in FIG. 10. When the SMT type connector is arranged as in FIG. 10, a connector that can be inserted and removed from the connector on the mating FPC cable side perpendicular to the wafer surface can be used. If the connector shape on the FPC cable side is L-shaped, it may be inserted and removed parallel to the wafer surface.

In the optical switch disclosed herein, all element SW circuits of the optical switch are mounted on one wafer, and the element SW circuits in one stage are arranged in multiple SW regions. As described in FIG. 8, multiple SW regions 211-1 to 213-2 are arranged in a zigzag pattern alternately with the waveguide regions 214a to 214g, so that one SW region is arranged in close proximity to another SW region in the same stage or in an adjacent stage. All element SW circuits of the three-stage Clos type optical switch are arranged together in the wafer surface. By arranging multiple SMT type connectors on the inner side of the wafer surface across the SW regions of adjacent stages, centralized electrical wiring can be realized. By arranging each of the multiple SMT type connectors so as to cross at least two SW regions, the connector can be shared within the same stage or across different stages.

Compared to the conventional technology in which connectors are arranged around the periphery of the wafer, electrical wiring can be arranged more compactly. There is no need to route electrical wiring around the periphery of the wafer, and no need to provide an area for electrical wiring. The area of the circular wafer can be used without waste, resulting in a very high utilization rate of the wafer. There is no need to increase the diameter of the wafer, and small-diameter wafers can be used, so a sufficiently stable and proven process can be used in the manufacturing process of optical integrated circuits. By mixing sub-SWs with different configurations in the first and third stage blocks to reduce the number of element SW circuits and adopting the connector arrangement described above, the manufacturing cost of the entire optical switch can be reduced.

Figure 11 is a diagram showing the configuration of an element SW circuit in the optical switch disclosed herein. Figure 11 shows an element SW circuit when a three-stage Clos-type optical switch is configured with a matrix switch. To obtain a high extinction ratio as an optical switch, it is necessary to increase the extinction ratio in the element SW circuits corresponding to each intersection of the matrix switch. An element SW circuit that achieves a high extinction ratio can be realized by connecting multiple MZIs in parallel or in cascade (Non-Patent Document 5). Figures 11 (a) and (b) both show element SW circuits with a double-gate configuration using two MZIs connected in cascade.

Referring to FIG. 11, each of the double-gate element SW circuits 300a and 300b includes two MZIs 301 and 302. One MZI 301 is composed of an input coupler 307a, two arm waveguides, and an output coupler 307b. Heaters 304-1 and 304-2 are formed on one arm waveguide of each MZI. (a) and (b) of FIG. 11 show different examples of electrical wiring to the two heaters of the element SW circuit. (a) of FIG. 11 shows electrical wiring 305-1 and 305-2 that drive the heaters in parallel connection, and (b) shows electrical wiring 306 that drives the heaters in direct connection. In either case of electrical wiring, by applying a control voltage 303 to both ends of the electrical wiring, the optical path length of one of the waveguides can be changed by the heater to switch the output port. Multiple MZIs connected in series are always turned on and off simultaneously. By electrically connecting the heaters in series, it is possible to reduce the number of electrodes taken out per element SW circuit. This type of electrical connection reduces the area occupied by electrical wiring on the wafer, and also contributes to miniaturizing the optical switch chip.

Two electrical wiring is required to control the element SW circuit shown in FIG. 11, but if one terminal is grounded to drive the heater, only one electrical wiring is required per element SW circuit. In the 64 x 64 optical switch shown in FIG. 8, when sub-SWs with different configurations are combined in the first and third stages, the total number S of element SW circuits is 2640 as shown in FIG. 4. Here, if an SMT connector with 80 pins is used, and one of the heater electrical wirings is grounded and one pin of each SMT connector is used for grounding, the total number of connectors is 34. This allows the number of connectors to be reduced compared to the total number of 35 when the first and third stages of sub-SWs are configured with the same configuration as in the conventional technology configuration shown in FIG. 3.

In the above description of the implementation form, a three-stage Clos type optical switch has been used as an example, but in a Clos type optical switch with a different number of stages other than three, sub-SWs with different configurations may be mixed in the first stage (input side) and the final stage (output side). The effect of reducing the number of element SW circuits may also be achieved by mixing sub-SWs with different configurations only on either the input side or the output side. In addition, the above-mentioned implementation structure example of a three-stage Clos type optical switch has been described in the case where the input ports M and output ports N are the same number, but it can also be applied to an asymmetric optical switch with different M and N configurations as described in Figure 6.

As described in detail above, the optical switch disclosed herein provides a circuit topology and implementation form that realizes a non-blocking, large-scale optical switch with fewer element SW circuits compared to conventional technology.

The present invention can be used in optical switches used in optical communications.

Claims (5)

A three-stage Clos-type optical switch having M input ports and N output ports,
a first stage of sub-switches, the first stage including a first configuration of sub-switches having m input ports and a second configuration of sub-switches having a number of input ports different from m;
a second stage including a plurality of sub-switches to which output ports of the plurality of sub-switches of the first stage are connected;
a third stage comprising a plurality of sub-switches to which output ports of the plurality of sub-switches of the second stage are connected, the third stage including a sub-switch of a third configuration having n output ports and a sub-switch of a fourth configuration having a number of output ports different from n;
Each of the sub-switches includes a plurality of element switch circuits, and the element switch circuits include two or more cascaded Mach-Zehnder interferometers and a heater formed on one arm waveguide of each of the Mach-Zehnder interferometers;
all of the sub-switches in the first stage, the second stage and the third stage are disposed on a single wafer;
the element switch circuits are divided into one or more switch regions in each stage, and waveguide regions each consisting of only a waveguide connecting adjacent switch regions are arranged alternately with the switch regions, and the switch regions and the waveguide regions are arranged in a zigzag pattern from the input side of the optical switch toward the output side in the order of the first stage, the second stage, and the third stage,
an electrical wiring connector for connecting the electrical wiring for driving the heater to an external device, the electrical wiring connector being disposed across the switch regions in different stages; the number of input ports M and the number of output ports N are equal;
The optical switch described in claim 1, characterized in that the number m of input ports of the sub-switch of the first configuration is equal to the number n of output ports of the sub-switch of the third configuration, and the number of input ports of the sub-switch of the second configuration is equal to the number of output ports of the sub-switch of the fourth configuration. M=N=64,
the first stage includes one 4×8 switch and twelve 5×9 switches;
the second stage includes eight 13×13 switches and one 12×12 switch;
The optical switch of claim 2, wherein the third stage includes one 8x4 switch and twelve 9x5 switches. 4. The optical switch according to claim 1, wherein the material of the wafer is quartz (SiO ₂ ). An optical switch according to any one of claims 1 to 3, characterized in that in the waveguide region between two adjacent switch regions, different waveguides intersect at an intersection angle of 90 degrees.

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