JP7690974B2 - Wiring board and method for manufacturing same - Google Patents

Description

This disclosure relates to a wiring board that can be used as an interposer, a semiconductor device having a wiring board, and a method for manufacturing the same.

Semiconductor chips made using semiconductor substrates such as silicon are mounted on almost all electronic devices and provide various functions to the electronic devices. Terminals for inputting power and signals required for operation are provided on the semiconductor chip and mounted on the main substrate. At this time, a wiring substrate (hereinafter also referred to as an interposer) is provided between the semiconductor chip and the main substrate. The interposer has a substrate and multiple wirings as its basic components, and the wirings are provided on the substrate in various forms. For example, they are provided as through-hole wirings formed to penetrate the substrate, or as multi-layer wirings embedded in an insulating film provided on the substrate and arranged to form multiple wiring layers. Through such wirings, the terminals of the semiconductor chip and the wirings on the main substrate are electrically connected. For example, Patent Document 1 discloses an interposer having multi-layer wirings in which multiple wirings including copper are stacked via an insulating film, and a method for manufacturing the interposer.

International Publication No. WO 2014/069662

One of the objectives of the present disclosure is to provide a wiring board that can be used as an interposer and a method for manufacturing the same. For example, one of the objectives of the present disclosure is to provide a wiring board that can be applied to semiconductor devices that require high operating frequencies, such as those used in high-speed communications, a semiconductor device having a wiring board, and a method for manufacturing the same.

One embodiment of the present disclosure is a wiring board. The wiring board has a base film containing an organic compound, a first wiring containing copper located on the base film, and a first protective film located on the first wiring and in contact with the first wiring. The first protective film includes a first inorganic compound layer containing silicon nitride, a second inorganic compound layer located on the first inorganic compound layer and in contact with the first inorganic compound layer, containing silicon oxide, and a third inorganic compound layer located on the second inorganic compound layer and in contact with the second inorganic compound layer, containing silicon nitride.

One embodiment of the present disclosure is a wiring board. The wiring board includes a substrate having a first surface and a second surface opposite to the first surface, a base film on the substrate, a first wiring located on the first surface and embedded in the base film and containing copper, a first protective film located on the first wiring and in contact with the first wiring, a second wiring on the first protective film, and a second protective film on the second wiring. The first protective film includes a first inorganic compound layer containing silicon nitride, and a second inorganic compound layer located on the first inorganic compound layer and in contact with the first inorganic compound layer and containing silicon oxide. The second protective film includes a first inorganic compound layer containing silicon nitride, a second inorganic compound layer located on the first inorganic compound layer and in contact with the first inorganic compound layer and containing silicon oxide, and a third inorganic compound layer located on the second inorganic compound layer and in contact with the second inorganic compound layer and containing silicon nitride.

FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment. FIG. 2 is a schematic top view of wiring of a wiring board according to an embodiment. FIG. 2 is a schematic top view of wiring of a wiring board according to an embodiment. FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment. FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment. FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment. FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment. 1A to 1C are schematic cross-sectional views showing a method for manufacturing a wiring board according to an embodiment. 1A to 1C are schematic cross-sectional views showing a method for manufacturing a wiring board according to an embodiment. 1A to 1C are schematic cross-sectional views showing a method for manufacturing a wiring board according to an embodiment. 1A to 1C are schematic cross-sectional views showing a method for manufacturing a wiring board according to an embodiment. 1A to 1C are schematic cross-sectional views showing a method for manufacturing a wiring board according to an embodiment. 1A to 1C are schematic cross-sectional views showing a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor layer according to an embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor layer according to an embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor layer according to an embodiment.

Each embodiment of the present disclosure will be described below with reference to the drawings. However, the present disclosure can be implemented in various forms without departing from the spirit of the disclosure, and should not be interpreted as being limited to the description of the embodiments exemplified below.

In order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present disclosure. In this specification and each figure, elements having the same functions as those explained in the previous figures may be given the same reference numerals and duplicate explanations may be omitted.

In this specification and claims, when describing a mode in which a structure is placed on top of another structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a structure so as to be in contact with the structure, and a case in which another structure is placed above a structure via yet another structure.

In this specification and claims, the expression "a certain structure is exposed from another structure" means that a part of a certain structure is not covered by another structure, and includes a case where the part not covered by the other structure is covered by yet another structure.

First Embodiment
1. Basic Structure A wiring board 100 according to an embodiment of the present disclosure will be described with reference to the schematic cross-sectional views of Figures 1(A) and 1(B). As shown in Figure 1(A), the wiring board 100 has a base film 102, a first wiring 104 on the base film 102, and a first protective film 108 located on the first wiring 104 and in contact with the first wiring 104.

The base film 102 includes an organic compound. The organic compound used preferably has a low dielectric constant and a low dielectric loss tangent. For example, an organic compound having a dielectric constant of 2.0 or more and 4.0 or less and a low dielectric loss tangent of 1×10 ⁻⁴ or more and 1× ^{10 −2} or less, or 1×10 ⁻³ or more and 1×10 −2 or less, can be used as the base film 102. Such an organic compound is typically a polymer having a polyimide skeleton (hereinafter, simply referred to as polyimide), and the polyimide may be in a chain form or may be crosslinked between molecules. The base film 102 may be mixed with epoxy resin, silicon oxide particles, glass fiber, or the like. The base film 102 may be flexible.

The first wiring 104 may include metals such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, and chromium, or alloys thereof, and typically includes copper. The first wiring 104 is disposed so that a portion of it is within an opening provided in the base film 102, and a portion of it covers a portion of the upper surface of the base film 102. The thickness of the portion of the first wiring 104 above the base film 102 may be 0.5 μm or more and 50 μm or less, 1 μm or more and 20 μm or less, or 1 μm or more and 10 μm or less. Although two first wirings 104 are illustrated in FIG. 1(A) and FIG. 1(B), there is no restriction on the number of first wirings 104.

There are no restrictions on the planar shape of the first wiring 104, and it is determined based on the required function. For example, the first wiring 104 can be provided so as to extend mainly in one direction, as shown in FIG. 2(A). In this case, the width W of the first wiring 104 can be selected in the range of 10 μm to 1000 μm. Alternatively, as shown in FIG. 2(B), the first wiring 104 may have a mesh-like shape. In this case, the width W (i.e., the distance between adjacent openings provided in the mesh shape) can be selected in the range of 5 μm to 500 μm. Alternatively, as shown in FIG. 3, the first wiring 104 may have the same or nearly the same shape as the planar shape of the wiring substrate 100. In this case, the width W is selected in the range of more than 1000 μm and less than 7 cm.

As shown in FIG. 1A, the first protective film 108 contacts the top and side surfaces of the first wiring 104 and the top surface of the base film. The first protective film 108 has a three-layer structure. Specifically, the first protective film 108 has a first inorganic compound layer 108a, a second inorganic compound layer 108b located on the first inorganic compound layer 108a and in contact with the first inorganic compound layer 108a, and a third inorganic compound layer 108c located on the second inorganic compound layer 108b and in contact with the second inorganic compound layer 108b.

The dielectric constant of the second inorganic compound layer 108b is preferably smaller than that of the first inorganic compound layer 108a and the second inorganic compound layer 108b. More specifically, the first inorganic compound layer 108a and the third inorganic compound layer 108c contain silicon nitride or silicon carbide. That is, the first inorganic compound layer 108a and the third inorganic compound layer 108c contain silicon and nitrogen or silicon and carbon as main constituent elements. On the other hand, the second inorganic compound layer 108b contains silicon oxide or silicon oxynitride. That is, the second inorganic compound layer 108b contains silicon and oxygen as constituent elements, and may further contain nitrogen. When nitrogen is contained, its composition is smaller than that of oxygen. The first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c are formed by a chemical vapor deposition (CVD) method (plasma CVD method) in the presence of plasma.

The thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c can be determined arbitrarily. For example, the thickness of the first inorganic compound layer 108a is smaller than the thicknesses of the second inorganic compound layer 108b and the third inorganic compound layer 108c, and can be, for example, 0.05 μm to 0.2 μm, typically 0.1 μm. The thickness of the second inorganic compound layer 108b is larger than the thicknesses of the first inorganic compound layer 108a and the third inorganic compound layer 108c, and can be 0.5 μm to 10 μm, or 1 μm to 5 μm. The thickness of the third inorganic compound layer 108c can be 0.2 μm to 1 μm, or 0.3 μm to 0.7 μm, typically 0.5 μm. That is, assuming that the thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c are _T1 , _T2 , and _T3 , respectively, the first protective film 108 may be configured so that the following relationship holds:
_T1 < _T3 < _T2

1B, the thickness of the second inorganic compound layer 108b may be greater than the thickness of the portion of the first wiring 104 above the base film 102. In this case, even if a plurality of first wirings 104 are close to each other, the bottom surface of the third inorganic compound layer 108c is located above the top surface of the first wiring 104 between the adjacent first wirings 104. That is, the third inorganic compound layer 108c is not sandwiched between the adjacent first wirings 104 in the cross section. For this reason, it is possible to prevent the formation of a capacitance (parasitic capacitance) between the third inorganic compound layer 108c, which has a relatively high dielectric constant, and the adjacent first wiring 104. In addition, by making the thickness of the first inorganic compound layer 108a smaller than the thickness of the second inorganic compound layer 108b, it is possible to simultaneously prevent the formation of a large capacitance between the first inorganic compound layer 108a and the adjacent first wiring 104. As a result, it is possible to prevent the occurrence of parasitic capacitance and the associated decrease in signal transmission speed.

As shown in FIG. 1(A) and FIG. 1(B), an opening is provided in the first protective film 108 that reaches the first wiring 104. This allows electrical connection between the first wiring 104 and other wiring, or a semiconductor chip provided on the wiring substrate 100, etc.

As an optional configuration, the wiring substrate 100 may have a second protective film 110 on the first protective film 108. The second protective film 110 may also contain a polymer, such as polyimide, polyamide, polyester, polycarbonate, or polysiloxane. The material contained in the second protective film 110 and the material contained in the base film 102 may be the same. In this case, due to the difference in impurity concentration, the dielectric constant and dielectric tangent of the second protective film 110 may be higher than those of the first protective film 108.

As an optional configuration, the wiring board 100 may have a lower wiring 112 located below the first wiring 104 and electrically connected to the first wiring 104. The lower wiring 112 is covered by the base film 102. Like the first wiring 104, the lower wiring 112 also contains the above-mentioned metal or alloy, and typically contains copper. By using the lower wiring 112 and the first wiring 104, electrical connection can be made between the semiconductor chip and the main substrate.

Seed layers 106 and 114 may be provided so as to contact the bottom and side surfaces of the first wiring 104 and the bottom surface of the lower wiring 112, respectively. The seed layers 106 and 114 contain metals such as titanium, nickel, chromium, copper, and gold, or alloys thereof, typically containing copper. By forming the seed layers 106 and 114, the first wiring 104 and the lower wiring 112 can be formed by electrolytic plating, as described later. Although not shown, a barrier layer may be further provided under each of the seed layers 106 and 114. More specifically, a barrier layer may be provided between the undercoat 118 and the seed layer 114, which will be described later, and between the lower wiring 112 and the seed layer 106. The material contained in the barrier layer is preferably a conductive material selected from metals such as titanium, tantalum, molybdenum, and tungsten, alloys thereof, or nitrides thereof, and has a higher melting point than the metals contained in the first wiring 104 and the lower wiring 112. By providing a barrier layer, it is possible to prevent metals contained in the first wiring 104 and the lower wiring 112 from diffusing into the base film 102.

As an optional configuration, the wiring board 100 may have a substrate 116 under the base film 102. Materials used for the substrate 116 include glass, silicon, gallium arsenide, gallium nitride, ceramics, and composite materials of glass and resin. Examples of resins include epoxy resin, polyimide, polyamide, and polyester. When the substrate 116 is provided, an undercoat 118 may be provided between the substrate 116 and the base film 102. The undercoat 118 is a film that has the function of preventing impurities such as metal ions from diffusing from the substrate 116 to the base film 102, and contains, for example, silicon-containing inorganic compounds such as silicon oxide and silicon nitride. The undercoat 118 may have a single layer structure, or may be composed of multiple films containing different materials.

When a wiring board is used as an interposer for semiconductor devices that require high operating frequencies (e.g., 1 GHz to 100 GHz) such as high-frequency elements, the insulating film surrounding the wiring of the wiring board is required to have a low dielectric constant and dielectric dissipation factor to prevent signal transmission loss and delay. Even if an insulating film (e.g., base film 102 in wiring board 100) is formed using a material that satisfies such performance requirements, impurities such as water, oxygen, and metal ions will penetrate the insulating film from the outside after the wiring board is formed, and the dielectric constant and dielectric dissipation factor of the insulating film will gradually increase. As a result, signal transmission loss and delay will occur, significantly affecting the characteristics of the semiconductor chip mounted on the interposer.

On the other hand, in the wiring board 100 of this embodiment, the upper surface of the base film 102 covering the first wiring 104 and the lower wiring 112 is covered by the first protective film 108 having a three-layer structure. Here, if the third inorganic compound layer 108c does not exist, the silicon oxide contained in the second inorganic compound layer 108b is relatively hydrophilic, so when impurities such as water enter from the outside, the impurities diffuse into the first inorganic compound layer 108a. Although the first inorganic compound layer 108a contains silicon nitride, which has low hydrophilicity and high blocking properties against impurities, as described above, its thickness is small, so that some of the impurities penetrate. Therefore, the impurities enter the base film 102, and the dielectric constant and dielectric loss tangent of the base film 102 increase.

However, the first protective film 108 has a third inorganic compound layer 108c on the second inorganic compound layer 108b, which has a thickness greater than that of the first inorganic compound layer 108a and contains silicon nitride. This significantly reduces the rate at which impurities penetrate into the first inorganic compound layer 108a and the base film 102 through the second inorganic compound layer 108b, and suppresses increases in the dielectric constant and dielectric loss tangent of the base film 102. This makes it possible to prevent transmission loss and delays in signals from semiconductor chips mounted on the wiring board 100.

2. Modifications The structural features described above can be applied to various wiring boards. Hereinafter, wiring boards 120, 150, 160, and 170 having a different structure from wiring board 100 will be described as wiring boards according to this embodiment.

As shown in FIG. 4, the wiring board 120 has a base film 102 and multiple stacked connection wiring layers embedded in the base film 102. Here, an example is shown in which four connection wiring layers including a first connection wiring layer 122, a second connection wiring layer 124, a third connection wiring layer 126, and a fourth connection wiring layer 128 are stacked within the base film 102.

The first connection wiring layer 122 has first connection wirings 130a, 130b embedded in the base film 102. Similarly, the second connection wiring layer 124 has a second connection wiring 132 embedded in the base film 102, and the third connection wiring layer 126 has third connection wirings 134a, 134b embedded in the base film 102. The fourth connection wiring layer 128 is provided with a first wiring 104, similar to the wiring board 100, and a first protective film 108 is arranged so as to contact the first wiring 104 and the base film 102. The first wiring 104 is electrically connected to the lower wiring 112 via these connection wirings 130a, 132, 134a. As with the first wiring 104, in each connection wiring layer, the upper surface shape of the connection wirings 130a, 130b, 132, 134a, and 134b may be a shape that extends mainly in one dimension, a mesh shape, or may be substantially the same as the planar shape of the wiring substrate 100, as shown in FIGS. 2A, 2B, and 3. As an optional configuration, seed layers 136a, 136b, 138, 140a, and 140b may be provided on the bottom and side surfaces of each connection wiring 130a, 130b, 132, 134a, and 134b. In addition, a barrier layer may be formed under each seed layer 136a, 136b, 138, 140a, and 140b. The other configurations are the same as those of the wiring substrate 100, so a description thereof will be omitted.

Like the wiring board 100, the first protective film 108 of the wiring board 120 also has a first inorganic compound layer 108a, a second inorganic compound layer 108b, and a third inorganic compound layer 108c, so that the intrusion of impurities into the base film 102 is effectively suppressed, and an increase in the dielectric constant and dielectric loss tangent of the organic compounds contained in the base film 102 can be suppressed.

5 differs from the wiring board 120 in that a third protective film 152 having a structure similar to or similar to the first protective film 108 is formed on the connection wiring embedded in the base film 102. In the example shown here, the third protective film 152 is provided so as to cover the second connection wiring 132 of the second connection wiring layer 124. The third protective film 152 has a fourth inorganic compound layer 152a, a fifth inorganic compound layer 152b located on the fourth inorganic compound layer 152a and in contact with the fourth inorganic compound layer 152a, and a sixth inorganic compound layer 152c located on the fifth inorganic compound layer 152b and in contact with the fifth inorganic compound layer 152b. The fourth inorganic compound layer 152a, the fifth inorganic compound layer 152b, and the sixth inorganic compound layer 152c correspond to the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c of the first protective film 108, respectively, and can each have a similar structure.

By adopting such a structure, even if the number of connection wiring layers increases and the thickness of the base film 102 increases, it is possible to effectively prevent impurities from penetrating the base film 102, and it is possible to prevent a deterioration in the characteristics of the semiconductor chip mounted on the wiring board 150.

The third protective film 152 covering the connection wiring does not necessarily have to include the sixth inorganic compound layer 152c. This is because the first protective film 108 having a three-layer structure is formed on the first wiring 104. In this case, the fifth inorganic compound layer 152b contacts the base film 102.

The wiring board 160 shown in FIG. 6 has a structure different from the wiring board 150 in that the first protective film 108 also covers the side of the base film 102. In this structure, as shown in FIG. 6, the fourth inorganic compound layer 152a and the first inorganic compound layer 108a may be in contact. The first protective film 108 may cover the side of the substrate 116. Although not shown, the side of the base film 102 between the connection wiring layers 122, 124, 126, and 128 may not be located on the same plane. For example, the side of the base film 102 of one connection wiring layer may overlap the upper surface of the base film 102 of the connection wiring layer below it. By adopting such a structure, it is possible to more effectively prevent impurities from entering the base film 102, and therefore it is possible to suppress an increase in the dielectric constant and dielectric loss tangent of the organic compound contained in the base film 102, and to prevent a deterioration in the characteristics of the semiconductor chip to be mounted.

The wiring board 170 shown in FIG. 7 is different in structure from the wiring board 150 in that the lower wiring 112 is formed as a through wiring that penetrates the substrate 116. That is, the base film 102 and multiple connection wiring layers 122, 124, 126, 128 are formed on one surface (first surface) of the substrate 116, and the lower wiring 112 covers a part of this first surface, a part of the second surface opposite the first surface, and the side wall of the through hole 172 provided in the substrate 116. Similarly, the seed layer 114 covers a part of the first surface, a part of the second surface, and the side wall of the through hole 172. The lower wiring 112 and the first wiring 104 can be used to electrically connect the semiconductor chip and the main substrate.

As described above, the wiring boards 150, 160, and 170 shown in FIGS. 5 to 7 have a third protective film 152 that contacts one or more connection wirings (in the example shown here, the second connection wiring 132a) selected from the multiple connection wirings located inside the base film 102. That is, the metal such as copper contained in the connection wiring contacts the fourth inorganic compound layer 152a. In this case, if impurities penetrate into the base film 102, the surface of the connection wiring is oxidized, and the adhesion between the connection wiring and the fourth inorganic compound layer 152a is reduced. In addition, since the thermal expansion coefficients of the materials contained in these connection wirings and the fourth inorganic compound layer 152a are significantly different, peeling occurs due to the film stress generated between them.

However, as described above, by applying this embodiment, it is possible to effectively prevent impurities from entering the base film 102. This prevents oxidation of the connection wiring, and effectively prevents peeling between the connection wiring and the third protective film 152 inside the base film 102. This not only makes it possible to suppress transmission loss and delays in signals from a semiconductor chip mounted on a wiring board, but also makes it possible to improve the reliability of a semiconductor device including a semiconductor chip and a wiring board.

Second Embodiment
In this embodiment, a method for manufacturing the wiring substrate 170 shown in Fig. 7 will be described with reference to schematic cross-sectional views. Descriptions of configurations similar to or identical to those described in the first embodiment may be omitted.

First, through holes 172 are formed in the substrate 116 (FIG. 8(A)). When a glass substrate is used as the substrate 116, the through holes 172 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sandblasting or ultrasonic drilling. The number and size of the through holes 172 can be determined as desired according to the design of the wiring substrate 170.

After that, the seed layer 114 is formed so as to cover the sidewalls of the through-hole 172 and both sides (first side and second side) of the substrate 116 (FIG. 8(B)). The seed layer 114 can be formed by sputtering, CVD, electroless plating, vapor deposition, or the like. In particular, the seed layer 114 is formed efficiently by applying the sputtering method. Although not shown, before the formation of the seed layer 114, one or more layers of an insulating film containing an organic compound such as polyimide or polyamide, or an inorganic compound such as silicon oxide or silicon nitride, may be formed on the sidewalls of the through-hole 172 and both sides of the substrate 116.

Next, a resist mask 176 is formed on the first and second surfaces of the substrate 116 to protect the areas where the lower wiring 112 is not to be formed (FIG. 8(B)). The resist mask 176 may be formed by applying and hardening a liquid resist, but since the substrate 116 has through holes 172, it can be efficiently formed by attaching a film-like resist to the first and second surfaces and then performing exposure and development. Then, electricity is supplied to the seed layer 114 to perform electrolytic plating, and a metal film is formed on the seed layer 114 that is not covered by the resist mask 176, forming the lower wiring 112 (FIG. 8(C)).

Then, the resist mask 176 is removed, and the seed layer 114 exposed from the lower wiring 112 is removed by etching (FIG. 8(D)). An etchant containing an acid such as sulfuric acid can be used as the etchant.

Next, a part of the base film 102 is formed. Specifically, a polymer such as polyimide described in the first embodiment, or a solution or suspension of its precursor is applied onto the substrate 116, and then exposure using a photomask, development, and baking are performed to form the base film 102 having an opening 178 that exposes the lower wiring 112. Alternatively, the base film 102 may be formed by attaching a film of the polymer, and then exposure using a photomask, development, and baking. The thickness of the base film 102 formed at this stage is appropriately adjusted in the range of 0.5 μm to 5 μm.

Next, the seed layer 136 is formed by applying a sputtering method, a CVD method, or the like (FIG. 9(A)). The thickness of the seed layer 136 is appropriately selected in the range of 5 μm to 20 μm. The seed layer 136 is formed on the base film 102 so that a portion of the seed layer 136 covers the opening 178. Note that before forming the seed layer 136, a barrier layer (not shown) may be formed by using a sputtering method or the like so as to cover the opening 178 and the surface of the base film 102.

Next, similar to the formation of the lower wiring 112, a resist mask is formed, the first connection wiring 130 is formed by electrolytic plating, and then the seed layer 136 that is not covered by the first connection wiring 130 is removed by etching (Figure 9 (B)). If a barrier layer is formed, the barrier layer is removed at the same time as the seed layer 136. Through the steps up to this point, the first connection wiring layer 122 is formed. The same process is repeated to form the second connection wiring layer 124 (Figure 10 (A)).

Next, the third protective film 152 is formed. Specifically, a fourth inorganic compound layer 152a containing silicon nitride and a fifth inorganic compound layer 152b containing silicon oxide are formed in sequence by applying a plasma CVD method (FIG. 10B). After that, a base film 102 having an opening overlapping with the second connection wiring 132a is formed on the third protective film 152 (FIG. 11A). The thickness of the base film 102 formed at this time (the portion of the base film 102 above the third protective film 152) is appropriately selected from the range of 1 μm to 10 μm, taking into consideration the need to provide the first wiring 104 and the connection wiring with a characteristic impedance that is compatible with the semiconductor chip mounted on the wiring board 170.

Next, the third protective film 152 is removed by plasma etching in an opening provided in the uppermost base film 102 to expose the second connection wiring 132a. After that, using a method similar to that used to form the seed layer 136 and the first connection wiring 130a, the third connection wiring 134a, 134b and the seed layers 140a, 140b are formed (FIG. 11B). The same method is repeated to form the first wiring 104a, 104b and the seed layers 106a, 106b of the fourth connection wiring layer 128 (FIG. 12).

Next, the first protective film 108 is formed (FIG. 13). The first protective film 108 is formed by sequentially forming the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c using a plasma CVD method. Thereafter, similar to the formation of the base film 102 of the first connection wiring layer 122, the second protective film 110 having an opening overlapping the first wiring 104a is formed (FIG. 13), and then the first protective film 108 exposed in this opening is subjected to plasma etching to expose the first wiring 104a. For the plasma etching, for example, fluorine-containing alkanes or alkenes such as _CF4 and _CHF4 may be used.

Through the above steps, the wiring board 170 shown in Figure 7 can be formed.

Third Embodiment
In this embodiment, a semiconductor device using the wiring substrates 100, 120, 150, 160, and 170 described in the first embodiment will be described. For convenience, the semiconductor device using the wiring substrate 170 will be described as a representative example.

The semiconductor device 180 shown in FIG. 14 has a main substrate 182 and a plurality of wiring substrates 170 (wiring substrates 170-1, 170-2, 170-3) stacked thereon. There is no limit to the number of wiring substrates 170, and it is determined according to the performance required for the semiconductor device 180. The main substrate 182 is connected to various semiconductor chips (memory devices, central processing units) and semiconductor elements (microelectromechanical systems (MEMS), etc.) not shown. As described in the first embodiment, the wiring substrate 170 has lower wiring 112 that functions as through wiring, which contributes to the electrical connection in the vertical direction in the semiconductor device 180. The lower wiring 112 of the wiring substrate 170-1 in the bottom layer is electrically connected to the terminal 186 provided on the main substrate 182 via the bump 184-1. The stacked wiring substrates 170-1, 170-2, 170-3 are also electrically connected to each other by the bumps 184-2 and 184-3. Bump 184 includes metals such as indium, copper, or gold, or alloys such as solder.

As in the semiconductor device 190 shown in FIG. 15, the stacked wiring boards 170 may differ in size and shape, and the number of wiring boards 170 stacked on the main board 182 may also differ. In the example shown in FIG. 15, two wiring boards 170-4 and 170-5 are stacked in some areas, and three wiring boards 170-1, 170-2, and 170-3 are stacked in other areas.

The semiconductor device 200 shown in FIG. 16 has a structure in which multiple semiconductor chips 202-1, 202-2 are stacked on a main substrate 182 via a wiring substrate 170. Terminals 186 are formed on the semiconductor chips 172-1, 172-2, which are electrically connected to the lower wiring 112 of the wiring substrate 170 and the first wiring 104 via bumps 184. This electrically connects the semiconductor chips 202-1, 202-2 to each other. The semiconductor chip 202-2 and the main substrate 182 may also be electrically connected by wire wiring 206. In FIGS. 14 to 16, the lower wiring 112 functioning as a through wiring is shown to be directly connected to the bumps 184, but other wiring such as lead wiring may be provided between the bumps 184 and the lower wiring 112.

In this example, the results of a reliability test performed on the wiring board of the first embodiment are described. The wiring board used was wiring board 170 (see FIG. 7), and the thicknesses of the fourth inorganic compound layer 152a and the fifth inorganic compound layer 152b were 0.1 μm and 2.0 μm, respectively. The thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c were 0.1 μm, 0.5 μm, and 0.4 μm, respectively.

The fabricated wiring board was left to stand for 96 hours under conditions of a temperature of 130°C and a humidity of 85%, and then the first wiring 104 and the connection wirings 130a, 130b, 132, 134a, and 134b were observed using an optical microscope. As a result, no peeling was observed between the second connection wiring 132 and the fourth inorganic compound layer 152a, regardless of the wiring shape or width.

In contrast, when a wiring board having the same structure as wiring board 170 but without first protective film 108 was used as a comparative example, it was confirmed that the surfaces of all of the above wirings, regardless of their width or shape, were discolored red. This suggests that the wirings were oxidized by impurities that had invaded from the outside. In addition, it was confirmed that peeling did not occur between second connection wiring 132 and fourth inorganic compound layer 152a in areas where the wiring width was small (for example, wiring with a width of 10 μm or less, or mesh-like wiring with a width of 5 μm), but peeling occurred in other areas.

As shown in this example, it was confirmed that by applying a protective film having a three-layer structure, it is possible to provide a highly reliable wiring board.

The above-described embodiments of the present disclosure may be implemented in any suitable combination, provided they are not mutually inconsistent. In addition, any embodiment in which a person skilled in the art appropriately adds or deletes components or modifies the design is also included in the scope of the present disclosure, so long as it satisfies the gist of the present disclosure.

Furthermore, even if there are other effects and advantages different from those brought about by the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by this disclosure.

100: wiring substrate, 102: base film, 104: first wiring, 104a: first wiring, 104b: first wiring, 106: seed layer, 106a: seed layer, 106b: seed layer, 108: first protective film, 108a: first inorganic compound layer, 108b: second inorganic compound layer, 108c: third inorganic compound layer, 110: second protective film, 112: lower wiring, 114: seed layer, 116: substrate, 118: undercoat, 120: wiring substrate, 122: first connection wiring layer, 124: second connection wiring layer, 126: third connection wiring layer, 128: fourth connection wiring layer, 130: first connection wiring, 130a: first connection wiring, 130b: first connection wiring, 132: second connection wiring, 13 2a: second connection wiring, 134: third connection wiring, 134a: third connection wiring, 134b: third connection wiring, 136: seed layer, 136a: seed layer, 136b: seed layer, 138: seed layer, 140a: seed layer, 140b: seed layer, 150: wiring board, 152: third protective film, 152a: fourth inorganic compound layer, 152b: fifth inorganic compound layer, 152c: sixth inorganic compound layer, 160: wiring board, 170: wiring board, 172: through hole, 176: resist mask, 178: opening, 180: semiconductor device, 182: main board, 184: bump, 186: terminal, 188: bump, 190: semiconductor device, 200: semiconductor device, 202: semiconductor chip, 206: wire wiring

Claims (21)

substrate,
a plurality of wiring layers laminated on the substrate; and a first protective film on the plurality of wiring layers,
Each of the plurality of wiring layers is
an organic film having a through hole; and a connection wiring disposed in the through hole,
The first protective film is
A first inorganic compound layer;
a second inorganic compound layer on the first inorganic compound layer; and a third inorganic compound layer on the second inorganic compound layer,
the first protective film covers side surfaces of the organic film of the plurality of wiring layers and has an opening exposing the connection wiring of the uppermost wiring layer. The wiring board according to claim 1, wherein the thickness of the third inorganic compound layer is greater than the thickness of the first inorganic compound layer and less than the thickness of the second inorganic compound layer. The wiring board according to claim 1, wherein the connection wiring is electrically connected between the adjacent wiring layers. 2. The wiring board according to claim 1, wherein the organic film has a dielectric loss tangent of 1×10 ⁻⁴ or more and 1×10 ⁻² or less. The wiring board according to claim 1, wherein the organic film includes polyimide. The wiring board according to claim 1, further comprising a lower wiring between the substrate and the plurality of wiring layers, the lowermost wiring being electrically connected to the connection wiring of the wiring layer. The wiring board according to claim 6, wherein the lower wiring penetrates the board. the first inorganic compound layer and the third inorganic compound layer contain nitrogen and silicon;
The wiring board according to claim 1 , wherein the second inorganic compound layer contains oxygen and silicon. The wiring board according to claim 1, further comprising a second protective film between adjacent wiring layers. The wiring board according to claim 9, wherein the second protective film includes a fourth inorganic compound layer and a fifth inorganic compound layer stacked together. forming an organic film having a through hole on a substrate and forming a connection wiring in the through hole, alternately stacking a plurality of wiring layers each having the organic film and the connection wiring;
forming a first protective film on the plurality of wiring layers so as to cover side surfaces of the organic film of the plurality of wiring layers; and forming a first protective film having an opening for exposing the connection wiring of the uppermost wiring layer,
The first protective film is
A first inorganic compound layer;
a second inorganic compound layer on the first inorganic compound layer, and a third inorganic compound layer on the second inorganic compound layer. The method of claim 11, wherein the thickness of the third inorganic compound layer is greater than the thickness of the first inorganic compound layer and less than the thickness of the second inorganic compound layer. The method of claim 11, wherein the stacking of the wiring layers is performed so that the connection wiring is electrically connected between the adjacent wiring layers. The method according to claim 11, wherein the organic film has a dielectric loss tangent of 1×10 ⁻⁴ or more and 1×10 ⁻² or less. The method of claim 11, wherein the organic film includes polyimide. The method further includes forming a lower wiring on the substrate before stacking the plurality of wiring layers;
The manufacturing method according to claim 11 , wherein the lower wiring is electrically connected to the connection wiring of the lowermost wiring layer. The method further includes forming a through hole in the substrate before forming the lower wiring;
The method of claim 16 , wherein the underlying interconnect is formed in the through hole of the substrate. the first inorganic compound layer and the third inorganic compound layer contain nitrogen and silicon;
The method of claim 11 , wherein the second inorganic compound layer comprises oxygen and silicon. The method of claim 11 further comprising forming a second protective film between adjacent wiring layers. The method of claim 19, wherein the second protective film includes a fourth inorganic compound layer and a fifth inorganic compound layer stacked together. The method according to claim 11, wherein the organic film is formed using a polymer film.

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