JP7694064B2 - Data processing device, data processing method and program - Google Patents

Description

The present disclosure relates to a data processing device, a data processing method, and a program.

As semiconductor devices become more highly integrated and miniaturized, there has been a sharp increase in transient bit errors (soft errors) in memory. Soft errors are caused by collisions with alpha particles or cosmic ray neutrons, for example. When memory susceptible to soft errors is used in a system, the soft errors can cause the system to temporarily stop working.

Technologies have been developed to avoid temporary system shutdowns due to soft errors. For example, Japanese Patent No. 6733843 (Patent Document 1) discloses a data processing device equipped with a processing unit that writes and reads specified variables to memory. When the processing unit receives a write instruction, it writes data indicating the value of the specified variable to each of three areas of the memory. This results in triplicate data in the memory, and even if a soft error occurs in one piece of data, processing can continue using the remaining two pieces of data.

Patent No. 6733843

In the technology described in Patent Publication No. 6733843, when a read instruction is received, the processing unit sequentially reads data from each of the three areas in the memory. Then, the read data is used to sequentially execute arithmetic processing. As a result, the same arithmetic processing is executed three times repeatedly, which lengthens the time required for the arithmetic processing. In other words, the processing speed decreases.

The present disclosure has been made in consideration of the above problems, and its purpose is to provide a data processing device, a data processing method, and a program that are capable of continuing operation even if a soft error occurs and that can suppress a decrease in processing speed.

According to an example of the present disclosure, a data processing device that executes at least one arithmetic process includes first to Nth arithmetic units and a memory. N is an integer equal to or greater than 3. One of the first to Nth arithmetic units is a main arithmetic unit. The memory has first to Nth areas in which identical data is stored. The first to Nth arithmetic units each execute at least one arithmetic process using the data stored in the first to Nth areas. The main arithmetic unit compares the arithmetic results of the first to Nth arithmetic units for each of the at least one arithmetic process. The main arithmetic unit continues the operation of the first to Nth arithmetic units in response to a match between a predetermined number or more of the arithmetic results of the first to Nth arithmetic units. In response to a mismatch between the arithmetic results of the first arithmetic unit and the arithmetic results of the second to Nth arithmetic units, the main arithmetic unit rewrites at least a portion of the data in the first area so that it matches any of the data in the second to Nth areas.

According to this disclosure, the first to Nth calculation units can execute calculation processes in parallel using the first to Nth areas of the memory, which prevents the processing time required for calculation from increasing. In other words, the decrease in processing speed is prevented.

Furthermore, the calculation results of the first to Nth calculation units are compared, and if a predetermined number or more of the calculation results match, the operation of the first to Nth calculation units continues. Therefore, even if a soft error occurs and the calculation results are less than the predetermined number and do not match other calculation results, it is possible to continue operation.

Furthermore, if the calculation result of the first calculation unit does not match the calculation results of the second to Nth calculation units, it is presumed that a soft error has occurred in the first region. Therefore, in response to a mismatch between the calculation result of the first calculation unit and the calculation results of the second to Nth calculation units, at least a portion of the data in the first region is rewritten to match any of the data in the second to Nth regions. In this way, data corrupted by a soft error is restored to correct data, thereby suppressing temporary system shutdowns caused by soft errors.

In this way, even if a soft error occurs, operation can continue and a decrease in processing speed can be suppressed.

In the above disclosure, the main calculation unit rewrites all data in the first area so that it matches all data in any of the second to Nth areas in response to a mismatch between the calculation results of the first calculation unit and the calculation results of the second to Nth calculation units.

According to the above disclosure, the data in the first region where a soft error is presumed to have occurred is rewritten so that it matches all of the data in any of the second through Nth regions. This allows the data corrupted by the soft error to be restored to the correct data.

In the above disclosure, at least one arithmetic process includes multiple arithmetic processes. Each of the first to Nth regions has multiple sub-regions that respectively store data to be overwritten by the execution of the multiple arithmetic processes. The main arithmetic unit identifies a target sub-region among the multiple sub-regions that corresponds to a target arithmetic process in response to a mismatch between the arithmetic results of the first arithmetic unit and the arithmetic results of the second to Nth arithmetic units for a target arithmetic process among the multiple arithmetic processes. The main arithmetic unit rewrites the data in the target sub-region used by the first arithmetic unit so that it matches the data in the target sub-region used by any of the second to Nth arithmetic units.

According to the above disclosure, a target sub-area in the first area in which a soft error is presumed to have occurred is identified. Then, the data in the target sub-area is repaired to the correct data. As a result, the time required to repair the data is reduced compared to when all data in the first area is rewritten.

In the above disclosure, each of the multiple sub-regions is divided into multiple blocks. The main calculation unit calculates an error detection code for each of the multiple blocks of the target sub-region. The main calculation unit identifies a target block, among the multiple blocks of the target sub-region, for which the error detection code does not match between the target sub-region used by the first calculation unit and the target sub-regions used by the second to Nth calculation units. The main calculation unit rewrites the data of the target block used by the first calculation unit so that it matches the data of the target block used by the second to Nth calculation units.

According to the above disclosure, a target block in the target sub-area in which a soft error is estimated to have occurred is identified. Then, the data in the target block is repaired to the correct data. As a result, the time required to repair the data is further reduced compared to when all data in the target sub-area is rewritten.

In the above disclosure, the first to Nth calculation units write the calculation results to the first to Nth areas, respectively. In response to a mismatch between the calculation results of the first calculation unit and the calculation results of the second to Nth calculation units, the main calculation unit rewrites the calculation result written in the first area so that it matches the calculation results of the second to Nth calculation units.

According to the above disclosure, only the calculation results are repaired. This further reduces the time required for repair. Even when only the calculation results are repaired, data that has been corrupted due to a soft error can be repaired, as described below.

In the above disclosure, each of the first to Nth regions has a first sub-region and a second sub-region in which the same data is written. Each of the first to Nth arithmetic units reads data from one of the first sub-region and the second sub-region to execute at least one arithmetic process. Each of the first to Nth arithmetic units updates data in both the first sub-region and the second sub-region in response to the execution of the at least one arithmetic process. The at least one arithmetic process includes a first arithmetic process and a second arithmetic process executed after the first arithmetic process. In response to a result of the first arithmetic process performed by the first arithmetic unit using the data in the first sub-region not matching a result of the first arithmetic process performed by the second to Nth arithmetic units using the data in the first sub-region, the main arithmetic unit switches the region from which the first arithmetic unit reads data in the second arithmetic process from the first sub-region to the second sub-region. The main calculation unit rewrites at least a portion of the data in the first region to match the data in the second to Nth regions in response to a calculation result of the second calculation process by the first calculation unit using the data in the second sub-region not matching the calculation result of the second calculation process by the second to Nth calculation units using the data in the first sub-region.

According to the above disclosure, even if the result of the calculation by the first calculation unit using the first sub-region is inconsistent with the result of the calculation by the second to Nth calculation units using the first sub-region, data repair is not performed. Therefore, the frequency of data repair processing can be reduced. In other words, the frequency with which the execution of the calculation processing is put on hold in order to repair data can be reduced. Furthermore, as described below, depending on the content of the calculation processing, data corrupted by a soft error can be automatically repaired by normal calculation processing.

According to an example of the present disclosure, the data processing method of the data processing device includes first to fourth steps. The first step is a step in which the first to Nth calculation units each execute at least one calculation process using the data stored in the first to Nth areas. The second step is a step in which the main calculation unit compares the calculation results by the first to Nth calculation units for each of the at least one calculation process. The third step is a step in which the main calculation unit continues the operation of the first to Nth calculation units in response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units. The fourth step is a step in which the main calculation unit rewrites at least a portion of the data in the first area so that it matches any of the data in the second to Nth areas in response to a mismatch between the calculation results of the first calculation unit and the calculation results of the second to Nth calculation units.

According to one example of the present disclosure, the program is a computer-readable program that causes the first to Nth calculation units to execute the above data processing method.

These disclosures also make it possible to continue operation even if a soft error occurs, and to prevent a decrease in processing speed.

According to the present disclosure, even if a soft error occurs, operation can be continued and a decrease in processing speed can be suppressed.

FIG. 2 is a schematic diagram illustrating a configuration of a safety IO unit according to an embodiment. FIG. 1 is a diagram illustrating an example of a method for repairing a soft error. 1 is a schematic diagram showing an overall configuration of a control system according to an embodiment; FIG. 2 is a schematic diagram illustrating an example of a hardware configuration of a safety IO unit. 11A and 11B are diagrams illustrating a second example of a method for recovering data in a region to be recovered. 13A and 13B are diagrams illustrating a third example of a method for repairing data in a repair target area. FIG. 13 is a diagram showing an example of a state of the main memory when the arithmetic processing "process A" is terminated. FIG. 8 is a diagram showing a state of restoration processing after the calculation processing "process A" shown in FIG. 7; FIG. 9 is a diagram showing an example of a state of the main memory when a calculation process "process B" is executed after the restoration process shown in FIG. 8. FIG. 10 is a diagram showing the state of restoration processing after the calculation processing "process B" shown in FIG. 9; FIG. 13 is a diagram showing another example of the state of the main memory when the arithmetic processing "process A" is terminated. FIG. 12 is a diagram showing the state of the collation process after the calculation process "process A" shown in FIG. 11. 13 is a diagram showing an example of a state of the main memory 104 when a calculation process "process B" is executed after the matching process shown in FIG. 12. FIG. 14 is a diagram showing an example of a state of the main memory when the arithmetic process "process C" is executed after the arithmetic process "process B" shown in FIG. 13. FIG. 14 is a diagram showing an example of a state of the main memory when the arithmetic process "process C'" is executed after the arithmetic process "process B" shown in FIG. 13. FIG. 16 is a diagram showing the state of the matching and repair process after the calculation process “process C′” shown in FIG. 15 .

The embodiment of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings will be given the same reference numerals and their description will not be repeated.

§1 Application Examples In various fields such as aerospace systems, automobiles, medical devices, communication devices, and industrial devices, it is desirable to suppress temporary system shutdowns caused by memory soft errors. The present disclosure can be applied to systems in such various fields. In the following, a safety IO unit incorporated in a control system in the FA (factory automation) field will be described as an application example of a data processing device. However, application examples of the data processing device are not limited to safety IO units incorporated in control systems.

An example of a situation in which the present invention is applied will be described with reference to Figures 1 and 2. Figure 1 is a schematic diagram showing the configuration of a safety IO unit 100 according to an embodiment. The safety IO unit 100 is an example of a data processing device. The safety IO unit 100 receives an input signal from a safety device and provides the input signal to a PLC (programmable logic controller). The safety IO unit 100 periodically executes at least one arithmetic process using the input signal received from the safety device, etc.

As shown in FIG. 1, the safety IO unit 100 includes a multi-core processor 102 and a main memory 104.

The multi-core processor 102 is a processor equipped with multiple cores. The number of cores, N, is an integer equal to or greater than 3. In the example shown in FIG. 1, the multi-core processor 102 has three cores, 11, 12, and 13.

Each of cores 11, 12, and 13 operates as a calculation unit that executes at least one of the above-mentioned calculation processes. Core 11 is a master core that operates as a main calculation unit. Cores 12 and 13 operate as slave cores. Cores 12 and 13 stop and resume operation in response to instructions from core 11.

The main memory 104 is composed of a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). SRAM uses flip-flops as the storage structure, and has the advantage that it does not require a refresh operation and can operate faster than DRAM. For this reason, it is preferable to use an SRAM as the main memory 104.

DRAMs with a stacked structure have high soft error resistance. On the other hand, SRAMs with a flip-flop structure have a lower soft error resistance due to miniaturization. Therefore, when using a main memory 104 made of highly integrated SRAMs to increase capacity, soft errors are likely to occur in the main memory 104. In the following description, it is assumed that the main memory 104 is an SRAM.

The main memory 104 has the same number of areas as the number N of cores of the multi-core processor 102, in which the same data is stored. In the example shown in FIG. 1, the main memory 104 has three areas 21, 22, and 23.

Cores 11, 12, and 13 each execute the same arithmetic processing using data stored in areas 21, 22, and 23. FIG. 1 shows cores 11, 12, and 13 each executing arithmetic processing "Process A" using data in areas 21, 22, and 23. Because cores 11, 12, and 13 each use data stored in areas 21, 22, and 23, the arithmetic processing of cores 11, 12, and 13 is executed in parallel. This makes it possible to avoid an increase in the time required for arithmetic processing. In other words, a decrease in processing speed is suppressed.

Core 11, which is the main calculation unit, collates the calculation results by cores 11 to 13 for each calculation process. The calculation results by cores 11 to 13 are written to areas 21 to 23, respectively. Core 11 simply collates the calculation results written in areas 21 to 23.

In the example shown in FIG. 1, cores 11 and 12 execute the calculation process "process A" using data in areas 21 and 22, respectively, and write the calculation result (=9) to areas 21 and 22. Core 13 also executes the calculation process "process A" using data in area 23, and writes the calculation result to area 23. However, a soft error has occurred in area 23, causing corruption (garbled data) in the data used to execute the calculation process "process A". Therefore, the calculation result (=15) by core 13 differs from the calculation result (=9) by cores 11 and 12.

Core 11 determines whether or not a predetermined number or more of the calculation results of cores 11 to 13 match. The predetermined number is an integer that is a majority of the number N of cores in multi-core processor 102.

When a predetermined number or more of the calculation results match, it is presumed that the calculation result was generated using data that did not contain a soft error. Therefore, core 11 allows cores 11 to 13 to continue operation in response to a predetermined number or more of the calculation results of cores 11 to 13 matching. For example, when N=3, core 11 allows cores 11 to 13 to continue operation in response to two or more of the calculation results of cores 11 to 13 matching.

When core 11 outputs a calculation result to the outside, it outputs a predetermined number or more of the calculation results of cores 11 to 13 that match. Alternatively, when core 11 outputs a command corresponding to the calculation result to the outside, it outputs a command corresponding to a predetermined number or more of the calculation results of cores 11 to 13 that match.

If a predetermined number or more of the calculation results do not match, it is not possible to estimate the calculation results generated using data that is not affected by soft errors. Therefore, core 11 stops the operation of cores 11 to 13 in response to a predetermined number or more of the calculation results of cores 11 to 13 not matching.

Furthermore, in response to the fact that the operation result less than the predetermined number does not match the operation result equal to or greater than the predetermined number, the core 11 rewrites at least a portion of the data in the area in which the operation result that does not match the operation result equal to or greater than the predetermined number is written so that the data matches any of the data in the other areas. This makes it possible to repair data that has been corrupted by a soft error.

Figure 2 is a diagram showing an example of a method for repairing a soft error. In response to a discrepancy between the calculation result of core 13 (=15) and the calculation results of cores 11 and 12 (=9), core 11 rewrites at least a portion of the data in region 23 corresponding to core 13 so that it matches the data in either region 21 or 22. In the example shown in Figure 2, core 11 rewrites the data in region 23 so that it matches the data in region 21. In other words, core 11 copies the data in region 21 to region 23. In this way, even if a soft error occurs in one of the three regions 21 to 23, the data in the region where the soft error occurred can be repaired.

In this way, according to this embodiment, N (N is an integer equal to or greater than 3) arithmetic units (cores) execute arithmetic processing using N areas of the main memory 104, so that the processing time required for the calculation is prevented from increasing. In other words, the decrease in processing speed is prevented.

Furthermore, the N calculation results are compared, and if a predetermined number or more of the calculation results match, the operation of the N calculation units (cores) continues. Therefore, operation can continue even if a soft error occurs.

Furthermore, in response to a mismatch between the calculation result (=15) of core 13 and the calculation results (=9) of cores 11 and 12, at least a portion of the data in area 23 corresponding to core 13 is rewritten to match the data in either area 21 or 22. In this way, data corrupted by a soft error is restored to the correct data, thereby preventing temporary system shutdowns caused by soft errors.

§2 Specific example <Overall configuration of the control system>
Fig. 3 is a schematic diagram showing an overall configuration of a control system according to an embodiment. The control system 1 illustrated in Fig. 3 includes, as main components, one or more safety IO units 100, a standard PLC 200, a safety PLC 300, and one or more couplers 400. These devices included in the control system 1 are data processing devices that execute various types of arithmetic processing.

The standard PLC 200 executes standard control of any control object according to a pre-created standard control program. "Standard control" is a general term for processing to control a control object according to pre-defined required specifications. Control objects are, for example, servo motors, robots, etc.

The safety PLC 300 executes safety control for any control object, independent of the standard PLC 200. The safety PLC 300 illustrated in FIG. 3 is connected to the standard PLC 200 via a local bus. "Safety control" is a general term for processing to prevent human safety from being threatened by equipment, machinery, etc. "Safety control" is designed to meet the requirements for realizing safety functions stipulated in, for example, IEC 61508.

The coupler 400 mediates data exchange between the standard PLC 200 and the safety IO unit 100. The coupler 400 is electrically connected to the standard PLC 200 via the field network 2. The field network 2 is a communication medium for realizing data transmission for FA. In the field network 2, frame transmission is possible at a predetermined cycle, and the data arrival time for each node in the network is guaranteed. As an example of a protocol that guarantees such data arrival time, EtherCAT (registered trademark) is adopted for the field network 2 in the control system 1 according to the present embodiment.

The coupler 400 transmits data received from the standard PLC 200 to the safety IO unit 100, and when it receives data from the safety IO unit 100, it prepares to store the received data in the next arriving frame.

The safety IO unit 100 is connected to the safety PLC 300 or the coupler 400 via a local bus. In addition, any safety device (not shown) is connected to the safety IO unit 100. The safety devices include a light curtain, an emergency stop button, a safety door switch, etc.

The safety IO unit 100 receives an input signal from a safety device and provides the input signal to the safety PLC 300. Alternatively, the safety IO unit 100 receives an input signal from a safety device and provides the input signal to the standard PLC 200 via the coupler 400. The input signal provided to the standard PLC 200 is provided to the safety PLC 300.

Furthermore, the safety IO unit 100 outputs an output signal to a safety device in response to a command from the safety PLC 300. Alternatively, the safety IO unit 100 outputs an output signal to a safety device in response to a command from the safety PLC 300 via the coupler 400 and the standard PLC 200.

The safety IO unit 100 performs calculations related to receiving input signals from safety devices, providing the input signals, outputting output signals to the safety devices, etc. at predetermined intervals.

The safety PLC 300 executes safety control in response to an input signal provided from the safety IO unit 100. For example, when an input signal indicating a human intrusion is provided from a safety device that is a light curtain, the safety PLC 300 cuts off the power supply to the control target of the standard PLC 200 and temporarily stops the control system 1. Alternatively, when an input signal indicating a button press is provided from a safety device that is an emergency stop button, the safety PLC 300 cuts off the power supply to the control target of the standard PLC 200 and temporarily stops the control system 1.

In this way, the safety IO unit 100 is directly involved in safety control to prevent threats to human safety. Therefore, the safety PLC 300 is designed to temporarily stop the control system 1 even if a failure or abnormality occurs in the safety IO unit 100.

If a soft error occurs in the main memory 104 of the safety IO unit 100 and the safety IO unit 100 continues to operate without repairing the damaged data, the safety PLC 300 will not be able to properly execute safety control. Therefore, even if a soft error occurs, the safety IO unit 100 has the function of continuing operation and repairing the damaged data.

<Hardware configuration of safety IO unit>
Fig. 4 is a schematic diagram showing an example of the hardware configuration of a safety IO unit. The safety IO unit 100 shown in Fig. 4 includes a storage 110, a local bus controller 120, and a safety IO module 130 in addition to the multi-core processor 102 and main memory 104 described above. These components are connected via a processor bus 140.

Storage 110 is composed of a non-volatile storage device such as a solid state drive (SSD) or a hard disk drive (HDD). Executable program 111 for implementing IO functions and a comparison and repair program 112 are stored in storage 110.

The local bus controller 120 exchanges data with devices (e.g., safety PLC 300, coupler 400) to which the safety IO unit 100 is connected via the local bus.

The safety IO module 130 is electrically connected to the safety device, and accepts inputs such as detection results from the safety device and outputs signals to the safety device.

<Running an executable program>
The cores 11 to 13 (see FIG. 1) of the multi-core processor 102 execute in parallel an executable program 111. The cores 11 to 13 execute the executable program 111 using the areas 21 to 23 (see FIG. 1) of the main memory 104, respectively.

Cores 11 to 13 execute executable program 111 at each predetermined control period. Executable program 111 defines at least one computational process. Therefore, cores 11 to 13 periodically execute at least one computational process defined by executable program 111.

<Computation results verification and data recovery>
The core 11, which is the main calculation unit, executes the matching and repair program 112 every time the calculation processing by the cores 11 to 13 is completed.

Specifically, core 11 compares three calculation results obtained by the execution of calculation processes by cores 11 to 13. The three calculation results are written to areas 21 to 23 of main memory 104, respectively. Therefore, core 11 compares the calculation results written to areas 21 to 23. Note that core 11 instructs cores 12 and 13 to suspend processing while it is comparing the calculation results.

As a result of the comparison, the following patterns (1) to (3) are possible.
(1) The results of the three calculations are the same.
(2) Two of the calculation results match, and the remaining calculation result differs from the two above calculation results.
(3) The results of the three calculations are different from each other.

In the case of pattern (1), it is estimated that no soft error has occurred in the main memory 104. Therefore, core 11 determines that data recovery is not necessary, and starts the next calculation process while instructing cores 12 and 13 to start the next calculation process.

In the case of pattern (3), it is estimated that a soft error has occurred in at least two of areas 21 to 23 of the main memory 104. In this case, it is difficult to identify which of areas 21 to 23 has not experienced a soft error. Therefore, the core 11 determines that the safety IO unit 100 is in an abnormal state, and outputs an abnormality signal to the safety PLC 300. Upon receiving the abnormality signal, the safety PLC 300 cuts off the power supply to the controlled object of the standard PLC 200, and temporarily stops the control system 1.

Soft errors occur infrequently. Therefore, it is unlikely that soft errors will occur at two locations in main memory 104 at approximately the same time. Therefore, in the case of pattern (2), it is expected that no soft errors have occurred in the two areas in which matching calculation results are written. On the other hand, it is estimated that a soft error has occurred in an area of areas 21 to 23 in which a calculation result different from the calculation results of the two areas is written (hereinafter referred to as the "area to be repaired"). Therefore, core 11 determines that the data in the area to be repaired needs to be repaired, and executes a repair process for the data in the area to be repaired. After completing the data repair process, core 11 starts the next calculation process and instructs cores 12 and 13 to start the next calculation process.

To identify the bit in the repair target area where a soft error has occurred, it is necessary to compare all bits in the repair target area with the remaining two areas. This comparison process takes time. Therefore, the core 11 rewrites at least a portion of the data in the repair target area so that it matches the data in one of the remaining two areas, without performing this comparison process. An example of a method for repairing data in the repair target area is described below.

(First Example of Method for Restoring Data in a Region to be Restored)
The core 11 may rewrite all the data in the repair target area so that it matches all the data in any area other than the repair target area. This allows both the data corrupted (garbled) by the soft error and the operation result written in the repair target area to be repaired to the correct content.

(Second Example of Method for Restoring Data in a Region to be Restored)
In the first example, both the data corrupted by the soft error and the calculation result are restored to the correct contents. However, since all data in the area to be repaired is rewritten, the time required for the repair is long. During the repair, the next calculation process is not started. Therefore, even if an input signal indicating a human intrusion is provided from a safety device such as a light curtain, the transfer of the input signal from the safety IO unit 100 to the safety PLC 300 is delayed. In consideration of such a delay time, it becomes necessary to set a long safety distance. Specifically, the distance between the equipment and the light curtain is set long. This increases the scale of the production line including the equipment and the light curtain.

Therefore, in the second example, core 11 rewrites only a portion of the data in the area to be repaired so that it matches the data in one of the remaining two areas.

Figure 5 is a diagram illustrating a second example of a method for repairing data in an area to be repaired. As shown in Figure 5, each of areas 21, 22, and 23 of main memory 104 has multiple subareas corresponding to multiple arithmetic processes, respectively. Area 21 has subareas 21a to 21x corresponding to arithmetic processes "Process A" to "Process X", respectively. Similarly, area 22 has subareas 22a to 22x corresponding to arithmetic processes "Process A" to "Process X", respectively. Area 23 has subareas 23a to 23x corresponding to arithmetic processes "Process A" to "Process X", respectively. A set of variables used for the corresponding arithmetic process is written into each subarea.

Core 11 identifies a target sub-area among the multiple sub-areas that corresponds to a target computation process among the multiple computation processes when the computation results of cores 11 to 13 satisfy the above pattern (2). For example, if the computation results of computation process "process A" by cores 11 and 12 match, and the computation result of computation process "process A" by core 13 does not match the computation result of computation process "process A" by cores 11 and 12, sub-areas 21a to 23a are identified as the target sub-area.

Core 11 rewrites the data in the target sub-area corresponding to the core that generated the inconsistent calculation result with the two matching calculation results so that it matches the data in the target sub-area corresponding to one of the remaining two cores. For example, if the calculation result of the calculation process "process A" by core 13 does not match the calculation result of the calculation process "process A" by cores 11 and 12, the data in sub-area 23a is rewritten to match the data in sub-area 21a.

If the calculation result of the calculation process "process A" by core 13 does not match the calculation result of the calculation process "process A" by cores 11 and 12, it is presumed that a soft error has occurred in sub-area 23a that stores the variables used in the calculation process "process A" by core 13. The data in sub-area 23a is rewritten so that it matches the data in sub-area 21a, and the data corrupted by the soft error is restored to the correct data.

The data is rewritten not in the entire area 23, but only in sub-area 23a, which is a part of area 23. This reduces the time required for repairs. As a result, for example, the increase in the scale of the production line, including the equipment and the light curtain, is suppressed.

(Third Example of Method for Restoring Data in Restoration Target Area)
The third example of the method for repairing data in the repair target area is a modification of the above-mentioned second example. Each sub-area is divided into a plurality of blocks in advance.

Figure 6 is a diagram illustrating a third example of a method for repairing data in an area to be repaired. Figure 6 shows a method for repairing data in an area to be repaired when the calculation result of the calculation process "process A" by core 13 does not match the calculation result of the calculation process "process A" by cores 11 and 12. Sub-area 21a is divided into a plurality of blocks 31_1, 31_2, ..., 31_M. Sub-area 22a is divided into a plurality of blocks 32_1, 32_2, ..., 32_M. Sub-area 23a is divided into a plurality of blocks 33_1, 33_2, ..., 33_M.

As shown in FIG. 6, the core 11 calculates the error detection code CRC for each of the multiple blocks 31_1 to 31_M, 32_1 to 32_M, and 33_1 to 33_M in the subareas 21a, 22a, and 23a (target subareas) corresponding to the computation process "Process A."

Core 11 identifies a target block among the multiple blocks in the target sub-area for which the error detection code CRC does not match between sub-area 23a used by core 13 and sub-areas 21a and 22a used by cores 11 and 12. For example, if the error detection code CRC of block 33_1 does not match the error detection code CRC of blocks 31_1 and 32_1, blocks 31_1, 32_1, and 33_1 are identified as the target blocks.

Core 11 rewrites the data of the target block used by core 13 so that it matches the data of the target block used by cores 11 and 12. For example, core 11 rewrites the data of block 33_1 used by core 13 so that it matches the data of either block 31_1 or 32_1 used by cores 11 and 12.

In blocks where the error detection code CRC matches between the sub-area 23a used by core 13 and the sub-areas 21a and 22a used by cores 11 and 12, it is presumed that no soft errors have occurred. Therefore, such blocks are excluded from the targets for which data is rewritten. In other words, the targets for which data is rewritten are limited to only block 33_1 in sub-area 23a, whose error detection code CRC does not match blocks 31_1 and 32_1. As a result, the time required for repair is further reduced.

(Fourth Example of Method for Restoring Data in a Restoration Target Area)
7 to 10, a fourth example of the method for recovering data in a region to be recovered will be described. In the fourth example, in response to a discrepancy between the calculation result of a certain core (e.g., core 13) and the calculation result of the remaining cores (e.g., cores 11 and 12), core 11 rewrites the calculation result of the certain core in main memory 104 so that the calculation result of the certain core matches the calculation result of the remaining core.

7 is a diagram showing an example of the state of the main memory when the arithmetic process "process A" is completed. In the example shown in Fig. 7, a soft error occurs in area 23 of the main memory 104, and the variable a changes from "1" to "3". The arithmetic process "process A" is a process for updating the variable x according to the following formula (1).
x=(a+b)*c...Formula (1).

As shown in FIG. 7, cores 11 and 12 read variables (variables a, b, c) used in the calculation from areas 21 and 22, respectively, and update variable x in areas 21 and 22 from "5" to "9" by executing calculation process "Process A". Similarly, core 13 reads variables a, b, c used in the calculation from area 23, and updates variable x in area 23 by executing calculation process "Process A". As mentioned above, data corruption has occurred in variable a in area 23. Therefore, core 13 updates variable x in area 23 from "5" to "15".

Figure 8 is a diagram showing the state of the restoration process after the calculation process "process A" shown in Figure 7. As shown in Figure 8, core 11 collates the calculation results of the calculation process "process A" by cores 11, 12, and 13. In response to the fact that the calculation result "15" by core 13 differs from the calculation result "9" by cores 11 and 12, core 11 rewrites the calculation result "15" written in area 23 to the calculation result "9" written in areas 21 and 22. As a result, the variable x, which is the calculation result of the calculation process "process A", is restored to the correct value in area 23.

Note that core 11 does not verify the reason why the calculation result "15" by core 13 differs from the calculation result "9" by cores 11 and 12. Therefore, core 11 does not recognize that data corruption has occurred in variable a in area 23, and does not repair variable a.

Fig. 9 is a diagram showing an example of the state of the main memory when the calculation process "process B" is executed after the restoration process shown in Fig. 8. The calculation process "process B" is a process for updating the variable a according to the following formula (2).
a = a + 1... equation (2).

As shown in FIG. 9, cores 11 and 12 read variable a to be used in the calculation from areas 21 and 22, respectively, and update variable a in areas 21 and 22 from "1" to "2" by executing calculation process "process B". Similarly, core 13 reads variable a to be used in the calculation from area 23, and updates variable a in area 23 by executing calculation process "process B". As mentioned above, data corruption has occurred in variable a in area 23. Therefore, core 13 updates variable x in area 23 from "3" to "4".

Figure 10 is a diagram showing the state of the restoration process after the calculation process "process B" shown in Figure 9. As shown in Figure 10, core 11 collates the calculation results of the calculation process "process B" by cores 11, 12, and 13. In response to the fact that the calculation result "4" by core 13 differs from the calculation result "2" by cores 11 and 12, core 11 rewrites the calculation result "4" written in area 23 to the calculation result "2" written in areas 21 and 22. As a result, variable a, which is the calculation result of the calculation process "process B", is restored to the correct value in area 23.

In this way, in the fourth example, only the calculation results are repaired. This reduces the time required for repair. Even when only the calculation results are repaired, data that has been corrupted (garbled) due to a soft error can also be repaired, as shown in Figures 7 to 10.

(Fifth Example of Method for Restoring Data in a Region to be Restored)
A fifth example of a method for repairing data in a repair target area will be described with reference to Figures 11 to 16. In the fifth example, each of areas 21 to 23 has two subareas into which the same data is written. Each of cores 11 to 13 reads data from one of the two subareas to perform arithmetic processing, and updates the data in both of the two subareas in response to the execution of the arithmetic processing.

Figure 11 is a diagram showing another example of the state of the main memory when the computation process "Process A" is completed. As shown in Figure 11, area 21 has subareas 41a and 41b in which the same data is written. Area 22 has subareas 42a and 42b in which the same data is written. Area 23 has subareas 43a and 43b in which the same data is written. However, in the example shown in Figure 11, a soft error has occurred in subarea 43a of area 23 in main memory 104, causing variable a to change from "1" to "3".

As shown in FIG. 11, the core 11 reads the variables (variables a, b, c) used in the calculation from the sub-area 41a, and updates the variables x in both sub-areas 41a and 41b from "5" to "9" in accordance with the execution of the calculation process "Process A". The core 12 reads the variables (variables a, b, c) used in the calculation from the sub-area 42a, and updates the variables x in both sub-areas 42a and 42b from "5" to "9" in accordance with the execution of the calculation process "Process A". Similarly, the core 13 reads the variables (variables a, b, c) used in the calculation from the sub-area 43a, and updates the variables x in both sub-areas 43a and 43b in accordance with the execution of the calculation process "Process A". As described above, data corruption has occurred in the variable a in the sub-area 43a. Therefore, the core 13 updates the variables x in the sub-areas 43a and 43b from "5" to "15".

Figure 12 is a diagram showing the state of the comparison process after the calculation process "process A" shown in Figure 11. As shown in Figure 12, core 11 compares the calculation results of the calculation process "process A" by cores 11, 12, and 13. Since the calculation result "15" by core 13 differs from the calculation result "9" by cores 11 and 12, it is estimated that a soft error has occurred in sub-area 43a. Therefore, in response to the fact that the calculation result "15" by core 13 differs from the calculation result "9" by cores 11 and 12, core 11 switches the area used by core 13 for calculation processing from sub-area 43a to sub-area 43b.

Figure 13 is a diagram showing an example of the state of the main memory 104 when the calculation process "process B" is executed after the matching process shown in Figure 12.

As shown in FIG. 13, the core 11 reads the variable a used in the calculation from the sub-area 41a, and updates the variables a in both sub-areas 41a and 41b from "1" to "2" in accordance with the execution of the calculation process "Process B". The core 12 reads the variable a used in the calculation from the sub-area 42a, and updates the variables a in both sub-areas 42a and 42b from "1" to "2" in accordance with the execution of the calculation process "Process B". The core 13 reads the variable a used in the calculation from the sub-area 43b, and updates the variables a in both sub-areas 43a and 43b in accordance with the execution of the calculation process "Process B". Although data corruption has occurred in the variable a in the sub-area 43a, data corruption has not occurred in the sub-area 43b. Therefore, the core 13 updates the variable a in the sub-area 43a from "3" to "2" and updates the variable a in the sub-area 43b from "1" to "2". This restores the value of variable a in subarea 43a to the correct value.

Fig. 14 is a diagram showing an example of the state of the main memory when the arithmetic process "process C" is executed after the arithmetic process "process B" shown in Fig. 13. The arithmetic process "process C" is a process for updating a variable x according to the following formula (3).
x=4*c...Formula (3).

As shown in FIG. 14, core 11 reads variable c used in the calculation from sub-area 41a, and updates variable x in both sub-areas 41a and 41b from "9" to "12" in accordance with the execution of calculation process "process C". Core 12 reads variable c used in the calculation from sub-area 42a, and updates variable x in both sub-areas 42a and 42b from "9" to "12" in accordance with the execution of calculation process "process C". Core 13 reads variable c used in the calculation from sub-area 43b, and updates variable x in both sub-areas 43a and 43b from "15" to "12" in accordance with the execution of calculation process "process C". This restores the values of variable x in sub-areas 43a and 43b to their correct values.

Fig. 15 is a diagram showing an example of the state of the main memory when the arithmetic process "process C'" is executed after the arithmetic process "process B" shown in Fig. 13. The arithmetic process "process C'" is a process that updates a variable x according to the following formula (4).
x=x+1...Formula (4).

As shown in FIG. 15, core 11 reads variable x used in the calculation from sub-area 41a, and updates variable x in both sub-areas 41a and 41b from "9" to "10" in accordance with the execution of calculation process "process C'". Core 12 reads variable x used in the calculation from sub-area 42a, and updates variable x in both sub-areas 42a and 42b from "9" to "10" in accordance with the execution of calculation process "process C'". Core 13 reads variable x used in the calculation from sub-area 43b, and updates variable x in both sub-areas 43a and 43b from "15" to "16" in accordance with the execution of calculation process "process C'".

Figure 16 is a diagram showing the state of the comparison and repair process after the calculation process "process C'" shown in Figure 15. As shown in Figure 16, core 11 compares the calculation results of the calculation process "process C'" by cores 11, 12, and 13. Core 11 determines that repair of area 23 is necessary because the calculation result "16" by core 13 differs from the calculation result "10" by cores 11 and 12. Then, core 11 rewrites all data in area 23, which is the area to be repaired, so that it matches all data in either area 21 or 22, for example, according to the first example above. As a result, the values of variables x in subareas 43a and 43b are repaired to the correct value.

According to the fifth example, even if the results of the calculations using the sub-areas 41a to 43a are inconsistent, the data is not repaired. This makes it possible to reduce the frequency with which data repair processing is performed. In other words, it is possible to reduce the frequency with which the execution of calculation processing is put on hold in order to repair data.

Furthermore, as shown in Figures 11 to 14, depending on the content of the calculation process, data corrupted by a soft error can be automatically repaired by normal calculation processing.

<Modification>
In the above description, the safety IO unit 100 is provided with a multi-core processor 102 having multiple cores. However, the safety IO unit 100 may be provided with a multi-processor having multiple processors instead of the multi-core processor 102. The multiple processors operate as a calculation unit. For example, the safety IO unit 100 is provided with a multi-processor having three processors. The three processors each execute a calculation process using areas 21, 22, and 23 of the main memory 104. One of the three processors operates as a main calculation unit. The processor operating as the main calculation unit executes a verification and repair process in the same manner as the above-mentioned core 11.

The standard PLC 200, the safety PLC 300, and the coupler 400, like the safety IO unit 100, may also be equipped with a multi-core processor and have a verification and repair program. This allows the standard PLC 200, the safety PLC 300, and the coupler 400 to continue operating even if a soft error occurs in the main memory. As a result, the frequency of stoppages of the control system 1 is reduced.

§3 Supplementary Note As described above, the present embodiment includes the following disclosure.

(Configuration 1)
A data processing device (100) for executing at least one arithmetic process,
First to Nth calculation units (11 to 13),
A memory (104),
N is an integer of 3 or more,
One of the first to Nth calculation units (11 to 13) is a main calculation unit (11),
The memory (104) has first to Nth areas (21 to 23) in which the same data is stored,
the first to Nth calculation units (11 to 13) execute the at least one calculation process using data stored in the first to Nth areas (21 to 23), respectively;
The main calculation unit (11)
collating the calculation results by the first to Nth calculation units (11 to 13) for each of the at least one calculation process;
In response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units (11 to 13), the operation of the first to Nth calculation units (11 to 13) is continued;
a data processing device (100) that rewrites at least a portion of the data in the first area (23) so that it matches any of the data in the second to Nth areas (21, 22) in response to a discrepancy between the calculation result of the first calculation unit (13) and the calculation results of the second to Nth calculation units (11, 12).

(Configuration 2)
The data processing device of configuration 1, wherein the main calculation unit (11) rewrites all data in the first area (23) to match all data in any of the second to Nth areas (21, 22) in response to a discrepancy between the calculation result of the first calculation unit (13) and the calculation results of the second to Nth calculation units (11, 12).

(Configuration 3)
The at least one arithmetic operation includes a plurality of arithmetic operations,
Each of the first to Nth regions (21 to 23) has a plurality of sub-regions (21 a to 21 x, 22 a to 22 x, 23 a to 23 x) for storing data to be overwritten by the execution of the plurality of arithmetic processes,
The main calculation unit (11)
identifying a target sub-area (21a, 22a, 23a) corresponding to the target arithmetic process among the plurality of sub-areas (21a to 21x, 22a to 22x, 23a to 23x) in response to a mismatch between the arithmetic result of the first arithmetic unit (13) and the arithmetic result of the second to Nth arithmetic units (11, 12) for a target arithmetic process among the plurality of arithmetic processes;
The data processing device (100) according to configuration 1, wherein data of the target sub-area (23a) used by the first calculation unit (13) is rewritten so as to match data of the target sub-area (21a, 22a) used by any of the second to Nth calculation units (11, 12).

(Configuration 4)
Each of the plurality of sub-regions (21a to 21x, 22a to 22x, 23a to 23x) is divided into a plurality of blocks (31_1 to 31_M, 32_1 to 32_M, 33_1 to 33_M),
The main calculation unit (11)
Computing an error detection code for each of the blocks of the target sub-region (21 a, 22 a, 23 a);
Identifying a target block (31_1, 32_1, 33_1) among the plurality of blocks of the target sub-area, in which the error detection code does not match between the target sub-area used by the first calculation unit (13) and the target sub-area used by the second to Nth calculation units (11, 12);
The data processing device (100) according to configuration 3, wherein data of the target block (33_1) used by the first calculation unit (13) is rewritten so as to match data of the target block (31_1, 32_1) used by the second to Nth calculation units (11, 12).

(Configuration 5)
the first to Nth calculation units (11 to 13) write the calculation results into the first to Nth areas (21 to 23), respectively;
The main calculation unit (11)
The data processing device (100) according to configuration 1, wherein, in response to a discrepancy between the calculation result of the first calculation unit (13) and the calculation results of the second to Nth calculation units (11, 12), the calculation result written in the first area (23) is rewritten so as to match the calculation result of the second to Nth calculation units (11, 12).

(Configuration 6)
Each of the first to Nth regions (21 to 23) has a first sub-region (41a, 42a, 43a) and a second sub-region (41b, 42b, 43b) in which the same data is written,
Each of the first to Nth calculation units (11 to 13)
reading data from one of the first sub-area (41a, 42a, 43a) and the second sub-area (41b, 42b, 43b) to execute the at least one arithmetic process;
updating data of both the first sub-area (41 a, 42 a, 43 a) and the second sub-area (41 b, 42 b, 43 b) in response to execution of the at least one arithmetic process;
the at least one arithmetic process includes a first arithmetic process and a second arithmetic process executed after the first arithmetic process;
The main calculation unit (11)
in response to a result of the first arithmetic process by the first arithmetic unit (13) using the data of the first sub-area (43a) not matching a result of the first arithmetic process by the second to N-th arithmetic units (11, 12) using the data of the first sub-area (41a, 42a), switching an area from which the first arithmetic unit (13) reads data in the second arithmetic process from the first sub-area (43a) to the second sub-area (43b);
The data processing device (100) according to configuration 1, wherein, in response to a result of the second arithmetic processing by the first arithmetic unit (13) using data in the second sub-area (43b) not matching a result of the second arithmetic processing by the second to Nth arithmetic units (11a, 12) using data in the first sub-area (41a, 42a), at least a portion of the data in the first area (23) is rewritten so as to match the data in the second to Nth areas (21, 22).

(Configuration 7)
A data processing method for a data processing device (100) that executes at least one arithmetic process, comprising the steps of:
The data processing device (100)
First to Nth calculation units (11 to 13),
A memory (104),
N is an integer of 3 or more,
One of the first to Nth calculation units (11 to 13) is a main calculation unit (11),
The memory (104) has first to Nth areas (21 to 23) in which the same data is stored,
The data processing method includes:
a step in which the first to Nth calculation units (11 to 13) execute the at least one calculation process using data stored in the first to Nth areas (21 to 23);
a step in which the main calculation unit (11) checks the calculation results by the first to Nth calculation units (11 to 13) for each of the at least one calculation process;
a step in which the main calculation unit (11) continues the operation of the first to Nth calculation units (11 to 13) in response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units (11 to 13);
a step in which the main calculation unit (11) rewrites at least a portion of the data in the first area (23) so that it matches any of the data in the second to Nth areas (21, 22) in response to a discrepancy between the calculation result of the first calculation unit (13) and the calculation results of the second to Nth calculation units (11a, 12).

(Configuration 8)
A computer-readable program for causing the first to Nth calculation units (11 to 13) to execute the data processing method according to configuration 7.

Although the embodiments of the present invention have been described, the embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present invention is defined by the claims, and it is intended to include all modifications within the meaning and scope of the claims.

1 Control system, 2 Field network, 11, 12, 13 Core, 21, 22, 23 Area, 21a to 21x, 22a to 22x, 23a to 23x, 41a, 41b, 42a, 42b, 43a, 43b Sub-area, 31_1 to 31_M, 32_1 to 32_M, 33_1 to 33_M Block, 100 Safety IO unit, 102 Multi-core processor, 104 Main memory, 110 Storage, 111 Executable program, 112 Verification repair program, 120 Local bus controller, 130 Safety IO module, 140 Processor bus, 200 Standard PLC, 300 Safety PLC, 400 Coupler.

Claims (6)

A data processing device for performing at least one arithmetic operation, comprising:
First to Nth calculation units;
A memory,
N is an integer of 3 or more,
one of the first to Nth calculation units is a main calculation unit;
the memory has first to Nth areas in which the same data is stored;
the first to Nth calculation units respectively execute the at least one calculation process using data stored in the first to Nth areas;
The main calculation unit includes:
collating the calculation results by the first to Nth calculation units for each of the at least one calculation process;
continuing the operation of the first to Nth calculation units in response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units;
The at least one arithmetic operation includes a plurality of arithmetic operations,
each of the first to Nth regions has a plurality of sub-regions for storing data to be overwritten by execution of the plurality of arithmetic operations;
The main calculation unit is
identifying a target sub-area among the plurality of sub-areas corresponding to a target arithmetic process among the plurality of arithmetic processes in response to a discrepancy between the arithmetic result of the first arithmetic unit and the arithmetic results of the second to Nth arithmetic units;
a data processing device that rewrites data of the target sub-region used by the first calculation unit so as to match data of the target sub-region used by any of the second to Nth calculation units . Each of the plurality of sub-regions is divided into a plurality of blocks;
The main calculation unit includes:
Computing an error detection code for each of the plurality of blocks of the target sub-region;
Identifying a target block among the plurality of blocks of the target sub-area, in which the error detection code does not match between the target sub-area used by the first calculation unit and the target sub-areas used by the second to Nth calculation units;
2. The data processing device according to claim 1, wherein data of the target block used by said first processing unit is rewritten so as to coincide with data of the target block used by said second to Nth processing units. A data processing device for performing at least one arithmetic operation, comprising:
First to Nth calculation units;
A memory,
N is an integer of 3 or more,
one of the first to Nth calculation units is a main calculation unit;
the memory has first to Nth areas in which the same data is stored;
the first to Nth calculation units respectively execute the at least one calculation process using data stored in the first to Nth areas;
The main calculation unit is
collating the calculation results by the first to Nth calculation units for each of the at least one calculation process;
continuing the operation of the first to Nth calculation units in response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units;
Each of the first to Nth regions has a first sub-region and a second sub-region in which the same data is written;
Each of the first to Nth calculation units is
reading data from one of the first sub-area and the second sub-area to perform the at least one arithmetic operation;
updating data of both the first sub-region and the second sub-region in response to execution of the at least one arithmetic operation;
the at least one arithmetic process includes a first arithmetic process and a second arithmetic process executed after the first arithmetic process;
The main calculation unit includes:
switching an area from which the first calculation unit reads data to the second sub-area in the second calculation process in response to a result of the first calculation process by the first calculation unit using the data of the first sub-area not matching a result of the first calculation process by the second to Nth calculation units using the data of the first sub-area;
a data processing device which rewrites at least a portion of the data in the first region so that it matches the data in the second to Nth regions in response to a calculation result of the second calculation process by the first calculation unit using the data in the second sub-region not matching a calculation result of the second calculation process by the second to Nth calculation units using the data in the first sub-region. A data processing method for a data processing device that executes at least one arithmetic process, comprising the steps of:
The data processing device includes:
First to Nth calculation units;
A memory,
N is an integer of 3 or more,
one of the first to Nth calculation units is a main calculation unit;
the memory has first to Nth areas in which the same data is stored;
The data processing method includes:
a step in which the first to Nth calculation units execute the at least one calculation process using data stored in the first to Nth areas, respectively;
a step in which the main calculation unit checks the calculation results by the first to Nth calculation units for each of the at least one calculation process;
a step of causing the main calculation unit to continue the operation of the first to Nth calculation units in response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units ;
The at least one arithmetic operation includes a plurality of arithmetic operations,
each of the first to Nth regions has a plurality of sub-regions for storing data to be overwritten by execution of the plurality of arithmetic operations;
The data processing method further comprises:
the main calculation unit, in response to a mismatch between the calculation result of the first calculation unit and the calculation results of the second to Nth calculation units for a target calculation process among the plurality of calculation processes, identifies a target sub-area among the plurality of sub-areas corresponding to the target calculation process;
A data processing method comprising a step in which the main calculation unit rewrites the data of the target sub-area used by the first calculation unit so that it matches the data of the target sub-area used by any of the second to Nth calculation units . A data processing method for a data processing device that executes at least one arithmetic process, comprising the steps of:
The data processing device includes:
First to Nth calculation units;
A memory,
N is an integer of 3 or more,
one of the first to Nth calculation units is a main calculation unit;
the memory has first to Nth areas in which the same data is stored;
The data processing method includes:
a step in which the first to Nth calculation units execute the at least one calculation process using data stored in the first to Nth areas, respectively;
a step in which the main calculation unit checks the calculation results by the first to Nth calculation units for each of the at least one calculation process;
a step of causing the main calculation unit to continue the operation of the first to Nth calculation units in response to a match between a predetermined number or more of the calculation results by the first to Nth calculation units;
Each of the first to Nth regions has a first sub-region and a second sub-region in which the same data is written;
The data processing method further comprises:
Each of the first to Nth arithmetic units reads data from one of the first sub-area and the second sub-area and executes the at least one arithmetic process;
each of the first to Nth calculation units updates data of both the first sub-region and the second sub-region in response to execution of the at least one calculation process;
the at least one arithmetic process includes a first arithmetic process and a second arithmetic process executed after the first arithmetic process;
The data processing method further comprises:
a step of the main calculation unit switching an area from which the first calculation unit reads data in the second calculation process from the first sub-area to the second sub-area in response to a result of the first calculation process by the first calculation unit using the data of the first sub-area not matching a result of the first calculation process by the second to Nth calculation units using the data of the first sub-area;
a step in which the main calculation unit rewrites at least a portion of the data in the first area to match the data in the second to Nth areas in response to a calculation result of the second calculation process by the first calculation unit using the data in the second sub-area not matching a calculation result of the second calculation process by the second to Nth calculation units using the data in the first sub-area. 6. A computer-readable program for causing the first to Nth calculation units to execute the data processing method according to claim 4 or 5 .

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