JP7698259B2 - SEMICONDUCTOR SOLID-STATE BATTERY AND METHOD FOR DETECTING LEVEL OF SEMICONDUCTOR SOLID-STATE BATTERY - Google Patents

Description

Embodiments of the present invention relate to a semiconductor solid-state battery and a method for determining the level of the semiconductor solid-state battery.

In recent years, the spread of electrical equipment and energy conservation have led to a demand for efficient use of electricity. Accordingly, development of secondary batteries that can charge and discharge electricity has progressed. Various types of secondary batteries have been developed, including Li-ion secondary batteries, lead-acid batteries, and nickel-metal hydride batteries. For example, JP 2001-338649 A (Patent Document 1) discloses a Li-ion secondary battery that uses a Li-containing transition metal composite oxide as the positive electrode active material. Li-ion secondary batteries can be miniaturized, and are therefore used as batteries for electrical equipment.

On the other hand, Li-ion secondary batteries are configured to take in and out Li ions via an electrolyte. Therefore, they are batteries that require an electrolyte such as a liquid electrolyte (electrolytic solution). Lead-acid batteries and nickel-metal hydride batteries are also batteries that require an electrolyte. Leaking electrolyte can cause fires and explosions. For this reason, Li-ion secondary batteries have a sealed structure to prevent leakage. However, problems have arisen, such as deterioration due to long-term use, leakage depending on how the electrical device is used, and the operating environment.

In order to eliminate such problems caused by leakage, development of semiconductor solid-state batteries is underway. Semiconductor solid-state batteries charge by capturing electrons at the energy level. As they can be made into all-solid-state secondary batteries, there is no need to use electrolyte.

An example of a semiconductor solid-state battery is disclosed in International Publication No. 2018/117235 (Patent Document 2). In Patent Document 2, the semiconductor solid-state battery has a three-layer structure of an N-type semiconductor layer, an insulating layer, and a P-type semiconductor layer. In Patent Document 2, the energy density is improved and voltage drop is suppressed by controlling the capture level of the semiconductor layer.

JP 2001-338649 A International Publication No. 2018/117235

M. Wistey, “Bandgap+Workfunction Heaven (v3.8)”, [Retrieved January 28, 2020], Internet <URL: https://cpb-us-e1.wpmucdn.com/wp.txstate.edu/dist/f/1377/files/2018/05/BandgapWorkfn-Heavens-3.8.pdf>

The problem that the present invention aims to solve is to provide a high-capacity semiconductor solid-state battery and a method for determining the battery level of the semiconductor solid-state battery.

According to the embodiment, a semiconductor solid state battery is provided that includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer. The insulating layer is provided between the P-type semiconductor layer and the N-type semiconductor layer. The P-type semiconductor layer is made of nickel oxide, and the N-type semiconductor layer is made of titanium oxide. The insulating layer is made of one or more materials having a band gap of 4.5 eV selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins. When the interface between the P-type semiconductor layer and the insulating layer is the first interface, and the interface between the insulating layer and the N-type semiconductor layer is the second interface, in a state of thermal equilibrium or before charging, the level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 of the upper end of the valence band of the insulating layer at the second interface.

According to another embodiment, a semiconductor solid state battery is provided that includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer. The insulating layer is provided between the P-type semiconductor layer and the N-type semiconductor layer. The P-type semiconductor layer is made of nickel oxide, and the N-type semiconductor layer is made of titanium oxide. The insulating layer is made of one or more materials having a band gap of 4.5 eV selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins. When the interface between the P-type semiconductor layer and the insulating layer is a first interface, and the interface between the insulating layer and the N-type semiconductor layer is a second interface, in a state of thermal equilibrium or before charging, the level E-II of the conduction band lower end of the insulating layer is lower than the level E-I of the conduction band lower end of the P-type semiconductor layer at the first interface.

According to still another embodiment, a method for determining the level of a semiconductor solid-state battery is provided. The semiconductor solid-state battery includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. In the semiconductor solid-state battery, the interface between the P-type semiconductor layer and the insulating layer is defined as a first interface. The interface between the insulating layer and the N-type semiconductor layer is defined as a second interface. The level determination method determines levels including the level E1 of the upper end of the valence band of the insulating layer at the second interface and the level E2 of the upper end of the valence band of the N-type semiconductor layer at the second interface, and/or the level E-I of the lower end of the conduction band of the P-type semiconductor layer at the first interface and the level E-II of the lower end of the conduction band of the insulating layer. In the level determination method, the level in a state of thermal equilibrium or a state before charging is determined. The level determination method includes: calculating a self-consistent loop using a Poisson equation and a carrier continuity equation to determine levels including the levels E1 and E2 and/or the levels E-I and E-II; determining the convergence of the calculation of the self-consistent loop by checking the consistency with an external circuit; and checking whether the levels E1 and E2 are high or low and/or whether the levels E-I and E-II are high or low.

FIG. 2 is a conceptual diagram showing an example of a band structure of a semiconductor solid state battery according to an embodiment. 4 is a graph showing an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a semiconductor solid state battery according to an embodiment. 1 is a graph showing an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a conventional semiconductor solid-state battery. FIG. 1 is a schematic cross-sectional view illustrating an example of a semiconductor solid state battery according to an embodiment. 13 is a graph showing an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a semiconductor solid state battery according to another embodiment. 5A to 5C are diagrams showing an example of a method for determining a level of a semiconductor solid-state battery according to an embodiment. FIG. 1 is a diagram showing an overview of Non-Patent Document 1. 3 is a graph showing an example of constant current discharge of a semiconductor solid state battery having the relationship of the levels of the upper end of the valence band and the lower end of the conduction band shown in FIG. 2 . 4 is a graph showing an example of constant current discharge of a semiconductor solid-state battery having the relationship of the levels of the upper end of the valence band and the lower end of the conduction band shown in FIG. 3 .

In Patent Document 2, the voltage drop is reduced by suppressing the internal resistance of the semiconductor layer. This prevents a sudden drop in voltage. However, there is a limit to how much capacity can be improved. After investigating the cause of this, it was found that it is necessary to control the level of the upper end of the valence band at the interface between the insulating layer and the semiconductor layer, or the level of the lower end of the conduction band at the interface between the insulating layer and the semiconductor layer.

In the semiconductor solid-state battery according to the embodiment, high capacity can be achieved by controlling the levels of the upper end of the valence band and the lower end of the conduction band at the interface between the insulating layer and the semiconductor layer.

[First embodiment]
According to the first embodiment, a semiconductor solid state battery is provided that includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer. The insulating layer is between the P-type semiconductor layer and the N-type semiconductor layer. Here, the interface between the P-type semiconductor layer and the insulating layer is defined as a first interface. Also, the interface between the insulating layer and the N-type semiconductor layer is defined as a second interface. The level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 of the upper end of the valence band of the insulating layer at the second interface. At the second interface, the level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 of the upper end of the valence band of the insulating layer, so that holes can be accumulated at the second interface. This can improve the capacity.

It is preferable that the level E6 of the conduction band minimum of the N-type semiconductor layer is lower than the level E5 of the conduction band minimum of the insulating layer at the second interface. By making the level E6 of the conduction band minimum of the N-type semiconductor layer lower than the level E5 of the conduction band minimum of the insulating layer at the second interface, electrons can be accumulated at the second interface. As described above, in a semiconductor solid-state battery that can accumulate holes at the second interface by satisfying the relationship E1>E2, the capacity of the semiconductor solid-state battery can be further improved by further satisfying the relationship E5>E6 to enable electrons to be accumulated at the second interface.

The relationship between the energy levels in the semiconductor solid-state battery according to the embodiment will be described with reference to Figures 1 to 3. Figure 1 is a conceptual diagram showing an example of the band structure of the semiconductor solid-state battery according to the embodiment. Also, Figure 2 is a graph showing an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of the semiconductor solid-state battery according to the embodiment. Figure 3 is a graph showing an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a conventional semiconductor solid-state battery.

The semiconductor solid-state battery 1 shown in FIG. 1 includes a P-type semiconductor layer 2, an insulating layer 3, and an N-type semiconductor layer 4. The insulating layer 3 is between the P-type semiconductor layer 2 and the N-type semiconductor layer 4. Although FIG. 1 illustrates an example of the order of P-type semiconductor layer 2/insulating layer 3/N-type semiconductor layer 4, the P-type semiconductor layer 2 and the N-type semiconductor layer 4 may be reversed.

The following describes an example of a structure in which the interface between the insulating layer 3 and the N-type semiconductor layer 4 is the second interface. In other words, this describes a semiconductor solid-state battery 1 that accumulates carriers (electrons or holes) at the second interface.

The semiconductor solid-state battery 1 has an insulating layer 3 between a P-type semiconductor layer 2 and an N-type semiconductor layer 4. The P-type semiconductor layer 2 uses holes as carriers. The N-type semiconductor layer 4 uses electrons as carriers. The insulating layer 3 has a function of suppressing recombination between the holes in the P-type semiconductor layer 2 and the electrons in the N-type semiconductor layer 4. The interface between the P-type semiconductor layer 2 and the insulating layer 3 is a first interface, and the interface between the insulating layer 3 and the N-type semiconductor layer 4 is a second interface.

In the semiconductor solid-state battery according to the embodiment, the level E2 of the upper end 12 of the valence band of the N-type semiconductor layer 4 at the second interface is lower than the level E1 of the upper end 11 of the valence band of the insulating layer 3 at the second interface. In addition, it is preferable that the level E6 of the lower end 26 of the conduction band of the N-type semiconductor layer at the second interface is lower than the level E5 of the lower end 25 of the conduction band of the insulating layer 3 at the second interface.

2 shows an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a semiconductor solid-state battery according to an embodiment. FIG. 2 is a graph corresponding to a band diagram of a semiconductor solid-state battery 1 in a state of thermal equilibrium or before charging. In FIG. 2, the horizontal axis represents the position, and the vertical axis represents the energy level. The solid line 10 in the lower part of FIG. 2 represents the upper end of the valence band. The solid line 20 in the upper part of FIG. 2 represents the lower end of the conduction band. The dashed line 30 represents the Fermi level in a state of thermal equilibrium. In the graph, the regions representing the P-type semiconductor layer 2, the insulating layer 3, and the N-type semiconductor layer 4 are arranged in order from the 0 nm side along the horizontal axis. In addition, the horizontal and vertical axes of FIG. 2 are provided with a memory for the convenience of explaining the embodiment, and the positions and dimensions of each semiconductor layer and insulating layer are not limited to this range.

In FIG. 2, there is a point where the level rises vertically at a position near 300 nm. This point corresponds to the first interface between the P-type semiconductor layer 2 and the insulating layer 3. Also, in FIG. 2, there is a point where the level rises vertically at a position near 600 nm. This point corresponds to the second interface between the insulating layer 3 and the N-type semiconductor layer 4.

When the semiconductor solid-state battery 1 is charged, some of the holes supplied to the P-type semiconductor layer 2 can overcome the barrier at the first interface due to thermal excitation, tunneling effect, or the like, pass through the insulating layer 3, and move to the second interface. The semiconductor solid-state battery according to the embodiment satisfies the relationship E1>E2. By satisfying this relationship, holes can be stored at the second interface. This makes it possible to achieve a high capacity.

Figure 3 shows an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a conventional semiconductor solid-state battery. Figure 3 is a model created with reference to Figure 1 of Patent Document 2, and is a graph corresponding to a band diagram in a state of thermal equilibrium or before charging. The solid line 10 in the lower part of Figure 3 shows the upper end of the valence band, and the solid line 20 in the upper part shows the lower end of the conduction band. The dashed line 30 represents the Fermi level in a state of thermal equilibrium. In Figure 3, the point where the level rises vertically around a position of 300 nm is the first interface, and the point where the level rises vertically around a position of 600 nm is the second interface.

In conventional semiconductor solid-state batteries, the relationship E1 < E2 exists. Even with this relationship, the recombination of electrons and holes was suppressed. On the other hand, the amount of holes gathering at the second interface was very small.

By satisfying E1>E2, holes can be stored at the second interface. It is also preferable that E1-E2≧0.1 eV. By creating a difference in the levels of E1 and E2, more holes can be stored. Therefore, the larger "E1-E2" is, the more preferable it is.

In addition, when the level of the valence band upper end 13 of the P-type semiconductor layer 2 at the first interface is E3 and the level of the valence band upper end 14 of the insulating layer 3 is E4, it is preferable to satisfy |E3-E4|≦2 eV. |E3-E4|≦2 eV indicates that the difference in level at the interface between the P-type semiconductor layer 2 and the insulating layer 3 is small. The difference in level (|E3-E4|) between the P-type semiconductor layer 2 and the insulating layer 3 at this interface (first interface) can be a barrier at the first interface, but by reducing the value of |E3-E4|, holes can easily overcome the barrier, and the storage of holes at the second interface is promoted. This can achieve even higher capacity. For example, the amount of hole accumulation at the second interface can be 1×10 ¹⁹ cm ⁻³ or more. On the other hand, if |E3-E4| is larger than 2 eV, the barrier may become too large. There may be no difference in the levels at the first interface (|E3-E4|=0), i.e., E3=E4.

Note that since either E3 or E4 can be larger, the difference in the levels is discussed in terms of the absolute value |E3-E4|. It is also preferable that E3>E4. By controlling the level at the first interface, the amount of carrier accumulation can be improved. Furthermore, the recombination of electrons and holes can be suppressed. Furthermore, by combining the relationship |E3-E4|≦2 eV with the relationship E1>E2, even greater effects can be obtained.

When the level E5 of the conduction band lower end 25 of the insulating layer 3 at the second interface, which is the interface between the insulating layer 3 and the N-type semiconductor layer 4, and the level E6 of the conduction band lower end 26 of the N-type semiconductor layer 4 at the second interface are taken as the interface between the insulating layer 3 and the N-type semiconductor layer 4, it is preferable to satisfy the relationship E5-E6>0. E5 and E6 are the levels of the conduction band lower end of the second interface. By making E5 larger than E6 (E5>E6), electrons can be stored at the second interface. For this reason, it is preferable that E5-E6>0, and furthermore E5-E6≧1.5 eV. By combining this relationship with the aforementioned relationship E1>E2, the amount of electrons stored can be further increased. The above-mentioned relationship shown in E1 to E6 shows the band diagram in a thermal equilibrium state or before charging. In other words, it is not necessary to satisfy the above-mentioned relationship after charging. For example, in Figure 2, which shows a state of thermal equilibrium or a state before charging, the relationship E1<E4 is shown, but as charging progresses and carriers accumulate, the relationship E1>E4 may occur. After discharging, the relationship returns to E1<E4.

The above description relates to a semiconductor solid-state battery 1 having a structure in which carriers are accumulated at the second interface. When fabricating a semiconductor solid-state battery 1 having a structure in which carriers are accumulated at the first interface, the battery has a state obtained by rotating FIG. 2 by 180°. For this reason, a simulation is performed by swapping the relationship between the first interface and the second interface. Such a semiconductor solid-state battery 1 will be described in the second embodiment.

The P-type semiconductor layer 2 uses holes as carriers. The N-type semiconductor layer 4 uses electrons as carriers. Various semiconductor materials can be used for the P-type semiconductor layer 2 or the N-type semiconductor layer 4. Examples of the semiconductor material include silicon semiconductors, compound semiconductors, oxide semiconductors, nitride semiconductors, and amorphous semiconductors. Examples of the silicon semiconductor include metal silicide, amorphous silicon, polycrystalline silicon, crystalline silicon, and single crystal silicon. Examples of the compound semiconductor include Group IV, Group I-VII, Group II-VI, Group III-V, chalcopyrite, and perovskite. Group IV, Group I, Group VII, Group II, Group VI, Group III, and Group V are families of elements shown in the periodic table. Examples of the oxide semiconductor include metal oxides, metal composite oxides, and metal oxynitrides.

The P-type semiconductor layer 2 or the N-type semiconductor layer 4 is preferably made of a metal oxide. This is because metal oxides make it easy to control the amount of carriers by introducing oxygen vacancies or metal vacancies, or by doping with impurities.

As the metal oxide, it is preferable to use one or more selected from the group consisting of tungsten oxide ( _WO3 ), molybdenum oxide ( _MoO2 , _MoO3 ), titanium oxide ( _TiO2 ), tin oxide ( _SnO2 , SnO), zinc oxide ( _ZnO ), nickel oxide (NiO), copper oxide (Cu2O), cadmium oxide ( _CdO ), aluminum oxide ( _Al2O3 ), _and gallium oxide ( _Ga2O3 ).

The material of the insulating layer 3 is not particularly limited as long as it can suppress the recombination of electrons and holes. In addition, it is preferable that the thickness of the insulating layer 3 is 30 μm or less. The lower limit of the thickness of the insulating layer 3 is not particularly limited, but it is preferable that it is 1 nm or more. If the thickness is 1 nm or more, the effect of suppressing recombination can be more reliably exhibited. For this reason, it is preferable that the thickness of the insulating layer 3 is 1 nm or more and 30 μm or less, and further 10 nm or more and 20 μm or less.

For the insulating layer 3, it is preferable to use one or more selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins. For the metal oxide, it is preferable to use one or more oxides (including composite oxides) selected from the group consisting of silicon, aluminum, tantalum, nickel, copper, and iron. For the metal nitride, it is preferable to use one or more nitrides (including composite nitrides) selected from the group consisting of silicon and aluminum. An example of a metal oxynitride is silicon oxynitride (SiON).

As described above, by controlling the energy levels at the second interface, or at the second interface and the first interface, the capacity of the semiconductor solid-state battery can be improved. Such a semiconductor solid-state battery can be manufactured using a film formation method such as a sputtering method.

So far, the levels in the stacked structure of the P-type semiconductor layer 2/insulating layer 3/N-type semiconductor layer 4 have been described. When used as a semiconductor solid-state battery, for example, an electrode can be further provided. FIG. 4 shows a schematic cross-sectional view illustrating an example of the structure of a semiconductor solid-state battery according to an embodiment. The semiconductor solid-state battery 1 includes a P-type semiconductor layer 2, an insulating layer 3, an N-type semiconductor layer 4, a front electrode 5, a back electrode 6, and a substrate 7. With the substrate 7 side as the back side, the components of the semiconductor solid-state battery 1 are stacked from the front side to the back side in the order of the front electrode 5/P-type semiconductor layer 2/insulating layer 3/N-type semiconductor layer 4/back electrode 6/substrate 7.

The front electrode 5 and the back electrode 6 are preferably made of a metal material with good electrical conductivity, such as gold (Au), titanium (Ti), copper (Cu), aluminum (Al), or molybdenum (Mo). Each electrode may also be made of a transparent electrode material, such as ITO (indium-doped tin oxide). Each electrode may also have a multilayer structure that combines these materials.

For example, an insulating substrate can be used as the substrate 7. Examples of insulating substrates include a glass substrate, a ceramic substrate, and a resin substrate. In addition, a semiconductor substrate such as a silicon substrate provided with an insulating film can be used as the insulating substrate.

In FIG. 4, the order is shown as front electrode 5/P-type semiconductor layer 2/insulating layer 3/N-type semiconductor layer 4/back electrode 6/substrate 7, but the positions of the P-type semiconductor layer 2 and the N-type semiconductor layer 4 may be reversed. In addition, the front electrode 5 and the back electrode 6 may be provided on the entire surface or part of the surface of the semiconductor layer.

As explained above, it is important to control the level in a semiconductor solid-state battery. For level control, it is preferable to use a simulation technique described in the third embodiment below. In other words, it is preferable to manufacture the semiconductor solid-state battery according to the first embodiment based on the level judgment according to the third embodiment.

The semiconductor solid-state battery according to the first embodiment includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. The level E2 at the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 at the upper end of the valence band of the insulating layer at the second interface between the insulating layer and the N-type semiconductor layer. This semiconductor solid-state battery can exhibit a high capacity.

[Second embodiment]
According to the second embodiment, a semiconductor solid state battery is provided that includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer. The insulating layer is between the P-type semiconductor layer and the N-type semiconductor layer. As in the first embodiment, the interface between the P-type semiconductor layer and the insulating layer is the first interface. Also, the interface between the insulating layer and the N-type semiconductor layer is the second interface. The level E-II of the conduction band lower end of the insulating layer is lower than the level E-I of the conduction band lower end of the P-type semiconductor layer at the first interface. At the first interface, electrons can be stored at the first interface by lowering the level E-II of the conduction band lower end of the insulating layer to the level E-I of the conduction band lower end of the P-type semiconductor layer. This can improve the capacity.

When the level of the upper end of the valence band of the insulating layer at the first interface is E-V, and the level of the upper end of the valence band of the P-type semiconductor layer is E-VI, it is preferable to satisfy [E-VI]-[E-V]≧0.1 eV. [E-VI]-[E-V]≧0.1 eV indicates that the level of the upper end of the valence band of the P-type semiconductor layer, E-VI, is higher than the level of the upper end of the valence band of the insulating layer at the interface between the insulating layer and the P-type semiconductor layer (E-VI>E-V), and that there is a substantial difference in the levels. Due to the difference in levels at this interface (first interface), holes can be stored here. This makes it possible to achieve even higher capacity.

By controlling the energy level at the first interface, the amount of carrier accumulation can be improved. Furthermore, the recombination of electrons and holes can be suppressed. Furthermore, by combining the relationship [E-VI]-[E-V]≧0.1 eV with the relationship E-I＞E-II, even greater effects can be obtained. Furthermore, by making E-VI larger than E-V, even greater effects can be obtained. For this reason, the larger the difference between E-VI and E-V, the more preferable it is. If the difference between E-VI and E-V is small, holes tend to accumulate at the second interface.

As described above, in a semiconductor solid-state battery that can store electrons at the first interface by satisfying the relationship E-I>E-II, the capacity of the semiconductor solid-state battery can be further improved by further satisfying the relationship E-VI>E-V to enable holes to be stored at the first interface.

The relationship between the energy levels in the semiconductor solid-state battery according to the embodiment will be described with reference to FIG. 5. FIG. 5 is a graph showing an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band in the semiconductor solid-state battery according to the second embodiment. Note that the semiconductor solid-state battery according to the second embodiment may have a band structure similar to that of the semiconductor solid-state battery according to the first embodiment, for example. Details will be omitted as they overlap with the explanation given in the first embodiment.

In the semiconductor solid-state battery according to the embodiment, the level E-II of the conduction band lower edge 22 of the insulating layer 3 at the first interface is lower than the level E-I of the conduction band lower edge 21 of the P-type semiconductor layer 2 at the first interface. In addition, it is preferable that the level E-V of the valence band upper edge 15 of the insulating layer 3 at the first interface and the level E-VI of the valence band upper edge 16 of the P-type semiconductor layer 2 at the first interface satisfy the relationship [E-VI]-[E-V]≧0.1 eV.

Figure 5 shows an example of the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of the semiconductor solid-state battery according to the second embodiment. Figure 5 is a graph corresponding to a band diagram of the semiconductor solid-state battery 1 in a state of thermal equilibrium or before charging. In Figure 5, the horizontal axis represents position, and the vertical axis represents energy level. The solid line 10 in the lower part of Figure 5 represents the upper end of the valence band, and the solid line 20 in the upper part represents the lower end of the conduction band. The dashed line 30 represents the Fermi level in a state of thermal equilibrium. In the graph, the regions representing the P-type semiconductor layer 2, the insulating layer 3, and the N-type semiconductor layer 4 are arranged in order from the 0 nm side along the horizontal axis. In addition, the horizontal and vertical axes of Figure 5 are provided with memory for the convenience of explaining the embodiment, and the positions and dimensions of each semiconductor layer and insulating layer are not limited to this range.

In FIG. 5, the point where the level rises vertically at a position near 300 nm corresponds to the first interface between the P-type semiconductor layer 2 and the insulating layer 3. Also, the point where the level rises vertically at a position near 600 nm corresponds to the second interface between the insulating layer 3 and the N-type semiconductor layer 4.

When the semiconductor solid-state battery 1 is charged, some of the electrons supplied to the N-type semiconductor layer 4 can overcome the barrier at the second interface due to thermal excitation or the tunneling effect, and travel through the insulating layer 3 to the first interface. In the semiconductor solid-state battery according to the second embodiment, the relationship E-I>E-II is satisfied, so that electrons can be stored at the first interface. This allows a high capacity to be achieved.

It is preferable that {[E-I] - [E-II]} ≧ 0.1 eV. By creating a difference between the levels of E-I and E-II, more electrons can be stored. Therefore, the larger {[E-I] - [E-II]} is, the more preferable it is.

In addition, when the level of the conduction band minimum 23 of the N-type semiconductor layer 4 at the second interface is E-III, and the level of the conduction band minimum 24 of the insulating layer 3 is E-IV, it is preferable to satisfy |[E-III]-[E-IV]|≦2 eV. |[E-III]-[E-IV]|≦2 eV indicates that the difference in the levels at the interface between the N-type semiconductor layer 4 and the insulating layer 3 is small. The difference in the levels (|[E-III]-[E-IV]|) between the N-type semiconductor layer 4 and the insulating layer 3 at this interface (second interface) can be a barrier at the second interface, but by reducing the value of |[E-III]-[E-IV]|, electrons can easily overcome the barrier, and the storage of electrons at the first interface is promoted. This can achieve even higher capacity. On the other hand, if |[E-III]-[E-IV]| is larger than 2 eV, the barrier may become too large. There may be no difference in levels at the second interface (|[E-III] - [E-IV]| = 0), and the relationship E-III = E-IV may be true.

Note that since either E-III or E-IV can be larger, the difference in the levels is discussed in terms of the absolute value |[E-III] - [E-IV]|. It is also preferable that E-IV > E-III. By controlling the level at the second interface, the amount of carrier accumulation can be improved. Furthermore, the recombination of electrons and holes can be suppressed. Furthermore, by combining the relationship |[E-III] - [E-IV]| ≦ 2 eV with the relationship E-I > E-II, even greater effects can be obtained.

The above equations E-I to E-VI show the band diagrams in a thermal equilibrium state or before charging. In other words, the above equations do not have to be satisfied after charging. For example, in Figure 5, which shows the thermal equilibrium state or the state before charging, the relationship E-II>E-IV is shown, but as charging progresses and carriers accumulate, the relationship E-II<E-IV can occur. After discharging, the relationship returns to E-II>E-IV.

The P-type semiconductor layer 2, the insulating layer 3, and the N-type semiconductor layer 4 can each be made of the same materials as those described in the first embodiment. The dimensions of each layer, such as the thickness, can also be set in the same way as in Example 1. Since the contents are redundant, the explanation will be omitted.

As described above, by controlling the energy levels at the first interface, or at the first interface and the second interface, the capacity of the semiconductor solid-state battery can be improved. Such a semiconductor solid-state battery can be manufactured using a film formation method such as a sputtering method.

As with the first embodiment, the semiconductor solid-state battery according to the second embodiment can also be provided with, for example, further electrodes. To avoid redundancy, the description will be omitted.

As explained above, it is important to control the level in a semiconductor solid-state battery. For level control, it is preferable to use a simulation technique described in the third embodiment below. In other words, it is preferable to manufacture the semiconductor solid-state battery according to the second embodiment based on the level judgment according to the third embodiment.

The semiconductor solid-state battery according to the second embodiment includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. At the first interface between the P-type semiconductor layer and the insulating layer, the level E-II at the upper end of the valence band of the insulating layer is lower than the level E-I at the upper end of the valence band of the P-type semiconductor layer. This semiconductor solid-state battery can exhibit a high capacity.

[Third embodiment]
According to the third embodiment, a method for determining the level of a semiconductor solid-state battery is provided. In other words, the method makes it possible to determine whether a semiconductor solid-state battery exhibits battery operation by using a combination of materials having a level such as level E1 or level E-I.

Here, the semiconductor solid-state battery includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. In the semiconductor solid-state battery, the interface between the P-type semiconductor layer and the insulating layer is the first interface. The interface between the insulating layer and the N-type semiconductor layer is the second interface. The level determination method determines the level of the semiconductor solid-state battery, including the level E1 of the upper end of the valence band of the insulating layer at the second interface and the level E2 of the upper end of the valence band of the N-type semiconductor layer at the second interface, and/or the level E-I of the lower end of the conduction band of the P-type semiconductor layer at the first interface and the level E-II of the lower end of the conduction band of the insulating layer. The level determination method includes calculating a self-consistent loop using the Poisson equation and the carrier continuity equation to obtain levels including the levels E1 and E2 and/or the levels E-I and E-II, determining the convergence of the calculation of the self-consistent loop by checking the consistency with an external circuit, and checking the level of the levels E1 and E2 and/or the level of the levels E-I and E-II. The consistency with the external circuit is a process of checking whether the current and voltage at the electrodes controlled by the external circuit in a virtual device in which the semiconductor solid-state battery is connected to a virtual external circuit match those in the semiconductor solid-state battery. If they match, it is determined that the calculation has converged, that is, a solution has been obtained. The determination of whether or not they match will be described in detail later.

In addition to the above levels E1 and E2, the levels obtained by the self-consistent loop calculation may include the level E3 of the upper end of the valence band of the P-type semiconductor layer at the first interface, the level E4 of the upper end of the valence band of the insulating layer at the first interface, the level E5 of the lower end of the conduction band of the insulating layer at the second interface, and the level E6 of the lower end of the conduction band of the N-type semiconductor layer at the second interface. Alternatively, in addition to the above levels E-I and E-II, the levels obtained may include the level E-III of the lower end of the conduction band of the N-type semiconductor layer at the second interface, the level E-IV of the lower end of the conduction band of the insulating layer at the second interface, the level E-V of the upper end of the valence band of the insulating layer, and the level E-VI of the upper end of the valence band of the P-type semiconductor layer at the first interface. By performing the self-consistent loop calculation, for example, band diagrams such as those shown in Figures 2, 3, and 5 can be obtained.

By performing a simulation in advance using the level determination method according to the embodiment, for example, when selecting materials to be used for each layer (N-type semiconductor layer, insulating layer, P-type semiconductor layer) of a semiconductor solid-state battery, it is possible to predict the above levels E1 to E6 or levels E-I to E-VI when the selected materials are combined. Therefore, it is possible to estimate before manufacturing whether the semiconductor solid-state battery according to the first embodiment or the semiconductor solid-state battery according to the second embodiment can be obtained by combining the selected materials. In addition, it is also possible to determine the physical properties of each material to be combined based on the simulation, and select materials based on the results.

This simulation method combines the Poisson equation and the carrier continuity equation, and is similar to the method generally known as device simulation. More specifically, this simulation method corresponds to a simulation based on the drift-diffusion method.

Figure 6 shows the general flow of the level determination method (simulation method). The details are explained below.

The first step is to calculate the initial conditions. Calculating the initial conditions is a process of preparing the physical properties of the materials to be used in each layer of the semiconductor solid-state battery. Literature values may be used for the physical properties of the materials. For example, Non-Patent Document 1 (M. Wistey, "Bandgap+Workfunction Heaven (v3.8)"), the overview of which is shown in Figure 7, summarizes the band gaps and work functions of various materials.

In the second step, the bias voltages (V _A , V _C ) and time (t) are updated.

Then, in the third step, we calculate the self-consistent loop (i) using the Poisson equation and the carrier continuity equation.

The Poisson equation is used to express the electrostatic potential when a charge distribution is given. The Poisson equation is shown as the following equation (1). In the equation, e is the electron charge, p is the hole density, n is the electron density, N _D ⁺ is the ionized donor density, and N _A ^- is the ionized acceptor density.

The carrier concentrations (electron density n and hole density p) are calculated using the continuity equations for electrons and holes shown in the following formulas (2) and (3) together with the Poisson equation. The recombination can be, for example, a three-level model of SRH (Shockley-Read-Hall) type. If necessary, recombination other than the SRH type may be considered. The current components include drift current and diffusion current. In the formulas, J _n represents the electron current, J _p represents the hole current, and R represents the recombination rate of the carriers.

Here, the second step, which is a process of updating the bias voltages ( _VA , _VC ) and time (t), will be described. The second step is a process of updating the time t and the electrode potentials ( _VA , _VC ). At this time, the bias V(t) is calculated by the following formula (4). The symbol _JExt in the formula indicates the current flowing through the external circuit.

Equation (4) shows how to handle the constant voltage boundary condition. Under the constant voltage boundary condition, the total amount of charge injected (or discharged) is controlled by the potential of both electrodes. The total amount of charge, or the accumulated charge Q(t), can be calculated using the following equation (5). Under the constant voltage boundary condition, there is no constraint on the electrode current. Therefore, the bias V(t) can be calculated based on equations (4) and (5). In the equation, n(t) is the electron density at time t, n _eq is the electron density in the equilibrium state, p(t) is the hole density at time t, p _eq is the hole density in the equilibrium state, and R is the recombination rate of carriers.

When parasitic resistance cannot be ignored even under constant voltage boundary conditions, the effect of voltage drop is taken into consideration using the electrode current according to the following formula (6). In the formula, V _Ext is the voltage applied to the external circuit, V _A is the anode potential, V _C is the cathode potential, J _Ext ^A/C is the current flowing between the anode/cathode and the external circuit, and R _S is the resistance component such as parasitic resistance that may occur due to poor electrode quality. More specifically, J _Ext ^A/C is a symbol meaning "J _Ext ^A or J _Ext ^C ", where J _Ext ^A is the current flowing in or out from the external circuit to the positive electrode, and J _Ext ^C is the current flowing in or out from the external circuit to the negative electrode.

Next, in the fourth step, the calculation results of the self-consistent loop (i) are used to check the consistency with the external circuit.

The fourth step, which checks for consistency with the external circuit, requires constant current boundary conditions. First, the potentials of both electrodes are updated using Newton's method so that equation (7) becomes zero.

Next, the acceleration parameter corresponding to the time step based on the displacement current _JD is calculated using the following formula (8). In the formula, _JD (0) is the displacement current density at the positive electrode, D(0) is the electric flux density at the positive electrode, _JD (L) is the displacement current density at the negative electrode, and D(L) is the electric flux density at the negative electrode.

The above steps are performed to determine convergence in two stages. The convergence is determined by the convergence of the electrode current and the voltage. At this time, a threshold value is set for each. For discharge by an external resistance, the following formula (9) is used. Here, the symbol R _S represents a resistor that discharges or consumes power.

The electrode potential and voltage can be determined from the resistance and electrode current. In addition, the electrode current is used to determine convergence. When convergence occurs, the relationship shown in formula (10) is satisfied.

The electrode voltage is updated using equation (7) (Newton's method). The fourth step is to perform this update and check the consistency between the external circuit and the semiconductor solid-state battery. Specifically, by checking whether the current and voltage match between the external circuit and inside the semiconductor solid-state battery, it is confirmed whether the calculation of the electrode current and voltage has converged, that is, whether a solution has been obtained for the calculation.

As an example, we will explain the case where a resistor R _S is connected as a virtual external circuit to a semiconductor battery that is charged and not connected to an external circuit, and the state is calculated Δt seconds after discharging begins.
(1) Before starting the calculation, the semiconductor battery is charged and not connected to an external circuit (open state), so the electrode current is zero and the voltage is V _0. When an external resistance R _S is connected, it is assumed that a current of J ₀ = V ₀ /R _S flows through the electrodes.
(2) The electrode current _J0 is required as a boundary condition, and the third step is calculated. At this time, a charge of _J0 × Δt is lost from inside the battery, so the voltage inside the semiconductor battery shifts to _V1 ( _V0 > _V1 ).
(3) Because the electrode voltage is _V1 , it is assumed that a current of _J1 = _V1 / _Rs flows out of the external circuit. However, the current _J1 does not match the previous _J0 , so there is no consistency between the external circuit and the inside of the semiconductor battery.
(4) Now, when the third step is calculated for the semiconductor battery with a current of _J1 as the boundary condition, a charge discharge of _J1 × Δt is assumed, and therefore the electrode voltage is obtained as _V2 .
(5) By repeating steps (3) and (4), the current and electrode voltage calculated by the external circuit gradually become consistent with the current and electrode voltage calculated by the semiconductor battery. This consistency means that the calculations have converged, and it is possible to calculate the current and voltage Δt after connection.

If the result of the fourth step is that the current and voltage at the electrodes controlled by the external circuit match those in the semiconductor solid-state battery, it is determined that consistency with the external circuit has been achieved. After the fourth step, the fifth step is to determine whether or not to recalculate under different conditions. For example, if a result that satisfies the required level is obtained, such as satisfying the relationship E1>E2 or the relationship E-I>E-II, it can be determined that the conditions are such that the desired battery operation can be obtained, and calculations under other conditions can be omitted. If the required level of the relationship is not obtained, calculations may be performed again to determine the conditions under which the required relationship can be obtained. Even if the required level of the relationship is obtained, recalculation may be performed for the purpose of further verifying other conditions. If calculations are to be recalculated under different conditions, the process returns to the second step. If calculations are not to be recalculated, the calculations are terminated.

If the current and voltage do not match in the fourth step, it is determined that there is no consistency with the external circuit, and the calculation is repeated from the third step. When the calculation is repeated in the third step, the calculation is performed using formula (7) for each electrode under the conditions of formulas (11) and (12) below. Such trials with V _A ⁱ⁺¹ and V _C ⁱ⁺¹ are referred to as the sixth step.

By carrying out the above steps, it is possible to simulate whether or not a semiconductor solid-state battery with the desired level can be produced. By using this method, it is possible to determine whether or not the level can be controlled before manufacturing a semiconductor solid-state battery, allowing for efficient manufacturing.

For example, nickel oxide (NiO _x ) is used as the P-type semiconductor layer 2, silicon oxynitride (SiON) is used as the insulating layer 3, and titanium oxide (TiO ₂ ) is used as the N-type semiconductor layer 4. The thickness of each layer is unified to 300 nm. Parameters related to the physical properties of each layer are shown in Table 1 below.

The parameters shown in Table 1 are examples of parameters used in the simulation. For these parameters, for example, physical property values cited from publicly known literature can be used.

The graph in Figure 3 was obtained by performing the above-mentioned simulation using the parameters in Table 1. Figure 3 is a graph showing the relationship between the levels of the upper end of the valence band and the lower end of the conduction band of a conventional semiconductor solid-state battery. In Figure 3, the relationship E1<E2.

By appropriately changing the parameter values shown in Table 1 and performing a simulation, it can be determined whether the graph in Figure 2 can be obtained. By selecting materials for the semiconductor solid-state battery so that they satisfy the physical property values that allow the graph in Figure 2 to be obtained, it is possible to increase the capacity. For example, if a change is made to the combination shown in Table 1 and a material with a band gap of about 4.5 eV is used as the insulating layer 3 instead of silicon oxynitride, the graph in Figure 2 can be obtained.

FIG. 8 shows an example of constant current discharge of a semiconductor solid-state battery having the level relationship of the upper end of the valence band and the lower end of the conduction band shown in FIG. 2. FIG. 9 shows an example of constant current discharge of a semiconductor solid-state battery having the level relationship of the upper end of the valence band and the lower end of the conduction band shown in FIG. 3. Both FIG. 8 and FIG. 9 show the behavior when a target semiconductor solid-state battery is charged at a constant voltage of 2 V and then discharged at a constant current of 10 μA/cm ^2. In generating the graph, the Boltzmann distribution is used as the carrier distribution function. In FIG. 8 and FIG. 9, the horizontal axis is the discharge time (s, ms). The vertical axis on the left side is the voltage (V), and the vertical axis on the right side is the residual charge (cm ⁻² ). The solid lines 40 and 50 are discharge curves showing the change in voltage. The dashed lines 41 and 51 show the residual charge. FIG. 8 shows a simulation of the behavior of constant current discharge of a semiconductor solid-state battery having the level relationship of FIG. 2. FIG. 9 shows a simulation of the constant current discharge behavior of a semiconductor solid-state battery having the level relationship shown in FIG.

In Fig. 8, it takes 160 seconds for the residual charge to reach 0 cm ^-2 . In contrast, in Fig. 9, the residual charge reaches 0 cm ^-2 in about 0.004 seconds. From the comparison, it can be seen that the capacitance increases when the relationship E1>E2 is satisfied.

As described above, a good semiconductor solid-state battery can be designed by using simulation. For example, an N-type semiconductor material can be determined and a simulation can be performed to derive parameters of a P-type semiconductor that satisfies the relationship E1>E2. Similarly, a P-type semiconductor material can be determined and a simulation can be performed to derive parameters of an N-type semiconductor that satisfies the relationship E1>E2. Also, an insulating layer can be determined and parameters of a semiconductor that satisfies the relationship E1>E2 can be derived. Similarly, a semiconductor material can be determined and parameters of an insulating layer that satisfies the relationship E1>E2 can be derived. Simulations can also be performed using literature values for the conduction band and valence band of the semiconductor material and insulating layer. Similar simulations are possible for other level relationships described in the first and second embodiments, such as the level relationship E-I>E-II. In other words, the level determination method according to the embodiment is a simulation technique suitable for manufacturing semiconductor solid-state batteries.

The level determination method for a semiconductor solid-state battery according to the third embodiment includes calculating a self-consistent loop using the Poisson equation and the carrier continuity equation, and confirming the consistency with an external circuit. The level can be obtained by the self-consistent loop. The obtained levels include the levels E1 and E2, and/or the levels E-I and E-II. By confirming the consistency with the external circuit, it is determined whether the calculation has converged. For the obtained levels, the level E1 and the level E2, and/or the level E-I and the level E-II can be confirmed. By the level determination method, in a semiconductor solid-state battery having a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, the levels E1 and E2, etc., and/or the levels E-I and E-II, etc. at the second interface between the insulating layer and the N-type semiconductor layer can be obtained, and their relationship can be known. This simulation technology will enable the achievement of high-capacity semiconductor solid-state batteries.

According to one or more of the embodiments described above, a semiconductor solid-state battery is provided that includes a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer. When the interface between the P-type semiconductor layer and the insulating layer is the first interface, and the interface between the insulating layer and the N-type semiconductor layer is the second interface, the level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than the level E1 of the upper end of the valence band of the insulating layer at the second interface. In this semiconductor solid-state battery, the interface levels of the three-layer structure of the P-type semiconductor layer, the insulating layer, and the N-type semiconductor layer are controlled, thereby exhibiting a high capacity.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.
The invention as originally claimed in the present application is set forth below.
[1] A P-type semiconductor layer;
An N-type semiconductor layer;
an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer,
a first interface being an interface between the P-type semiconductor layer and the insulating layer, and a second interface being an interface between the insulating layer and the N-type semiconductor layer, wherein a level E2 of an upper end of a valence band of the N-type semiconductor layer is lower than a level E1 of an upper end of a valence band of the insulating layer at the second interface.
[2] The semiconductor solid state battery according to [1], wherein a level E3 of the upper end of the valence band of the P-type semiconductor layer at the first interface and a level E4 of the upper end of the valence band of the insulating layer at the first interface satisfy a relationship of |E3-E4|≦2 eV.
[3] The semiconductor solid state battery according to [1] or [2], wherein a level E5 of the conduction band minimum of the insulating layer at the second interface and a level E6 of the conduction band minimum of the N-type semiconductor layer at the second interface satisfy a relationship of E5>E6.
[4] The semiconductor solid-state battery according to any one of [1] to [3], wherein the level E1 and the level E2 are obtained by calculating a self-consistent loop using a Poisson equation and a carrier continuity equation.
[5] A P-type semiconductor layer;
An N-type semiconductor layer;
an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer,
a first interface is an interface between the P-type semiconductor layer and the insulating layer, and a second interface is an interface between the insulating layer and the N-type semiconductor layer, and a level E-II of the conduction band minimum of the insulating layer is lower than a level E-I of the conduction band minimum of the P-type semiconductor layer at the first interface.
[6] The semiconductor solid state battery according to [5], wherein a level E-V of an upper end of a valence band of the insulating layer at the first interface and a level E-VI of an upper end of a valence band of the P-type semiconductor layer at the first interface satisfy a relationship of [E-VI]-[E-V]≧0.1 eV.
[7] The semiconductor solid state battery according to [5] or [6], wherein a level E-III of the conduction band minimum of the N-type semiconductor layer at the second interface and a level E-IV of the conduction band minimum of the insulating layer at the second interface satisfy a relationship of |[E-III]-[E-IV]|≦2 eV.
[8] The level E-I and the level E-II are obtained by calculating a self-consistent loop using a Poisson equation and a carrier continuity equation. The semiconductor solid-state battery according to any one of [5] to [7].
[9] In a semiconductor solid state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, when an interface between the P-type semiconductor layer and the insulating layer is defined as a first interface and an interface between the insulating layer and the N-type semiconductor layer is defined as a second interface,
A level determination method for determining levels including a level E1 of an upper end of a valence band of the insulating layer at the second interface and a level E2 of an upper end of a valence band of the N-type semiconductor layer at the second interface, and/or a level E-I of a lower end of a conduction band of the P-type semiconductor layer at the first interface and a level E-II of a lower end of a conduction band of the insulating layer,
Obtaining the levels including the levels E1 and E2 and/or the levels E-I and E-II by calculating a self-consistent loop using the Poisson equation and the carrier continuity equation;
determining convergence of the self-consistent loop calculation by checking consistency with an external circuit;
Checking whether the level E1 and the level E2 are high or low and/or whether the level E-I and the level E-II are high or low;
The method for determining a level of the semiconductor solid-state battery, comprising:

1...semiconductor solid-state battery, 2...P-type semiconductor layer, 3...insulating layer, 4...N-type semiconductor layer, 5...front electrode, 6...rear electrode, 7...substrate, 10...solid line (top of valence band), 11...top of valence band of insulating layer at second interface, 12...top of valence band of N-type semiconductor layer at second interface, 13...top of valence band of P-type semiconductor layer at first interface, 14...top of valence band of insulating layer at first interface, 15...top of valence band of insulating layer at first interface, 16...top of valence band of P-type semiconductor layer at first interface, 20...solid line (conduction band bottom), 21...conduction band bottom of the P-type semiconductor layer at the first interface, 22...conduction band bottom of the insulating layer at the first interface, 23...conduction band bottom of the N-type semiconductor layer at the second interface, 24...conduction band bottom of the insulating layer at the second interface, 25...conduction band bottom of the insulating layer at the second interface, conduction band bottom of the N-type semiconductor layer at the second interface, 30...dashed line (Fermi level), 40...solid line (discharge curve), 41...dashed line (residual charge), 50...solid line (discharge curve), 51...dashed line (residual charge).

Claims (9)

A P-type semiconductor layer made of nickel oxide ;
An N-type semiconductor layer made of titanium oxide ;
an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, the insulating layer being made of one or more materials having a band gap of 4.5 eV selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins;
an interface between the P-type semiconductor layer and the insulating layer is defined as a first interface, and an interface between the insulating layer and the N-type semiconductor layer is defined as a second interface, in a state of thermal equilibrium or before charging, a level E2 of the upper end of the valence band of the N-type semiconductor layer is lower than a level E1 of the upper end of the valence band of the insulating layer at the second interface,
The insulating layer has a thickness of 30 μm or less. The semiconductor solid-state battery according to claim 1, in which, in a state of thermal equilibrium or before charging, the level E3 of the upper end of the valence band of the P-type semiconductor layer at the first interface and the level E4 of the upper end of the valence band of the insulating layer at the first interface satisfy the relationship |E3-E4|≦2 eV. The semiconductor solid-state battery according to claim 1 or 2, in a state of thermal equilibrium or before charging, a level E5 of the conduction band minimum of the insulating layer at the second interface and a level E6 of the conduction band minimum of the N-type semiconductor layer at the second interface satisfy the relationship E5>E6. The semiconductor solid-state battery according to any one of claims 1 to 3, wherein the level E1 and the level E2 are obtained by calculating a self-consistent loop using the Poisson equation and the carrier continuity equation. A P-type semiconductor layer made of nickel oxide ;
An N-type semiconductor layer made of titanium oxide ;
an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, the insulating layer being made of one or more materials having a band gap of 4.5 eV selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, and insulating resins;
When an interface between the P-type semiconductor layer and the insulating layer is defined as a first interface, and an interface between the insulating layer and the N-type semiconductor layer is defined as a second interface, in a state of thermal equilibrium or before charging, a level E-II of the conduction band minimum of the insulating layer is lower than a level E-I of the conduction band minimum of the P-type semiconductor layer at the first interface,
The insulating layer has a thickness of 30 μm or less. The semiconductor solid-state battery according to claim 5, in which, in a state of thermal equilibrium or before charging, the level E-V of the upper end of the valence band of the insulating layer at the first interface and the level E-VI of the upper end of the valence band of the P-type semiconductor layer at the first interface satisfy the relationship [E-VI]-[E-V]≧0.1 eV. The semiconductor solid-state battery according to claim 5 or 6, in a state of thermal equilibrium or before charging, the level E-III of the conduction band minimum of the N-type semiconductor layer at the second interface and the level E-IV of the conduction band minimum of the insulating layer at the second interface satisfy the relationship |[E-III]-[E-IV]|≦2 eV. The semiconductor solid-state battery according to any one of claims 5 to 7, wherein the level E-I and the level E-II are obtained by calculating a self-consistent loop using the Poisson equation and the carrier continuity equation. In a semiconductor solid state battery including a P-type semiconductor layer, an N-type semiconductor layer, and an insulating layer provided between the P-type semiconductor layer and the N-type semiconductor layer, when an interface between the P-type semiconductor layer and the insulating layer is defined as a first interface and an interface between the insulating layer and the N-type semiconductor layer is defined as a second interface,
A level determination method for determining levels including a level E1 of an upper end of a valence band of the insulating layer at the second interface and a level E2 of an upper end of a valence band of the N-type semiconductor layer at the second interface, and/or a level E-I of a lower end of a conduction band of the P-type semiconductor layer at the first interface and a level E-II of a lower end of a conduction band of the insulating layer in a thermal equilibrium state or a state before charging,
Obtaining the levels including the levels E1 and E2 and/or the levels E-I and E-II by calculating a self-consistent loop using the Poisson equation and the carrier continuity equation;
determining convergence of the self-consistent loop calculation by checking consistency with an external circuit;
confirming whether the level E1 is higher than the level E2 and/or whether the level E-I is higher than the level E-II.