JP7699185B2 - Symbol demapping circuit, receiving device, and symbol demapping method - Google Patents

Description

The present invention relates to a symbol demapping circuit of a receiving device used, for example, in a digital coherent optical transmission system.

In recent years, there has been a need for a method of transmitting large amounts of information, and attempts have been made to increase transmission capacity by increasing the number of values of modulated signals. With multi-level modulation, a large number of bits (information) can be transmitted with one symbol, making it suitable for large capacity transmissions. However, since a large number of signal points are placed on the IQ plane, the signal point intervals become small, making it susceptible to the effects of noise and making it difficult to determine which signal point the received signal corresponds to. For this reason, the importance of powerful error correction codes is increasing even more (see Patent Document 1).

When decoding a code on the receiving side, the LLR (Log-Likelihood Ratio) is used as the soft decision information that is input to the error correction decoding circuit. This LLR is a value derived from the received signal by the symbol demapping process on the receiving side, and is a priori probability that the transmitted signal is either 0 or 1.

Figure 28 shows the configuration of a receiving device in a conventional communication system. The receiving device 2 includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, and an error correction decoding circuit 23.

The AD conversion circuit 20 converts an analog received signal received from a transmitting device via a communication path into a digital signal.
The demodulation circuit 21 performs demodulation processing on the signal output from the AD conversion circuit 20 in accordance with the modulation performed on the transmitting device side, and outputs the demodulated received signal to a symbol demapping circuit 22. Here, the modulation performed on the transmitting device side is, for example, Orthogonal Frequency Division Multiplexing (OFDM) modulation.

The symbol demapping circuit 22 outputs a bit string corresponding to the ideal signal point that is closest to the received signal (received symbol) by hard decision from the received signal output from the demodulation circuit 21, and also outputs an LLR, which is likelihood information for each bit of the bit string.
The error correction decoding circuit 23 performs error correction decoding processing on the bit string output from the symbol demapping circuit 22 based on the LLR.

In conventional technology, symbols were demapped using a mid-tread type. The input/output characteristics of the mid-tread type are shown in Figure 29. An example of the results of demapping processing by a conventional symbol demapping circuit 22 when the multi-level modulation method is 16QAM (Quadrature Amplitude Modulation) is shown in Figures 30 and 31. Also, an example of the results of demapping processing by the symbol demapping circuit 22 when the multi-level modulation method is QPSK (Quadrature Phase Shift Keying) is shown in Figure 32.

Note that Figures 30 to 32 only show the coordinates (input amplitude) on the I axis of the received symbol. For example, "31 (+31.0)" for the input amplitude in Figures 30 and 31 means that 31 is the representative value for inputs in the range of +30.5 to +31.5. Similarly, for example, "15 (+15.0)" for the input amplitude in Figure 32 means that 15 is the representative value for inputs in the range of +14.5 to +15.5.

As shown in FIG. 33(A), when the multi-level modulation method is 16QAM, the symbol demapping circuit 22 outputs the MSB (Most Significant Bit) and LSB (Least Significant Bit) for 64 levels of input amplitude represented by 6 bits, as well as the LLRs of each of these bits. In FIG. 30 to FIG. 32, LLR:MSB indicates the LLR of the MSB, and LLR:LSB indicates the LLR of the LSB.

Also, as shown in FIG. 33B, when the multi-level modulation method is QPSK, the symbol demapping circuit 22 outputs a 1-bit output DT and the LLR of this bit for 32 levels of input amplitude represented by 5 bits.
In either case of 16QAM or QPSK, the LLR is expressed by 4 bits, with 9 levels of values from 0 to 8.

As shown in Figures 30 to 32, in conventional technology, when the input amplitude is at the minimum value (-32 (-32.0) for 16QAM, -16 (-16.0) for QPSK), it is unused, which causes an issue of poor data usage efficiency.

In addition, in the conventional technology, as shown in Figures 30 to 32, at the boundary where the output bit of the symbol demapping circuit 22 changes from "1" to "0", the LLR of the output bit "1" immediately before it changes to "0" is 1, whereas the LLR of the output bit "0" immediately after the change is 0, resulting in an imbalance in the generated LLR values at the boundary where the value of the output bit changes.

In addition, in the conventional technology, LLRs are expressed in 4 bits, which increases the circuit scale of the symbol demapping circuit 22 and the downstream error correction decoding circuit 23, resulting in an increase in power consumption. If an attempt is made to simply delete the lower bits of the LLR and express the LLR in 2 bits in order to reduce the number of bits of the LLR value, as shown in FIG. 34, the ratio of 0s and 1s is not maintained in the LLR with the lower 2 bits deleted compared to the conventional 4-bit LLR, and this causes an issue that it becomes impossible to correctly distinguish between correction candidates when correcting errors.

Patent No. 6633262

The present invention has been made to solve the above problems, and aims to provide a symbol demapping circuit, a receiving device, and a symbol demapping method that can realize highly efficient symbol demapping processing.

The symbol demapping circuit of the present invention comprises a hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated, a likelihood information derivation unit configured to derive likelihood information for each bit of the bit sequence, and a weighting processing unit configured to weight the received signal that has been multi-level modulated so that the number of pieces of likelihood information of 0 or 1 at the boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4, and the likelihood information derivation unit is characterized in that it uses the received signal that has been subjected to the weighting process as input and expresses the likelihood information in 2 bits.
In addition, the symbol demapping circuit of the present invention comprises a hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated, a likelihood information derivation unit configured to derive likelihood information for each bit of the bit sequence , and a weighting processing unit configured to weight the received signal that has been multi-level modulated so that the number of the likelihood information of 0 or 1 at the boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4, and the likelihood information derivation unit is characterized in that it uses the received signal that has been subjected to the weighting process as an input and derives 2-bit of the likelihood information using a mid-riser type input/output characteristic.
Furthermore, the symbol demapping circuit of the present invention comprises a reception amplitude adjustment unit configured to adjust the input amplitude value of a reception signal that has been multi-level modulated to 32/33.5 times in PCS reception processing, a hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point that is closest to a reception symbol based on the reception signal with the adjusted input amplitude value, and a likelihood information derivation unit configured to derive likelihood information for each bit of the bit sequence, and is characterized in that the likelihood information derivation unit receives the reception signal with the adjusted input amplitude value as input and derives the likelihood information using an SD table in which the likelihood information for the input amplitude is set.
The receiving device of the present invention is also characterized in that it comprises the symbol demapping circuit and an error correction decoding circuit configured to perform error correction decoding processing of the bit string based on the likelihood information and decode the received data.

Furthermore, the symbol demapping method of the present invention includes a first step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated; a second step of weighting the received signal that has been multi-level modulated so that the number of likelihood information pieces of 0 or 1 at the boundary where the value of the output bit of the first step changes becomes four; and a third step of deriving the likelihood information for each bit of the bit string using the weighted received signal as an input, wherein the third step includes a step of expressing the likelihood information in two bits.
Furthermore, the symbol demapping method of the present invention includes a first step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated; a second step of weighting the received signal that has been multi-level modulated so that the number of pieces of likelihood information of 0 or 1 at the boundary where the value of the output bit of the first step changes becomes four; and a third step of deriving the likelihood information for each bit of the bit string using the weighted received signal as an input, wherein the third step includes a step of deriving 2 bits of the likelihood information using a midriser type input/output characteristic.
Furthermore, the symbol demapping method of the present invention includes, in PCS receiving processing, a first step of adjusting an input amplitude value of a received signal that has been multi-level modulated to 32/33.5 times , a second step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted, and a third step of deriving likelihood information for each bit of the bit string, wherein the third step includes a step of deriving the likelihood information using an SD table in which the likelihood information for the input amplitude is set, using the received signal whose input amplitude value has been adjusted as an input.

According to the present invention, it is possible to generate likelihood information even when the input amplitude of the received signal is at a minimum value, thereby improving the efficiency of data usage. In addition, the present invention can solve the problem that the generated values of likelihood information become unbalanced at the boundary where the value of the output bit of the hard decision value derivation unit changes.

In addition, in the present invention, by providing a weighting processing unit, it is possible to maintain the number of low likelihood allocations at the boundary where the value of the output bit of the hard decision value derivation unit changes. As a result, in the present invention, it is possible to solve the problem that it becomes impossible to correctly distinguish between correction candidates when correcting errors due to a reduction in the bit width of the likelihood information, and the output bit with a high error probability can be correctly selected and corrected by the downstream error correction decoding circuit. In addition, in the present invention, the circuit scale of the symbol demapping circuit and the downstream error correction decoding circuit can be reduced compared to the conventional case, thereby reducing power consumption.

FIG. 1 is a block diagram showing the configuration of a transmitting device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a receiving device according to a first embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a symbol demapping circuit of a receiving device according to a first embodiment of the present invention. FIG. 4 is a flow chart for explaining the operation of the symbol demapping circuit of the receiving device according to the first embodiment of the present invention. FIG. 5 is a diagram showing an example of input/output characteristics of a mid-riser type. FIG. 6 is a diagram showing an example of the result of demapping processing performed by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM. FIG. 7 is a diagram showing an example of the result of demapping processing performed by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM. FIG. 8 is a diagram showing an example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is QPSK. FIG. 9 is a diagram for explaining the output of the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM or QPSK. FIG. 10 is a diagram for explaining boundaries at which the values of the output bits of the symbol demapping circuit according to the first embodiment of the present invention change. FIG. 11 is a diagram showing input/output characteristics of a mid-riser type for generating an LLR in the first embodiment of the present invention. FIG. 12 is a diagram showing a specific example of mid-tread type input/output characteristics of a conventional LLR derivation unit. FIG. 13 is a diagram showing a specific example of mid-riser type input/output characteristics of the LLR derivation unit according to the first embodiment of the present invention. FIG. 14 is a diagram showing a specific example of input/output characteristics when a weighting processing unit is provided in front of the LLR derivation unit according to the first embodiment of the present invention. FIG. 15 is a diagram showing another example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM. FIG. 16 is a diagram showing another example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM. FIG. 17 is a diagram showing another example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM. FIG. 18 is a diagram showing another example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is 16QAM. FIG. 19 is a diagram showing another example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is QPSK. FIG. 20 is a diagram showing another example of the result of demapping processing by the symbol demapping circuit according to the first embodiment of the present invention when the multi-level modulation method is QPSK. FIG. 21 is a block diagram showing the configuration of a symbol demapping circuit in a receiving device according to a second embodiment of the present invention. FIG. 22 is a diagram showing the amplitude distribution of a 16QAM signal that has not been subjected to PCS processing. FIG. 23 is a diagram showing the amplitude distribution of a PCS-16QAM signal. FIG. 24 is a diagram showing an example of the result of demapping processing performed by a conventional symbol demapping circuit when the multi-level modulation method is PCS-16QAM. FIG. 25 is a diagram showing an example of the result of demapping processing performed by a conventional symbol demapping circuit when the multi-level modulation method is PCS-16QAM. FIG. 26 is a diagram showing the relationship between the LSB threshold shift amount of the SD table and the BER. FIG. 27 is a diagram for explaining the effect of the second embodiment of the present invention. FIG. 28 is a block diagram showing the configuration of a receiving device in a conventional communication system. FIG. 29 is a diagram showing input/output characteristics of a mid-tread type. FIG. 30 is a diagram showing an example of the result of demapping processing performed by a conventional symbol demapping circuit when the multi-level modulation method is 16QAM. FIG. 31 is a diagram showing an example of the result of demapping processing performed by a conventional symbol demapping circuit when the multi-level modulation method is 16QAM. FIG. 32 is a diagram showing an example of the result of demapping processing performed by a conventional symbol demapping circuit when the multi-level modulation method is QPSK. FIG. 33 is a diagram for explaining the output of the symbol demapping circuit when the multi-level modulation method is 16QAM or QPSK. FIG. 34 is a diagram for explaining a problem that occurs when the lower bits of the LLR are deleted.

[First embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of a transmitting device in a communication system according to a first embodiment of the present invention. The communication system is composed of a transmitting device 1 and a receiving device. The transmitting device 1 generates a transmission signal by encoding and modulating transmission data. The transmission signal is received by the receiving device via a wired or wireless communication path. The receiving device demodulates and decodes the received signal to generate received data.

The transmitting device 1 includes an error correction coding circuit 10 , a symbol mapping circuit 11 , a modulation circuit 12 , and a DA conversion circuit 13 .
The error correction coding circuit 10 performs, for example, turbo coding or LDPC (Low Density Parity Check) coding on the transmission data to generate coded data.

The symbol mapping circuit 11 performs carrier modulation by allocating the coded data output from the error correction coding circuit 10 to symbol points such as QPSK and 16QAM.
The modulation circuit 12 performs, for example, OFDM modulation on the data carrier-modulated by the symbol mapping circuit 11 to generate a modulated signal.
The DA conversion circuit 13 converts the modulated signal from a digital signal to an analog signal to generate a transmission signal.

Figure 2 is a block diagram showing the configuration of a receiving device of a communication system according to this embodiment. The receiving device 2a includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22a, and an error correction decoding circuit 23.

The symbol demapping circuit 22a of this embodiment uses hard decision to output a bit string corresponding to the ideal signal point closest to the received signal (received symbol) from the received signal output from the demodulation circuit 21, and also outputs an LLR, which is likelihood information for each bit of the bit string.

Figure 3 is a block diagram showing the configuration of the symbol demapping circuit 22a. The symbol demapping circuit 22a is composed of a hard decision value derivation unit 220, a weighting processing unit 221, and an LLR derivation unit 222 (likelihood information derivation unit).

Figure 4 is a flow chart explaining the operation of the symbol demapping circuit 22a. The hard decision value derivation unit 220 derives a bit string (hard decision value) based on the coordinates on the I axis and the coordinates on the Q axis of the received signal that has been multi-level modulated. The hard decision value derivation unit 220 converts the coordinates (input amplitude) of the received signal (received symbol) into a bit string, for example, using an internal table (step S100 in Figure 4).

The weighting processing unit 221 applies weighting to the multi-level modulated received signal (step S101 in FIG. 4). The LLR derivation unit 222 derives an LLR for each bit of the bit string output from the hard decision value derivation unit 220 based on the I-axis coordinate and the Q-axis coordinate of the weighted received signal (step S102 in FIG. 4).
In this embodiment, the LLR derivation unit 222 performs a mid-riser type demapping process on the symbols to generate LLRs. An example of the mid-riser type input/output characteristic is shown in FIG.

An example of the result of demapping processing by the symbol demapping circuit 22a of this embodiment when the multi-level modulation method is 16QAM is shown in Figures 6 and 7. Also, an example of the result of demapping processing by the symbol demapping circuit 22a when the multi-level modulation method is QPSK is shown in Figure 8.

Figures 6 to 8 only show the coordinates (input amplitude) on the I axis of the received symbol. As above, an input amplitude of, for example, "31 (+31.0)" in Figures 6 and 7 means that 31 is the representative value for inputs in the range of +30.5 to +31.5. Similarly, an input amplitude of, for example, "15 (+15.0)" in Figure 8 means that 15 is the representative value for inputs in the range of +14.5 to +15.5.

As shown in FIG. 9A, the symbol demapping circuit 22a corresponding to 16QAM outputs the MSB and LSB and the LLR of each of these bits for 64 levels of input amplitude represented by 6 bits. In FIG. 6 to FIG. 8, LLR:MSB indicates the LLR of the MSB, and LLR:LSB indicates the LLR of the LSB.

As shown in FIG. 9B, a symbol demapping circuit 22a corresponding to QPSK outputs a 1-bit output DT and the LLR of this bit for an input amplitude of 32 stages represented by 5 bits.
In either case of 16QAM or QPSK, the LLR is expressed by four levels of values from 0 to 3 using two bits.

As can be seen from the constellation shown in Figure 10, in the case of 16QAM, there is one boundary on the I axis where the value of the output bit of the symbol demapping circuit 22a changes for the MSB, whereas there are two boundaries for the LSB. In the example of Figure 10, 80 indicates the boundary where the MSB value changes, and 81 and 82 indicate the boundaries where the LSB value changes.

Therefore, in the case of the symbol demapping circuit 22a corresponding to 16QAM, there are mid-riser type input/output characteristics as shown in FIG. 11(A) for outputting four-level LLR of MSB for an input amplitude in the range of "0" to "31", mid-riser type input/output characteristics as shown in FIG. 11(B) for outputting four-level LLR of MSB for an input amplitude in the range of "-32" to "-1", and mid-riser type input/output characteristics as shown in FIG. 11(C) for outputting four-level LLR of LSB for an input amplitude in the range of "16" to "31". It is necessary to prepare the following output characteristics and mid-riser type input/output characteristics as shown in FIG. 11(D) for outputting LLRs in four stages of LSB for an input amplitude in the range of "0" to "15", mid-riser type input/output characteristics with input/output characteristics similar to FIG. 11(C) for outputting LLRs in four stages of LSB for an input amplitude in the range of "-16" to "-1", and mid-riser type input/output characteristics with input/output characteristics similar to FIG. 11(D) for outputting LLRs in four stages of LSB for an input amplitude in the range of "-32" to "-17".

In the case of a symbol demapping circuit 22a that supports QPSK, it is necessary to prepare a mid-riser type input/output characteristic whose input/output characteristics are similar to those in FIG. 11(A) and which outputs four levels of LLR for an input amplitude in the range of "0" to "15", and a mid-riser type input/output characteristic whose input/output characteristics are similar to those in FIG. 11(B) and which outputs four levels of LLR for an input amplitude in the range of "-16" to "-1".

As shown in Figures 30 to 32, in the conventional technology, when the input amplitude is at the minimum value (-32 (-32.0) for 16QAM, -16 (-16.0) for QPSK), the signal is unused, resulting in poor data usage efficiency.
In contrast, in this embodiment, the input amplitude is converted to an LLR using a mid-riser type input/output characteristic, so that an LLR can be generated even when the input amplitude is at the minimum value, thereby improving the efficiency of data usage.

In addition, in this embodiment, by converting the input amplitude into LLR using mid-riser type input/output characteristics, as shown in Figures 6 to 8, at the boundary where the output bit of the symbol demapping circuit 22a changes from "1" to "0", the LLR of the output bit "1" immediately before it changes to "0" can be set to 0, and the LLR of the output bit "0" immediately after the change can also be set to 0. Also, at the boundary where the output bit of the symbol demapping circuit 22a changes from "0" to "1", the LLR of the output bit "0" immediately before it changes to "1" can be set to 0, and the LLR of the output bit "1" immediately after the change can also be set to 0. In this way, in this embodiment, the problem of the LLR generation values becoming unbalanced at the boundary where the value of the output bit changes can be resolved.

In addition, in this embodiment, since the LLR is expressed in 2 bits, the circuit scale of the symbol demapping circuit 22a and the error correction decoding circuit 23 can be reduced compared to the conventional case, and power consumption can be reduced. However, it is necessary to maintain the ratio of 0s and 1s in the LLR compared to the conventional 4-bit representation of the LLR.

Therefore, in this embodiment, a weighting processing unit 221 is provided before the LLR derivation unit 222, and weighting is applied to the received signal that has been multi-level modulated. This makes it possible to maintain the number of allocations with low likelihood (low bit reliability) at the boundary where the value of the output bit of the symbol demapping circuit 22a changes. A specific example of mid-tread type input/output characteristics of a conventional LLR derivation unit is shown in FIG. 12, a specific example of mid-riser type input/output characteristics of the LLR derivation unit 222 of this embodiment is shown in FIG. 13, and a specific example of input/output characteristics when the weighting processing unit 221 is provided before the LLR derivation unit 222 is shown in FIG. 14. In FIGS. 12 to 14, 300 indicates the characteristics of the LLR of the MSB, and 301 indicates the characteristics of the LLR of the LSB.

In the case of the symbol demapping circuit 22a corresponding to 16QAM, the weighting processing unit 221 includes a weighting processing unit for the MSB and a weighting processing unit for the LSB. That is, in the case of the symbol demapping circuit 22a corresponding to 16QAM, it is necessary to prepare the input/output characteristics of the weighting processing unit 221 for the MSB, which applies weighting to the input amplitude in the range of "-32" to "31" to generate an output amplitude in the range of "-32" to "31". It is also necessary to prepare the input/output characteristics of the weighting processing unit 221 for the LSB, which applies weighting to the input amplitude in the range of "0" to "31" to generate an output amplitude in the range of "0" to "31", and the input/output characteristics of the weighting processing unit 221 for the LSB, which applies weighting to the input amplitude in the range of "-32" to "-1" to generate an output amplitude in the range of "-32" to "-1".

The LLR derivation unit 222 takes the output of the weighting processing unit 221 for the MSB as input to derive the LLR of the MSB, and takes the output of the weighting processing unit 221 for the LSB as input to derive the LLR of the LSB.

In the case of a symbol demapping circuit 22a that supports QPSK, it is sufficient to prepare input/output characteristics for the weighting processing unit 221 that applies weighting to an input amplitude in the range of "-16" to "15" to generate an output amplitude in the range of "-16" to "15."

In this embodiment, low likelihood means that the LLR is 0 or 1. In the conventional technology, the number of LLRs of 0 or 1 at the boundary where the output bit of the symbol demapping circuit 22 changes from "1" to "0" or from "0" to "1" is three. On the other hand, in this embodiment, in order to solve the problem of LLRs becoming unbalanced at the boundary where the value of the output bit changes as described above, the number of LLRs of 0 is increased by one, so that the number of LLRs of 0 or 1 at the boundary where the value of the output bit changes is four.

In this way, in this embodiment, the number of low-likelihood allocations can be maintained at the boundary where the value of the output bit of the symbol demapping circuit 22a changes. In this embodiment, the problem that it becomes impossible to correctly distinguish between correction candidates when correcting an error due to the reduction in the bit width of the LLR can be resolved, and the error correction decoding circuit 23 can correctly select and correct output bits with a high error probability.

In this embodiment, an example of generating a 2-bit LLR has been described, but a 3-bit LLR may also be generated. An example of generating a 3-bit LLR using the symbol demapping circuit 22a configured as shown in FIG. 3 is shown in FIGS. 15 to 20. FIGS. 15 to 18 show the results of demapping processing by the symbol demapping circuit 22a when the multi-level modulation method is 16QAM, and FIGS. 19 and 20 show the results of demapping processing by the symbol demapping circuit 22a when the multi-level modulation method is QPSK.

In Figures 15 to 20, only the coordinates (input amplitude) of the received symbol on the I axis are shown. In the examples of Figures 15 to 18, the symbol demapping circuit 22a corresponding to 16QAM outputs the MSB and LSB and the LLRs of each of these bits for 128 levels of input amplitude represented by 7 bits.

In the examples of FIGS. 19 and 20, the symbol demapping circuit 22a corresponding to QPSK outputs a 1-bit output DT and the LLR of this bit for an input amplitude of 64 stages represented by 6 bits.
In either case of 16QAM or QPSK, the LLR is expressed by 3 bits and has 8 levels from 0 to 7.

In the case of the symbol demapping circuit 22a corresponding to the examples of Figures 15 to 18, there are mid-riser type input/output characteristics as shown in Figure 11(A) for outputting eight-level LLR of MSB for an input amplitude in the range of "0" to "63", mid-riser type input/output characteristics as shown in Figure 11(B) for outputting eight-level LLR of MSB for an input amplitude in the range of "-64" to "-1", and mid-riser type input/output characteristics as shown in Figure 11(C) for outputting eight-level LLR of LSB for an input amplitude in the range of "32" to "64". It is necessary to prepare input/output characteristics of a mid-riser type as shown in FIG. 11(D) for outputting eight LSB-level LLRs for an input amplitude in the range of "0" to "31", input/output characteristics of a mid-riser type as shown in FIG. 11(C) for outputting eight LSB-level LLRs for an input amplitude in the range of "-32" to "-1", and input/output characteristics of a mid-riser type as shown in FIG. 11(D) for outputting eight LSB-level LLRs for an input amplitude in the range of "-64" to "-33".

In the case of the symbol demapping circuit 22a corresponding to the examples of Figures 19 and 20, it is necessary to prepare a mid-riser type input/output characteristic whose input/output characteristics are similar to those of Figure 11(A) and which outputs eight levels of LLR for an input amplitude in the range of "0" to "31", and a mid-riser type input/output characteristic whose input/output characteristics are similar to those of Figure 11(B) and which outputs eight levels of LLR for an input amplitude in the range of "-32" to "-1".

In the case of the symbol demapping circuit 22a corresponding to the examples of Figures 15 to 18, it is necessary to prepare input/output characteristics of the weighting processing unit 221 for MSB, which applies weighting to an input amplitude in the range of "-64" to "63" to generate an output amplitude in the range of "-64" to "63". It is also necessary to prepare input/output characteristics of the weighting processing unit 221 for LSB, which applies weighting to an input amplitude in the range of "0" to "63" to generate an output amplitude in the range of "0" to "63", and input/output characteristics of the weighting processing unit 221 for LSB, which applies weighting to an input amplitude in the range of "-64" to "-1" to generate an output amplitude in the range of "-64" to "-1".

In the case of the symbol demapping circuit 22a corresponding to the examples of Figures 19 and 20, it is sufficient to prepare the input/output characteristics of the weighting processing unit 221 that applies weighting to input amplitudes in the range of "-32" to "31" to generate output amplitudes in the range of "-32" to "31".

Note that although Figures 6 to 8 and Figures 15 to 20 only show the coordinates of the received symbols on the I axis, the symbol demapping circuit 22a can also process the coordinates of the received symbols on the Q axis (input amplitude) in the same way as the coordinates on the I axis.

[Second embodiment]
Next, a second embodiment of the present invention will be described. In this embodiment, the overall configuration of the transmitting device 1 and the receiving device 2a is similar to that of the first embodiment, so the description will be given using the symbols in Figures 1 and 2. In this embodiment, a method in which PCS (Probabilistic Constellation Shaping) processing is applied in addition to orthogonal modulation such as 16QAM and QPSK as a multi-level modulation method will be described. In this embodiment, an example of PCS-16QAM in which PCS processing is applied to 16QAM will be described.

Figure 21 is a block diagram showing the configuration of the symbol demapping circuit 22a of the receiving device 2a of this embodiment. The symbol demapping circuit 22a is composed of a hard decision value derivation unit 220a, an LLR derivation unit 222a (likelihood information derivation unit), and a reception amplitude adjustment unit 223.

The operation of the hard decision value derivation unit 220a is similar to that of the hard decision value derivation unit 220 in the first embodiment, but it converts the PCS-16QAM signal into a bit string due to characteristics corresponding to PCS-16QAM. The operation of the LLR derivation unit 222a is similar to that of the LLR derivation unit 222 in the first embodiment, but it derives LLRs from the PCS-16QAM signal due to characteristics corresponding to PCS-16QAM.

Figure 22 shows the amplitude distribution of a 16QAM signal that has not undergone PCS processing. TH1 in Figure 22 indicates the MSB threshold where the MSB is 1 or 0, and TH2 indicates the LSB threshold where the LSB is 1 or 0. The LSB threshold of a 16QAM signal that has not undergone PCS processing is the symbol midpoint value, "+32."

The amplitude distribution of the PCS-16QAM signal is shown in Fig. 23. In the case of a 16QAM signal that has been subjected to PCS processing, the LSB threshold TH2 shifts outward.
An example of the result of demapping processing by a conventional symbol demapping circuit when the multi-level modulation method is PCS-16QAM is shown in Figures 24 and 25. Bit strings and LLRs are generated based on a SD (Soft Decision) table. "+0", "+1", "+2", and "+3" in Figures 24 and 25 indicate input amplitude values of PCS-16QAM. The example of the SD table in Figures 24 and 25 shows a case where the LSB threshold TH2 is set to the input amplitude value "+2".

Figure 26 shows the relationship between the amount of LSB threshold shift in the SD table and the BER (Bit Error Rate). Thus, in PCS, the BER improves by shifting the threshold in the SD table. In Figure 26, 100 shows the case where the standard deviation σ of the noise component of the PCS-16QAM signal is 0.51, 101 shows the case where σ is 0.52, and 102 shows the case where σ is 0.53.

However, by changing the SD table, only integer shifts of +1 or +2 can be achieved. Therefore, in this embodiment, a reception amplitude adjustment unit 223 is provided. The reception amplitude adjustment unit 223 multiplies the input amplitude value of the PCS-16QAM signal by, for example, 32/33.5. As a result, in this embodiment, an LSB threshold shift equivalent to a +1.5 shift can be achieved without changing the SD tables used by the hard decision value derivation unit 220a and the LLR derivation unit 222a.

The effect of this embodiment will be explained using FIG. 27. The horizontal axis of FIG. 27 indicates SNR (Signal to Noise ratio), and the vertical axis indicates BER after the error correction decoding circuit performs error correction decoding processing based on LLR on the bit string output from the symbol demapping circuit 22a. 200 in FIG. 27 indicates the case without coding. 201 indicates the case where a PCS-16QAM signal is input to the symbol demapping circuit and an LSB threshold shift of +1 is performed by changing the SD table. 202 indicates the case where a PCS-16QAM signal is input to the symbol demapping circuit and an LSB threshold shift of +2 is performed by changing the SD table. 203 indicates the case where a PCS-16QAM signal is input to the symbol demapping circuit 22a in this embodiment.

As described above, in this embodiment, by providing the reception amplitude adjustment unit 223, it is possible to achieve an LSB threshold shift equivalent to a +1.5 shift without changing the SD table, enabling high-performance, low-power error correction.

Each of the transmitting device 1 and receiving device 2a described in the first and second embodiments can be configured with hardware logic, such as an ASIC (application specific integrated circuit) or an FPGA (field-programmable gate array). Also, at least a part of each of the transmitting device 1 and receiving device 2a may be realized by a computer. In this case, the CPU of each device executes the processing described in the first and second embodiments according to a program stored in the memory.

The present invention can be applied to a technique for decoding a received signal that has been multilevel modulated.

1...Transmitting device, 2a...Receiving device, 10...Error correction coding circuit, 11...Symbol mapping circuit, 12...Modulation circuit, 13...DA conversion circuit, 20...AD conversion circuit, 21...Demodulation circuit, 22a...Symbol demapping circuit, 23...Error correction decoding circuit, 220, 220a...Hard decision value derivation unit, 221...Weighting processing unit, 222, 222a...LLR derivation unit, 223...Reception amplitude adjustment unit.

Claims (7)

a hard decision value derivation unit configured to derive a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated;
a likelihood information derivation unit configured to derive likelihood information for each bit of the bit string;
a weighting processing unit configured to weight the received signal that has been multilevel modulated so that the number of pieces of likelihood information that are 0 or 1 at the boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4;
A symbol demapping circuit, characterized in that the likelihood information derivation unit receives the weighted received signal as an input and expresses the likelihood information in two bits. a hard decision value derivation unit configured to derive a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated;
a likelihood information derivation unit configured to derive likelihood information for each bit of the bit string ;
a weighting processing unit configured to weight the received signal that has been multilevel modulated so that the number of pieces of likelihood information that are 0 or 1 at the boundary where the value of the output bit of the hard decision value derivation unit changes becomes 4;
A symbol demapping circuit, characterized in that the likelihood information derivation unit receives the weighted received signal as an input and derives the 2-bit likelihood information using a mid-riser type input/output characteristic. A reception amplitude adjustment unit configured to adjust an input amplitude value of a reception signal that has been multi-level modulated to 32/33.5 times in a PCS reception process;
a hard decision value derivation unit configured to derive a bit sequence corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted;
a likelihood information derivation unit configured to derive likelihood information for each bit of the bit string,
The symbol demapping circuit is characterized in that the likelihood information derivation unit receives as input the received signal whose input amplitude value has been adjusted, and derives the likelihood information using an SD table in which the likelihood information for the input amplitude is set. A symbol demapping circuit according to any one of claims 1 to 3;
an error correction decoding circuit configured to perform an error correction decoding process on the bit string based on the likelihood information and decode received data. A first step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated;
a second step of weighting the received signal that has been subjected to the multi-level modulation so that the number of pieces of likelihood information of 0 or 1 at the boundary where the value of the output bit of the first step changes becomes 4;
a third step of deriving the likelihood information for each bit of the bit string using the weighted received signal as an input;
A symbol demapping method, wherein the third step includes a step of expressing the likelihood information in two bits. A first step of deriving a bit string corresponding to an ideal signal point closest to a received symbol based on a received signal that has been multi-level modulated;
a second step of weighting the received signal that has been subjected to the multi-level modulation so that the number of pieces of likelihood information of 0 or 1 at the boundary where the value of the output bit of the first step changes becomes 4;
a third step of deriving the likelihood information for each bit of the bit string using the weighted received signal as an input ;
A symbol demapping method, wherein the third step includes a step of deriving the 2-bit likelihood information using a midriser type input/output characteristic. In a PCS receiving process, a first step of adjusting an input amplitude value of a received signal that has been multi-level modulated to 32/33.5 times ;
a second step of deriving a bit sequence corresponding to an ideal signal point closest to a received symbol based on the received signal whose input amplitude value has been adjusted;
and a third step of deriving likelihood information for each bit of the bit string;
The symbol demapping method according to claim 3, wherein the third step includes a step of using as input the received signal whose input amplitude value has been adjusted, and deriving the likelihood information using an SD table in which the likelihood information for the input amplitude is set.