JP7701087B2 - Silicon carbide MOSFET device and method for fabricating same - Google Patents

Description

cross reference

This application claims priority to a Chinese patent application, application number 202210004474.8, entitled "Silicon carbide MOSFET device and manufacturing method thereof," filed with the State Intellectual Property Office of the People's Republic of China on January 4, 2022, the entire contents of which are incorporated herein by reference.

This application claims priority to a Chinese patent application entitled "Silicon Carbide MOSFET Device," application number 202220017322.7, filed with the State Intellectual Property Office of the People's Republic of China on January 4, 2022, the entire contents of which are incorporated herein by reference.

This application relates to the technical field of semiconductor devices, and in particular to silicon carbide (SiC) MOSFET devices and methods for manufacturing the same.

With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

The main structure that electronic devices use to realize various functions is the integrated circuit, and MOSFET devices are important components of integrated circuits. Silicon carbide MOSFET devices have become a major development direction in the semiconductor field due to their excellent properties in high power applications.

Existing silicon carbide MOSFET devices still have shortcomings, and their structures and manufacturing methods need to be further optimized to improve performance.

An epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on a surface of the substrate;
a well region, a source region, and a trench gate disposed within the epitaxial layer,

the trench gate includes a trench located in a surface of the epitaxial layer opposite the substrate, and a gate located in the trench, with a gate dielectric layer between the gate and the trench;
the source region surrounds the trench and contacts a sidewall of the trench;
a first layer well region, a second layer well region, and a third layer well region provided in that order in a direction toward the source region of the substrate, a bottom of the trench being located between the first layer well region and the third layer well region, the third layer well region surrounding the trench and contacting a sidewall of the trench, a doping region being in an epitaxial layer below the trench, the first layer well region surrounding the doping region and contacting the doping region, a partial epitaxial layer being between the first layer well region and the third layer well region, the second layer well region being located on both sides of the partial epitaxial layer, a masking layer being in the partial epitaxial layer to protect the trench gate bottom, the masking layer being located below the trench, and having the same doping type as the well region of each layer.

Preferably, in the silicon carbide MOSFET device described above, the vertical projection of the doped region on the substrate lies within the vertical projection of the trench on the substrate;
A vertical projection of the trench on the substrate lies within a vertical projection of the partial epitaxial layer on the substrate, the two vertical projections having a non-zero spacing.

Preferably, in the silicon carbide MOSFET device described above, there is also a connection region in the partial epitaxial layer connecting the masking layer and the first layer well region, the connection region having the same doping type as the well region of each layer.

Preferably, in the above silicon carbide MOSFET device, the first-layer well region includes a first portion of a first-layer well region and a second portion of a first-layer well region located on both sides of the trench,
the first-layer well region of the first portion is connected to the masking layer via a plurality of the connection regions arranged in sequence in a first direction, and/or the first-layer well region of the second portion is connected to the masking layer via a plurality of the connection regions arranged in sequence in the first direction;
Here, the first direction is parallel to the substrate and parallel to the extension direction of the trench.

Preferably, in the silicon carbide MOSFET device described above, there is at least one said doped region beneath said trench,
When there are a plurality of the doped regions, the plurality of doped regions are arranged in sequence in a first direction, where the first direction is parallel to the substrate and parallel to an extension direction of the trench.

Preferably, in the silicon carbide MOSFET device described above, the distance from the masking layer to the bottom of the trench in a direction perpendicular to the substrate is less than the distance to the first layer well region.

Preferably, in the silicon carbide MOSFET device described above, the masking layer contacts the bottom of the trench.

Preferably, in the above silicon carbide MOSFET device, the second-layer well region includes a first portion of the second-layer well region and a second portion of the second-layer well region located on both sides of the trench,
The second-level well region of the first portion and the second-level well region of the second portion each have an integrated structure.

Preferably, in the above silicon carbide MOSFET device, the second-layer well region includes a first portion of the second-layer well region and a second portion of the second-layer well region located on both sides of the trench,
The second-layer well region of the first portion and the second-layer well region of the second portion each include a plurality of subregions arranged in sequence in a first direction, and between two adjacent subregions in the first direction there is a current spreading region having an opposite doping type to that of the subregions, where the first direction is parallel to the substrate and parallel to the extension direction of the trench.

Preferably, in the silicon carbide MOSFET device described above, the doping type of the well region of each layer, the masking layer and the connection region is the same, and the doping concentration of the connection region is higher than the doping concentration of the well region of each layer.

Preferably, in the silicon carbide MOSFET device described above, for the same connection region, the connection region extends from the bottom of the trench at least into the first-layer well region, or a portion of the connection region extends from the bottom of the trench at least into the first-layer well region, and another portion extends from the surface of the epitaxial layer along the sidewall of the trench at least into the first-layer well region.

The present application also provides a method for manufacturing a silicon carbide MOSFET device according to any one of the above claims, comprising:
Providing an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on a surface of the substrate;
forming a well region, a source region, and a trench gate in the epitaxial layer,
the trench gate includes a trench located in a surface of the epitaxial layer opposite the substrate, and a gate located in the trench, with a gate dielectric layer between the gate and the trench;
the source region surrounds the trench and contacts a sidewall of the trench;
The well region includes a first layer well region, a second layer well region, and a third layer well region arranged in order in a direction toward the source region of the substrate, a bottom of the trench is located between the first layer well region and the third layer well region, the third layer well region surrounds the trench and contacts a sidewall of the trench, a doping region is located in the epitaxial layer below the trench, the first layer well region surrounds the doping region and contacts the doping region, a partial epitaxial layer is located between the first layer well region and the third layer well region, the second layer well region is located on both sides of the partial epitaxial layer, and a masking layer for protecting the trench gate bottom is located in the partial epitaxial layer, the masking layer is located under the trench and has the same doping type as the well region of each layer.

Preferably, in the above manufacturing method, the epitaxial layer includes a first epitaxial layer provided on a surface of the substrate, a second epitaxial layer provided on a surface of the first epitaxial layer opposite to the substrate, and a third epitaxial layer provided on a surface of the second epitaxial layer opposite to the first epitaxial layer, the second epitaxial layer having a region to be implanted and a first-layer well region surrounding the region to be implanted;
Forming a well region, a source region, and a trench gate in the epitaxial layer includes:
forming the source region, the second-level well region, and the third-level well region in a surface of the third epitaxial layer opposite the substrate;
forming the trench in a surface of the third epitaxial layer opposite the substrate;
forming the masking layer and the doping region based on the trench;
forming a connection region connecting the masking layer and the first-level well region based on the trench;
forming a gate dielectric layer and a gate in the trench.

As can be seen from the above description, in the silicon carbide MOSFET device and the manufacturing method thereof provided by the technical solution of the present application, the silicon carbide MOSFET device includes an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on the surface of the substrate, and a well region, a source region, and a trench gate provided in the epitaxial layer, wherein the trench gate includes a trench located in the surface of the epitaxial layer opposite the substrate, and a gate located in the trench, a gate dielectric layer is present between the gate and the trench, the source region surrounds the trench and contacts the sidewall of the trench, and the well region is a first layer well formed in the substrate in a direction toward the source region. The trench includes a well region, a second layer well region, and a third layer well region, the bottom of the trench is located between the first layer well region and the third layer well region, the third layer well region surrounds the trench and contacts the sidewalls of the trench, there is a doping region in the epitaxial layer below the trench, the first layer well region surrounds the doping region and contacts the doping region, there is a partial epitaxial layer between the first layer well region and the third layer well region, the second layer well region is located on both sides of the partial epitaxial layer, and there is a masking layer in the partial epitaxial layer to protect the trench gate bottom, the masking layer is located below the trench and has the same doping type as the well region of each layer.

In order to more clearly describe the technical solutions in the embodiments of the present application or the related art, the necessary drawings used in the description of the embodiments or the prior art are briefly described below. Obviously, the drawings in the following description are only the embodiments of the present application, and those skilled in the art can obtain other drawings based on the drawings provided without creative efforts.

The structures, ratios, sizes, etc. shown in the drawings of this specification are used only to fit the contents disclosed in the specification so that those skilled in the art can understand and read them, and are not used to limit the limiting conditions under which this application can be implemented, and therefore have no technically substantial meaning. Any modification of the structure, change in the ratio relationship, or adjustment of the size shall still be included in the scope of the technical content disclosed in this application without affecting the effects that can be produced and the objectives that can be achieved by this application.
FIG. 1 is a schematic diagram of the structure of a DMOSFET. FIG. 2 is a schematic diagram of the structure of a UMOSFET. FIG. 3 is a waveform diagram showing the voltage overshoot and oscillation phenomenon at the moment of MOSFET switching. Figure 4a is a structural schematic diagram of a silicon carbide MOSFET device provided by an embodiment of the present application, Figure 4b is a schematic diagram of the main current path at the moment when the silicon carbide MOSFET device shown in Figure 4a is turned on, and Figure 4c is a schematic diagram of the equivalent parasitic parameters of the silicon carbide MOSFET device shown in Figure 4b. FIG. 5 is a structural schematic diagram of another silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 6 is a three-dimensional view of a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 7 is a top view of the spacer well regions, trenches, doping regions and connection regions in the silicon carbide MOSFET device shown in FIG. FIG. 8 is a first cross-sectional view of the silicon carbide MOSFET device shown in FIG. 6 in a direction perpendicular to the trench extension. FIG. 9 is a second cross-sectional view of the silicon carbide MOSFET device shown in FIG. 6 in a direction perpendicular to the trench extension. FIG. 10 is a three-dimensional view of another silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 11 is a top view of the spacer well regions, trenches, doping regions and connection regions in the silicon carbide MOSFET device shown in FIG. FIG. 12 is a structural schematic diagram of yet another silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 13 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 14 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 15 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 16 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 17 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 18 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 19 is a process flow diagram of a method for fabricating a silicon carbide MOSFET device provided by an embodiment of the present application. FIG. 20 is a layout of the trench design and doping region ion implantation areas of a silicon carbide MOSFET device provided by an embodiment of the present application.

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, but obviously, the described embodiments are only some of the embodiments of the present invention, and are not all of the embodiments. All other embodiments obtained by those skilled in the art without creative efforts based on the embodiments of the present invention are included in the scope of protection of the present invention.

In order to make the above objects, features and advantages of the present invention clear and easily understandable, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.

SiC material has strong appeal for high power due to its excellent properties, making it one of the best materials for high performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and vertical gate trench UMOSFETs.

As shown in FIG. 1, FIG. 1 is a schematic diagram of the structure of a DMOSFET, and includes an n+ (high n-type doping) substrate 2, an n- (low n-type doping) drift region 3 provided on the surface of the substrate 2, a p-type well region 4 located in the drift region 3, and a source region 5 including an n+ doped region 51 and a p+ (high p-type doping) doped region 52 located in the p-type well region. A gate dielectric layer 7 is provided on the surface of the drift region 3, and a gate 8 is provided on the surface of the gate dielectric layer 7. A drain 1 is provided on the surface of the substrate 2 opposite the drift region 3.

The DMOSFET structure employs planar diffusion technology, employing a high melting point material such as a polysilicon gate as a mask, and using the edges of the polysilicon gate to define the p-base and n+ source regions. The name DMOS is derived from this double diffusion process. The lateral diffusion difference between the p-type base and n+ source regions is used to form the surface channel region.

As shown in Figure 2, Figure 2 is a schematic diagram of the structure of a UMOSFET, which differs from the structure shown in Figure 1 in that the UMOSFET is provided with a U-shaped trench, the surface of the U-shaped trench is covered with a gate dielectric layer 7, and the gate 8 is filled into the U-shaped trench. The name UMOSFET with vertical gate trench structure comes from the U-shaped trench structure. This U-shaped trench structure is formed in the gate region using reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the channel width of the active region), which greatly reduces the resistance of the on-state characteristics of the device.

After many years of research on planar SiC MOSFETs in the industry, some manufacturers have taken the initiative to launch commercial products. In the general lateral DMOSFET structure, modern technological advances mean that the on-resistance cannot be reduced even by reducing the MOS cell size. The main reason is that due to the resistance limitations of the JFET neck region, even if smaller photolithography sizes are used, it is difficult to reduce the on-resistance per unit area to 2 mΩ· ^cm2 , but the trench structure can effectively solve this problem. The U-shaped trench structure is shown in Figure 2, and the trench etching technology is adopted in various processes of memory storage capacitor manufacturing to change the conductive channel from lateral to vertical, which eliminates the JFET neck resistance compared with the normal structure, greatly increases the cell density, and improves the current handling capability of the power semiconductor.

However, SiC UMOSFETs still have some problems in practical process fabrication and applications.

1) The high electric field in the SiC drift region creates high electric fields in the gate dielectric layer, and this problem is further exacerbated at the trench corners, which causes the gate dielectric layer to break down quickly under high drain voltages and makes it less resistant to electrostatic effects in harsh environments and high voltage spikes in the circuit.

2) SiC power MOSFETs are mainly used in the fields of high voltage, high frequency, and large current, so spike burrs occur during the high frequency switching process due to parasitic parameters in the circuit, as shown in Figure 3. Figure 3 is a waveform diagram showing the voltage overshoot and oscillation phenomenon at the moment of MOSFET switching. Based on Figure 3, it can be seen that instantaneous overvoltage occurs in the current path of the device and the loss in the switching process increases, or a large surge voltage occurs due to changes in power load, etc., so the ability of the MOSFET to withstand surge voltages and overvoltage protection are also very important.

Conventional MOSFET devices themselves do not have the surge voltage self-suppression ability or overvoltage protection ability, so in practical applications, it is often necessary to design complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits. However, such external matching suppression and overvoltage protection circuits often have time delays, and the high-frequency spike voltage surge during the actual switching process is still borne by the device itself, which may gradually lead to breakdown failure of the channel region of the device and failure of the ohmic contact area of the gate structure and electrode, causing device reliability problems.

3) The depth of ion implantation is limited, making it difficult to technically realize many targeted trench gate protection structures and surge resistance designs. Generally, the trench depth for forming the gate is 1 μm to 2 μm or more, and since it is necessary to protect the gate structure in the trench, the actual fabrication process of the buried protection structure cannot be completed directly by ion implantation. This is because the ion implantation depth is difficult to exceed 1 μm in the silicon carbide process. Due to the characteristics of silicon carbide materials, in order to achieve doping at a deeper implantation depth, high-energy ion implantation causes damage to the lattice, so when fabricating a silicon carbide MOSFET device with a deeper doping region, in the epitaxial wafer fabrication process, it is necessary to form the necessary doping region in the previously formed epitaxial layer by etching and ion implantation, and then form the next epitaxial layer. Therefore, in the conventional process, it is common to form the necessary doping region in the previously formed epitaxial layer by etching and ion implantation, and then form two P-type epitaxial layers of a specific structure, which makes the fabrication process complicated and increases the fabrication cost.

As shown in FIG. 4a, FIG. 4a is a structural schematic diagram of a silicon carbide MOSFET device provided by an embodiment of the present application;
An epitaxial wafer including a semiconductor substrate 10 and an epitaxial layer provided on a surface of the substrate 10;
The epitaxial layer includes a well region, a source region, and a trench gate.

Here, the trench gate includes a trench 20 located in the surface of the epitaxial layer opposite the substrate, and a gate 18 located in the trench 20, with a gate dielectric layer 181 between the gate 18 and the trench 20.

The source region 15 surrounds the trench 20 and contacts the sidewalls of the trench 20.

The well region includes a first layer well region 141, a second layer well region 142, and a third layer well region 143 arranged in sequence in a direction toward the source region 15 of the substrate 10, the bottom of the trench 20 is located between the first layer well region 141 and the third layer well region 143, the third layer well region 143 surrounds the trench 20 and contacts the sidewall of the trench 20, there is a doping region 17 in the epitaxial layer below the trench 20, the first layer well region 141 surrounds the doping region 17 and contacts the doping region 17, there is a partial epitaxial layer 100 between the first layer well region 141 and the third layer well region 143, and the second layer well region 142 is located on both sides of the partial epitaxial layer 100.

On the opposite side of the substrate 10 from the epitaxial layer is a metal drain 19. The source region 15 includes a first region 151 and a second region 152 having opposite doping types, and the first region 151 can be configured to be an n+ type doped region and the second region 152 can be configured to be a p+ type doped region. A metal source 21 is in contact with both the first region 151 and the second region 152. On the surface of the source region 15 is an insulating layer 16, which exposes the metal source 21 and a gate 18. The gate 18 includes a fill dielectric located in the trench 20 and a metal gate located on the surface of the fill dielectric.

In the silicon carbide MOSFET device shown in FIG. 4a, the well region structure includes three layers: a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143. The top third-layer well region 143 is located on both the left and right sides of the trench 20 and contacts the sidewalls of the trench 20. The middle second-layer well region 142 includes two portions located on both the left and right sides of the trench 20 and does not contact the sidewalls of the trench 20. The bottom first-layer well region 141 is located below the trench 20 and does not contact the trench 20.

The distance between the two left and right parts of the second-layer well region 142 and the vertical central axis of the cell structure is greater than the distance between the two left and right parts of the first-layer well region 141 and the vertical central axis of the cell structure. Specifically, the vertical central axis of the cell structure is the central axis of the trench 20, and as shown by the dotted line in FIG. 4a, the first-layer well region 141 is closer to the central axis than the second-layer well region 142. The first-layer well region 141 is closer to the trench sidewall than the second-layer well region 142, which protects the trench corner at the bottom of the trench 20, forms a parasitic JFET, and can suppress high-frequency oscillation and surges. The second-layer well region 142 can suppress surges by connecting the first-layer well region 141 to the source.

The doping region 17 allows a specific JFET structure to be formed on the current path diameter between the source and drain, and the conduction characteristics of the JFET structure can be optimized and adjusted by the pattern design, ion implantation concentration, and pattern contour of the doping region 17 to improve the performance of the MOSFET device.

The technical solution of the present application solves the problems of the shielding of the gate oxide film structure of the SiC trench MOSFET and the deep implantation process of silicon carbide material by cleverly designing the second epitaxial layer 12 and the doping region 17 penetrating the second epitaxial layer 12 in the epitaxial wafer. At the same time, the doping region 17 can also introduce a JFET structure that can be modulated by ion implantation on the current path of the device, automatically adjusting the on-resistance and self-locking protection effect of the device, while keeping the device cell size small.

The silicon carbide MOSFET device shown in Figure 4a has at least the following beneficial effects:

The silicon carbide MOSFET device can introduce a JFET structure into the current path of the cell structure, automatically adjusting the device on-resistance and self-locking protection effect while keeping the device cell size small, and the conduction characteristics of the JFET structure are optimized and adjusted by the pattern design, ion implantation concentration and pattern contour of the doping region 17, and the design and process are flexible and have good manufacturability.

By utilizing an epitaxial wafer with a buried layer (second epitaxial layer 12) and a JFET structure modulated by the injection of the doping region 17, the depletion regions on both sides can be automatically enlarged under a large surge voltage to increase the on-resistance of the JFET structure, which is equivalent to a buffer circuit structure that independently suppresses surge spikes. At the same time, when the surge voltage is too large, the depletion regions on both sides continue to expand and overlap each other, exerting a blocking effect, protecting the gate dielectric layer on the inner trench surface, and playing a certain role in the overvoltage protection of the spike voltage.

The introduction of a JFET structure increases the on-resistance to some extent, but it also provides a switching buffer effect and a self-suppression effect against surge voltage.

The silicon carbide MOSFET device enhances the device's self-limiting immunity to surge voltages and overvoltages, and can avoid damage to the device and reduced reliability caused by the actual time delays of overvoltage and overcurrent protection circuits.

At the same time, it buffers spike jitter during the circuit switching process and reduces switching losses. It can reduce the number of buffer circuits and buffer circuit structures in the circuit design and reduce discrete components, thus reducing costs, reducing the actual module volume, and improving reliability.

As shown in FIG. 4b, FIG. 4b is a schematic diagram of the main current path at the moment when the silicon carbide MOSFET device shown in FIG. 4a is turned on, there is a current path between the source and the drain, the central dotted curve shown in FIG. 4b represents the circuit path, the current passing through the JFET structure formed based on the doping region 17. Due to the rapid change of the current, a high-frequency spike voltage is generated in the circuit, and at the same time, due to the rapid change of the voltage on the current path, the depletion region of the JFET structure (the area between the two dotted curves on the left and right in FIG. 4b) rapidly expands or contracts corresponding to various voltage changes, at this time, the JFET structure becomes equivalent to a parallel structure of a variable resistance R and a junction capacitance C, as shown in FIG. 4c, and FIG. 4c is a schematic diagram of the equivalent parasitic parameters of the silicon carbide MOSFET device shown in FIG. 4b.

Through electrical model simulation of a specific circuit application and device, appropriate thickness d and doping concentration of the second epitaxial layer 12, as well as the pattern design, concentration and pattern contour design of the ion implantation structure of the doping region 17 can be selected, optimized and adjusted to obtain appropriate parasitic parameter values (required variable resistance R and junction capacitance C) to effectively suppress voltage spikes and reduce turn-on losses when actually used in circuit modules with different switching frequencies.

In the silicon carbide MOSFET device shown in FIG. 4a, the breakdown voltage performance at the bottom of the trench gate needs to be further improved, so on this basis, as shown in FIG. 5, FIG. 5 is a structural schematic diagram of another silicon carbide MOSFET device provided by an embodiment of the present application:
An epitaxial wafer including a semiconductor substrate 10 and an epitaxial layer provided on a surface of the substrate;
The epitaxial layer includes a well region, a source region, and a trench gate.

Here, the trench gate includes a trench 20 located in the surface of the epitaxial layer opposite the substrate 10, and a gate 18 located in the trench 20, with a gate dielectric layer 181 between the gate 18 and the trench 20.

The source region 15 surrounds the trench 20 and contacts the sidewalls of the trench 20.

The well region includes a first layer well region 141, a second layer well region 142, and a third layer well region 143, which are arranged in sequence in a direction toward the source region 15 of the substrate 10. The bottom of the trench 20 is located between the first layer well region 141 and the third layer well region 143. The third layer well region 143 surrounds the trench 20 and contacts the sidewall 20 of the trench. A doping region 17 is present in the epitaxial layer below the trench 20. The first layer well region 141 surrounds the doping region 17 and contacts the doping region 17, there is a partial epitaxial layer 100 between the first layer well region 141 and the third layer well region 143, the second layer well region 142 is located on both sides of the partial epitaxial layer 100, there is a masking layer 31 in the partial epitaxial layer 100 to protect the bottom of the trench gate, the masking layer 31 is located under the trench 20, and has the same doping type as the well region of each layer. The doping type of the well region of each layer is the same.

Optionally, the well regions of each layer have the same doping type and concentration, i.e., the doping types and doping concentrations of the first layer well region 141, the second layer well region 142 and the third layer well region 143 are all the same, for example, all p-doped. The masking layer 31 may have the same doping concentration as the well regions of each layer, may be p-doped, or may be higher than the doping concentration of the well regions of each layer, for example, the masking layer 31 may be p+ doped. Obviously, in other aspects, the doping concentrations of the first layer well region 141, the second layer well region 142 and the third layer well region 143 may be different.

In the embodiment shown in FIG. 5, the masking layer 31 is provided under the trench 20 to protect the bottom of the trench gate and improve the breakdown voltage performance of the bottom of the trench gate.

Here, in a direction perpendicular to the substrate 10, the distance from the masking layer 31 to the bottom of the trench 20 is smaller than the distance to the first-layer well region 141 so as to effectively protect the bottom of the trench gate. Optionally, the masking layer 31 is in contact with the bottom of the trench 20, i.e., the distance between the masking layer 31 and the bottom of the trench 20 is 0.

In the embodiment shown in FIG. 5, the vertical projection of the doping region 17 on the substrate 10 lies within the vertical projection of the trench 20 on the substrate 10. The vertical projection of the trench 20 on the substrate 10 lies within the vertical projection of the partial epitaxial layer 100 on the substrate 10, and the two vertical projections have a non-zero spacing, i.e., the spacing between the two portions of the second-layer well region 142 in FIG. 5 and the sidewall of the trench 20 is not zero.

5, the partial epitaxial layer 100 further includes a connection region 32 connecting the masking layer 31 and the first-layer well region 141, the connection region 32 having the same doping type as the well region of each layer. The connection region 32 connects the masking layer 31 and the first-layer well region 141, and achieves better trench bottom protection by cleverly encapsulating the trench gate bottom in an "encapsulation" shape.

By providing the connection region 32, the masking layer 31 can be connected to the third-layer well region 143 via the connection region 32, and further connected to the source region 15, and can be grounded via the source 21. On the one hand, it is possible to avoid the accumulation effect caused by dynamic carrier capture during long-term dynamic switching operation due to the floating potential of the masking layer 31, and to avoid the gradual loss of protection of the bottom of the trench gate by the masking layer 31 due to the accumulation effect caused by dynamic carrier capture. On the other hand, it is possible to avoid the problem of an increase in gate parasitic capacitance caused by the floating potential of the masking layer 31, and to avoid the problem of an increase in switching loss caused by parasitic capacitance.

The doping type of the well region of each layer, the masking layer 31, and the connection region 32 is the same, and the doping concentration of the connection region 32 is higher than the doping concentration of the well region of each layer to reduce the connection resistance between the masking layer 31 and the first layer well region 141. For example, it can be set that the well region of each layer is p-doped and the connection region 32 is p+ doped.

As shown in Figures 6 to 9, Figure 6 is a three-dimensional view of a silicon carbide MOSFET device provided by an embodiment of the present application, Figure 7 is a top view of the spacer well region, trench, doping region and connection region in the silicon carbide MOSFET device shown in Figure 6, Figure 8 is a first cross-sectional view of the silicon carbide MOSFET device shown in Figure 6 in a direction perpendicular to the trench extension, and Figure 9 is a second cross-sectional view of the silicon carbide MOSFET device shown in Figure 6 in a direction perpendicular to the trench extension. Here, the cross section of Figure 8 passes through two opposing connection regions 32 on either side of the doping region 17, and the cross section of Figure 9 passes within the spacing region between two adjacent connection regions 32 in the first direction X.

As shown in FIG. 6, the first-layer well region 141 includes a first portion first-layer well region 141a and a second portion first-layer well region 141b located on both sides of the trench 20, and the first portion first-layer well region 141a is connected to the masking layer 31 via at least one of the connection regions 32, and/or the second portion first-layer well region 141b is connected to the masking layer 31 via at least one of the connection regions 32.

In order to improve connection reliability and stability and reduce connection impedance, as shown in FIG. 6 and FIG. 7, the first-layer well region 141a of the first portion is connected to the masking layer 31 via a plurality of the connection regions 32 arranged in sequence in the first direction X, and/or the first-layer well region 141b of the second portion is connected to the masking layer 31 via a plurality of the connection regions 32 arranged in sequence in the first direction X. Here, the first direction X is parallel to the substrate 10 and parallel to the extension direction of the trench 20.

For one trench 20, at least one doping region 17 may be set under the trench. If there are multiple doping regions 17 under the trench 20, the multiple doping regions 17 are arranged in sequence in the first direction X, and the number of doping regions 17 may be any number as required, including but not limited to the two shown in FIG. 7. In order to ensure the protection effect of the bottom of the trench gate, the masking layer 31 is located under the trench 20 and is set as a monolithic structure extending from one end of the trench 20 to the other end.

As shown in FIG. 6 and FIG. 7, the second-layer well region 142 includes a first portion second-layer well region and a second portion second-layer well region located on both sides of the trench 20, and the first portion second-layer well region and the second portion second-layer well region are each an integrated structure.

10 and 11, FIG. 10 is a three-dimensional view of another silicon carbide MOSFET device provided by an embodiment of the present application, and FIG. 11 is a top view of the spacer well region, trench, doping region, and connection region in the silicon carbide MOSFET device shown in FIG. 10. In this embodiment, the second layer well region 142 includes a first portion second layer well region 142a and a second portion second layer well region 142b located on both sides of the trench 20, respectively, and the first portion second layer well region 142a and the second portion second layer well region 142b each include a plurality of sub-regions 33 arranged in sequence in the first direction X, and between two adjacent sub-regions 33 in the first direction X, there is a current spreading region 34 having an opposite doping type to the sub-regions 33. The partial epitaxial layer 100 includes the current spreading region 34.

Taking the first-layer well region 141 as an example of P-type, if the inverse type of the first-layer well region 141 is N-channel, the current will spread to the boundary of the second-layer well region 142, and the current spreading region 34 between two adjacent sub-regions 33 of the second-layer well region 142 can spread the current, further reducing the resistance and reducing the loss.

In the above embodiment, for the same connection region 32, the connection region 32 extends from the bottom of the trench 20 at least into the first-layer well region 141. At this time, the trench 20 completely blocks the connection region 32 in the direction perpendicular to the substrate 10.

As shown in FIG. 12, FIG. 12 is a structural schematic diagram of yet another silicon carbide MOSFET device provided by an embodiment of the present application, and based on the above embodiment, in the aspect shown in FIG. 12, a part of the connection region 32 extends from the bottom of the trench 20 to at least the first-layer well region 141, and another part extends from the surface of the epitaxial layer along the sidewall of the trench 20 to at least the first-layer well region 141. At this time, the trench 20 partially blocks the connection region 32. This aspect allows the masking layer 31 to better connect to the source region 15 and reduce the connection impedance.

In the embodiment of the present application, the connection region 32 is formed by ion implantation based on the trench 20. If the ion implantation region is located within the trench 20 and does not overlap with the sidewall of the trench 20, the connection region 32 will be located completely under the trench 20. If the ion implantation region is close to one side of the trench 20 and has a predetermined angle of incidence with respect to the sidewall of this side, a structure as shown in FIG. 12 can be formed.

In the present embodiment, the lower end of the connection region 32 extends at least into the first-layer well region 141, but may also penetrate downward through the first-layer well region 141.

Note that the drawings of the embodiments of this application show only one cell structure of a MOSFET device. In an actual product, the MOSFET device may have multiple cell structures. The number of cells and the layout method may be set as needed, and are not particularly limited in the embodiments of this application.

In the silicon carbide MOSFET device, the thickness of the third epitaxial layer 13 does not exceed 1 μm, so that the ion implantation depth of the second-layer well region 142 and the third-layer well region 143 does not exceed 1 μm, and the second-layer well region 142 and the third-layer well region 143 can be formed by ion implantation without causing lattice damage in the third epitaxial layer 13 of silicon carbide material.

In the present embodiment, the distance between the bottom of the trench 20 and the first epitaxial layer 11 is less than 1 μm, so that when trench-based ion implantation is performed to form the doped region 17, the ion implantation depth of the doped region 17 is less than 1 μm, and the doped region 17 can be formed by ion implantation in the second epitaxial layer 12 of silicon carbide material without causing lattice damage. The distance between the doped region 17 and the trench bottom is not zero.

In the drawings of the above embodiment, the width of the trench 20 satisfies the uniformity condition in the direction from the bottom of the trench 20 toward the opening, i.e., the width of the trench is the same or approximately the same in this direction, i.e., the trench 20 is a rectangular trench. A typical second epitaxial layer 12 is an epitaxial layer with a uniform thickness, and the width of the trench is set to satisfy the uniformity condition, making it easier to form a doping region 17 with a uniform width in the direction.

In another embodiment, the width of the trench 20 gradually increases in the direction from the bottom of the trench toward the opening, i.e., the trench can be set to be a V-shaped trench or an inverted trapezoidal trench. In the case of a V-shaped trench, the doping region 17 has a V-shaped structure, and in the case of an inverted trapezoidal trench, if the ion implantation window is larger than the trench bottom, the doping region has an inverted trapezoidal structure as shown in FIG. 11, and if the ion implantation window is not larger than the trench bottom, the doping region has a rectangular structure.

In the present embodiment, the width of the doping region 17 is not greater than the width of the trench so that the trench-based ion implantation can be performed to form the doping region 17 in order to reduce the depth of ion implantation.

The doping concentration of the doping region 17 is higher than the doping concentrations of the first epitaxial layer 11 and the third epitaxial layer 13. For example, the doping region 17 is n+ doped, and the first epitaxial layer 11 and the third epitaxial layer 13 are n- doped.

The substrate 10 is an n+ type substrate, the second epitaxial layer 12 is p- type doped, and the doped region 17 is n- type doped. In the present embodiment, the relationship of the doping concentrations is n+>n>n-, p+>p>p-. n-, n, and n+ are homogeneous dopings, and are all first type dopings. p-, p, and p+ are homogeneous dopings, and are all second type dopings. The first type doping and the second type doping are opposite type dopings.

The silicon carbide MOSFET devices can be NMOS or PMOS, and the doping type of each region can be set as required to form NMOS or PMOS.

Based on the above embodiment, another embodiment of the present application also provides a manufacturing method for fabricating a silicon carbide MOSFET device described in the above embodiment, as shown in Figures 13 to 19, which are process flow diagrams of a manufacturing method for a silicon carbide MOSFET device provided by an embodiment of the present application, and the manufacturing method includes the following steps:

Step S11: As shown in FIG. 13, an epitaxial wafer is provided that includes a semiconductor substrate 10 and an epitaxial layer provided on the surface of the substrate.

Here, the epitaxial wafer is a silicon carbide epitaxial wafer, and the substrate 10 and each epitaxial layer on its surface are made of silicon carbide material.

Step S12: As shown in any one of Figures 5 to 12, a well region, a source region 15, and a trench gate are formed in the epitaxial layer.

wherein the trench gate includes a trench 20 located in a surface of the epitaxial layer opposite the substrate 10, and a gate located in the trench 20, with a gate dielectric layer 181 between the gate and the trench 20;
The source region 15 surrounds the trench 20 and contacts the sidewall of the trench 20,
The well region includes a first layer well region 141, a second layer well region 142, and a third layer well region 143, which are sequentially provided in a direction toward the source region 15 of the substrate 10. The bottom of the trench 20 is located between the first layer well region 141 and the third layer well region 143. The third layer well region 143 surrounds the trench 20 and contacts a sidewall of the trench 20. A doping region 17 is present in the epitaxial layer below the trench 20. The first layer well region 141 surrounds and contacts the doping region 17, a partial epitaxial layer 100 is located between the first layer well region 141 and the third layer well region 143, the second layer well region 142 is located on both sides of the partial epitaxial layer 100, and a masking layer 31 is located within the partial epitaxial layer 100 to protect the bottom of the trench gate, the masking layer 31 is located under the trench 20 and has the same doping type as the well region of each layer.

As shown in FIG. 13, the epitaxial layer includes a first epitaxial layer 11 provided on the surface of the base 10, a second epitaxial layer 12 provided on the surface of the first epitaxial layer 11 opposite the substrate 10, and a third epitaxial layer 13 provided on the surface of the second epitaxial layer 12 opposite the first epitaxial layer 11, and the second epitaxial layer 12 includes a region 140 to be implanted and a first-layer well region 141 surrounding the region 140 to be implanted.

In the MOSFET device, the well region structure includes a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143. The second epitaxial layer 12 includes a region to be implanted and a first-layer well region 141 surrounding the region to be implanted, and the region to be implanted 140 is used to form the doping region 17.

In the manufacturing method described in the embodiment of the present application, the manufacturing method of the epitaxial wafer includes epitaxially forming the first epitaxial layer 11, the second epitaxial layer 12, and the third epitaxial layer 13 in sequence on the surface of the substrate 10, where the first epitaxial layer 11 has the same doping type as the third epitaxial layer 13 and is opposite doped to the second epitaxial layer 12.

The substrate 10 can be set to be a silicon carbide substrate with n+ type doping, the first epitaxial layer 11 and the third epitaxial layer 13 can be set to be silicon carbide epitaxial layers with n- type doping, and the second epitaxial layer 12 can be set to be a silicon carbide epitaxial layer with p-type doping. In this way, the second epitaxial layer 12 with p-type doping is a buried layer, and by skillfully adopting an epitaxial wafer having this buried layer, the trench 20 required for the gate 18 is utilized, ion implantation is performed, and a doping region 17 is formed, thereby solving the difficulty of the shield of the trench gate structure and the implantation process of the silicon carbide material. In addition, the doping region 17 can form a JFET structure that can be modulated in the device current path, and can automatically adjust the device resistance and the self-locking protection effect, while at the same time reducing the device cell size.

In step S12, a well region, a source region 15, and a trench gate are formed in the epitaxial layer, and includes the following steps:

Step S121: As shown in Figures 14 to 16, the source region, the second-layer well region, and the third-layer well region are formed in the surface of the third epitaxial layer opposite the substrate.

In this step, a second-layer well region 142, a third-layer well region 143, and a source region 15 are formed in the third epitaxial layer 13 by ion implantation, the second-layer well region 142 being located between the first-layer well region 141 and the third-layer well region 143, and the source region 15 being located on the opposite side of the third-layer well region 143 to the second-layer well region 142.

Specifically, as shown in FIG. 14, ion implantation is performed based on the mask layer 01 to form a second-layer well region 142 in the third epitaxial layer 13, and the second-layer well region 142 incorporates the non-implanted region including the partial epitaxial layer 100. A necessary non-implanted region is formed based on the patterned mask layer 01. The vertical projection of the trench 20 and the doping region 17 is within this non-implanted region, and is spaced from this non-implanted region in a direction parallel to the epitaxial wafer (i.e., the horizontal direction in FIG. 14). Furthermore, as shown in FIG. 15, a third-layer well region 143 is formed on the second-layer well region 142 by ion implantation again, and the third-layer well region 143 covers the second-layer well region 142 and the non-implanted region it surrounds. Furthermore, as shown in FIG. 16, a source region 15 is formed on the third-layer well region 143 by ion implantation again.

Step S122: As shown in FIG. 17, the trench 20 is formed in the surface of the third epitaxial layer 13 opposite the substrate 10, and the bottom of the trench 20 is located between the second epitaxial layer 12 and the third layer well region 143.

Here, the source region 15 and the third-layer well region 143 are in contact with the sidewall of the trench 20, and when the source region 15 is formed by ion implantation, the ion implantation region covers the region for forming the trench 20, so that after the trench is subsequently formed, the unremoved source region 15 can be directly in contact with the sidewall of the trench 20. Similarly, when the third-layer well region 143 is formed by ion implantation, the ion implantation region covers the region for forming the trench 20, so that after the trench is subsequently formed, the unremoved third-layer well region 143 can be directly in contact with the sidewall of the trench 20.

The second-layer well region 142 is spaced from the sidewall of the trench 20. The size of the non-implanted region surrounded by the second-layer well region 142 is larger than the size of the trench 20, and the vertical projection of the trench 20 is set to be located within the non-implanted region and spaced from the non-implanted region, so that the second-layer well region 142 does not contact the sidewall of the trench 20 and a space is provided between the two.

Step S123: As shown in FIG. 18, the masking layer 31 and the doping region 17 are formed based on the trench.

The doping region 17 and the first epitaxial layer 11 have the same doping type as the third epitaxial layer 13.

Based on the trench 20, the masking layer 31 and the doping region 17 can be formed by ion implantation, so that the masking layer 31 and the doping region 17 can be formed within a large depth of the epitaxial layer, meeting quality requirements. The first-layer well region 141 is an epitaxial layer, and the required first-layer well region 141 can be formed within a large depth of the epitaxial layer without ion implantation. The doping region 17 penetrates the second epitaxial layer 12.

Step S124: As shown in FIG. 19, a connection region 32 is formed based on the trench 20 to connect the masking layer 31 and the first-layer well region 141.

The connection region 32 can be formed by ion implantation. By forming the connection region 32 by ion implantation based on the trench, a connection region 32 that meets quality requirements is formed within a large depth of the epitaxial layer.

Step S125: Form a gate dielectric layer 181 and a gate 18 in the trench 20 to form a silicon carbide MOSFET device as described in the above embodiment.

The gate 18 includes a fill dielectric that fills the trench 20 and a metal gate located on the surface of the fill dielectric. A gate dielectric layer 181 is present on the surface of the trench 20, and after forming the gate dielectric layer 181, the gate 18 is formed in the trench 20. The fill dielectric 181 may be polycrystalline silicon, etc. A doping region 17 is formed before forming the gate dielectric layer 181 in the trench 20.

In an embodiment of the present application, the manufacturing method further includes forming a metal source 21 connected to the source region 15 and forming a metal drain 19 on the surface of the substrate 10 opposite the first epitaxial layer 11. The source region 15 includes a first region 151 and a second region 152 of opposite doping type, and the metal source 21 contacts both the first region 151 and the second region 152. The first region 151 can be set to be n+ doped and the second region 152 can be set to be p+ doped.

As shown in FIG. 20, FIG. 20 is a layout of the trench design and ion implantation area of the doped region of a silicon carbide MOSFET device provided by an embodiment of the present application, where the implantation window of the doped region 17 is located in the trench 20, and the channel characteristics of the JFET structure can be adjusted by the pattern design, ion implantation concentration and pattern contour design of the doped region 17. The implantation window area of the doped region 17 may be equal to or smaller than the area of the trench 20.

In the embodiments of the present application, the silicon carbide MOSFET device has only been described with a single cell structure. Obviously, when fabricating the MOSFET device, multiple cell structures can be fabricated simultaneously based on a wafer-level process, and then the wafer can be divided to form the silicon carbide MOSFET device, and the silicon carbide MOSFET device has multiple cell structures.

Although each embodiment in this specification is described in a progressive or parallel or combination of progressive and parallel manner, each example embodiment focuses on the differences between the other embodiments, and the same similar parts of each embodiment may be referenced from one another.

It should be understood that in the description of this application, the orientations and positions indicated by terms such as "upper", "lower", "top", "bottom", "inner", "outer", etc., are based on the orientations and positions shown in the drawings, are merely for the purpose of simplifying the description and illustration of this application, and do not indicate or imply that the devices or elements referred to have a particular orientation or are constructed and operated in a particular orientation, and therefore cannot be construed as limitations on this application. When one component is considered to be "connected" to another component, there may be a component that is directly connected to or centrally located in the other component at the same time.

It should also be noted that in this specification, relational terms such as first and second are used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that such an actual relationship or sequence exists between these entities or operations. Furthermore, the terms "comprise", "comprise", or any other variation thereof are intended to cover a non-exclusive inclusion, such that an article or device that includes a set of elements includes not only those elements, but also other elements not expressly listed or elements inherent in such article or device. Without further limitation, an element defined by a statement "comprises ..." does not exclude the presence of other identical elements in the article or device that includes the above element. The above description of the disclosed embodiments enables one skilled in the art to realize or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be realized in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not limited to these embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (13)

An epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on a surface of the substrate;
a well region, a source region, and a trench gate disposed within the epitaxial layer,
the trench gate includes a trench located in a surface of the epitaxial layer opposite the substrate, and a gate located in the trench, with a gate dielectric layer between the gate and the trench;
the source region surrounds the trench and contacts a sidewall of the trench;
the well region includes a first layer well region, a second layer well region, and a third layer well region provided in order in a direction toward the source region of the substrate, a bottom of the trench is located between the first layer well region and the third layer well region, the third layer well region surrounds the trench and contacts a sidewall of the trench, a doping region is located in an epitaxial layer below the trench, the first layer well region surrounds the doping region and contacts the doping region, a partial epitaxial layer is located between the first layer well region and the third layer well region, the second layer well region is located on both sides of the partial epitaxial layer, a masking layer is located in the partial epitaxial layer to protect a bottom of the trench gate, the masking layer is located under the trench and has the same doping type as the well region of each layer,
A silicon carbide MOSFET device , wherein the dopant in the doped region has the same polarity as the dopant in the first level well region and has a higher concentration than the dopant in the first level well region . a vertical projection of the doped region on the substrate lies within a vertical projection of the trench on the substrate;
2. The silicon carbide MOSFET device of claim 1, wherein a vertical projection of said trench on said substrate lies within a vertical projection of said partial epitaxial layer on said substrate, and wherein two of said vertical projections have a non-zero spacing. The silicon carbide MOSFET device of claim 1, further comprising a connection region in the partial epitaxial layer connecting the masking layer and the first layer well region, the connection region having the same doping type as the well region of each layer. the first-layer well region includes a first portion of a first-layer well region and a second portion of a first-layer well region located on both sides of the trench,
a first-layer well region of the first portion is connected to the masking layer via a plurality of the connection regions arranged in sequence in a first direction, and/or a first-layer well region of the second portion is connected to the masking layer via a plurality of the connection regions arranged in sequence in a first direction;
4. The silicon carbide MOSFET device of claim 3, wherein said first direction is parallel to said substrate and parallel to an extension direction of said trenches. at least one of the doped regions beneath the trench;
2. The silicon carbide MOSFET device of claim 1 , wherein when there are multiple doped regions, the multiple doped regions are arranged sequentially in a first direction, wherein the first direction is parallel to the substrate and parallel to an extension direction of the trench. The silicon carbide MOSFET device of claim 1, characterized in that the distance from the masking layer to the bottom of the trench in a direction perpendicular to the substrate is less than the distance to the first layer well region. The silicon carbide MOSFET device of claim 6, wherein the masking layer contacts the bottom of the trench. the second-level well region includes a first portion of the second-level well region and a second portion of the second-level well region located on both sides of the trench,
2. The silicon carbide MOSFET device of claim 1, wherein the first portion second level well region and the second portion second level well region are each an integral structure. the second-level well region includes a first portion of the second-level well region and a second portion of the second-level well region located on both sides of the trench;
2. The silicon carbide MOSFET device of claim 1, wherein the second-level well region of the first portion and the second-level well region of the second portion both include a plurality of sub-regions arranged in sequence in a first direction, and between two adjacent sub-regions in the first direction there is a current spreading region having an opposite doping type to that of the sub-regions, and the first direction is parallel to the substrate and parallel to an extension direction of the trench. The silicon carbide MOSFET device of claim 3, characterized in that the doping type of the well regions of each layer, the masking layer and the connection regions is the same, and the doping concentration of the connection regions is higher than the doping concentration of the well regions of each layer. The silicon carbide MOSFET device of claim 3, characterized in that the same connection region extends from the bottom of the trench at least into the first-layer well region, or a portion of the connection region extends from the bottom of the trench at least into the first-layer well region and another portion extends from the surface of the epitaxial layer along the sidewall of the trench at least into the first-layer well region. Providing an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on a surface of the substrate;
forming well regions, source regions and trench gates in the epitaxial layer,
the trench gate includes a trench located in a surface of the epitaxial layer opposite the substrate, and a gate located in the trench, with a gate dielectric layer between the gate and the trench;
the source region surrounds the trench and contacts a sidewall of the trench;
the well region includes a first layer well region, a second layer well region, and a third layer well region provided in order in a direction toward the source region of the substrate, a bottom of the trench is located between the first layer well region and the third layer well region, the third layer well region surrounds the trench and contacts a sidewall of the trench, a doping region is located in an epitaxial layer below the trench, the first layer well region surrounds the doping region and contacts the doping region, a partial epitaxial layer is located between the first layer well region and the third layer well region, the second layer well region is located on both sides of the partial epitaxial layer, a masking layer is located in the partial epitaxial layer to protect a bottom of the trench gate, the masking layer is located under the trench and has the same doping type as the well region of each layer,
The method of manufacturing , wherein the dopant in the doped region has the same polarity as the dopant in the first-level well region and has a higher concentration than the dopant in the first-level well region . the epitaxial layer includes a first epitaxial layer provided on a surface of the substrate, a second epitaxial layer provided on a surface of the first epitaxial layer opposite to the substrate, and a third epitaxial layer provided on a surface of the second epitaxial layer opposite to the first epitaxial layer, the second epitaxial layer having a region to be implanted and a first-layer well region surrounding the region to be implanted;
Forming a well region, a source region, and a trench gate in the epitaxial layer includes:
forming the source region, the second-level well region, and the third-level well region in a surface of the third epitaxial layer opposite the substrate;
forming the trench in a surface of the third epitaxial layer opposite the substrate;
forming the masking layer and the doping region based on the trench;
forming a connection region connecting the masking layer and the first-level well region based on the trench;
and forming a gate dielectric layer and a gate in the trench.

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