JP7701249B2 - Variable capacitance element and its manufacturing method - Google Patents

Description

The present invention relates to a variable capacitance element and a manufacturing method thereof.

Variable capacitance elements are used in high-frequency filters, TV tuners, and voltage-controlled variable oscillators (VCOs) such as VCXOs (Voltage Controlled Xtal Oscillators) that use a quartz crystal as a resonator.

As a variable capacitance element, for example, a variable capacitance diode using a pn junction, as described in Patent Documents 1 and 2, is known. The variable capacitance element disclosed in Patent Document 1 has a structure in which a ring-shaped contact layer of a second conductivity type is formed around a diffusion layer of a first conductivity type, and the units are arranged in an array.

The variable capacitance element disclosed in Patent Document 2 includes a first conductivity type impurity diffusion region formed on the surface of a semiconductor substrate, a second conductivity type impurity diffusion region formed on the surface of the semiconductor substrate so as to overlap the first conductivity type impurity diffusion region, a first electrode formed on the surface of the second conductivity type impurity diffusion region and made of aluminum silicon with a silicon content of 3 wt% or more and 10 wt% or less, and a second electrode formed on the back surface of the semiconductor substrate.

Patent document 3 discloses a method for manufacturing a variable capacitance element, which includes the steps of forming a groove in a variable capacitance element formation region on a semiconductor substrate of a first conductivity type having a low impurity concentration, forming a semiconductor region of the first conductivity type having a medium impurity concentration on the inner wall of the groove, embedding a semiconductor material of a second conductivity type having a high impurity concentration inside the groove, and performing a heat treatment to activate the semiconductor region of the first conductivity type having a medium impurity concentration of the semiconductor substrate.

JP 2005-183813 A JP 2002-343980 A JP 2005-294714 A

Variable capacitance elements such as those described in Patent Documents 1 to 3 have a first region located on the surface side of a semiconductor substrate, in which the impurity concentration increases with increasing distance from the surface of the semiconductor substrate in the stacking direction, and a second region located below the first region so as to be adjacent to the first region, in which the impurity concentration of the semiconductor substrate decreases. In a variable capacitance element having such an impurity concentration profile, when ions are implanted along the crystal axis of the semiconductor substrate, ions are implanted deep into the semiconductor crystal due to channeling, resulting in a so-called "flared" profile in which the impurity concentration decreases gradually in the depth direction, making it difficult to obtain an abrupt junction profile with a steep impurity concentration gradient. As a result, it has been difficult to obtain a variable capacitance element with a high capacitance variable ratio and a high linearity of the capacitance variable ratio with respect to the magnitude of the applied voltage.

The present invention was made in consideration of the above circumstances, and aims to provide a variable capacitance element that has a high capacitance variable ratio and a high linearity of the capacitance variable ratio with respect to the magnitude of the applied voltage.

(1) A variable capacitance element according to a first aspect of the present invention comprises:
A semiconductor substrate and a cap layer provided on a main surface of the semiconductor substrate,
the semiconductor substrate has a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type disposed between the first semiconductor layer and the cap layer;
the cap layer includes a conductive layer and an insulating layer located between the conductive layer and the second semiconductor layer;
The impurity concentration of the second semiconductor layer decreases with increasing distance from the insulating layer in the stacking direction.

(2) In the variable capacitance element according to the above aspect, the impurity concentration of the second semiconductor layer may have a concentration gradient of −5 {log ₁₀ (atoms·cm ⁻³ )/μm} or less.

(3) In the variable capacitance element according to the above aspect, the semiconductor substrate may have a minimum value of the impurity concentration at the interface between the first semiconductor layer and the second semiconductor layer in the stacking direction.

(4) In the variable capacitance element according to the above aspect, the thickness of the cap layer may be 50 nm or more.

(5) In the variable capacitance element according to the above aspect, the semiconductor substrate may be made of silicon containing an impurity element, the insulating layer may be made of silicon dioxide, and the conductive layer may be made of polycrystalline silicon.

(6) A method for manufacturing a variable capacitance element according to a second aspect of the present invention includes a first step of forming an insulating layer on a main surface of a semiconductor substrate having a semiconductor region of a first conductivity type, a second step of forming a conductor layer on the main surface of the insulating layer and providing a cap layer having the insulating layer and the conductor layer on the main surface of the semiconductor substrate, and a third step of implanting ions into the semiconductor substrate from the conductor layer side of the cap layer through the conductor layer and the insulating layer to form a second semiconductor layer of the first conductivity type in which the impurity concentration decreases with increasing distance from the insulating layer in the stacking direction in a region of the semiconductor region that contacts the insulating layer, and forming a first semiconductor layer of the first conductivity type in the remaining semiconductor region.

(7) In the method for manufacturing a variable capacitance element according to the above aspect, in the first and second steps, the insulating layer and the conductive layer may be formed so that the thickness of the cap layer is 50 nm or more.

(8) In the method for manufacturing a variable capacitance element according to the above aspect, in the first step and the second step, a cap layer made of the insulating layer and the conductive layer may be formed in a position overlapping with the region in which the second semiconductor layer is to be formed.

(9) In the method for manufacturing a variable capacitance element according to the above aspect, in the third step, ions may be implanted into the semiconductor substrate to form the second semiconductor layer having the same shape as the conductive layer when viewed in a plan view from the stacking direction.

The present invention provides a variable capacitance element with a highly linear capacitance ratio versus the variable ratio and the magnitude of the applied voltage.

1 is a schematic cross-sectional view of a variable capacitance element according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of the laminated structure in FIG. 5A to 5C are diagrams illustrating a method for manufacturing a variable capacitance element according to an embodiment of the present invention. 1A to 1C are diagrams for explaining a method for manufacturing a variable capacitance element. 1A to 1C are diagrams for explaining a method for manufacturing a variable capacitance element. 1A to 1C are diagrams for explaining a method for manufacturing a variable capacitance element. 1A to 1C are diagrams for explaining a method for manufacturing a variable capacitance element. 1 is a circuit diagram of a voltage-controlled crystal oscillator including a variable capacitance element according to an embodiment of the present invention. 1 is a semi-logarithmic graph showing impurity concentration profiles in a stacking direction of semiconductor substrates having stacked structures according to Example 1 and Comparative Example 1.

Below, an example of an embodiment of the present invention will be described in detail with reference to the drawings. Note that the drawings used in the following description may show enlarged characteristic parts for the sake of convenience in order to make the features of the present invention easier to understand. For this reason, the dimensional ratios of each component may differ from the actual ones.

[Variable capacitance element]
First Embodiment
FIG. 1 is a diagram showing a schematic cross-sectional structure of a MOS variable capacitance element 100 according to the present embodiment.
1, the variable capacitance element 100 includes a semiconductor substrate 20 and a cap layer 10 provided on a major surface S of the semiconductor substrate. The semiconductor substrate 20 includes a first semiconductor layer 22 of a first conductivity type and a second semiconductor layer 23 of the first conductivity type disposed between the first semiconductor layer 22 and the cap layer 10. The cap layer 10 includes a conductor layer 12 and an insulator layer 11 located between the conductor layer 12 and the second semiconductor layer 23. The impurity concentration of the second semiconductor layer 23 decreases with increasing distance from the insulator layer 11 in the stacking direction. Hereinafter, a case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

The semiconductor substrate 20 of the variable capacitance element 100 is made of, for example, silicon containing an impurity element. The semiconductor substrate 20 has a first semiconductor layer (well) 22 overlapping a base substrate 21, a second semiconductor layer 23, a low concentration layer 24 provided above the base substrate 21 and on the outer side of the second semiconductor layer in the in-plane direction, diffusion layers 25a, 25b provided on the outer side of the low concentration layer 24 in the in-plane direction, and an epitaxial region 26 provided above the base substrate 21 and on the outer side of the diffusion layer 25b in the in-plane direction.

The low concentration layers 24a, 24b and the epitaxial region 26 are not limited to being in direct contact with the base substrate 21, but may be spaced apart from the base substrate 21, for example, provided on the base substrate 21 via one or more other layers. Note that "upward" does not necessarily mean the direction along the direction of gravity. In FIG. 1, the region enclosed by the dashed line is referred to as the stacked structure 50.

The base substrate 21 is, for example, a p-type semiconductor substrate containing a low concentration of impurity elements.
The low concentration layer 24 is, for example, a p-type region having a lower impurity concentration than the impurity concentration at the interface between the first semiconductor layer 22 and the second semiconductor layer 23. The low concentration layer 24 is formed, for example, along the main surface S of the semiconductor substrate 20. The distance between the main surface S20 of the semiconductor substrate ₂₀ and the end surface _S24 in the stacking direction of the low concentration layer 24 is, for example, equal to or greater than the distance between the main surface _S20 of the semiconductor substrate ₂₀ and the end surface S23 in the stacking direction of the second semiconductor layer 23. By including the low concentration layer 24 in the variable capacitance element 100, the circuit structure from the gate terminal a to the terminal wiring b can be controlled to partially include a stacking direction component of the semiconductor substrate 20.

The diffusion layers 25a, 25b include, for example, a p-type impurity element. The diffusion layers 25a, 25b include, for example, first diffusion layers 25aa, 25ba including a higher concentration of the impurity element than the first semiconductor layer 22, and second diffusion layers 25ab, 25bb including a higher concentration of the impurity element than the first diffusion layers 25aa, 25ba. The distance between the main surface _S20 of the semiconductor substrate 20 and the stacking direction end faces _S25b of the second diffusion layers 25ab, 25bb is greater than the distance between the main surface S20 of the semiconductor substrate ₂₀ and the stacking direction end faces _S24 of the low concentration layers 24, for example. The distance between the principal surface S20 of the semiconductor substrate ₂₀ and the end faces _S25a of the first diffusion layers 25aa, 25ba in the stacking direction is, for example, larger than the distance between the principal surface S20 of the semiconductor substrate ₂₀ and the end faces _S25b of the second diffusion layers 25ab, 25bb in the stacking direction.

Conductor wiring such as polysilicon wiring or aluminum wiring is connected to the diffusion layers 25a and 25b (terminal wiring b in the figure).

The epitaxial region 26 is, for example, an n-type epitaxial region (or well region) containing a low concentration of impurity elements. Elements such as p-type diffused resistors and PMOS transistors are formed in the epitaxial region 26. A sidewall spacer 13 containing, for example, silicon dioxide as a main component is provided on the insulating layer 11 and next to the conductive layer 12.

<Laminated structure>
Fig. 2 is an enlarged cross-sectional view of a laminated structure 50 in the variable capacitance element 100 of Fig. 1. The laminated structure 50 includes, for example, a semiconductor substrate 20 formed by laminating a base substrate 21, a first semiconductor layer 22, and a second semiconductor layer 23 in this order, and a cap layer 10 formed by laminating an insulating layer 11 and a conductor layer 12 in this order on the semiconductor substrate 20.

The semiconductor substrate 20 is made of, for example, silicon containing impurity elements. The insulating layer 11 and the conductive layer 12 are made of, for example, an oxide and a polycrystalline semiconductor, respectively. As a specific example, the insulating layer 11 is made of silicon dioxide, and the conductive layer 12 is made of polycrystalline silicon. In this way, the stacked structure 50 has a MOS structure.

The base substrate 21, the first semiconductor layer 22, and the second semiconductor layer 23 are semiconductor regions containing, for example, a p-type impurity element. For example, the first semiconductor layer 22 is a p ^- layer, and the second semiconductor layer 23 is a p-layer, and the impurity concentration of the second semiconductor layer 23 is, for example, higher than the impurity concentration of the first semiconductor layer 22.

The impurity concentration of the second semiconductor layer 23 decreases with increasing distance from the insulating layer 11 in the stacking direction, as shown by the dot shading in FIG. 2. The impurity concentration of the second semiconductor layer 23 is, for example, 1.0×10 ¹⁷ to 5.0×10 ¹⁸ (pieces/cm ³ ), and preferably 4.0×10 ¹⁷ to 2.0×10 ¹⁸ (pieces/cm ³ ). The impurity concentration of the second semiconductor layer 23 has a concentration gradient of, for example, −5 {log ₁₀ (pieces·cm ⁻³ )/μm} or less, and a concentration gradient of, for example, −10 {log ₁₀ (pieces·cm ⁻³ )/μm} or more. The concentration gradient of the impurity concentration of the second semiconductor layer 23 can be obtained by dividing the difference in impurity concentration between the main surface S of the semiconductor substrate 20 and the end surface S ₂₃ in the stacking direction of the second semiconductor layer 23 by the difference in depth of the second semiconductor layer 23. That is, the concentration gradient of the impurity concentration of the second semiconductor layer 23 can be obtained by calculating [{log ₁₀ (impurity concentration at the stacking direction end surface S ₂₃ of the second semiconductor layer 23) - log ₁₀ (impurity concentration at the main surface S of the semiconductor substrate 20)} / (difference in depth of the second semiconductor layer 23)].

The position of the stacking direction end face _S23 of the second semiconductor layer 23 can be determined based on, for example, the impurity concentration profile of the semiconductor substrate 20. Specifically, as described above, the impurity concentration of the second semiconductor layer 23 decreases with increasing distance from the main surface of the semiconductor substrate 20, and as described later, the impurity concentration of the region of the first semiconductor layer 22 that contacts the second semiconductor layer 23 increases with increasing distance from the main surface S of the semiconductor substrate 20, so that the impurity concentration of the stacking direction end face _S23 is the minimum value of the impurity concentration profile in the stacking direction. In this way, the semiconductor substrate 20 has a minimum value of the impurity concentration at the interface between the first semiconductor layer 22 and the second semiconductor layer 23 in the stacking direction, for example. Therefore, it can be determined that the minimum value of the impurity concentration closest to the main surface S of the semiconductor substrate in the stacking direction is the stacking direction end face _S23 of the second semiconductor layer 23, and is also the interface between the second semiconductor layer 23 and the first semiconductor layer 22 in the stacking direction.

As shown by the dot shading in FIG. 2, the first semiconductor layer 22 has, for example, a region R22a that contacts the stacking direction end face _S23 of the second semiconductor layer ₂₃ and whose impurity concentration increases with increasing distance from the stacking direction end face S23, and a region R22b that contacts the region R22a and whose impurity concentration increases with increasing distance from the stacking direction end face. That is, the impurity concentration of the first semiconductor layer 22 is maximum at the interface 22i between these two regions R22a and R22b. The maximum value of the impurity concentration of the first semiconductor layer 22 is preferably smaller than the maximum value of the impurity concentration of the second semiconductor layer 23. In addition, the average impurity concentration in the first semiconductor layer 22 is preferably lower than the average impurity concentration in the second semiconductor layer 23.

The cap layer 10 is composed of, for example, an insulating layer 11 laminated on the second semiconductor layer 23 and a conductive layer 12 laminated on the insulating layer 11.

The cap layer 10 is composed of, for example, an insulating layer 11 laminated on the second semiconductor layer 23 and a conductive layer 12 laminated on the insulating layer 11.

The insulating layer 11 is composed of an insulator such as silicon dioxide. The insulating layer 11 is larger than the second semiconductor layer 23 in a direction intersecting the stacking direction (in-plane direction of the substrate). When viewed in a plan view from the stacking direction, for example, the insulating layer 11 overlaps with the second semiconductor layer 23 and the low concentration layer 24 arranged next to the second semiconductor layer 23.

The conductor layer 12 is made of a conductive material such as polysilicon. When viewed from above in the stacking direction, the conductor layer 12 overlaps with the second semiconductor layer 23 and has, for example, the same shape. The conductor layer 12 contains, for example, an n-type impurity element.

The thickness d ₁₀ of the cap layer 10 is, for example, 50 nm or more. The thickness of the cap layer 10 is, for example, 400 nm or less, and preferably 100 nm to 300 nm.

The thickness d ₁₀ of the cap layer 10 determines the impurity concentration distribution and thickness of the second semiconductor layer 23 together with the magnitude of the acceleration energy during ion implantation. When the thickness d ₁₀ of the cap layer 10 is 50 nm or more, it is easy to obtain the effect of blocking a part of the impurity element in the process (third process) of forming the second semiconductor layer 23 by ion implantation into the semiconductor substrate in the manufacturing process described later, and the impurity concentration of the second semiconductor layer 23 can be made to have a profile that decreases with distance from the insulator layer 11 in the stacking direction. In addition, when the thickness d ₁₀ of the cap layer 10 is large, it is necessary to increase the acceleration energy of the ion implantation in order to form the second semiconductor layer 23. When the thickness d ₁₀ of the cap layer 10 is 400 nm or less, it is possible to easily suppress the occurrence of excessive channeling in the cap layer 10, and it is easy to form the second semiconductor layer 23 having a thickness of about submicrons, which is controlled to have a configuration in which the impurity concentration of the second semiconductor layer 23 is high and decreases with distance from the insulator layer 11.

The thickness _d11 of the insulating layer 11 is, for example, 3 nm to 14 nm, and preferably 5 nm to 8 nm, and the thickness _d12 of the conductive layer 12 is, for example, 50 nm to 400 nm, and preferably 100 nm to 300 nm.

In the variable capacitance element 100, the capacitance between the semiconductor substrate 20 and the conductive layer 12 can be changed by changing the potential difference between the gate terminal a and the terminal wiring b. Specifically, when a positive potential is applied to the gate terminal a and the potential difference between the gate terminal a and the terminal wiring b is increased, a depletion layer is formed near the surface of the semiconductor substrate 20. When the potential of the gate terminal a is increased, the depletion layer expands in the stacking direction, and the capacitance between the semiconductor substrate 20 and the conductive layer 12 decreases.

In addition, in the variable capacitance element 100, when a negative potential is applied to the gate terminal a and the potential difference between the gate terminal a and the terminal wiring b is made sufficiently large, holes gather near the surface of the semiconductor substrate 20, and the variable capacitance element enters an accumulation state. As a result, the capacitance of the variable capacitance element 100 becomes approximately the same as the capacitance of the insulating layer 11, and takes the maximum value.

Therefore, if the impurity concentration of the second semiconductor layer 23 decreases with increasing distance from the insulating layer 11 in the stacking direction, a uniform correlation is established in which the impurity concentration decreases with increasing distance in the depth direction in the second semiconductor layer 23, and an abrupt junction profile or a profile similar thereto can be obtained. As a result, the capacitance variable ratio of the variable capacitance element 100 is high, and the linearity of the profile of the change in the capacitance variable ratio relative to the change in the magnitude of the voltage applied to the conductor layer 12 is high. Furthermore, if the concentration gradient of the impurity concentration of the second semiconductor layer 23 is -5 {log ₁₀ (particles cm ^-3 )/μm} or less, a profile similar to an ideal abrupt junction can be obtained, and the linearity of the profile of the change in the capacitance variable ratio relative to the change in the magnitude of the applied voltage can be further increased.

In the above embodiment, an example is shown in which the semiconductor substrate 20 is made of silicon containing an impurity element, but the semiconductor substrate 20 is not limited to being made of silicon containing an impurity element, and may be made of germanium, selenium, or the like containing an impurity element.

In the above embodiment, the first semiconductor layer 22 has a region R22a in which the impurity concentration increases with increasing distance from the stacking direction end face _S23 and a region R22b in which the impurity concentration decreases with increasing distance from the stacking direction end face _S23 , but the present invention is not limited to this example, and the first semiconductor layer 22 may have a configuration in which the impurity concentration monotonically decreases with increasing distance from the stacking direction end face _S23 , or may have a configuration in which the impurity concentration monotonically decreases. In such a case, the interface between the first semiconductor layer 22 and the second semiconductor layer 23 can be defined by comparing a graph of the impurity concentration profile in the stacking direction before the second semiconductor layer is formed with a graph of the impurity concentration profile in the stacking direction after the second semiconductor layer is formed.

In the above embodiment, the variable capacitance element is described in which the first conductivity type is p-type and the second conductivity type is n-type, but the present invention is not limited thereto, and the first conductivity type may be n-type and the second conductivity type may be p-type. For example, in the above embodiment, the first semiconductor layer 22 is a p ^- layer and the second semiconductor layer 23 is a p-layer, but the first semiconductor layer 22 may be an n ^- layer and the second semiconductor layer an n-layer. Here, the p ^- layer and the n ^- layer indicate that the average impurity concentration is lower than that of the p-layer and the n-layer, respectively. In such a configuration, when the potential of the gate terminal a is lowered, the depletion layer expands and the capacitance between the semiconductor substrate 20 and the conductor layer 12 decreases.

[Manufacturing method of variable capacitance element]
Next, an example of a method for manufacturing the variable capacitance element according to this embodiment will be described. The following mainly describes the process for forming the layered structure 50 of the variable capacitance element 100. In this embodiment, the manufacturing process of the variable capacitance element according to this embodiment shown in FIGS. 3 to 7 will be referred to.

The method for manufacturing a variable capacitance element according to this embodiment includes a first step of forming an insulating layer 11 on a main surface S of a semiconductor substrate 20 having a semiconductor region of a first conductivity type; a second step of forming a conductor layer 12 on the main surface _S11 of the insulating layer 11 and providing a cap layer 10 having the insulating layer 11 and the conductor layer on the main surface S of the semiconductor substrate 20; and a third step of implanting ions into the semiconductor substrate 20 from the conductor layer 12 side of the cap layer 10, via the conductor layer 12 and the insulating layer 11, to form a second semiconductor layer 23 of the first conductivity type in which the impurity concentration decreases with increasing distance from the insulating layer 11 in the stacking direction, in a region of the semiconductor region that is in contact with the insulating layer 11, and forming a first semiconductor layer 22 of the first conductivity type in the remaining semiconductor region.

(preparation process)
When manufacturing the variable capacitance element 100 using a semiconductor substrate that does not have a semiconductor region of the first conductivity type, for example, a first preparation step and a second preparation step are performed as preparation steps before performing the first step. Note that when manufacturing the variable capacitance element 100 using a semiconductor substrate 20 that has a semiconductor region of the first conductivity type, the preparation steps can be omitted.

In the first preparation step, as shown in FIG. 3, for example, a semiconductor region of the second conductivity type is formed in the semiconductor substrate 20. Specifically, for example, an n-type epitaxial region 26 is formed on the main surface S side of the p-type semiconductor substrate 20.

In the second preparation step, as shown in Fig. 4, a semiconductor region of a first conductivity type is formed in a semiconductor substrate. Specifically, ions are implanted into a semiconductor substrate 20 having an n-type epitaxial region 26, for example, to form a well 22' of the first conductivity type up to a region farther from the main surface S than the epitaxial region 26. The well 22' is, for example, a p (p ^- ) type semiconductor region. For example, the well 22' has a region R22a' on the main surface S side of the semiconductor substrate, in which the impurity concentration increases with increasing distance from the main surface S of the semiconductor substrate, and a region R22b in contact with this region, in which the impurity concentration decreases with increasing distance from the main surface S of the semiconductor substrate.

(First step)
In the first step, as shown in Fig. 5, an insulating layer 11 is formed on a main surface S of a semiconductor substrate having a p-type semiconductor region (well 22'). In the first step, the semiconductor substrate is first heat-treated to form a thermal oxide film having a thickness _d11 of, for example, 3 to 14 nm on the main surface S. Next, a photoresist (not shown) or the like is used to cover the region where the insulating layer 11 is to be formed. Next, etching is performed using this photoresist as a mask, and the thermal oxide film in the region other than the masked region is removed, thereby forming the insulating layer 11.

(Second process)
6, a conductor layer 12 is formed on the main surface _S11 of the insulator layer 11, and a cap layer 10 having the insulator layer 11 and the conductor layer 12 is provided on the main surface S of the semiconductor substrate. In the second step, for example, a polycrystalline semiconductor such as polysilicon is formed on the main surface _S11 of the insulator layer 11 and patterned to form an n-type conductor layer 12. The patterning in the second step is performed so that the size of the conductor layer 12 in the in-plane direction is smaller than the size of the insulator layer 11 in the in-plane direction (see FIG. 1).

In this second step, a cap layer 10 having an insulating layer 11 and a conductive layer 12 can be provided. That is, a cap layer 10 consisting of an insulating layer 11 and a conductive layer 12 may be provided, or a cap layer having other layers in addition to the insulating layer 11 and the conductive layer 12 may be provided. In the manufacturing method of the variable capacitance element according to this embodiment, in the first and second steps, a cap layer 10 consisting of an insulating layer 11 and a conductive layer 12 is formed in a position overlapping with a region in which a second semiconductor layer 23, which will be described later, is to be formed.

In the first and second steps, the insulating layer 11 and the conductive layer 12 are preferably formed so that the thickness d ₁₀ of the cap layer 10 is 50 nm or more, and more preferably so that the thickness d ₁₀ is 100 nm or more. In the first and second steps, the insulating layer 11 and the conductive layer 12 are preferably formed so that the thickness d ₁₀ of the cap layer 10 is 400 nm or less, and more preferably so that the thickness d 10 is 300 nm or less.

In addition, a sidewall spacer 13 is formed on the insulating layer 11 in a position aligned with the conductive layer 12, using, for example, silicon dioxide.

(Third step)
7, ions are implanted into the semiconductor substrate 20 from the conductive layer 12 side of the cap layer 10 through the conductive layer 12 and the insulating layer 11 to form a second semiconductor layer 23 of a first conductive type having an impurity concentration decreasing with increasing distance from the insulating layer 11 in the stacking direction in a region of the well 22' that contacts the insulating layer 11, and a first semiconductor layer 22 of a first conductive type is formed in the remaining well 22'. That is, in the third step, the second semiconductor layer 23 is formed in the well 22', and the portion of the well 22' other than the second semiconductor layer 23 becomes the first semiconductor layer 22. The first semiconductor layer 22 is, for example, a p (p) type semiconductor region.

In the third step, for example, ions are implanted into the semiconductor substrate 20 to form a second semiconductor layer 23 having the same shape as the conductive layer 12 when viewed in a plan view from the stacking direction.

In the third step, the second semiconductor layer 23 can be formed by, for example, self-alignment, so no mask is required. The acceleration energy during ion implantation can be, for example, 30 to 70 kEV, depending on the thickness of the cap layer 10 and the depth of the semiconductor region formed as the second semiconductor layer 23. If the acceleration energy is too small, the ions cannot penetrate the cap layer 10 and be implanted into the semiconductor substrate, so it is preferable to use an acceleration energy of a predetermined magnitude or more.

The conductor layer 12 is composed of disordered crystal grains, and when ions are implanted into the semiconductor substrate 20 through the cap layer 10, the implanted ions are more likely to collide with atoms of the conductor layer 12 composed of crystal grains with disordered orientations, and some of the ions are blocked and remain in the cap layer 10. Therefore, by manufacturing the stacked structure 50 by the manufacturing method of this embodiment, channeling is suppressed. Therefore, when ions are directly implanted into the semiconductor substrate without providing a cap layer as in the past, the impurity concentration in the region on the main surface side increases with distance from the main surface, and the impurity concentration in the region away from the main surface decreases with distance from the main surface. In this embodiment, however, the impurity concentration of the second semiconductor layer 23 decreases with distance in the stacking direction. This forms the stacked structure 50.

The manufacturing method for the laminated structure 50 has been described above, but it may further include other steps, and the variable capacitance element 100 as shown in FIG. 1 may be manufactured by the following procedure.

When manufacturing the variable capacitance element 100, for example, a MOS transistor with a p-type LDD structure may be used. In such a case, the p-channel of the MOS transistor with a p-type LDD structure can be used as the low concentration layer 24.

Furthermore, after the above preparation step and before the above first step, ion implantation may be performed with a mask on the portion of the main surface S that overlaps with the region other than the region in which the low concentration layer 24 is to be formed, to form the low concentration layer 24 as a p-type low concentration region.

In addition, in the first step, when removing the thermal oxide film to form the insulating layer 11, the thermal oxide film may be left covering the entire upper surface of the low concentration layer 24.

Also, after the first step and before the second step, ion implantation may be performed on the semiconductor substrate through a mask having a predetermined pattern to form p-type first diffusion layers 25aa, 25ba in the well.

Furthermore, after the second step and before the third step, ion implantation may be further performed on the first diffusion layers 25aa, 25ba to form second diffusion layers 25ab, 25bb having a higher impurity concentration than the first diffusion layers 25aa, 25ba.

Furthermore, after the third step, the terminal wiring b may be connected to the diffusion layer 25b and set to the same potential as the base substrate 21. In this way, the variable capacitance element 100 as shown in FIG. 1 can be manufactured.

As described above, according to the variable capacitance element 100 of the present embodiment, in the MOS structure, the cap layer 10 has a conductor layer 12 and an insulating layer 11 located between the conductor layer 12 and the second semiconductor layer 23, and the impurity concentration of the second semiconductor layer 23 decreases with increasing distance from the main surface S of the semiconductor substrate 20 in the stacking direction, so that a variable capacitance element having a high capacitance variable ratio and a high linearity of the capacitance variable ratio with respect to the depth of the semiconductor substrate 20 can be provided.
Furthermore, when the variable capacitance element 100 has a first semiconductor layer 22 that exhibits an average impurity concentration lower than that of the second semiconductor layer 23 on the side away from the main surface S with respect to the second semiconductor layer 23 in the stacking direction, the impurity concentration of the second semiconductor layer 23 increases during operation due to the rise of p- caused by thermal diffusion from the first semiconductor layer 22. Therefore, the series resistance can be suppressed.

In addition, according to the manufacturing method of the variable capacitance element of this embodiment, in the third step, ions are implanted through the cap layer 10 having the conductive layer 12, so that the implanted ions are likely to collide with atoms of the conductive layer 12, which is composed of disordered crystal grain orientations, and channeling is suppressed. Therefore, the impurity concentration of the second semiconductor layer 23 decreases as it moves away from the insulator layer 11 in the stacking direction, and the concentration gradient of the impurity concentration can be made high. Therefore, a variable capacitance element 100 having a high capacitance variable ratio and a high linearity of the impurity concentration with respect to the depth of the semiconductor substrate 20 can be manufactured by a simple method.

<Application Examples>
8 is an example of a circuit diagram of a voltage-controlled oscillator 200 including the variable capacitance element 100 of the above embodiment. As shown in FIG. 8, the voltage-controlled oscillator 200 includes, for example, an internal circuit 71, a resistor 72, a protection diode 73, a VDD terminal 74, an input terminal 75, a VSS terminal 76, and the variable capacitance element 100.
The voltage of the VDD terminal 74 is, for example, a ground voltage, and the voltage of the VSS terminal is a power supply voltage. In the voltage-controlled oscillator 200, an internal circuit 71 is provided between the VDD terminal 74 and the VSS terminal 76. This internal circuit 71 is configured with a general oscillator circuit such as an inverting amplifier and a feedback resistor. The input terminal 75 is a terminal to which a piezoelectric vibrator such as a crystal is connected to the internal circuit 71 via a resistor 72, and a variable capacitance element 100 is provided between this input terminal 75 and the VSS terminal 76. Although not shown, a control voltage is applied to the input terminal 75 side of the variable capacitance element 100 through another terminal, and the capacitance value is adjusted. Furthermore, a protection diode 73 is provided as a protection element between the VDD terminal 74 and the VSS terminal 76.
In this way, the variable capacitance element 100 of this embodiment can be applied to a voltage controlled oscillator 200 or the like that uses a quartz crystal unit as a resonator.

So far, we have described a variable capacitance element, a manufacturing method thereof, and a voltage-controlled oscillator using a variable capacitance element, but the characteristic configurations of the above embodiments and modifications may be combined.

The following describes examples and comparative examples of the present invention. The present invention is not limited to the following examples.

[Example 1]
As Example 1, a laminated structure as shown in Fig. 2 was fabricated by process simulation. The process simulation was performed using TCAD. In the process simulation, a process was simulated under the following conditions.

In Example 1, first, as a first preparation step, an epitaxial region 26 was formed on a p-type silicon substrate. Next, as a second preparation step, B+ ions were implanted into the main surface of the silicon substrate at a dose of 2.5× ¹⁰ ions/cm ² with an acceleration energy of 120 kEV, to form a p-type semiconductor region on a base substrate 21.

Next, in the first step, the silicon substrate on which the p-type semiconductor region was formed was thermally oxidized at 800°C in air to form an insulating layer with a thickness of 6.5 nm on the main surface of the silicon substrate.

Next, in the second step, a polysilicon layer with a thickness of 200 nm was formed on the main surface of the insulating layer by low-pressure CVD, and a cap layer consisting of the insulating layer and the polysilicon layer was formed.

Next, in the third step, ion implantation was performed on the silicon substrate from the polysilicon layer side of the cap layer through the polysilicon layer and the insulator layer. The ion implantation was performed by implanting B+ ions at a dose of 2.0×10 ¹³ ions/cm ² ions/cm ² with an acceleration energy of 50 kEV. In Example 1, a stacked structure as shown in FIG. 2 was thus produced, in which the base substrate, the first semiconductor layer, the second semiconductor layer, the insulator layer, and the polysilicon layer were provided in this order in the stacking direction.

Next, the impurity concentration distribution in the stacking direction at one position in the in-plane direction of the fabricated stacked structure was determined by simulation based on SIMS (Secondary Ion Mass Spectrometry) profile data.

[Comparative Example 1]
As Comparative Example 1, a laminated structure formed by the following process was simulated by process simulation. In Comparative Example 1, the simulation was performed in the same manner as in Example 1.

A first semiconductor region was formed by implanting B+ ions into the main surface of the silicon substrate at a dose of 1.5× ¹⁰¹³ ions/ ^cm2 with an acceleration energy of 160 kEV.
Next, B ⁺ ions were implanted at a dose of 2.0 × ¹⁰¹³ ions/ ^cm2 with an acceleration energy of 50 kEV into the main surface of the silicon substrate in which the first semiconductor region was formed near the surface layer portion, to produce a stacked structure in which the first semiconductor region was formed on the base substrate and the second semiconductor region was formed on the first semiconductor region.

Next, the impurity concentration in the stacking direction of the fabricated stacked structure was determined in the same manner as in Example 1.

Figure 9 shows a semi-logarithmic graph of the measurement results of the impurity concentration in the stacking direction of the stacked structures of Example 1 and Comparative Example 1. In Figure 9, a depth of 0 μm is the main surface S of the semiconductor substrate. That is, a depth of 0 μm in Comparative Example 1 corresponds to the surface of the second semiconductor region, and a depth of 0 μm in Example 1 corresponds to the surface of the second semiconductor layer.

In Example 1, the second semiconductor layer is located at a depth of 0 μm to 0.14 μm, and the first semiconductor layer is located at a depth of 0.14 μm to approximately 0.6 μm. The second semiconductor layer in Example 1 exhibits an impurity concentration profile in which the impurity concentration decreases with increasing distance from the major surface of the semiconductor substrate. In Example 1, the boundary between the first semiconductor layer and the second semiconductor layer corresponds to the minimum value of the impurity concentration.

The results in Figure 9 confirm that in Example 1, the impurity concentration of the second semiconductor layer located on the main surface side of the semiconductor substrate decreases with increasing distance from the insulating layer in the stacking direction.

On the other hand, in the method of directly implanting ions into a semiconductor substrate as in Comparative Example 1, it was confirmed that the impurity concentration profile is such that in the region on the main surface side, the impurity concentration increases with increasing distance from the main surface of the semiconductor substrate, and in the region away from the main surface, the impurity concentration decreases with increasing distance from the main surface of the semiconductor substrate.

Furthermore, in Comparative Example 1, the concentration gradient of the impurity concentration was relatively steep at a depth of 0.2 μm to 0.35 μm, and the concentration gradient of the impurity concentration in this region was -2.65 {log ₁₀ (particles·cm ^-3 )/μm}. In contrast, the concentration gradient of the impurity concentration in the second semiconductor layer (depth 0 μm to 0.14 μm) in Example 1 was -9.66 {log ₁₀ (particles·cm ^-3 )/μm}. Thus, by comparing Example 1 and Comparative Example 1, it was confirmed that the concentration gradient of the impurity concentration in the second semiconductor layer in Example 1 was approximately 3.6 times steeper than the region in Comparative Example 1 where the concentration gradient of the impurity concentration was relatively steep.

10 Cap layer, 11 Insulator layer, 12 Conductor layer, 20 Semiconductor substrate, 21 Base substrate, 22 First semiconductor layer, 23 Second semiconductor layer,
24 low concentration layer, 25a and 25b diffusion layers, 25aa and 25ba first diffusion layers, 25ab and 25bb second diffusion layers, 26 epitaxial region

Claims (9)

A semiconductor substrate and a cap layer provided on a main surface of the semiconductor substrate,
the semiconductor substrate has a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type disposed between the first semiconductor layer and the cap layer;
the cap layer includes a conductive layer and an insulating layer located between the conductive layer and the second semiconductor layer;
A variable capacitance element, wherein the impurity concentration of the second semiconductor layer decreases with increasing distance from the insulating layer in a stacking direction. 2. The variable capacitance element according to claim 1, wherein the impurity concentration of the second semiconductor layer has a concentration gradient of −5 {log ₁₀ (atoms·cm ⁻³ )/μm} or less. The variable capacitance element according to claim 1 or 2, wherein the semiconductor substrate has a minimum impurity concentration at the interface between the first semiconductor layer and the second semiconductor layer in the stacking direction. The variable capacitance element according to any one of claims 1 to 3, wherein the thickness of the cap layer is 50 nm or more. the semiconductor substrate is made of silicon containing an impurity element,
The insulating layer is made of silicon dioxide,
5. The variable capacitance element according to claim 1, wherein the conductive layer is made of polycrystalline silicon. A first step of forming an insulating layer on a main surface of a semiconductor substrate having a semiconductor region of a first conductivity type;
a second step of forming a conductive layer on a main surface of the insulating layer and providing a cap layer having the insulating layer and the conductive layer on a main surface of the semiconductor substrate;
a third step of implanting ions into the semiconductor substrate from the conductor layer side of the cap layer, through the conductor layer and the insulating layer, to form a second semiconductor layer of a first conductivity type in a region of the semiconductor region that contacts the insulating layer, the second semiconductor layer having an impurity concentration that decreases with increasing distance from the insulating layer in a stacking direction, and a third step of forming a first semiconductor layer of the first conductivity type in the remaining semiconductor region. The method for manufacturing a variable capacitance element according to claim 6, wherein in the first and second steps, the insulating layer and the conductive layer are formed so that the thickness of the cap layer is 50 nm or more. The method for manufacturing a variable capacitance element according to claim 6 or 7, wherein in the first and second steps, a cap layer made of the insulating layer and the conductive layer is formed in a position overlapping a region in which the second semiconductor layer is to be formed. The method for manufacturing a variable capacitance element according to any one of claims 6 to 8, wherein in the third step, ions are implanted into the semiconductor substrate to form the second semiconductor layer having the same shape as the conductor layer when viewed in a plan view from the stacking direction.

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