JP7701944B2 - Targets and algorithms for measuring overlay by modeling backscattered electrons on overlapping structures. - Google Patents

Description

This disclosure relates generally to semiconductor targets and metrology.

As the semiconductor manufacturing industry evolves, there is an increasing demand for yield management, especially metrology and inspection systems. As critical dimensions continue to shrink, the industry is under pressure to achieve higher yields and higher value production in shorter times. Reducing the total time between detecting a yield problem and correcting it is becoming increasingly critical to the return on investment for semiconductor manufacturers.

Inspection processes are used at various steps during semiconductor manufacturing to detect wafer-side defects that can help increase yields and therefore profits in the manufacturing process. Inspection has long been an important part of the manufacture of semiconductor devices, such as integrated circuits (ICs). However, as the dimensions of semiconductor devices shrink, inspection has become more important than ever for the successful manufacture of acceptable semiconductor devices, since even smaller defects can lead to device failure. For example, as the dimensions of semiconductor devices shrink, detection of smaller sized defects becomes necessary, since even relatively small defects can cause undesired deviations in those semiconductor devices.

Standard marks used in electron beam overlay metrology have separate patterns so that the signals from different layers can be separated in a non-overlapping manner, such as the side-by-side mark shown in Figure 1 and the interleaved mark shown in Figure 2. In these cases, simple algorithms can be used to extract the position of each layer.

3 and 4 depict a multi-layer pattern 1 with a top layer 2 and a buried layer 3. When multiple layers are present, it may be impossible to distinguish whether a secondary electron signal corresponds to secondary electrons 4 from the top layer 2, which may be referred to as SE, or secondary electrons 5 from the buried layer 3, which may be referred to as SE2. As depicted in FIG. 3, SE2 may be associated with secondary electrons 5 resulting from backscattered electrons scattering at the buried layer 3. Similarly, as depicted in FIG. 4, it may be impossible to distinguish whether a backscattered electron (BSE) signal 6 or 7 corresponds to the top layer 2 or the buried layer 3.

There may be difficulties in measuring spatially separated targets. One such difficulty may be the large blank areas, which increase costs and are not compatible with fine electronic circuit fabrication. Another difficulty may be that imaging an asymmetric field of view with an electron beam may result in beam alignment distortions due to non-uniform charging of the surface. In addition, the separated areas may not adequately represent the device, e.g. with its stacked layers.

One conventional approach to circumvent these difficulties (i.e., to measure stack layers when spatial separation of the signals from each layer is not possible) is to model the electron beam-stack interaction. However, full modeling requires knowledge of the design, process steps, and tool-material interactions. This type of approach is performed using optical metrology, e.g., optical critical dimension (OCD) applications. There is no accurate and fast metrology method for electron beam overlay metrology.

Another conventional approach is to construct a dedicated grid-over-grid target with a specified shift, which can incorporate algorithms that use differential signals. Such targets are not compatible with in-line production control, as the signal-to-noise ratio (SNR) is orders of magnitude lower than spatially separated features, requiring longer measurement times.

U.S. Pat. No. 7,274,814 U.S. Pat. No. 7,068,833 US Patent Application Publication No. 2014/0060148

Therefore, improved overlay targets and methods for measuring them are needed.

In one embodiment, the overlay target may include a grating over grating structure, a calibration scan location, and an overlay scan location.

In another embodiment, a method may include capturing an overlay target with an electron beam output capture subsystem to form a captured image and using the captured image to measure overlay of a grating-over-grating structure. The overlay target may include a grating-over-grating structure, a calibration scan location, and an overlay scan location. Using the captured image to measure overlay of the grating-over-grating structure may include decomposing and extracting the overlay from the captured image.

In one example, a non-transitory computer readable storage medium may include one or more programs for performing method steps, such as capturing an overlay target with an electron beam output capture subsystem, forming a captured image, and using the captured image to measure overlay of a grid-over-grid structure, which may further include decomposing and extracting the overlay from the captured image.

In one example, a system can include a stage, an electron beam power capture subsystem, and a processor in electronic communication with the electron beam power capture subsystem. The stage can be configured to hold a sample having an overlay target. The overlay target can include a grating-over-grating structure, a calibration scan location, and an overlay scan location. The processor can be configured to measure an overlay of the grating-over-grating structure using the captured images. The processor can be further configured to measure an overlay of the grating-over-grating structure using the captured images by decomposing and extracting the overlay from the captured images.

The grating-over-grating structure may include a lower grating structure and an upper grating structure. The lower grating structure may be disposed on the sample. The sample may be on a stage. The upper grating structure may be disposed on the lower grating structure. Both the upper grating structure and the lower grating structure may be part of the sample, such as a semiconductor wafer or other type of sample. The calibration scan location may be where the lower grating structure is present but the upper grating structure is not. According to certain embodiments, the calibration scan location may consist essentially of the lower grating structure. The overlay scan location may be where the upper grating structure and the lower grating structure are present.

The lattice-over-lattice structure may have blank areas. The blank areas may be areas where there is neither a lower lattice structure nor an upper lattice structure.

During the decomposition and extraction, an extracted signal may be extracted from a single layer. The method may further include improving the signal-to-noise ratio of the extracted signal. During the improvement, a designed stance filter may be applied to the extracted signal. During the decomposition and extraction, the scattering of the extracted signal may be decomposed.

During the scattering decomposition, a backscattered electron profile may be applied to the extracted signal to determine a transfer function for the extracted signal, and a model of the scattering may be generated having that transfer function.

The parameters of the model may be optimized using the local asymmetry or center of symmetry of the secondary electron signal. The parameters of the model may be optimized by aligning the calibration scan location to a second calibration scan location where the backscattered electron-secondary electron interaction for a particular layer can be found.

For a more complete understanding of the nature and purpose of this disclosure, please refer to the attached drawings in conjunction with the detailed description below.

FIG. 1 illustrates a conventional target design. FIG. 1 illustrates a conventional target design. FIG. 1 illustrates a conventional target design. FIG. 1 illustrates a conventional target design. FIG. 1 illustrates a target according to an embodiment of the present disclosure. FIG. 1 illustrates a target according to an embodiment of the present disclosure. FIG. 1 illustrates a target according to an embodiment of the present disclosure. FIG. 1 illustrates a method according to an embodiment of the present disclosure. FIG. 1 illustrates a graphical representation of the signal contamination cleaning steps. FIG. 1 illustrates a graphical representation of the signal contamination cleaning steps. FIG. 1 illustrates a graphical representation of the signal contamination cleaning steps. FIG. 1 illustrates a graphical representation of the signal contamination cleaning steps. FIG. 1 illustrates a graphical representation of the signal contamination cleaning steps. FIG. 1 illustrates a graphical representation of the signal contamination cleaning steps. FIG. 1 illustrates a system according to an embodiment of the present disclosure.

Although certain embodiments are described of the claimed subject matter, other embodiments are within the scope of the disclosure, including embodiments that do not provide all of the benefits and features described herein. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is to be determined solely by reference to the appended claims.

In embodiments, improvements can be made to overlay metrology (i.e., misregistration metrology) using electron beam (e-beam) metrology tools, which may include critical dimension scanning electron microscopy (CD-SEM) tools, defect/defect review tools, inspection tools, and the like. By applying specialized targets and algorithms to complex semiconductor stacks, accuracy errors due to mixing of signals from multiple layers can be overcome.

In electron beam metrology, an image can be constructed by scanning a focused electron beam over a target (e.g. using a scanning electron microscope (SEM)). Two types of electrons can be captured from each scan point using one or more detectors to generate the image: backscattered electrons (BSE) and secondary electrons (SE). When constructing an image from a multi-layer structure, such as those used for misregistration or overlay metrology, the two sets of electrons can occur in any layer touched by the beam.

According to one example, the targets of the embodiments can be optimized for metrology performance, expressed as total measurement uncertainty (TMU) and inaccuracy due to target-to-device bias. Even when the targets are optimized for short measurement times and low TMU, overlay measurements can vary from one semiconductor device to another. This bias can be referred to as target inaccuracy or non-zero overlay (NZO). To overcome this bias, the targets of the embodiments can have features similar to the devices (e.g., stacked layers, small pitch).

The challenges posed by device-like targets include, for example, overcoming signal contamination without spatial separation. It would be impractical to analytically model such complex interactions as is done for optical interactions. The claimed embodiments of this application overcome these challenges.

According to one example algorithm, the SE-SE interactions can be defined as described by Equation 1.
SE(x)= _SE1 (x)+ _SE2 (x+ _x2 ) [1]

In Equation 1, x represents the position along the target, _x2 is the offset (e.g., overlay) of the second grating, and SE represents the detected secondary electrons from the top layer ( _SE1 ) and the bottom layer ( _SE2 ). If the position of the second layer can be measured with sufficient accuracy, it can serve as an input, e.g., if a clear enough signal is captured so that the noise can be overcome and the position of the grating can be measured. However, the position of the second layer does not have to be an input, and can be calculated according to the embodiments of the present disclosure. For example, the position of the second layer can be calculated when the position of one grating is known or when the position of one grating is unknown.

According to embodiments herein, signal contamination can be overcome by modeling the secondary electron signal using knowledge of secondary electrons ( _SE2 ) and backscattered electrons ( _BSE2 ) from buried layers. α, γ and the function f are the scattering coefficients when the signal is transferred from layer to layer using electrons.
SE(x)=SE ₁ (x)+αBSE ₂ (x+x ₂ ) [2]
SE(x)= _SE1 (x)+ _γSE1 (x) _BSE2 (x+ _x2 ) [3]
SE (x) = SE ₁ (x) + f (SE ₁ (x), BSE (x + x ₂ )) [4]

However, the interactions expressed in Equations 2-4 are more complex, have more variables, and are more sensitive, all rooted in the ability to utilize dedicated areas within a target to unambiguously measure both _{BSE2 and SE2 profiles} .

To be able to solve this set of equations, the target is considered to have or consist of at least one area where one of the two layers is not contaminated. Examples of such target designs can be found in Figures 5-7.

In one example, the overlay target may include a grating over grating structure, a calibration scan location, and an overlay scan location.

5 is an exemplary embodiment of such an overlay target 10. The overlay target 10 may include a lower grating structure 12, an upper grating structure 11, and an area of interest 13, which may be used to capture both the position and signal profile of the lower grating structure 12, which may be used as SE ₂ or BSE ₂ in Equation 1. For target designs capturing device effects and process steps, pitches may range from fine pitches of 40 nm to coarse pitches of 200 and 400 nm. Total target size may range from 1 μm to several μm (e.g., 2-4 μm).

Figure 6 is an exemplary embodiment of such an overlay target 20. The overlay target 20 may include a lower grating structure 22, an upper grating structure 21, and a region of interest 23. The pitch and target size in the embodiment of Figure 6 may be similar to that of Figure 5. The calibration area may be 200 nm or less.

Figure 7 is an exemplary embodiment of such an overlay target 30. The overlay target 30 may include a lower grating structure 32, an upper grating structure 31, and a region of interest 33. The pitch and target size in the embodiment of Figure 7 may be similar to that of Figure 5. The calibration area may be 200 nm or less.

In some embodiments, a transparent resist can be used and a BSE channel can be used as a seed for the method. When a transparent resist is used, the overlay target can have or not have blank areas. One example with a transparent resist is one in which the overlay target has two blank areas, such as the two rectangles in FIG. 5 surrounding the region of interest 13.

The grating-over-grating structure may have a lower grating structure and an upper grating structure. The lower grating structure may be disposed on the sample. The sample may be on a stage. The upper grating structure may be disposed on the lower grating structure. An example of a calibration scan location is where there is a lower grating structure but no upper grating structure. In certain embodiments, the calibration scan location may consist essentially of only the lower grating structure. An example of an overlay scan location is where there is a lower grating structure and an upper grating structure.

The grid-over-grid structure can have blank areas. An example of a blank area is where there is no lower grid structure or upper grid structure. The blank area can then be used for calibration. In one example, the blank area can be a location where a single grid signature is captured that is useful for solving the equations disclosed herein.

In one example, as shown in FIG. 8, a method 100 can include capturing an overlay target with an electron beam output capture subsystem at 101, forming a captured image at 102, and using the captured image at 103 to measure overlay of the grating-over-grating structure. The overlay target can include a grating-over-grating structure, a calibration scan location, and an overlay scan location. When using the captured image at 103 to measure overlay of the grating-over-grating structure, the overlay can be resolved and extracted from the captured image.

During the decomposition and extraction, the extracted signal from a single layer may be extracted, for example, by modeling the profile. The profile may be a projection of the 2D region of interest, marked as the frame area in Figures 5-7.

The method may further include improving the signal-to-noise ratio of the extracted signal. In one example, design-based filtering is applied, which is a filtering algorithm that incorporates information about the design criteria. Signal-to-noise ratio improvements are described in U.S. Pat. Nos. 5,393,343 and 5,433,633, which are incorporated by reference in their entireties.

During the refinement, a design-based filter may be applied to the extracted signal. This may be useful when the non-contaminated area is small. In some cases, a 1D or 2D filter with known fine and coarse pitches is used. The target designer can provide these design parameters. During profile extraction, anything that does not follow the design is considered noise and removed, improving the signal-to-noise ratio.

During decomposition and extraction, the scattering of the extracted signal may be further decomposed. The scattering can be resolved by applying the BSE profile to Equation 2 or Equation 3.

During the scattering decomposition, the backscattered electron profile may be applied to the extracted signal to determine a transfer function for the extracted signal, and a model for the scattering may be generated having the transfer function. The transfer function may be as illustrated in Equation 4.

The parameters of the model may be optimized using the local asymmetry or center of symmetry of the secondary electron signal. The parameters of the model may be optimized by aligning the calibration scan location to a second calibration scan location where the backscattered electron-secondary electron interaction for a particular layer can be found.

Physical properties may be used to optimize the parameters of the scattering model. For example, the center of symmetry of the full SE signal can be used. The center of symmetry is an assumption that the target designer must follow. The assumption can be used when solving the scattering problem. This symmetry can be broken when grid-over-grids are placed. Therefore, it is better to constrain the algorithm to make each grid in the equations symmetric.

A local asymmetry (e.g., qMerit function) may be used. A local asymmetry may be generated during extraction of the periodic signal. Yet, each period may be asymmetric, as disclosed, for example, in U.S. Pat. No. 6,399,323, which is incorporated by reference in its entirety. qMerit may be used in solving the equations disclosed herein. Constraints may be used to ensure that the local asymmetry (qMerit) is minimized for each grid that is input to the equations.

The alignment of the blank area (calibration area) where the BSE-SE interactions of a particular layer can be found can be used as represented by the function f( _SE1 (x), BSE(x+ _x1 )) in Equation 4. After the equations disclosed in this application are solved, the found signals can be aligned to the blank area according to the constraints.

The signal contamination cleaning step is depicted in Figures 9A-9F, which depict the process of solving the scattering problem. Figures 9A-9F are profiles and images, respectively. The profile is a 1D projection extracted from the image. This is a grid-over-grid image, so both grids are visible. The two grids are not aligned, and are affected by process overlay and design. This misalignment causes the profile to be asymmetric, even if they are processed symmetrically. According to the procedure described in the embodiments of the present disclosure, profiles and images are extracted for each layer. This is shown in Figures 9C-9D, 9E-9F for the top and bottom grids, respectively. Both profiles are shown as projections and images, and they have been reconstructed to appear symmetric.

Figure 10 is a block diagram of one embodiment of a system 200. The system 200 includes a wafer inspection tool (having an electron column 201) configured to generate an image of a wafer 204.

The wafer inspection tool may include a power capture subsystem (e.g., an electron beam power capture subsystem) that includes at least an energy source and a detector. The power capture subsystem may be an electron beam power capture subsystem. For example, in one embodiment, the energy directed to the wafer 204 may be electrons, and the energy detected from the wafer 204 may be electrons. Note that the wafer 204 may be the specimen. In this configuration, the energy source may be an electron beam source. In such an embodiment shown in FIG. 10, the power capture subsystem may include an electron column 201 that may be coupled to a computer subsystem 202. A stage 210 may hold the wafer 204.

The wafer 204 may have an overlay target. The overlay target may include a grating over grating structure, a calibration scan location, and an overlay scan location.

Also shown in FIG. 10, the electron column 201 may include an electron beam source 203 configured to generate electrons that are focused onto a wafer 204 by one or more elements 205. The electron beam source 203 may include, for example, a cathode type electron source or an emitter tip. The one or more elements 205 may include, for example, a gun lens, an anode, a beam limiting aperture, a gate valve, a beam flow selection aperture, an objective lens, and a scanning subsystem, any of which may include any type of element known and suitable in the art.

Electrons returning from wafer 204 (e.g., secondary electrons) may be focused by one or more elements 206 onto detector 207. One or more elements 206 may include, for example, a scanning subsystem, which may be the same as the scanning subsystem included in element(s) 205.

The electron column 201 may also include any other suitable type of element known in the art.

Although the electron column 201 is shown in FIG. 10 configured such that electrons are directed at the wafer 204 at one oblique angle of incidence and scattered from the wafer 204 at another oblique angle, the electron beam may be directed at and scattered from the wafer 204 at any suitable angle. In addition, the electron beam output capture subsystem may be configured to generate images of the wafer 204 using multiple modes (e.g., with different illumination angles, collection angles, etc.). The differences between the multiple modes of the electron beam output capture subsystem may be differences in any imaging parameters of the output capture subsystem.

As described above, the computer subsystem 202 may be coupled to a detector 207. The detector 207 may detect electrons returning from the surface of the wafer 204 to form an electron beam image of the wafer 204. The electron beam image may include any suitable electron beam image. The computer subsystem 202 may be configured to perform any of the functions described herein using the output of the detector 207 and/or the electron beam image. The computer subsystem 202 may be configured to perform any additional step(s) described herein. The system 200 with output capture subsystem shown in FIG. 10 may be further configured as disclosed herein.

10 is provided herein to provide a simplified depiction of an e-beam power capture subsystem configuration that may be used in the embodiments described herein. The e-beam power capture subsystem configuration described herein may be modified to optimize the performance of the power capture subsystem, as is commonly done when designing a commercial power capture system.

In addition, the systems described herein may be implemented using existing systems (e.g., by adding the functionality described herein to an existing system). In such a system, the methods described herein may be provided as optional features of the system (e.g., in addition to other features of the system). Alternatively, the systems described herein may be designed as entirely new systems.

Although the output capture subsystem is described above as an electron beam output capture subsystem, the output capture subsystem may be an ion beam output capture subsystem. Such an output capture subsystem may be configured as shown in FIG. 10, except that the electron beam source is replaced by any suitable ion beam source known in the art. In addition, the output capture subsystem may be any other suitable ion beam output capture subsystem, such as those incorporated in commercially available focused ion beam (FIB) systems, helium ion microscope (HIM) systems, and secondary ion mass spectrometry (SIMS) systems.

The computer subsystem 202 includes a processor 208 and an electronic data storage unit 209. The processor 208 may be a microprocessor, a microcontroller, or other device.

Computer subsystem 202 may be coupled to the components of system 200 in any suitable manner (e.g., via one or more transmission media, including, for example, wired and/or wireless transmission media) so that the processor 208 can receive the output. Processor 208 may be configured to perform a number of functions using the output. The wafer inspection tool may receive instructions and other information from processor 208. Processor 208 and/or electronic data storage unit 209 may optionally be in electronic communication with another wafer inspection tool, wafer metrology tool, or wafer review tool (not shown) to receive additional information or send instructions.

The processor 208 is in electronic communication with a wafer inspection tool, such as the detector 207. The processor 208 may be configured to process images generated using metrology results provided by the detector 207. For example, the processor may be configured to perform the method 100 of the embodiments.

The computer subsystem 202, other system or systems, or other subsystems described herein may be part of a variety of systems, including personal computer systems, image computers, mainframe computer systems, workstations, network appliances, Internet appliances, and other devices. The or those subsystems or systems may include any suitable processor known in the art, such as a parallel processor. In addition, the or those subsystems or systems may include high speed processing platforms and software, whether stand-alone or network-attached tools.

The processor 208 and electronic data storage unit 209 may be located within or otherwise part of the system 200 or other device. According to one example, the processor 208 and electronic data storage unit 209 may be part of a stand-alone control unit or may be provided within a centralized quality control unit. Multiple processors 208 or electronic data storage units 209 may be used.

Processor 208 may be implemented in any combination of hardware, software, and firmware. Furthermore, the functions described herein may be performed in a single unit or may be shared among different components, each of which may also be implemented in any combination of hardware, software, and firmware. Program code or instructions for causing processor 208 to perform and implement the various methods and functions may be stored in a readable storage medium, which may be, for example, the memory of electronic data storage unit 209 or other memory.

When system 200 includes multiple computer subsystems 202, the different subsystems may be coupled together to transmit images, data, information, instructions, and the like between the subsystems. For example, a subsystem may be coupled to one or more additional subsystems by any suitable transmission medium, which may be any suitable wired and/or wireless transmission medium known in the art. Two or more of such subsystems may be substantially coupled together by a shared computer-readable storage medium (not shown).

Processor 208 may be configured to perform a number of functions using the output of system 200 or other outputs. For example, processor 208 may be configured to send an output to electronic data storage unit 209 or other storage medium. Processor 208 may be further configured as described herein.

The processor 208 or computer subsystem 202 may be part of a defect review system, an inspection system, a metrology system, or any other type of system. That is, some configurations described in the embodiments of the present disclosure may be tailored in various ways for systems with different capabilities that are more or less suitable for different applications.

When the system has multiple subsystems, the different subsystems may be coupled together to transmit images, data, information, instructions, etc. between the subsystems. For example, a subsystem may be coupled to one or more additional subsystems by any suitable transmission medium, which may be any suitable wired and/or wireless transmission medium known in the art. Two or more of such subsystems may be substantially coupled together by a shared computer-readable storage medium (not shown).

Processor 208 may be configured according to any of the embodiments described herein. Processor 208 may be configured to perform other functions or additional steps using the output of system 200, or using images or data from other sources.

According to an example, a processor 208 can be in communication with the system 200. The processor 208 can be configured to measure the overlay of the grating-over-grating structure using the captured images. The processor 208 can be further configured to measure the overlay of the grating-over-grating structure using the captured images by decomposing and extracting the overlay from the captured images.

Processor 208 may be communicatively coupled to any of the various components or subsystems of system 200 in any manner known in the art. Additionally, processor 208 may be configured to receive and/or capture data or information from other systems (e.g., inspection results from an inspection system, e.g., review tools, design data in a remote database, etc.) via a transmission medium, e.g., having wired and/or wireless sections. In such a manner, the transmission medium may act as a data link between processor 208 and other subsystems of system 200 or systems outside of system 200.

According to one example, a non-transitory computer readable storage medium may include one or more programs for performing method steps, such as a method 100 for capturing an overlay target with an electron beam output capture subsystem to form a captured image, and using the captured image to measure overlay of a grating-over-grid structure. The steps may further include decomposing and extracting the overlay from the captured image.

The various steps, functions and/or operations of the system 200 and methods disclosed herein may be performed by one or more of electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controllers/switches, microcontrollers, or information processing systems. Program instructions implementing the methods, such as those described herein, may be transmitted or stored on a carrier medium. The carrier medium may include a storage medium, such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid-state memory, a magnetic tape, or the like. The carrier medium may include a transmission medium, such as a wire, a cable, or a wireless transmission link. For example, the various steps described throughout this disclosure may be performed by a single processor 208 (or computer subsystem 202) or, alternatively, by multiple processors 208 (or multiple computer subsystems 208). Additionally, the various subsystems of the system 200 may include one or more information processing or logic systems. Therefore, the above statements should not be construed as limitations on the present disclosure, but merely as illustrative.

The method steps described in accordance with the various embodiments and examples of the present disclosure are sufficient to carry out the method of the present invention. That is, in one embodiment, the method consists essentially of a combination of the method steps of the methods disclosed herein. In another embodiment, the method consists solely of those steps.

Although the present disclosure has been described with reference to one or more specific embodiments and/or examples, it will be understood that other embodiments of the present disclosure may be constructed without departing from the scope of the present disclosure.

Claims (18)

1. A method comprising:
1. A method for forming a captured image by capturing an overlay target with an electron beam output capture subsystem, wherein the overlay target comprises:
A lower lattice structure, and an upper lattice structure disposed on the lower lattice structure,
a lattice-over-lattice structure having
a calibration scan location where the lower grating structure is present but the upper grating structure is absent;
an overlay scanning location where the upper lattice structure and the lower lattice structure are located;
and a method for measuring overlay of the grating-over-grating structure using the captured images. The method of claim 1, wherein when measuring the overlay of the grating-over-grating structure, the method decomposes and extracts the overlay from the captured image. The method of claim 2, wherein an extracted signal is extracted from a single layer during the decomposition and extraction. The method of claim 3, further comprising improving the signal-to-noise ratio of the extracted signal. The method of claim 4, wherein a design stance filter is applied to the extracted signal during the refinement. The method of claim 3, further comprising decomposing the scattering of the extracted signal during the decomposition and extraction. 7. The method of claim 6, wherein resolving the scattering comprises:
applying a backscattered electron profile to the extracted signal;
determining a transfer function for the extracted signal;
generating a model of the scattering having the transfer function;
method. 8. The method of claim 7, wherein the parameters of the model are optimized by aligning the calibration scan location to a second calibration scan location where a backscattered electron-secondary electron interaction for a particular layer is found, or by using a local asymmetry or center of symmetry of the secondary electron signal. A non-transitory computer-readable storage medium having one or more programs for executing the method of claim 1 on one or more information processing devices. A non-transitory computer-readable storage medium having one or more programs for executing the method of claim 2 on one or more information processing devices. 1. A system comprising:
a stage configured to hold a specimen having an overlay target, the overlay target comprising:
a lower lattice structure disposed on the sample; and an upper lattice structure disposed on the lower lattice structure.
a lattice-over-lattice structure having
a calibration scan location where the lower grating structure is present but the upper grating structure is absent;
an overlay scanning location where the upper lattice structure and the lower lattice structure are located;
an overlay target comprising:
an electron beam output capture subsystem configured to measure the overlay target on the stage; and
A system comprising: a processor in electronic communication with the electron beam output capture subsystem configured to measure overlay of the grating-over-grating structure using a captured image. The system of claim 11, wherein the processor is configured to measure the overlay of the grid-over-grid structure using the captured image by decomposing and extracting the overlay from the captured image. The system of claim 12, wherein the decomposition and extraction extracts an extracted signal from a single layer. The system of claim 13, further comprising: improving the signal-to-noise ratio of the extracted signal using the processor. The system of claim 14, wherein a design stance filter is applied to the extracted signal during the refinement. The system of claim 13, further comprising, during the decomposition and extraction, decomposing scattering of the extracted signal. 17. The system of claim 16, wherein resolving the scattering comprises:
applying a backscattered electron profile to the extracted signal;
determining a transfer function for the extracted signal;
generating a model of the scattering having the transfer function;
system. 20. The system of claim 17, wherein the model parameters are optimized by aligning the calibration scan location to a second calibration scan location where a backscattered electron-secondary electron interaction for a particular layer is found, or by using a local asymmetry or center of symmetry of the secondary electron signal.

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