JP7703880B2 - Multi-chip module and electronic control device equipped with multi-chip module - Google Patents

Description

This disclosure relates to a multi-chip module and an electronic control device equipped with a multi-chip module.

Patent Document 1 discloses an example of a multi-chip module. The multi-chip module has a module substrate and a semiconductor element mounted on the module substrate, and is mounted on a main substrate. The semiconductor element is supplied with power via surface power wiring provided on the surface of the main substrate.

Patent No. 6468360

Although not a conventional technique, a multi-chip module may be configured such that a semiconductor element having a communication function and a power supply circuit that supplies power to the semiconductor element are mounted on the mounting surface of a module substrate. The module substrate may also be configured to have, as wiring, conductor patterns stacked with an insulator interposed therebetween and interlayer connectors that connect the conductor patterns of different layers. This multi-chip module will have a power supply path, which is wiring that connects the semiconductor element and the power supply circuit, and a communication path, which is wiring used for communication between the semiconductor elements.

However, in multi-chip modules, the power supply paths and communication paths may run parallel to each other between wiring or adjacent vias on adjacent layers. This parallel running of wiring in multi-chip modules may result in noise being superimposed on the communication paths.

One disclosed objective is to provide a multi-chip module that reduces noise on the communication path. Another disclosed objective is to provide an electronic control device that can suppress the propagation of noise from the multi-chip module.

The multi-chip module disclosed herein comprises:
A module substrate (1) having a plurality of substrate electrodes (13a to 13e, 14) and a plurality of wirings connected to the substrate electrodes, the wirings including conductor patterns laminated via an insulator and interlayer connection portions connecting the conductor patterns of different layers;
a semiconductor element (2) having a plurality of element terminals (21, 211 to 213), the element terminals being connected to substrate electrodes and mounted on a module substrate;
a power supply circuit (3) having a plurality of circuit terminals (32a, 32b), the circuit terminals being connected to the board electrodes and mounted on the module board, and supplying power to the semiconductor element;
The semiconductor element has, as element terminals, a plurality of communication terminals (211) having a communication interface function, and power supply terminals (212, 213) connected to a power supply path including some wirings and some substrate electrodes that are paths between the semiconductor element and a power supply circuit;
The power supply circuit has a circuit terminal connected to a power supply path,
The module substrate has a communication path that includes some wiring different from the power supply path and some substrate electrodes and is connected to the communication terminal, and a plurality of low-speed chip terminals (16) on a surface opposite to the mounting surface on which the semiconductor element and the power supply circuit are mounted ,
the communication path is provided outside an area facing the power supply path in a mounting direction of the semiconductor element on the module substrate,
The communication terminal is used for high-speed communication,
The semiconductor element includes, in addition to the communication terminal, a low-speed communication terminal (26a) provided in a part of an opposing region of the plurality of low-speed chip terminals in the mounting direction and used for low-speed communication slower than high-speed communication;
the module substrate has a low-speed communication path that includes some wiring and some substrate electrodes different from the power supply path and the communication path and is connected to the low-speed communication terminal;
At least a portion of the low-speed communication path is provided in an area facing the power supply path in the mounting direction ,
The power supply path is arranged linearly between the power supply circuit and the semiconductor element in a plan view .

In this way, the multi-chip module has a communication path arranged outside the opposing area of the power path. This allows the multi-chip module to reduce the area in which the communication path and the power path run parallel to each other, compared to a configuration in which the communication path is arranged in the opposing area of the power path. As a result, the multi-chip module can reduce the superposition of noise from the power path onto the communication path.

The electronic control device disclosed herein comprises:
The multi-chip module;
A wiring board (200) on which the multi-chip module is mounted,
The wiring board comprises an insulating substrate (201), a plurality of wiring layers (202) stacked via the insulating substrate, and a plurality of through vias (203) that penetrate the insulating substrate and electrically connect each wiring layer.

The electronic control device includes a multi-chip module. This reduces the superposition of noise from the power supply path to the communication path in the multi-chip module. This allows the electronic control device to suppress noise propagating from the multi-chip module to the multilayer wiring board via the communication path. The electronic control device also uses a wiring board with through vias. This makes it easier to suppress noise deterioration in the electronic control device than when a build-up board is used as the wiring board.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference symbols in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

1 is a plan view showing a schematic configuration of an electronic control device according to a first embodiment; FIG. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 11 is a plan view showing a schematic configuration of an electronic control device according to a second embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3 . FIG. 13 is a plan view showing a schematic configuration of an electronic control device according to a third embodiment. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 13 is a cross-sectional view showing a schematic configuration of an electronic control device according to a fourth embodiment.

Below, several embodiments for implementing the present disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in the preceding embodiment may be given the same reference numerals, and duplicated descriptions may be omitted. In each embodiment, when only a part of the configuration is described, the other parts of the configuration may be applied by referring to the other embodiment described previously.

First Embodiment
A multi-chip module 100 and an electronic control device 1000 will be described with reference to Figures 1 and 2. The electronic control device 1000 is configured to be mountable on, for example, a vehicle. That is, the electronic control device 1000 can be used, for example, in an in-vehicle electronic control device. The electronic control device 1000 includes a multi-chip module 100 and a motherboard 200. Hereinafter, the multi-chip module will also be referred to as MCM for short.

<Multi-chip module>
The MCM 100 includes a module substrate 1, a semiconductor element 2, and a power supply circuit 3. The MCM 100 includes components such as the semiconductor element 2 and the power supply circuit 3 mounted on the module substrate 1. The MCM 100 may also include a memory device in addition to the semiconductor element 2 and the power supply circuit 3.

The module substrate 1 comprises an insulating substrate 10, a protective film 11, pattern wiring 12a, an interlayer connection portion 12b, a plurality of pads 13e-13e, 14, and a chip connection terminal 15. The insulating substrate 10 is composed primarily of an electrically insulating material such as resin or ceramics. The insulating substrate 10 corresponds to an insulator. The module substrate 1 has a mounting surface on which the semiconductor element 2 and the power supply circuit 3 are mounted, and a surface opposite the mounting surface.

The protective film 11 is composed mainly of an electrically insulating material. The protective film 11 covers the surface of the insulating substrate 10 and the pattern wiring 12a provided on the surface of the insulating substrate 10 so that at least a portion of each of the pads 13e-13e, 14 is exposed. The protective film 11 is provided to ensure electrical insulation between each of the pads 13e-13e, 14 as necessary. The protective film 11 is also provided to protect the surface of the insulating substrate 10 and the pattern wiring 12a provided on the surface of the insulating substrate 10.

The pattern wiring 12a and the interlayer connection portion 12b constitute the wiring. The pattern wiring 12a and the interlayer connection portion 12b are mainly composed of conductive materials. The pattern wiring 12a is laminated via the insulating substrate 10. The pattern wiring 12a is provided on the inner layer and the surface layer of the insulating substrate 10. The interlayer connection portion 12b connects the pattern wiring 12a of different layers. The module substrate 1 is provided with a plurality of pattern wirings 12a and a plurality of interlayer connection portions 12b. The pattern wiring 12a corresponds to a conductor pattern.

The multiple pads 13a to 13e, 14 are mainly made of a conductive material. Each of the pads 13a to 13e, 14 is connected to the pattern wiring 12a and the interlayer connection portion 12b. The multiple pads 13a to 13e are provided on the mounting surface side of the module substrate 1. The back surface pad 14 is provided on the opposite surface side of the module substrate 1. Each of the pads 13a to 14 corresponds to a substrate electrode.

The module substrate 1 has a power supply path formed by some of the wiring and some of the substrate electrodes. The module substrate 1 has a supply path and a ground path as the power supply path. The supply path includes some of the wiring, a first power supply pad 13a, and a second power supply pad 13b. The first power supply pad 13a and the second power supply pad 13b are electrically connected via some of the wiring. The ground path includes some of the wiring different from the supply path, a first ground pad 13c, and a second ground pad 13d. The first ground pad 13c and the second ground pad 13d are electrically connected via some of the wiring different from the supply path.

In addition, in the module substrate 1, a communication path is formed by a portion of wiring different from the power supply path and a portion of substrate electrodes different from the power supply path. The communication path includes a portion of wiring different from the power supply path and a communication pad 13e. Furthermore, the communication path includes a back surface pad 14. The communication pad 13e and the back surface pad 14 are electrically connected via a portion of wiring different from the power supply path.

The first power supply pad 13a, the first ground pad 13c, and the communication pad 13e are arranged facing the semiconductor element 2. The first power supply pad 13a is electrically connected to the element power supply terminal 212. The module substrate 1 is provided with the same number of first power supply pads 13a as the number of element power supply terminals 212. Therefore, when the module substrate 1 is provided with a plurality of element power supply terminals 212, it can be said that the module substrate 1 is provided with a first power supply pad group consisting of a plurality of first power supply pads 13a.

The first ground pad 13c is electrically connected to the element ground terminal 213. The module substrate 1 is provided with the same number of first ground pads 13c as the number of element ground terminals 213. Therefore, when the module substrate 1 is provided with a plurality of element ground terminals 213, it can be said that the module substrate 1 is provided with a first ground pad group consisting of a plurality of first ground pads 13c.

The communication pad 13e is electrically connected to the communication terminal 211. The module board 1 is provided with the same number of communication pads 13e as the number of communication terminals 211. Therefore, when the module board 1 is provided with a plurality of communication terminals 211, it can be said that a communication pad group consisting of a plurality of communication pads 13e is provided.

The second power supply pad 13b and the second ground pad 13d are arranged facing the power supply circuit. The second power supply pad 13b is electrically connected to the circuit power supply terminal 32a. The module substrate 1 is provided with the same number of second power supply pads 13b as the number of circuit power supply terminals 32a. Therefore, when the module substrate 1 is provided with a plurality of circuit power supply terminals 32a, it can be said that the module substrate 1 is provided with a second power supply pad group consisting of a plurality of second power supply pads 13b.

The second ground pad 13d is electrically connected to the circuit ground terminal 32b. The module substrate 1 is provided with the same number of second ground pads 13d as the number of circuit ground terminals 32b. Therefore, when the module substrate 1 is provided with a plurality of circuit ground terminals 32b, it can be said that the module substrate 1 is provided with a second ground pad group consisting of a plurality of second ground pads 13d.

The back surface pads 14 are electrically connected to the mother board 200. The module board 1 is provided with the same number of back surface pads 14 as the number of communication terminals 211. Therefore, when the module board 1 is provided with a plurality of communication terminals 211, it can be said that a communication pad group consisting of a plurality of back surface pads 14 is provided.

The chip connection terminals 15 are electrically connected to the back surface pads 14. The chip connection terminals 15 are terminals for connecting to the mother board 200 in the MCM 100. The chip connection terminals 15 correspond to board terminals.

The semiconductor element 2 includes an element substrate 20 and element terminals 21. The semiconductor element 2 includes a communication circuit. In other words, the semiconductor element 2 has a communication function. The semiconductor element 2 includes element terminals 21, which include a communication terminal 211, an element power supply terminal 212, and an element ground terminal 213. The element terminals 21 are mainly made of a conductive material. The element terminals 21 are provided in a portion of the element substrate 20 that faces the module substrate 1 (hereinafter, the facing portion). The semiconductor element 2 includes a plurality of element terminals 21. The semiconductor element 2 is mounted on the module substrate 1 with the element terminals 21 connected to the substrate electrodes.

The communication terminals 211 have a communication interface function. The semiconductor element 2 includes a plurality of communication terminals 211. The communication terminals 211 are disposed opposite the communication pads 13e. The communication terminals 211 are connected to the communication pads 13e via a conductive adhesive such as solder. In the following, solder is used as an example of a conductive adhesive.

The semiconductor element 2 has a plurality of element power supply terminals 212 and a plurality of element ground terminals 213. The plurality of element power supply terminals 212 are electrically connected to the first power supply pad 13a via solder. The plurality of element ground terminals 213 are electrically connected to the first ground pad 13c via solder. The element power supply terminals 212 and the element ground terminals 213 correspond to power supply terminals.

As shown in FIG. 1, the semiconductor element 2 is provided with a first terminal group 21a, a second terminal group 21b, a third terminal group 21c, a fourth terminal group 21d, and a power supply terminal group 21e. Each of the first terminal group 21a to the fourth terminal group 21d includes a plurality of communication terminals 211. The power supply terminal group 21e includes a plurality of element power supply terminals 212 and a plurality of element ground terminals 213.

The semiconductor element 2 has a power supply terminal group 21e arranged in the center of the opposing portion. The semiconductor element 2 has a first terminal group 21a to a fourth terminal group 21d arranged around the power supply terminal group 21e in the opposing portion.

In this embodiment, as an example, an example is used in which one semiconductor element 2 is mounted on the module substrate 1. In the present disclosure, multiple semiconductor elements 2 may be mounted on the module substrate 1.

The power supply circuit 3 includes a circuit board 30, a circuit power terminal 32a, and a circuit ground terminal 32b. The power supply circuit 3 is a circuit element that supplies power to the semiconductor element 2. In other words, the power supply circuit 3 supplies power to the semiconductor element 2 via a power supply path.

The circuit power supply terminal 32a and the circuit ground terminal 32b are provided at a portion of the circuit board 30 that faces the module board 1. The power supply circuit 3 is provided with a plurality of circuit power supply terminals 32a and a plurality of circuit ground terminals 32b. The power supply circuit 3 is mounted on the module board 1 with the circuit power supply terminals 32a and the circuit ground terminals 32b connected to the board electrodes.

The multiple circuit power terminals 32a are electrically connected to the second power pad 13b via solder. The multiple circuit ground terminals 32b are electrically connected to the second ground pad 13d via solder. The circuit power terminals 32a and the circuit ground terminals 32b correspond to circuit terminals.

As shown in FIG. 2, in the MCM1 configured in this manner, the communication path is provided outside the opposing area of the power path in the stacking direction. In other words, the pattern wiring 12a, the communication pad 13e, and the back surface pad 14 are provided outside the opposing area of the power path in the stacking direction. The communication path is provided including the opposing area of the power path in the direction perpendicular to the stacking direction.

The stacking direction is the direction in which the pattern wiring 12a is stacked. The stacking direction also coincides with the mounting direction of the semiconductor element on the module substrate. Furthermore, the stacking direction also coincides with the thickness direction of the module substrate 1.

<Motherboard>
The motherboard 200 is a wiring board in which a plurality of wirings 202 made mainly of a conductive material are provided on an insulating substrate 201 such as resin or ceramics. In the motherboard 200, the plurality of wirings 202 are provided inside and on the surface of the insulating substrate 201. In the motherboard 200, the plurality of wirings 202 are stacked with the insulating substrate 201 interposed therebetween. The wirings 202 correspond to a wiring layer.

The motherboard 200 is a through-hole substrate in which through-hole vias 203 are formed, penetrating the insulating substrate 201. The through-hole vias 203 are electrically connected to the wiring 202. The through-hole vias 203 electrically connect the wiring 202 of different layers. In more detail, the motherboard 200 has a through-hole, which penetrates from one surface of the insulating substrate 201 to the opposite surface, provided with a metal film on the surface. In other words, the motherboard 200 has through-hole vias 203 whose surface is plated with metal. The surface of the through-hole is the surface of the annular wall surrounding the through-hole in the insulating substrate.

In the motherboard 200, some of the through vias 203 are provided as electrodes on one side and the opposite side of the insulating substrate 201. In the motherboard 200, the electrodes and the chip connection terminals 15 are connected via solder. The motherboard 200 corresponds to a wiring board. Note that the motherboard 200 has wiring 202 and through vias 203 provided in multiple locations. However, in FIG. 2, in order to simplify the drawing, only some of the wiring 202 and through vias 203 are shown.

<Electronic control device>
The electronic control device 1000 is configured by mounting an MCM 100 on a motherboard 200. In the present embodiment, as an example, an electronic control device 1000 in which one MCM 100 is mounted on the motherboard 200 is employed. However, the present disclosure is not limited to this. The electronic control device 1000 may be mounted with a plurality of MCMs 100. Furthermore, the electronic control device 1000 may be mounted with circuit elements, connectors, etc. different from the MCM 100.

＜Effects＞
In the MCM 100 configured as described above, a large current flows through the power supply path when power is supplied from the power supply circuit 3 to the semiconductor element 2. In the MCM 100, a power supply loop is formed in a portion including the power supply path, as shown by the dashed line in Fig. 2. In addition, in the MCM 100, a current flows through the communication path, as shown by the dashed line in Fig. 2.

Therefore, in the MCM100, the communication path is arranged outside the opposing area of the power path. As a result, the MCM100 can reduce the area in which the communication path and the power path run parallel to each other, compared to a configuration in which the communication path is arranged in the opposing area of the power path. Therefore, the MCM100 can reduce the superposition (propagation) of noise from the power path to the communication path. As a result, the MCM100 can improve the margin for communication by the semiconductor element 2 and the establishment of power supply to the semiconductor element 2.

In this way, the MCM 100 suppresses the propagation of noise caused by the current flowing through the power supply path to the communication path. Therefore, the MCM 100 confines the noise caused by the current flowing through the power supply path within the MCM 100. Therefore, the MCM 100 can suppress the diffusion of noise from the MCM 100 to the motherboard 200.

The electronic control device 1000 has a configuration in which the MCM 100 is mounted on the mother board 200, which improves EMC (Electromagnetic Compatibility) more than when the mother board 200 and the MCM 100 are configured on a single board. Furthermore, the electronic control device 1000 uses the MCM 100 around a semiconductor element having a group of multiple high-speed terminals. Therefore, the electronic control device 1000 can be inexpensive, has high reliability, and can suppress noise. Furthermore, the electronic control device 1000 can reduce the number of layers of the mother board 200 compared to when the mother board 200 and the MCM 100 are configured on a single board. Therefore, the electronic control device 1000 can reduce the cost of the mother board 200. Therefore, the electronic control device 1000 is more likely to achieve the above-mentioned effect. Note that a low-layer board is, for example, a board with 8 layers or less, preferably 6 layers or less. However, the mother board 200 is not limited to a low-layer board.

The electronic control device 1000 also includes an MCM 100. As described above, this MCM 100 can reduce noise generated on the MCM 100 and can suppress the diffusion of noise to the motherboard 200. This allows the electronic control device 1000 to have improved noise resistance.

Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure. Below, the second to fourth embodiments are described as other forms of the present disclosure. The above embodiments and the second to fourth embodiments can each be implemented alone, but can also be implemented in appropriate combinations. The present disclosure is not limited to the combinations shown in the embodiments, and can be implemented in various combinations.

Second Embodiment
The MCM 100 and electronic control device 1000 of the second embodiment will be described with reference to Figures 3 and 4. In this embodiment, the configuration of the module board 1 is mainly different from that of the first embodiment. Note that in Figure 4, the mother board 200 is illustrated in a simplified form. The mother board 200 is the same as in the above embodiment. The mother board 200 is the same in the other embodiments.

As shown in Figures 3 and 4, the module substrate 1 has multiple chip terminal groups 15a to 15d. Each chip terminal group 15a to 15d includes multiple chip connection terminals 15. In other words, each chip terminal group 15a to 15d represents a collection of multiple chip connection terminals 15 included in the respective chip terminal group 15a to 15d. For example, the first chip terminal group 15a represents a collection of multiple chip connection terminals 15 included in the first chip terminal group 15a. Each chip terminal group 15a to 15d is provided on the surface of the module substrate 1 opposite the mounting surface.

As shown in FIG. 3, the chip connection terminals 15 of each chip terminal group 15a-15d are electrically connected to the element terminals 21 via each of the wirings 12c1-12c4. Each of the wirings 12c1-12c4 is included in a communication path. It can also be said that the module substrate 1 includes a plurality of wirings 12c1-12c4 that are included in different communication paths. Note that in FIG. 3, the wirings 12c1-12c4 are simplified and illustrated with lines.

More specifically, the chip connection terminals 15 of the first chip terminal group 15a are connected to the element terminals 21 of the first terminal group 21a via the first wiring 12c1. The chip connection terminals 15 of the second chip terminal group 15b are connected to the element terminals 21 of the second terminal group 21b via the second wiring 12c2. The chip connection terminals 15 of the third chip terminal group 15c are connected to the element terminals 21 of the third terminal group 21c via the third wiring 12c3. The chip connection terminals 15 of the fourth chip terminal group 15d are connected to the element terminals 21 of the fourth terminal group 21d via the fourth wiring 12c4.

Each chip terminal group 15a-15d is arranged along the edge of the opposite surface of the module substrate 1. The module substrate 1 has multiple chip connection terminals 15 arranged in multiple rows along the edge of the opposite surface. It can be said that the module substrate 1 has multiple chip connection terminals 15 arranged in a rectangular frame shape. Each chip terminal group 15a-15d includes a portion of the multiple chip connection terminals 15 arranged in this manner. Furthermore, each chip terminal group 15a-15d is arranged to avoid the area facing the power supply terminal group 21e. The electronic control device 1000 is implemented with an MCM 100 configured in this manner.

For this reason, the module substrate 1 is easy to provide each of the wirings 12c1-12c4 outside the opposing area of the power supply path in the stacking direction. In other words, the module substrate 1 can prevent the power supply path and the communication path including each of the wirings 12c1-12c4 from overlapping in the stacking direction. It can also be said that the module substrate 1 can prevent the power supply path and each of the wirings 12c1-12c4 (communication paths) from running parallel to each other in the stacking direction. Note that, as an example, the present embodiment employs a module substrate 1 in which all of the wirings 12c1-12c4 are arranged outside the opposing area of the power supply path in the stacking direction.

It is also preferable to arrange each of the chip terminal groups 15a-15d in the vicinity of the respective wirings 12c1-12c4 to which they are connected. In other words, each of the chip terminal groups 15a-15d is provided in a position where each of the wirings 12c1-12c4 can be arranged without crossing each other. This allows the MCM 100 to prevent each of the communication paths including each of the wirings 12c1-12c4 from crossing or running parallel to each other. This allows the MCM 100 to suppress noise caused by crosstalk between each of the communication paths.

Furthermore, the MCM 100 can arrange many chip connection terminals 15 on the opposite side. Therefore, the electronic control device 1000 can improve the wiring density of the motherboard 200. Naturally, the electronic control device 1000 and MCM 100 of the second embodiment can achieve the same effects as the first embodiment.

Third Embodiment
An MCM 100 and an electronic control device 1000 according to the third embodiment will be described with reference to Figures 5 and 6. In this embodiment, the main difference from the first embodiment is the configuration of the semiconductor element 2 and the module substrate 1.

The semiconductor element 2 is configured with a high-speed communication circuit for performing high-speed communication, and a low-speed communication circuit whose communication speed is slower than that of the high-speed communication circuit. In other words, it can be said to have a high-speed communication function and a low-speed communication function whose communication speed is slower than that of the high-speed communication function.

As shown in Figures 5 and 6, the semiconductor element 2 has multiple communication terminals 211 for high-speed communication and multiple low-speed communication terminals 26a for low-speed communication. Each of the terminal groups 21a to 21d can be considered a high-speed terminal group. In this embodiment, the communication terminal 211 is a terminal used for high-speed communication. Each of the chip terminal groups 15a to 15d and each of the wirings 12c1 to 12c4 are used for high-speed communication. Therefore, the communication path including the wirings 12c1 to 12c4 can be considered a high-speed communication path.

On the other hand, the low-speed terminal group 26 includes a number of low-speed communication terminals 26a. The low-speed communication terminals 26a are terminals used for low-speed communication.

The module substrate 1 has a plurality of low-speed chip terminals 16 on the opposite surface of the module substrate 1. Each low-speed chip terminal 16 is electrically connected to each low-speed communication terminal 26a and the fifth wiring 12c5. The plurality of low-speed chip terminals 16 are provided in the center of the opposite surface of the module substrate 1. The low-speed chip terminals 16 correspond to substrate terminals. The fifth wiring 12c5 includes some wiring and some substrate electrodes that are different from the high-speed communication path and the power supply path. The semiconductor element 2 has a low-speed communication path that includes the fifth wiring 12c5.

The power supply path pattern wiring 12a is provided around the fifth wiring 12c5 in a direction perpendicular to the stacking direction. The power supply path pattern wiring 12a is not mechanically connected to the fifth wiring 12c5. FIG. 6 illustrates only a portion of the power supply path pattern wiring 12a. However, the power supply path pattern wiring 12a is provided in locations other than those shown in FIG. 6. The entire power supply path pattern wiring 12a is provided around the fifth wiring 12c5 in a direction perpendicular to the stacking direction. In FIG. 6, the fifth wiring 12c5 is illustrated in white to make the drawing easier to see.

As shown in FIG. 6, at least a portion of the low-speed communication path is provided in an area facing the power supply path in the stacking direction. In other words, the high-speed communication path is arranged outside the area facing the power supply path in the stacking direction. On the other hand, the low-speed communication path is arranged within the area facing the power supply path in the stacking direction. Note that the low-speed communication path may be arranged outside the area facing the power supply path in the stacking direction. The electronic control device 1000 is implemented with an MCM 100 configured in this manner.

The electronic control device 1000 and MCM 100 of the third embodiment can achieve the same effects as those of the first embodiment. In addition, in the MCM 100 of the third embodiment, the low-speed communication path is arranged in the opposing area of the power supply path. However, the low-speed communication path is less likely to adversely affect communication even if noise propagates. Therefore, the MCM 100 of the third embodiment can increase the number of wirings that can be electrically connected to substrate terminals such as the chip connection terminals 15 and the low-speed chip terminals 16. In other words, the MCM 100 of the third embodiment can increase the number of wirings that can be electrically connected to substrate terminals compared to when the chip connection terminals 15 are provided only in a frame shape. In other words, the MCM 100 of the third embodiment can improve the wiring density of the module substrate 1.

Furthermore, the MCM 100 of the third embodiment has multiple low-speed chip terminals 16 in the center of the opposite surface of the module substrate 1. Therefore, the electronic control device 1000 of the third embodiment can distribute stress caused by warping of the MCM 100 or the motherboard 200 to each substrate terminal. In other words, the electronic control device 1000 of the third embodiment can distribute stress to each substrate terminal more than when the chip connection terminals 15 are provided only in a frame shape. Therefore, the electronic control device 1000 of the third embodiment can improve the mounting reliability of the MCM 100 to the motherboard 200.

Fourth Embodiment
An MCM 100 and an electronic control device 1000 according to the fourth embodiment will be described with reference to Fig. 7. This embodiment differs from the first embodiment mainly in that the MCM 100 is provided with a bypass capacitor 4.

As described above, the semiconductor element 2 has the power supply terminal group 21e arranged in the center of the opposing portion. In other words, the semiconductor element 2 has a plurality of element power supply terminals 212 and a plurality of element ground terminals 213 arranged in the center of the opposing portion.

The MCM 100 has a bypass capacitor 4 mounted on the opposite surface of the module substrate 1. The bypass capacitor 4 has a first electrode 41 and a second electrode 42. The bypass capacitor 4 is disposed between the element power supply terminal 212 and the element ground terminal 213. The first electrode 41 is connected to the element power supply terminal 212 via the pattern wiring 12a, the interlayer connection 12b, etc. On the other hand, the second electrode 42 is connected to the element ground terminal 213 via the pattern wiring 12a, the interlayer connection 12b, etc.

The bypass capacitor 4 is mounted on the opposite side of the module substrate 1, in an area facing the element power supply terminal 212 and the element ground terminal 213 in the mounting direction. In other words, the bypass capacitor 4 is mounted in an area facing the power supply terminal group 21e in the mounting direction.

Preferably, in the mounting direction, the module substrate 1 is connected in the shortest distance between the element power supply terminal 212 and the element ground terminal 213 connected to the mounting surface and the first electrode 41 and the second electrode 42 provided on the opposite surface. The electronic control device 1000 is mounted with an MCM 100 configured in this way.

The electronic control device 1000 and MCM 100 of the fourth embodiment can achieve the same effects as those of the first embodiment. The MCM 100 can connect the shortest path from the element power supply terminal 212 through the bypass capacitor 4 to the element ground terminal 213. Therefore, the MCM 100 can minimize impedance and maximize the power supply noise cutting effect of the bypass capacitor 4. In other words, the MCM 100 can be connected via a path with lower impedance than when the bypass capacitor 4 is placed horizontally, so the power supply noise cutting effect of the bypass capacitor 4 can be maximized. In addition, the MCM 100 can be expected to reduce the capacity and number of bypass capacitors 4.

Although the present disclosure has been described with reference to an embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, while various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more, or less are also within the scope and concept of the present disclosure.

1...module substrate, 10...insulating substrate, 11...protective film, 12a...pattern wiring, 12b...interlayer connection, 12c1...first wiring, 12c2...second wiring, 12c3...third wiring, 12c4...fourth wiring, 13a...first power supply pad, 13b...second power supply pad, 13c...first ground pad, 13d...second ground pad, 13e...communication pad, 14...back surface pad, 15...chip connection terminal, 15a...first chip terminal group, 15b...second chip terminal group, 15c...third chip chip terminal group, 15d...fourth chip terminal group, 2...semiconductor element, 20...element substrate, 21...element terminal, 211...communication terminal, 212...element power supply terminal, 213...element ground terminal, 21a...first terminal group, 21b...second terminal group, 21c...third terminal group, 21d...fourth terminal group, 21e...power supply terminal group, 3...power supply circuit, 30...circuit substrate, 32a...circuit power supply terminal, 32b...circuit ground terminal, 100...multi-chip module, 200...mother substrate, 1000...electronic control device

Claims (3)

A module substrate (1) having a plurality of substrate electrodes (13a to 13e, 14) and a plurality of wirings connected to the substrate electrodes, the wirings including conductor patterns laminated with an insulator interposed therebetween and interlayer connection portions connecting the conductor patterns of different layers;
a semiconductor element (2) having a plurality of element terminals (21, 211 to 213), the element terminals being connected to the board electrodes and mounted on the module board;
a power supply circuit (3) having a plurality of circuit terminals (32a, 32b), the circuit terminals being connected to the board electrodes and mounted on the module board, and supplying power to the semiconductor element,
The semiconductor element has, as the element terminals, a plurality of communication terminals (211) having a communication interface function, and power supply terminals (212, 213) connected to a power supply path including a part of the wiring and a part of the board electrodes, which is a path between the power supply circuit,
The power supply circuit has a circuit terminal connected to the power supply path,
the module substrate has a communication path that includes a part of the wiring and a part of the substrate electrodes different from the power supply path and is connected to the communication terminal, and a plurality of low-speed chip terminals (16) on a surface opposite to a mounting surface on which the semiconductor element and the power supply circuit are mounted ,
the communication path is provided outside an opposing region of the power supply path in a mounting direction of the semiconductor element on the module substrate,
the communication terminal is used for high-speed communication,
In addition to the communication terminals, the semiconductor element includes low-speed communication terminals (26 a) provided in a portion of an opposing region of the low-speed chip terminals in a mounting direction, the low-speed communication terminals being used for low-speed communication slower than the high-speed communication,
the module substrate has a low-speed communication path that includes a part of the wiring and a part of the substrate electrodes different from the power supply path and the communication path and is connected to the low-speed communication terminal;
At least a portion of the low-speed communication path is provided in an opposing region to the power supply path in the mounting direction ,
The power supply path is disposed linearly between the power supply circuit and the semiconductor element in a plan view of the multi-chip module. the module substrate further includes a plurality of terminal groups (15a to 15d) including a plurality of substrate terminals (15) on a surface opposite to the surface on which the semiconductor element and the power supply circuit are mounted;
2. The multi-chip module according to claim 1 , wherein the plurality of terminal groups are connected to the communication paths and are arranged along a side of the opposite surface. A multi-chip module according to claim 1 or 2 ;
a wiring board (200) on which the multi-chip module is mounted;
The wiring board is an electronic control device comprising an insulating substrate (201), a plurality of wiring layers (202) stacked via the insulating substrate, and a plurality of through vias (203) that penetrate the insulating substrate and electrically connect each wiring layer.

Images