JP7704074B2 - Resistivity measurement method - Google Patents

Description

The present invention relates to a resistivity measurement method, and more specifically, to a resistivity measurement method that converts the resistivity of a silicon epitaxial layer measured by the C-V method into a four-probe resistivity that is traceable to international standards such as NIST.

Conventionally, the C-V (Capacitance-Voltage) method has been known as a method for measuring the resistivity of polished wafers (PW) (hereinafter sometimes simply referred to as PW), which are silicon single crystal wafers whose main surface has been polished, or silicon epitaxial wafers (hereinafter sometimes simply referred to as EPW), which are silicon epitaxial layers (hereinafter sometimes simply referred to as epilayers) grown by vapor phase growth on the main surface of the PW wafer.

For example, as described in Patent Document 1, in order to measure the C-V characteristics of a silicon single crystal wafer, a Schottky junction is formed on the main surface (first main surface) of the silicon single crystal wafer as a sample using a metal electrode, and the sample is fixed to the wafer stage of a C-V measurement device, and a reverse bias voltage is applied to the electrode while being continuously changed, expanding the depletion layer inside the silicon single crystal wafer and changing its capacitance.

Then, the impurity concentration and resistivity at a specified depth from the main surface of the silicon single crystal wafer are calculated based on the relationship between the bias voltage and the capacitance of the depletion layer.

To obtain highly accurate C-V characteristics, it is necessary to keep the contact resistance between the main back surface (second main surface) of the sample and the wafer stage small.

Patent Document 1 discloses a method for measuring C-V characteristics by placing a conductive cushion on the wafer stage and then closely contacting a silicon single crystal wafer with a conductive paste applied to its back surface on the conductive cushion.

The conductive cushion is preferably made of silicone rubber with silver or carbon kneaded into it, a resistivity of 0.01 Ω·cm or less, and a thickness of 0.2 mm to 0.75 mm.

SEMI MF723-0307 or Irvin curves are used to convert C-V characteristics to resistivity. Resistivity measurements using the four-probe method can be corrected using standard wafers with traceability to international standards, such as the seven resistivity reference materials (SRMs: Standard Reference Materials) SRM2541 (0.01 Ω·cm) to SRM2547 (200 Ω·cm) provided by NIST (National Institute of Standards and Technology).

It is desirable that resistivity measurements using the C-V method also have traceability to international standards such as NIST. Therefore, it has been proposed to ensure traceability by, for example, measuring a standard wafer that has traceability to the resistivity standard material SRM using the C-V method.

For example, in Patent Document 2, the resistivity of the epitaxial layer of a silicon epitaxial wafer having a P/N junction is valued and used as a secondary standard sample using a four-probe measuring device calibrated using the resistivity standard materials SRM2541 to SRM2547 as the primary standard sample, and the epitaxial layer is measured with a surface electrode C-V method measuring device to calibrate the surface electrode C-V method measuring device.

It is then proposed to use a C-V method measuring device for front electrodes calibrated with the secondary standard sample to measure the epitaxial layer resistivity of a P/P type or N/N type silicon epitaxial wafer to obtain a tertiary standard sample, and then to calibrate a C-V method measuring device for back electrodes using the tertiary standard sample.

JP 2016-76662 A JP 2018-32771 A

When using the method proposed in Patent Document 2, it is necessary to calibrate the resistivity using a silicon epitaxial wafer (EPW) with a P/N junction. In addition, both a C-V method measuring device for the front electrode and a C-V method measuring device for the back electrode are required.

The present invention has been made to address the above-mentioned issues, and aims to provide a resistivity measurement method with a new resistivity conversion that is used when tracing the C-V method to international standards such as NIST using PW wafers.

In order to solve the above problems, the present invention provides a resistivity measurement method for measuring the resistivity of a silicon epitaxial layer to be measured, which is formed on a silicon epitaxial wafer manufactured using a low resistivity substrate having a resistivity of 0.02 Ω cm or less, by a CV method, comprising:
The resistivity of the silicon epitaxial layer to be measured is measured by a CV method to obtain a SEMI-converted resistivity or a resistivity obtained by performing a predetermined conversion on the SEMI-converted resistivity.
A conversion according to a first conversion formula obtained by comparing a CV resistivity obtained by measuring a standard polished wafer, to which a four-probe standard resistivity is assigned, by a CV method with the four-probe standard resistivity;
Conversion by a second conversion formula obtained by comparing the C-V resistivity of a silicon epitaxial layer of a high resistivity substrate silicon epitaxial wafer prepared using a high resistivity substrate having a resistivity measurable by a C-V method and a silicon epitaxial layer of a low resistivity substrate silicon epitaxial wafer prepared using a low resistivity substrate having a resistivity of 0.02 Ω cm or less;
and obtaining a four-probe resistivity of the silicon epitaxial layer to be measured.
Here, the resistivity of a high resistivity substrate that has a resistivity that can be measured by the CV method is, for example, not less than 0.1 Ω·cm and not more than 1000 Ω·cm.

By using this invention, in addition to the conversion according to the first conversion formula obtained by comparing the C-V resistivity of a standard polished wafer with the four-probe standard resistivity, a conversion according to the second conversion formula obtained by comparing the C-V resistivity of a silicon epitaxial layer formed on a high resistivity substrate silicon epitaxial wafer with the C-V resistivity of a silicon epitaxial layer formed on a low resistivity substrate silicon epitaxial wafer is performed, making it possible to convert the C-V resistivity of a silicon epitaxial layer formed on a low resistivity substrate into a four-probe resistivity that is traceable to international standards such as NIST.

In other words, the present invention can provide a resistivity measurement method with a new resistivity conversion that is used when tracing the C-V method to international standards such as NIST using PW wafers.

The four-probe standard resistivity for the standard polished wafer is determined as follows:
a four-probe resistivity measurement device calibration process for calibrating the four-probe resistivity measurement device using a standard wafer that is traceable to an international standard;
a polished wafer standard resistivity rating step of rating a polished wafer to the four-probe standard resistivity using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibrating step;
It is desirable to have

The standard polished wafer obtained in this manner is used to determine the first conversion formula, and by performing conversion using this first conversion formula, the C-V resistivity of a silicon epitaxial layer formed on a high resistivity substrate can be converted with higher accuracy into a four-probe resistivity that is traceable to international standards such as NIST.

In this case, in the polished wafer standard resistivity rating process, the main surface of the polished wafer may be measured with the four-probe resistivity measuring device.

Alternatively, the polished wafer may be ground to produce a ground surface, and the ground surface may be measured with the four-point resistivity measuring device. It is preferable to perform surface grinding as the grinding.

In this way, measurements using a four-probe resistivity measurement device can be performed on the main surface (PW surface) of a polished wafer, or on the ground surface. Measuring the ground surface with a four-probe resistivity measurement device improves the measurement accuracy of the four-probe resistivity compared to measuring the PW surface.

It is preferable to use a polished wafer that has been heat-treated to eliminate oxygen donors.

By doing this, the four-probe standard resistivity can be determined more accurately.

Alternatively, as a standard polished wafer to which the four-probe standard resistivity is valued,
a four-probe resistivity measurement device calibration process for calibrating the four-probe resistivity measurement device using a standard wafer that is traceable to an international standard;
a rating step of measuring the resistivity of a silicon single crystal wafer that has been previously subjected to a heat treatment for eliminating oxygen donors, using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibrating step, and rating the four-probe standard resistivity;
A processing step of processing at least a first main surface of the priced silicon single crystal wafer into a polished wafer;
a cleaning step of cleaning the polished wafer;
As the silicon single crystal wafer, for example, one whose main surface is a lapped surface, a ground surface, or a chemically etched surface is used.

By using such standard polished wafers, the C-V resistivity of the silicon epitaxial layer being measured can be converted with greater precision into four-probe resistivity that is traceable to international standards such as NIST.

The second conversion formula is
a substrate polished wafer preparation step of preparing a high resistivity polished wafer having a resistivity measurable by a CV method and a low resistivity polished wafer having a resistivity of 0.02 Ω cm or less;
an epitaxial wafer preparation step of epitaxially growing a silicon epitaxial layer having the same resistivity and the same conductivity type as that of the high resistivity polished wafer under growth conditions of the same dopant concentration on each of the high resistivity polished wafer and the low resistivity polished wafer, thereby preparing the high resistivity substrate silicon epitaxial wafer and the low resistivity substrate silicon epitaxial wafer;
a CV measurement step of a comparative epitaxial wafer, in which a CV measurement is performed on a silicon epitaxial layer of the low resistivity substrate silicon epitaxial wafer and a silicon epitaxial layer of the high resistivity substrate silicon epitaxial wafer;
a comparison step of comparing the C-V resistivity of the silicon epitaxial layer of the low resistivity substrate silicon epitaxial wafer with that of the silicon epitaxial layer of the high resistivity substrate silicon epitaxial wafer;
It is desirable to carry out a second conversion step of converting the CV resistivity measurement result of the silicon epitaxial layer formed on the low resistivity substrate into the CV resistivity of a silicon epitaxial layer formed on a silicon epitaxial wafer including a high resistivity substrate by the second conversion formula.

By performing the second conversion process in this way in addition to the conversion using the first conversion formula, the C-V resistivity of a silicon epitaxial layer formed on a low resistivity substrate can be converted with higher accuracy into a four-probe resistivity that is traceable to international standards such as NIST.

When determining the first conversion formula, it is desirable to heat treat the standard polished wafer in a hydrogen atmosphere at 250°C or higher and 1150°C or lower before measuring the resistivity of the standard polished wafer by the C-V method.

By subjecting a standard polished wafer that has been heat-treated in this manner to C-V measurement, it is possible to prevent high resistance regions from appearing in the surface portion of the impurity concentration profile or resistivity profile.

When determining the first conversion formula, it is desirable to place a conductive cushion between the second main surface of the standard polished wafer and the measurement stage of a measurement device using the C-V method, apply a high-frequency voltage to the first main surface of the standard polished wafer, and measure the resistivity of the standard polished wafer by the C-V method.

When determining the first conversion formula, by measuring the C-V resistivity of a standard polished wafer with a conductive cushion placed in this manner, the contact resistance to the wafer stage is kept constant even for high resistivity wafers with different resistivities, which is expected to improve the accuracy of the first and second conversion formulas.

As described above, with the present invention, in addition to the conversion using the first conversion formula obtained by comparing the C-V resistivity of a standard polished wafer with the standard four-probe resistivity, the conversion is performed using the second conversion formula obtained by comparing the C-V resistivity of a silicon epitaxial layer formed on a high resistivity substrate silicon epitaxial wafer with the C-V resistivity of a silicon epitaxial layer formed on a low resistivity substrate silicon epitaxial wafer, making it possible to convert the C-V resistivity of a silicon epitaxial layer formed on a low resistivity substrate into a four-probe resistivity that is traceable to international standards such as NIST.

FIG. 2 is a schematic process diagram showing a schematic process for determining a first conversion equation in the resistivity measurement method according to the first embodiment of the present invention. FIG. 2 is a schematic process diagram showing a schematic process for determining a second conversion formula in the resistivity measurement method of the present invention. FIG. 1 is a schematic diagram of a CV measuring device. FIG. 11 is a schematic diagram showing a process for converting a CV resistivity measurement result of a silicon epitaxial layer formed on a silicon epitaxial wafer to be measured into a four-probe resistivity by performing conversion using a second conversion formula and then conversion using a first conversion formula. FIG. 11 is a schematic process diagram showing a schematic process for determining a first conversion equation in a resistivity measurement method according to a second embodiment of the present invention. 13 is a graph showing the amount of bias that the resistivity has when the second conversion formula is not used, relative to the resistivity converted using the second conversion formula. 1 is a graph comparing the four-probe standard resistivity with the CV resistivity measurement results of a silicon epitaxial layer formed on a silicon epitaxial wafer, which has been converted using the second conversion formula and the first conversion formula.

As mentioned above, there was a need to develop a resistivity measurement method with a new resistivity conversion that can be used to trace the C-V method to international standards such as NIST using polished wafers (hereinafter sometimes simply referred to as "PW wafers").

After extensive research into the above problem, the inventors discovered that by performing conversion using a second conversion formula obtained by comparing the C-V resistivity of the epitaxial layer of a high resistivity substrate silicon epitaxial wafer and the epitaxial layer of a low resistivity substrate silicon epitaxial wafer in addition to conversion using a first conversion formula obtained by comparing the C-V resistivity of the standard polished wafer with the standard four-probe resistivity, it is possible to convert the C-V resistivity of the silicon epitaxial layer to be measured into a four-probe resistivity that is traceable to international standards such as NIST, and thus completed the present invention.

That is, the present invention provides a resistivity measurement method for measuring the resistivity of a silicon epitaxial layer to be measured, which is formed on a silicon epitaxial wafer manufactured using a low resistivity substrate having a resistivity of 0.02 Ω cm or less, by a CV method, comprising:
The resistivity of the silicon epitaxial layer to be measured is measured by a CV method to obtain a SEMI-converted resistivity or a resistivity obtained by performing a predetermined conversion on the SEMI-converted resistivity.
A conversion according to a first conversion formula obtained by comparing a CV resistivity obtained by measuring a standard polished wafer, to which a four-probe standard resistivity is assigned, by a CV method with the four-probe standard resistivity;
Conversion by a second conversion formula obtained by comparing the C-V resistivity of a silicon epitaxial layer of a high resistivity substrate silicon epitaxial wafer prepared using a high resistivity substrate having a resistivity measurable by a C-V method and a silicon epitaxial layer of a low resistivity substrate silicon epitaxial wafer prepared using a low resistivity substrate having a resistivity of 0.02 Ω cm or less;
and obtaining a four-probe resistivity of the silicon epitaxial layer to be measured.

The present invention will be described in detail below with reference to the drawings, but the present invention is not limited to these.

[First embodiment]
A first embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a schematic diagram showing the general steps for determining the first conversion formula in the resistivity measurement method according to the first embodiment of the present invention.

First, the four-probe resistivity measurement device is calibrated using an international standard, for example, a standard wafer that is traceable to NIST (Figure 1 (a) Four-probe resistivity measurement device calibration process).

For example, for resistivity measurements using the four-probe method, a four-probe resistivity measuring device can be calibrated and corrected using a standard wafer that has traceability to seven levels of resistivity standard materials (SRMs: Standard Reference Materials) such as SRM2541 (0.01 Ω·cm) to SRM2547 (200 Ω·cm) provided by NIST (National Institute of Standards and Technology).

In this example, to calibrate the four-probe resistivity measurement device, the resistivity standard materials such as SRM2541 to SRM2547 are measured with the four-probe resistivity measurement device, and it is confirmed that the measurement results are within the control standards. In addition, to make corrections, the resistivity standard materials are measured with the four-probe resistivity measurement device, the ratio between the measurement results and the standard value assigned to the resistivity standard materials is calculated, and the measurement value obtained by the four-probe resistivity measurement device is multiplied by this ratio.

Next, the resistivity of the PW wafer is measured using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibration process, and the four-probe standard resistivity is assigned (Figure 1 (b) Standard resistivity assignment process).

It is desirable to use a PW wafer that has a resistivity that can be measured by the C-V method and that has been subjected to heat treatment to eliminate oxygen donors. When measuring the PW surface of the PW wafer with the four-probe resistivity measurement device, it is desirable to measure the resistivity multiple times and use the average value as the standard value in order to ensure the accuracy of the four-probe standard resistivity. When the PW wafer is ground (e.g., surface grinding) to form a ground surface and the ground surface is measured with the four-probe resistivity measurement device, the measurement accuracy of the four-probe standard resistivity is improved compared to when the PW surface is measured. Hereinafter, a PW wafer that has been assigned a value for the four-probe standard resistivity may be referred to as a standard PW.

Then, the standard PW is subjected to CV measurement (Figure 1(c) Standard PW CV measurement process). If the surface has been ground in the PW standard resistivity rating process (Figure 1(b)), another PW wafer having the same resistivity is subjected to CV measurement. If a high resistance region appears in the surface layer of the impurity concentration profile or resistivity profile during the CV measurement, it is desirable to heat treat the standard PW for 10 to 60 minutes in a hydrogen atmosphere at 250°C to 1150°C before subjecting it to CV measurement.

Then, by comparing the C-V resistivity obtained by measuring the standard PW by the C-V method with the four-probe standard resistivity (Fig. 1(d) - comparison process between the C-V measurement value of the standard PW and the four-probe standard resistivity), a first conversion formula is obtained for converting the C-V measurement value of the PW wafer into a four-probe resistivity that is traceable to an international standard (Fig. 1(e)).

The first conversion formula obtained in this manner can be applied to EPWs using high resistivity substrates, such as P ^- type PWs, N ^- type PWs, P/P ^- type silicon epitaxial wafers (hereinafter sometimes simply referred to as "EPWs") and N/N ^- type EPWs, but cannot be applied to EPWs using low resistivity substrates, such as P/P ⁺ type EPWs and N/N ⁺ type EPWs. This is because the contact resistance between the wafer stage that fixes the wafer during CV measurement and the backside of the EPW differs depending on whether the backside of the EPW is a high resistivity substrate or a low resistivity substrate, and this difference affects the measurement results of the CV resistivity.

Therefore, a high resistivity substrate EPW and a low resistivity substrate EPW with the same dopant concentration of silicon epitaxial layer (hereinafter sometimes simply referred to as "epilayer") are prepared, and the C-V resistivities of the epilayers of these EPWs are compared to determine a second conversion formula for converting the epilayer C-V resistivity of the low resistivity substrate EPW to the epilayer C-V resistivity of the high resistivity substrate EPW (Figure 2). That is, Figure 2 is a schematic process diagram showing the general process for determining the second conversion formula in the resistivity measurement method of the present invention.

In FIG. 2, first, a high resistivity PW wafer having a resistivity measurable by the C-V method and a low resistivity PW wafer having a resistivity of 0.02 Ω·cm or less are prepared (FIG. 2(a) PW wafer preparation process for substrate). Here, the resistivity of the high resistivity substrate having a resistivity measurable by the C-V method is, for example, 0.1 Ω·cm or more and 1000 Ω·cm or less.

Next, on each of the high resistivity PW wafer and the low resistivity PW wafer, a silicon epitaxial layer having substantially the same resistivity and conductivity type as the high resistivity PW wafer is epitaxially grown under the same growth conditions with the same dopant concentration. This prepares a high resistivity substrate EPW and a low resistivity substrate EPW (Figure 2(b) Comparative EPW preparation process).

Then, the epitaxial layer of the low resistivity substrate EPW and the epitaxial layer of the high resistivity substrate EPW are subjected to C-V measurement (FIG. 2(c) C-V measurement process of comparative EPW). Furthermore, the C-V resistivity of the epitaxial layer of the low resistivity substrate EPW and the epitaxial layer of the high resistivity substrate EPW are compared (FIG. 2(d) C-V resistivity comparison process of the EP layer of the low resistivity substrate EPW and the EP layer of the high resistivity substrate EPW).

Then, a second conversion formula is obtained for converting the C-V resistivity of the epilayer of the low resistivity substrate EPW to the C-V resistivity of the epilayer of the high resistivity substrate EPW (FIG. 2(e)). The high resistivity substrate EPW, in which the resistivity of the epilayer and the substrate are the same, is substantially the same as PW. Therefore, the second conversion formula can also be used to convert the C-V resistivity of the epilayer of the low resistivity substrate EPW to the C-V resistivity of PW.

As mentioned above, the contact resistance between the wafer stage to which the EPW is fixed during C-V measurement and the back surface of the EPW differs depending on whether the back surface of the EPW is a high resistivity substrate or a low resistivity substrate, and this difference affects the measurement results of the C-V resistivity. Furthermore, even with the same high resistivity substrate or high resistivity PW, the contact resistance with the wafer stage differs between, for example, 1 Ω·cm and 100 Ω·cm.

Therefore, when performing C-V measurements with a high resistivity substrate EPW or high resistivity PW (hereinafter sometimes referred to as a high resistivity wafer) fixed to a wafer stage, it is desirable to perform the C-V measurements while sandwiching a conductive cushion between the high resistivity wafer and the wafer stage. In this way, even for high resistivity wafers with different resistivities, the contact resistance to the wafer stage is kept constant, which is expected to improve the accuracy of the first and second conversion formulas.

Figure 3 shows a schematic diagram of a C-V measurement device 10 (hereinafter sometimes simply referred to as device 10) used when performing C-V measurements with a conductive cushion 7 sandwiched between a high resistivity wafer 3 and a wafer stage 6.

The high resistivity wafer 3 is formed by vapor-phase growth of a silicon epitaxial layer 2 on a high resistivity substrate 1, and can be applied to either P/ ^P- or N/N- ^, but for convenience of explanation, the case of P/ ^P- is illustrated. Furthermore, the device 10 has a back electrode, but can also be applied to a front electrode.

As a pretreatment for the C-V measurement, the high resistivity wafer 3 is treated with, for example, hydrofluoric acid (HF) to remove the oxide film formed on the surface. Next, a metal electrode 4 is formed at a desired position on the surface of the silicon epitaxial layer 2. The metal for the metal electrode 4 is preferably samarium (Sm) when the silicon epitaxial layer 2 is P-type, and is preferably gold (Au) when the silicon epitaxial layer 2 is N-type. When mercury (Hg) is used as the metal electrode 4, it can be used for both P-type and N-type.

Next, a conductive cushion 7 is sandwiched between the second main surface (main back surface) of the HF-treated high resistivity wafer 3 and the measurement stage 6 of the C-V measurement device 10, and a high-frequency voltage is applied to the metal electrode 4 that is in contact with the first main surface of the high resistivity wafer 3 to perform C-V measurement.

The conductive cushion 7 is preferably silicone rubber with a resistivity of 1 Ωcm or less that is kneaded with silver or carbon. The conductive cushion 7 is used to maintain a good constant resistivity for the ohmic contact between the second main surface of the high resistivity wafer 1 and the measurement stage 6 of the C-V measurement device 10.

When the conductive cushion 7 is not used, the magnitude of the resistance formed between the second main surface of the high resistivity wafer 3 and the measurement stage 6 varies depending on the resistivity of the high resistivity substrate 1. It also varies depending on the strength of the suction between the back surface of the high resistivity wafer 3 and the measurement stage 6. The magnitude of the resistance formed between the second main surface of the high resistivity wafer 3 and the measurement stage 6 is smaller if the suction force is strong, and is larger if the suction force is weak.

When a reverse bias voltage is applied to the metal electrode 4 in contact with the first main surface of the high resistivity wafer 3, a depletion layer is formed near the surface of the EP layer 2 in contact with the metal electrode 4, and expands.

The depletion layer width W can be calculated by the following formula:
(Formula 1)
W=Aε ₀ ε _Si /C
Here, A is the area of the metal electrode 4, ε ₀ is the vacuum dielectric constant, ε _Si is the relative dielectric constant of silicon, and C is the electrostatic capacitance formed by the depletion layer of the epitaxial layer 2.

The dopant concentration N(W) at the depletion layer width W is calculated from the following formula:
(Formula 2)
N(W)=2/(qε ₀ ε _Si A ² )*{d(C ^-2 )/dV} ^-1
Here, q is the charge of the electron.

The dopant concentration N(W) can be output as a dopant concentration profile once a correspondence list with the depletion layer width W (depth) is created. In addition, the dopant concentration N(w) can also be output as a resistivity profile once a correspondence list with the depletion layer width (depth) is created after it has been converted to resistivity (SEMI converted resistivity) using SEMI MF723-0307.

By applying the first conversion formula to the SEMI converted resistivity or a resistivity obtained by performing a predetermined conversion on the SEMI converted resistivity, the measurement result of the C-V resistivity of the high resistivity wafer 3 can be converted into a four-probe resistivity that is traceable to NIST.

When the object of CV measurement does not include a high resistivity substrate 1, that is, when it is a low resistivity substrate EPW such as a P/P ⁺ type EPW or an N/N ⁺ type EPW, there is no need to use the conductive cushion 7. The CV resistivity of an epitaxial layer (hereinafter, sometimes referred to as an "EP layer") formed on a low resistivity substrate EPW can also be measured as shown in FIG. 3, except that the conductive cushion 7 is not used. Then, the measurement result of the CV resistivity of the silicon epitaxial layer to be measured can be converted into a four-probe resistivity traceable to NIST by performing conversion (FIG. 4(b)) using the second conversion formula and conversion (FIG. 4(c)) using the first conversion formula for the SEMI converted resistivity or the CV resistivity measurement result of the EP layer formed on the low resistivity substrate EPW, which is obtained by performing a predetermined conversion on the SEMI converted resistivity (FIG. 4(a)).

Examples of specific conversions applied to SEMI converted resistivity include conversions to match other C-V method resistivity measuring devices, conversions to match customer measured values (customer conversions), and conversions to correct bias from the standard value.

[Second embodiment]
A second embodiment of the present invention will be described below with reference to the drawings.
In the first embodiment, the resistivity of a PW wafer is measured using a calibrated four-probe resistivity measurement device, and the four-probe standard resistivity is assigned. In contrast, in the second embodiment, the four-probe standard resistivity is assigned to a silicon single crystal wafer (hereinafter, sometimes simply referred to as LW surface) whose main surface is a lapped surface (hereinafter, sometimes simply referred to as LW surface), a silicon single crystal wafer (hereinafter, sometimes simply referred to as ground surface), or a silicon single crystal wafer (hereinafter, sometimes simply referred to as CW surface) whose main surface is a chemically etched surface (hereinafter, sometimes simply referred to as CW surface).

Figure 5 is a schematic diagram showing the steps of a resistivity measurement method according to a second embodiment of the present invention. First, a four-probe resistivity measurement device is calibrated using a standard wafer that is traceable to NIST (Figure 5(a) Four-probe resistivity measurement device calibration step).

Next, four-probe standard resistivity is assigned to silicon single crystal wafers whose main surface is an LW surface, a ground surface, or a CW surface (Figure 5(b) Standard resistivity assignment process). This reduces the variability in repeated measurements compared to when a PW wafer whose main surface is a PW surface is measured using the four-probe method. CW surfaces include high-brightness flat ground surfaces.

When oxygen in silicon single crystals is subjected to heat treatment at around 450°C, several atoms come together and release one electron, generating a donor. For this reason, it is desirable to use crystals with a low oxygen concentration for the silicon single crystal wafers used in the four-probe standard resistivity determination. It is also desirable to perform a heat treatment aimed at eliminating oxygen donors (donor killer heat treatment) before the four-probe standard resistivity determination.

Next, at least the first main surface of the priced silicon single crystal wafer is processed to form a PW wafer (FIG. 5(c) processing step). If the main surface of the wafer is the LW surface, etching, chemical mechanical polishing (polishing), etc. are performed to form a PW wafer. Furthermore, the PW wafer is washed to clean the PW surface. For example, a combination of ammonia/hydrogen peroxide solution, hydrochloric acid/hydrogen peroxide solution, ozone water, and hydrofluoric acid are used for the washing.

When a PW wafer is cleaned, hydrogen is introduced into the PW wafer, which increases the resistivity of the surface layer of the PW wafer. As a countermeasure, the cleaned PW wafer is heat-treated at a temperature of 250°C or higher and 1150°C or lower. The heat-treated standard PW prepared in this way is used for C-V measurement.

The process from this standard PW C-V measurement process (FIG. 5(d)) onwards is the same as the process from the C-V measurement process described in the first embodiment (FIG. 1(c) C-V measurement process for standard PW) onwards.

By performing the four-probe standard resistivity determination on silicon single crystal wafers whose main surface is an LW surface, a ground surface, or a CW surface, the variation in repeated measurements is smaller than when measuring PW wafers whose main surface is a PW surface. As a result, more accurate first and second conversion formulas can be obtained, so that the C-V resistivity measurement results of the EP layer formed on the low resistivity substrate EPW can be converted to four-probe resistivity with greater accuracy.

The present invention will be specifically described below using examples and comparative examples, but the present invention is not limited to these. Note that the reference numbers in the following description of the examples correspond to the reference numbers shown in Figure 3.

[Example 1]
First, as substrate PW wafers for determining the second conversion formula, five PW wafers with a diameter of 300 mm, P type, <100> were prepared, each having five levels of high resistivity PW wafers with resistivity of 1 to 100 Ω cm measurable by the CV method, and five low resistivity PW wafers with a resistivity of 0.015 Ω cm.

Next, on each of the high resistivity PW wafer 1 and the low resistivity PW wafer 1, a silicon epitaxial layer 2 having substantially the same resistivity and the same conductivity type as the high resistivity PW wafer was epitaxially grown under the same growth conditions of dopant concentration. For example, on each of the high resistivity P-type PW wafer 1 having a resistivity of 1 Ω·cm and the low resistivity P-type PW wafer 1 having a resistivity of 0.015 Ω·cm, a P-type silicon epitaxial layer 2 having a resistivity of approximately 1 Ω·cm was epitaxially grown under the same growth conditions of dopant concentration to form EPW3 (low resistivity substrate EPW and high resistivity substrate EPW).

Next, an electrode 4 was formed on the main surface of the EPW3, and the epilayer 2 of each of the EPW3 having the high resistivity PW1 and the EPW3 having the low resistivity PW1 that had been epitaxially grown was subjected to C-V measurements. When measuring the C-V of the epilayer 2 of the high resistivity substrate EPW3, the high resistivity substrate EPW3 was held by suction on the wafer stage 6 with a conductive cushion 7 having a resistivity of 0.9 Ω cm sandwiched between the high resistivity substrate EPW3 and the wafer stage 6, and the measurements were performed.

Then, the C-V resistivity of the epitaxial layer 2 of the low resistivity substrate EPW3 was compared with that of the epitaxial layer 2 of the high resistivity substrate EPW3, and a second conversion formula was obtained for converting the C-V resistivity of the epitaxial layer of the low resistivity substrate EPW to the C-V resistivity of the epitaxial layer of the high resistivity substrate EPW.

Figure 6 shows the ratio of the C-V resistivity of the epitaxial layer of the high resistivity substrate EPW to that of the epitaxial layer of the low resistivity substrate EPW, i.e., the bias amount of resistivity (measured value - standard value) when the second conversion formula is not used, relative to the resistivity converted using the second conversion formula, expressed as a percentage. It can be seen that when the second conversion formula is not used, the resistivity is measured to be about 1% higher at a resistivity level of 10 Ω cm and about 6% higher at a resistivity level of 100 Ω cm.

The definition of "bias (%)" on the vertical axis of FIG. 6 is as follows.
Bias (%) = (measured value - standard value) / standard value x 100 (%)

Furthermore, by comparing the C-V resistivity obtained by measuring a standard PW by the C-V method, which has a value assigned to a four-probe standard resistivity previously obtained by measuring it by the four-probe method, with the above-mentioned four-probe standard resistivity, a first conversion formula was obtained for converting the C-V measurement value of a high resistivity PW wafer into a four-probe resistivity that is traceable to an international standard.

On the other hand, a silicon epitaxial wafer (EPW) manufactured using a low resistivity substrate with a resistivity of 0.015 Ω·cm was prepared as the measurement subject. The resistivity of the silicon epitaxial layer formed on this EPW was measured by C-V measurement, and the SEMI-equivalent resistivity of the silicon epitaxial layer (EP layer) to be measured, which was formed on the low resistivity substrate, was obtained.

Finally, the SEMI-converted resistivity of the silicon epitaxial layer to be measured was converted using the second conversion formula and then the first conversion formula, thereby converting the measurement result of the C-V resistivity of the EP layer to be measured formed on the low resistivity substrate EPW into a four-probe resistivity that is traceable to NIST.

Figure 7 shows a graph comparing the standard four-probe resistivity previously obtained by measurement using the four-probe method with the C-V resistivity measurement results (after conversion) of the EP layer being measured, which has been converted into a four-probe resistivity traceable to NIST. As shown in Figure 7, according to the present invention, the four-probe resistivity and the C-V resistivity measurement results of the EP layer being measured are substantially the same value.

That is, according to the present invention, it is possible to convert the C-V resistivity of the silicon epitaxial layer to be measured, which is formed on a silicon epitaxial wafer manufactured using a low resistivity substrate, into a four-probe resistivity that is traceable to an international standard such as NIST. In other words, it is possible to provide a resistivity measurement method with a new resistivity conversion that is performed when tracing the C-V method to an international standard such as NIST using a PW wafer.

In addition to the conversion using the first conversion formula that compares the C-V resistivity of the standard PW with the four-probe standard resistivity, the present invention can be used to convert the C-V resistivity of the EP layer formed on an EPW manufactured using a low resistivity substrate into a four-probe resistivity that is traceable to international standards such as NIST by performing a conversion using a second conversion formula that is obtained by comparing the C-V resistivity of the EP layer for a high resistivity substrate EPW and a low resistivity substrate EPW.

The present invention is not limited to the above-described embodiment. The above-described embodiment is merely an example, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits similar effects is included within the technical scope of the present invention.

1...High resistivity substrate, 2...Silicon epitaxial layer, 3...Epitaxial wafer, 4...Metal electrode, 6...Wafer stage, 7...Conductive cushion, 10...C-V measuring device.

Claims (11)

A resistivity measurement method for measuring the resistivity of a silicon epitaxial layer to be measured, which is formed on a silicon epitaxial wafer manufactured using a low resistivity substrate having a resistivity of 0.02 Ω cm or less, by a CV method, comprising:
The resistivity of the silicon epitaxial layer to be measured is measured by a CV method to obtain a SEMI-converted resistivity or a resistivity obtained by performing a predetermined conversion on the SEMI-converted resistivity.
A conversion according to a first conversion formula obtained by comparing a CV resistivity obtained by measuring a standard polished wafer, to which a four-probe standard resistivity is assigned, by a CV method with the four-probe standard resistivity;
Conversion by a second conversion formula obtained by comparing the C-V resistivity of a silicon epitaxial layer of a high resistivity substrate silicon epitaxial wafer prepared using a high resistivity substrate having a resistivity measurable by a C-V method and a silicon epitaxial layer of a low resistivity substrate silicon epitaxial wafer prepared using a low resistivity substrate having a resistivity of 0.02 Ω cm or less;
and obtaining a four-probe resistivity of the silicon epitaxial layer to be measured. The four-probe standard resistivity for the standard polished wafer is determined as follows:
a four-probe resistivity measurement device calibration process for calibrating the four-probe resistivity measurement device using a standard wafer that is traceable to an international standard;
a polished wafer standard resistivity rating step of rating a polished wafer to the four-probe standard resistivity using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibrating step;
2. The method for measuring resistivity according to claim 1, further comprising: The resistivity measurement method according to claim 2, characterized in that in the polished wafer standard resistivity rating process, the main surface of the polished wafer is measured with the four-probe resistivity measurement device. The resistivity measurement method according to claim 2, characterized in that in the polished wafer standard resistivity rating process, the polished wafer is ground to produce a ground surface, and the ground surface is measured with the four-probe resistivity measurement device. The resistivity measurement method according to claim 4, characterized in that the grinding is performed by surface grinding. The resistivity measurement method according to any one of claims 2 to 4, characterized in that the polished wafer is one that has been subjected to a heat treatment to eliminate oxygen donors. As the standard polished wafer to which the four-probe standard resistivity is assigned,
a four-probe resistivity measurement device calibration process for calibrating the four-probe resistivity measurement device using a standard wafer that is traceable to an international standard;
a rating step of measuring the resistivity of a silicon single crystal wafer that has been previously subjected to a heat treatment for eliminating oxygen donors, using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibrating step, and rating the four-probe standard resistivity;
A processing step of processing at least a first main surface of the priced silicon single crystal wafer into a polished wafer;
a cleaning step of cleaning the polished wafer;
2. The resistivity measuring method according to claim 1, wherein the resistivity measuring material is a material having a resistance to the electric field of the electric field. The resistivity measurement method according to claim 7, characterized in that the silicon single crystal wafer has a main surface that has been lapped, ground, or chemically etched. The second conversion formula is
a substrate polished wafer preparation step of preparing a high resistivity polished wafer having a resistivity measurable by a CV method and a low resistivity polished wafer having a resistivity of 0.02 Ω cm or less;
an epitaxial wafer preparation step of epitaxially growing a silicon epitaxial layer having the same resistivity and the same conductivity type as that of the high resistivity polished wafer under growth conditions of the same dopant concentration on each of the high resistivity polished wafer and the low resistivity polished wafer, thereby preparing the high resistivity substrate silicon epitaxial wafer and the low resistivity substrate silicon epitaxial wafer;
a CV measurement step of a comparative epitaxial wafer, in which a CV measurement is performed on a silicon epitaxial layer of the low resistivity substrate silicon epitaxial wafer and a silicon epitaxial layer of the high resistivity substrate silicon epitaxial wafer;
a comparison step of comparing the C-V resistivity of the silicon epitaxial layer of the low resistivity substrate silicon epitaxial wafer with that of the silicon epitaxial layer of the high resistivity substrate silicon epitaxial wafer;
The resistivity measurement method according to claim 1, further comprising a second conversion step of converting a measurement result of the CV resistivity of the silicon epitaxial layer formed on the low resistivity substrate into a CV resistivity of a silicon epitaxial layer formed on a silicon epitaxial wafer including a high resistivity substrate by the second conversion formula. The resistivity measurement method according to claim 1, characterized in that, when determining the first conversion formula, the standard polished wafer is heat-treated in a hydrogen atmosphere at 250°C or higher and 1150°C or lower before measuring the resistivity of the standard polished wafer by the C-V method. The resistivity measurement method according to claim 1, characterized in that, when determining the first conversion formula, a high-frequency voltage is applied to the first main surface of the standard polished wafer while a conductive cushion is placed between the second main surface of the standard polished wafer and a measurement stage of a measurement device using the CV method, and the resistivity of the standard polished wafer is measured by the CV method.

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