JP7704449B2 - COMMUNICATION SYSTEM, COMMUNICATION METHOD, AND PROGRAM - Google Patents

Description

The present invention relates to a communication system, a communication method, and a program.

Regarding clock synchronization within a network, the following literature can be cited:

Patent document 1 relates to a method of subordinate synchronization in which, when a failure occurs on one of multiple lines, it does not affect the subordinate synchronization of the other lines.

Patent document 2 relates to a transceiver module that can inexpensively meet the needs for high-speed, short-distance communication.

Patent document 3 relates to a network device used to realize a synchronous network on Ethernet (registered trademark).

JP 2002-033721 A Republished Patent No. 2005/125027 Republished Patent No. 2008/120382

The following analysis is given by the inventor.

In 10GBASE-X XFI interfaces used in routers and other devices, bit errors can occur when data is imported at the connection between a control device such as a CPU and a communication device such as an Ethernet (registered trademark) transceiver, causing packets to be discarded by the receiving device without being recognized correctly. In such cases, the expected communication quality may not be achieved.

The present invention aims to provide a communication system, a communication method, and a program that contribute to improving the rate of data discard by synchronizing the clocks used for transmission and reception.

According to a first aspect of the present invention, there is provided a control device, comprising: one or more clock extraction units each extracting a clock from a first bit of data transmitted from one or more transmitting/receiving devices via each line, and generating a clock synchronized with the transmitted data;
one or more clock divider units that divide the frequency of each of the clocks synchronized with the transmitted data and output each of the divided clocks;
a frequency-divided clock selection unit that selects a frequency-divided clock corresponding to any one of the lines from the one or more frequency-divided clocks and outputs the selected frequency-divided clock;
an asynchronous clock divider that divides the asynchronous clock and generates a divided asynchronous clock;
a phase synchronization unit that generates and outputs a reference clock synchronized with the selected frequency-divided clock based on the selected frequency-divided clock and the frequency-divided asynchronous clock;
and a reference clock multiplier section that multiplies the reference clock and outputs one or more multiplied clocks.

According to a second aspect of the present invention, there is provided a computer including one or more clock extraction units, one or more clock divider units, a divided clock selection unit, an asynchronous clock divider unit, a phase synchronization unit, and a reference clock multiplication unit, comprising:
one or more clock extraction steps for extracting a clock from a leading bit of data transmitted from one or more transmitting/receiving devices via each line to a control device, and generating a clock synchronized with the transmitted data;
one or more clock dividing steps for dividing each of the clocks synchronized with the transmitted data and outputting each divided clock;
a frequency-divided clock selection step of selecting a frequency-divided clock corresponding to any one of the lines from the one or more frequency-divided clocks and outputting the selected frequency-divided clock;
a frequency-dividing asynchronous clock to generate a frequency-divided asynchronous clock;
a phase synchronization step of generating and outputting a reference clock synchronized with the selected frequency-divided clock based on the selected frequency-divided clock and the frequency-divided asynchronous clock;
A communication method can be provided, which includes a reference clock multiplying step of multiplying the reference clock to output one or more multiplied clocks. This method is associated with a specific machine, that is, a computer, which performs the communication method.

According to a third aspect of the present invention, there is provided a computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit,
one or more clock extraction processes for extracting a clock from the first bit of data transmitted from one or more transmitting/receiving devices via each line for a control device, and generating a clock synchronized with the transmitted data;
one or more clock division processes for dividing a frequency of each of the clocks synchronized with the transmitted data and outputting each of the divided clocks;
a divided clock selection process for selecting a divided clock corresponding to any one of the lines from the one or more divided clocks and outputting the selected divided clock;
an asynchronous clock division process that divides the asynchronous clock to generate a divided asynchronous clock;
a phase synchronization process for generating and outputting a reference clock synchronized with the selected frequency-divided clock based on the selected frequency-divided clock and the frequency-divided asynchronous clock;
It is possible to provide a program for executing a reference clock multiplication process that multiplies the reference clock and outputs one or more multiplied clocks.

These programs can be recorded on a computer-readable storage medium. The storage medium can be a non-transient medium such as a semiconductor memory, a hard disk, a magnetic recording medium, or an optical recording medium. The present invention can also be embodied as a computer program product.

The present invention provides a communication system, a communication method, and a program that contribute to improving the rate of data discard by synchronizing the clocks used for transmission and reception.

FIG. 1 is a diagram illustrating an example of a configuration of a communication system according to an embodiment of the present invention. 1 is a diagram illustrating an example of a configuration of a communication system according to a first exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a configuration of a clock generating unit of the communication system according to the first exemplary embodiment of the present invention. FIG. 11 is a diagram illustrating an example of a configuration of a clock extraction unit of a communication system according to a second exemplary embodiment of the present invention. FIG. 11 is a diagram illustrating an example of an operation of a clock extraction unit in the communication system according to the second exemplary embodiment of the present invention. FIG. 13 is a diagram illustrating an example of a configuration of a clock generating unit of a communication system according to a third exemplary embodiment of the present invention. FIG. 2 is a diagram showing a configuration of a computer that constitutes the communication system of the present invention.

First, an overview of one embodiment of the present invention will be described with reference to the drawings. Note that the reference symbols for the drawings given in this overview are given for convenience as an example to aid understanding, and are not intended to limit the present invention to the illustrated form. Furthermore, the connection lines between blocks in the drawings and the like referred to in the following description include both bidirectional and unidirectional lines. Unidirectional arrows are used to diagrammatically indicate the flow of the main signal (data), and do not exclude bidirectionality.

FIG. 1 is a diagram showing an example of the configuration of a communication system according to an embodiment of the present invention. Referring to FIG. 1, the communication system 100 includes one or more clock extraction units 1201 to 120n and a clock generation unit 130, and the clock generation unit 130 includes one or more clock division units 1401 to 140n, a divided clock selection unit 150, an asynchronous clock division unit 160, a phase synchronization unit 170, and a reference clock multiplication unit 180.

The transmitting/receiving device 1101 is connected to the control device 190 via lines 1011 and 1021, the transmitting/receiving device 110n is connected to the control device 190 via lines 101n and 102n, the clock extraction unit 1201 acquires data 101 transmitted via line 1011, and the clock extraction unit 120n acquires data 10n transmitted via line 101n.

The clock extraction units 1201-120n extract the clock from the first bit of the data 101-10n transmitted from one or more transmitting/receiving devices 1101-110n to the control device 190 via the respective lines 1011-101n, and generate clocks 211-21n synchronized with the transmitted data 101-10n. The lines 1011-101n and lines 1021-102n are, for example, multiple Ethernet (registered trademark) lines used in routers, etc.

One or more clock divider units 1401 to 140n of the clock generation unit 130 divide the clocks 211 to 21n synchronized with the transmitted data and output the respective divided clocks.

The divided clock selection unit 150 of the clock generation unit 130 selects a divided clock corresponding to any one of the lines 1011 to 101n from one or more divided clocks, and outputs the selected divided clock.

The asynchronous clock divider 160 of the clock generator 130 divides the asynchronous clock and generates a divided asynchronous clock.

The phase synchronization unit 170 of the clock generation unit 130 generates and outputs a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock.

The reference clock multiplier 180 of the clock generator 130 multiplies the reference clock and outputs one or more multiplied clocks.

The reference clock multiplier 180 of the clock generator 130 supplies the multiplied clock to the transmitting/receiving devices 1101-110n and the control device 190, which are used by the transmitting/receiving devices 1101-110n and the control device 190 for transmission and reception.

As described above, according to one embodiment of the present invention, a multiplied clock can be generated that is synchronized with the transmitted data and is used by the transmitting/receiving device and the control device for transmission and reception.

Furthermore, one embodiment of the present invention can provide each device with a clock of any frequency that is synchronized with the data transmitted on any line, or a clock of any frequency that is independent of the data transmitted on any line.

Furthermore, according to one embodiment of the present invention, functions related to sending and receiving data via lines within the device can be operated based on a synchronized clock, thereby reducing bit errors and improving the rate of data discard.

Therefore, according to one embodiment of the present invention, it is possible to provide a communication system, a communication method, and a program that contribute to improving the occurrence rate of data discard by synchronizing the clocks used for transmission and reception.

[First embodiment]
Next, a communication system according to a first embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a diagram showing an example of the configuration of the communication system according to the first embodiment of the present invention. Fig. 3 is a diagram showing an example of the configuration of a clock generating unit of the communication system according to the first embodiment of the present invention. In Fig. 2 and Fig. 3, components with the same reference numerals as those in Fig. 1 indicate the same components.

Referring to FIG. 2, the communication system 100 includes clock extraction units 1201-120n and a clock generation unit 130. Also, referring to FIG. 3, the clock generation unit 130 includes clock division units 1401-140n, a divided clock selection unit 150, an asynchronous clock division unit 160, a phase synchronization unit 170, and a reference clock multiplication unit 180.

The clock extraction units 1201-120n extract clocks from the first bit of data 101-10n transmitted from one or more transmitting/receiving devices 1101-110n via lines 1011-101n for the control device 190, generate clocks 211-21n synchronized with the transmitted data 101-10n, and supply them to the clock generation unit 130. The lines 1011-101n and lines 1021-102n are, for example, multiple Ethernet (registered trademark) lines used in routers. The clock extraction reference clocks (clocks that serve as a reference for clock extraction) 201-20n are supplied to the clock extraction units 1201-120n by the clock generation unit 130. For example, in the case of a 10GBASE-X XFI interface, both the clocks 211-21n synchronized with the transmitted data and the clock extraction reference clocks 201-20n are 156.25 MHz. That is, the clock extraction units 1201-1201n for each line 1011-101n transmit the clocks 211-21n synchronized with the transmitted data, which are extracted and generated based on the clock extraction reference clocks 201-20n, to the clock generation unit 130.

Referring to FIG. 3, clocks 211-21n synchronized with the transmitted data generated by clock extraction units 1201-120n shown in FIG. 2 are supplied to clock division units 1401-140n of clock generation unit 130, and clock division units 1401-140n divide the clock by, for example, 25 to generate divided clocks 311-31n with a frequency of 6.25 MHz.

From the divided clocks 311 to 31n that are respectively divided by the clock dividers 1401 to 140n, the divided clock selection unit 150 selects the divided clock 151 selected for any one of the lines.

The asynchronous clock 200, which is generally supplied from a crystal oscillator or the like, is divided by the asynchronous clock divider 160 to generate the asynchronous divided clock 161 of 6.25 MHz.

The divided clock 151 selected by the divided clock selection unit 150 and the asynchronous divided clock 161 divided by the asynchronous clock division unit 160 are input to the phase synchronization unit 170, and the phase locked loop (PLL) in the phase synchronization unit 170 uses the asynchronous divided clock 161 divided by the asynchronous clock division unit 160 to generate a reference clock 171 synchronized with the selected divided clock 151 corresponding to the selected line.

The phase synchronization unit 170 may be configured, for example, by a digital phase-locked loop (DPLL). The DPLL process may involve performing phase adjustment on the asynchronous divided clock 161 divided by the asynchronous clock divider unit 160, generating a clock of the same phase as the divided clock 151 selected by the divided clock selection unit 150, and outputting the generated clock as the reference clock 171. Another DPLL process may involve generating multi-phase clocks with different multiplied phases from the asynchronous divided clock 161 divided by the asynchronous clock divider unit 160, selecting a multiplied clock with an optimal phase, such as a multiplied clock with the closest phase, for the divided clock 151 selected by the divided clock selection unit 150, and dividing the multiplied clock with the selected phase to output it as the reference clock 171.

The reference clock multiplier 180 multiplies the clock extraction reference clocks 201-20n supplied to the clock extraction units 1201-120n, the clocks 301-30n input to the transmission/reception devices 1101-110n for each communication, and the clock 400 input to the control device 190 from the reference clock 171 output by the phase synchronization unit 170 to the required frequencies, and outputs them. At this time, the clock extraction reference clocks 201, 202, 20n, the clocks 301, 302, 30n input to the transmission/reception devices 1101-110n, the clock 400 input to the control device 190, and other required clocks are generally clocks of frequencies that can be generated by multiplying the 6.25 MHz reference clock 171.

As described above, according to the first embodiment of the present invention, it is possible to generate a multiplied clock that is synchronized with the transmitted data and is used by the transmitting/receiving device and the control device for transmission and reception. Therefore, according to the first embodiment of the present invention, it is possible to provide a communication system, a communication method, and a program that contribute to making it possible to improve the occurrence rate of data discard by synchronizing the clocks used for transmission and reception.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to the drawings. Fig. 4 is a diagram showing an example of the configuration of a clock extraction unit of a communication system according to the second embodiment of the present invention. Fig. 5 is a diagram showing an example of the operation of the clock extraction unit of a communication system according to the second embodiment of the present invention. In Fig. 4, components with the same reference numerals as those in Figs. 1 to 3 indicate the same components.

Referring to FIG. 4, the clock extraction unit 1201 includes a 66-fold multiplier 401 that generates a multiplied clock 501 by multiplying the clock extraction reference clock 201 by 66, and a clock recovery unit 402 that receives the multiplied clock 501 and data 101 transmitted from the transmitting/receiving device 1101 on the line 1011 as input, and outputs a clock 211 that is generated by extracting it from these and synchronized with the transmitted data. The clock 211 synchronized with the transmitted data is sent to a clock divider 1401 that divides it by 66 to generate a divided clock 311, and the divided clock 311 is generated.

Next, an example of the operation of the clock extraction unit 1201 of the second embodiment of the present invention will be described. The portion surrounded by the dashed line 600 in FIG. 5 shows the operation of the clock recovery. Referring to FIG. 5, there are shown the clock extraction reference clock 201, the multiplied clock 501 obtained by multiplying the clock extraction reference clock, data 101 transmitted from the transmitting/receiving device 1101 over the line 1011 (received data of the clock extraction unit 1201), the clock 211 synchronized with the transmitted data extracted and generated by the clock recovery unit 402 based on the multiplied clock 501, and the divided clock 311 obtained by dividing the clock 211 synchronized with the transmitted data by 66 by the clock divider unit 1401.

The clock recovery unit 402 extracts and generates a clock 211 synchronized with the transmitted data 101 from the multiplied clock 501 obtained by multiplying the clock extraction reference clock 201. The clock recovery operation may, for example, be a method of performing phase adjustment from the multiplied clock 501 to generate a clock with the same phase as the transmitted data 101, and outputting the generated clock as a clock 211 synchronized with the transmitted data 101. Another method may be to generate multi-phase clocks with different phases from the multiplied clock 501 obtained by multiplying the reference clock, select a clock with an optimal phase, such as a clock with the closest phase, for the transmitted data 101, and output it as a clock 211 synchronized with the transmitted data.

As described above, according to the second embodiment of the present invention, a clock extraction unit 1201 can be configured to extract a clock synchronized with the transmitted data from the first bit of the data transmitted through each line.

[Third embodiment]
Next, a third embodiment of the present invention will be described with reference to the drawings. Fig. 6 is a diagram showing an example of the configuration of a clock generating unit 130 of a communication system according to the third embodiment of the present invention. In Fig. 6, components with the same reference numerals as those in Figs. 1 to 3 indicate the same components.

The third embodiment of the present invention is an embodiment in which a phase-locked loop (PLL) is formed by an asynchronous clock divider unit 160 and a phase synchronization unit 170.

Referring to FIG. 6, the phase synchronization unit 170 includes a phase comparator 601 that compares the phase of the divided clock 151 selected by the divided clock selection unit 150 with the phase of the asynchronous clock 200 divided by the asynchronous clock division unit 160, a low-pass filter (LPF) 602 that receives the output of the phase comparator 601, and a voltage-controlled oscillator 603, such as a VCXO (voltage-controlled crystal oscillator), that receives the output of the low-pass filter 602, and the output of the voltage-controlled oscillator 603 is supplied to the asynchronous clock division unit 160 as the asynchronous clock 200, and the divided asynchronous clock 200 is output as the reference clock 171. When the PLL starts operating, the asynchronous clock 200 is a clock that is asynchronous with the selected divided clock 151 and is generated by dividing the output of the voltage-controlled oscillator 603 by the asynchronous clock divider 160. However, when the PLL synchronizes in phase with the selected divided clock 151, the reference clock 171 becomes a clock that is phase-synchronized with the selected divided clock 151.

As described above, according to the third embodiment of the present invention, it is possible to configure a phase synchronization unit 170 of the third embodiment that operates differently from the phase synchronization unit 170 described in the first embodiment.

Although each embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiments, and further modifications, substitutions, and adjustments can be made without departing from the basic technical concept of the present invention. For example, the network configurations, element configurations, and message expression formats shown in the drawings are examples to aid in understanding the present invention, and are not limited to the configurations shown in these drawings. In addition, "A and/or B" is used to mean at least either A or B.

The procedures shown in the first to third embodiments can be realized by a program that causes a computer (9000 in FIG. 7) that functions as the communication system of the present invention to function as a communication system. Such a computer is exemplified by a configuration including a CPU (Central Processing Unit) 9010, a communication interface 9020, a memory 9030, and an auxiliary storage device 9040 in FIG. 7. That is, the CPU 9010 in FIG. 7 executes a control program for the communication system, and performs an update process for each calculation parameter stored in the auxiliary storage device 9040, etc.

The memory 9030 is a RAM (Random Access Memory), a ROM (Read Only Memory), etc.

In other words, each part (processing means, function) of the communication system shown in the first to third embodiments can be realized by a computer program that causes the processor of the computer to execute each of the above-mentioned processes using its hardware.

Finally, preferred embodiments of the present invention will be summarized.
[First embodiment]
(See the communication system according to the first aspect above)
[Second embodiment]
In the communication system according to the first aspect, it is preferable that the clock extraction section executes clock data recovery based on the multiplied clock output by the reference clock multiplication section.
[Third embodiment]
In the communication system according to the first aspect, it is preferable that the phase synchronization unit is a digital phase-locked loop (DPLL).
[Fourth embodiment]
In the communication system described in the first aspect, it is preferable that the phase synchronization unit includes a phase comparator that compares the phase of the selected divided clock with the phase of the divided asynchronous clock, a low-pass filter that receives the output of the phase comparator, and a voltage-controlled oscillator that receives the output of the low-pass filter, and supplies the output of the voltage-controlled oscillator to the asynchronous clock division unit as the asynchronous clock, and outputs the divided asynchronous clock as the reference clock.
[Fifth embodiment]
In the communication system described in the first aspect, it is preferable that the reference clock multiplier unit supplies to the transmitting/receiving device and the control device the multiplied clock used by the transmitting/receiving device and the control device for transmission and reception.
[Sixth embodiment]
In the communication system according to the first aspect, it is preferable that the line is an Ethernet (registered trademark) line.
[Seventh embodiment]
(See the second aspect of the communication method above.)
[Eighth embodiment]
In the communication method according to the seventh aspect, it is preferable that, in the clock extraction step, the computer executes clock data recovery based on the multiplied clock.
[Ninth Form]
(See the third perspective program above)
[Tenth Mode]
The program according to a ninth aspect preferably causes the computer to execute clock data recovery based on the multiplied clock in the clock extraction process.
The seventh and ninth embodiments can be expanded into the third to sixth embodiments in the same manner as the first embodiment.

The disclosures of the above patent documents are incorporated herein by reference. Within the framework of the entire disclosure of the present invention (including the scope of claims), and further based on the basic technical ideas, modifications and adjustments of the embodiments and examples are possible. Furthermore, within the framework of the disclosure of the present invention, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes various modifications and corrections that a person skilled in the art would be able to make in accordance with the entire disclosure, including the scope of claims, and the technical ideas. In particular, with regard to the numerical ranges described in this document, any numerical value or subrange included within the range should be interpreted as being specifically described even if not otherwise specified. Furthermore, the disclosures of the above cited documents, when necessary, in accordance with the spirit of the present invention, may be used in part or in whole in combination with the disclosures of this document as part of the disclosure of the present invention, and are considered to be included in the disclosures of this application.

100 Communication systems 101 to 10n Transmitted data 1011, 1012, 101n, 1021, 1022, 102n Lines 1101, 1102, 110n Transmitting/receiving device 130 Clock generating section 1201, 1202, 120n Clock extraction section 1401, 1402, 140n Clock dividing section 150 Divided clock selection section 151 Selected divided clock 160 Asynchronous clock dividing section 161 Asynchronous divided clock 170 Phase synchronization section 171 Reference clock 180 Reference clock multiplier section 190 Control device 200 Asynchronous clock 201, 202, 20n Clock extraction reference clock 211, 212, 21n Clocks synchronized with transmitted data 301, 302, 30n, 400 Clocks 311, 312, 31n Divided clock 401 66x multiplier 402 Clock recovery unit 501 Multiplied clock 601 Phase comparator 602 Low pass filter (LPF)
603 Voltage controlled oscillator 9000 Computer 9010 CPU
9020 Communication interface 9030 Memory 9040 Auxiliary storage device

Claims (9)

one or more clock extraction units for extracting a clock from a leading bit of data transmitted from one or more transmitting/receiving devices via each line for the control device, and generating a clock synchronized with the transmitted data;
one or more clock divider units that divide the frequency of each of the clocks synchronized with the transmitted data and output each of the divided clocks;
a frequency-divided clock selection unit that selects a frequency-divided clock corresponding to any one of the lines from the one or more frequency-divided clocks and outputs the selected frequency-divided clock;
an asynchronous clock divider that divides the asynchronous clock and generates a divided asynchronous clock;
a phase synchronization unit that generates and outputs a reference clock synchronized with the selected frequency-divided clock based on the selected frequency-divided clock and the frequency-divided asynchronous clock, the phase synchronization unit generating multiphase clocks having different phases by multiplying the frequency-divided asynchronous clock, selecting the clock having the closest phase to the selected frequency-divided clock, dividing the selected clock having the closest phase, and outputting the clock as the reference clock;
a reference clock multiplier unit that multiplies the reference clock and outputs one or more multiplied clocks. The communication system according to claim 1, wherein the clock extraction unit performs clock data recovery based on the multiplied clock output by the reference clock multiplication unit. The communication system according to claim 1, wherein the phase synchronization unit is a digital phase-locked loop (DPLL). The communication system according to claim 1, wherein the reference clock multiplier supplies the multiplied clock to the transmitting/receiving device and the control device, the multiplied clock being used by the transmitting/receiving device and the control device for transmission and reception. The communication system according to claim 1, wherein the line is an Ethernet (registered trademark) line. a computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit,
one or more clock extraction steps for extracting a clock from a leading bit of data transmitted from one or more transmitting/receiving devices via each line to a control device, and generating a clock synchronized with the transmitted data;
one or more clock dividing steps for dividing each of the clocks synchronized with the transmitted data and outputting each divided clock;
a frequency-divided clock selection step of selecting a frequency-divided clock corresponding to any one of the lines from the one or more frequency-divided clocks and outputting the selected frequency-divided clock;
a frequency-dividing asynchronous clock to generate a frequency-divided asynchronous clock;
a phase synchronization step of generating and outputting a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock, the phase synchronization step generating multi-phase clocks having different phases by multiplying the divided asynchronous clock, selecting the clock having the closest phase to the selected divided clock, dividing the selected clock having the closest phase, and outputting it as the reference clock;
A communication method comprising a reference clock multiplying step of multiplying the reference clock and outputting one or more multiplied clocks. 7. The communication method according to claim 6 , wherein said computer executes clock data recovery based on said multiplied clock in said clock extraction step. A computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit,
one or more clock extraction processes for extracting a clock from the first bit of data transmitted from one or more transmitting/receiving devices via each line for a control device, and generating a clock synchronized with the transmitted data;
one or more clock division processes for dividing a frequency of each of the clocks synchronized with the transmitted data and outputting each of the divided clocks;
a divided clock selection process for selecting a divided clock corresponding to any one of the lines from the one or more divided clocks and outputting the selected divided clock;
an asynchronous clock division process that divides the asynchronous clock to generate a divided asynchronous clock;
a phase synchronization process for generating and outputting a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock, the phase synchronization process generating multi-phase clocks having different phases by multiplying the divided asynchronous clock, selecting the clock having the closest phase to the selected divided clock, dividing the selected clock having the closest phase, and outputting the clock as the reference clock;
A program for executing a reference clock multiplication process for multiplying the reference clock and outputting one or more multiplied clocks. 9. The program according to claim 8 , further comprising causing the computer to execute clock data recovery based on the multiplied clock in the clock extraction process.

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