JP7704572B2 - Output Circuit - Google Patents

Description

The present invention relates to an output circuit.

Open-drain output terminals are often used as interface outputs when communicating between ICs with different power supply voltages, such as a microcontroller and a motor driver circuit driven by it. The drain of a transistor used as an output terminal is pulled up to the power supply voltage by a resistor or other device. For this reason, if both ends of the resistor are shorted, a large current may flow through the transistor, damaging it. For this reason, an overcurrent protection circuit is required to limit the current flowing through the transistor.

Such overcurrent protection circuits are proposed in Patent Documents 1 and 2. The overcurrent protection circuit in Patent Document 1 detects the current flowing through a transistor, and turns off the transistor if it is determined that an overcurrent has flowed. However, the overcurrent protection circuit in Patent Document 1 has the problem that when there are multiple transistors, the circuit size becomes large because it requires a current sense resistor to detect the current for each of the multiple transistors and an amplifier to determine the overcurrent.

The overcurrent protection circuit of Patent Document 2 uses an open-drain transistor, which is the output terminal, as the output of a current mirror circuit, and supplies a reference current to an input transistor. With this overcurrent protection circuit, the limit current of the output transistor is determined by the gate aspect ratio of the input and output transistors and the reference current. For example, if the current ratio between the input and output of this current mirror circuit is set to about 100 times and the current is limited to 50 mA, the reference current is about 500 μA. To reduce this reference current, it is necessary to make the gate width of the output transistor larger than the gate width of the input transistor, which poses the problem of expanding the element area of the open-drain transistor.

Japanese Patent Application Publication No. 6-38363 JP 2013-232760 A

The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide an output circuit that has a simple configuration, consumes little current, and allows for miniaturization of the open-drain transistor that serves as the output terminal.

In order to achieve the above-mentioned object, an output circuit according to the present invention is characterized by the following [1] to [4].
[1]
a first MOS transistor having a drain connected to an output terminal;
a second MOS transistor, the drain and source of which are connected to the gate and source of the first MOS transistor, respectively , and the gate of which receives a drive signal for turning the first MOS transistor on or off;
a current generating unit including: a transconductance amplifier having gates of a third MOS transistor and a fourth MOS transistor, the sources of which are connected to a current source and which have different gate aspect ratios, as a differential input stage; a first resistor; and a fifth MOS transistor which supplies a current corresponding to an output of the transconductance amplifier to the first resistor, the current generating unit connecting the first resistor between the gates of the third MOS transistor and the fourth MOS transistor, thereby causing a current determined by negative feedback by the transconductance amplifier to flow through the first resistor;
an output drive section including a sixth MOS transistor having a gate and a source commonly connected to the fifth MOS transistor, a second resistor to which a current equal to the current flowing through the fifth MOS transistor mirrored by the sixth MOS transistor is supplied, and a seventh MOS transistor having a diode-connected drain-gate, and the output drive section supplies a drive voltage between the gate and source of the first MOS transistor according to a voltage drop occurring in the second resistor and a gate-source voltage of the seventh MOS transistor,
limiting a drain current of the first MOS transistor to a value according to a ratio of the first resistance to the second resistance and a ratio of a transconductance coefficient of the first MOS transistor to a transconductance coefficient of the fourth MOS transistor;
It is an output circuit.
[2]
In the output circuit according to [1],
a switch for cutting off the drive voltage supplied from the output drive unit between the gate and source of the first MOS transistor when the drain voltage of the first MOS transistor drops, thereby raising the gate voltage of the first MOS transistor;
It is an output circuit.
[3]
In the output circuit according to [2],
the switch is composed of an eighth MOS transistor having a drain-source connected between the second resistor and ground and a gate connected to the drain of the first MOS transistor;
It is an output circuit.
[4]
In the output circuit according to any one of [1] to [3],
a plurality of the first MOS transistors and a plurality of the output driving units are provided;
the sixth MOS transistors of the plurality of output driving units are current-mirror-connected to one of the fifth MOS transistors;
It is an output circuit.

The present invention provides an output circuit that has a simple configuration, consumes little current, and allows for miniaturization of the open-drain transistor that serves as the output terminal.

The present invention has been briefly described above. The details of the present invention will become clearer by reading the following description of the embodiment of the invention (hereinafter referred to as "embodiment") with reference to the attached drawings.

FIG. 1 is a circuit diagram showing an output circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an output circuit according to a second embodiment of the present invention. FIG. 3 is a circuit diagram showing an output circuit according to a third embodiment of the present invention.

Specific embodiments of the present invention are described below with reference to the drawings.

First Embodiment
1, the output circuit 1A of the first embodiment includes a transistor MN6 (first MOS transistor) that serves as an open-drain output terminal, a transistor MN4 (second MOS transistor), a current generating unit 2, and an output driving unit 3. The drain of the transistor MN6 is connected to the output terminal Tout, and the source is connected to the ground. In addition, a resistor RL and a battery V2 are connected between the output terminal Tout and the ground.

Transistor MN4 is composed of an Nch MOSFET. The drain and source of transistor MN4 are connected between the gate and source of transistor MN6. A drive signal VIN is supplied to the gate of transistor MN4 to turn transistor MN6 on or off. When the drive signal VIN is supplied to transistor MN4 and transistor MN4 turns on, the gate and source of transistor MN6 are shorted and transistor MN6 turns off. On the other hand, when the drive signal VIN of transistor MN4 is cut off and transistor MN4 turns off, a gate voltage Vgsn6 (described later) is supplied between the gate and source of transistor MN6 and transistor MN6 turns on.

The current generating unit 2 is a circuit that generates a drain current Idp3 proportional to 1/R1. The output driving unit 3 is a circuit that generates a gate-source voltage Vgsn6 (driving voltage) proportional to R2/R1 by supplying a drain current Idp4 equal to the drain current Idp3 to resistor R2, and supplies this to the gate-source of transistor MN6. Here, R1 and R2 are the resistance values of resistors R1 and R2.

The current generating unit 2 includes a transconductance amplifier AMP, a transistor MP3 (a fifth MOS transistor), a resistor R1 (a first resistor), and a transistor MN3. The transconductance amplifier AMP includes a current mirror circuit 21 including transistors MP1 and MP2, a differential input stage 22 including transistors MN1 and MN2 (third and fourth MOS transistors), and a current source I1.

The transistors MP1 and MP2 that make up the current mirror circuit 21 are composed of Pch MOSFETs. The sources of the transistors MP1 and MP2 are connected to the power supply voltage VDD supplied from the battery V1, and the gates of the transistors MP1 and MP2 are connected to each other. The gate and drain of the transistor MP2 are connected. The transistors MP1 and MP2 are arranged so that the current mirror ratio is 1:1. This makes the drain currents of the transistors MP1 and MP2 equal.

The transistors MN1 and MN2 constituting the differential input stage 22 are composed of Nch MOSFETs. The drain of the transistor MN1 is connected to the drain of the transistor MP1, and the drain of the transistor MN2 is connected to the drain of the transistor MP2. The sources of the transistors MN1 and MN2 are connected to a current source I1. In addition, the aspect ratio of the transistor MN1 is greater than the aspect ratio of the transistor MN2. In this embodiment, the aspect ratio of the transistor MN1:the aspect ratio of the transistor MN2 is set to 4:1. The current source I1 is connected between the sources of the transistors MN1 and MN2 and ground.

Transistor MP3, resistor R1, and transistor MN3 are connected in series with each other. Transistor MP3 is composed of a Pch MOSFET. The gate of transistor MP3 is connected to the output of the transconductance amplifier AMP (the drains of transistors MP1 and MN1). The source of transistor MP3 is connected to the power supply voltage VDD. Resistor R1 is connected between the drain of transistor MP3 and the drain of transistor MN3, which will be described later.

Transistor MN3 is composed of an Nch MOSFET. Transistor MN3 is diode-connected with its gate connected to its drain, and its source connected to ground. This transistor MN3 is provided to set the operating voltage of transistors MN1 and MN2 that constitute the differential input stage 22. Any configuration that sets the operating voltage of transistors MN1 and MN2 may be used, and a configuration other than transistor MN3 may also be used.

The gate of the transistor MN1 constituting the differential input stage 22 described above is connected to one end of the resistor R1 on the ground side, and the gate of the transistor MN2 is connected to one end of the resistor R1 on the power supply VDD side. This allows the drain current Idp3 of the transistor MP3 flowing through the resistor R1 to be a current determined by negative feedback by the transconductance amplifier AMP.

The transconductance amplifier AMP operates so that the same drain current flows through the transistors MN1 and MN2 by the current mirror circuit 21. Also, the aspect ratio of the transistor MN1 is greater than the aspect ratio of the transistor MN2. Therefore, the transconductance amplifier AMP generates a voltage drop across the resistor R1, making the gate voltage of the transistor MN1 lower than the gate voltage of the transistor MN2, and making the drain currents Idn1 and Idn2 of the transistors MN1 and MN2 equal. In other words, the transconductance amplifier AMP outputs to the gate of the transistor MP3 such that the drain currents Idn1 and Idn2 of the transistors MN1 and MN2 are equal to each other. As a result, the drain current Idp3 of the transistor MP3 becomes a current proportional to 1/R1, as described below.

The output driver 3 has a transistor MP4 (sixth MOS transistor), a resistor R2 (second resistor), and a transistor MN5 (seventh MOS transistor). The transistor MP4, the resistor R2, and the transistor MN5 are connected in series with each other. The transistor MP4 is composed of a Pch MOSFET. The gates and sources of the transistor MP4 are commonly connected to the transistor MP3, and the aspect ratio of the transistors MP3 and MP4 is set to 1:1. As a result, the drain current Idp3 of the transistor MP3 is mirrored to the drain current Idp4 of the transistor MP4, and the drain currents Idp3 and Idp4 become equal.

Resistor R2 is connected between the drain of transistor MP4 and the drain of transistor MN5, and a drain current Idp4 is supplied to it. Transistor MN5 is composed of an Nch MOSFET. Transistor MN5 is diode-connected with its gate connected to its drain, and its source connected to ground.

The relationship between the drain current Idn1 of transistor MN1 and the gate-source voltage Vgsn1 of transistor MN1 is expressed by the following equation (1).

The relationship between the drain current Idn2 of transistor MN2 and the gate-source voltage Vgsn1 of transistor MN1 is expressed by the following equation (2).

As described above, the current mirror circuit 21 operates to cause the same drain current to flow through the transistors MN1 and MN2, and as shown in the following equations (3) and (4), the drain currents Idn1 and Idn2 of the transistors MN1 and MN2 are equal to each other, and their sum is equal to the current source I1.
Idn1=Idn2...(3)
Idn1+Idn2=I1...(4)
Furthermore, if the aspect ratio of the transistor MN1:the aspect ratio of the transistor MN2 is 4:1, the following formula (5) is obtained.
βn1=4βn2...(5)

From the above equations (1) to (5), the drain current Idp3 of transistor MP3 can be expressed by the following equation (6). As shown in equation (6), the drain current Idp3 is proportional to 1/R1.

The drain current Idp4 of transistor MP4 is a mirror of the drain current Idp3 and can be expressed by the following equation (7).

Therefore, when a drain current Idp4 is supplied to resistor R2, a voltage drop VR2 occurs across resistor R2, as shown in the following equation (8).

Furthermore, the gate-source voltage Vgsn5 of transistor MN5 can be expressed by the following equation (9).

Furthermore, the gate-source voltage Vgsn6 of transistor MN6 can be expressed by the following equation (10):

Here, if the gate aspect ratio of transistor MN5 is increased and the transconductance coefficient βn5 is made large, the gate-source voltage Vgsn5 becomes closer to the threshold voltage Vthn, and can be expressed by the following equation (11).

Furthermore, the drain current Idn6 of transistor MN6 can be expressed by the following equation (12).

Therefore, from equations (11) and (12), the drain current Idn6 can be expressed by the following equation (13).

As is clear from the above formula (13), when transistors MN1, MN2, MN5, and MN6 use elements having the same threshold voltage Vthn, carrier mobility μn, and gate oxide thickness COX, the drain current Idn6 is not affected by Vthn. That is, the drain current Idn6 can be limited to a value according to the ratio of resistors R1 and R2 and the ratio of transconductance coefficients βn6 and βn2. In this case, the ratio of transconductance coefficients βn6 and βn2 is the size ratio of transistors MN2 and MN6. As a result, this embodiment can limit the drain current Idn6 of transistor MN6 that is less susceptible to characteristic variations in the elements of transistors MN1, MN2, MN5, and MN6, variations in the absolute values of resistors R1 and R2, and temperature fluctuations.

With the above configuration, the limit current of the drain current Idn6 depends not only on the size ratio of the transistors MN2 and MN6 but also on the resistance value ratio of the resistors R2 and R1, so even if the current source I1 is limited to a small value, it is not necessary to make the size ratio of the transistors MN2 and MN6 huge. This allows for a simple configuration, low current consumption, and a miniaturized transistor MN6.

Second Embodiment
Next, a second embodiment will be described with reference to Fig. 2. In this figure, parts equivalent to those in the output circuit 1A shown in Fig. 1 already described in the first embodiment with reference to Fig. 1 are given the same reference numerals and detailed description thereof will be omitted.

The major difference between the first and second embodiments is that the output circuit 1B includes a transistor MN7 (switch, eighth MOS transistor). The transistor MN7 is composed of an Nch MOSFET. The source and drain of the transistor MN7 are connected between the transistor MN5 and ground. The gate of the transistor MN7 is connected to the drain of the transistor MN6.

The role of this transistor MN7 is to activate the overcurrent protection function only when the drain voltage of transistor MN6 is higher than the short circuit between elements of resistor RL. In the case of the first embodiment shown in FIG. 1, the gate-source voltage Vgns6 of transistor MN6 is always limited to a constant value shown in equation (11). The ON resistance Ron6 of transistor MN6 is expressed by the following equation (14).

As shown in formula (14), the ON resistance Ron6 increases as the gate-source voltage Vgsn6 decreases. In the first embodiment, if the resistance value of the resistor RL is set small, the drain voltage of the transistor MN6 may not be sufficiently reduced even if the transistor MN6 is turned on. The second embodiment shown in FIG. 2 is a circuit for improving this point. If the transistor MN6 is turned on and its drain voltage is lower than the threshold voltage Vthn of the transistor MN7, the transistor MN7 is turned off. As a result, the gate-source voltage Vgsn6 shown in formula (11) supplied from the output driver 3 between the gate and source of the transistor MN6 is cut off, and the gate voltage of the transistor MN6 is raised to the power supply voltage VDD, so that the ON resistance Ron6 expressed by formula (14) can be reduced. If the drain voltage does not decrease due to a short circuit of the resistor RL, the transistor MN7 is turned on, and the drain current can be limited in the same way as in the first embodiment.

In the second embodiment, the gate of transistor MN7 is connected to the drain of transistor MN6, and transistor MN7 turns off when the drain voltage falls below the threshold voltage Vthn, but this is not limited to the above. A comparator may be provided to which the drain voltage of transistor MN6 is input, and transistor MN7 may be turned on and off depending on the output of the comparator.

Third Embodiment
Next, a third embodiment will be described with reference to Fig. 3. In this figure, parts equivalent to those in the output circuit 1B shown in Fig. 2 already described in the second embodiment with reference to Fig. 2 are given the same reference numerals, and detailed description thereof will be omitted.

The major difference between the second and third embodiments is that the output circuit 1C controls multiple (two in FIG. 3) open-drain transistors MN6 and MN6B. Resistors RL and RLB are connected to the drains of the transistors MN6 and MN6B. In other words, the output circuit 1C of the third embodiment includes multiple output drive units 3 and 3B.

In FIG. 3, transistors MP4 and MP4B that make up multiple output drivers 3 and 3B are mirror-connected in parallel to transistor MP3, and their drain currents Idp3 are supplied to resistors R2 and R2B, respectively. This allows for a single circuit as the current generator 2, resulting in a simpler circuit configuration than when multiple output circuits are provided as in the conventional example.

The present invention is not limited to the above-described embodiment, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary as long as they can achieve the present invention, and are not limited.

1A to 1C output circuit 2 current generating section 3 output driving section 22 differential input stage I1 current source MP3 transistor (fifth MOS transistor)
MP4 transistor (sixth MOS transistor)
MN1 transistor (third MOS transistor)
MN2 transistor (fourth MOS transistor)
MN4 transistor (second MOS transistor)
MN5 transistor (seventh MOS transistor)
MN6 transistor (first MOS transistor)
MN7 transistor (eighth MOS transistor)
R1 Resistor (first resistor)
R2 Resistor (second resistor)

Claims (4)

a first MOS transistor having a drain connected to an output terminal;
a second MOS transistor, the drain and source of which are connected to the gate and source of the first MOS transistor, respectively , and the gate of which receives a drive signal for turning the first MOS transistor on or off;
a current generating unit including: a transconductance amplifier having gates of a third MOS transistor and a fourth MOS transistor, the sources of which are connected to a current source and which have different gate aspect ratios, as a differential input stage; a first resistor; and a fifth MOS transistor which supplies a current corresponding to an output of the transconductance amplifier to the first resistor, the current generating unit connecting the first resistor between the gates of the third MOS transistor and the fourth MOS transistor, thereby causing a current determined by negative feedback by the transconductance amplifier to flow through the first resistor;
an output drive section including a sixth MOS transistor having a gate and a source commonly connected to the fifth MOS transistor, a second resistor to which a current equal to the current flowing through the fifth MOS transistor mirrored by the sixth MOS transistor is supplied, and a seventh MOS transistor having a diode-connected drain-gate, and the output drive section supplies a drive voltage between the gate and source of the first MOS transistor according to a voltage drop occurring in the second resistor and a gate-source voltage of the seventh MOS transistor,
limiting a drain current of the first MOS transistor to a value according to a ratio of the first resistance to the second resistance and a ratio of a transconductance coefficient of the first MOS transistor to a transconductance coefficient of the fourth MOS transistor;
Output circuit. 2. The output circuit according to claim 1,
a switch for cutting off the drive voltage supplied from the output drive unit between the gate and source of the first MOS transistor when the drain voltage of the first MOS transistor drops, thereby raising the gate voltage of the first MOS transistor;
Output circuit. 3. The output circuit according to claim 2,
the switch is composed of an eighth MOS transistor having a drain-source connected between the second resistor and ground and a gate connected to the drain of the first MOS transistor;
Output circuit. In the output circuit according to any one of claims 1 to 3,
a plurality of the first MOS transistors and a plurality of the output driving units are provided;
the sixth MOS transistors of the plurality of output driving units are current-mirror-connected to one of the fifth MOS transistors;
Output circuit.

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