JP7704699B2 - Semiconductor Device - Google Patents

Description

The embodiment relates to a semiconductor device.

In order to suppress the on-resistance while outputting a large current, power semiconductor chips such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) may be connected in parallel.

JP 2013-98541 A

The embodiment aims to provide a semiconductor device that can improve avalanche resistance.

The semiconductor device according to the embodiment includes a substrate having conductivity and a second thickness, a first surface facing the substrate, and a second surface located opposite the first surface, a first chip having a first electrode electrically connected to the substrate arranged on the first surface and a second electrode arranged on the second surface, a third surface facing the second surface and a fourth surface located opposite the third surface, a second chip having a third electrode arranged on the third surface and a fourth electrode arranged on the fourth surface, a first connector arranged between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode, and a second connector electrically connected to the substrate and the fourth electrode, including a first portion located above the second chip, and the difference between the first thickness and the second thickness of the first portion is 20% or less of the larger of the first thickness and the second thickness.

1 is a top view showing a semiconductor device according to a first embodiment; 1 is a top view showing a substrate, a first lead, a second lead, and a first chip of a semiconductor device according to a first embodiment. 1 is a top view showing a substrate, a first lead, a second lead, a first chip, a first connector, and a third connector of a semiconductor device according to a first embodiment. FIG. This is a cross-sectional view taken along line A-A' in Figure 1. This is a cross-sectional view taken along line B-B' in Figure 1. 1 is a circuit diagram of a semiconductor device according to a first embodiment; 1 illustrates an evaluation circuit for semiconductor devices according to a reference example and an embodiment. 1 is a graph showing the relationship between the breakdown voltage and the current ratio Tr1/Tr2. 1 is a graph showing the relationship between chip area and the rate of decrease in on-resistance. FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. The horizontal axis shows the current flowing through the chip when the chip undergoes avalanche breakdown, and the vertical axis shows the frequency of occurrence of chips for which each current was measured. FIG. 13 is a cross-sectional view showing a semiconductor device according to a fourth embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual and are appropriately simplified. The relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing.
In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate.

In the following, to make the explanation easier to understand, an XYZ Cartesian coordinate system is used. Furthermore, within the Z direction, the direction of the arrow is referred to as the "upward direction" and its opposite direction as the "downward direction," but these directions are relative and are unrelated to the direction of gravity. Furthermore, among the directions in which the X axis extends, the direction of the arrow is also referred to as the "+X direction," and its opposite direction is also referred to as the "-X direction." Furthermore, among the directions in which the Y axis extends, the direction of the arrow is also referred to as the "+Y direction," and its opposite direction is also referred to as the "-Y direction."

First Embodiment
First, the first embodiment will be described.
FIG. 1 is a top view showing a semiconductor device according to the present embodiment.
FIG. 2 is a top view showing a substrate, a first lead, a second lead, and a first chip of the semiconductor device according to the present embodiment.
FIG. 3 is a top view showing the substrate, the first lead, the second lead, the first chip, the first connector, and the third connector of the semiconductor device according to the present embodiment.
FIG. 4 is a cross-sectional view taken along line AA' in FIG.
FIG. 5 is a cross-sectional view taken along line BB' in FIG.

The semiconductor device 100 according to this embodiment, when generally described with reference to Figures 1 and 4, comprises a substrate 110, a first lead 120, a second lead 130, a first chip 140, a second chip 150, a first connector 160, a second connector 170, a third connector 180, and a resin member 190. In Figure 1, the resin member 190 is indicated by a two-dot chain line to make the internal structure of the semiconductor device 100 easier to understand. Each part of the semiconductor device 100 will be described in detail below.

The substrate 110 is made of, for example, a metal material. Examples of metal materials used for the substrate 110 include metals with high heat dissipation properties, such as copper. The shape of the substrate 110 is, for example, substantially flat. Specifically, as shown in FIG. 4, the lower surface 110a and the upper surface 110b of the substrate 110 are substantially flat and generally parallel to the XY plane. However, the shape of the substrate is not limited to the above.

The first lead 120 is made of, for example, a metal material. Examples of metal materials used for the first lead 120 include materials similar to those used for the substrate 110. As shown in FIG. 1, the first lead 120 is located on the +X side of the substrate 110 and is spaced apart from the substrate 110. The shape of the first lead 120 is, for example, substantially flat. However, the position and shape of the first lead are not limited to the above.

The second lead 130 is made of, for example, a metal material. Examples of metal materials used for the second lead 130 include materials similar to those used for the substrate 110. The second lead 130 is located on the -X side of the substrate 110 and is separated from the substrate 110 and the first lead 120. The shape of the second lead 130 is, for example, substantially flat. However, the position and shape of the second lead are not limited to the above.

The first chip 140 is disposed on the substrate 110 as shown in FIG. 2. The first chip 140 is, for example, a MOSFET having a FP (Field Plate) electrode. However, the first chip may be a MOSFET without a FP electrode, or may be another type of semiconductor element. The shape of the first chip 140 is, for example, substantially flat. Specifically, the shape of the first chip 140 in a top view is substantially rectangular. As shown in FIG. 4, the surface of the first chip 140 includes a lower surface 140a facing the substrate 110 and an upper surface 140b located on the opposite side of the lower surface 140a.

As shown in FIG. 5, the first chip 140 has a semiconductor portion 145. The semiconductor portion 145 is made of a semiconductor material such as silicon, and impurities are locally introduced to make the conductivity type n-type or p-type. A drain electrode 141 is disposed on the lower surface 140a of the first chip 140. The drain electrode 141 is electrically connected to the substrate 110 by a conductive bonding layer 141c such as solder. Here, "disposed on a surface with an electrode" means that at least a part of the surface of the electrode is exposed on that surface. In this embodiment, the bonding layer 141c is in contact with both the substrate 110 and the drain electrode 141. A source electrode 142 and a gate electrode 143 are disposed on the upper surface 140b of the first chip 140.

When viewed from above, i.e., from the +Z direction, the shape of the source electrode 142 is a rectangle with one corner cut out and the other corner rounded, as shown in FIG. 2. The gate electrode 143 is spaced apart from the source electrode 142 and is disposed in the region where the corner of the source electrode 142 is cut out. The shape of the gate electrode 143 in top view is a roughly rectangular shape with rounded corners. The gate electrode 143 is spaced apart from the source electrode 142. However, the positions and shapes of the source electrode and gate electrode are not limited to those described above.

The second chip 150 is, for example, the same semiconductor element as the first chip 140. Specifically, the second chip 150 is a MOSFET having an FP electrode. In this embodiment, the chip area and shape of the second chip 150 are substantially the same as the chip area and shape of the first chip 140. Note that "chip area" refers to the area in the XY plane.

The second chip 150 is disposed above the first chip 140 as shown in FIG. 4. The surface of the second chip 150 includes a lower surface 150a that faces the upper surface 140b of the first chip 140, and an upper surface 150b that is located on the opposite side of the lower surface 150a.

As shown in FIG. 5, the second chip 150 has a semiconductor portion 155. The semiconductor portion 155 is made of a semiconductor material such as silicon, and impurities are locally introduced to make the conductivity type n-type or p-type. A source electrode 151 and a gate electrode 152 are arranged on the lower surface 150a of the second chip 150. A drain electrode 153 is arranged on the upper surface 150b of the second chip 150.

The source electrode 151 of the second chip 150 faces the source electrode 142 of the first chip 140. The shape of the source electrode 151 of the second chip 150 is approximately the same as the shape of the source electrode 142 of the first chip 140. The area of the source electrode 151 of the second chip 150 is approximately the same as the area of the source electrode 142 of the first chip 140.

The gate electrode 152 of the second chip 150 faces the gate electrode 143 of the first chip 140. The shape of the gate electrode 152 of the second chip 150 is approximately the same as the shape of the gate electrode 143 of the first chip 140. The area of the gate electrode 152 of the second chip 150 is approximately the same as the area of the gate electrode 143 of the first chip 140.

Therefore, the first chip 140 and the second chip 150 are arranged approximately symmetrically with respect to a plane P that passes through the center of the gap between the first chip 140 and the second chip 150 and is approximately parallel to the XY plane. However, the positions and shapes of the source electrode and gate electrode are not limited to the above.

The area of the first chip 140 and the area of the second chip 150 as viewed from above are preferably 10 mm ² or more and 25 mm ² or less, respectively. However, the area of each chip is not limited to the above.

The first connector 160 is electrically connected to the source electrode 142 of the first chip 140, the source electrode 151 of the second chip 150, and the first lead 120. The first connector 160 is made of, for example, a metal material. The metal material used for the first connector 160 may be the same material as that used for the substrate 110. The first connector 160 is formed, for example, by bending a single copper plate.

The first connector 160 has a first portion 161 located above the first chip 140, a second portion 162 extending from the first portion 161 toward the first lead 120, and a third portion 163 connected to the lower end of the second portion 162 and extending along the surface of the first lead 120.

The first portion 161 is shaped like a generally flat plate that is generally parallel to the X-Y plane, for example. The first portion 161 is disposed between the two source electrodes 142, 151, and extends in the +X direction further than the first chip 140 and the second chip 150 when viewed from above. The first portion 161 is connected to the source electrode 142 of the first chip 140 by a conductive bonding layer 142c such as solder. The first portion 161 is also connected to the source electrode 151 of the second chip 150 by a conductive bonding layer 151c such as solder.

In this embodiment, the second portion 162 is connected to the end of the first portion 161 in the +X direction and extends downward. The third portion 163 extends in the +X direction from the lower end of the second portion 162. The third portion 163 is connected to the first lead 120 by a conductive bonding layer 120c such as solder. However, the shape of the first connector 160 is not limited to the above.

The third connector 180 is electrically connected to the gate electrode 143 of the first chip 140, the gate electrode 152 of the second chip 150, and the second lead 130. The third connector 180 may be made of the same material as that used for the first connector 160. The third connector 180 is formed, for example, by bending a single copper plate.

The third connector 180 has a first portion 181 located above the first chip 140, a second portion 182 extending from the first portion 181 toward the second lead 130, and a third portion 183 connected to the lower end of the second portion 182 and extending along the surface of the second lead 130.

The first portion 181 is shaped like a generally flat plate that is generally parallel to the X-Y plane, for example. The first portion 181 is disposed between the two gate electrodes 143, 152, and protrudes in the -X direction further than the first chip 140 and the second chip 150 when viewed from above. The first portion 181 is connected to the gate electrode 143 of the first chip 140 by a conductive bonding layer 143c such as solder. The first portion 181 is connected to the gate electrode 152 of the second chip 150 by a conductive bonding layer 152c such as solder.

In this embodiment, the second portion 182 is connected to the end of the first portion 181 in the -X direction and extends downward. The third portion 183 extends in the -X direction from the lower end of the second portion 182. The third portion 183 is connected to the second lead 130 by a conductive bonding layer 130c such as solder. However, the shape of the third connector 180 is not limited to the above.

As shown in FIG. 5, the second connector 170 is electrically connected to the drain electrode 153 of the second chip 150 and the substrate 110. The second connector 170 is made of, for example, the same material as the substrate 110. The second connector 170 is formed, for example, by bending a single copper plate.

The second connector 170 has a first portion 171 located above the second chip 150, a second portion 172 extending from the first portion 171 to the substrate 110, and a third portion 173 connected to the lower end of the second portion 172 and extending along the surface of the substrate 110.

The first portion 171 is shaped like a generally flat plate that is generally parallel to the XY plane, for example. When viewed from above, the first portion 171 covers the drain electrode 153 of the second chip 150, and extends further in the +Y direction than the first chip 140 and the second chip 150 when viewed from above. The first portion 171 is connected to the drain electrode 153 of the second chip 150 by a conductive bonding layer 153c such as solder.

In this embodiment, the second portion 172 is connected to the end of the first portion 171 in the +Y direction and extends downward. The third portion 173 extends in the +Y direction from the lower end of the second portion 172. The third portion 173 is connected to the substrate 110 by a conductive bonding layer 110c such as solder. It is preferable that the thickness of the second portion 172 is equal to or smaller than the thickness of the first portion 171. Since the thickness of the second portion 172 is smaller than the thickness of the first portion 171, it becomes easier to form the second connector 170 by bending. However, the shape of the second connector 170 is not limited to the above.

In this embodiment, the first thickness D1 of the first portion 171 is smaller than the second thickness D2 of the portion of the substrate 110 that overlaps with the drain electrode 141 when viewed from above. The difference between the first thickness D1 and the second thickness D2 is preferably 20% or less of the second thickness D2. However, the first thickness may be greater than the second thickness. In this case, the difference between the first thickness and the second thickness is preferably 20% or less of the first thickness. In addition, the first thickness and the second thickness may be the same. That is, the difference between the first thickness and the second thickness is preferably 20% or less of the larger of the first thickness and the second thickness. That is, the thicknesses D1 and D2 preferably satisfy the following formula.
(D2-D1)/D2×100≦20 (D1≦D2)
(D1-D2)/D1×100≦20 (D1≧D2)

The resin member 190 seals the first chip 140, the second chip 150, the first connector 160, the second connector 170, and the third connector 180. As shown in FIG. 1, FIG. 4, and FIG. 5, the resin member 190 exposes the end of the substrate 110 in the +Y direction and the lower surface 110a of the substrate 110. The portion of the substrate 110 exposed from the resin member 190 functions as a connection terminal that connects the two drain electrodes 141, 153 to the outside. The resin member 190 exposes the end of the first lead 120 in the +X direction and the lower surface of the first lead 120. The portion of the first lead 120 exposed from the resin member 190 functions as a connection terminal that connects the two source electrodes 142, 151 to the outside. The resin member 190 exposes the end of the second lead 130 in the -X direction and the lower surface of the second lead 130. The portion of the second lead 130 exposed from the resin member 190 functions as a connection terminal that connects the two gate electrodes 143 and 152 to the outside. The resin member 190 is made of a resin material such as a thermosetting resin.

The withstand voltage of the first chip 140 and the second chip 150 is preferably, for example, greater than 0 V and equal to or less than 100 V. However, the withstand voltage of the first chip 140 and the second chip 150 is not limited to the above.

Next, the effects of this embodiment will be described.
FIG. 6 is a circuit diagram of the semiconductor device according to this embodiment.
In FIG. 6, in the semiconductor device 100, the external connection terminals of the two drain electrodes 141, 153 are indicated by the reference symbol 110d, the external connection terminals of the two source electrodes 142, 151 are indicated by the reference symbol 120d, and the external connection terminals of the two gate electrodes 143, 152 are indicated by the reference symbol 130d.

As shown in Figures 4 and 6, the gate electrode 143 of the first chip 140 and the gate electrode 152 of the second chip 150 are connected to the outside via the third connector 180 and the second lead 130. Therefore, the current path from the external connection terminal 130d to the gate electrode 143 and the current path from the external connection terminal 130d to the gate electrode 152 are mostly common. Therefore, a difference in electrical resistance is unlikely to occur between the current path from the connection terminal 130d to the gate electrode 143 and the current path from the connection terminal 130d to the gate electrode 152.

Similarly, the source electrode 142 of the first chip 140 and the source electrode 151 of the second chip 150 are connected to the outside via the first connector 160 and the first lead 120. Therefore, the current path from the source electrode 142 to the connection terminal 120d to the outside and the current path from the source electrode 151 to the connection terminal 120d to the outside are mostly common. Therefore, a difference in electrical resistance is unlikely to occur between the current path from the connection terminal 120d to the source electrode 142 and the current path from the connection terminal 120d to the source electrode 151.

On the other hand, as shown in FIG. 5 and FIG. 6, the drain electrode 141 of the first chip 140 is connected to the outside via the substrate 110, and the drain electrode 153 of the second chip 150 is connected to the outside by the substrate 110 and the second connector 170. Therefore, the current path from the external connection terminal 110d to the drain electrode 141 and the current path from the external connection terminal 110d to the drain electrode 153 are largely different. In the following, the electrical resistance of the portion of the substrate 110 that is common to these two current paths is referred to as electrical resistance R1, the electrical resistance of only the current path leading to the drain electrode 141 of the first chip 140 in these two current paths in the substrate 110 is referred to as electrical resistance R2, and the electrical resistance of the second connector 170 is referred to as electrical resistance R3.

The smaller the first thickness D1 of the second connector 170 is than the second thickness D2 of the substrate 110, the greater the electrical resistance R3 is than the electrical resistance R2. The greater the electrical resistance R3 is than the electrical resistance R2, the easier it is for a current to flow to the drain electrode 141 of the first chip 140 than the drain electrode 153 of the second chip 150. In such a case, if the source-drain current of the semiconductor device 100 is increased, the first chip 140, through which a larger current flows, becomes more susceptible to avalanche breakdown. Conversely, the smaller the second thickness D2 of the substrate 110 is than the first thickness D1 of the second connector 170, the greater the electrical resistance R2 is than the electrical resistance R3. The greater the electrical resistance R2 is than the electrical resistance R3, the easier it is for a current to flow to the drain electrode 153 of the second chip 150 than the drain electrode 141 of the first chip 140. In such a case, if the source-drain current of the semiconductor device 100 is increased, the second chip 150, through which a larger current flows, becomes more susceptible to avalanche breakdown.

In this embodiment, the difference between the first thickness D1 and the second thickness D2 is 20% or less of the larger of the first thickness D1 and the second thickness D2. Therefore, the difference between the electrical resistance R2 and the electrical resistance R3 can be reduced. As a result, it is possible to prevent current from flowing unevenly through the first chip 140 or the second chip 150, which would lead to avalanche breakdown. As a result, the avalanche resistance of the entire semiconductor device 100 can be improved.

In addition, in this embodiment, the second thickness D2 is smaller than the first thickness D1. Therefore, the amount of thermal expansion of the second connector 170 can be reduced. This makes it possible to prevent the resin member 190 covering the second connector 170 from being deformed or damaged when the second connector 170 thermally expands.

First Example
Next, a first example of the first embodiment will be described.
FIG. 7 shows an evaluation circuit for the semiconductor device according to the reference example and the embodiment.
FIG. 8 is a graph showing the relationship between the breakdown voltage and the current ratio Tr1/Tr2.

The semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3 were created. The semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3 each include a substrate 110, a first lead 120, a second lead 130, a first chip 140, a second chip 150, a first connector 160, a second connector 170, a third connector 180, and a resin member 190, similar to the first embodiment, and have a common configuration other than the first thickness D1 of the second connector 170. In the semiconductor devices according to Reference Examples 1 to 3, the first thickness D1 of the second connector 170 is 150 μm, and in the semiconductor devices according to Examples 1 to 3, the first thickness D1 of the second connector 170 is 250 μm. In the semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3, the second thickness D2 of the substrate 110 is 300 μm. Therefore, in the semiconductor devices according to Reference Examples 1 to 3, the difference between the first thickness D1 and the second thickness D2 is 150 μm, which is 50% of the second thickness D2. In the semiconductor devices according to Examples 1 to 3, the difference between the first thickness D1 and the second thickness D2 is 50 μm, which is approximately 17% of the second thickness D2, and is less than 20%.

The withstand voltage of the semiconductor device according to Reference Example 1 and the semiconductor device according to Example 1 was set to 40 V, the withstand voltage of the semiconductor device according to Reference Example 2 and the semiconductor device according to Example 2 was set to 100 V, and the withstand voltage of the semiconductor device according to Reference Example 3 and the semiconductor device according to Example 3 was set to 150 V.

Then, the semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3 were each incorporated into the evaluation circuit shown in FIG. 7, and the current Tr1 flowing through the first chip 140 and the current Tr2 flowing through the second chip 150 were measured. Specifically, the connection terminal 110d was electrically connected to the inductor 910. The inductor 910 was further electrically connected to the power source 920. The connection terminal 120d was electrically connected to the earth 930. The connection terminal 130d was electrically connected to the signal source 940.

The ratio Tr1/Tr2 of the current Tr1 to the current Tr2 was calculated for each of the semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3. The relationship between the obtained current ratio Tr1/Tr2 and the withstand voltage is shown in FIG. 8. In FIG. 8, the horizontal axis indicates the withstand voltage, and the vertical axis indicates the current ratio Tr1/Tr2. The closer the current ratio Tr1/Tr2 is to 1, the more evenly the current flows through the first chip 140 and the second chip 150.

As shown in FIG. 8, even with the same breakdown voltage, the ratio Tr1/Tr2 is closer to 1 in the semiconductor devices according to Examples 1 to 3 than in the semiconductor devices according to Reference Examples 1 to 3. Therefore, when the source-drain current of the semiconductor device is increased, it is possible to prevent one of the chips from being destroyed first, improving the avalanche resistance of the entire semiconductor device. Therefore, it is preferable that the difference between the first thickness D1 and the second thickness D2 is 20% or less of the second thickness D2.

In addition, in the range where the withstand voltage is 100V or less, the effect of bringing the ratio Tr1/Tr2 closer to 1 by making the difference between the first thickness D1 and the second thickness D2 20% or less of the second thickness D2 is greater than in the range where the withstand voltage is greater than 100V. This is thought to be because the higher the withstand voltage, the higher the proportion of the internal resistance of each chip 140, 150 in the total resistance of the semiconductor device, and the lower the proportion of the electrical resistances R2, R3. Therefore, it is preferable that the withstand voltage of the semiconductor device is 100V or less.

Second Example
Next, a second example of the first embodiment will be described.
FIG. 9 is a graph showing the effect of stacking chips, with the horizontal axis representing the chip area of one chip and the vertical axis representing the rate of decrease in on-resistance caused by stacking and connecting two chips in parallel.
The vertical axis of Fig. 9 shows the reduction rate of the overall on-resistance when two identical chips are stacked and connected in parallel relative to the on-resistance of one chip. A simple calculation based only on the internal resistance of the chips would result in a reduction rate of -50% in the on-resistance.

As shown in Fig. 9, the smaller the chip area, the more significant the reduction rate of the on-resistance. This is thought to be because the smaller the chip area, the greater the resistance of the transistor section, and the greater the proportion of the resistance of the transistor section to the total resistance, so that the reduction in the resistance of the transistor section due to stacking increases the total resistance reduction rate. Therefore, it is preferable that the chip area of the first chip 140 and the chip area of the second chip 150 viewed from above are 10 ^mm2 or more and 25 ^mm2 or less, respectively.

Second Embodiment
Next, a second embodiment will be described.
FIG. 10 is a cross-sectional view showing the semiconductor device according to this embodiment.
The semiconductor device 200 according to this embodiment differs from the semiconductor device 100 according to the first embodiment in the orientation of the first chip 240 and the orientation of the second chip 250 .
In the following description, only the differences from the first embodiment will be mainly described. The configuration other than the matters described below can be the same as that of the first embodiment. The same applies to the other embodiments described later.

A source electrode 241 and a gate electrode 242 are disposed on the underside 240a of the first chip 240. The source electrode 241 faces the conductive first substrate 210 and is electrically connected to the first substrate 210 via a bonding layer 241c. The gate electrode 242 faces the conductive second substrate 220 and is electrically connected to the second substrate 220 via a bonding layer 242c.

A drain electrode 243 is disposed on the upper surface 240b of the first chip 240. The drain electrode 243 faces the first connector 260. The drain electrode 243 is electrically connected to the first connector 260 via a bonding layer 243c. The first connector 260 is connected to a drain lead (not shown) in the same manner as the first connector 160 in the first embodiment.

A drain electrode 251 is disposed on the lower surface 250a of the second chip 250. The drain electrode 251 faces the first connector 260. The drain electrode 251 is electrically connected to the first connector 260 via a bonding layer 251c.

A source electrode 252 and a gate electrode 253 are disposed on the upper surface 250b of the second chip 250. The source electrode 252 faces the second connector 270. The source electrode 252 is electrically connected to the second connector 270 via a bonding layer 252c. The gate electrode 253 faces the third connector 280. The gate electrode 253 is electrically connected to the third connector 280 via a bonding layer 253c.

The second connector 270 has a first portion 271 located above the second chip 250, a second portion 272 extending from the first portion 271 toward the first substrate 210, and a third portion 273 connected to the lower end of the second portion 272 and extending in a direction along the surface of the first substrate 210. The difference between the first thickness D21 of the first portion 271 and the second thickness D22 of the portion of the first substrate 210 that overlaps with the source electrode 241 when viewed from above is 20% or less of the larger of the first thickness D21 and the second thickness D22 (the second thickness D22 in FIG. 10).

Similarly, the third connector 280 has a first portion 281 located above the second chip 250, a second portion 282 extending from the first portion 281 toward the second substrate 220, and a third portion 283 connected to the lower end of the second portion 282 and extending in a direction along the surface of the second substrate 220.

Even in such a semiconductor device 200, by making the difference between the first thickness D21 and the second thickness D22 20% or less of the larger of the first thickness D21 and the second thickness D22, the difference between the electrical resistance of the current path from the first substrate 210 to the source electrode 241 of the first chip 240 and the electrical resistance of the current path from the first substrate 210 to the source electrode 252 of the second chip 250 via the second connector 270 can be reduced, and current concentration on one chip can be suppressed. As a result, the avalanche resistance of the semiconductor device 200 can be improved.

Third Embodiment
Next, a third embodiment will be described.
FIG. 11 is a cross-sectional view showing the semiconductor device according to this embodiment.
As shown in FIG. 11, the semiconductor device 300 according to this embodiment differs from the semiconductor device 100 according to the first embodiment in that it further includes a plurality of metal layers 341e, 342e, and 343e.

In this embodiment, the second thickness D2 is thicker than the first thickness D1. Furthermore, the difference between the first thickness D1 and the second thickness D2 is 20% or less of the second thickness D2. Therefore, current flows more easily through the first chip 140 than through the second chip 150. However, the difference between the first thickness D1 and the second thickness D2 may be greater than 20% of the second thickness D2. In other words, the difference between the first thickness D1 and the second thickness D2 may be greater than 20% of the larger of the first thickness D1 and the second thickness D2.

The metal layer 341e is located between the drain electrode 141 and the bonding layer 141c. The metal layer 341e is in contact with the upper surface of the bonding layer 141c and the lower surface of the drain electrode 141, and is thus electrically connected to the bonding layer 141c and the drain electrode 141. The metal layer 342e is located between the source electrode 142 and the bonding layer 142c. The metal layer 342e is in contact with the upper surface of the source electrode 142 and the lower surface of the bonding layer 142c, and is thus electrically connected to the source electrode 142 and the bonding layer 142c. The metal layer 343e is located between the gate electrode 143 and the bonding layer 143c. The metal layer 343e is in contact with the upper surface of the gate electrode 143 and the lower surface of the bonding layer 143c, and is thus electrically connected to the gate electrode 143 and the bonding layer 143c. The metal layers 341e, 342e, and 343e each extend along the X-Y plane.

The thermal conductivity of each of the metal layers 341e, 342e, and 343e is higher than that of the bonding layers 141c, 142c, and 143c. Each of the metal layers 341e includes, for example, one or more of gold, silver, and copper. The thickness of each of the metal layers 341e, 342e, and 343e is not particularly limited, but is, for example, 10 μm or more and 20 μm or less. On the other hand, the bonding layers 141c, 142c, and 143c are made of, for example, solder. Solder generally has low thermal conductivity.

In the semiconductor device 300 according to this embodiment, the second thickness D2 is greater than the first thickness D1, so that current flows more easily through the first chip 140 than through the second chip 150. Therefore, metal layers 341e, 342e, and 343e are disposed on the electrodes 141, 142, and 143 of the first chip 140, respectively. This allows the heat generated in the portion of the first chip 140 where the current is particularly concentrated to be diffused along the X-Y plane, thereby making the temperature inside the first chip 140 uniform. This prevents thermal destruction in the portion of the first chip 140 where the current is concentrated, and prevents avalanche destruction of the first chip 140. As a result, the avalanche resistance of the semiconductor device 300 can be improved.

In addition, in this embodiment, each metal layer is disposed closer to the first chip 140 than each bonding layer. This allows heat to be transferred directly from the first chip 140 to each metal layer without passing through the bonding layers, which have low thermal conductivity. As a result, heat can be effectively diffused by the metal layers, and the avalanche resistance of the semiconductor device 300 is reliably improved.

<Test Example>
Next, a test example of the third embodiment will be described.
FIG. 12 is a histogram showing the current flowing through a chip when the chip undergoes avalanche breakdown on the horizontal axis and the frequency of occurrence of chips for which each current was measured on the vertical axis.
Ten chips were prepared that had the same configuration as the first chip 140 and the second chip 150, and had a 10 μm thick metal layer made of copper on each of the drain electrode, source electrode, and gate electrode. In addition, ten chips were prepared that had the same configuration as the first chip 140 and the second chip 150, and had no metal layer on each of the drain electrode, source electrode, and gate electrode. Then, the current Tr was measured when each chip broke down in avalanche. The results are shown in FIG. 12 .

As shown in Figure 12, it was found that in chips with a metal layer disposed on the electrodes, the current Tr at which the chip breaks down is likely to be high. In other words, it was found that by disposing a metal layer on the electrodes of the chip, the avalanche resistance of the chip can be improved. When the average current Tr for each chip was taken, the avalanche resistance was improved by about 10% when a metal layer was provided, compared to when a metal layer was not provided.

However, it is not necessary to place a metal layer on all the electrodes of the first chip. The second thickness may be greater than the first thickness. In this case, current flows more easily through the second chip than through the first chip. Therefore, in such a case, if a metal layer is placed on the electrodes of the second chip, the heat generated in the second chip can be efficiently uniformed. That is, if the first thickness is smaller than the second thickness, the metal layer is placed on any of the electrodes of the first chip, and if the first thickness is greater than the second thickness, the metal layer is placed on any of the electrodes of the second chip. Also, such a metal layer may be placed in the semiconductor device according to the second embodiment.

Fourth Embodiment
Next, a fourth embodiment will be described.
FIG. 13 is a cross-sectional view showing the semiconductor device according to this embodiment.
FIG. 13 corresponds to FIG. 5 in the first embodiment.

The semiconductor device 400 according to this embodiment differs from the semiconductor device 100 according to the first embodiment in that the chip area of the chip through which current flows more easily is smaller than the chip area of the chip through which current flows less easily.

As shown in FIG. 13, in the semiconductor device 400, the second thickness D2 of the substrate 110 is greater than the first thickness D1 of the first portion 171 of the second connector 170. For this reason, if the first chip 340 and the second chip 350 are chips of the same specification, current tends to concentrate in the first chip 340. Therefore, in this embodiment, the chip area of the first chip 340 is made smaller than the chip area of the second chip 350. As a result, the internal resistance of the first chip 340 becomes higher than the internal resistance of the second chip 350, and current concentration in the first chip 340 can be suppressed. This improves the avalanche resistance of the entire semiconductor device 400.

In the above-described embodiments, the substrate and the second connector are formed from the same material, but this is not limiting. For example, if the substrate is thicker than the second connector, the electrical resistivity of the material forming the substrate may be higher than the electrical resistivity of the material forming the second connector. For example, the substrate may be formed from aluminum (electrical resistivity is 28.2 nΩ·m at 20°C), and the second connector may be formed from copper (electrical resistivity is 16.8 nΩ·m at 20°C).

Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope and gist of the invention, as well as within the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments may be implemented in combination with each other.

100, 200, 300, 400: Semiconductor device 110: Substrate 110a: Bottom surface 110b: Top surface 110c, 120c, 130c, 141c, 142c, 143c, 151c, 152c, 153c: Bonding layer 110d, 120d, 130d: Connection terminal 120: First lead 130 : Second lead 140, 240, 340: First chip 140a, 240a: Lower surface 140b, 240b: Upper surface 141, 243: Drain electrode 142, 241: Source electrode 143, 242: Gate electrode 145, 155: Semiconductor portion 150, 250, 350: Second chip 150a, 250a: Lower surface 150b, 250b: Upper surface 151, 252: Source electrode 152, 253: Gate electrode 153, 251: Drain electrode 160, 260: First connector 161: First portion 162: Second portion 163 : Third portion 170, 270: Second connector 171, 271: First portion 172, 272: Second portion 173, 273: Third portion 180, 280: Third connector 181, 281: First portion 182, 282: Second portion 183, 283: Third portion 190: Resin member 210: First board 220: Second board 341e, 342e, 343e: Metal layer 910: Inductor 920: Power supply 930: Earth 940: Signal source D1, D21: First thickness D2, D22: Second thickness P: Plane R1, R2, R3: Electrical resistance Tr, Tr1, Tr2: Current

Claims (7)

a substrate having electrical conductivity and a second thickness;
a first chip including a first surface facing the substrate and a second surface located on the opposite side to the first surface, a first electrode electrically connected to the substrate being disposed on the first surface and a second electrode being disposed on the second surface;
a second chip including a third surface facing the second surface and a fourth surface located on the opposite side of the third surface, a third electrode being arranged on the third surface and a fourth electrode being arranged on the fourth surface;
a first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode;
a second connector electrically connected to the substrate and the fourth electrode, the second connector including a first portion located above the second chip, the difference between a first thickness and the second thickness of the first portion being 20% or less of the first thickness , and the second thickness being smaller than the first thickness ;
Equipped with
A semiconductor device in which the distance between the connection point of the second connector with the substrate and the connection point of the fourth electrode is longer than the distance between the connection point of the second connector with the substrate and the connection point of the first electrode . a first bonding layer located between the first electrode and the substrate and having electrical conductivity;
a second bonding layer located between the second electrode and the first connector and having electrical conductivity;
a third bonding layer located between the third electrode and the first connector and having electrical conductivity;
a fourth bonding layer located between the fourth electrode and the second connector and having electrical conductivity;
a metal layer having a thermal conductivity higher than thermal conductivities of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer, and being disposed between the first bonding layer and the first electrode or between the second bonding layer and the second electrode when the first thickness is smaller than the second thickness, and being disposed between the third bonding layer and the third electrode or between the fourth bonding layer and the fourth electrode when the first thickness is greater than the second thickness;
The semiconductor device according to claim 1 , further comprising: A conductive substrate;
a first chip including a first surface facing the substrate and a second surface located on the opposite side to the first surface, a first electrode electrically connected to the substrate being disposed on the first surface and a second electrode being disposed on the second surface;
a second chip including a third surface facing the second surface and a fourth surface located on the opposite side of the third surface, a third electrode being arranged on the third surface and a fourth electrode being arranged on the fourth surface;
a first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode;
a second connector including a first portion electrically connected to the substrate and the fourth electrode and positioned above the second chip;
a first bonding layer located between the first electrode and the substrate and having electrical conductivity;
a second bonding layer located between the second electrode and the first connector and having electrical conductivity;
a third bonding layer located between the third electrode and the first connector and having electrical conductivity;
a fourth bonding layer located between the fourth electrode and the second connector and having electrical conductivity;
a metal layer having a thermal conductivity higher than that of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer, and disposed at least one of between the first bonding layer and the first electrode, between the second bonding layer and the second electrode, between the third bonding layer and the third electrode, and between the fourth bonding layer and the fourth electrode;
Equipped with
A semiconductor device in which the metal layer is arranged between the first bonding layer and the first electrode or between the second bonding layer and the second electrode when a first thickness of the first portion is smaller than a second thickness of a portion of the substrate that overlaps with the first electrode when viewed from above, and is arranged between the third bonding layer and the third electrode or between the fourth bonding layer and the fourth electrode when the first thickness is greater than the second thickness . the first thickness is less than the second thickness;
The semiconductor device according to claim 3 , wherein the metal layer is disposed both between the first bonding layer and the first electrode and between the second bonding layer and the second electrode. A conductive substrate;
a first chip including a first surface facing the substrate and a second surface located on the opposite side to the first surface, a first electrode electrically connected to the substrate being disposed on the first surface and a second electrode being disposed on the second surface;
a second chip including a third surface facing the second surface and a fourth surface located on the opposite side of the third surface, a third electrode being arranged on the third surface and a fourth electrode being arranged on the fourth surface, and an area viewed from above being larger than an area of the first chip;
a first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode;
a second connector electrically connected to the substrate and the fourth electrode, the second connector including a first portion located above the second chip, the first thickness of the first portion being smaller than a second thickness of a portion of the substrate overlapping with the first electrode when viewed from above;
A semiconductor device comprising: the second connector further includes a second portion extending from the substrate toward the first portion;
6. The semiconductor device according to claim 1 , wherein the thickness of said second portion is smaller than the thickness of said first portion. 7. The semiconductor device according to claim 1 , wherein an area of the first chip and an area of the second chip are each 10 mm ² or more and 25 mm ² or less when viewed from above.

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