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JP7706949B2 - Circuit board and high frequency module - Google Patents
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JP7706949B2 - Circuit board and high frequency module - Google Patents

Circuit board and high frequency module Download PDF

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JP7706949B2
JP7706949B2 JP2021101566A JP2021101566A JP7706949B2 JP 7706949 B2 JP7706949 B2 JP 7706949B2 JP 2021101566 A JP2021101566 A JP 2021101566A JP 2021101566 A JP2021101566 A JP 2021101566A JP 7706949 B2 JP7706949 B2 JP 7706949B2
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conductor
dielectric substrate
circuit board
layer
conductor line
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JP2023000630A (en
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直敬 石村
康明 小田
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JRC Mobility Inc
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Description

本開示は、回路基板における層間給電技術に関する。 This disclosure relates to interlayer power supply technology in circuit boards.

回路基板の反対面に給電する場合、単一のビア(via)導体を用いて給電するのが一般的である。しかし、ミリ波帯のように電波が短い場合、高周波信号が回路基板の反対面に給電されにくい問題があった。 When supplying power to the opposite side of a circuit board, it is common to use a single via conductor. However, when the radio waves are short, such as in the millimeter wave band, there is a problem in that it is difficult to supply high-frequency signals to the opposite side of the circuit board.

この問題を解決するため、ミリ波帯の高周波信号の層間給電技術が提案されている(例えば、特許文献1参照。)。特許文献1では、ビア導体の長さを高周波信号の波長λに対して所定の範囲にすることで、ミリ波帯の高周波信号を給電可能にする。このため、特許文献1では、ビア導体の長さによって層間の厚みが制限される問題がある。 To solve this problem, an interlayer power supply technology for millimeter-wave band high-frequency signals has been proposed (see, for example, Patent Document 1). In Patent Document 1, the length of the via conductor is set within a predetermined range with respect to the wavelength λ of the high-frequency signal, making it possible to supply a millimeter-wave band high-frequency signal. For this reason, Patent Document 1 has the problem that the interlayer thickness is limited by the length of the via conductor.

特開2003-204209号公報JP 2003-204209 A

そこで、本開示は、任意の層間の厚みを有する回路基板において、高周波信号を給電可能にすることを目的とする。 Therefore, the purpose of this disclosure is to make it possible to supply high-frequency signals to circuit boards with any inter-layer thickness.

本開示の回路基板は、
誘電体基板に配置されている第1の導体線路と、
前記第1の導体線路の配置されている誘電体基板を貫通するビア導体と、
誘電体基板のうちの前記第1の導体線路とは異なる面に配置され、前記ビア導体と接続されている第2の導体線路と、
前記ビア導体の周囲に配置され、前記ビア導体の貫通する誘電体基板と同じ誘電体基板を貫通する複数の貫通導体と、
前記第1の導体線路及び前記第2の導体線路の少なくとも一方に接続されている整合器と、
を備える。
The circuit board of the present disclosure includes:
a first conductor line disposed on a dielectric substrate;
a via conductor penetrating a dielectric substrate on which the first conductor line is disposed;
a second conductor line disposed on a surface of a dielectric substrate different from the surface of the first conductor line and connected to the via conductor;
a plurality of through conductors disposed around the via conductor and penetrating the same dielectric substrate as the dielectric substrate penetrated by the via conductor;
a matching unit connected to at least one of the first conductor line and the second conductor line;
Equipped with.

本開示の高周波モジュールは、
本開示の回路基板を用いた高周波モジュールであって、
前記第1の導体線路又は前記第2の導体線路を用いたアンテナ素子と、
前記アンテナ素子へ供給する高周波信号を生成する信号処理部と、
を備え、
前記ビア導体は、前記信号処理部からの高周波信号を前記アンテナ素子へ給電する。
The high-frequency module of the present disclosure includes:
A high-frequency module using a circuit board according to the present disclosure,
an antenna element using the first conductor line or the second conductor line;
a signal processing unit that generates a high frequency signal to be supplied to the antenna element;
Equipped with
The via conductor supplies a high frequency signal from the signal processing unit to the antenna element.

本開示は、ビア導体の周囲に複数の貫通導体が配置されている回路基板において、前記第1の導体線路及び前記第2の導体線路の少なくとも一方に整合器が配置されているため、任意の層間の厚みを有する回路基板においても高周波信号を給電することができる。 The present disclosure relates to a circuit board in which a plurality of through conductors are arranged around a via conductor, and a matching device is arranged on at least one of the first conductor line and the second conductor line, so that a high-frequency signal can be supplied even to a circuit board having any interlayer thickness.

回路基板の平面図であり、(a)は上面を示し、(b)は下面を示す。3A and 3B are plan views of a circuit board, in which FIG. 回路基板のA-A’断面構成例である。2 is an example of the A-A' cross-sectional structure of a circuit board. 本開示の回路基板の構成例である。1 illustrates an example of the configuration of a circuit board according to the present disclosure. 複数の貫通導体の配置例である。13 is an example of an arrangement of a plurality of through conductors. 複数の貫通導体の配置例である。13 is an example of an arrangement of a plurality of through conductors. 複数の貫通導体の配置例である。13 is an example of an arrangement of a plurality of through conductors. 実施形態の貫通導体の配置例である。4 is an example of an arrangement of through conductors according to an embodiment. B-B’断面構成の一例である。This is an example of the B-B' cross-sectional configuration. C-C’断面構成の一例である。This is an example of the C-C' cross-sectional configuration. 回路基板の製造過程の一例である。1 is an example of a manufacturing process for a circuit board. 回路基板の製造過程の一例である。1 is an example of a manufacturing process for a circuit board. 回路基板の製造過程の一例である。1 is an example of a manufacturing process for a circuit board. 誘電体基板の第2層及び第3層にずれがある場合の回路基板の断面構成例である。13 is a cross-sectional configuration example of a circuit board when there is a misalignment between a second layer and a third layer of a dielectric substrate. 誘電体基板の第2層及び第3層に形成するパターン抜き部の一例である。1 is an example of a pattern cut-out portion formed in a second layer and a third layer of a dielectric substrate. 第2層及び第3層のパターン抜き部を拡大した場合の回路基板の断面構成例である。4 is an example of a cross-sectional configuration of a circuit board when pattern cut-out portions of a second layer and a third layer are enlarged. 反対面への出力レベルの比較例であり、(a)はパターン抜き部を拡大しない場合を示し、(b)はパターン抜き部を拡大した場合を示す。13A and 13B are comparative examples of output levels to the opposite surface, in which (a) shows a case where the pattern cut-out portion is not enlarged, and (b) shows a case where the pattern cut-out portion is enlarged. 実施形態のアンテナ基板の一例である。2 is an example of an antenna substrate according to an embodiment.

以下、本開示の実施形態について、図面を参照しながら詳細に説明する。なお、本開示は、以下に示す実施形態に限定されるものではない。これらの実施の例は例示に過ぎず、本開示は当業者の知識に基づいて種々の変更、改良を施した形態で実施することができる。なお、本明細書及び図面において符号が同じ構成要素は、相互に同一のものを示すものとする。 The following describes in detail the embodiments of the present disclosure with reference to the drawings. Note that the present disclosure is not limited to the embodiments shown below. These implementation examples are merely illustrative, and the present disclosure can be implemented in various forms with various modifications and improvements based on the knowledge of those skilled in the art. Note that components with the same reference numerals in this specification and drawings are mutually identical.

(第1の実施形態)
図1及び図2に、本実施形態の回路基板の一例を示す。本実施形態の回路基板は、誘電体基板11と、誘電体基板11の上面に配置されている導体線路12と、誘電体基板11の下面に配置されている導体線路14と、を備える。導体線路12及び14は、誘電体基板11を貫通するビア導体16で接続されている。
(First embodiment)
1 and 2 show an example of a circuit board according to the present embodiment. The circuit board according to the present embodiment includes a dielectric substrate 11, a conductor line 12 disposed on the upper surface of the dielectric substrate 11, and a conductor line 14 disposed on the lower surface of the dielectric substrate 11. The conductor lines 12 and 14 are connected by a via conductor 16 that penetrates the dielectric substrate 11.

本実施形態では、誘電体基板11が第1層11-1から第4層11-4を備え、導体線路12が第1層11-1の上面に配置され、導体線路14が第4層11-4の下面に配置されている例を示す。導体線路12及び14は、それぞれ第1及び第2の導体線路として機能する。第1層11-1及び第4層11-4は、それぞれ第1及び第2の誘電体基板として機能する。 In this embodiment, an example is shown in which the dielectric substrate 11 includes a first layer 11-1 to a fourth layer 11-4, the conductor line 12 is disposed on the upper surface of the first layer 11-1, and the conductor line 14 is disposed on the lower surface of the fourth layer 11-4. The conductor lines 12 and 14 function as first and second conductor lines, respectively. The first layer 11-1 and the fourth layer 11-4 function as first and second dielectric substrates, respectively.

導体線路12及び14の少なくともいずれかは、アンテナ素子に接続されているか、或いはアンテナ素子に用いられている。例えば、導体線路12は部品実装面に配置されている給電線路として機能し、導体線路14はアンテナ素子として機能し、ビア導体16は給電導体として機能する。これにより、部品実装面からその反対面に配置されているアンテナ素子に給電するアンテナ基板を構成することができる。このような構成では、ミリ波帯のように電波が短い場合、ビア導体16のみでは導体線路12からの高周波信号が導体線路14に給電されにくい。 At least one of the conductor lines 12 and 14 is connected to an antenna element or is used in an antenna element. For example, the conductor line 12 functions as a power feed line arranged on the component mounting surface, the conductor line 14 functions as an antenna element, and the via conductor 16 functions as a power feed conductor. This makes it possible to configure an antenna board that feeds power from the component mounting surface to an antenna element arranged on the opposite surface. In this configuration, when the radio waves are short, such as in the millimeter wave band, it is difficult for the high-frequency signal from the conductor line 12 to be fed to the conductor line 14 using only the via conductor 16.

本実施形態の回路基板は、図3に示すように、ビア導体16の周囲に配置され、誘電体基板11を貫通する複数の貫通導体20を備える。複数の貫通導体20は、ビア導体16を中心とする点対称に配置されている。このように、本開示は、ビア導体16の周囲に複数の貫通導体20を配置することによる、同軸ケーブルを模した構造を採用する。これにより、本開示の回路基板は、給電のための導波路を確保し、同軸ケーブル形状を有する給電用変換器として機能させることができる。 As shown in FIG. 3, the circuit board of this embodiment includes a plurality of through conductors 20 that are arranged around the via conductor 16 and penetrate the dielectric substrate 11. The plurality of through conductors 20 are arranged in point symmetry with the via conductor 16 as the center. In this manner, the present disclosure employs a structure that mimics a coaxial cable by arranging a plurality of through conductors 20 around the via conductor 16. This allows the circuit board of the present disclosure to secure a waveguide for power supply and function as a power supply converter having a coaxial cable shape.

例えば、図4に示すように、6本の貫通導体22~24、26~28が、ビア導体16を中心とする半径φ20の同心円上に、ビア導体16を囲むように配置されている。貫通導体22~24、26~28は、ビア導体16と同様に、第1層11-1から第4層11-4の全てを貫通する。そのため、貫通導体22~24、26~28は、半径φ20の同心円上のうち、導体線路12と重ならない位置に配置されている。貫通導体22~24の間隔及び貫通導体26~28の間隔は、任意であるが、例えば、ビア導体16を中心とする点対称になるように、等しい間隔で配置されている。 For example, as shown in Fig. 4, six through conductors 22 to 24, 26 to 28 are arranged on a concentric circle of radius φ 20 centered on the via conductor 16 so as to surround the via conductor 16. The through conductors 22 to 24, 26 to 28, like the via conductor 16, penetrate all of the first layer 11-1 to the fourth layer 11-4. Therefore, the through conductors 22 to 24, 26 to 28 are arranged on the concentric circle of radius φ 20 at positions that do not overlap with the conductor line 12. The intervals between the through conductors 22 to 24 and the intervals between the through conductors 26 to 28 are arbitrary, but for example, they are arranged at equal intervals so as to be point symmetrical with the via conductor 16 at the center.

例えば、図5に示すように、8本の貫通導体21~28が、ビア導体16を中心とする半径φ20の同心円上に、ビア導体16を囲むように配置されている。図5の例では、導体線路12と重なる位置に配置されている複数の貫通導体21及び25を備える。この場合、貫通導体21及び25は、図6に示すように、第1層11-1及び第4層11-4の間に配置されている第2層11-2及び第3層11-3のみを貫通させる。 For example, as shown in Fig. 5, eight through conductors 21 to 28 are arranged on a concentric circle of radius φ 20 centered on the via conductor 16 so as to surround the via conductor 16. In the example of Fig. 5, a plurality of through conductors 21 and 25 are provided which are arranged at positions overlapping with the conductor line 12. In this case, the through conductors 21 and 25 penetrate only the second layer 11-2 and the third layer 11-3 which are arranged between the first layer 11-1 and the fourth layer 11-4 as shown in Fig. 6.

このように、本開示は、ビア導体16の周囲に複数の貫通導体を配置することで、給電のための導波路を確保する。本実施形態では、さらに、ビア導体16での高周波信号の伝送特性を調整するため、導体線路12及び14の延長線上に整合器12M及び14Mを備える。本開示の回路基板は、ビア導体16での高周波信号の伝送特性を調整するため、整合器12M及び14Mの長さ、給電元の導体線路12の線路幅の調整、給電先の導体線路14の線路幅の調整を行う。これにより、本開示は、ビア導体16を用いた反対面への給電を行うことを可能にする。 In this way, the present disclosure provides a waveguide for power supply by arranging multiple through conductors around the via conductor 16. In this embodiment, matching devices 12M and 14M are further provided on the extensions of the conductor lines 12 and 14 in order to adjust the transmission characteristics of the high-frequency signal in the via conductor 16. In order to adjust the transmission characteristics of the high-frequency signal in the via conductor 16, the circuit board of the present disclosure adjusts the length of the matching devices 12M and 14M, the line width of the conductor line 12 that is the power supply source, and the line width of the conductor line 14 that is the power supply destination. This makes it possible for the present disclosure to supply power to the opposite surface using the via conductor 16.

図7に、本実施形態の貫通導体の配置例を示す。この例では、導体線路12に沿って貫通導体31及び32が配置され、整合器12M及び14Mの周囲に貫通導体33~35が配置されている。図8及び図9に、B-B’断面構成及びC-C’断面構成の一例を示す。貫通導体33~35は、図8に示すように、誘電体基板11の第1層11-1から第4層11-4までを貫通する。貫通導体32は、図9に示すように、誘電体基板11の第1層11-1及び第4層11-4のみを貫通する。貫通導体31も、貫通導体32と同様に、誘電体基板11の第1層11-1及び第4層11-4のみを貫通する。 Figure 7 shows an example of the arrangement of the through conductors in this embodiment. In this example, the through conductors 31 and 32 are arranged along the conductor line 12, and the through conductors 33 to 35 are arranged around the matching units 12M and 14M. Figures 8 and 9 show an example of the B-B' cross-sectional configuration and the C-C' cross-sectional configuration. As shown in Figure 8, the through conductors 33 to 35 penetrate from the first layer 11-1 to the fourth layer 11-4 of the dielectric substrate 11. As shown in Figure 9, the through conductor 32 penetrates only the first layer 11-1 and the fourth layer 11-4 of the dielectric substrate 11. Like the through conductor 32, the through conductor 31 also penetrates only the first layer 11-1 and the fourth layer 11-4 of the dielectric substrate 11.

以上説明したように、本実施形態の回路基板は、ビア導体16の周囲に複数の貫通導体を配置することで同軸ケーブル形状の変換器を構成し、導体線路12及び14に整合器12M及び14Mを設けている。これにより、本実施形態の回路基板は、任意の層間の厚みを有する回路基板に対し、高周波信号を給電することができる。 As described above, the circuit board of this embodiment forms a coaxial cable-shaped converter by arranging multiple through conductors around the via conductor 16, and provides matching devices 12M and 14M on the conductor lines 12 and 14. This allows the circuit board of this embodiment to supply high-frequency signals to a circuit board having any interlayer thickness.

ここで、本実施形態では、導体線路12及び14の両方に整合器12M及び14Mを備える例を示したが、整合器12M及び14Mの両方を備える必要はなく、整合器12M及び14Mのいずれか一方であっても本開示の作用・効果が得られる。 In this embodiment, an example is shown in which matching devices 12M and 14M are provided on both conductor lines 12 and 14, but it is not necessary to provide both matching devices 12M and 14M, and the action and effect of the present disclosure can be obtained even if only one of matching devices 12M and 14M is provided.

なお、本実施形態では回路基板が部品実装面からその反対面に給電する例を示したが、本開示はビア導体16を用いて高周波信号を給電する任意の回路基板に適用することができる。例えば、後述するように、誘電体基板11の両面にアンテナ素子が形成されていてもよい。 In this embodiment, an example is shown in which power is supplied from the component mounting surface to the opposite surface of the circuit board, but the present disclosure can be applied to any circuit board that supplies high-frequency signals using via conductors 16. For example, as described below, antenna elements may be formed on both sides of the dielectric substrate 11.

また、本実施形態では、ビア導体16及び貫通導体22~24、26~28が第1層11-1から第4層11-4までを貫通する例を示したが、本開示はこれに限定されない。例えば、導体線路12及び14は異なる任意の面に配置することが可能であり、ビア導体16は導体線路12と14を接続可能な任意の長さでありうる。そのため、ビア導体16及び貫通導体22~24、26~28は同じ誘電体基板を貫通していればよく、例えば第1層11-1から第3層11-3までを貫通し、第4層11-4を貫通しない構成であってもよい。この場合、貫通導体21及び25は第2層11-2のみを貫通する。 In addition, in this embodiment, an example has been shown in which the via conductor 16 and the through conductors 22 to 24, 26 to 28 penetrate from the first layer 11-1 to the fourth layer 11-4, but the present disclosure is not limited to this. For example, the conductor lines 12 and 14 can be arranged on any different planes, and the via conductor 16 can be of any length that can connect the conductor lines 12 and 14. Therefore, the via conductor 16 and the through conductors 22 to 24, 26 to 28 only need to penetrate the same dielectric substrate, and may be configured to penetrate, for example, from the first layer 11-1 to the third layer 11-3, but not the fourth layer 11-4. In this case, the through conductors 21 and 25 penetrate only the second layer 11-2.

本実施形態では誘電体基板11の一例として、第1層~第4層の4つの層を備える例を示すが、本開示の回路基板に備わる誘電体基板の層の数は1以上の任意の数でありうる。例えば、第1層11-1と第4層11-4の間に配置されている誘電体基板は3層以上であってもよい。この場合、第1層11-1と第4層11-4の間に配置されている3層以上の誘電体基板が第3の誘電体基板として機能し、貫通導体21及び25は、第3の誘電体基板のうちの任意の数の誘電体基板を貫通する。 In this embodiment, an example of the dielectric substrate 11 is shown having four layers, the first layer to the fourth layer, but the number of layers of the dielectric substrate provided in the circuit board of the present disclosure can be any number equal to or greater than one. For example, the dielectric substrate disposed between the first layer 11-1 and the fourth layer 11-4 may have three or more layers. In this case, the three or more layers of dielectric substrate disposed between the first layer 11-1 and the fourth layer 11-4 function as a third dielectric substrate, and the through conductors 21 and 25 penetrate any number of the third dielectric substrates.

(第2の実施形態)
第1の実施形態で説明したビア導体16を配置する場合、第1層11-1~第4層11-4を作製し(図10)、第2層11-2及び第3層11-3をプリプレグ13で張り合わせ、これらを貫通する貫通導体21及び25を形成する(図11)。そして、第1層11-1から第4層11-4まで全てを張り合わせ、ビア導体16を配置する(図12)。
Second Embodiment
When arranging the via conductors 16 described in the first embodiment, the first layer 11-1 to the fourth layer 11-4 are fabricated (FIG. 10), the second layer 11-2 and the third layer 11-3 are laminated with the prepreg 13, and the through conductors 21 and 25 that penetrate these layers are formed (FIG. 11). Then, the first layer 11-1 to the fourth layer 11-4 are all laminated together, and the via conductors 16 are arranged (FIG. 12).

第2層11-2及び第3層11-3をプリプレグ13で張り合わせる前に、図11に示すような、第2層11-2及び第3層11-3に、銅箔層などによる導体パターンが無い領域(パターン抜き部と称する)を形成する。例えば、第2層11-2の上面にパターン抜き部62-1を形成し、第2層11-2の下面及び第3層11-3の上面にパターン抜き部62を形成し、第3層11-3の下面にパターン抜き部62-4を形成する。また、第1層11-1から第4層11-4まで全てを張り合わせる前に、第1層11-1の下面にパターン抜き部61を形成し、第4層11-4の上面にパターン抜き部63を形成する。 Before laminating the second layer 11-2 and the third layer 11-3 with the prepreg 13, as shown in FIG. 11, regions (called pattern cutouts) that do not have a conductor pattern made of a copper foil layer or the like are formed on the second layer 11-2 and the third layer 11-3. For example, a pattern cutout 62-1 is formed on the upper surface of the second layer 11-2, a pattern cutout 62 is formed on the lower surface of the second layer 11-2 and the upper surface of the third layer 11-3, and a pattern cutout 62-4 is formed on the lower surface of the third layer 11-3. In addition, before laminating all of the first layer 11-1 to the fourth layer 11-4, a pattern cutout 61 is formed on the lower surface of the first layer 11-1, and a pattern cutout 63 is formed on the upper surface of the fourth layer 11-4.

第1層11-1~第4層11-4を張り合わせる際に、第2層11-2及び第3層11-3にずれがある場合、図13に示すように、第1層11-1の下面のパターン抜き部61と第2層11-2の上面のパターン抜き部62-1との間にずれΔPが生じ、第4層11-4の上面のパターン抜き部63と第3層11-3の下面のパターン抜き部62-4との間にずれΔPが生じる。このずれΔPにより、給電経路が歪になる。そこで、本実施形態の回路基板は、パターン抜き部62-1及び62-4の直径φ62を拡大する。 If there is a misalignment between the second layer 11-2 and the third layer 11-3 when the first layer 11-1 to the fourth layer 11-4 are bonded together, as shown in Fig. 13, a misalignment ΔP occurs between the pattern cut-out 61 on the lower surface of the first layer 11-1 and the pattern cut-out 62-1 on the upper surface of the second layer 11-2, and a misalignment ΔP occurs between the pattern cut-out 63 on the upper surface of the fourth layer 11-4 and the pattern cut-out 62-4 on the lower surface of the third layer 11-3. This misalignment ΔP causes distortion of the power supply path. Therefore, in the circuit board of this embodiment, the diameter φ 62 of the pattern cut-outs 62-1 and 62-4 is enlarged.

図14に、パターン抜き部62-1及び62-4の一例を示す。本実施形態では、パターン抜き部62-1及び62-4がビア導体16の直径に対して余裕をもって形成されている。例えば、パターン抜き部62-1及び62-4の内径φ62とビア導体16の直径の差は、回路基板の製造誤差よりも大きい。パターン抜き部62-1及び62-4は、貫通導体22~24、26~28と重なっていてもよい。すなわち、パターン抜き部62-1及び62-4内に、貫通導体22~24、26~28の少なくとも一部又は全部が配置されていてもよい。この場合、図15に示すように、貫通導体21及び25の位置がパターン抜き部62-1及び62-4に重なるため、貫通導体21及び25を配置しない。 FIG. 14 shows an example of the pattern cutouts 62-1 and 62-4. In this embodiment, the pattern cutouts 62-1 and 62-4 are formed with a margin relative to the diameter of the via conductor 16. For example, the difference between the inner diameter φ 62 of the pattern cutouts 62-1 and 62-4 and the diameter of the via conductor 16 is larger than the manufacturing error of the circuit board. The pattern cutouts 62-1 and 62-4 may overlap the through conductors 22 to 24, 26 to 28. That is, at least a part or all of the through conductors 22 to 24, 26 to 28 may be disposed in the pattern cutouts 62-1 and 62-4. In this case, as shown in FIG. 15, the positions of the through conductors 21 and 25 overlap the pattern cutouts 62-1 and 62-4, so the through conductors 21 and 25 are not disposed.

図16に、出力レベルの比較例を示す。図16(a)は、第2層11-2及び第3層11-3に貫通導体21及び25を配置し、パターン抜き部62-1及び62-4を拡大しない場合を示す。図16(b)は、パターン抜き部62-1及び62-4を拡大し、貫通導体21及び25を配置しない場合を示す。いずれの場合も、第1層11-1及び第4層11-4に対して第2層11-2及び第3層11-3を-200μm、-100μm、0μm、100μm、200μmずらした場合を示す。パターン抜き部62-1及び62-4を拡大しない場合、図16(a)に示すように、出力レベルの差は約2dBであった。パターン抜き部62-1及び62-4を拡大した場合、図16(b)に示すように、出力レベルの差は約0.6dBであった。 Figure 16 shows comparative examples of output levels. Figure 16(a) shows a case where the through conductors 21 and 25 are arranged on the second layer 11-2 and the third layer 11-3, and the pattern cutouts 62-1 and 62-4 are not enlarged. Figure 16(b) shows a case where the pattern cutouts 62-1 and 62-4 are enlarged, and the through conductors 21 and 25 are not arranged. In both cases, the second layer 11-2 and the third layer 11-3 are shifted by -200 μm, -100 μm, 0 μm, 100 μm, and 200 μm relative to the first layer 11-1 and the fourth layer 11-4. When the pattern cutouts 62-1 and 62-4 are not enlarged, the difference in output level was about 2 dB, as shown in Figure 16(a). When the pattern cutouts 62-1 and 62-4 are enlarged, the difference in output level was about 0.6 dB, as shown in Figure 16(b).

したがって、パターン抜き部62-1及び62-4の直径φ62を拡大することで、第1層11-1~第4層11-4を張り合わせのずれに起因する給電経路の変形度合いを軽減することが出来る。その結果、層間張り合わせのずれに対する出力レベルのばらつきを大きく低減することができる。 Therefore, by enlarging the diameter φ62 of the pattern cut-out portions 62-1 and 62-4, it is possible to reduce the degree of deformation of the power supply path caused by misalignment of the first layer 11-1 to the fourth layer 11-4, and as a result, it is possible to significantly reduce the variation in output level due to misalignment of the interlayer bonding.

(第3の実施形態)
本開示のビア導体16は、反対面への給電が可能であることに加え、2分岐の分配器としても併用できる。そのため、本開示の回路基板は、アンテナの分配器に適用することができる。
Third Embodiment
The via conductor 16 of the present disclosure can feed power to the opposite surface and can also be used as a two-branch distributor, so the circuit board of the present disclosure can be applied to an antenna distributor.

図17は、本実施形態のアンテナ基板の一例を示す。本実施形態のアンテナ基板は、導体線路12、14及びビア導体16を複数備え、導体線路12を用いて誘電体基板11の同一面に複数のアンテナ素子70が構成されている。各アンテナ素子70は、誘電体基板11を貫通するビア導体16を用いて誘電体基板11の反対面の導体線路14と接続されている。これにより、中央にビア導体16が配置されている中央給電のアレイアンテナが構成されている。 Figure 17 shows an example of an antenna board of this embodiment. The antenna board of this embodiment includes a plurality of conductor lines 12, 14 and via conductors 16, and a plurality of antenna elements 70 are formed on the same surface of the dielectric board 11 using the conductor lines 12. Each antenna element 70 is connected to a conductor line 14 on the opposite surface of the dielectric board 11 using a via conductor 16 that penetrates the dielectric board 11. This forms a centrally fed array antenna with the via conductor 16 located in the center.

本開示は、貫通導体22~24、26~28を同軸ケーブル形状に配置し、図示されていない反対の面に整合器14Mを配置することで、整合器を備えた給電線路により給電を行う。これにより、本実施形態では、2分岐用の給電器を省スペースで実現することができる。したがって、本開示は、アンテナ素子70の間隔D70を、アンテナ素子70の送受信波長λの一波長未満、例えばλ/2程度の狭い間隔で設計することが可能となる。 In the present disclosure, the through conductors 22-24, 26-28 are arranged in a coaxial cable shape, and a matching device 14M is arranged on the opposite side (not shown), so that power is fed from a feeder line equipped with a matching device. As a result, in this embodiment, a two-branch feeder can be realized in a small space. Therefore, in the present disclosure, it is possible to design the spacing D70 of the antenna elements 70 to be less than one wavelength of the transmission and reception wavelength λ of the antenna elements 70, for example, a narrow spacing of about λ/2.

以上において説明した本開示の回路基板は、部品実装面にMMIC(Monolithic Microwave Integrated Circuit)などの信号処理部が配置され、信号処理部からの高周波信号を導体線路12及び14に供給する、任意の高周波モジュールに適用することができる。 The circuit board of the present disclosure described above can be applied to any high-frequency module in which a signal processing unit such as an MMIC (Monolithic Microwave Integrated Circuit) is arranged on the component mounting surface and a high-frequency signal from the signal processing unit is supplied to the conductor lines 12 and 14.

信号処理部における処理は任意である。例えば、信号処理部は、高周波信号を生成し、これを用いてアンテナ素子を介した信号の送受信を行う。これにより、送受信モジュールを構成することができる。例えば、信号処理部は、レーダ用の送信波を生成して送信アンテナに供給し、受信アンテナで受信された対象物からの反射波を用いて対象物を検知する。これにより、レーダモジュールを構成することができる。このほか、本開示の高周波モジュールは、導体線路12及び14に高周波信号を供給する任意のモジュールでありうる。 The processing in the signal processing unit is arbitrary. For example, the signal processing unit generates a high-frequency signal and uses it to transmit and receive signals via the antenna element. This makes it possible to configure a transmission and reception module. For example, the signal processing unit generates a transmission wave for radar and supplies it to a transmitting antenna, and detects an object using the reflected wave from the object received by the receiving antenna. This makes it possible to configure a radar module. In addition, the high-frequency module of the present disclosure may be any module that supplies high-frequency signals to the conductor lines 12 and 14.

ここで、高周波信号は、24GHz、28GHz、36GHz、39GHz、60GHz、76GHz、79GHzなどのミリ波帯の高周波信号のほか、アンテナを用いて送受信可能な任意の周波数の高周波信号でありうる。 Here, the high-frequency signal may be a millimeter-wave band high-frequency signal of 24 GHz, 28 GHz, 36 GHz, 39 GHz, 60 GHz, 76 GHz, 79 GHz, etc., or a high-frequency signal of any frequency that can be transmitted and received using an antenna.

本開示は情報通信産業に適用することができる。 This disclosure can be applied to the information and communications industry.

11:誘電体基板
12、14:導体線路
13:プリプレグ
16:ビア導体
17、18:導体
19:グランド導体
20、21~28、31~35:貫通導体
41、42:ランド
61、62-1、62-4、63:パターン抜き部
70:アンテナ素子
11: dielectric substrate 12, 14: conductor line 13: prepreg 16: via conductor 17, 18: conductor 19: ground conductor 20, 21-28, 31-35: through conductor 41, 42: lands 61, 62-1, 62-4, 63: pattern cut-out portion 70: antenna element

Claims (7)

第1の誘電体基板と第2の誘電体基板との間に第3の誘電体基板が配置されている誘電体基板と、
前記第1の誘電体基板に配置されている第1の導体線路と、
前記第2の誘電体基板に配置されている第2の導体線路と、
前記誘電体基板を貫通し、前記第1の導体線路と前記第2の導体線路を接続するビア導体と、
前記ビア導体を中心とする同心円上に配置され、前記誘電体基板を貫通する第1の複数の貫通導体と、
前記同心円と前記第1の導体線路又は前記第2の導体線路との重なる位置に、前記第3の誘電体基板のみを貫通する第2の複数の貫通導体と、
前記第1の導体線路及び前記第2の導体線路の少なくとも一方に接続されている整合器と、
を備え回路基板。
a dielectric substrate including a third dielectric substrate disposed between a first dielectric substrate and a second dielectric substrate;
a first conductor line disposed on the first dielectric substrate;
a second conductor line disposed on the second dielectric substrate;
a via conductor that passes through the dielectric substrate and connects the first conductor line and the second conductor line;
a first plurality of through conductors arranged on a concentric circle centered on the via conductor and penetrating the dielectric substrate;
a second plurality of through conductors penetrating only the third dielectric substrate at positions where the concentric circles and the first conductor line or the second conductor line overlap ;
a matching unit connected to at least one of the first conductor line and the second conductor line;
A circuit board comprising :
記第3の誘電体基板の前記第1の導体線路側に配置されている導体及び前記第3の誘電体基板の前記第2の導体線路側に配置されている導体は、前記ビア導体の配置されている位置に、導体の配置されていないパターン抜き部を備え、
前記パターン抜き部の内径と前記ビア導体の直径との差が、当該回路基板の製造誤差よりも大きい、
請求項1に記載の回路基板。
a conductor arranged on a side of the first conductor line of the third dielectric substrate and a conductor arranged on a side of the second conductor line of the third dielectric substrate each include a pattern cut-out portion in which no conductor is arranged, at a position where the via conductor is arranged;
a difference between an inner diameter of the pattern cut-out portion and a diameter of the via conductor is greater than a manufacturing error of the circuit board;
The circuit board according to claim 1 .
前記第3の誘電体基板に形成されている前記パターン抜き部と、前記第1の誘電体基板及び前記第2の誘電体基板を貫通する前記第1の複数の貫通導体と、が重なっている、
請求項に記載の回路基板。
the pattern cut-out portion formed in the third dielectric substrate and the first plurality of through conductors penetrating the first dielectric substrate and the second dielectric substrate overlap each other;
The circuit board according to claim 2 .
前記第1の複数の貫通導体は、前記ビア導体を中心とする点対称に配置されている、
請求項1又は2に記載の回路基板。
the first plurality of through conductors are arranged point symmetrically with respect to the via conductor;
The circuit board according to claim 1 or 2 .
前記第1の導体線路、前記第2の導体線路及び前記ビア導体を複数備え、
前記第1の導体線路又は前記第2の導体線路を用いて複数のアンテナ素子が構成され、
前記複数のアンテナ素子の間隔が、各アンテナ素子の送信波長又は受信波長の一波長未満である、
請求項1からのいずれかに記載の回路基板。
a plurality of the first conductor lines, a plurality of the second conductor lines, and a plurality of the via conductors;
A plurality of antenna elements are configured using the first conductor line or the second conductor line,
The spacing between the antenna elements is less than one wavelength of the transmission or reception wavelength of each antenna element.
5. The circuit board according to claim 1.
前記送信波長又は前記受信波長は、ミリ波帯に含まれる波長である、
請求項に記載の回路基板。
The transmission wavelength or the reception wavelength is a wavelength included in the millimeter wave band.
The circuit board according to claim 5 .
請求項1からのいずれかに記載の回路基板を用いた高周波モジュールであって、
前記第1の導体線路又は前記第2の導体線路を用いたアンテナ素子と、
前記アンテナ素子へ供給する高周波信号を生成する信号処理部と、
を備え、
前記ビア導体は、前記信号処理部からの高周波信号を前記アンテナ素子へ給電する、
高周波モジュール。
A high-frequency module using the circuit board according to any one of claims 1 to 6 ,
an antenna element using the first conductor line or the second conductor line;
a signal processing unit that generates a high frequency signal to be supplied to the antenna element;
Equipped with
The via conductor supplies a high-frequency signal from the signal processing unit to the antenna element.
High frequency module.
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Publication number Priority date Publication date Assignee Title
JP2010073891A (en) 2008-09-18 2010-04-02 Nec Corp Printed circuit board and method of manufacturing the same
JP2014096742A (en) 2012-11-12 2014-05-22 Mitsubishi Electric Corp Array antenna device and process of manufacturing the same
JP2019080193A (en) 2017-10-25 2019-05-23 株式会社Soken High frequency transmission line
JP2019096929A (en) 2017-11-17 2019-06-20 株式会社Soken High frequency transmission line
JP2021061313A (en) 2019-10-07 2021-04-15 株式会社デンソー High-frequency line connection structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010073891A (en) 2008-09-18 2010-04-02 Nec Corp Printed circuit board and method of manufacturing the same
JP2014096742A (en) 2012-11-12 2014-05-22 Mitsubishi Electric Corp Array antenna device and process of manufacturing the same
JP2019080193A (en) 2017-10-25 2019-05-23 株式会社Soken High frequency transmission line
JP2019096929A (en) 2017-11-17 2019-06-20 株式会社Soken High frequency transmission line
JP2021061313A (en) 2019-10-07 2021-04-15 株式会社デンソー High-frequency line connection structure

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