JP7707955B2 - Silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a SiC semiconductor device made of silicon carbide (hereinafter simply referred to as SiC).

Conventionally, a SiC semiconductor device has been proposed in which a MOSFET (short for metal oxide semiconductor field effect transistor) having a base layer, a source region, and the like is formed on a semiconductor substrate made of SiC. Specifically, this SiC semiconductor device includes a semiconductor substrate made of SiC in which an ^n- type drift layer and a p-type base layer are stacked in order on an n ⁺ type substrate, and a source region is formed on a surface layer of the base layer. In addition, in this SiC semiconductor device, a trench is formed that penetrates the base layer and the source region and reaches the drift layer. Then, a gate insulating film and a gate electrode are formed in order in the trench.

A first electrode is disposed on one side of the semiconductor substrate, and is connected to the source region and the base layer. A second electrode is disposed on the other side of the semiconductor substrate, and is connected to the substrate that constitutes the drain region.

In such SiC semiconductor devices, it has been reported that the semiconductor substrate made of SiC contains basal plane dislocations (hereinafter also referred to as BPDs). In addition, in such SiC semiconductor devices, a parasitic diode is formed including a base layer and a drift layer. In such SiC semiconductor devices, when the parasitic diode is activated, holes are injected into the drift layer, and the injected holes recombine with electrons in the BPDs to form single Shockley stacking faults (hereinafter also referred to simply as SSFs). SSFs are defects that are more likely to degrade the characteristics of SiC semiconductor devices than BPDs.

For this reason, for example, Patent Document 1 proposes forming a lifetime killer in the drift layer to reduce the hole concentration when the parasitic diode is operating, making it difficult for an SSF to form.

JP 2019-3969 A

However, when a SiC semiconductor device is constructed by forming a lifetime killer in the drift layer, there is a concern that the on-resistance may increase.

In view of the above, the present invention aims to provide a SiC semiconductor device that can suppress the occurrence of SSF while suppressing an increase in on-resistance.

In order to achieve the above object, claims 1 , 3, and 5 provide a SiC semiconductor device made of SiC, comprising: a semiconductor substrate (10) made of SiC and having one surface (10a) and another surface (10b) opposite to the one surface; an element region (1) formed in the semiconductor substrate and having a switching element constituting a parasitic diode; a diode region (2) formed in the semiconductor substrate and having a diode element; a first electrode (30) disposed on one surface of the semiconductor substrate and electrically connected to the switching element and the diode element; and a second electrode (33) disposed on the other surface of the semiconductor substrate and electrically connected to the switching element and the diode element, and the diode element formed in the diode region has a smaller forward voltage at which a forward current begins to flow than a parasitic diode.
In addition, in claim 1, contact regions (23a, 23b) are formed in the element region and the diode region at portions connected to the first electrode, and the contact region formed in the diode region has a higher impurity concentration than the contact region formed in the element region.
In claim 3, a metal silicide layer (31 a, 31 b) is formed in a portion of the semiconductor substrate that is connected to the first electrode, and the metal silicide layer formed in the diode region is made of a material that has a lower contact resistance with the first electrode than the metal silicide layer formed in the element region.
In claim 5, a guard region insulated from the first electrode is disposed between the element region and the diode region, and the length of the guard region disposed between the element region and the diode region along the arrangement direction of the element region and the diode region is set to be equal to or longer than the diffusion length of holes.

According to this, the forward voltage of the diode region is set lower than the forward voltage of the parasitic diode formed in the element region. Therefore, when the SiC semiconductor device operates as a diode, the diode region operates more easily and the parasitic diode in the element region operates less easily. Therefore, it is possible to suppress the formation of an SSF in the element region.

In addition, in this SiC semiconductor device, the diode region is disposed to prevent SSF from being formed in the element region. Therefore, the on-resistance of the element region can be prevented from increasing compared to the case where a lifetime killer or the like is formed in the element region. In other words, this SiC semiconductor device can prevent SSF from occurring in the element region (i.e., in the switching element) while preventing the on-resistance from increasing.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

FIG. 1 is a plan view of a SiC semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. FIG. FIG. 13 is a diagram showing the relationship between forward voltage and forward current. FIG. 11 is a cross-sectional view of a SiC semiconductor device according to a second embodiment. FIG. 13 is a diagram showing the relationship between forward voltage and forward current. FIG. 11 is a cross-sectional view of a SiC semiconductor device according to a third embodiment. FIG. 13 is a plan view of a SiC semiconductor device according to a fourth embodiment. FIG. 13 is a plan view of a SiC semiconductor device in a fifth embodiment.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. The SiC semiconductor device of the present embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

As shown in FIG. 1, the SiC semiconductor device has a rectangular shape in plan view and includes an element region 1, a diode region 2, a guard region 3 surrounding the diode region 2, and an outer periphery region 4 surrounding the element region 1, the diode region 2, and the guard region 3. In this embodiment, a MOSFET is formed as a switching element in the element region 1, and a diode element is formed in the diode region 2.

The guard region 3 is also disposed between the element region 1 and the diode region 2 by being disposed so as to surround the diode region 2. In addition, the peripheral region 4 is formed with a pad portion 5 and the like that is connected to a gate electrode 27 and the like, which will be described later.

In the following description, one direction in the surface direction of the substrate 11 described later is defined as the X-axis direction, the direction intersecting with the one direction in the surface direction of the substrate is defined as the Y-axis direction, and the direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other. In FIG. 1, the up-down direction of the paper corresponds to the X-axis direction, the left-right direction of the paper corresponds to the Y-axis direction, and the depth direction of the paper corresponds to the Z-axis direction. In the following description, when indicating the orientation of a crystal, a bar (-) should be placed above the desired number, but due to the limitations on expression based on electronic filing, a bar is placed before the desired number in this specification.

As shown in Figures 2 and 3, the SiC semiconductor device is constructed using a semiconductor substrate 10 that is made of 4H-SiC type SiC as a whole, and contains BPD. In this embodiment, the X-axis direction is the direction along the [1-100] direction, and the Y-axis direction is the direction along the [11-20] direction.

Specifically, the semiconductor substrate 10 includes an n ⁺ type substrate 11 made of a SiC single crystal. In this embodiment, the substrate 11 has an off angle of 0 to 8° in the Y-axis direction with respect to the (0001) Si-plane, an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 ¹⁹ /cm ³ , and a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes the drain region and constitutes a high concentration layer. The substrate 11 also contains BPDs. As described later, an epitaxial layer or the like is disposed on the substrate 11, thereby forming the semiconductor substrate 10 containing BPDs.

An n ^- type buffer layer 12 made of SiC is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration between that of the substrate 11 and a low concentration layer 13 described below, and has a thickness of about 1 μm.

On the surface of the buffer layer 12, for example, an n-type low concentration layer 13 made of SiC having an n ^- type impurity concentration of 5.0 to 10.0×10 ¹⁵ /cm ³ and a thickness of about 10 to 15 μm is formed by epitaxial growth. The impurity concentration of this low concentration layer 13 may be constant in the Z-axis direction, but it is preferable that the concentration distribution is inclined so that the low concentration layer 13 is higher on the substrate 11 side than on the side away from the substrate 11. For example, it is preferable that the impurity concentration of the low concentration layer 13 is higher by about 2.0×10 ¹⁵ /cm ³ in a portion about 3 to 5 μm from the surface of the substrate 11 than in other portions. By adopting such a configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced.

In the surface layer of the low concentration layer 13, the JFET section 14 and the first deep layer 15 are formed in the element region 1. In this embodiment, the JFET section 14 and the first deep layer 15 of the element region 1 are each configured to extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. In other words, the JFET section 14 and the first deep layer 15 of the element region 1 are configured to be stripes extending along the X-axis direction in the normal direction (hereinafter simply referred to as the normal direction) to the surface of the substrate 11, and are arranged alternately along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, it can also be said that when viewed from the normal direction to the surface of the substrate 11.

The JFET section 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a depth of 0.3 to 1.5 μm. In this embodiment, the JFET section 14 has an n-type impurity concentration of 7.0×10 ¹⁶ to 5.0×10 ¹⁷ /cm ^3. The first deep layer 15 has a p-type impurity concentration of boron or the like of 2.0×10 ¹⁷ to 2.0×10 ¹⁸ /cm ³ .

The first deep layer 15 in this embodiment is formed shallower than the JFET section 14. In other words, the first deep layer 15 is formed so that its bottom is located within the JFET section 14. In other words, the first deep layer 15 is formed so that the JFET section 14 is located between it and the low concentration layer 13.

In addition, a first deep layer 15 is formed entirely in the surface layer of the low concentration layer 13 in the diode region 2. Furthermore, a first floating region 16 is formed in the guard region 3 in the surface layer of the low concentration layer 13. A plurality of first floating regions 16 are formed so as to surround the diode region 2. In this embodiment, the first floating region 16 is formed concentrically, for example, in a rectangular frame shape with rounded corners. However, this first floating region 16 may be formed concentrically in another frame shape, such as a circular frame shape, instead of a rectangular frame shape.

The first deep layer 15 formed in the element region 1 and the diode region 2 and the first floating region 16 formed in the guard region 3 each have the same depth and thickness on their lower surfaces facing the substrate 11, and have the same p-type impurity concentration.

Then, a current spreading layer 17, a second deep layer 18, a base layer 21, a source region 22, and a contact region 23a are formed on the JFET portion 14 and the first deep layer 15 in the element region 1. The second deep layer 18, a base layer 21, and a contact region 23b are formed on the first deep layer 15 in the diode region 2. The current spreading layer 17 and a second floating region 24 are formed on the low concentration layer 13 and the first deep layer 15 in the guard region 3.

The current spreading layer 17 is composed of an n-type impurity layer, and is connected to the JFET section 14 in the element region 1. Therefore, in this embodiment, the low concentration layer 13, the JFET section 14, and the current spreading layer 17 are connected, and these constitute the drift layer 19.

The second deep layer 18 has a thickness equal to that of the current spreading layer 17. In the element region 1, the current spreading layer 17 and the second deep layer 18 extend in a direction intersecting the longitudinal direction of the striped portion of the JFET section 14 and the first deep layer 15. In this embodiment, the current spreading layer 17 and the second deep layer 18 extend in the Y-axis direction as the longitudinal direction, and are arranged in a layout in which multiple layers are alternately arranged in the X-axis direction. The formation pitch of the current spreading layer 17 and the second deep layer 18 is set to match the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed to sandwich the trench 25 described later.

On the other hand, in the diode region 2, the second deep layer 18 is formed entirely on the first deep layer 15.

The base layer 21 is of p-type, and in the element region 1, it is formed on the current spreading layer 17 and the second deep layer 18. In the diode region 2, the base layer 21 is formed on the second deep layer 18.

In the element region 1, an n ⁺ type source region 22 and a p ⁺ type contact region 23a are formed in a surface layer portion of the base layer 21. Specifically, the source region 22 is formed so as to contact a side surface of a trench 25 described later. The contact region 23a is formed on the opposite side of the source region 22 to the trench 25 described later. In this embodiment, the source region 22 constitutes an impurity region.

In the diode region 2 , ap ⁺ type contact region 23 b is formed in a surface layer portion of the base layer 21 .

In the guard region 3, the current spreading layer 17 is arranged to form one surface 10a of the semiconductor substrate 10 described later. In the guard region 3, a plurality of second floating regions 24 are formed in the surface layer of the current spreading layer 17 so as to surround the diode region 2. In this embodiment, the second floating regions 24 are formed concentrically, for example, in the shape of a rectangular frame with rounded corners. However, the second floating regions 24 may be formed concentrically in other frame shapes, such as a circular frame, instead of a rectangular frame shape.

The second deep layer 18 formed in the element region 1 and the diode region 2, and the second floating region 24 formed in the guard region 3 each have the same depth and thickness on the bottom surface facing the substrate 11, and have the same p-type impurity concentration.

In this embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, buffer layer 12, low concentration layer 13, JFET section 14, first deep layer 15, first floating region 16, current spreading layer 17, second deep layer 18, base layer 21, source region 22, second floating region 24, etc. One surface 10a of the semiconductor substrate 10 is configured to include the source region 22, contact regions 23a, 23b, current spreading layer 17, second floating region 24, etc., and the other surface 10b of the semiconductor substrate 10 is configured to include the substrate 11. In addition, in the diode region 2, a diode element is configured in which the substrate 11, buffer layer 12, and low concentration layer 13 are the cathode, and the first deep layer 15, second deep layer 18, base layer 21, and contact region 23b are the anode.

In the semiconductor substrate 10, a trench 25 having a width of, for example, 1.4 to 2.0 μm is formed in the element region 1 so that it penetrates the source region 22, base layer 21, etc. to reach the current spreading layer 17 and has its bottom surface located within the current spreading layer 17. The trench 25 is formed so that it does not reach the JFET portion 14 and the first deep layer 15. In other words, the trench 25 is formed so that the JFET portion 14 and the first deep layer 15 are located below the bottom surface.

The trenches 25 are formed in a stripe pattern with multiple trenches 25 extending along the Y-axis direction and arranged at equal intervals in the X-axis direction. In other words, in this embodiment, the trenches 25 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. The trenches 25 are also formed so that they are sandwiched between the second deep layers 18 in the normal direction.

A gate insulating film 26 is formed on the inner wall surface of the trench 25, and a gate electrode 27 made of doped Poly-Si or the like is formed on the gate insulating film 26. This forms a trench gate structure. Although not particularly limited, the gate insulating film 26 is formed by thermally oxidizing the inner wall surface of the trench 25 or by carrying out a CVD (short for chemical vapor deposition) method. The gate insulating film 26 has a thickness of about 100 nm on both the side and bottom sides of the trench 25.

The gate insulating film 26 is also formed on surfaces other than the inner wall surface of the trench 25. Specifically, the gate insulating film 26 is formed in the element region 1 so as to cover a part of the surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed so as to cover a part of the surface of the source region 22. In other words, the gate insulating film 26 has a contact hole 26a that exposes the base layer 21 and the source region 22 in a part different from the part where the gate electrode 27 is arranged. In addition, the gate insulating film 26 has a contact hole 26b that exposes the entire surface 10a of the semiconductor substrate 10 in the diode region 2. In the guard region 3, the gate insulating film 26 is formed so as to cover the entire surface 10a of the semiconductor substrate 10.

An interlayer insulating film 28 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 27, the gate insulating film 26, etc. The interlayer insulating film 28 is made of BPSG (short for borophosphosilicate glass) or the like.

The interlayer insulating film 28 has a contact hole 28a formed therein, which communicates with the contact hole 26a and exposes the source region 22 and the contact region 23a in the element region 1. The interlayer insulating film 28 also has a contact hole 28b formed therein, which communicates with the contact hole 26b and exposes the contact region 23b in the diode region 2.

The contact hole 28a formed in the interlayer insulating film 28 is formed so as to communicate with the contact hole 26a formed in the gate insulating film 26, and functions together with the contact hole 26a as one contact hole. Similarly, the contact hole 28b formed in the interlayer insulating film 28 is formed so as to communicate with the contact hole 26b formed in the gate insulating film 26, and functions together with the contact hole 26b as one contact hole. For this reason, hereinafter, the contact holes 26a and 28a are collectively referred to as contact holes 29a, and the contact holes 26b and 28b are collectively referred to as contact holes 29b. The pattern of the contact holes 29a and 29b is arbitrary, and examples of the pattern include a pattern in which a plurality of squares are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are arranged. In this embodiment, the contact hole 29a formed in the element region 1 is a line along the longitudinal direction of the trench 25. In addition, the contact hole 29b formed in the diode region 2 is formed so as to expose the entire diode region 2.

An upper electrode 30 is formed on the interlayer insulating film 28. The upper electrode 30 is electrically connected to the source region 22 and the contact region 23a through the contact hole 29a, and is electrically connected to the contact region 23b through the contact hole 29b. That is, the contact region 23a in the element region 1 and the contact region 23b in the diode region 2 are electrically connected to the common upper electrode 30. In this embodiment, the upper electrode 30 corresponds to the first electrode. In addition, in the guard region 3, since the gate insulating film 26 and the interlayer insulating film 28 are arranged as described above, the guard region 3 is not electrically connected to the upper electrode 30 and is insulated.

The upper electrode 30 in this embodiment is composed of an Al-Si layer mainly composed of Al (aluminum) and is connected to the source region 22 and the contact regions 23a, 23b as follows. Specifically, a metal silicide layer 31a made of a metal such as Ni (nickel) is formed in the source region 22 and the contact regions 23a, 23b in the element region 1 in the portion exposed from the contact hole 29a. Similarly, a metal silicide layer 31b made of a metal such as Ni is formed in the contact region 23b in the diode region 2 in the portion exposed from the contact hole 29a. These metal silicide layers 31a, 31b are intended to reduce the contact resistance between the source region 22 and the contact regions 23a, 23b and the upper electrode 30.

A barrier metal film 32 made of Ti (titanium), TiN (titanium nitride), or the like is formed on the metal silicide layers 31a and 31b. The barrier metal film 32 is also formed on the wall surfaces of the contact holes 29a and 29b and on the surface of the interlayer insulating film 28. This barrier metal film 32 prevents Al constituting the upper electrode 30 from diffusing to the semiconductor substrate 10 side or the interlayer insulating film 28 side, and prevents Ni constituting the metal silicide layers 31a and 31b from diffusing to the upper electrode 30 side.

The upper electrode 30 is disposed on the barrier metal film 32, and is connected to the source region 22 and the contact regions 23a and 23b via the barrier metal film 32 and the metal silicide layers 31a and 31b.

A lower electrode 33 that is electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 33 corresponds to the second electrode.

Here, as described above, in the element region 1, the contact hole 29a is formed to expose a part of the source region 22 and the contact regions 23a and 23b. In the diode region 2, the contact hole 29b is formed to expose the entire region. Therefore, the connection area with the upper electrode 30 per unit area of the diode region 2 is larger than the connection area with the upper electrode 30 per unit area of the element region 1. Therefore, in the SiC semiconductor device of this embodiment, the contact resistance with the upper electrode 30 is smaller in the diode region 2 than in the element region 1. Also, in the element region 1, a parasitic diode including the drift layer 19 and the base layer 21 is formed. Therefore, as shown in FIG. 4, when comparing the parasitic diode formed in the element region 1 and the diode element formed in the diode region 2, the forward voltage Vf (hereinafter also simply referred to as the forward voltage Vf) at which the forward current If starts to flow is smaller in the diode region 2 than in the element region 1. In other words, in the SiC semiconductor device of this embodiment, when the diode operates as a diode, the diode region 2 is easier to operate than the parasitic diode formed in the element region 1.

In addition, as shown in FIG. 1, the guard region 3 in this embodiment is also disposed between the element region 1 and the diode region 2 by being disposed so as to surround the diode region 2. The width of the guard region 3 is set so that the interval between the portion disposed between the element region 1 and the diode region 2 is longer than the diffusion length of holes. In other words, the length of the portion of the guard region 3 disposed between the element region 1 and the diode region 2 is longer than the length along the arrangement direction between the element region 1 and the diode region 2. In other words, in this embodiment, the length along the X-axis direction of the portion of the guard region 3 disposed between the element region 1 and the diode region 2 is longer than the diffusion length of holes.

The above is the configuration of the SiC semiconductor device in this embodiment. Note that in this embodiment, n ^- type, n-type, and n ⁺ type correspond to the first conductivity type, and p-type and p ⁺ type correspond to the second conductivity type.

Next, the operation and effects of the SiC semiconductor device in this embodiment will be described.

First, in the SiC semiconductor device, in the off state before a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 27, no inversion layer is formed in the base layer 21. Therefore, even if a positive voltage, for example 1600 V, is applied to the lower electrode 33, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device is in an off state in which no current flows between the upper electrode 30 and the lower electrode 33.

Furthermore, when the SiC semiconductor device is in the off state, an electric field is applied between the drain and gate, and electric field concentration may occur at the bottom of the gate insulating film 26. However, in the above-mentioned SiC semiconductor device, the first deep layer 15 and the JFET section 14 are provided at a position deeper than the trench 25. Therefore, the depletion layer formed between the first deep layer 15 and the JFET section 14 suppresses the rise of the equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 26. Therefore, in this embodiment, it is possible to suppress the destruction of the gate insulating film 26.

Furthermore, in this embodiment, the first floating region 16 and the second floating region 24 are formed in the guard region 3. Therefore, the depletion layer formed between the first floating region 16 and the second floating region 24 and the drift layer 19 can suppress the concentration of equipotential lines due to the influence of the drain voltage. Therefore, the withstand voltage of the guard region 3 can also be improved.

When a voltage equal to or higher than the threshold voltage in the insulated gate structure, for example 20 V, is applied to the gate electrode 27, an inversion layer is formed on the surface of the base layer 21 that contacts the trench 25. This causes a current to flow between the upper electrode 30 and the lower electrode 33, and the SiC semiconductor device is turned on. In this embodiment, electrons that have passed through the inversion layer pass through the current spreading layer 17, the JFET portion 14, and the low concentration layer 13 and flow to the substrate 11, so that a drift layer 19 having the current spreading layer 17, the JFET portion 14, and the low concentration layer 13 is formed.

In addition, in such a SiC semiconductor device, a parasitic diode including the drift layer 19 and the base layer 21 is formed in the element region 1. Then, the SiC semiconductor device may operate as a diode, for example, when a voltage higher than that of the lower electrode 33 is applied to the upper electrode 30. In this case, in this embodiment, a diode region 2 having a lower forward voltage Vf than the parasitic diode is formed in the common semiconductor substrate 10. Therefore, in this embodiment, when the SiC semiconductor device operates as a diode, the diode region 2 is more likely to operate and the parasitic diode in the element region 1 is less likely to operate. Therefore, it is possible to suppress the formation of an SSF in the element region 1.

In addition, in this embodiment, a guard region 3 is disposed between the element region 1 and the diode region 2, and the portion of the guard region 3 located between the element region 1 and the diode region 2 has a width equal to or greater than the diffusion length of holes. This makes it possible to prevent holes injected into the diode region 2 from reaching the element region 1 when the diode region 2 operates as a diode. This also makes it possible to prevent holes from forming an SSF in the element region 1 when the diode region 2 operates as a diode.

According to the present embodiment described above, the forward voltage Vf of the diode region 2 is set lower than the forward voltage Vf of the parasitic diode formed in the element region 1. Therefore, when the SiC semiconductor device operates as a diode, the diode region 2 operates more easily and the parasitic diode in the element region 1 operates less easily. Therefore, it is possible to suppress the formation of an SSF in the element region 1.

In addition, in the SiC semiconductor device of this embodiment, the diode region 2 is disposed to prevent the formation of SSF in the element region 1. Therefore, compared to the case where a lifetime killer or the like is formed in the element region 1, an increase in the on-resistance of the element region 1 can be prevented. In other words, according to the SiC semiconductor device of this embodiment, it is possible to prevent the occurrence of SSF in the element region 1 while preventing an increase in the on-resistance.

(1) In this embodiment, the connection area with the upper electrode 30 per unit area of the diode region 2 is set to be larger than the connection area with the upper electrode 30 per unit area of the element region 1. This makes it easy to realize a configuration in which the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1.

(2) In this embodiment, the guard region 3 is disposed between the element region 1 and the diode region 2. The length of the portion of the guard region 3 located between the element region 1 and the diode region 2 is set to be equal to or greater than the diffusion length of holes. This makes it possible to prevent holes injected when the diode region 2 operates as a diode from reaching the element region 1. This makes it possible to prevent holes from forming an SSF in the element region 1 when the diode region 2 operates as a diode.

(3) In this embodiment, the guard region 3 is formed with a first floating region 16 and a second floating region 24 that form a depletion layer between the guard region 3 and the drift layer 19. This improves the breakdown voltage of the guard region 3.

Second Embodiment
A second embodiment will be described. In this embodiment, the configuration of the diode region 2 is changed from that of the first embodiment. As the rest is the same as the first embodiment, the description will be omitted here.

In the SiC semiconductor device of this embodiment, as shown in FIG. 5, the contact region 23b formed in the diode region 2 has a higher impurity concentration than the contact region 23a formed in the element region 1.

According to the present embodiment described above, the forward voltage Vf of the diode region 2 is set lower than the forward voltage Vf of the parasitic diode formed in the element region 1, so that the same effect as in the first embodiment can be obtained.

(1) In this embodiment, the contact region 23b formed in the diode region 2 has a higher impurity concentration than the contact region 23a formed in the element region 1. Therefore, as shown in FIG. 6, the forward voltage Vf of the diode region 2 can be further reduced.

Third Embodiment
A third embodiment will be described. In this embodiment, the configuration of the diode region 2 is changed from that of the first embodiment. As the rest is similar to the first embodiment, a description thereof will be omitted here.

In the SiC semiconductor device of this embodiment, as shown in FIG. 7, the metal silicide layer 31a formed in the element region 1 and the metal silicide layer 31b formed in the diode region 2 are different metal silicide layers. Specifically, the metal silicide layer 31b formed in the diode region 2 is made of a material that has a lower contact resistance with the upper electrode 30 than the metal silicide layer 31a formed in the element region 1. For example, the metal silicide layer 31a formed in the element region 1 is Ni silicide made of Ni, and the metal silicide layer 31b formed in the diode region 2 is Al silicide made of Al.

According to the present embodiment described above, the forward voltage Vf of the diode region 2 is set lower than the forward voltage Vf of the parasitic diode formed in the element region 1, so that the same effect as in the first embodiment can be obtained.

(1) In this embodiment, the metal silicide layer 31b formed in the diode region 2 is made of a material that has a lower contact resistance with the upper electrode 30 than the metal silicide layer 31a formed in the element region 1. This makes it possible to further reduce the forward voltage Vf of the diode region 2.

Fourth Embodiment
A fourth embodiment will be described. This embodiment is different from the first embodiment in that a diode region 2 is added. As the rest is similar to the first embodiment, a description thereof will be omitted here.

In the SiC semiconductor device of this embodiment, as shown in FIG. 8, two diode regions 2 are provided. A guard region 3 is provided to surround each diode region 2. Each diode region 2 and guard region 3 has the configuration shown in FIG. 2.

According to the present embodiment described above, the forward voltage Vf of the diode region 2 is set lower than the forward voltage Vf of the parasitic diode formed in the element region 1, so that the same effect as in the first embodiment can be obtained.

(1) In this embodiment, two diode regions 2 are provided. This further suppresses the element region 1 from operating as a diode. Although not shown, the number of diode regions 2 can be changed, and three or more diode regions 2 may be provided.

Fifth Embodiment
A fifth embodiment will be described. In this embodiment, the location of the diode region 2 is changed from that of the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

In the SiC semiconductor device of this embodiment, as shown in FIG. 9, the diode region 2 is arranged along the Y-axis direction relative to the element region 1. The guard region 3 is arranged to surround this diode region 2.

According to the present embodiment described above, the forward voltage Vf of the diode region 2 is set lower than the forward voltage Vf of the parasitic diode formed in the element region 1, so that the same effect as in the first embodiment can be obtained.

(1) In this embodiment, the diode region 2 is disposed along the Y-axis direction relative to the element region 1. Here, in the case of a SiC semiconductor device such as that of this embodiment, it has been reported that the SSF formed during diode operation tends to extend along the [1-100] direction. For this reason, the SSF that may be formed in the diode region 2 tends to extend along the X-axis direction. Therefore, it becomes difficult for the SSF that may be formed in the diode region 2 to reach the element region 1, which makes it easier to further suppress deterioration of the characteristics of the element region 1.

Other Embodiments
Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in the first embodiment, a SiC semiconductor device in which an n-channel type trench gate structure MOSFET with a first conductivity type being n-type and a second conductivity type being p-type is formed in the element region 1 has been described. However, this is merely an example, and for example, a SiC semiconductor device in which a p-channel type trench gate structure MOSFET with the conductivity type of each component reversed with respect to the n-channel type is formed in the element region 1 as a switching element may be used. Furthermore, the SiC semiconductor device may be configured such that an IGBT with a similar structure is formed in the element region 1 as a switching element in addition to the MOSFET. When an IGBT is formed in the element region 1, it is the same as the MOSFET described in each of the above embodiments, except that the n ⁺ type substrate 11 in each of the above embodiments is changed to a p ⁺ type substrate 11. Furthermore, the switching element may be configured to have a planar gate structure instead of a trench gate structure.

In addition, in each of the above embodiments, the SiC semiconductor device may have other elements formed therein, such as a current sense region for detecting current.

In each of the above embodiments, the first deep layer 15 and the second deep layer 18 may not be provided. Furthermore, the drift layer 19 may be composed of a single layer with a uniform impurity concentration.

Furthermore, in the second and third embodiments, if the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the relationship between the connection area with the upper electrode 30 per unit area in the diode region 2 and the guard region 3 can be changed as appropriate.

In each of the above embodiments, an example was described in which the semiconductor substrate 10 was made of 4H-SiC, but the semiconductor substrate 10 may also be made of 6H-SiC, etc.

In addition, in each of the above embodiments, only one of the first floating region 16 and the second floating region 24 may be formed in the guard region 3, or the first floating region 16 and the second floating region 24 may not be formed. Furthermore, in each of the above embodiments, the guard region 3 may not be formed. Even with such a SiC semiconductor device, the same effect as each of the above embodiments can be obtained as long as the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1.

The above embodiments may be combined to form a SiC semiconductor device. For example, the second embodiment may be combined with the third to fifth embodiments so that the contact region 23b of the diode region 2 has a higher impurity concentration than the contact region 23a of the element region 1. The third embodiment may be combined with the fourth and fifth embodiments so that the metal silicide layer 31b of the diode region 2 has a lower contact resistance with the upper electrode 30 than the metal silicide layer 31a of the element region 1. The fourth embodiment may be combined with the fifth embodiment so that a plurality of diode regions 2 are provided.

REFERENCE SIGNS LIST 1: element region 2: diode region 10: semiconductor substrate 10a: one surface 10b: other surface 30: first electrode 33: second electrode

Claims (7)

A silicon carbide semiconductor device made of silicon carbide,
A semiconductor substrate (10) made of silicon carbide and having one surface (10a) and another surface (10b) opposite to the one surface;
An element region (1) having a switching element formed on the semiconductor substrate and constituting a parasitic diode;
a diode region (2) formed on the semiconductor substrate and having a diode element;
a first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element;
a second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element;
The diode element formed in the diode region has a smaller forward voltage at which a forward current starts to flow than the parasitic diode,
In the element region and the diode region, contact regions (23a, 23b) are formed in portions connected to the first electrode,
The silicon carbide semiconductor device , wherein the contact region formed in the diode region has an impurity concentration higher than that of the contact region formed in the element region . A metal silicide layer (31 a, 31 b) is formed on the semiconductor substrate in a portion connected to the first electrode,
2. The silicon carbide semiconductor device according to claim 1, wherein the metal silicide layer formed in the diode region is made of a material having a lower contact resistance with the first electrode than the metal silicide layer formed in the element region. A silicon carbide semiconductor device made of silicon carbide,
A semiconductor substrate (10) made of silicon carbide and having one surface (10a) and another surface (10b) opposite to the one surface;
An element region (1) having a switching element formed on the semiconductor substrate and constituting a parasitic diode;
a diode region (2) formed on the semiconductor substrate and having a diode element;
a first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element;
a second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element;
The diode element formed in the diode region has a smaller forward voltage at which a forward current starts to flow than the parasitic diode,
A metal silicide layer (31a, 31b) is formed on the semiconductor substrate in a portion connected to the first electrode,
a metal silicide layer formed in the diode region using a material that has a lower contact resistance with the first electrode than a metal silicide layer formed in the element region; a guard region insulated from the first electrode is disposed between the element region and the diode region;
4. The silicon carbide semiconductor device according to claim 1, wherein the guard region disposed between the element region and the diode region has a length along an arrangement direction of the element region and the diode region that is equal to or greater than a diffusion length of holes . A silicon carbide semiconductor device made of silicon carbide,
A semiconductor substrate (10) made of silicon carbide and having one surface (10a) and another surface (10b) opposite to the one surface;
An element region (1) having a switching element formed on the semiconductor substrate and constituting a parasitic diode;
a diode region (2) formed on the semiconductor substrate and having a diode element;
a first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element;
a second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element;
The diode element formed in the diode region has a smaller forward voltage at which a forward current starts to flow than the parasitic diode,
a guard region insulated from the first electrode is disposed between the element region and the diode region;
a length of the guard region disposed between the element region and the diode region along an arrangement direction of the element region and the diode region that is equal to or greater than a diffusion length of holes . The guard area is
A drift layer (19) of a first conductivity type;
6. The silicon carbide semiconductor device according to claim 4, further comprising a floating region (16, 24) of a second conductivity type insulated from the first electrode, the floating region forming a depletion layer between the drift layer and the first electrode. 7. The silicon carbide semiconductor device according to claim 1, wherein a connection area per unit area of said diode region to said first electrode is larger than a connection area per unit area of said element region to said first electrode.