JP7714865B2 - Multilayer wiring board and method of manufacturing the same - Google Patents

Description

The present invention relates to a multilayer wiring board and a method for manufacturing a multilayer wiring board.

As semiconductor devices have become faster and more highly integrated in recent years, there is a demand for narrower pitches for the connecting terminals to the semiconductor elements and for finer wiring within the board, even for FC-BGA (Flip Chip-Ball Grid Array) boards on which semiconductor elements are mounted. On the other hand, there is a demand for connecting FC-BGA boards to motherboards with connecting terminals at roughly the same pitch as before.
In order to accommodate the narrower pitch of the bonding terminals with semiconductor elements and the accompanying finer wiring within the FC-BGA substrate, a technology has been adopted in which a multilayer wiring substrate containing fine wiring, also known as an interposer, is placed between the FC-BGA substrate and the semiconductor element.
One of them is silicon interposer technology, in which an interposer is formed on a silicon wafer using semiconductor circuit manufacturing technology.
Furthermore, a method has been developed in which the interposer is fabricated directly on an FC-BGA substrate, rather than being formed on a silicon wafer. This method involves planarizing the surface of the FC-BGA substrate using CMP (Chemical Mechanical Polishing) or the like, and then forming a multilayer wiring substrate that will serve as the interposer directly on the FC-BGA substrate. This method is disclosed in Patent Document 1.
Furthermore, there is also a method in which an interposer (multilayer wiring board) is formed on a support such as a glass substrate, and then this is mounted on an FC-BGA substrate, and the support substrate is then peeled off to form a narrow-pitch multilayer wiring board on an FC-BGA substrate, which is disclosed in Patent Document 2.

Japanese Patent Application Laid-Open No. 2014-225671 International Publication No. 2018/047861

Silicon interposers are made from silicon wafers using equipment used in front-end semiconductor manufacturing, making them suitable for forming fine wiring layers. However, silicon wafers are limited in shape and size, the number of interposers that can be made from a single wafer is limited, and manufacturing equipment is expensive, making interposers expensive. Furthermore, because silicon wafers are semiconductors, there is also the problem of degradation in transmission characteristics.

Furthermore, in a method in which the surface of an FC-BGA substrate is planarized and then multiple wiring layers that serve as an interposer are formed on top of it, the degradation in transmission characteristics seen with silicon interposers is minimal. However, there are issues with low overall manufacturing yields due to the manufacturing yield of the FC-BGA substrate itself and the high difficulty of forming the fine wiring on the FC-BGA substrate. Furthermore, there are also issues with mounting semiconductor elements due to warping and distortion of the FC-BGA substrate.

Furthermore, in a method in which a multilayer wiring board is formed on a support such as a glass substrate, and then the support is peeled off after being placed on an FC-BGA substrate, a semi-additive method is often used when forming a multilayer wiring layer on the support. However, the photosensitive resin layer used in the semi-additive method does not contain a filler, and tends to have a lower elastic modulus and a higher CTE than the underfill layer and solder resist layer used in subsequent processes, which contain a filler.
As a result, only the photosensitive resin layer deforms significantly when heated, making it easy for the substrate to warp. In particular, stress concentrates at the connection between the via and land sections, which serve as interlayer connections for the multilayer wiring on the side that connects to the FC-BGA substrate, causing cracks to form in the resin layer starting from the connection between the via and land sections, and these cracks then propagate, resulting in disconnections between the via and land sections.
Furthermore, warping due to heat can cause the photosensitive resin to peel off from the side or top surface of the land portion.

The present invention was developed in consideration of the above-mentioned problems, and aims to provide a multilayer wiring board formed on a support that can suppress cracks and breaks within the multilayer wiring board even after bonding to an FC-BGA substrate, as well as a method for manufacturing the multilayer wiring board.

To solve the above problems, one representative multilayer wiring board of the present invention has a first layer having a first interlayer connection conductor and a second layer having a second interlayer connection conductor, the first interlayer connection conductor and the second interlayer connection conductor being embedded in insulating resin forming the first layer and the second layer, respectively, via a seed adhesion layer, the first interlayer connection conductor and the second interlayer connection conductor being bonded to each other via the seed adhesion layer, and the top and bottom surfaces of the first layer and the second layer being covered with an inorganic insulating film, except for the portions where the first interlayer connection conductor and the second interlayer connection conductor are connected to each other or to other connection conductors.

Also, one of the representative methods for manufacturing a multilayer wiring board of the present invention includes a step of forming an inorganic insulating film layer, a step of forming a pattern of a first photosensitive resin having a first opening on the inorganic insulating film layer,
The method includes the steps of forming a pattern of a second photosensitive resin above the first photosensitive resin, the pattern having second openings with a diameter larger than that of the first openings; removing the inorganic insulating film layer within the first openings; forming a seed adhesion layer and a seed layer at the first openings and at ends of the patterns of the first photosensitive resin and the second photosensitive resin; forming an electrolytic copper plating layer on the seed layer; and polishing the electrolytic copper plating layer, the seed layer, and the seed adhesion layer until the second photosensitive resin pattern is exposed.

According to the present invention, it is possible to provide a multilayer wiring board capable of suppressing cracks and breaks in the multilayer wiring board and a method for manufacturing the multilayer wiring board.
Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

10 is a cross-sectional view showing a state in which a multilayer wiring board and an FC-BGA board are joined and a semiconductor element is mounted. FIG. 2 is a cross-sectional view showing a state in which a photosensitive resin, a seed adhesion layer, a seed layer, and a conductor layer are formed above a support. FIG. 10 is a cross-sectional view showing a state in which an inorganic insulating film is formed after surface polishing. FIG. 10 is a cross-sectional view showing a state in which a first opening portion has been formed. FIG. 10 is a cross-sectional view showing a state in which a second opening portion has been formed. FIG. 10 is a cross-sectional view showing a state in which the inorganic insulating film has been removed. FIG. 2 is a cross-sectional view showing a state in which a seed adhesion layer and a seed layer have been formed. FIG. 10 is a cross-sectional view showing a state in which a conductor layer has been formed. FIG. 10 is a cross-sectional view showing a state in which a via portion and a wiring portion are formed by surface polishing. 10 is a cross-sectional view showing a state in which the seed adhesion layer and the photosensitive resin layer are polished by surface polishing, and an interlayer connection conductor is formed. FIG. FIG. 12 is a cross-sectional view showing a state in which multilayer wiring is formed by repeating the steps shown in FIGS. FIG. 2 is a cross-sectional view showing a state in which an inorganic insulating film has been formed. 10 is a cross-sectional view showing a state in which a surface treatment layer and a solder joint are formed and a wiring board on a support is completed. FIG. FIG. 2 is an enlarged detailed cross-sectional view of the AA' surrounding portion in this embodiment. FIG. 10 is an enlarged detailed cross-sectional view of the AA' surrounding portion in the comparative example.

An example of a multilayer wiring board according to one embodiment of the present invention and a manufacturing process thereof will be described below with reference to FIGS.
In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

Furthermore, the embodiments shown below are examples of devices and methods that embody the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical concept of the present invention can be modified in various ways within the technical scope defined by the claims.

In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, the terms "upper surface" and "lower surface" refer to the surfaces shown at the top and bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member.
Furthermore, the term "side surface" refers to a surface or thickness portion of a layer included in a plate-like member or a layer included in a plate-like member. Furthermore, a portion of a surface and a side surface may be collectively referred to as an "edge portion."
Furthermore, "upper" refers to the direction vertically upward when the plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower," are sometimes referred to as the "Z-axis direction," and the horizontal direction is sometimes referred to as the "X-axis direction" or the "Y-axis direction."
Furthermore, "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction.
Furthermore, "center" means the center of a surface or layer, not the periphery, and "toward the center" means the direction from the periphery of the surface or layer toward the center of the planar shape of the surface or layer.

The multilayer wiring board 30 of this embodiment can be connected to a semiconductor element on its first surface, and can be connected to another wiring board on its second surface. First, as shown in Figure 1, we will explain the entire semiconductor device 18 manufactured using the multilayer wiring board 30 of this embodiment. In Figure 1, a semiconductor element 17 is bonded to the top surface of the multilayer wiring board 30, and an FC-BGA substrate 14 is bonded to the bottom surface of the multilayer wiring board 30, which together form the semiconductor device 18.

The semiconductor element 17 is joined to the multilayer wiring substrate 30 at solder joints 25, and then sealed and fixed with sealing resin 26. The semiconductor element 17 is joined to the FC-BGA substrate 14 at solder joints 27, and then sealed and fixed with sealing resin 28.
As will be described later, the multilayer wiring board 30 is formed above the support 1 via a release layer 2, and after being bonded to the FC-BGA substrate 14, the support 1 is peeled off and removed by the release layer.

The semiconductor element 17 may be bonded to the multilayer wiring substrate 30 after the multilayer wiring substrate 30 has been bonded to the FC-BGA substrate 14, or may be bonded to the multilayer wiring substrate 30 before the multilayer wiring substrate 30 is bonded to the FC-BGA substrate 14. In the following description of the embodiment, we will explain an aspect in which the semiconductor element 17 is bonded to the multilayer wiring substrate 30 after the multilayer wiring substrate 30 has been bonded to the FC-BGA substrate 14.

Next, the configuration of the multilayer wiring board 30 and a method for manufacturing the same will be described with reference to FIGS.
FIG. 2 is a cross-sectional view showing a state in which a release layer 2, a photosensitive resin 3, a seed adhesion layer 4, a seed layer 5, and a conductor layer 6 are formed above a support.
The steps for obtaining the configuration shown in FIG. 2 will be described below in order.

(1) Formation of release layer 2 on the upper surface of support 1 Since light may be irradiated onto release layer 2 through support 1, it is advantageous for support 1 to be light-transmitting, and rectangular glass, for example, can be used. Rectangular glass is suitable for large sizes, and glass has excellent flatness and high rigidity, making it suitable for forming a fine pattern on a support.
Furthermore, glass has a small coefficient of thermal expansion (CTE) and is less susceptible to distortion, making it excellent for ensuring pattern placement accuracy and flatness. When glass is used as the support 1, the thickness of the glass is preferably large in order to suppress the occurrence of warping during the manufacturing process, and is, for example, 0.5 mm or more, preferably 1.2 mm or more.

Furthermore, the CTE of the glass is preferably 3 ppm or more and 16 ppm or less, and from the viewpoint of matching with the CTE of the FC-BGA substrate 14 and the semiconductor element 17, it is more preferably about 10 ppm.
On the other hand, if the support 1 does not need to be light-transmitting when peeling it off, such as when the peel-off layer 2 is made of a resin that foams when heated, the support 1 can be made of a material with little distortion, such as metal or ceramics.
In the following, an embodiment of the present invention will be described by taking an example in which a resin that absorbs UV light and becomes peelable is used as the peel layer 2 and glass is used as the support 1 .

The release layer 2 may be made of a resin that absorbs light such as UV light, generates heat, or changes properties to become peelable, or it may be made of a resin that foams when heated and becomes peelable. Furthermore, the release layer 2 may contain additives such as photodecomposition accelerators, light absorbers, sensitizers, and fillers.

Furthermore, the release layer 2 may be composed of multiple layers, and for example, for the purpose of protecting the multilayer wiring layer formed on the support 1 in a later step, a protective layer may be further provided on the release layer 2, or a layer that improves adhesion to the support 1 may be provided below the release layer 2. Furthermore, a laser light reflective layer or a metal layer may be provided between the release layer 2 and the multilayer wiring layer, and the configuration thereof is not limited by this embodiment.
In addition, when a resin that can be peeled off by light such as UV light, for example laser light, is used as the peeling layer 2, if the support 1 is translucent, the direction in which light is irradiated onto the peeling layer 2 may be such that light is irradiated onto the support 1 from the side opposite to the side on which the peeling layer 2 is provided.

(2) Formation of Photosensitive Resin Layer 3 on the Upper Surface of Release Layer 2 After forming the release layer 2 on the upper surface of the support 1, the photosensitive resin layer 3 is formed on the upper surface of the release layer 2. In this embodiment, the photosensitive resin layer 3 is formed by spin coating, for example, using a photosensitive epoxy resin.

(3) Patterning of Photosensitive Resin 3 Next, openings are formed in the photosensitive resin layer 3 by photolithography. The openings may be subjected to plasma treatment to remove residues left behind during development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the openings, and is set to, for example, 8 μm in one embodiment of the present invention.
The shape of the openings in plan view is set according to the pitch and shape of the bonding electrodes of the semiconductor element, and in one embodiment of the present invention, the openings have a diameter of 25 μm, for example, and the pitch is 55 μm.

(4) Formation of Seed Adhesion Layer 4 and Seed Layer 5 Next, the seed adhesion layer 4 and the seed layer 5 are formed in a vacuum. The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and prevents peeling of the seed layer 5. The seed layer 5 acts as a power supply layer for electrolytic plating in forming the wiring. The seed adhesion layer 4 and the seed layer 5 are formed by, for example, a sputtering method or a vapor deposition method, and may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, _Cu3N4 , a Cu alloy, or a combination of _two or more of these.
In the present invention, taking into consideration electrical properties, ease of manufacturing, and cost, a titanium layer is formed on the seed adhesion layer 4, followed by a copper layer as the seed layer 5, in that order by sputtering. The total thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are used.

(5) Formation of Conductive Layer 6 Next, the conductor layer 6 is formed on the seed layer 5 by electrolytic plating. The conductor layer 6 serves as an electrode for bonding to the semiconductor element 17. Options for electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, but electrolytic copper plating is preferred because it is simple, inexpensive, and has good electrical conductivity.
The thickness of the electrolytic copper plating is preferably 1 μm or more and 30 μm or less from the viewpoint of productivity, considering that the conductor layer 6 serves as an electrode for bonding to the semiconductor element 17 and is soldered. In one embodiment of the present invention, Cu: 10 μm is formed in the openings of the photosensitive resin layer 3, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

By these steps, the structure shown in Fig. 2 can be obtained. Next, the following steps are carried out to obtain the structure shown in Fig. 3.
(6) Polishing of Conductive Layer 6 For the structure obtained in Fig. 2, the copper layer is polished by CMP (chemical mechanical polishing) or the like to remove the conductive layer 6 and the seed layer 5. Then, polishing is performed so that the seed adhesion layer 4 and the conductive layer 6 become the surface. In one embodiment of the present invention, 2 µm of Cu in the upper conductive layer 6 of the photosensitive resin 3 and 300 nm of Cu in the seed layer 5 are removed by polishing.

(7) Polishing of the seed adhesion layer 4 and the photosensitive resin 3 Next, polishing such as CMP is performed again to remove the seed adhesion layer 4 and the photosensitive resin 3. Because the seed adhesion layer 4 and the photosensitive resin 3 are polished from different materials, chemical polishing is less effective, and physical polishing using an abrasive is dominant. For the purpose of simplifying the process, the same technique as used for polishing the conductor layer 6 and the seed layer 5 described above may be used, or the polishing technique may be changed depending on the material type of the seed adhesion layer 4 and the photosensitive resin 3 for the purpose of improving polishing efficiency.
The conductor layer 6 remaining after polishing serves as an electrode for bonding to the semiconductor element 17. Furthermore, by making the conductor contact the photosensitive resin via the seed adhesion layer 4, it is possible to prevent the conductor from peeling off from the photosensitive resin due to warping during heating or the like.

(8) Formation of Inorganic Insulating Film 7 Next, an inorganic insulating film 7 is formed on the upper surface of the conductor layer 6, which serves as an electrode for bonding to the polished semiconductor element, to obtain the structure with the insulating film formed as shown in FIG. 3. The inorganic insulating film 7 may be made of silicon oxide (SiOx), silicon nitride (SiNx), SiC, SiOF, SiOC, or the like. In one embodiment of the present invention, the inorganic insulating film 7 is SiNx: 50 nm, and is formed by plasma CVD.

The inorganic insulating film 7 does not have to be an insulating film formed by plasma CVD, such as the silicon oxide film (SiOx) or silicon nitride film (SiNx), and there are no restrictions on the type or manufacturing method as long as it is an inorganic insulating film.

(9) Formation of First Openings Next, as shown in Figure 4, a pattern of first photosensitive resin 31, which will serve as an interlayer insulating resin, is formed on the upper surface of the inorganic insulating film 7. The thickness of the first photosensitive resin layer 31, which serves as insulating resin, is set according to the thickness of the conductor layer to be formed in the openings, and in one embodiment of the present invention, the thickness is set to, for example, 2 µm. The diameter of the first openings provided in the first photosensitive resin is set from the perspective of connection with the conductor layer 6.
In one embodiment of the present invention, an opening having a diameter of, for example, 11 μm is formed, which will be the diameter of a via portion connecting upper and lower layers of a multilayer wiring.

Also, as shown in Figure 4, by interposing an inorganic insulating film 7 at the interface between photosensitive resin layers, adhesion is improved compared to when photosensitive resin is formed directly on photosensitive resin. Furthermore, by interposing an inorganic insulating film 7 between the photosensitive resin layer 3 and the conductor layer 6, adhesion is improved compared to when the conductor layer 6 is in direct contact with the photosensitive resin layer 3. These effects make it possible to suppress cracks in the resin layer originating from the connection between the via portion and the land portion during multi-layering, and the resulting disconnection between the via portion and the land portion.

(10) Formation of Second Openings Furthermore, as shown in Figure 5, a pattern of second photosensitive resin 32, which serves as an interlayer insulating resin, is formed on the upper surface of the pattern of first photosensitive resin 31. The thickness of second photosensitive resin 32, which serves as an insulating resin, is set according to the thickness of the conductor layer to be formed in the opening, and in one embodiment of the present invention, it is formed to be, for example, 2 µm. Furthermore, the opening diameter of the second opening provided in the second photosensitive resin is set from the viewpoint of the connectivity of the laminate, and is an opening shape with an opening diameter larger than the first opening below, and is formed in a shape that surrounds the outside of the first opening.
In one embodiment of the present invention, an opening having a diameter of, for example, 25 μm is formed. This second opening is the wiring portion of the multilayer wiring board. When the wiring board is multilayered, it also becomes a receiving pad for the via portion, or a so-called land portion. In the present invention, the via portion for connecting the layers is formed integrally with the land portion.

(11) Removal of Inorganic Insulating Film 7 Next, as shown in FIG. 6, the inorganic insulating film 7 in the openings of the first photosensitive resin layer 31 is removed by, for example, dry etching in a vacuum.

(12) Formation of Seed Adhesion Layer 4 and Seed Layer 5 Next, as shown in Fig. 7, the seed adhesion layer 4 and the seed layer 5 are formed in a vacuum. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm are formed.

At this time, a seed adhesion layer 4 is formed on the side surface of the inorganic insulating film 7. By forming the seed adhesion layer 4 as a continuous film on both the side surface of the resin and the side surface of the inorganic insulating film 7, the risk of disconnection between the via portion and the land portion due to thermal warping can be reduced.

(13) Formation of Conductive Layer 6 Next, the conductor layer 6 is formed by electrolytic plating as shown in Fig. 8. The conductor layer 6 formed at this stage will become the via portion and the wiring portion. Options for electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating, but electrolytic copper plating is preferred because it is simple, inexpensive, and has good electrical conductivity.
The thickness of the electrolytic copper plating is preferably 0.5 μm or more from the viewpoint of electrical resistance of the wiring portion, and 30 μm or less from the viewpoint of productivity.
In one embodiment of the present invention, Cu: 6 μm is formed in the double opening of the photosensitive resin layer 3, Cu: 4 μm is formed in the single opening of the photosensitive resin layer 3, and Cu: 2 μm is formed on the top of the photosensitive resin layer 3.

(14) Surface Polishing Next, as shown in FIG. 9, the surface is polished by CMP (chemical mechanical polishing) or the like to remove the conductor layer 6 and the seed layer 5.

(15) Removal of the Seed Adhesion Layer 4 and the Photosensitive Resin Layer 3 Next, as shown in FIG. 10 , polishing is again performed using a process such as CMP (chemical mechanical polishing) to remove the seed adhesion layer 4 and a portion of the surface layer of the second photosensitive resin 32. The conductor layer 6 remaining after the CMP process becomes the conductor portion of the via portion and the wiring portion. In one embodiment of the present invention, 2 μm of Cu from the upper conductor layer 6 of the photosensitive resin layer 3 and 300 nm of Cu from the seed layer 5 are removed by polishing. In this manner, an interlayer connection conductor in which the via portion and the land portion are integrated can be formed. Here, as shown in FIG. 10 , by contacting the conductor with the photosensitive resin via the seed adhesion layer 4, peeling of the conductor from the photosensitive resin due to warping during heating can be suppressed.

(16) Formation of Multilayer Wiring by Repeating Steps As shown in Fig. 11, multilayer wiring is formed by repeating the steps shown in Fig. 4 to Fig. 10. In one embodiment of the present invention, two wiring layers are formed. Also, as shown in Fig. 11, the interlayer connection conductors are formed so that the land portion of the interlayer connection conductor formed first and the via portion of the interlayer connection conductor formed next are electrically connected.

The steps for forming electrodes for bonding to the FC-BGA substrate 14, up to obtaining the configuration shown in FIG. 12, will be described below in order.
(17) Formation of Inorganic Insulating Film 7 An inorganic insulating film 7 is formed on the upper surface of the polished surface formed in Fig. 11. The inorganic insulating film 7 is formed by forming SiNx: 50 nm by plasma CVD, for example.
Next, the photosensitive resin layer 3 is formed on the inorganic insulating film 7. Next, similarly to FIG. 6, the inorganic insulating film 7 in the openings of the photosensitive resin layer 3 is removed by dry etching.

(18) Formation of Seed Adhesion Layer 4 and Seed Layer 5 Next, the seed adhesion layer 4 and the seed layer 5 are formed in a vacuum. Next, a resist pattern 8 is formed.

(19) Formation of Conductive Layer (for Solder Connection) 9 Then, the conductive layer (for solder connection) 9 is formed by electrolytic plating.
This conductor layer (for solder connection) 9 will later become an electrode for joining to the FC-BGA substrate 14 .
The thickness of the electrolytic copper plating is preferably 1 μm or more from the viewpoint of solder bonding and 30 μm or less from the viewpoint of productivity. In one embodiment of the present invention, Cu: 10 μm is formed in the opening of the photosensitive resin layer 3, and Cu: 8 μm is formed on the upper part of the photosensitive resin layer 3.
In this way, the configuration shown in FIG. 12 can be obtained.

Next, the steps up to the completion of the wiring board on the support body shown in FIG. 13 will be described in order.
(20) Removal of Resist Pattern and Formation of Solder Resist 10 First, the resist pattern 8 shown in Fig. 12 is removed, and then unnecessary parts of the seed adhesion layer 4 and seed layer 5 are removed by etching. Then, the solder resist 10 is formed.
The solder resist 10 is exposed to light and developed so as to cover the photosensitive resin layer 3, and is formed to have openings through which the conductor layer (for solder connection) 9 is exposed.
Note that an insulating resin such as an epoxy resin or an acrylic resin can be used as the material of the solder resist 10. In the embodiment of the present invention, the solder resist 10 is formed using a photosensitive epoxy resin containing a filler.

(21) Formation of Surface Treatment Layer 11 Next, a surface treatment layer 11 is provided to prevent oxidation of the surface of the conductor layer (for solder connection) 9 and to improve the wettability of the solder bumps.
In an embodiment of the present invention, electroless Ni/Pd/Au plating is formed as the surface treatment layer 11. Note that an OSP (organic solderability preservative, a surface treatment using a water-soluble preflux) film may be formed on the surface treatment layer 11. Alternatively, electroless tin plating, electroless Ni/Au plating, or the like may be selected as appropriate depending on the application.

(22) Formation of Solder Joints Next, a solder material is placed on the surface treatment layer 11, and then melted, cooled, and solidified to form solder joints 12. This completes the formation of a multilayer wiring substrate 13 on the support 1, as shown in FIG.

The multilayer wiring board 13 thus completed on the support body is joined to the FC-BGA substrate 14, and then the joint is sealed with an underfill layer.
The underfill layer is made of a material obtained by adding a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide to one or more of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins. The underfill layer is formed by filling with a liquid resin.

Next, the release layer 2 is irradiated with laser light, making it possible to remove the support 1. Next, the release layer 2, seed adhesion layer 4, and seed layer 5 are removed.

Then, a semiconductor element 17 is mounted to complete the semiconductor device 18 shown in Figure 1. At this time, prior to mounting the semiconductor element 17, the exposed conductor layer 6 may be subjected to a surface treatment such as electroless Ni/Pd/Au plating, OSP, electroless tin plating, or electroless Ni/Au plating to prevent oxidation and improve the wettability of the solder bumps.

<Verification of effectiveness>
Next, the effects of using the configuration of the multilayer wiring board and the manufacturing method thereof as described above will be described with reference to FIG. 14 showing an example of an embodiment of the present invention and FIG. 15 showing a comparative example.

This embodiment will be described using Figure 14. Figure 14 is an enlarged view of the connection between interlayer connection conductors in a multilayer wiring substrate 13. As shown in Figure 14, the outer periphery of the interlayer connection conductor is covered with a seed adhesion layer 4 or an inorganic insulating film 7. This improves adhesion between the photosensitive resin by forming the inorganic insulating film 7 on the land portion excluding the surface where the via portion and land portion contact each other due to warping of the substrate when heated, and suppresses cracks in the photosensitive resin layer originating from portion A', which is subjected to the most stress due to the warping. This also reduces the likelihood of disconnection between the via portion and the land portion. It also reduces the likelihood of the via portion and the land portion peeling from the photosensitive resin due to warping of the substrate when heated.

A comparative example will be described using Figure 15. Figure 15 shows a multilayer wiring board 19 in which inner conductor layers and interlayer connection conductors are fabricated using the well-known semi-additive method (SAP method). In the configuration shown in Figure 15, the conductors on the side and upper ends of the land portions are partially exposed. In this case, compared to the case in which the entire periphery of the via portion and land portion of the interlayer connection conductor is covered with a seed adhesion layer 4 or inorganic insulating film 7 as shown in Figure 14, cracks occur in the resin in the X direction starting from point B' where the via portion 20 and land portion 21 meet, i.e., in the area on the land portion 21 where no adhesion layer is formed. As these cracks propagate, stress is further concentrated at the connection interface between the via portion and the land portion, making the wiring more susceptible to breakage. Furthermore, warping during heating can easily cause the wiring to peel off from the resin in the wiring portion.

To confirm the effects of this embodiment, a multilayer wiring board 13 produced in accordance with the embodiment of the present invention and a multilayer wiring board 19 produced in accordance with the comparative example were mounted on an FC-BGA substrate 14, and subjected to 500 cycles of temperature changes from -55°C to 125°C. As a result, resin cracks and disconnections were observed at the via connection portions in the wiring board 19 produced in the comparative example. On the other hand, neither resin cracks nor disconnections were observed in the multilayer wiring board 13 produced in accordance with the embodiment of the present invention.

The above-described embodiment is merely an example, and it goes without saying that other specific details, such as the structure, can be modified as appropriate.

1 Support 2 Release layer 3 Photosensitive resin 4 Seed adhesion layer 5 Seed layer 6 Conductor layer 7 Inorganic insulating film 8 Resist pattern 9 Conductor layer (for solder connection)
10 solder resist 11 surface treatment layer 12 solder 13 multilayer wiring board on support 14 FC-BGA board 15 laser light 17 semiconductor element 18 semiconductor device 19 multilayer wiring board (SAP)
20 via portion 21 land portion 30 multilayer wiring substrate 31 first photosensitive resin 32 second photosensitive resin 36 interlayer connection conductor

Claims (6)

A multilayer wiring board having a first layer having a first interlayer connection conductor and a second layer having a second interlayer connection conductor,
the first interlayer connection conductor and the second interlayer connection conductor are embedded in insulating resin forming the first layer and the second layer via a seed adhesion layer, respectively;
the first interlayer connection conductor and the second interlayer connection conductor are formed by integrating a via portion and a land portion having a diameter larger than that of the via portion,
a side surface of the via portion of the first interlayer connection conductor , a surface of the land portion surrounding the outside of the via portion, and a side surface of the land portion are in contact with the insulating resin forming the first layer via the seed adhesion layer,
a side surface of the via portion of the second interlayer connection conductor, a surface of the land portion surrounding the outside of the via portion, and a side surface of the land portion are in contact with the insulating resin forming the second layer via the seed adhesion layer,
the first interlayer connection conductor and the second interlayer connection conductor are bonded to each other via the seed adhesion layer;
a multilayer wiring board characterized in that the upper and lower surfaces of the first layer and the second layer are covered with an inorganic insulating film except for the portions where the first interlayer connection conductor and the second interlayer connection conductor are connected to each other or to other connection conductors. 2. The multilayer wiring board according to claim 1,
The multilayer wiring substrate is characterized in that the seed adhesion layer covers the side surface of the inorganic insulating film. 3. The multilayer wiring board according to claim 1,
10. The multilayer wiring substrate according to claim 9, wherein the seed adhesion layer is a layer containing titanium. 4. The multilayer wiring board according to claim 1,
The multilayer wiring board is characterized in that the insulating resin is a photosensitive insulating resin. A method for manufacturing a multilayer wiring board, comprising forming the multilayer wiring layer according to any one of claims 1 to 4, which comprises an insulating resin layer and a wiring layer above a support, the method comprising:
forming an inorganic insulating film layer;
forming a pattern of a first photosensitive resin having a first opening on the inorganic insulating film layer;
forming a pattern of a second photosensitive resin above the first photosensitive resin, the second photosensitive resin having second openings with a diameter larger than that of the first openings;
removing the inorganic insulating film layer in the first opening;
forming the seed adhesion layer and the seed layer at the first opening and at the end of the patterns of the first photosensitive resin and the second photosensitive resin;
forming an electrolytic copper plating layer on the seed layer;
polishing the electrolytic copper plating layer, the seed layer, and the seed adhesion layer until the pattern of the second photosensitive resin is exposed. 6. The method for manufacturing a multilayer wiring board according to claim 5,
2. A method for manufacturing a multilayer wiring board, wherein the seed adhesion layer and the seed layer are formed by a sputtering method.