JP7716360B2 - Switching Circuit - Google Patents

Description

The technology disclosed in this specification relates to switching circuits.

The inverter circuit disclosed in Patent Document 1 has two switching elements connected in series between a high-potential wiring and a low-potential wiring. An output wiring is connected to the junction of the two switching elements. The inverter circuit also has a gate control circuit for each switching element. Each gate control circuit controls the gate potential of the corresponding switching element. The gate control circuit switches the switching element by switching the gate potential between a gate-on potential and a gate-off potential. The gate control circuit can apply a first gate-off potential equal to or greater than 0 V and a second gate-off potential less than 0 V as the gate-off potential. When one of the series-connected switching elements turns on, the gate potential of the other switching element may momentarily rise due to capacitive coupling. In response to this, each gate control circuit applies a second gate-off potential (i.e., a negative potential) to the gate of the target switching element when the switching element connected to it (hereinafter referred to as the target switching element) is in the off state and the switching element connected in series to the target switching element (hereinafter referred to as the opposing switching element) turns on. This prevents the target switching element from being accidentally turned on (hereinafter referred to as "false ignition") even if the gate potential of the target switching element rises due to capacitive coupling. Furthermore, applying a negative potential to the gate of a switching element can easily cause the switching element to deteriorate. In response, each gate control circuit applies a first gate-off potential to the gate of the target switching element during off periods other than when the opposing switching element turns on. This prevents deterioration of the target switching element.

JP 2019-068691 A

This specification proposes technology that can suppress erroneous firing of the target switching element and shorten the period during which a negative potential is applied to the gate of the target switching element.

In the technology of Patent Document 1, a negative potential is always applied to the gate of the target switching element when the opposing switching element is turned on. However, even if the opposing switching element is turned on while a forward current is flowing through the diode connected in parallel to the opposing switching element, the gate potential of the target switching element does not rise due to capacitive coupling, and false firing of the target switching element does not occur. Therefore, the switching circuit disclosed in this specification has the following configuration.

The switching circuit disclosed in this specification comprises a high-potential wiring, an output wiring, a low-potential wiring, a first switching element having a gate and a high-potential main terminal connected to the high-potential wiring and a low-potential main terminal connected to the output wiring, a second switching element having a gate and a high-potential main terminal connected to the output wiring and a low-potential main terminal connected to the low-potential wiring, a first diode having a cathode connected to the high-potential main terminal of the first switching element and an anode connected to the low-potential main terminal of the first switching element, a second diode having a cathode connected to the high-potential main terminal of the second switching element and an anode connected to the high-potential main terminal of the second switching element and the low-potential main terminal of the second switching element, a target gate control circuit that changes the potential of the gate of the target switching element between a gate-on potential and a gate-off potential when one of the first switching element and the second switching element is a target switching element and the other is an opposing switching element, and an opposing gate control circuit that changes the potential of the gate of the opposing switching element between a gate-on potential and a gate-off potential. The target gate control circuit and the opposing gate control circuit control the gate potential of the target switching element and the gate potential of the opposing switching element so that the target switching element and the opposing switching element are alternately turned on. The target gate control circuit is capable of applying, as the gate-off potential, a first gate-off potential that is equal to or greater than the potential of the low-potential main terminal of the target switching element and a second gate-off potential that is lower than the potential of the low-potential main terminal of the target switching element to the gate of the target switching element. The first diode and the second diode, which are connected in parallel to the target switching element, are the target diode. The first diode and the second diode, which are connected in parallel to the opposing switching element are the opposing diode. The target gate control circuit applies the first gate-off potential to the gate of the target switching element at a first timing when the opposing switching element turns on while a forward current is flowing through the opposing diode, and applies the second gate-off potential to the gate of the target switching element at a second timing when the opposing switching element turns on while no forward current is flowing through the opposing diode.

The first switching element and the second switching element may be field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs). The first diode may be a diode provided separately from the first switching element. If the first switching element is a FET, the first diode may be the body diode of the first switching element. The second diode may be a diode provided separately from the second switching element. If the second switching element is a FET, the second diode may be the body diode of the second switching element. In this specification, the term "gate-on potential" refers to the gate potential required to turn on a switching element. In other words, the gate-on potential refers to a potential equal to or greater than the gate threshold of the switching element. In this specification, the term "gate-off potential" refers to the gate potential required to turn off a switching element. In other words, the gate-off potential refers to a potential less than the gate threshold of the switching element. In this specification, the term "forward current" refers to a current flowing through a diode from the anode to the cathode.

In this switching circuit, the target gate control circuit applies a first gate-off potential (i.e., a potential of 0 V or higher) to the gate of the target switching element at a first timing when the opposing switching element turns on while a forward current is flowing through the opposing diode. Even if the opposing switching element turns on at the first timing, the gate potential of the target switching element does not rise due to capacitive coupling. Therefore, even if a negative potential is not applied to the gate of the target switching element at the first timing, false firing does not occur. Furthermore, by applying a first gate-off potential of 0 V or higher to the gate of the target switching element at the first timing, the period during which a negative potential is applied to the gate of the target switching element can be shortened, thereby suppressing deterioration of the target switching element. Furthermore, in this switching circuit, the target gate control circuit applies a second gate-off potential (i.e., a negative potential) to the gate of the target switching element at a second timing when the opposing switching element turns on while a forward current is not flowing through the opposing diode. At the second timing, the gate potential of the target switching element may rise due to capacitive coupling when the opposing switching element turns on. Therefore, applying a negative potential to the gate of the target switching element at the second timing can suppress erroneous firing. As described above, this switching circuit can suppress erroneous firing of the target switching element and shorten the period during which a negative potential is applied to the gate of the target switching element compared to conventional techniques.

Inverter circuit diagram. FIG. 2 is a circuit diagram of a switching circuit 20a. FIG. 10 is an explanatory diagram of a current path in the outflow direction. FIG. 10 is an explanatory diagram of a current path in the inflow direction. 10 is a flowchart showing a process executed by a control IC 47. 10 is a flowchart showing a process executed by a control IC 57. Graph showing the change in each value during operation in the inflow direction. Graph showing the change in each value in the outflow direction behavior. Graph showing the changes in each value during startup operation. FIG. 10 is a circuit diagram of a modified example of the switching circuit 20a. FIG. 2 is a circuit diagram of a switching circuit 20a2. FIG. 2 is a circuit diagram showing an example of a drain potential detection circuit. FIG. 2 is a circuit diagram showing an example of a drain potential detection circuit. FIG. 2 is a circuit diagram of a switching circuit 20a3. FIG. 2 is a circuit diagram of a switching circuit 20a4. 10 is a graph showing an increase amount ΔV. Circuit diagram of a peak hold circuit. 10 is a graph showing a method for calculating a gate-off potential Voff. FIG. 2 is a circuit diagram of a switching circuit 20a5. FIG. 10 is a circuit diagram of a modified example of the switching circuit 20a5.

In one example switching circuit disclosed herein, the target gate control circuit may determine whether a forward current is flowing through the opposing diode based on the direction of the current flowing through the output wiring.

When current flows in the output wiring in the direction outgoing from the series circuit (i.e., the series circuit of the first switching element and the second switching element), a forward current flows through the second diode when the first switching element is off. Also, when current flows in the output wiring in the direction into the series circuit, a forward current flows through the first diode when the second switching element is off. Therefore, it is possible to appropriately determine whether a forward current is flowing through the opposing diode based on the direction of the current flowing in the output wiring.

In one example switching circuit disclosed herein, the target gate control circuit may determine whether a forward current is flowing through the opposing diode based on the direction of current flowing through a parallel circuit of the opposing switching element and the opposing diode.

If current flows in the parallel circuit of the opposing switching element and opposing diode from the anode to the cathode of the opposing diode, a forward current is flowing in the opposing diode. Therefore, it is possible to appropriately determine whether a forward current is flowing in the opposing diode based on the direction of the current flowing in the parallel circuit.

In one example switching circuit disclosed herein, an opposing command signal including a turn-on command and a turn-off command for the opposing switching element may be input to the target gate control circuit and the opposing gate control circuit. The opposing gate control circuit may control the potential of the gate of the opposing switching element based on the opposing command signal. When the target gate control circuit receives the turn-on command while a forward current is flowing through the opposing diode, it may lower the potential of the gate of the target switching element from the first gate-off potential to the second gate-off potential, and then maintain the potential of the gate of the target switching element at the second gate-off potential until the turn-on of the opposing switching element is complete.

This configuration makes it possible to shorten the period during which the second gate-off potential (i.e., negative potential) is applied to the gate of the target switching element.

In one example switching circuit disclosed herein, the target gate control circuit may determine whether turn-on of the opposing switching element is complete based on the potential of the gate of the opposing switching element.

This configuration makes it possible to effectively determine whether the opposing switching element has been turned on.

In one example switching circuit disclosed in this specification, the target gate control circuit may determine whether turn-on of the opposing switching element is complete based on the voltage between the high-potential main terminal and the low-potential main terminal of the target switching element.

This configuration makes it possible to effectively determine whether the opposing switching element has been turned on.

In one example of a switching circuit disclosed in this specification, the target gate control circuit may include a rise detection circuit that detects the amount of rise in the gate potential of the target switching element at the second timing, and a rise-amount-second gate-off potential correction circuit that lowers the second gate-off potential as the rise detected by the rise detection circuit increases.

This configuration effectively suppresses deterioration of the target switching element.

In one example of a switching circuit disclosed in this specification, the increase amount detection circuit may include a peak value hold circuit that holds the peak value of the potential of the gate of the target switching element, and a reset circuit that resets the peak value after the peak value is held and before the next second timing arrives.

This configuration makes it possible to effectively detect the increase in gate potential of the target switching element at the second timing.

An example switching circuit disclosed in this specification may further include a temperature sensor and a temperature-second gate-off potential correction circuit that lowers the second gate-off potential as the temperature detected by the temperature sensor increases.

This configuration effectively suppresses deterioration of the target switching element.

The inverter 10 shown in FIG. 1 is mounted on a vehicle. The vehicle is also equipped with a battery 80 and a motor 82. The motor 82 is a three-phase motor. The motor 82 drives the vehicle's drive wheels to propel the vehicle. The inverter 10 has a high-potential wiring 12, a low-potential wiring 14, and three output wirings 16a to 16c. The high-potential wiring 12 is connected to the positive electrode of the battery 80. The low-potential wiring 14 is connected to the negative electrode of the battery 80. Therefore, the output voltage (i.e., DC voltage) of the battery 80 is applied between the high-potential wiring 12 and the low-potential wiring 14. The output wirings 16a to 16c are connected to the motor 82. The inverter 10 converts the DC power supplied by the battery 80 between the high-potential wiring 12 and the low-potential wiring 14 into three-phase AC power and outputs the three-phase AC power to the output wirings 16a to 16c. The three-phase AC power output by the inverter 10 is supplied to the motor 82 via output wiring 16a-16c.

The inverter 10 has three switching circuits 20. Each switching circuit 20 has a switching element 21 and a switching element 22. The switching elements 21 and 22 are FETs (i.e., field effect transistors). However, the switching elements 21 and 22 may also be IGBTs (i.e., insulated gate bipolar transistors). The drain of the switching element 21 is connected to the high-potential wiring 12. The source of the switching element 21 is connected to the drain of the switching element 22. The source of the switching element 22 is connected to the low-potential wiring 14. Each switching circuit 20 has a gate control circuit 25 and 26. The gate control circuit 25 is connected to the gate G21 of the switching element 21. The gate control circuit 25 switches the switching element 21 by controlling the gate potential Vg21 of the switching element 21. The gate control circuit 26 is connected to the gate G22 of the switching element 22. The gate control circuit 26 switches the switching element 22 by controlling the gate potential Vg22 of the switching element 22. Each switching circuit 20 has diodes 23 and 24. The diodes 23 and 24 may be body diodes of the switching elements 21 and 22, or may be diodes provided separately from the diodes 23 and 24. The diode 23 is connected in parallel to the switching element 21. The anode of the diode 23 is connected to the source of the switching element 21. The cathode of the diode 23 is connected to the drain of the switching element 21. The diode 24 is connected in parallel to the switching element 22. The anode of the diode 24 is connected to the source of the switching element 22. The cathode of the diode 24 is connected to the drain of the switching element 22. Each of the three switching circuits 20 is connected to a corresponding output wiring 16. That is, the output wiring 16a is connected to the switching circuit 20a of the three switching circuits 20. The output wiring 16b is connected to the switching circuit 20b of the three switching circuits 20. The output wiring 16c is connected to the switching circuit 20c of the three switching circuits 20. In each of the three switching circuits 20, an output wiring 16 is connected to the connection point between the source of the switching element 21 and the drain of the switching element 22. When each switching element 21, 22 of each switching circuit 20 switches, three-phase AC power is output to the output wiring 16a to 16c.

The inverter 10 has current sensors 31 to 33. Current sensor 31 detects the current Iout1 in output wiring 16a. Current sensor 32 detects the current Iout2 in output wiring 16b. Current sensor 33 detects the current Iout3 in output wiring 16c.

The inverter 10 has a control device 30. A control target value for the motor 82 is input to the control device 30 from an external device. The control device 30 also receives the detected values of currents Iout1 to Iout3 detected by current sensors 31 to 33. The control device 30 calculates signals SG1 and SG2 for the three switching circuits 20 based on the control target value for the motor 82, the currents Iout1 to Iout3, etc. The signal SG1 is a value that commands the switching timing of the switching element 21, and the signal SG2 is a value that commands the switching timing of the switching element 22. The control device 30 calculates different signals SG1 and SG2 for each switching circuit 20. The control device 30 transmits the signals SG1 and SG2 to the corresponding switching circuits 20. The control device 30 also calculates a signal CP based on the currents Iout1 to Iout3. The signal CP indicates the direction of the currents Iout1 to Iout3. That is, signal CP indicates whether current Iout is flowing in a direction from switching circuit 20 toward motor 82 (hereinafter referred to as the outflow direction) or in a direction from motor 82 toward switching circuit 20 (hereinafter referred to as the inflow direction). Control device 30 transmits signal CP indicating the direction of current Iout1 to switching circuit 20a, transmits signal CP indicating the direction of current Iout2 to switching circuit 20b, and transmits signal CP indicating the direction of current Iout3 to switching circuit 20c.

Next, the switching circuit 20 will be described in detail. Since switching circuits 20a to 20c have the same configuration, only switching circuit 20a will be described below. Figure 2 shows the details of the gate control circuits 25 and 26 of switching circuit 20a. In the following description, each potential within gate control circuit 25 refers to a potential based on the potential of the source of switching element 21, and each potential within gate control circuit 25 refers to a potential based on the potential of the source of switching element 22.

The gate control circuit 25 switches the switching element 21 by changing the gate potential Vg21 of the switching element 21. The gate control circuit 25 has a VCC line 43, a source line 48, and a DC power supply 46. The VCC line 43 is applied with a potential VCC. The source line 48 is connected to the source of the switching element 21. That is, the potential of the source line 48 is 0V (i.e., the same potential as the source of the switching element 21). The DC power supply 46 outputs a negative potential -VNG lower than 0V. The gate control circuit 25 changes the gate potential Vg21 between potentials VCC, 0V, and the negative potential -VNG. The gate threshold of the switching element 21 (i.e., the minimum gate potential Vg21 required to turn on the switching element 21) is lower than potential VCC and higher than 0V. Therefore, the potential VCC is the gate-on potential that turns on the switching element 21, and 0V and the negative potential -VNG are the gate-off potentials that turn off the switching element 21. The gate control circuit 25 has a gate-on switch 40, a gate-off switch 41, a gate-off switch 42, a gate-on resistor 44, a gate-off resistor 45, and a control IC 47.

The gate-on switch 40 and gate-on resistor 44 are connected in series between the VCC wiring 43 and gate G21. The gate-on switch 40 is composed of a switching element such as an FET. The gate-on switch 40 is controlled by a control IC 47. When the gate-on switch 40 is turned on, a gate current flows from the VCC wiring 43 through the gate-on switch 40 and gate-on resistor 44 to gate G21, charging the gate G21. This allows the gate potential Vg21 to rise to the potential VCC.

The gate-off resistor 45 and gate-off switch 41 are connected in series between the gate G21 and the source wiring 48. The gate-off switch 41 is composed of a switching element such as an FET. The gate-off switch 41 is controlled by a control IC 47. When the gate-off switch 41 is turned on, a gate current flows from the gate G21 through the gate-off resistor 45 and gate-off switch 41 to the source wiring 48, discharging the gate G21. This allows the gate potential Vg21 to drop to 0V.

The DC power supply 46 applies a voltage VNG between its positive and negative electrodes. The positive electrode of the DC power supply 46 is connected to the source wiring 48. Therefore, the potential of the negative electrode of the DC power supply 46 is a negative potential -VNG (i.e., a potential lower than the source of the switching element 21). The negative electrode of the DC power supply 46 is connected to the gate G21 via the gate-off switch 42. The gate-off switch 42 is composed of a switching element such as an FET. The gate-off switch 42 is controlled by the control IC 47. When the gate-off switch 42 is turned on, a negative potential -VNG is applied to the gate G21. The negative potential -VNG can be set to a value that satisfies the equation -VNG = Vgth - Vin Ciss/Crss. Note that Vgth is the gate threshold of the switching element 21, Vin is the voltage between the high-potential wiring 12 and the low-potential wiring 14, Ciss is the input capacitance of the switching element 21, and Crss is the feedback capacitance of the switching element 21.

As described above, the control IC 47 controls the gate-on switch 40, the gate-off switch 41, and the gate-off switch 42. The control IC 47 controls these switches to control the gate potential Vg21. The control IC 47 is also connected to the gate G21 via the gate potential detection wiring 49, allowing it to detect the gate potential Vg21. Signals CP, SG1, SG2, Son1, and Son2 are input and output to and from the control IC 47. These signals are input and output to and from the control IC 47 via the insulating element 38. As described above, the signals CP, SG1, and SG2 are transmitted from the control device 30 and input to the control IC 47. The signal Son1 indicates whether the switching element 21 is on or off, and is transmitted from the control IC 47 to the control IC 57, described below. Control IC 47 detects gate potential Vg21 via gate potential detection wiring 49, determines whether switching element 21 is on or off based on the detected gate potential Vg21, and transmits the determination result as signal Son1 to control IC 57. Signal Son2 is a signal indicating whether switching element 22 is on or off, and is transmitted from control IC 57 to control IC 47.

The gate control circuit 26 switches the switching element 22 by changing the gate potential Vg22 of the switching element 22. The gate control circuit 26 has a VCC line 53, a source line 58, and a DC power supply 56. The VCC line 53 is applied with a potential VCC. The source line 58 is connected to the source of the switching element 22. That is, the potential of the source line 58 is 0V (i.e., the same potential as the source of the switching element 22). The DC power supply 56 outputs a negative potential -VNG lower than 0V. The gate control circuit 26 changes the gate potential Vg22 between the potential VCC, 0V, and the negative potential -VNG. The gate threshold of the switching element 22 (i.e., the minimum gate potential Vg22 required to turn on the switching element 22) is lower than the potential VCC and higher than 0V. Therefore, the potential VCC is the gate-on potential that turns on the switching element 22, and 0V and the negative potential -VNG are the gate-off potentials that turn off the switching element 22. The gate control circuit 26 has a gate-on switch 50, a gate-off switch 51, a gate-off switch 52, a gate-on resistor 54, a gate-off resistor 55, and a control IC 57.

The gate-on switch 50 and gate-on resistor 54 are connected in series between the VCC wiring 53 and gate G22. The gate-on switch 50 is composed of a switching element such as an FET. The gate-on switch 50 is controlled by a control IC 57. When the gate-on switch 50 is turned on, a gate current flows from the VCC wiring 53 through the gate-on switch 50 and gate-on resistor 54 to gate G22, charging gate G22. This allows the gate potential Vg22 to rise to the potential VCC.

The gate-off resistor 55 and gate-off switch 51 are connected in series between the gate G22 and the source wiring 58. The gate-off switch 51 is composed of a switching element such as an FET. The gate-off switch 51 is controlled by a control IC 57. When the gate-off switch 51 is turned on, a gate current flows from the gate G22 through the gate-off resistor 55 and gate-off switch 51 to the source wiring 58, discharging the gate G22. This allows the gate potential Vg22 to drop to 0V.

The DC power supply 56 applies a voltage VNG between its positive and negative electrodes. The positive electrode of the DC power supply 56 is connected to the source wiring 58. Therefore, the potential of the negative electrode of the DC power supply 56 is a negative potential -VNG (i.e., a potential lower than the source of the switching element 22). The negative electrode of the DC power supply 56 is connected to the gate G22 via the gate-off switch 52. The gate-off switch 52 is composed of a switching element such as an FET. The gate-off switch 52 is controlled by the control IC 57. When the gate-off switch 52 is turned on, a negative potential -VNG is applied to the gate G22. The negative potential -VNG can be set to a value that satisfies the equation -VNG = Vgth - Vin Ciss/Crss. Note that Vgth is the gate threshold of the switching element 22, Vin is the voltage between the high-potential wiring 12 and the low-potential wiring 14, Ciss is the input capacitance of the switching element 22, and Crss is the feedback capacitance of the switching element 22.

As described above, the control IC 57 controls the gate-on switch 50, the gate-off switch 51, and the gate-off switch 52. The control IC 57 controls these switches to control the gate potential Vg22. The control IC 57 is also connected to the gate G22 via the gate potential detection wiring 59, allowing it to detect the gate potential Vg22. Signals CP, SG1, SG2, Son1, and Son2 are input and output to and from the control IC 57. These signals are input and output to and from the control IC 57 via the insulating element 38. As described above, the signals CP, SG1, and SG2 are transmitted from the control device 30 and input to the control IC 57. The signal Son2 is a signal indicating whether the switching element 22 is on or off, and is transmitted from the control IC 57 to the control IC 47. Control IC 57 detects gate potential Vg22 via gate potential detection wiring 59, determines whether switching element 22 is on or off based on the detected gate potential Vg22, and transmits the determination result as signal Son2 to control IC 47. Signal Son1 is a signal indicating whether switching element 21 is on or off, and is transmitted from control IC 47 to control IC 57 as described above.

Next, the path of the current flowing within the switching circuit 20a will be described. The control ICs 47 and 57 control the switching elements 21 and 22 so that they alternately turn on with dead times sandwiched between them. That is, the control ICs 47 and 57 control the switching elements 21 and 22 so that a first on-time in which the switching element 21 is on and the switching element 22 is off, a first dead time in which both the switching elements 21 and 22 are off, a second on-time in which the switching element 22 is on and the switching element 21 is off, and a second dead time in which both the switching elements 21 and 22 are off are repeated in this order. The current path within the switching circuit 20a changes depending on the state of the switching elements 21 and 22. Furthermore, the manner in which the current path within the switching circuit 20a changes differs depending on the direction of the current Iout1 flowing through the output wiring 16a.

Figure 3 shows how the current path changes when the direction of current Iout1 shown in Figure 1 is the outflow direction. Figure 3(a) shows the first on-time, Figure 3(b) shows the first dead time, Figure 3(c) shows the second on-time, and Figure 3(d) shows the second dead time. As shown in Figure 3(a), during the first on-time, switching element 21 is on and switching element 22 is off, so current I flows from high-potential wiring 12 to output wiring 16a through switching element 21. In this state, the potential of output wiring 16a is approximately equal to the potential of high-potential wiring 12. Next, during the first dead time (i.e., Figure 3(b)), switching element 21 turns off. This stops the current through switching element 21. The potential of output wiring 16a drops due to an induced voltage generated by the inductance L of motor 82, turning diode 24 on. As a result, current flows from low-potential wiring 14 to output wiring 16a through diode 24. That is, a forward current flows through the diode 24. In this state, the potential of the output wiring 16a is approximately equal to the potential of the low-potential wiring 14. Next, the switching element 22 is turned on during the second on-time (i.e., FIG. 3(c)). Then, current I flows from the low-potential wiring 14 to the output wiring 16a through the parallel circuit of the diode 24 and the switching element 22. That is, when the switching element 22 is turned on, the path through which current I flows branches to the diode 24 and the switching element 22. In other words, even when the switching element 22 is turned on, the state in which current I flows from the low-potential wiring 14 to the output wiring 16a does not change, and the potential of the output wiring 16a hardly changes. Therefore, the voltage applied to the switching element 21 hardly changes. Therefore, even if the switching element 22 is turned on while a forward current is flowing through the diode 24, there is no risk of erroneous firing of the switching element 21. Next, the switching element 22 is turned off during the second dead time (i.e., FIG. 3(d)). As a result, the current stops flowing through the switching element 22. In this state, current I flows from the low-potential wiring 14 to the output wiring 16a through the diode 24. Next, the first on-time (i.e., FIG. 3A) occurs again, and the switching element 21 turns on. As described above, current I flows from the high-potential wiring 12 to the output wiring 16a through the switching element 21, and the potential of the output wiring 16a becomes approximately equal to the potential of the high-potential wiring 12. That is, when the switching element 21 turns on, the potential of the output wiring 16a suddenly rises from approximately the same potential as the low-potential wiring 14 to approximately the same potential as the high-potential wiring 12. This sudden rise in the potential of the output wiring 16a causes a sudden rise in the potential of the drain of the switching element 22. Then, due to capacitive coupling between the drain and gate G22 of the switching element 22, the gate potential Vg22 momentarily rises. This momentary rise in the gate potential Vg22 may cause the switching element 22 to erroneously fire. In other words, if switching element 21 is turned on when no forward current is flowing through diode 23, there is a risk of erroneous firing of switching element 22. As explained above, if the direction of current Iout1 is the outflow direction, there is a risk of erroneous firing of switching element 22 when switching element 21 is turned on, but there is no risk of erroneous firing of switching element 21 when switching element 22 is turned on.

Figure 4 shows how the current path changes when the direction of current Iout1 shown in Figure 1 is the inflow direction. Figure 4(a) shows the first on-time, Figure 4(b) shows the first dead time, Figure 4(c) shows the second on-time, and Figure 4(d) shows the second dead time. As shown in Figure 4(c), during the second on-time, switching element 22 is on and switching element 21 is off, so current I flows from output wiring 16a to low-potential wiring 14 through switching element 22. In this state, the potential of output wiring 16a is approximately equal to the potential of low-potential wiring 14. Next, during the second dead time (i.e., Figure 4(d)), switching element 22 turns off. This stops the current through switching element 22. The potential of output wiring 16a rises due to an induced voltage generated by the inductance L of motor 82, turning diode 23 on. As a result, current I flows from output wiring 16a to high-potential wiring 12 through diode 23. That is, a forward current flows through the diode 23. In this state, the potential of the output wiring 16a is approximately equal to the potential of the high-potential wiring 12. Next, the switching element 21 is turned on during the first on-time (i.e., FIG. 4A). Then, a current I flows from the output wiring 16a to the high-potential wiring 12 through the parallel circuit of the diode 23 and the switching element 21. That is, when the switching element 21 is turned on, the path through which the current I flows branches to the diode 23 and the switching element 21. In other words, even when the switching element 21 is turned on, the state in which the current I flows from the output wiring 16a to the high-potential wiring 12 remains unchanged, and the potential of the output wiring 16a changes very little. Therefore, the voltage applied to the switching element 22 changes very little. Therefore, even if the switching element 21 is turned on while a forward current is flowing through the diode 23, there is no risk of the switching element 22 erroneously igniting. Next, the switching element 21 is turned off during the first dead time (i.e., FIG. 4B). As a result, the current stops flowing through the switching element 21. In this state, current I flows from the output wiring 16 to the high-potential wiring 12 through the diode 23. Next, the second on-time (i.e., FIG. 4(c)) occurs again, and the switching element 22 turns on. As a result, as described above, current I flows from the output wiring 16a to the low-potential wiring 14 through the switching element 22, and the potential of the output wiring 16a becomes approximately equal to the potential of the low-potential wiring 14. That is, when the switching element 22 turns on, the potential of the output wiring 16a suddenly drops from approximately the same potential as the high-potential wiring 12 to approximately the same potential as the low-potential wiring 14. Because the potential of the output wiring 16a suddenly drops in this way, the potential of the drain of the switching element 21 relative to the source suddenly rises. Then, due to capacitive coupling between the drain and gate G21 of the switching element 21, the gate potential Vg21 momentarily rises. This momentary rise in the gate potential Vg21 may cause the switching element 21 to erroneously fire. In other words, if switching element 22 is turned on when no forward current is flowing through diode 24, there is a risk of erroneous firing of switching element 21. As explained above, if the direction of current Iout1 is the inflow direction, there is a risk of erroneous firing of switching element 21 when switching element 22 is turned on, but there is no risk of erroneous firing of switching element 22 when switching element 22 is turned on.

Next, we will explain how the switching circuit 20 controls the gate potentials Vg21 and Vg22. Figure 5 shows the processing performed by the control IC 47. Figure 6 shows the processing performed by the control IC 57. The control ICs 47 and 57 repeatedly perform the processing shown in Figures 5 and 6 while the inverter 10 is operating.

First, we will explain the case where the direction of current Iout1 is the outflow direction. When the direction of current Iout1 is the outflow direction, control device 30 controls signal CP to be HIGH. Figure 7 shows the changes in each value when the direction of current Iout1 is the outflow direction. In Figure 7, period Ton1 is the first on-time, period Td1 is the first dead time, period Ton2 is the second on-time, and period Td2 is the second dead time. Also, as described above, signal SG1 is a value that commands the on-off of switching element 21, and signal SG2 is a value that commands the on-off of switching element 22.

As shown in FIG. 7, during the second on-time Ton2, signal SG1 is OFF and signal SG2 is ON. Because signal SG1 is OFF, control IC 47 determines YES in step S2 of FIG. 5 and executes step S4. Because signal CP is HIGH, control IC 47 determines YES in step S4 and executes step S12. In step S12, control IC 47 controls gate potential Vg21 to 0 V by turning gate on switch 40 OFF, gate off switch 41 ON, and gate off switch 42 OFF. Furthermore, because signal SG2 is ON during the second on-time Ton2, control IC 57 determines NO in step S52 of FIG. 6 and executes step S64. In step S64, the control IC 57 controls the gate potential Vg22 to potential VCC by turning on the gate-on switch 50 and turning off the gate-off switches 51 and 52. Therefore, as shown in FIG. 7, during the second on-time Ton2, the gate potential Vg21 is controlled to 0 V and the gate potential Vg22 is controlled to potential VCC. Therefore, during the second on-time Ton2, the switching element 21 is off and the switching element 22 is on. As a result, the current I flows through the current path shown in FIG. 3(c). In this state, the potential of the output wiring 16a is approximately equal to the potential of the low-potential wiring 14, so the drain-source voltage Vds21 of the switching element 21 is high and the drain-source voltage Vds22 of the switching element 22 is low.

After that, at timing t1, signal SG2 switches from ON to OFF. At timing t1, signal SG1 is maintained OFF. The period following timing t1 is a second dead time Td2 during which signals SG1 and SG2 are both OFF. When signal SG2 switches from ON to OFF, control IC 57 determines YES in step S52 of FIG. 6 and executes step S54. Because signal CP is HIGH, control IC 57 determines YES in step S54 and executes step S56. Because signal SG1 is OFF, control IC 57 determines NO in step S56 and executes step S62. In step S62, control IC 57 controls gate-on switch 50 to OFF, gate-off switch 51 to ON, and gate-off switch 52 to OFF. As a result, gate G22 is discharged via gate-off resistor 55 and gate-off switch 52. Therefore, after timing t1, gate potential Vg22 drops to 0 V, turning off switching element 22. Control IC 57 maintains gate potential Vg22 at 0 V by repeating steps S52, S54, S56, and S62 during second dead time Td2. Furthermore, control IC 47 maintains gate potential Vg21 at 0 V during second dead time Td2, similar to second on time Ton2, to keep switching element 21 off. Therefore, during second dead time Td2, current I flows through the current path shown in FIG. 3(d). During second dead time Td2, voltages Vds21 and Vds22 change little from second on time Ton2.

After that, at timing t2, signal SG1 switches from OFF to ON. At timing t2, signal SG2 remains OFF. That is, the period after timing t2 is the first on-time Ton1, during which signal SG1 is ON and signal SG2 is OFF.

When signal SG1 switches from OFF to ON at timing t2, control IC 47 determines NO in step S2 of FIG. 5 and executes step S14. In step S14, control IC 47 controls gate-on switch 40 to ON and gate-off switches 41 and 42 to OFF. As a result, gate G21 is charged via gate-on resistor 44 and gate-on switch 40. Therefore, after timing t2, gate potential Vg21 rises. Gate potential Vg21 reaches potential VCC a predetermined time after timing t2. Control IC 47 monitors gate potential Vg21 via gate potential detection wiring 49. After timing t2, control IC 47 determines whether turn-on of switching element 21 is complete based on gate potential Vg21. Control IC 47 can determine that turn-on of switching element 21 is complete when gate potential Vg21 rises to a reference value (e.g., a value close to potential VCC). In another example, the control IC 47 can determine that the turning on of the switching element 21 is complete when the rate of increase of the gate potential Vg21 drops below a reference value (i.e., when the gate potential Vg21 stabilizes). The control IC 47 outputs a LOW signal Son1 if the turning on of the switching element 21 is not complete, and outputs a HIGH signal Son1 if the turning on of the switching element 21 is complete. In FIG. 7, the control IC 47 switches the signal Son1 from LOW to HIGH at timing t3.

Also, when signal SG1 switches from OFF to ON at timing t2, control IC 57 determines YES in step S56 and executes step S58. In step S58, control IC 57 determines whether or not turning on of switching element 21 is complete based on signal Son1. During period Ta immediately after timing t2 (i.e., period Ta from timing t2 to timing t3), turning on of switching element 21 is not complete, and signal Son1 is LOW. Therefore, control IC 57 determines NO in step S58 and executes step S60. In step S60, control IC 57 controls gate potential Vg22 to the negative potential -VNG by turning gate-on switch 50 OFF, gate-off switch 51 OFF, and gate-off switch 52 ON. During period Ta, control IC 57 repeats steps S58 and S60 to maintain gate potential Vg22 at the negative potential -VNG. Thereafter, when signal Son1 switches from LOW to HIGH at timing t3, control IC 57 determines YES in step S58 and executes step S62. As described above, in step S62, control IC 57 controls gate potential Vg22 to 0 V. During the first on-time Ton1 from timing t3 onwards, control IC 57 repeats steps S52, S54, S56, S58, and S62 to maintain gate potential Vg22 at 0 V. In this way, during the first on-time Ton1, control IC 57 controls gate potential Vg22 to the negative potential -VNG during period Ta from timing t2 to timing t3, and controls gate potential Vg22 to 0 V from timing t3 onwards.

When signal SG1 switches from OFF to ON at timing t2, switching element 21 turns on during period Ta. As a result, as described above, the current path changes from the state shown in FIG. 3(d) to the state shown in FIG. 3(a), causing a sudden rise in the potential of output wiring 16a. Therefore, during period Ta, voltage Vds21 suddenly drops and voltage Vds22 suddenly rises. As a result of the sudden rise in voltage Vds22, capacitive coupling between the drain and gate G22 of switching element 22 can cause a momentary rise in the potential of gate G22. That is, as shown in FIG. 7, a momentary rise 84 in gate potential Vg22 can occur during period Ta. In this embodiment, because control IC 57 controls gate potential Vg22 to a negative potential -VNG during period Ta, even if rise 84 occurs, gate potential Vg22 is unlikely to exceed the gate threshold. This prevents erroneous firing of switching element 22.

After that, at timing t4, signal SG1 switches from ON to OFF. At timing t4, signal SG2 remains OFF. That is, the period following timing t4 is the first dead time Td1 during which both signals SG1 and SG2 are OFF. When signal SG1 switches from ON to OFF, control IC 47 determines YES in step S2 of FIG. 5 and executes step S4. Because signal CP is HIGH, control IC 47 determines YES in step S4 and executes step S12. As described above, in step S12, control IC 47 controls gate potential Vg21 to 0 V. Therefore, switching element 21 is turned off. Furthermore, when signal SG1 switches from ON to OFF, control IC 57 determines NO in step S56 of FIG. 6 and executes step S62. As described above, in step S62, the control IC 57 controls the gate potential Vg22 to 0 V. Therefore, the switching element 22 is maintained off. Therefore, at timing t4, the current path switches from the state shown in FIG. 3(a) to the state shown in FIG. 3(b). At this time, the potential of the output wiring 16a drops suddenly, causing the voltage Vds21 to rise suddenly and the voltage Vds22 to fall suddenly.

After that, at timing t5, signal SG2 switches from OFF to ON. At timing t5, signal SG1 remains OFF. That is, the period after timing t5 is the second on-time Ton2, during which signal SG2 is ON and signal SG1 is OFF. When signal SG2 switches from OFF to ON, control IC 57 determines NO in step S52 of FIG. 6 and executes step S64. As described above, in step S64, control IC 57 controls gate potential Vg22 to potential VCC. Therefore, switching element 22 is turned on. Furthermore, even when signal SG2 switches from OFF to ON at timing t5, control IC 47 does not change its operation. That is, the control IC 47 repeatedly executes steps S2, S4, and S12 from the first dead time Td1 to the second on time Ton2, controlling the gate potential Vg21 to 0 V. That is, the control IC 47 maintains the switching element 21 in the off state. Therefore, at timing t5, the current path switches from the state shown in FIG. 3(b) to the state shown in FIG. 3(c). As described above, when the current path switches from the state shown in FIG. 3(b) to the state shown in FIG. 3(c), the potential of the output wiring 16a changes very little. Therefore, no instantaneous rise in the gate potential Vg21 occurs at timing t5. Therefore, even if the gate potential Vg21 is not controlled to a negative potential at timing t5, erroneous firing of the switching element 21 does not occur.

Next, we will explain the case where the direction of current Iout1 is the inflow direction. When the direction of current Iout1 is the inflow direction, control device 30 controls signal CP to LOW. Figure 8 shows the changes in each value when the direction of current Iout1 is the inflow direction.

As shown in FIG. 8, during the first on-time Ton1, signal SG1 is ON and signal SG2 is OFF. Because signal SG1 is ON, control IC 47 determines NO in step S2 of FIG. 5 and executes step S14. As described above, control IC 47 controls gate potential Vg21 to potential VCC in step S14. Also, because signal SG2 is OFF, control IC 57 determines YES in step S52 of FIG. 6 and executes step S54. Because signal CP is LOW, control IC 57 determines NO in step S54 and executes step S62. As described above, control IC 57 controls gate potential Vg22 to 0 V in step S62. Therefore, during the first on-time Ton1, switching element 21 is ON and switching element 22 is OFF. As a result, current I flows through the current path shown in FIG. 4(a). In this state, the potential of the output wiring 16a is approximately equal to the potential of the high-potential wiring 12, so the voltage Vds21 is low and the voltage Vds22 is high.

After that, at timing t11, signal SG1 switches from ON to OFF. At timing t11, signal SG2 is maintained OFF. The period after timing t11 is the first dead time Td1, during which signals SG1 and SG2 are both OFF. When signal SG1 switches from ON to OFF, control IC 47 determines YES in step S2 of FIG. 5 and executes step S4. Because signal CP is LOW, control IC 47 determines NO in step S4 and executes step S6. Because signal SG2 is OFF, control IC 47 determines NO in step S6 and executes step S12. As described above, in step S12, control IC 47 controls gate potential Vg22 to 0 V. Furthermore, the control IC 57 maintains the gate potential Vg22 at 0 V during the first dead time Td1, just as it did during the first on-time Ton1. Therefore, during the first dead time Td1, the current I flows through the current path shown in FIG. 4(b). During the first dead time Td1, the voltages Vds21 and Vds22 change very little from the first on-time Ton1.

After that, at timing t12, signal SG2 switches from OFF to ON. At timing t12, signal SG1 remains OFF. That is, the period after timing t12 is the second on-time Ton2, during which signal SG2 is ON and signal SG1 is OFF.

When signal SG2 switches from OFF to ON at timing t12, control IC 57 determines NO in step S52 of FIG. 6 and executes step S64. In step S64, control IC 57 controls gate-on switch 50 to ON and gate-off switches 51 and 52 to OFF. As a result, gate G22 is charged via gate-on resistor 54 and gate-on switch 50. Therefore, after timing t12, gate potential Vg22 rises. Gate potential Vg22 reaches potential VCC a predetermined time after timing t12. Control IC 57 monitors gate potential Vg22 via gate potential detection wiring 59. After timing t12, control IC 57 determines whether turn-on of switching element 22 has been completed based on gate potential Vg22. The control IC 57 can determine that the turn-on of the switching element 22 is complete when the gate potential Vg22 rises to a reference value (e.g., a value close to the potential VCC). In another example, the control IC 57 can determine that the turn-on of the switching element 22 is complete when the rate of rise of the gate potential Vg22 drops below the reference value (i.e., when the gate potential Vg22 stabilizes). The control IC 57 outputs a LOW signal Son2 if the turn-on of the switching element 22 is not complete, and outputs a HIGH signal Son2 if the turn-on of the switching element 22 is complete. In FIG. 8 , the control IC 57 switches the signal Son2 from LOW to HIGH at timing t13.

Furthermore, when signal SG2 switches from OFF to ON at timing t12, control IC 47 determines YES in step S6 and executes step S8. In step S8, control IC 47 determines whether or not turning on of switching element 22 is complete based on signal Son2. During period Tb immediately after timing t12 (i.e., period Tb from timing t12 to timing t13), turning on of switching element 22 is not complete, and signal Son2 is LOW. Therefore, control IC 47 determines NO in step S8 and executes step S10. In step S10, control IC 47 controls gate potential Vg21 to negative potential -VNG by turning gate-on switch 50 OFF, gate-off switch 51 OFF, and gate-off switch 52 ON. During the period Tb, the signal Son2 is maintained at LOW, so the control IC 47 repeats steps S8 and S10 to maintain the gate potential Vg21 at the negative potential −VNG. Thereafter, when the signal Son2 switches from LOW to HIGH at timing t13, the control IC 47 determines YES in step S8 and executes step S12. As described above, in step S12, the control IC 47 controls the gate potential Vg22 to 0 V. During the second on-time Ton2 after timing t13, the control IC 47 repeats steps S2, S4, S6, S8, and S12 to maintain the gate potential Vg21 at 0 V. Thus, during the second on-time Ton2, the control IC 47 controls the gate potential Vg21 to the negative potential -VNG during the period Tb between timing t12 and timing t13, and controls the gate potential Vg21 to 0 V after timing t13.

When signal SG2 switches from OFF to ON at timing t12, switching element 22 turns on during period Tb. As a result, as described above, the current path changes from the state shown in FIG. 4(b) to the state shown in FIG. 4(c), causing a sudden drop in the potential of output wiring 16a. Therefore, during period Tb, voltage Vds21 rises suddenly, and voltage Vds22 falls suddenly. As a result of this sudden rise in voltage Vds21, capacitive coupling between the drain and gate G21 of switching element 21 can cause gate potential Vg21 to momentarily rise. That is, as shown in FIG. 8, a momentary rise 86 in gate potential Vg21 can occur during period Tb. In this embodiment, because control IC 47 controls gate potential Vg21 to a negative potential -VNG during period Tb, even if rise 86 occurs, gate potential Vg21 is unlikely to exceed the gate threshold. This prevents erroneous firing of switching element 21.

Thereafter, at timing t14, signal SG2 switches from ON to OFF. At timing t14, signal SG1 remains OFF. That is, the period following timing t14 is the second dead time Td2, during which both signals SG1 and SG2 are OFF. When signal SG2 switches from ON to OFF, control IC 57 determines YES in step S52 of FIG. 6 and executes step S54. Because signal CP is LOW, control IC 57 determines NO in step S54 and executes step S62. As described above, in step S62, control IC 57 controls gate potential Vg22 to 0 V. Furthermore, when signal SG2 switches from ON to OFF, control IC 57 determines NO in step S6 of FIG. 5 and executes step S12. As described above, in step S12, the control IC 47 controls the gate potential Vg21 to 0 V. Therefore, at timing t14, the current path switches from the state shown in FIG. 4(c) to the state shown in FIG. 4(d). At this time, the potential of the output wiring 16a rises sharply, causing the voltage Vds21 to drop sharply and the voltage Vds22 to rise sharply.

After that, at timing t15, signal SG1 switches from OFF to ON. At timing t15, signal SG2 remains OFF. That is, the period following timing t15 is the first on-time Ton1, during which signal SG1 is ON and signal SG2 is OFF. When signal SG1 switches from OFF to ON, control IC 47 determines NO in step S2 of FIG. 5 and executes step S14. As described above, in step S14, control IC 47 controls gate potential Vg21 to potential VCC. Furthermore, even when signal SG1 switches from OFF to ON at timing t5, control IC 57 does not change its operation. That is, control IC 57 repeatedly executes steps S52, S54, and S62 from the second dead time Td2 through the first on-time Ton1, controlling gate potential Vg22 to 0 V. Therefore, at timing t15, the current path switches from the state shown in FIG. 4(d) to the state shown in FIG. 4(a). As described above, when the current path switches from the state shown in FIG. 4(d) to the state shown in FIG. 4(a), the potential of the output wiring 16a changes very little. Therefore, at timing t15, there is no momentary rise in the gate potential Vg22. For this reason, even if the gate potential Vg22 is not controlled to a negative potential at timing t15, erroneous firing of the switching element 22 does not occur.

As described above, the gate control circuit 25 applies a negative potential -VNG to the gate G21 when the switching element 22 turns on while no forward current is flowing through the diode 24 (i.e., during the period Tb in FIG. 8), thereby suppressing erroneous firing of the switching element 21. Furthermore, the gate control circuit 25 applies 0V to the gate G21 when the switching element 22 turns on while a forward current is flowing through the diode 24 (i.e., during the period t5 in FIG. 7). Even if a negative potential is not applied to the gate G21 at the time t5, erroneous firing does not occur. Furthermore, not applying a negative potential at the time t5 reduces stress on the switching element 21. Furthermore, the gate control circuit 26 applies a negative potential -VNG to the gate G22 when the switching element 21 turns on while no forward current is flowing through the diode 23 (i.e., during the period Ta in FIG. 7), thereby suppressing erroneous firing of the switching element 22. Furthermore, the gate control circuit 26 applies 0V to the gate G22 at the timing when the switching element 21 turns on while a forward current is flowing through the diode 23 (i.e., timing t15 in FIG. 8). Even if a negative potential is not applied to the gate G22 at timing t15, false ignition does not occur. Furthermore, by not applying a negative potential at timing t15, stress on the switching element 22 can be reduced.

Furthermore, as shown in FIG. 8, the gate control circuit 25 lowers the gate potential Vg21 to 0V after timing t11 when the signal SG1 switches from ON to OFF, and controls the gate potential Vg21 to the negative potential -VNG after timing t12 when the signal SG2 switches from OFF to ON. In this way, by not applying the negative potential -VNG to the gate G21 during the period from timing t11 to timing t12, stress on the switching element 21 can be reduced. Furthermore, the gate control circuit 25 raises the gate potential Vg21 from the negative potential -VNG to 0V after timing t13 when the switching element 22 has completed turning on. This further shortens the period during which the negative potential -VNG is applied to the gate G21, thereby reducing stress on the switching element 21. As shown in FIG. 7, the gate control circuit 26 reduces the gate potential Vg22 to 0V after timing t1 when the signal SG2 switches from ON to OFF, and controls the gate potential Vg22 to the negative potential -VNG after timing t2 when the signal SG1 switches from OFF to ON. By not applying the negative potential -VNG to the gate G22 between timing t1 and timing t2, stress on the switching element 22 can be reduced. Furthermore, the gate control circuit 26 increases the gate potential Vg22 from the negative potential -VNG to 0V after timing t3 when the switching element 21 has completely turned on. This further shortens the period during which the negative potential -VNG is applied to the gate G22, reducing stress on the switching element 22.

As described above, when switching element 22 is turned on with current Iout1 flowing in the outflow direction, a forward current flows through diode 24. Therefore, the determinations in steps S4 and S6 in FIG. 5 are equivalent to determining whether a forward current flows through diode 24. Also, as described above, when switching element 21 is turned on with current Iout1 flowing in the inflow direction, a forward current flows through diode 23. Therefore, the determinations in steps S54 and S56 in FIG. 6 are equivalent to determining whether a forward current flows through diode 23. In this way, in Example 1, gate control circuits 25 and 26 determine whether a forward current flows through diodes 23 and 24 based on the direction of current Iout1 flowing through output wiring 16a.

Furthermore, the switching circuit 20a of Example 1 can suppress erroneous ignition during startup of the switching circuit 20a. Figure 9 shows the changes in various values during startup. In Figure 9, timing t0 is the startup timing of the switching circuit 20a, and timing tx is the timing at which the signal SG2 first switches from OFF to ON after startup. In conventional control, turning off the switching element triggers application of a negative potential to the gate of the switching element, making it impossible to control the gate potential Vg21 of the switching element 21 to a negative potential in accordance with timing tx at which the switching element 22 first turns on after startup. In contrast, in the switching circuit 20a of Example 1, the control IC 47 determines NO in step S2, NO in step S4, YES in step S6, and NO in step S8 at timing tx. Therefore, in step S10, the gate potential Vg21 is controlled to a negative potential -VNG. Therefore, as shown in Figure 9, during the period Tc immediately after timing tx, the gate potential Vg21 is controlled to the negative potential -VNG. This prevents erroneous firing of the switching element 21 during startup.

The potential VCC in Example 1 is an example of a gate-on potential. 0 V in Example 1 is an example of a first gate-off potential. The negative potential -VNG in Example 1 is an example of a second gate-off potential. Note that in Example 1 and Examples 2 to 5 described below, any value equal to or greater than 0 V and less than the gate threshold may be used as the first gate-off potential.

The gate control circuit 25 of Example 1 is an example of a target gate control circuit, and the gate control circuit 26 of Example 1 is an example of an opposing gate control circuit. In this case, the switching element 21 is an example of a target switching element. The drain of the switching element 21 is an example of a high-potential main terminal of the target switching element. The source of the switching element 21 is an example of a low-potential main terminal of the target switching element. The switching element 22 is an example of an opposing switching element. The drain of the switching element 22 is an example of a high-potential main terminal of the opposing switching element. The source of the switching element 22 is an example of a low-potential main terminal of the opposing switching element. The diode 23 is an example of a target diode. The diode 24 is an example of an opposing diode. The timing t5 is an example of a first timing. The period Tb is an example of a second timing. The signal SG2 is an example of an opposing command signal. The switching of the signal SG2 from OFF to ON is an example of a turn-on command. The switching of the signal SG2 from ON to OFF is an example of a turn-off command. Similar correspondence can be achieved in Examples 2 to 5 described below.

Furthermore, gate control circuit 26 in Example 1 can be considered an example of a target gate control circuit, and gate control circuit 25 in Example 1 can be considered an example of an opposing gate control circuit. In this case, switching element 22 is an example of a target switching element. The drain of switching element 22 is an example of a high-potential main terminal of a target switching element. The source of switching element 22 is an example of a low-potential main terminal of a target switching element. Further, switching element 21 is an example of an opposing switching element. The drain of switching element 21 is an example of a high-potential main terminal of an opposing switching element. The source of switching element 21 is an example of a low-potential main terminal of an opposing switching element. Further, diode 24 is an example of a target diode. Further, diode 23 is an example of an opposing diode. Further, timing t15 is an example of a first timing. Further, period Ta is an example of a second timing. Further, signal SG1 is an example of an opposing command signal. Further, switching of signal SG1 from OFF to ON is an example of a turn-on command. Additionally, switching signal SG1 from ON to OFF is an example of a turn-off command. This same correspondence can be applied to Examples 2 to 5 described below.

In Example 1, the control ICs 47 and 57 determine whether the turn-on of the switching elements 21 and 22 is complete based on the gate potentials Vg21 and Vg22. However, in a modified example of Example 1, as shown in FIG. 10, the switching circuit 20a may include gate potential determination circuits 49x and 59x. The gate potential determination circuit 49x compares the gate potential Vg21 with the reference potential Vref21 using a comparator 49y and transmits the comparison result as a signal Son1 to the control IC 57. The reference potential Vref21 is set to the gate potential Vg21 when the turn-on of the switching element 21 is complete. The gate potential determination circuit 59x compares the gate potential Vg22 with the reference potential Vref22 using a comparator 59y and transmits the comparison result as a signal Son2 to the control IC 47. The reference potential Vref22 is set to the gate potential Vg22 when the turn-on of the switching element 22 is complete. Even with this configuration, signals Son1 and Son2 indicating whether or not the switching elements 21 and 22 have been turned on can be appropriately sent to the control ICs 47 and 57.

The switching circuit 20a2 of Example 2 shown in FIG. 11 detects the completion of turn-on of the switching elements 21 and 22 using a method different from that of the switching circuit 20a of Example 1. The switching circuit 20a2 of Example 2 has a drain potential detection circuit 49a instead of the gate potential detection wiring 49. The switching circuit 20a2 of Example 2 also has a drain potential detection circuit 59a instead of the gate potential detection wiring 59. In addition, in the switching circuit 20a2 of Example 2, signals Son1 and Son2 are not transmitted or received between the control IC 47 and the control IC 57. The other configuration of the switching circuit 20a2 of Example 2 is the same as that of the switching circuit 20a of Example 1.

In the switching circuit 20a2 of Example 2, the drain potential detection circuit 49a detects the voltage Vds21 between the source and drain of the switching element 21. Furthermore, the drain potential detection circuit 49a determines whether the switching element 22 is on or not based on the voltage Vds21. That is, when the switching element 22 is turned on at timing t13, the voltage Vds22 becomes low, and as a result, the voltage Vds21 becomes high. Therefore, the drain potential detection circuit 49a can determine whether the switching element 22 is on or not based on whether the voltage Vds21 is equal to or higher than a predetermined value. The determination result by the drain potential detection circuit 49a (i.e., the determination result indicating whether the switching element 22 is on or not) is input to the control IC 47 as the signal Son2. Therefore, in step S8, the control IC 47 can determine whether the turning on of the switching element 22 has been completed based on the signal Son2 input from the drain potential detection circuit 49a.

In the switching circuit 20a2 of Example 2, the drain potential detection circuit 59a detects the voltage Vds22 between the source and drain of the switching element 22. Furthermore, the drain potential detection circuit 59a determines whether the switching element 21 is on or not based on the voltage Vds22. That is, when the switching element 21 is turned on at timing t3, the voltage Vds21 becomes low, and as a result, the voltage Vds22 becomes high. Therefore, the drain potential detection circuit 59a can determine whether the switching element 21 is on or not based on whether the voltage Vds22 is equal to or greater than a predetermined value. The determination result by the drain potential detection circuit 59a (i.e., the determination result indicating whether the switching element 21 is on or not) is input to the control IC 57 as the signal Son1. Therefore, in step S58, the control IC 57 can determine whether the turning on of the switching element 21 has been completed based on the signal Son1 input from the drain potential detection circuit 59a.

The configuration of Example 2 eliminates the need to send and receive signals Son1 and Son2 between control ICs 47 and 57, thereby simplifying the configuration of gate control circuits 25 and 26.

The drain potential detection circuit 49a may have the configuration shown in FIG. 12 or 13. In FIG. 12, when voltage Vds21 exceeds a certain value, diode 49a-1 turns off. Then, the output potential V49a-2 of current source 49a-2 (i.e., the potential at the positive terminal of comparator 49a-3) exceeds reference potential V49a-4 (i.e., the potential at the negative terminal of comparator 49a-3), causing the output signal of comparator 49a-3 to change. Therefore, by inputting the output signal of comparator 49a-3 as signal Son2 to control IC 47, control IC 47 can determine whether voltage Vds21 is equal to or greater than a predetermined value (i.e., whether turning on of switching element 22 is complete). In FIG. 13, voltage Vds21-2, obtained by dividing voltage Vds21 by capacitors 49a-11 and 49a-12, is applied to the positive terminal of comparator 49a-13. When voltage Vds21 rises to a certain value, voltage Vds21-2 exceeds reference potential V49a-14 (i.e., the potential at the negative terminal of comparator 49a-13), causing the output signal of comparator 49a-13 to change. Therefore, by inputting the output signal of comparator 49a-13 as signal Son2 to control IC 47, control IC 47 can determine whether voltage Vds21 is equal to or greater than a predetermined value (i.e., whether turning on of switching element 22 has been completed). The circuits of Figures 12 and 13 may also be applied to drain potential detection circuit 59a.

Furthermore, in a modified example of Example 2, the drain potential detection circuit 49a can determine that turn-on of the switching element 22 is complete when the rate of increase of the voltage Vds21 drops to a predetermined value or less (i.e., when the voltage Vds21 stabilizes). Furthermore, the drain potential detection circuit 59a can determine that turn-on of the switching element 21 is complete when the rate of increase of the voltage Vds22 drops to a predetermined value or less (i.e., when the voltage Vds22 stabilizes).

The switching circuit 20a3 of Example 3 shown in FIG. 14 determines whether a forward current is flowing through the diodes 23 and 24 using a method different from that of the switching circuit 20a of Example 1. That is, in Example 1, the control device 30 determines the direction of the current Iout1 flowing through the output wiring 16a and transmits the determination result as a signal CP to the control ICs 47 and 57. In contrast, in Example 3, the switching circuit 20 includes current detection circuits 27s and 28s. The current detection circuit 27s detects the current flowing through the wiring 27 connecting the parallel circuit of the switching element 21 and the diode 23 to the high-potential wiring 12, and outputs a signal CP1 indicating the direction of that current. That is, the current detection circuit 27s detects the current flowing through the parallel circuit of the switching element 21 and the diode 23, and outputs a signal CP1 indicating the direction of that current. The signal CP1 is transmitted to the control IC 57. Therefore, in step S54, the control IC 57 can determine whether a forward current is flowing through the diode 23 based on the signal CP1. In this case, the control IC 57 determines YES in step S54 (i.e., executes step S56) if a forward current is flowing through the diode 23, and determines NO in step S54 if a forward current is not flowing through the diode 23. In addition, the current detection circuit 28s detects a current flowing through the wiring 28 connecting the parallel circuit of the switching element 22 and the diode 24 to the output wiring 16a, and outputs a signal CP2 indicating the direction of that current. That is, the current detection circuit 28s detects a current flowing through the parallel circuit of the switching element 22 and the diode 24, and outputs a signal CP2 indicating the direction of that current. The signal CP2 is transmitted to the control IC 47. Therefore, in step S4, the control IC 47 can determine whether a forward current is flowing through the diode 24 based on the signal CP2. In this case, the control IC 47 determines NO in step S4 (i.e., executes step S6) if a forward current is flowing through the diode 24, and determines NO and YES in step S4 if a forward current is not flowing through the diode 24.

Note that the determination of whether a forward current is flowing through diodes 23 and 24 may be performed using a method different from that used in Examples 1 and 3. For example, the current flowing through diodes 23 and 24 may be detected directly, or the determination may be made based on the current, voltage, etc. at other positions.

In Example 1, the output potential of the DC power supply 46 was fixed to a negative potential -VNG. In contrast, in Example 4 shown in FIG. 15, the switching circuit 20a4 of Example 4 allows the output potential V46 of the DC power supply 46 to be changed. The output potential V46 is changeable within a range between negative and positive potentials. That is, in Example 4, the gate-off potential applied to the gate G21 of the switching element 21 during period Tb in FIG. 8 is changeable within a range between negative and positive potentials. Also, in Example 4, the gate control circuit 25 includes a potential increase detection circuit 46a and a power supply potential correction circuit 46b.

As described above, during period Tb in FIG. 8, a momentary rise 86 in gate potential Vg21 occurs when switching element 22 is turned on. The potential rise detection circuit 46a detects the rise ΔV in gate potential Vg21 during period Tb. For example, if gate potential Vg21 changes during period Tb as shown in FIG. 16, the potential rise detection circuit 46a detects the difference between the maximum value of gate potential Vg21 and potential V46 as the rise ΔV. For example, potential rise detection circuit 46a may be a peak hold circuit as shown in FIG. 17. The peak hold circuit includes diode 46a-1, operational amplifier 46a-2, diode 46a-3, resistor 46a-4, operational amplifier 46a-5, capacitor 46a-6, and switch 46a-7. The gate potential Vg21 is input to the positive terminal of operational amplifier 46a-2. The anode of the diode 46a-1 is connected to the negative terminal of the operational amplifier 46a-2. The cathode of the diode 46a-1 is connected to the output terminal of the operational amplifier 46a-2. The anode of the diode 46a-3 is connected to the output terminal of the operational amplifier 46a-2. The cathode of the diode 46a-3 is connected to the positive terminal of the operational amplifier 46a-5. One end of the resistor 46a-4 is connected to the negative terminal of the operational amplifier 46a-2. The other end of the resistor 46a-4 is connected to the negative terminal and output terminal of the operational amplifier 46a-5. The capacitor 46a-6 is connected between the positive terminal of the operational amplifier 46a-5 and a potential V46 (i.e., the negative pole of the DC power supply 56). The switch 46a-7 is connected between the positive terminal of the operational amplifier 46a-5 and the potential V46. The switch 46a-7 is controlled by the control IC 47, etc. The peak hold circuit monitors the gate potential Vg21 and outputs the difference between its maximum value and the potential V46 as the increase amount ΔV. The output value of the peak hold circuit can be reset by turning on switch 46a-7. After the end of period Tb and before the next period Tb arrives, control IC 47 turns on switch 46a-7 to reset the output value of the peak hold circuit. Therefore, the peak hold circuit detects the increase amount ΔV for each period Tb. The output value of the peak hold circuit (i.e., the increase amount ΔV) is input to power supply potential correction circuit 46b.

The power supply potential correction circuit 46b receives the increase ΔV from the potential increase detection circuit 46a. The power supply potential correction circuit 46b also receives the temperature T21 of the switching element 21 from a temperature sensor (not shown) built into the switching element 21. The power supply potential correction circuit 46b calculates an appropriate gate-off potential Voff for the period Tb based on the increase ΔV and the temperature T21, and controls the DC power supply 46 so that the calculated gate-off potential Voff is output. The operation of the power supply potential correction circuit 46b is described in detail below. The power supply potential correction circuit 46b calculates a predicted value ΔVp of the increase ΔV of the gate potential Vg21 for the next period Tb based on the increase ΔV for the previous period Tb. The predicted value ΔVp may be the same as the increase ΔV for the previous period Tb, the average value of the increase ΔV for the past several periods Tb, or a value calculated using another algorithm. The power supply potential correction circuit 46b also stores a temperature characteristic C1 of the gate threshold Vgth of the switching element 21, as shown in FIG. 18 . As shown in FIG. 18 , the higher the temperature T21 of the switching element, the lower the gate threshold Vgth. After calculating a predicted value ΔVp of the increase amount ΔV of the gate potential Vg21, the power supply potential correction circuit 46b subtracts the predicted value ΔVp from the temperature characteristic C1 shown in FIG. 18 to calculate graph C2. Next, the power supply potential correction circuit 46b calculates an optimal gate-off potential Voff based on the temperature T21 and graph C2. When calculating the gate-off potential Voff in this manner, the higher the predicted value ΔVp, the lower the gate-off potential Voff, and the higher the temperature T21, the lower the gate-off potential Voff. After calculating the gate-off potential Voff, the power supply potential correction circuit 46b adjusts the output potential V46 of the DC power supply 46 to match the gate-off potential Voff. Therefore, during the next period Tb, the gate potential Vg21 is controlled to the gate-off potential Voff. As shown in graph C2 of FIG. 18, the gate-off potential Voff can be either a negative or positive potential. When the gate potential Vg21 during period Tb is controlled to the gate-off potential Voff in this manner, even if the gate potential Vg21 increases by the same amount as the predicted value ΔVp, the gate potential Vg21 does not exceed the gate threshold Vgth. This prevents erroneous firing of the switching element 21. Furthermore, by controlling the gate potential Vg21 in this manner, the negative potential applied to the gate G21 can be minimized, thereby reducing stress on the switching element 21. The gate-off potential Voff may be calculated with a predetermined margin relative to graph C2.

Furthermore, in the switching circuit 20a4 of Example 4, the gate control circuit 26 has a potential rise detection circuit 56a and a power supply potential correction circuit 56b. The potential rise detection circuit 56a and the power supply potential correction circuit 56b operate in substantially the same manner as the potential rise detection circuit 46a and the power supply potential correction circuit 46b. The potential rise detection circuit 56a and the power supply potential correction circuit 56b optimize the output potential V56 of the DC power supply 56 (i.e., the gate potential Vg22 during the period Ta).

In Example 4, the potential V46 was adjusted based on both the predicted value ΔVp and the temperature T21. However, in a modified example of Example 4, the potential V46 may be adjusted based on only one of the predicted value ΔVp and the temperature T21.

As shown in FIG. 19, in the switching circuit 20a5 of Example 5, the output potential V46 of the DC power supply 46 and the output potential V56 of the DC power supply 56 are variable. Unlike Example 4, Example 5 outputs either 0V or a negative potential -VNG as the output potential V46, and either 0V or a negative potential -VNG as the output potential V56. The output potential V46 is controlled by the control IC 47, and the output potential V56 is controlled by the control IC 57. In Example 5, at timing t11 in FIG. 8, the control IC 47 turns on the gate-off switch 41. Thereafter, when the gate potential Vg21 drops to 0V, the control IC 47 turns on the gate-off switch 42 and turns off the gate-off switch 41, with the output potential V46 set to 0V. Then, at timing t12, the control IC 47 sets the output potential V46 to the negative potential -VNG, thereby lowering the gate potential Vg21 to the negative potential -VNG. Then, at timing t13, the control IC 47 sets the output potential V46 to 0V, thereby raising the gate potential Vg21 to 0V. In this way, in Example 5, the control IC 47 changes the output potential V46 of the DC power supply 46 to change the gate potential Vg21 between 0V and the negative potential -VNG. Similarly to the control IC 47, the control IC 57 also changes the output potential V56 of the DC power supply 56 to change the gate potential Vg22 between 0V and the negative potential -VNG.

Figure 20 shows a modified example of Example 5. In Figure 20, a potential conversion circuit 46x is provided instead of the DC power supply 46. The potential conversion circuit 46x includes a buffer circuit 46x-1, a capacitor 46x-2, and a diode 46x-3. The anode of the diode 46x-3 is connected to the gate-off switch 42, and the cathode of the diode 46x-3 is connected to the source wiring 48. The output terminal of the buffer circuit 46x-1 is connected to the anode of the diode 46x-3 via the capacitor 46x-2. The output potential of the buffer circuit 46x-1 is controlled by the control IC 47 and is varied between negative and positive potentials. When the gate-off switch 42 is on, if the output potential of the buffer circuit 46x-1 is controlled to a negative potential, the gate potential Vg21 becomes negative, and if the output potential of the buffer circuit 46x-1 is controlled to a positive potential, the gate potential Vg21 becomes a positive potential lower than the gate threshold (i.e., the forward voltage of the diode 46x-3). Also, in FIG. 20, a potential conversion circuit 56x is provided instead of the DC power supply 56. The potential conversion circuit 56x includes a buffer circuit 56x-1, a capacitor 56x-2, and a diode 56x-3. The potential conversion circuit 56x operates in the same manner as the potential conversion circuit 46x.

Note that multiple combinations of the above-described Examples 1 to 5 or their variations may be used.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of those objectives itself has technical utility.

12: High-potential wiring, 14: Low-potential wiring, 16: Output wiring, 20: Switching circuit, 21: Switching element, 22: Switching element, 23: Diode, 24: Diode, 25: Gate control circuit, 26: Gate control circuit

Claims (6)

A switching circuit (20a) comprising:
A high potential wiring (12),
An output wiring (16a);
A low potential wiring (14);
a first switching element (21) having a high potential main terminal connected to the high potential wiring, a low potential main terminal connected to the output wiring, and a gate;
a second switching element (22) having a high potential main terminal connected to the output wiring, a low potential main terminal connected to the low potential wiring, and a gate;
a first diode (23) having a cathode connected to the high potential main terminal of the first switching element and an anode connected to the low potential main terminal of the first switching element;
a second diode (24) having a cathode connected to the high potential main terminal of the second switching element and an anode connected to the low potential main terminal of the second switching element;
a target gate control circuit (25) that, when one of the first switching element and the second switching element is a target switching element and the other is an opposing switching element, changes the potential of the gate of the target switching element between a gate-on potential and a gate-off potential;
an opposing gate control circuit (26) that changes the potential of the gate of the opposing switching element between a gate-on potential (VCC) and a gate-off potential;
and
the target gate control circuit and the opposing gate control circuit control the potential of the gate of the target switching element and the potential of the gate of the opposing switching element so that the target switching element and the opposing switching element are alternately turned on;
the target gate control circuit is capable of applying, as the gate-off potential, a first gate-off potential that is equal to or higher than the potential of the low-potential main terminal of the target switching element, and a second gate-off potential (-VNG) that is lower than the potential of the low-potential main terminal of the target switching element, to the gate of the target switching element;
one of the first diode and the second diode that is connected in parallel to the target switching element is a target diode,
one of the first diode and the second diode that is connected in parallel to the opposing switching element is an opposing diode,
the target gate control circuit applies the first gate-off potential to the gate of the target switching element at a first timing (t5) when the opposing switching element is turned on in a state where a forward current is flowing through the opposing diode, and applies the second gate-off potential to the gate of the target switching element at a second timing (Tb) when the opposing switching element is turned on in a state where a forward current is not flowing through the opposing diode;
the target gate control circuit determines whether or not a forward current is flowing through the opposing diode based on a direction of a current flowing through a parallel circuit of the opposing switching element and the opposing diode;
Switching circuit. A switching circuit (20a) comprising:
A high potential wiring (12),
An output wiring (16a);
A low potential wiring (14);
a first switching element (21) having a high potential main terminal connected to the high potential wiring, a low potential main terminal connected to the output wiring, and a gate;
a second switching element (22) having a high potential main terminal connected to the output wiring, a low potential main terminal connected to the low potential wiring, and a gate;
a first diode (23) having a cathode connected to the high potential main terminal of the first switching element and an anode connected to the low potential main terminal of the first switching element;
a second diode (24) having a cathode connected to the high potential main terminal of the second switching element and an anode connected to the low potential main terminal of the second switching element;
a target gate control circuit (25) that, when one of the first switching element and the second switching element is a target switching element and the other is an opposing switching element, changes the potential of the gate of the target switching element between a gate-on potential and a gate-off potential;
an opposing gate control circuit (26) that changes the potential of the gate of the opposing switching element between a gate-on potential (VCC) and a gate-off potential;
and
the target gate control circuit and the opposing gate control circuit control the potential of the gate of the target switching element and the potential of the gate of the opposing switching element so that the target switching element and the opposing switching element are alternately turned on;
the target gate control circuit is capable of applying, as the gate-off potential, a first gate-off potential that is equal to or higher than the potential of the low-potential main terminal of the target switching element, and a second gate-off potential (-VNG) that is lower than the potential of the low-potential main terminal of the target switching element, to the gate of the target switching element;
one of the first diode and the second diode that is connected in parallel to the target switching element is a target diode,
one of the first diode and the second diode that is connected in parallel to the opposing switching element is an opposing diode,
the target gate control circuit applies the first gate-off potential to the gate of the target switching element at a first timing (t5) when the opposing switching element is turned on in a state where a forward current is flowing through the opposing diode, and applies the second gate-off potential to the gate of the target switching element at a second timing (Tb) when the opposing switching element is turned on in a state where a forward current is not flowing through the opposing diode;
an opposing command signal (SG2) including a turn-on command and a turn-off command for the opposing switching element is input to the target gate control circuit and the opposing gate control circuit;
the opposing gate control circuit controls the potential of the gate of the opposing switching element based on the opposing command signal;
when the target gate control circuit receives the turn-on command while a forward current is flowing through the opposing diode, it reduces the potential of the gate of the target switching element from the first gate-off potential to the second gate-off potential, and thereafter maintains the potential of the gate of the target switching element at the second gate-off potential until turn-on of the opposing switching element is completed;
Switching circuit. 3. The switching circuit according to claim 2 , wherein the target gate control circuit determines whether or not the turn-on of the opposing switching element has been completed based on the potential of the gate of the opposing switching element. 3. The switching circuit according to claim 2, wherein the target gate control circuit determines whether or not the turn-on of the opposing switching element has been completed based on a voltage between the high potential main terminal and the low potential main terminal of the target switching element . A switching circuit (20a) comprising:
A high potential wiring (12),
An output wiring (16a);
A low potential wiring (14);
a first switching element (21) having a high potential main terminal connected to the high potential wiring, a low potential main terminal connected to the output wiring, and a gate;
a second switching element (22) having a high potential main terminal connected to the output wiring, a low potential main terminal connected to the low potential wiring, and a gate;
a first diode (23) having a cathode connected to the high potential main terminal of the first switching element and an anode connected to the low potential main terminal of the first switching element;
a second diode (24) having a cathode connected to the high potential main terminal of the second switching element and an anode connected to the low potential main terminal of the second switching element;
a target gate control circuit (25) that, when one of the first switching element and the second switching element is a target switching element and the other is an opposing switching element, changes the potential of the gate of the target switching element between a gate-on potential and a gate-off potential;
an opposing gate control circuit (26) that changes the potential of the gate of the opposing switching element between a gate-on potential (VCC) and a gate-off potential;
and
the target gate control circuit and the opposing gate control circuit control the potential of the gate of the target switching element and the potential of the gate of the opposing switching element so that the target switching element and the opposing switching element are alternately turned on;
the target gate control circuit is capable of applying, as the gate-off potential, a first gate-off potential that is equal to or higher than the potential of the low-potential main terminal of the target switching element, and a second gate-off potential (-VNG) that is lower than the potential of the low-potential main terminal of the target switching element, to the gate of the target switching element;
one of the first diode and the second diode that is connected in parallel to the target switching element is a target diode,
one of the first diode and the second diode that is connected in parallel to the opposing switching element is an opposing diode,
the target gate control circuit applies the first gate-off potential to the gate of the target switching element at a first timing (t5) when the opposing switching element is turned on in a state where a forward current is flowing through the opposing diode, and applies the second gate-off potential to the gate of the target switching element at a second timing (Tb) when the opposing switching element is turned on in a state where a forward current is not flowing through the opposing diode;
The target gate control circuit is
an increase amount detection circuit (46a) that detects an increase amount of the potential of the gate of the target switching element at the second timing;
an increase amount-second gate-off potential correction circuit (46b) that lowers the second gate-off potential as the increase amount detected by the increase amount detection circuit increases;
having
Switching circuit. The increase amount detection circuit
a peak value hold circuit that holds a peak value of the potential of the gate of the target switching element;
a reset circuit (46b-7) that resets the peak value after the peak value is held and before the next second timing arrives;
6. The switching circuit of claim 5 , wherein: