JP7717265B2 - Plasma processing system and method for manufacturing trained model - Google Patents

Description

The present disclosure relates to a plasma processing system including a plasma processing apparatus that generates plasma using an RF power source.

Plasma processing equipment that generates plasma using an RF (Radio Frequency) power source has been used in semiconductor manufacturing equipment such as RF plasma thin-film manufacturing equipment and RF plasma processing equipment. A typical example of a conventional plasma processing equipment is a parallel-plate reactive ion etching equipment that generates plasma using an RF power source that produces 13.56 MHz alternating current.

Furthermore, in conventional plasma processing equipment, the in-plane potential distribution of the substrate to be manufactured (hereinafter abbreviated as "substrate in-plane potential distribution") tends to be complex. Because the substrate in-plane potential distribution significantly affects manufacturing conditions such as etching conditions, it was necessary to accurately recognize it. One example of technology for measuring the substrate in-plane potential distribution is the process monitoring device disclosed in Patent Document 1.

Special table 2019-508888 publication

However, conventional process monitoring devices use substrates specifically for monitoring, rather than the actual substrates to be manufactured. As a result, while conventional process monitoring devices are suitable for detecting abnormalities in the potential distribution within the substrate, they are not suitable for optimizing manufacturing conditions such as etching conditions.

Therefore, even if data analysis processing was performed using conventional process monitoring devices, there was a problem in that it was not possible to recognize the optimal manufacturing conditions for actual substrates so that the desired in-plane potential distribution of the substrate could be obtained during the manufacturing of the actual substrates.

The present disclosure aims to solve the above-mentioned problems and provide a plasma processing system that can accurately recognize the optimal manufacturing conditions for actual use substrates so that the desired in-plane distribution of negative potential can be obtained when manufacturing actual use substrates using a plasma processing apparatus.

The plasma processing system according to the present disclosure is a plasma processing system having a plasma processing apparatus that generates plasma within a chamber and a data analysis apparatus, wherein the plasma processing apparatus comprises: a lower electrode disposed within the chamber and connected to an AC power supply; an upper electrode disposed within the chamber opposite the lower electrode and connected to a reference potential; a practical use substrate that is disposed on the lower electrode side of the upper electrode or the lower electrode; and a plurality of potential measurement sensors disposed corresponding to a plurality of locations on the formation surface of the practical use substrate, each of which measures the negative potential of a corresponding location on the practical use substrate. The practical use substrate is a substrate to be manufactured, and measured potential data indicating a plurality of measured potentials measured using the plurality of potential measurement sensors is provided to the data analysis apparatus. The data analysis apparatus further comprises an in-plane potential distribution data creation unit that obtains substrate-corresponding in-plane potential distribution data indicating the in-plane distribution of negative potential within the practical use substrate based on the measured potential data, and a data analysis unit that obtains correlation data indicating the correlation between analysis data reflecting the substrate-corresponding in-plane potential distribution data and manufacturing content data indicating the manufacturing content for the practical use substrate at the time the measured potential data was obtained.

The plasma processing apparatus in the plasma processing system disclosed herein has multiple potential measurement sensors provided at multiple locations on the formation surface of the actual use substrate, which is the substrate to be manufactured. Therefore, the measured potential data indicating multiple measured potentials measured using the multiple potential measurement sensors can accurately identify the in-surface distribution of negative potential corresponding to the actual use substrate.

The data analysis device in the plasma processing system disclosed herein obtains substrate-corresponding in-plane potential distribution data from the in-plane potential distribution data creation unit based on measured potential data, and then obtains correlation data from the data analysis unit that indicates the correlation between the analysis data reflecting the substrate-corresponding in-plane potential distribution data and the manufacturing content data.

Therefore, the plasma processing system disclosed herein can recognize the optimal manufacturing conditions for a substrate for actual use by making estimates using correlation data so that the desired in-plane distribution of negative potential is obtained when manufacturing the substrate for actual use.

The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is an explanatory diagram schematically illustrating a cross-sectional structure of a main part of a plasma processing apparatus included in a plasma processing system according to a first embodiment of the present disclosure. 1 is an explanatory diagram schematically illustrating the overall configuration of a plasma processing system; 1 is an explanatory diagram illustrating a schematic configuration of a learning model creation device in a plasma processing system according to a first embodiment. 1 is an explanatory diagram schematically illustrating a configuration of a manufacturing content inference device in a plasma processing system according to a first embodiment; FIG. 2 is a block diagram showing the configuration of a processing circuit corresponding to the components in the learning model creation device and manufacturing content inference device of the first embodiment. FIG. 10 is a block diagram showing another example of the configuration of the processing circuit. 10 is an explanatory diagram schematically illustrating a cross-sectional structure of a main part of a plasma processing apparatus included in a plasma processing system according to a second embodiment. FIG. FIG. 10 is a perspective view showing the overall configuration of a cathode electrode in a plasma processing apparatus according to a second embodiment. FIG. 11 is a perspective view showing the overall configuration of a sensor-embedded substrate in a plasma processing apparatus according to a third embodiment. 10 is an explanatory diagram schematically illustrating a cross-sectional structure of the sensor-embedded substrate and its periphery shown in FIG. 9 . FIG. 10 is a perspective view showing the overall configuration of a Vdc sensor substrate in a plasma processing apparatus according to a fourth embodiment. 12 is an explanatory diagram schematically showing a cross-sectional structure of the Vdc sensor substrate and its periphery shown in FIG. 11. FIG. 13 is an explanatory diagram schematically showing the arrangement structure of Vdc sensors on a Vdc sensor substrate according to a fifth embodiment. FIG. FIG. 13 is a circuit diagram showing a circuit configuration of a Vdc sensor in a Vdc sensor substrate according to a sixth embodiment. An explanatory diagram schematically showing the configuration of a learning model creation device of embodiment 7. FIG. 13 is an explanatory diagram schematically showing the planar structure of a wafer for embodiment 8. FIG. 1 is an explanatory diagram schematically illustrating a cross-sectional structure of a plasma processing apparatus according to a basic technique. 10 is a graph showing the DC bias of the plasma processing apparatus of the basic technology. FIG. 1 is a simplified explanatory diagram showing an etching phenomenon that occurs in an ion sheath region of a plasma processing apparatus according to the basic technology. FIG. 1 is an explanatory diagram (part 1) showing the influence of a DC bias generated in a plasma processing apparatus of the basic technology on etching characteristics. FIG. 10 is an explanatory diagram (part 2) showing the influence of a DC bias generated in a plasma processing apparatus of the basic technology on etching characteristics. FIG. 1 is an explanatory diagram (part 1) showing the influence of a DC bias generated in a plasma processing apparatus of the basic technology on film formation characteristics. FIG. 10 is an explanatory diagram (part 2) showing the influence of a DC bias generated in a plasma processing apparatus of the basic technology on film formation characteristics. 10 is an explanatory diagram showing that the in-plane distribution of the generated negative offset potential increases in the plasma processing apparatus of the basic technology. FIG. 17 is an explanatory diagram schematically illustrating a transport system for a substrate to be etched associated with the cathode electrode shown in FIG. 16. FIG.

<Basic technology>
An example of a plasma processing apparatus that generates plasma using an RF power supply is a parallel plate type reactive ion etching apparatus (hereinafter abbreviated as "RIE etching apparatus") that generates plasma using an RF power supply that serves as a high frequency AC power supply of 13.56 MHz. The principle of the RIE etching apparatus will be described below.

Figure 17 is an explanatory diagram showing a schematic cross-sectional structure of a plasma processing apparatus 200 of the basic technology. The plasma processing apparatus 200 shown in Figure 17 is an RIE etching apparatus that generates plasma in an etching chamber 1 and performs etching processing.

Note that the basic structure of the plasma processing apparatus 200 shown in Figure 17 is common to most of the basic structures of the plasma processing apparatuses 101 to 104 of embodiments 1 to 4 described below.

The etching chamber 1 has a chamber inner housing 1B as its main component, within which an anode electrode 2 serving as an upper electrode is provided above, and a cathode electrode 3 serving as a lower electrode is provided below. A portion of the anode electrode 2 penetrates the top surface of the chamber inner housing 1B and is provided outside the chamber inner housing 1B, and a portion of the cathode electrode 3 penetrates the bottom surface of the chamber inner housing 1B and is provided outside the chamber inner housing 1B.

An RF power supply 12 is connected to the cathode electrode 3 via a variable capacitor 13, and the negative offset potential Vdc, which is the potential of the cathode electrode 3, is detected by a Vdc measuring voltmeter 15. The RF power supply 12 is also connected to a ground potential 16. The variable capacitor 13 is provided to match the impedance required for RF discharge within the etching chamber 1 with the impedance of the RF power supply 12.

A gas exhaust hole 4 is provided on the bottom surface of the chamber inner housing 1B, below and outside the periphery of the cathode electrode 3. The substrate to be etched 10, which will be the substrate to be actually used, is placed on the cathode electrode 3. The etching process is carried out above the substrate to be etched 10.

The anode electrode 2 is connected to a ground potential 16, which serves as a reference potential. The anode electrode 2 also serves as a shower head SH for introducing etching gas. The shower head SH for introducing etching gas has multiple gas supply holes that penetrate the anode electrode 2.

Atmospheric air is first evacuated from the etching chamber 1 through the gas exhaust holes 4 by a vacuum pump (not shown) until a high vacuum is created. Then, etching gas is introduced into the etching chamber 1 through multiple gas supply holes that penetrate the anode electrode 2, which also serves as a shower head SH for introducing etching gas.

In this state, a 13.56 MHz RF voltage is applied between the anode electrode 2 and the cathode electrode 3 from the RF power supply 12, converting most of the etching gas into plasma. In other words, most of the etching gas in the etching chamber 1 dissociates into plasma.

As shown in Figure 17, the spatial region within the etching chamber 1 is divided into a plasma region 5 and an ion sheath region 6. In the plasma region 5, which occupies the majority of the etching chamber 1, the etching gas is occupied by cations 7 dissociated into plasma by RF discharge from the RF power supply 12, activated radicals 8 similarly dissociated by RF discharge, and gas molecules 9 that have not dissociated into plasma. Here, the activated radicals 8 and gas molecules 9 have a neutral charge.

The ion sheath region 6 exists below the plasma region 5 and is a region that extends over the surface of the substrate 10 to be etched. The reason for the formation of the ion sheath region 6 is that when a 13.56 MHz RF power supply 12 is applied to the etching gas, the dissociated cations 7 have a heavy mass relative to their charge and are therefore unable to follow the 13.5 MHz high frequency, causing the cations 7 present in the plasma region 5 to remain in place.

On the other hand, the electrons 11 emitted from the dissociated cations 7 have a light mass compared to their charge, and so begin to move back and forth between the anode electrode 2 and the cathode electrode 3 in response to the 13.56 MHz RF current. However, an RF power supply 12 is connected to the cathode electrode 3, and a variable capacitor 13 for impedance matching is sandwiched between the cathode electrode 3 and the RF power supply 12. For this reason, the electrons 11 remain in the variable capacitor 13, and as a result, the cathode electrode 3 and the substrate 10 to be etched become negatively charged.

On the other hand, the plasma region 5 lacks electrons 11 for the reasons described above and becomes positively charged. When considering the offset potential V1 within the etching chamber 1, the negative potential of the offset potential V1 resulting from the negative charge carried by the cathode electrode 3 and the substrate 10 to be etched is called the negative offset potential Vdc. The negative offset potential Vdc greatly influences the etching conditions, as will be described later.

A Vdc measuring voltmeter 15 is inserted between the cathode electrode 3 and the variable capacitor 13 for impedance matching, and the negative offset potential Vdc can be measured using the Vdc measuring voltmeter 15. Similarly, the positive potential of the offset potential V1 resulting from the positive charge carried by the plasma region 5 is called the positive offset potential Vpp, and like the negative offset potential Vdc, it largely controls the etching conditions.

For this reason, a blocking capacitor 17 that blocks the RF current discharged from the RF power supply 12 and a Vpp measurement voltmeter 18 that serves as an upper electrode voltmeter are inserted between the etching chamber 1 and the anode electrode 2. Specifically, the blocking capacitor 17 is inserted between the top surface of the chamber inner housing 1B and the Vpp measurement voltmeter 18, and the Vpp measurement voltmeter 18 is connected to the anode electrode 2, which is set to ground potential 16.

Then, the upper electrode potential, which is the potential of the anode electrode 2 measured by the Vpp measurement voltmeter 18, which is an upper electrode voltmeter, is measured. This upper electrode potential becomes the positive offset potential Vpp. In this way, the Vpp measurement voltmeter 18 measures the upper electrode potential as the positive offset potential Vpp. Here, the differential voltage between the positive offset potential Vpp and the negative offset potential Vdc is called the DC bias BV.

Figure 18 is a graph showing details of the DC bias BV shown on the right side of Figure 17. In this figure, the horizontal Y axis indicates the height direction of the plasma processing apparatus 200 shown in Figure 17, and the vertical axis indicates the voltage value based on 0 V applied from the ground potential 16.

As shown in the figure, the AC waveform AW, which is the RF output of the RF power supply 12, shifts to the negative side from the plasma region 5 to the ion sheath region 6. Therefore, the offset potential V1, which is the intermediate potential between the maximum and minimum values of the AC waveform AW, shifts to the positive side, higher than 0 V, in the plasma region 5, and shifts to the negative side in the ion sheath region 6 where the substrate to be etched 10 and the cathode electrode 3 are present.

The positively shifted offset potential V1 in the plasma region 5 becomes the positive offset potential Vpp, and the negatively shifted offset potential V1 at the location where the etched substrate 10 and the cathode electrode 3 are present becomes the negative offset potential Vdc.

The DC bias BV is the difference value obtained by subtracting the negative offset potential Vdc from the positive offset potential Vpp described above. Hereinafter, an increase in this difference value will be referred to as a higher DC bias BV, and a decrease in this difference value will be referred to as a lower DC bias BV.

Figure 19 is a simplified explanatory diagram showing the etching phenomenon that occurs within the ion sheath region 6. As shown in the figure, electrons 11 remain inside the substrate 10 to be etched, carrying a negative charge. The material 21 to be etched, which is covered with resist 20 except for the area to be etched, attracts positive ions 7 dissociated by the plasma due to the Coulomb force generated by the negatively charged substrate 10 to be etched.

At this time, the cations 7 are not only attracted to the material 21 to be etched, but also collide with activated radicals 8 and neutral gas molecules 9 that have not been dissociated by the plasma during their movement, causing them to descend toward the material 21 to be etched. The neutral gas molecules 9 do not chemically react with the material 21 to be etched, but they do chip away at the material 21 to be etched through a physical sputtering action. Furthermore, the cations 7 dissociated by the plasma are concentrated and descend toward the material 21 to be etched due to the Coulomb force with the substrate 10 to be etched, where they undergo a chemical reaction and evaporate.

Neutral activated radicals 8 dissociated by the plasma also collide with cations 7 and descend toward the material 21 to be etched, similarly undergoing a chemical reaction and evaporating. In this way, the etching phenomenon progresses within the ion sheath region 6, and it can be seen that the DC bias BV, which is the differential voltage between the positive offset potential Vpp and the negative offset potential Vdc, has a significant effect on the etching characteristics.

Figures 20 and 21 are explanatory diagrams showing the effect of DC bias BV on etching characteristics. Figure 20 shows a schematic cross-sectional structure when etching is performed with a relatively low DC bias BV, and Figure 21 shows a schematic cross-sectional structure when etching is performed with a relatively high DC bias BV.

As shown in Figures 20 and 21, a substrate 10 to be etched is placed on a cathode electrode 3, a material 21 to be etched is deposited on the substrate 10 to be etched, and a patterned resist 20 is provided on the material 21 to be etched.

The basic technology RIE etching apparatus shown in Figure 17 creates a plasma state inside the etching chamber 1 in the state shown in Figures 20 and 21, and performs an etching process on the material to be etched 21 using resist 20 as a mask.

As shown in Figure 20, when the DC bias BV is relatively low, the positive ions 7, activated radicals 8, and neutral gas molecules 9 do not fall vertically onto the material 21 to be etched, and the etching reaction direction DE proceeds isotropically. Furthermore, the etching rate of the material 21 to be etched also slows.

On the other hand, as shown in Figure 21, when the DC bias BV is relatively high, the cations 7, activated radicals 8, and neutral gas molecules 9 fall vertically, the etching reaction direction DE proceeds anisotropically, and the cross-sectional shape of the material 21 to be etched becomes vertically anisotropic. Furthermore, the etching rate of the material 21 to be etched also increases.

Therefore, in the case of an RIE etching apparatus, it can be inferred that a relatively high DC bias BV allows for more accurate etching of the material 21 to be etched. In other words, in thin film processing equipment such as an RIE etching apparatus, it can be inferred that a relatively high DC bias BV allows for more accurate shape processing such as etching.

However, it is believed that there is an upper limit to the height of the DC bias BV. Increasing the DC bias BV increases the absolute value of the negative offset potential Vdc, which could damage the underlying material.

Furthermore, RF plasma thin-film manufacturing equipment, such as a parallel-plate plasma CVD (Chemical Vapor Deposition) equipment that generates plasma using a 13.56 MHz RF power supply 12, performs film formation processing using a principle similar to that of an RIE etching equipment. Hereinafter, parallel-plate plasma CVD equipment may be simply referred to as "plasma CVD equipment."

In a plasma CVD device, in the basic technology plasma processing device shown in Figure 17, the etching chamber 1 functions as a film formation chamber, and the substrate to be etched 10 is replaced with a thin film deposition substrate 22.

Figures 22 and 23 are explanatory diagrams showing the effect of the DC bias BV on the film formation characteristics. Figure 22 shows a schematic cross-sectional structure when the film formation process is performed with a relatively low DC bias BV, and Figure 23 shows a schematic cross-sectional structure when the film formation process is performed with a relatively high DC bias BV.

As shown in Figures 22 and 23, the thin film deposition substrate 22 to be manufactured is placed on the cathode electrode 3, and after a lower thin film 23 is formed on the thin film deposition substrate 22, an upper thin film 24 is formed on the lower thin film 23.

In other words, when in the state shown in Figures 22 and 23, the plasma CVD apparatus creates a plasma state inside the etching chamber 1, which functions as a film formation chamber, and performs a film formation process to form an upper thin film 24 on a lower thin film 23.

In other words, in the state shown in Figures 22 and 23, cations 7 and activated radicals 8 that have fallen toward the thin film deposition substrate 22 due to the DC bias BV undergo a chemical reaction above the thin film deposition substrate 22, resulting in the formation of an upper thin film 24 on the lower thin film 23.

On the other hand, as shown in Figures 20 and 21, an RIE etching apparatus performs etching by causing cations 7 and activated radicals 8 to fall toward the substrate 10 to be etched by a DC bias BV, which then chemically reacts with the material 21 to be etched and evaporates.

As shown in Figure 22, when the DC bias BV is relatively low, the cations 7, activated radicals 8, and neutral gas molecules 9 do not fall vertically onto the lower thin film 23, and the film formation reaction direction DF proceeds isotropically, resulting in good coverage of the upper thin film 24 with respect to the lower thin film 23.In addition, since the upper thin film 24 receives less physical impact from the cations 7, activated radicals 8, and neutral gas molecules 9 during film formation, the film quality of the upper thin film 24 is good.

On the other hand, as shown in Figure 23, when the DC bias BV is relatively high, the cations 7, activated radicals 8, and neutral gas molecules 9 fall vertically onto the lower thin film 23, and the film formation reaction direction DF proceeds vertically, resulting in poor coverage of the upper thin film 24 with respect to the lower thin film 23. In addition, the film quality of the upper thin film 24 deteriorates due to the large physical impacts received from the cations 7, activated radicals 8, and neutral gas molecules 9 during the formation of the upper thin film 24.

Therefore, in the case of a plasma CVD apparatus, it is assumed that the deposition process of the upper thin film 24 can be performed better when the DC bias BV is relatively low. However, it is thought that there is a lower limit to the DC bias BV.

In the case of sputtering equipment using RF plasma, which performs the sputtering process that plays an important role in thin film formation, the chemical reaction in plasma CVD is simply changed into a physical reaction, and as with dry etching and plasma CVD, the DC bias BV plays a major role in optimizing the film formation process conditions.

As such, it is clear that the DC bias BV is important during thin film deposition and shape processing. As mentioned above, the DC bias BV is the differential voltage between the positive offset potential Vpp and the negative offset potential Vdc.

Generally, the measured positive offset potential Vpp is several to several tens of volts, while the negative offset potential Vdc is several tens to several hundred volts. Both the positive offset potential Vpp and the negative offset potential Vdc are expected to have an in-plane distribution, but in principle, because there are no potential disturbance elements in the etching chamber 1, it can be expected that there will be only slight fluctuations in the in-plane distribution of the positive offset potential Vpp at the boundary between the plasma region 5 and the ion sheath region 6.

On the other hand, the in-plane distribution of the negative offset potential Vdc is expected to be relatively large. This is because, as shown in Figures 20 and 21, the system consisting of the cathode electrode 3, the substrate 10 to be etched, the material 21 to be etched, and the resist 20 has relatively large potential disturbance factors. This point will be explained in detail below.

Figure 24 is an explanatory diagram showing that the in-plane distribution of the negative offset potential Vdc becomes larger. Figure 24 shows the layered structure of the cathode electrode 3, the substrate 10 to be etched, and the material 21 to be etched after patterning the resist 20.

In fact, when an etching process is performed on the material to be etched 21 using the resist 20 as a mask for a structure such as that shown in Figure 24, the etching results are different between the central portion 22c of the substrate 10 to be etched and the edge portion 22e of the substrate.

For example, the etching rate for the material 21 to be etched on the central portion 22c of the substrate is relatively slow, and the etching shape reflects isotropic etching, while the etching rate for the material 21 to be etched on the edge portion 22e of the substrate is relatively fast, and the etching shape reflects vertical anisotropic etching.

This phenomenon is thought to occur because the electric field concentrates at the substrate edge 22e, causing an increase in the negative offset potential Vdc, which is the basis for estimating that the in-plane distribution of the negative offset potential Vdc affects the etching process. Note that an increase in the negative offset potential Vdc means that the absolute value of the negative level of the negative offset potential Vdc increases.

Similarly, the etching rate is relatively slow in the dense resist region R20t, resulting in an etching shape that is close to isotropy, while the etching rate is relatively fast in the sparse resist region R20s, resulting in a phenomenon where the etching shape is perpendicularly anisotropic. The dense resist region R20t is a region where the density of resist 20 formed on the material 21 to be etched is relatively high, while the sparse resist region R20s is a region where the density of resist 20 formed on the material 21 to be etched is relatively low. In other words, the dense resist region R20t is a region where a larger portion of the resist 20 is covered per unit area compared to the sparse resist region R20s.

The cause of the above phenomenon is known as the microloading effect, and several factors have been identified, with the following thought to be the major contributing factor: The substrate 10 to be etched is made of silicon, which has a dielectric constant of approximately 12.0, and the substrate 10 is coated with films of materials to be etched 21, each with a varying dielectric constant, which are then covered with a patterned resist 20 with a dielectric constant of approximately 3.0 to 4.0.

In the dense resist region R20t, the capacitance decreases locally, reducing the amount of negative charge remaining on the substrate 10 to be etched, resulting in a decrease in the negative offset potential Vdc. Conversely, in the sparse resist region R20s, the capacitance increases locally, increasing the amount of negative charge remaining on the substrate 10 to be etched, resulting in an increase in the negative offset potential Vdc. The reason why the microloading effect occurs can be explained by the phenomenon described above.

In addition to the causes mentioned above, variations in the negative offset potential Vdc occur near the substrate lift pins 29 attached to the cathode electrode 3 and used to transport the substrate 10 to be etched, resulting in frequent variations in the etching rate and etching shape. The reasons for this are explained in detail below.

25 is an explanatory diagram schematically showing a transport system for a substrate 10 to be etched associated with the cathode electrode 3. Generally, the substrate lift pins 29 for transporting the substrate 10 to be etched are made of an aluminum alloy with a surface covered with aluminum oxide (Al ₂ O ₃ ), similar to the cathode electrode 3. Therefore, in order to block the RF power supply 12 applied to the cathode electrode 3, an insulator 30 is sandwiched between the substrate lift pins 29 and the lift pin support shaft 31.

The lower part of the insulator 30 is supported by a lift pin support shaft 31, which is raised and lowered by a lift motor 32, which is driven by an AC power source 33. In this way, the AC power source 33, the lift motor 32, the lift pin support shaft 31, and the insulator 30 form a drive mechanism for the substrate lift pins 29. The substrate lift pins 29 can be raised and lowered by this drive mechanism.

When the substrate lifting pins 29 are raised, the substrate 10 to be etched is moved by a transport arm (not shown) into the space above the cathode electrode 3, where it is supported by the substrate lifting pins 29 above the cathode electrode 3. The substrate lifting pins 29 are then lowered, positioning the substrate 10 on the cathode electrode 3.

Therefore, it is easy to understand that the amount of electrons 11 residing in the cathode electrode 3 and the substrate lifting pin 29 differs, and this is a factor that causes fluctuations in the negative offset potential Vdc.

From the above explanation, it can be seen that fluctuations in the DC bias BV exist on the substrate 10 to be etched, and that optimizing this DC bias BV is necessary to optimize the etching conditions. It can also be seen that most of the factors that cause fluctuations in the DC bias BV are due to the complex in-plane distribution of the negative offset potential Vdc on the substrate 10 to be etched.

However, in the RIE etching apparatus, which is a parallel plate type dry etching apparatus based on the basic technology, as shown in Figure 17, the negative offset potential Vdc across the entire cathode electrode 3 is measured using a Vdc measurement voltmeter 15, and there is a problem in that it is not configured to measure the in-plane distribution of the negative offset potential Vdc on the substrate 10 to be etched.

In order to solve the above-mentioned problems, a technology has been proposed in the past, such as the technology disclosed in Patent Document 1, in which a dedicated process monitoring device including an etching substrate equipped with various sensors is provided to measure the in-plane distribution of the negative offset potential Vdc.

However, as mentioned above, conventional process monitoring devices use substrates specifically for monitoring, rather than the actual substrates to be manufactured. This limits the process monitoring device's ability to detect abnormalities in the potential distribution, and poses the problem of being unsuitable for optimizing manufacturing conditions, such as etching conditions, for actual substrates.

The embodiments described below disclose a plasma processing system and a method for manufacturing a trained model that aim to resolve the above-mentioned problems.

First Embodiment
1 is an explanatory diagram schematically illustrating a cross-sectional structure of a main part of a plasma processing apparatus 101 included in a plasma processing system 501 according to a first embodiment of the present disclosure. The plasma processing apparatus 101 shown in FIG. 1 is a parallel plate type RIE etching apparatus that generates plasma in an etching chamber 1 and performs etching processing.

(Plasma Processing System 501)
2 is an explanatory diagram schematically illustrating the configuration of a plasma processing system 500 according to embodiment 1. As shown in the figure, plasma processing system 500 includes, as main components, a plasma processing apparatus 101, a learning model creation device 70, and a manufacturing content inference device 80.

The plasma processing apparatus 101 outputs Vdc data D1 and Vpp voltage data D2 to the learning model creation device 70. The learning model creation device 70, which is a data analysis device, generates a learned model D5 based on the Vdc data D1, Vpp voltage data D2, and manufacturing content data D3 obtained from an external source, and provides it to the downstream manufacturing content inference device 80.

Based on the learned model D5, the manufacturing content inference device 80 obtains data indicating the manufacturing content for the actual substrate as inference data D7 so as to obtain the in-plane distribution of negative potential indicated by the desired in-plane distribution data D4.

The configurations and operations of the plasma processing device 101, learning model creation device 70, and manufacturing content inference device 80 will be described in detail later.

(Plasma Processing Apparatus 101)
The configuration of the plasma processing apparatus 101 of the first embodiment will be described below with reference to Fig. 1. Note that the basic configuration of the plasma processing apparatus 200 shown in Fig. 17, including an exhaust system such as a vacuum pump using gas exhaust holes 4, a power supply system such as an RF power supply 12 and a variable capacitor 13 for impedance matching, and a transport system for an actual substrate corresponding to the substrate to be etched 10, including substrate lift pins 29 and a lift motor 32, is omitted from Fig. 1. That is, like the plasma processing apparatus 200, the plasma processing apparatus 101 of the first embodiment also has a basic configuration including the exhaust system, supply system, and transport system described above.

"Substrate for actual use" refers to a "substrate to be manufactured," and is typically used during manufacturing. This disclosure is characterized by the use of "substrate for actual use" as a "substrate to be measured for multiple potentials." In other words, in this specification, "substrate for actual use" includes "substrate used during manufacturing" and "substrate to be measured for multiple potentials." Furthermore, "substrate to be manufactured" includes "wafers used before mass production" and "mass-produced wafers."

The etching chamber 1 has a chamber inner housing 1B as its main component, within which an anode electrode 2 serving as an upper electrode is provided above and a lower electrode is provided below. A portion of the anode electrode 2 penetrates the top surface of the chamber inner housing 1B and is provided outside the chamber inner housing 1B, and a portion of the lower electrode penetrates the bottom surface of the chamber inner housing 1B and is provided outside the chamber inner housing 1B.

In the plasma processing apparatus 101, similar to the cathode electrode 3 of the plasma processing apparatus 200 shown in Figure 17, an RF power supply 12, which is a high-frequency AC power supply, is applied to the lower electrode via a variable capacitor 13. In other words, the plasma processing apparatus 101 of embodiment 1 also has a lower electrode equivalent to the cathode electrode 3 of the plasma processing apparatus 200.

In this way, in the plasma processing apparatus 101, the anode electrode 2, which serves as the upper electrode, and the lower electrode are provided facing each other in the etching chamber 1, and the actual substrate (not shown) is placed on the lower electrode side of the anode electrode 2 and the lower electrode. In other words, the plasma processing apparatus 101 of embodiment 1 also has an actual substrate corresponding to the substrate to be etched 10 of the plasma processing apparatus 200. As described above, the actual substrate is the substrate to be manufactured.

Furthermore, a Vdc sensor assembly 190 is provided directly below the actual use substrate or within the actual use substrate. The Vdc sensor assembly 190 has multiple Vdc sensors s19.

Multiple Vdc sensors s19 are provided corresponding to multiple locations on the formation surface of the actual use substrate, each of which is provided to measure the potential at a corresponding location on the actual use substrate.

The multiple Vdc sensors s19 function as multiple potential measurement sensors for obtaining multiple measured potentials. Specifically, the potentials at the multiple Vdc sensors s19 can be measured using multiple voltmeters or the like electrically connected to the multiple Vdc sensors s19.

Examples of a configuration in which the main part of the Vdc sensor assembly 190 is located directly below the actual use substrate include the cathode electrode 3S of embodiment 2 or the Vdc sensor substrate 19 of embodiment 4, which will be described later.

On the other hand, a configuration in which multiple Vdc sensors s19 are provided within an actual use board can be considered, such as the sensor-embedded board 10S of embodiment 3 described below.

In other words, the Vdc sensor assembly 190 shown in Figure 1 is a component of the plasma processing apparatus 101, which includes the cathode electrode 3S of embodiment 2, the sensor-embedded substrate 10S of embodiment 3, and the Vdc sensor substrate 19 of embodiment 4, which will be described later.

The Vdc sensor assembly 190 is primarily used for creating a trained model. To measure the in-plane distribution of the negative offset potential Vdc on a substrate placed in the ion sheath region 6 of the etching chamber 1, multiple Vdc sensors s19 are provided corresponding to multiple locations on the formation surface of the substrate when viewed in a plan view.

In other words, the multiple Vdc sensors s19 in the Vdc sensor assembly 190 can comprehensively measure the in-plane distribution of the negative offset potential Vdc on the actual substrate.

The multiple measured potentials obtained from the Vdc sensor assembly 190 are obtained as Vdc sense data D11, which will be described later, and the Vdc sense data D11 becomes the measured potential data. Furthermore, position information of the actual use substrate corresponding to the multiple measured potentials is obtained as position information data D12, which will be described later. The position information data D12 becomes data that complements the Vdc sense data D11, which is the measured potential data. The combination of the Vdc sense data D11 and the position information data D12 becomes the Vdc data D1.

Each Vdc sensor s19 refers to a component that can measure the potential difference between the potential at a corresponding location on the actual substrate placed within the ion sheath region 6 and the ground potential, which serves as the reference potential, using a voltmeter. Note that the type of voltmeter is not important.

The anode electrode 2 is connected to a ground potential 16, which serves as a reference potential. The anode electrode 2 also serves as a shower head SH for introducing etching gas. The shower head SH for introducing etching gas has multiple gas supply holes (not shown) that penetrate the anode electrode 2 and supply etching gas into the etching chamber 1.

In addition, instead of the shower head SH for introducing etching gas, a gas supply hole may be provided other than the anode electrode 2, and modifications such as providing a gas supply hole on the side of the chamber inner housing 1B are possible.

The atmosphere inside the etching chamber 1 is first evacuated to a high vacuum state through the gas exhaust holes 4 by a vacuum pump (not shown). Etching gas is then introduced into the etching chamber 1 through the multiple gas supply holes mentioned above in the anode electrode 2, which also serves as the shower head SH for introducing etching gas. A 13.56 MHz RF voltage is applied from the RF power supply 12 between the anode electrode 2 and the lower electrode, converting most of the etching gas into plasma.

Like the plasma processing apparatus 200, the plasma processing apparatus 101 has a blocking capacitor 17 and a Vpp measurement voltmeter 18, and the Vpp measurement voltmeter 18 can measure the upper electrode potential obtained from the anode electrode 2 as a positive offset potential Vpp. Vpp voltage data D2 indicating the measured positive offset potential Vpp is output to the downstream learning model creation device 70. This Vpp voltage data D2 becomes the upper electrode measurement data.

In principle, since it is believed that there is little in-plane distribution at the boundary between the plasma region 5 and the ion sheath region 6, the positive offset potential Vpp is measured by the Vpp measurement voltmeter 18, as in the plasma processing apparatus 200 of the basic technology. In other words, the positive offset potential Vpp is measured by measuring the potential difference between the blocking capacitor 17 and the ground potential 16 in the circuit extending from the chamber inner housing 1B to the ground potential 16 via the blocking capacitor 17, using the Vpp measurement voltmeter 18.

On the other hand, the in-plane distribution of the negative potential on the actually used substrate is determined as multiple measured potentials obtained from multiple Vdc sensors s19 of the Vdc sensor assembly 190. In other words, the complex in-plane portion of the negative offset potential Vdc on the actually used substrate can be recognized from the multiple measured potentials.

The plasma processing apparatus 101, which is a main component of the plasma processing system 501 of embodiment 1, is configured in this manner. The Vdc data D1 includes Vdc sense data D11 indicating multiple measured potential data obtained from the Vdc sensor assembly 190 in the plasma processing apparatus 101, and position information data D12 indicating position information on the actual use substrate for the multiple measured potential data. This Vdc data D1 is output to the subsequent learning model creation device 70, as shown in Figure 2.

The upper electrode potential measured by the Vpp measurement voltmeter 18 in the plasma processing device 101 becomes the positive offset potential Vpp, and Vpp voltage data D2 indicating the positive offset potential Vpp is output to the subsequent learning model creation device 70 as upper electrode measurement data.

(Learning model creation device 70)
FIG. 3 is an explanatory diagram schematically illustrating the configuration of learning model creation device 70 in plasma processing system 500 according to the first embodiment.

As shown in Figure 2, the learning model creation device 70, which is a data analysis device, receives Vdc data D1 and Vpp voltage data D2 from the plasma processing device 101. It also receives manufacturing content data D3 from the outside. The manufacturing content data D3 is data that indicates the manufacturing content for the actual use substrate when the Vdc data D1 and Vpp voltage data D2 were obtained.

Incidentally, since the position information corresponding to multiple measured potential data is known in advance, the position information data D12 of the Vdc data D1 may be supplied to the learning model creation device 70 from an external source. On the other hand, the manufacturing details data D3 may be obtained from the plasma processing device 101.

As shown in Figure 3, the learning model creation device 70 includes as its main components a Vdc in-plane distribution creation unit 71, a DC bias in-plane distribution creation unit 72, a learning model creation unit 73, and a learning model recording unit 74.

The Vdc in-plane distribution creation unit 71, which is an in-plane potential distribution data creation unit, creates Vdc in-plane distribution data D10 that indicates the in-plane distribution of the negative offset potential Vdc on the actually used substrate based on the Vdc data D1. This Vdc in-plane distribution data D10 becomes substrate-corresponding in-plane potential distribution data that indicates the in-plane distribution of the negative potential on the actually used substrate.

As mentioned above, Vdc sense data D11 of Vdc data D1 is obtained from the Vdc sensor assembly 190 of the plasma processing apparatus 101. In addition, position information data D12 of Vdc data D1 is obtained from the plasma processing apparatus 101 or externally. Position information data D12 is data indicating the position of the formation surface on the actual substrate for each of the multiple measured potentials indicated by the Vdc sense data D11.

Therefore, the Vdc in-plane distribution creation unit 71 recognizes multiple measured potentials with recognized position information as multiple position-recognized measured potentials based on the Vdc data D1.The Vdc in-plane distribution creation unit 71 then generates Vdc in-plane distribution data D10, which serves as substrate-corresponding in-plane potential distribution data, based on the multiple position-recognized measured potentials.

In this way, the Vdc in-plane distribution creation unit 71 functions as an in-plane potential distribution data creation unit that derives Vdc in-plane distribution data D10 indicating the in-plane distribution of negative potential on an actually used substrate based on Vdc data D1 including Vdc sense data D11.

The DC bias in-plane distribution creation unit 72, which is a bias potential distribution creation unit, generates BV in-plane distribution data D20 that shows the in-plane distribution of the DC bias BV on the actual use substrate based on the Vdc in-plane distribution data D10 and the Vpp voltage data D2.

The bias potential, DC bias BV, can be calculated as the difference between the positive offset potential Vpp and the negative offset potential Vdc. Since the positive offset potential Vpp is a constant value, the BV in-plane distribution data D20, which indicates the in-plane distribution of the DC bias BV, reflects the Vdc in-plane distribution data D10. This BV in-plane distribution data D20 is the subject of analysis by the learning model creation unit 73.

In this way, the DC bias in-plane distribution creation unit 72 calculates multiple DC biases BV, which are the difference values between the upper electrode potential and multiple measured potentials, based on the Vpp voltage data D2, which is the upper electrode measurement data, and the Vdc in-plane distribution data D10, which is the substrate-corresponding in-plane potential distribution data, and obtains BV in-plane distribution data D20 indicating the multiple DC biases BV as analysis data. Here, the DC bias BV becomes the bias potential, and the BV in-plane distribution data D20 becomes the bias in-plane distribution data.

The learning model creation unit 73 receives the BV in-plane distribution data D20 and manufacturing details data D3 obtained from the DC bias in-plane distribution creation unit 72. In other words, the learning model creation unit 73, which is a related data creation unit, receives the BV in-plane distribution data D20, which is bias in-plane distribution data, as analysis data.

As described above, the manufacturing content data D3 indicates the manufacturing content set in the plasma processing apparatus 101 when the Vdc data D1 and the Vpp voltage data D2 were obtained from the plasma processing apparatus 101. The manufacturing content data D3 includes gas type data D31, gas flow rate data D32, gas pressure data D33, RF output data D34, and process data D35.

Gas type data D31 is data indicating the gas type used in the etching process. There is at least one gas type. Gas flow rate data D32 is data indicating the supply flow rate of at least one gas that satisfies the gas type indicated by gas type data D31. Gas pressure data D33 is data indicating the etching pressure within the etching chamber 1. RF output data D34 is data indicating the oscillation frequency of the RF power supply 12, the maximum rated output which is the input power, etc.

Process data D35 is data indicating the details of the etching process other than the data indicated by the above-mentioned data groups D31 to D34. Examples of data indicated by process data D35 include the temperature of the lower electrode, the inter-electrode distance between the anode electrode 2 and the lower electrode, the reflected wave output of the RF power supply 12, the degree of vacuum achieved in the etching chamber 1 before the introduction of the etching gas, and the exhaust valve opening degree at the gas exhaust port 4.

In this way, manufacturing content data D3, which includes data groups D31 to D35, indicates manufacturing content, including etching processing, for actual use substrates.

As explained in the Basic Technology section using Figures 20 to 24, the negative offset potential Vdc and the positive offset potential Vpp are important monitoring parameters in plasma processes, but it is practically impossible to set them arbitrarily.

In other words, the negative offset potential Vdc and positive offset potential Vpp are affected by the manufacturing details data D3. For example, lowering the etching pressure indicated by the gas pressure data D33 lengthens the mean free path of the electrons 11, and as a result, the negative offset potential Vdc tends to rise to the negative side. To achieve an appropriate in-plane distribution of the negative offset potential Vdc on an actually used substrate, it is necessary to adjust the gas flow rate indicated by the gas flow rate data D32 and the inter-electrode distance between the anode electrode 2 and the lower electrode indicated by the process data D35.

Also, changing the etching gas flow rate indicated by the gas flow rate data D32 changes the degree of plasma dissociation, and therefore the negative offset potential Vdc. Therefore, to achieve an appropriate in-plane distribution of the negative offset potential Vdc on the actual substrate, it is necessary to adjust the etching pressure indicated by the gas pressure data D33 and the electrode distance indicated by the process data D35. Note that while the absolute value of the positive offset potential Vpp varies depending on the various process parameters indicated by the manufacturing details data D3, in principle, the in-plane distribution is assumed to be approximately uniform.

The learning model creation unit 73 performs machine learning using the BV in-plane distribution data D20 as input data and the manufacturing content data D3 as training data, and creates a learned model D5 for estimating the manufacturing content of an actually used substrate corresponding to the BV in-plane distribution data D20.

In other words, the learning model creation unit 73, which is the related data creation unit, analyzes the relationship between the BV in-plane distribution data D20 and the manufacturing content data D3, and creates a learned model D5 as related data that shows the relationship between the BV in-plane distribution data D20 and the manufacturing content data D3.

The data analysis unit is composed of the DC bias in-plane distribution creation unit 72, which is the bias potential distribution creation unit mentioned above, the learning model creation unit 73, which is the related data creation unit, and the learning model recording unit 74 described below.

The data analysis unit uses the BV in-plane distribution data D20 reflecting the Vdc in-plane distribution data D10 as analysis data, analyzes the relationship with manufacturing content data D3 indicating the manufacturing content for the embodiment when the Vdc data D1 and Vpp voltage data D2 were obtained, and obtains a trained model D5 as relationship data indicating the relationship between the analysis data and the manufacturing content data D3.

Since there is a multivariate correlation between the BV in-plane distribution data D20 reflecting the Vdc in-plane distribution data D10 and the manufacturing content data D3, by providing the BV in-plane distribution data D20 and the manufacturing content data D3 to the learning model creation unit 73, the learning model creation unit 73 can create a learned model D5 which is the result of multivariate analysis.

Note that the learning model creation unit 73 performed multivariate analysis using machine learning with AI technology, but even if general multivariate analysis processing is performed without using AI technology, it is expected that highly useful association data similar to the learned model D5 will be created.

The learning model creation unit 73 may create the learned model D5 by changing the conditions during etching using one set of Vdc sensor assemblies 190, or may create the learned model D5 using multiple sets of Vdc sensor assemblies 190 under different conditions.

The learning model recording unit 74 records the learned model D5 created by the learning model creation unit 73. The learned model D5 recorded in the learning model recording unit 74 can be output to the manufacturing content inference device 80 at a subsequent stage.

In this way, the learning model creation device 70 executes a method for producing a learned model, which includes steps including the following steps (a) and (b).

Step (a): The Vdc in-plane distribution creation unit 71 obtains Vdc in-plane distribution data D10 indicating the in-plane distribution of the negative offset potential Vdc in the actual use substrate based on Vdc data D1 including Vdc sense data D11.

Step (b): The data analysis unit performs machine learning using the analysis data as input data and manufacturing content data D3 indicating the manufacturing content of the actually used substrate when the analysis data was obtained as training data, and produces a trained model D5 for estimating the manufacturing content of the actually used substrate corresponding to the analysis data. In embodiment 1, the analysis data is BV in-plane distribution data D20.

Here, the data analysis unit includes a DC bias in-plane distribution creation unit 72 and a learning model creation unit 73, and the analysis data becomes BV in-plane distribution data D20 that reflects Vdc in-plane distribution data D10.

By using the learned model D5 obtained in step (b) in the manufacturing method of the learned model described above and performing inference using the manufacturing content inference device 80 described below, it is possible to accurately obtain optimal manufacturing conditions for the actual use substrate so that the desired in-plane distribution of the negative offset potential Vdc is obtained when manufacturing the actual use substrate.

(Modification)
3 has an internal learning model creation unit 73, but a configuration in which a component corresponding to the learning model creation unit 73 is provided as an external learning model creation unit outside the learning model creation device 70 can be considered as a modified example of the learning model creation device 70. In this modified example, the learned model D5 created by the external learning model creation unit is received, and the learned model D5 is recorded in the internal learning model recording unit 74.

Therefore, in a modified example of the learning model creation device 70, the learning model creation unit 73 shown in Figure 3 is omitted, the BV in-plane distribution data D20 is output to an external external learning model creation unit, and the learned model D5 is received from the external external learning model creation unit.

The external learning model creation unit performs machine learning using the BV in-plane distribution data D20 as input data and the manufacturing content data D3 as training data, creates a learned model D5 for estimating the manufacturing content of an actually used substrate corresponding to the BV in-plane distribution data D20, and outputs the learned model D5 to a modified example of the learning model creation device 70. In other words, the learned model D5 is data obtained externally by performing machine learning using the BV in-plane distribution data D20 as input data and the manufacturing content data D3 as training data.

Then, the learning model recording unit 74 in the modified example of the learning model creation device 70 receives the learned model D5 from the outside and records the learned model D5.

In the modified example of the learning model creation device 70 described above, the device configuration can be simplified because there is no need to have the learning model creation unit 73 internally.

(Manufacturing content inference device 80)
FIG. 4 is an explanatory diagram schematically showing the configuration of manufacturing content inference device 80 in plasma processing system 501 according to the first embodiment.

As shown in the same figure, the manufacturing content inference device 80 includes an inference unit 81 and a processing content determination unit 82 as its main components.

As shown in Figure 2, the manufacturing content inference device 80 receives the learned model D5 created by the learning model creation device 70 and externally receives desired in-plane distribution data D4. The desired in-plane distribution data D4 includes substrate-corresponding in-plane potential distribution data desired when manufacturing an actual substrate.

The inference unit 81 receives the desired in-plane distribution data D4 and the learned model D5. The desired in-plane distribution data D4 includes desired Vdc in-plane distribution data D10d that indicates the in-plane distribution of the negative offset potential Vdc on the actual substrate desired during manufacturing.

Specifically, the desired in-plane distribution data D4 includes desired Vdc in-plane distribution data D10d as well as desired BV in-plane distribution data D20d. The desired BV in-plane distribution data D20d is data indicating the in-plane distribution of the DC bias BV desired for the actual substrate used during manufacturing. The desired Vpp voltage data D2d is a constant value, which is the sum of the multiple negative offset potentials Vdc indicated by the desired Vdc in-plane distribution data D10d and the multiple DC biases BV indicated by the desired BV in-plane distribution data D20d.

Furthermore, a combination of the desired Vdc in-plane distribution data D10d and the desired Vpp voltage data D2d may be used as the desired in-plane distribution data D4. This is because the desired BV in-plane distribution data D20d can be obtained from the difference between the positive offset potential Vpp indicated by the desired Vpp voltage data D2d and multiple negative offset potentials Vdc indicated by the desired Vdc in-plane distribution data D10d.

The inference unit 81 uses the learned model D5 to estimate data indicating the manufacturing details for the actual substrate corresponding to the desired in-plane distribution data D4 as inference data D7.

The inference data D7 includes optimal gas flow rate data D72, optimal gas pressure data D73, optimal RF output data D74, and optimal process data D75. The optimal gas flow rate data D72 is data indicating the optimal supply flow rate of at least one gas that satisfies the gas type indicated by the gas type data D31. The optimal gas pressure data D73 is data indicating the optimal etching pressure within the etching chamber 1. The RF output data D34 is data indicating the optimal RF output, such as the oscillation frequency of the RF power supply 12 and the maximum rated output, which is the input power.

Optimal process data D75 is data indicating etching process details other than the data indicated by the above-mentioned data groups D72 to D74. Note that the type of etching gas used in the etching process has already been determined by gas type data D31 in the manufacturing details data D3, so the gas type data is not included in the inference data D7.

In this way, the inference data D7, which includes data groups D72 to D75, becomes data that indicates the optimal manufacturing details, including the etching process details for the actual substrate, in order to realize the in-plane distribution of the DC bias BV shown in the desired in-plane distribution data D4.

The processing content determination unit 82 receives the inference data D7 and determines the etching processing content of the actual process to be performed by the plasma processing device 101 based on the inference data D7.

Therefore, the plasma processing system 501 of embodiment 1 can perform etching processing that satisfies the desired etching shape and etching rate by using the plasma processing device 101 to perform etching processing on an actual substrate with the content determined by the processing content determination unit 82.

(effect)
The plasma processing apparatus 101 used in the plasma processing system 501 of the first embodiment includes a Vdc sensor assembly 190. The Vdc sensor assembly 190 has a plurality of Vdc sensors s19 that are provided corresponding to a plurality of locations on the formation surface of the actual use substrate to be manufactured in a plan view. Therefore, the in-plane distribution of the negative potential of the actual use substrate can be accurately recognized from the Vdc sense data D11 indicating a plurality of measured potentials obtained from the Vdc sensor assembly 190.

The Vdc data D1 input to the Vdc in-plane distribution creation unit 71 of the learning model creation device 70 is obtained from multiple Vdc sensors s19 arranged corresponding to the formation surface of the actual substrate, so the Vdc in-plane distribution creation unit 71 can create highly accurate Vdc in-plane distribution data D10.

The learning model creation device 70 in the plasma processing system 501 of embodiment 1 includes a DC bias in-plane distribution creation unit 72, a learning model creation unit 73, and a learning model recording unit 74 as data analysis units.

As mentioned above, the DC bias in-plane distribution creation unit 72, which is a related data creation unit, obtains BV in-plane distribution data D20 as analysis data reflecting the Vdc in-plane distribution data D10 based on the Vdc in-plane distribution data D10 and the Vpp voltage data D2.

As mentioned above, the learning model creation unit 73, which is the association data creation unit, creates association data showing the association between the BV in-plane distribution data D20 and the manufacturing content data D3 as a learned model D5.

In this way, in the plasma processing system 501 of embodiment 1, the data analysis unit in the learning model creation device 70 obtains the learned model D5 as association data indicating the association between the BV in-plane distribution data D20, which is analysis data reflecting the Vdc in-plane distribution data D10, and the manufacturing details data D3. The learned model D5 is recorded in the learning model recording unit 74.

Therefore, the plasma processing system 501 of embodiment 1 can recognize the optimal manufacturing conditions for actual use substrates by estimating using the learned model D5 so that the desired in-plane distribution of negative potential is obtained when manufacturing the actual use substrates.

In addition, the learning model creation unit 73 of the learning model creation device 70 performs machine learning using AI technology to create a learned model D5 for estimating the manufacturing details for the actually-used substrate. Therefore, by performing inference using the learned model D5 created by the learning model creation unit 73, it is possible to accurately obtain optimal manufacturing conditions for the actually-used substrate so that the desired in-plane distribution of the negative offset potential Vdc is obtained when the actually-used substrate is manufactured.

Specifically, the inference unit 81 in the manufacturing content inference device 80 of the plasma processing system 501 of embodiment 1 can use the trained model D5 to accurately obtain inference data D7 indicating the optimal manufacturing content for the actually-used substrate so that the in-plane distribution of negative potential indicated by the desired in-plane distribution data D4 is obtained during the manufacturing of the actually-used substrate. This inference data D7 defines the optimal manufacturing conditions for the actually-used substrate.

The plasma processing system 501 of embodiment 1 employs the algorithm for creating the trained model D5 in the learning model creation device 70 described above and the algorithm for obtaining the inference data D7 in the manufacturing content inference device 80. Therefore, compared to conventional etching condition optimization techniques, the plasma processing system 501 can significantly reduce the number of etching condition optimization experiments, and can reduce the number of actually used substrates required for etching condition optimization to one to several. In addition, it is possible to simplify the in-plane distribution measurement and cross-sectional microscopic observation required for etching characteristic evaluation.

The plasma processing system 501 of embodiment 1 includes a learning model creation device 70 shown in Figure 3 and a manufacturing content inference device 80 shown in Figure 4. Therefore, in the plasma processing system 501, the number of steps for shape step measurement or optical film thickness measurement, or in-plane distribution measurement that requires cross-sectional electron microscope observation, and cross-sectional shape observation that requires cross-sectional electron microscope observation, can be significantly reduced, and in some circumstances, can be eliminated.

In particular, cross-sectional electron microscope observations performed when measuring film thickness or observing cross-sectional shapes require cutting at a desired location, precision cross-section processing using a focused ion beam (FIB), and then electron microscope observation, which requires a significant amount of time and effort. Furthermore, cross-sectional electron microscope observations must be performed at multiple locations on a single substrate.

In the plasma processing system 501 of embodiment 1, the above-mentioned procedures can be eliminated, thereby simplifying the process optimization processing content for obtaining inference data D7.

In the plasma processing system 501 of embodiment 1, AI technology based on machine learning was used in the learning model creation unit 73 of the learning model creation device 70 and the inference unit 81 of the manufacturing content inference device 80, but as mentioned above, it is not necessary to use machine learning and other analysis technologies may also be used.

For example, in a data analysis device corresponding to the learning model creation device 70, the data analysis unit corresponding to the DC bias in-plane distribution creation unit 72 and the learning model creation unit 73 may use multivariate analysis using response surface methodology, which requires careful setting of experimental parameters in advance.

In other words, the data analysis unit may record as association data a database based on past experimental examples that shows the relationship between the correct value of the in-plane distribution of the negative offset potential Vdc and manufacturing content feature quantities consisting of data indicating the manufacturing content. This association data replaces the trained model D5. The data analysis unit may also create data equivalent to the correct amount of the in-plane distribution of the positive offset potential Vpp and the negative offset potential Vdc on an actually used substrate, i.e., the desired in-plane distribution data D4.

In this case, the inference unit 81 of the manufacturing content inference device 80 can predict the output value corresponding to the inference data D7 by calling it up as a data table in the database created by the data analysis unit and mathematically complementing the values in the data table.

(Processing circuit)
5 is a block diagram showing the configuration of a processing circuit 90 corresponding to components 71 to 73 in a learning model creation device 70 and components 81 and 82 in a manufacturing content inference device 80 in a plasma processing system 501. The functions of the components 71 to 73, 81, and 82 described above are realized by the processing circuit 90 shown in FIG. 5. That is, the processing circuit 90 functions as a circuit including components 71 to 73, 81, and 82. Note that component 71 includes a Vdc in-plane distribution creation unit 71V in a learning model creation device 70B of a seventh embodiment, which will be described later.

When the processing circuit 90 is dedicated hardware, the processing circuit 90 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination of these. Components 71 to 73, 81, and 82 may be realized individually by multiple processing circuits, or collectively by a single processing circuit.

Figure 6 is a block diagram showing another example configuration of a processing circuit corresponding to components 71-73, 81, and 82. As shown in the figure, processing circuit 90 includes processor 91, memory 92, and bus 96, which serves as a data transfer path between processor 91 and memory 92. The functions of components 71-73, 81, and 82 are realized by processor 91 executing a program stored in memory 92. For example, the functions of components 71-73, 81, and 82 are realized by processor 91 executing software or firmware written as a program. In other words, learning model creation device 70 and manufacturing content inference device 80 include memory 92 that stores a program, processor 91 that executes the program, and bus 96 for data transfer between memory 92 and processor 91.

The program causes the computer to execute the processing procedures or processing methods of the functions of each of the components 71 to 73, 81 and 82.

The processor 91 may be, for example, a central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, DSP (Digital Signal Processor), etc. The memory 92 may be, for example, a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), etc. Furthermore, the memory 92 may be any storage medium that will be used in the future, such as a magnetic disk, flexible disk, optical disk, compact disk, minidisk, DVD, etc.

Furthermore, the learning model recording unit 74 in the learning model creation device 70 can be realized by memory 92 or an external storage device (not shown) connected to bus 96. Vdc data D1, Vpp voltage data D2, manufacturing details data D3, desired in-plane distribution data D4, and inference data D7 are classified as data stored in memory 92 or an external storage device (not shown). Similarly, process data D6 used by the learning model creation device 70B of embodiment 7 described below is also data stored in memory 92 or an external storage device (not shown).

The functions of the above-mentioned components 71-73, 81, and 82 may be partially realized by dedicated hardware, and partially realized by software or firmware. In this way, the processing circuit 90 realizes the above-mentioned functions by hardware, software, firmware, or a combination of these.

<Second Embodiment>
7 is an explanatory diagram schematically illustrating a cross-sectional structure of a main part of plasma processing apparatus 102 included in plasma processing system 502 according to a second embodiment of the present disclosure. Plasma processing system 502 according to the second embodiment has a configuration in which plasma processing apparatus 101 in FIG. 2 is replaced with plasma processing apparatus 102.

The plasma processing apparatus 102 shown in Figure 7 is a parallel plate type RIE etching apparatus that generates plasma in the etching chamber 1 and performs etching processing, similar to the plasma processing apparatus 101 of embodiment 1.

(Plasma Processing Apparatus 102)
7, the same components as those in the plasma processing apparatus 101 shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted as appropriate, and the description will be centered on the characteristic parts of the plasma processing apparatus 102 according to the second embodiment.

The etching chamber 1 has a chamber inner housing 1B as its main component, and within the chamber inner housing 1B, an anode electrode 2 serving as the upper electrode is provided above, and a cathode electrode 3S serving as the lower electrode is provided below.

The cathode electrode 3S is divided into multiple segmented electrodes 3d. Each of the multiple segmented electrodes 3d is electrically connected to an individual coupling capacitor 34 provided under the bottom surface of the chamber inner casing 1B, thereby separating the DC component. Each of the multiple coupling capacitors 34 is connected to a common wiring L3 via an isolation diode 35.

Each isolation diode 35 is provided to prevent mutual interference between the direct currents separated from the multiple split electrodes 3d by the coupling capacitor 34, and its anode is connected to the coupling capacitor 34 side, and its cathode is connected to the common wiring L3.

The common wiring L3 is connected to a variable capacitor 13 for impedance matching. After impedance matching by the variable capacitor 13, the common wiring L3 is connected to an RF power supply 12, which supplies power for plasma discharge to each of the multiple segment electrodes 3d of the cathode electrode 3S. The RF power supply 12 is connected to a ground potential 16.

A Vdc measurement voltmeter 150, which is a lower electrode voltmeter, is connected to both poles of each coupling capacitor 34. In other words, multiple Vdc measurement voltmeters 150 are provided corresponding to the multiple split electrodes 3d.

Therefore, the potential of each of the multiple divided electrodes 3d can be measured by a corresponding Vdc measurement voltmeter 150 among the multiple Vdc measurement voltmeters 150, which are multiple lower electrode voltmeters.

In this way, the multiple split electrodes 3d in the cathode electrode 3S function as multiple Vdc sensors s19 of the Vdc sensor assembly 190 of embodiment 1. Each of the multiple split electrodes 3d is also provided with a voltage measurement mechanism including a coupling capacitor 34, an isolation diode 35, and a Vdc measurement voltmeter 150.

Therefore, the multiple split electrodes 3d in the cathode electrode 3S serve as multiple Vdc sensors s19 of the Vdc sensor assembly 190 of embodiment 1.

The substrate to be etched 10, which is the actual substrate, is placed on the cathode electrode 3S.

Since the cathode electrode 3S is positioned directly below the substrate 10 to be etched, the multiple Vdc measurement voltmeters 150 can comprehensively measure the in-plane distribution of the negative offset potential Vdc directly below the substrate 10 to be etched. Each of the multiple Vdc measurement voltmeters 150 is a conventional voltmeter.

Data indicating multiple measured potentials measured by multiple Vdc measuring voltmeters 150 constitutes the Vdc sense data D11 in embodiment 2. Furthermore, position information of the substrate 10 to be etched corresponding to the multiple measured potentials constitutes position information data D12. As mentioned above, since the position information corresponding to the multiple measured potential data is known in advance, the position information data D12 may be supplied to the learning model creation device 70 from an external source.

The combination of Vdc sense data D11 and position information data D12 becomes Vdc data D1. Position information data D12 is data that complements Vdc sense data D11.

Note that the exhaust system, such as a vacuum pump using the gas exhaust holes 4, and the transport system, such as the lifting motor 32, in the plasma processing apparatus 200 shown in Figure 17 are omitted from Figure 7. That is, like the plasma processing apparatus 200, the plasma processing apparatus 102 of embodiment 2 also has the above-mentioned exhaust system and a transport system including the substrate lifting pins 29.

Figure 8 is a perspective view showing the overall configuration of the cathode electrode 3S. As shown in the figure, the cathode electrode 3S is composed of a collection of multiple segmented electrodes 3d divided into a matrix. Because the multiple segmented electrodes 3d are arranged in an array, the complex in-plane distribution applied to the substrate 10 to be etched directly above can be measured comprehensively with high resolution using multiple Vdc measurement voltmeters 150 provided corresponding to the multiple segmented electrodes 3d.

The four lift pin holes 40 that run through the cathode electrode 3S near the center are each provided to allow the substrate lift pins 29 of the transport system for the substrate 10 to pass through.

The plasma processing apparatus 102, which is the main component of the plasma processing system 502 of embodiment 2, is configured in this manner.

In the plasma processing apparatus 102, the cathode electrode 3S, which functions as the Vdc sensor assembly 190, has multiple split electrodes 3d, each of which functions as the main part of the Vdc sensor s19, and the substrate to be etched 10, which is the actual substrate, is placed on the cathode electrode 3S.

The plasma processing apparatus 102 in the plasma processing system 502 of embodiment 2 measures the potential of multiple split electrodes 3d of the cathode electrode 3S arranged directly below the substrate to be etched 10, which is the actual substrate, using multiple Vdc measuring voltmeters 150.

Therefore, the in-plane distribution of the negative offset potential Vdc on the substrate 10 to be etched can be accurately detected from multiple measured potentials measured by multiple Vdc measurement voltmeters 150.

As such, the plasma processing apparatus 102 used in the plasma processing system 502 of embodiment 2 is equipped with a cathode electrode 3S as a Vdc sensor assembly 190. The multiple segmented electrodes 3d of the cathode electrode 3S are provided corresponding to multiple locations on the formation surface of the substrate 10 to be etched when viewed in a plan view. Therefore, the in-plane distribution of the negative offset potential Vdc of the substrate 10 to be etched can be accurately recognized from the multiple measured potentials obtained by the multiple Vdc measurement voltmeters 150 provided corresponding to the multiple segmented electrodes 3d.

As shown in Figure 2, Vdc data D1 including Vdc sense data D11 indicating multiple measured potential data obtained from multiple Vdc measurement voltmeters 150 within the plasma processing apparatus 102 and position information data D12 indicating position information of the multiple measured potential data on the substrate 10 to be etched is output to a downstream learning model creation device 70.

As shown in Figure 2, Vpp voltage data D2 indicating the positive offset potential Vpp obtained from the Vpp measuring voltmeter 18 in the plasma processing apparatus 102 is output to the subsequent learning model creation device 70.

(Learning model creation device 70)
The configuration of the learning model creation device 70 in the plasma processing system 502 of the second embodiment is the same as the configuration shown in Fig. 3. As in the first embodiment, the learning model creation device 70 receives Vdc data D1, Vpp voltage data D2, and manufacturing details data D3, and creates a learned model D5.

Therefore, the plasma processing system 502 of embodiment 2 achieves the same effects as the plasma processing system 501 of embodiment 1 with respect to the learning model creation device 70.

(Manufacturing content inference device 80)
The configuration of the manufacturing content inference device 80 in the plasma processing system 502 of the second embodiment is the same as the configuration shown in Fig. 4. Similarly to the first embodiment, the manufacturing content inference device 80 receives the desired in-plane distribution data D4 and the trained model D5 and creates inference data D7.

Therefore, the plasma processing system 502 of embodiment 2 achieves the same effects as the plasma processing system 501 of embodiment 1 with respect to the manufacturing content inference device 80.

<Third Embodiment>
9 is a perspective view showing an overall configuration of a sensor-embedded substrate 10S in a plasma processing apparatus 103 included in a plasma processing system 503 according to a third embodiment of the present disclosure. FIG. 10 is an explanatory diagram schematically showing a cross-sectional structure of the sensor-embedded substrate 10S and its periphery.

The plasma processing system 503 of embodiment 3 has a configuration in which the plasma processing device 101 in Figure 2 is replaced with the plasma processing device 103.

(Plasma Processing Apparatus 103)
9 and 10, components similar to those of the plasma processing apparatus 101 shown in FIG. 1 are designated by the same reference numerals and explanations thereof are omitted as appropriate, and the description will focus on the characteristic features of the plasma processing apparatus 103 of embodiment 3.

The plasma processing apparatus 103 is characterized by having a sensor-embedded substrate 10S shown in Figures 9 and 10. The sensor-embedded substrate 10S, which is the substrate for actual use, has multiple Vdc sensors s19 built in. This sensor-embedded substrate 10S is placed on the cathode electrode 3, which is the lower electrode.

The plasma processing apparatus 103 has a structure in which the substrate to be etched 10 in the plasma processing apparatus 200 of the basic technology shown in Figure 17 is replaced with a combination of a sensor-embedded substrate 10S and lead-out TAB wiring 38 and 38Y. Therefore, the plasma processing apparatus 103 has a cathode electrode 3 similar to that of the plasma processing apparatus 200. However, the Vdc measuring voltmeter 15 is omitted.

Multiple Vdc sensors s19 are built into the sensor-embedded substrate 10S in an array-like arrangement, allowing for comprehensive measurement of the complex in-plane distribution of the negative offset potential Vdc applied to the sensor-embedded substrate 10S itself with high resolution.

The multiple Vdc sensors s19 are electrically connected to lead-out TAB (Tape Automated Bonding) wiring 38X and 38Y. If the multiple Vdc sensors s19 are arranged in a matrix defined by the X and Y directions, the lead-out TAB wiring 38X can be used as multiple scanning lines that scan along the X direction, and the lead-out TAB wiring 38Y can be used as multiple output lines that extract the measured potential along the Y direction. This allows the measured potential of each of the multiple Vdc sensors s19 to be sequentially extracted from the lead-out TAB wiring 38Y.

The lead-out TAB wiring 38X and 38Y are each provided to connect from the side of the sensor-embedded substrate 10S to the multiple Vdc sensors s19 within the sensor-embedded substrate 10S. In this way, the lead-out TAB wiring 38X and 38Y can extract Vdc sense data D11 indicating the multiple measured potentials measured by the multiple Vdc sensors s19 built into the sensor-embedded substrate 10S.

As shown in Figure 10, the sensor-embedded substrate 10S is placed on the cathode electrode 3. Since the sensor-embedded substrate 10S is the substrate to be manufactured and used, various manufacturing processes are performed on the sensor-embedded substrate 10S.

In the example shown in Figure 10, a film of the material to be etched 21 has already been formed on the surface of the sensor-embedded substrate 10S, and a patterned resist 20 is provided on the material to be etched 21. In other words, Figure 10 shows the state in which an etching process is performed on the material to be etched 21 using the resist 20 as a mask.

In this state, etching gas is introduced into the etching chamber 1 of the plasma processing apparatus 103, and an RF discharge is initiated between the anode electrode 2 and the cathode electrode 3, thereby performing the etching process. The etching process causes an etching reaction on the material to be etched 21. At the same time that the material to be etched 21 is etched, multiple measured potentials measured by multiple Vdc sensors s19 built into the sensor-embedded substrate 10S are extracted to the outside via the extraction TAB wiring 38 and 38Y. Data indicating the extracted multiple measured potentials becomes the Vdc sense data D11.

In this way, in the plasma processing apparatus 103 of embodiment 3, the sensor-embedded substrate 10S has multiple Vdc sensors s19 built in. That is, the sensor-embedded substrate 10S functions as the Vdc sensor assembly 190 of embodiment 1 and as the substrate for actual use. In this case, the plasma processing apparatus 103 does not require any special modifications to the configuration of a conventional parallel plate RIE etching apparatus, and the negative offset potential Vdc can be measured with high in-plane resolution.

The plasma processing apparatus 103, which is the main component of the plasma processing system 503 of embodiment 3, is configured in this manner.

In the plasma processing apparatus 103 of embodiment 3, the sensor-embedded substrate 10S, which is the substrate to be actually used, has multiple Vdc sensors s19 built in, and this sensor-embedded substrate 10S is placed on the cathode electrode 3S.

The plasma processing apparatus 103 in the plasma processing system 503 of embodiment 3 can accurately detect the in-plane distribution of the negative offset potential Vdc of the sensor-embedded substrate 10S, which is the actual substrate, from multiple measured potentials obtained from the sensor-embedded substrate 10S incorporating multiple Vdc sensors s19.

As such, the plasma processing apparatus 103 used in the plasma processing system 503 of embodiment 3 includes a sensor-embedded substrate 10S as a Vdc sensor assembly 190. The multiple Vdc sensors s19 of the sensor-embedded substrate 10S are provided corresponding to multiple locations on the formation surface of the sensor-embedded substrate 10S to be manufactured in a planar view. Therefore, the multiple measured potentials obtained from the multiple Vdc sensors s19 can accurately determine the in-plane distribution of the negative offset potential Vdc of the sensor-embedded substrate 10S.

As shown in Figure 2, Vdc data D1 including Vdc sense data D11 indicating multiple measured potential data obtained from multiple Vdc sensors s19 within the plasma processing apparatus 103 and position information data D12 indicating position information of the multiple measured potential data on the substrate 10 to be etched is output to a downstream learning model creation device 70.

Furthermore, as in embodiments 1 and 2, Vpp voltage data D2 indicating the positive offset potential Vpp obtained from the Vpp measurement voltmeter 18 in the plasma processing device 103 is output to the subsequent learning model creation device 70.

(Learning model creation device 70)
The configuration of the learning model creation device 70 in the plasma processing system 503 of the third embodiment is the same as the configuration shown in Fig. 3. As in the first embodiment, the learning model creation device 70 receives Vdc data D1, Vpp voltage data D2, and manufacturing details data D3, and creates a learned model D5.

Therefore, the plasma processing system 503 of embodiment 3 achieves the same effects as the plasma processing system 501 of embodiment 1 with respect to the learning model creation device 70.

(Manufacturing content inference device 80)
The configuration of the manufacturing content inference device 80 in the plasma processing system 503 of the third embodiment is the same as the configuration shown in Fig. 4. Similarly to the first embodiment, the manufacturing content inference device 80 receives the desired in-plane distribution data D4 and the trained model D5 and creates inference data D7.

Therefore, the plasma processing system 503 of embodiment 3 achieves the same effects as the plasma processing system 501 of embodiment 1 with respect to the manufacturing content inference device 80.

<Fourth Embodiment>
11 is a perspective view showing the overall configuration of Vdc sensor substrate 19 in plasma processing apparatus 104 included in plasma processing system 504 according to the fourth embodiment of the present disclosure. FIG. 12 is an explanatory diagram schematically showing the cross-sectional structure of Vdc sensor substrate 19 and its periphery.

The plasma processing system 504 of embodiment 4 has a configuration in which the plasma processing device 101 in Figure 2 is replaced with the plasma processing device 104.

(Plasma processing apparatus 104)
11 and 12, the same components as those of the plasma processing apparatus 101 shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted as appropriate, and the description will be centered on the characteristic parts of the plasma processing apparatus 104.

The plasma processing apparatus 104 is characterized by the addition of a new Vdc sensor substrate 19. The Vdc sensor substrate 19 has multiple Vdc sensors 19 built in. This Vdc sensor substrate 19 is placed on the cathode electrode 3, which is the lower electrode. The substrate to be etched 10, which is the substrate to be actually used, is placed on the Vdc sensor substrate 19.

The plasma processing apparatus 104 has a structure in which a Vdc sensor substrate 19 is provided between the cathode electrode 3 and the substrate 10 to be etched in the plasma processing apparatus 200 of the basic technology shown in Figure 17. Therefore, the plasma processing apparatus 104 has the same cathode electrode 3 and substrate 10 to be etched as the plasma processing apparatus 200. However, the Vdc measuring voltmeter 15 is omitted.

Multiple Vdc sensors s19 are built into the Vdc sensor substrate 19 in an array arrangement, excluding the multiple lifting pin holes 40, and are configured to be able to comprehensively measure the complex in-plane distribution of the negative offset potential Vdc on the substrate 10 to be etched directly above with high resolution.

In addition, the four lifting pin holes 40 that run through the center of the Vdc sensor board 19 are each provided to allow the substrate lifting pins 29 of the transport system for the substrate 10 to pass through.

The multiple Vdc sensors s19 are electrically connected to the draw-out TAB wiring 38X and 38Y. If the multiple Vdc sensors s19 are arranged in a matrix defined by the X and Y directions, the draw-out TAB wiring 38X can be used as multiple scanning lines that scan along the X direction, and the draw-out TAB wiring 38Y can be used as multiple output lines that extract the measured potential along the Y direction, thereby allowing the measured potential of each of the multiple Vdc sensors s19 to be extracted from the draw-out TAB wiring 38Y.

The lead-out TAB wiring 38X and 38Y are each provided to connect from the side of the Vdc sensor substrate 19 to multiple Vdc sensors s19 within the Vdc sensor substrate 19. In this way, the lead-out TAB wiring 38X and 38Y can extract Vdc sense data D11 indicating multiple measured potentials measured by the multiple Vdc sensors s19 built into the Vdc sensor substrate 19.

As shown in Figure 12, a Vdc sensor substrate 19 is placed on the cathode electrode 3, and a substrate 10 to be etched is placed on the Vdc sensor substrate 19. Since the substrate 10 to be etched is a substrate for actual use, various manufacturing processes are performed on the substrate 10 to be etched.

In the example shown in Figure 12, a film of the material to be etched 21 has already been formed on the surface of the substrate to be etched 10, and a patterned resist 20 is provided on the material to be etched 21. In other words, Figure 12 shows the state in which an etching process is performed on the material to be etched 21 using the resist 20 as a mask.

In the plasma processing apparatus 104, etching gas is introduced into the etching chamber 1 in the state shown in FIG. 12, and an RF discharge is initiated between the anode electrode 2 and the cathode electrode 3, thereby performing an etching process. The etching process causes an etching reaction on the material to be etched 21. At the same time that the material to be etched 21 is etched, multiple measured potentials measured by multiple Vdc sensors s19 built into the Vdc sensor substrate 19 are extracted to the outside via the extraction TAB wiring 38 and 38Y. Data indicating the extracted multiple measured potentials becomes Vdc sense data D11.

In this way, in the plasma processing apparatus 104 of embodiment 4, the Vdc sensor substrate 19 has multiple Vdc sensors s19 built in. In other words, the Vdc sensor substrate 19 functions as the Vdc sensor assembly 190 of embodiment 1.

In this case, by replacing only the multiple substrate lift pins 29 used in the transport system for the substrate 10 to be etched from a conventional parallel plate RIE etching apparatus, a plasma processing apparatus 104 can be realized that can measure the negative offset potential Vdc with high in-plane resolution. The multiple substrate lift pins 29 are replaced because the Vdc sensor substrate 19 provided between the cathode electrode 3 and the substrate 10 to be etched increases the height at which the substrate 10 to be etched is positioned.

The plasma processing apparatus 104, which is the main component of the plasma processing system 504 of embodiment 4, is configured in this manner.

In the plasma processing apparatus 104, the Vdc sensor substrate 19 has multiple Vdc sensors s19 built in, and the Vdc sensor substrate 19 is placed on this Vdc sensor substrate 19.

By adopting this structure, the plasma processing apparatus 104 of embodiment 4 can collect high in-plane resolution Vdc sense data D11 from multiple Vdc sensors s19 by replacing only the substrate lifting pins 29 in a conventional parallel plate type RIE etching apparatus, as described above.

The plasma processing apparatus 104 in the plasma processing system 504 of embodiment 4 can accurately detect the in-plane distribution of the negative offset potential Vdc on the etching substrate 10, which is the actual substrate, from multiple measured potentials obtained from multiple Vdc sensors s19 built into the Vdc sensor substrate 19.

As such, the plasma processing apparatus 104 used in the plasma processing system 504 of embodiment 4 is equipped with a Vdc sensor substrate 19 as a Vdc sensor assembly 190. The multiple Vdc sensors s19 on the Vdc sensor substrate 19 are provided corresponding to multiple locations on the formation surface of the substrate 10 to be etched, as viewed in plan. Therefore, the multiple measured potentials obtained from the multiple Vdc sensors s19 can accurately recognize the in-plane distribution of the negative offset potential Vdc on the substrate 10 to be etched.

As shown in Figure 2, Vdc data D1 including Vdc sense data D11 indicating multiple measured potentials obtained from multiple Vdc sensors s19 within the plasma processing apparatus 104 and position information data D12 indicating position information of the multiple measured potential data on the substrate 10 to be etched is output to a downstream learning model creation device 70.

Furthermore, as in embodiments 1 to 3, Vpp voltage data D2 indicating the positive offset potential Vpp obtained from the Vpp measuring voltmeter 18 in the plasma processing apparatus 104 is output to the subsequent learning model creation device 70.

(Learning model creation device 70)
The configuration of the learning model creation device 70 in the plasma processing system 504 of the fourth embodiment is the same as the configuration shown in Fig. 3. As in the first embodiment, the learning model creation device 70 receives Vdc data D1, Vpp voltage data D2, and manufacturing details data D3, and creates a learned model D5.

Therefore, the plasma processing system 504 of embodiment 4 achieves the same effects as the plasma processing system 501 of embodiment 1 with respect to the learning model creation device 70.

(Manufacturing content inference device 80)
The configuration of the manufacturing content inference device 80 in the plasma processing system 504 of the fourth embodiment is the same as the configuration shown in Fig. 4. Similarly to the first embodiment, the manufacturing content inference device 80 receives the desired in-plane distribution data D4 and the trained model D5 and creates inference data D7.

Therefore, the plasma processing system 504 of embodiment 4 achieves the same effects as the plasma processing system 501 of embodiment 1 with respect to the manufacturing content inference device 80.

<Fifth Embodiment>
The fifth embodiment is characterized by the arrangement of the plurality of Vdc sensors s19 on the Vdc sensor substrate 19 shown in the fourth embodiment. That is, except that in the plasma processing apparatus 104 of the fourth embodiment, the Vdc sensor substrate 19 shown in Figures 11 and 12 is replaced with the Vdc sensor substrate 19B shown in Figure 13, the plasma processing system of the fifth embodiment is similar to the plasma processing system 504 of the fourth embodiment, and the plasma processing apparatus of the fifth embodiment is similar to the plasma processing apparatus 104 of the fourth embodiment.

(Vdc sensor board 19B)
13 is an explanatory diagram schematically illustrating the arrangement of Vdc sensors on a Vdc sensor substrate 19B according to embodiment 5. As shown in FIG. 13, Vdc sensor substrate 19B incorporates Vdc sensors s42 to s46 as potential measurement sensors corresponding to the multiple Vdc sensors s19 on Vdc sensor substrate 19. There is at least one of each of Vdc sensors s42 to s46. For convenience of explanation, the following description will simply refer to Vdc sensor s42, Vdc sensor s43, Vdc sensor s44, Vdc sensor s45, and Vdc sensor s46 without specifically indicating the number of Vdc sensors s42 to s46.

Similar to the multiple Vdc sensors s19 of the Vdc sensor substrate 19 of embodiment 4, the Vdc sensors s42 to s46 of the Vdc sensor substrate 19B of embodiment 5 are electrically connected to the lead-out TAB wiring 38X and 38Y.

As shown in Figure 13, the multiple potential measurement sensors provided on the Vdc sensor substrate 19B are classified into Vdc sensors s42 to s46. Vdc sensor s42 is provided in the central region of the Vdc sensor substrate 19 (hereinafter abbreviated as "substrate central region"), Vdc sensor s43 is provided in the peripheral region of the Vdc sensor substrate 19 (hereinafter abbreviated as "substrate peripheral region"), and Vdc sensor s44 is provided in the peripheral region of the lift pin hole 40 through which the substrate lift pin 29 passes (hereinafter abbreviated as "pin hole peripheral region").

In the substrate 10 to be etched, the above-mentioned central region of the substrate, peripheral region of the substrate, and peripheral region of the pin hole are each negative potential focus regions where large fluctuations in the negative offset potential Vdc are predicted.

Vdc sensor s45 is provided in sparse resist pattern region R45 during the etching process, and Vdc sensor s46 is provided in dense resist pattern region R46 during the etching process. Sparse resist pattern region R45 is a region where the formation density of the resist pattern to be formed during the etching process is lower than the normal level, and dense resist pattern region R46 is a region where the formation density of the resist pattern to be formed during the etching process is higher than the normal level.

When the resist pattern formation density in the sparse resist pattern region R45 is M45, the resist pattern formation density in the dense resist pattern region R46 is M46, and the normal level resist pattern formation density is M0, the density relationship {M46 > M0 > M45} holds. Note that the reference density M0 may be divided into two for determining the sparse resist pattern region R45 and the dense resist pattern region R46.

In this way, the resist pattern sparse region R45 and the resist pattern dense region R46 are recognized from the resist pattern that is to be formed above the etching substrate 10, which is the actual substrate.

In the substrate 10 to be etched, the sparse resist pattern region R45 and the dense resist pattern region R46 are negative potential focus regions where the fluctuations in the negative offset potential Vdc are predicted to be large.

In this way, the Vdc sensors s42 to s46, which are multiple potential measurement sensors provided on the Vdc sensor substrate 19, have sensor placement characteristics in which they are positioned corresponding to negative potential focus areas where the negative offset potential Vdc of the substrate to be etched 10 is expected to fluctuate significantly, based on the shape of the substrate to be etched 10 and the density of the resist pattern to be formed on the substrate to be etched 10.

For example, in the Vdc sensor substrate 19B, Vdc sensors s42 to s46 are arranged in areas that overlap in a planar view with the central substrate region, the peripheral substrate region, and the peripheral pin hole region of the etched substrate 10, as well as the sparse resist pattern region R45 and the dense resist pattern region R46.

Therefore, by having the above-mentioned sensor arrangement characteristics, the Vdc sensor substrate 19B used in the plasma processing apparatus of embodiment 5 can keep the number of potential measurement sensors corresponding to Vdc sensors s42 to s46 to a minimum, thereby accurately recognizing the in-plane distribution of the negative offset potential Vdc corresponding to the substrate 10 to be etched.

In other words, by using the Vdc sensor substrate 19B of embodiment 5, it is possible to use a conventional parallel plate type RIE etching apparatus as is, reduce the number of potential measurement sensors required for machine learning and the amount of data indicating the measured potential, and reduce the cost required for multiple potential measurement sensors.

As a result, the load on the processing circuitry required for machine learning processing in the learning model creation device 70 can be reduced, significantly reducing the number of etching condition optimization experiments required to obtain a highly accurate trained model D5. Furthermore, while a huge number of test substrates were previously required to perform data analysis, by adopting the Vdc sensor substrate 19B of embodiment 5, the number of substrates 10 to be etched required for etching condition optimization can be reduced to one to several.

Note that Figure 13 shows a Vdc sensor board 19B, which is an improved version of the Vdc sensor board 19 of embodiment 4. Similarly, the cathode electrode 3S of embodiment 2 may be improved to have the above-mentioned sensor placement characteristics, or the sensor-embedded board 10S of embodiment 3 may be improved to have the above-mentioned sensor placement characteristics.

For example, when improving the cathode electrode 3S of embodiment 2, it is possible to selectively provide a voltage measurement mechanism among the multiple split electrodes 3d in accordance with the above-mentioned sensor placement characteristics.

Sixth Embodiment
The sixth embodiment is characterized by the circuit configuration of the plurality of Vdc sensors s19 on the Vdc sensor substrate 19 C. Therefore, except for the fact that the circuit configuration of the plurality of Vdc sensors s19 on the Vdc sensor substrate 19 in the plasma processing apparatus 104 of the fourth embodiment is the circuit configuration shown in Vdc sensor substrate 19 C, the plasma processing system of the sixth embodiment is similar to the plasma processing system 504 of the fourth embodiment, and the plasma processing apparatus of the sixth embodiment is similar to the plasma processing apparatus 104 of the fourth embodiment.

(Vdc sensor board 19C)
Figure 14 is a circuit diagram showing the circuit configuration of the Vdc sensor s19 on the Vdc sensor substrate 19C of embodiment 6. An XY Cartesian coordinate system is shown in Figure 14. As shown in Figure 14, each of the multiple Vdc sensors s19 includes a Vdc detection capacitor 47 and a switching transistor 50 as main components. The Vdc detection capacitor 47 serves as a charge storage capacitor, and the switching transistor 50 serves as a charge extraction transistor.

The multiple Vdc sensors s19 are arranged in a matrix. Here, the multiple Vdc sensors s19 are arranged in an NX (≧2) × NY (≧2) arrangement, with the X direction being the row direction and the Y direction being the column direction. NX is the first number and NY is the second number. In this way, (NX × NY) Vdc sensors s19 are provided as the multiple Vdc sensors s19.

NX gate wirings L1 are arranged extending in the Y direction, and NY source wirings L2 are arranged extending in the X direction. The NX gate wirings L1 form a first number of scanning lines, and the NY source wirings L2 form a second number of output lines.

Therefore, the Vdc sensor substrate 19C has NX gate wirings L1, each arranged along the column direction, and NY source wirings L2, each arranged along the row direction.

Then, a group of NX gate wirings L1 are pulled out to the outside as the pull-out TAB wiring 38Y shown in Figures 11 and 12, and a group of NY source wirings L2 are pulled out to the outside as the pull-out TAB wiring 38X shown in Figures 11 and 12.

In each Vdc sensor s19, one electrode of the Vdc detection capacitor 47, which is a charge storage capacitor, is connected to the drain, which is one electrode of the switching transistor 50. The other electrode of the Vdc detection capacitor 47 is set to, for example, ground potential.

The gate, which serves as the control electrode of the switching transistor 50, which is a charge extraction transistor, is connected to the corresponding gate wiring L1 out of the NX gate wirings L1. The source, which serves as the other electrode of the switching transistor 50, is connected to the corresponding source wiring L2 out of the NY L2.

Electrons 11 from the plasma dissociated within the etching chamber 1 fall toward the cathode electrode 3 and are accumulated in the Vdc detection capacitor 47 of the Vdc sensor substrate 19C located directly below the substrate 10 to be etched. In other words, a negative charge equivalent to the negative offset potential Vdc at the corresponding location on the substrate 10 to be etched accumulates in the Vdc detection capacitor 47.

Each of the multiple Vdc sensors s19 in the Vdc sensor substrate 19C of embodiment 6 includes a Vdc detection capacitor 47 and a switching transistor 50 as its main components. Therefore, a negative charge equivalent to the negative offset potential Vdc can be stored in the Vdc detection capacitor 47.

When one of the NX gate wirings L1, which make up the first number of scanning lines, is designated as a selected scanning line, NY Vdc sensors s19, each having a switching transistor 50 whose gate is connected to the selected scanning line, are selected as NY selected potential measurement sensors. A selection signal that turns on the switching transistor 50 is applied to the selected scanning line.

Then, in each of the NY Vdc sensors s19 in the selected state, the negative charge accumulated in the Vdc detection capacitor 47 is output to the outside as NY measurement potentials from the NY source lines L2 via the on-state switching transistor 50.

Therefore, by sequentially selecting the NX gate wirings L1 as the selected scanning lines, all of the (NX x NY) Vdc sensors s19's measured potentials can be output to the outside. In this way, a plasma processing apparatus having the Vdc sensor substrate 19C of embodiment 6 can detect the in-plane distribution of the negative offset potential Vdc of the substrate 10 to be etched with high accuracy using multiple measured potentials.

By adopting the above-described circuit configuration, the multiple Vdc sensors s19 of the Vdc sensor substrate 19C of embodiment 6 can detect the in-plane distribution of the negative offset potential Vdc on the substrate 10 to be etched with a high resolution of several hundred μm.

In embodiment 6, the Vdc sensor board 19 of embodiment 4 is improved to provide a Vdc sensor board 19C having a circuit configuration of multiple Vdc sensors s19 as shown in Figure 14. As another aspect, the sensor-embedded board 10S of embodiment 3 can be improved to provide a modified version of the sensor-embedded board 10S having a circuit configuration of multiple Vdc sensors s19 as shown in Figure 14.

Similarly, the Vdc sensor substrate 19B of embodiment 5 may be improved to realize a circuit configuration for Vdc sensors s42 to s46. However, since Vdc sensors s42 to s46 are not arranged in a matrix, some ingenuity is required in the arrangement and number of gate wiring L1 and source wiring L2.

Note that the above-mentioned NX gate wirings L1 correspond to one of the lead-out TAB wirings 38X and 38Y shown in embodiments 3 and 4, and the above-mentioned NY source wirings L2 correspond to the other of the lead-out TAB wirings 38X and 38Y shown in embodiments 3 and 4.

Therefore, even if wiring cannot be drawn out to the bottom of multiple Vdc sensors s19, as in the case of the sensor-embedded substrate 10S of embodiment 3, the Vdc sensor substrate 19 of embodiment 4, and the Vdc sensor substrate 19B of embodiment 5, the in-plane distribution of the negative offset potential Vdc on the substrate to be etched 10 can be detected via the drawing TAB wiring 38 and 38Y.

Seventh Embodiment
(Introduction)
In connection with the seventh and eighth embodiments described below, a system that includes plasma processing systems 501 to 504 according to the first to fourth embodiments may be referred to as "plasma processing system 500," and an apparatus that includes plasma processing apparatuses 101 to 104 according to the first to fourth embodiments may be referred to as "plasma processing apparatus 100." Note that plasma processing apparatus 104 includes embodiment 5 in which Vdc sensor substrate 19 is replaced with Vdc sensor substrate 19B, and embodiment 6 in which Vdc sensor substrate 19 is replaced with a circuit configuration of Vdc sensor substrate 19C.

In other words, embodiment 7 has the same configuration as the plasma processing system 500 and plasma processing apparatus 100 shown in embodiments 1 to 6, except for the characteristics described below.

Figure 15 is an explanatory diagram showing a schematic configuration of a learning model creation device 70B of embodiment 7 included in a plasma processing system 500. The plasma processing system 500 of embodiment 7 has a configuration in which the learning model creation device 70 shown in Figure 3 is replaced with the learning model creation device 70B shown in Figure 15.

(Learning model creation device 70B)
Hereinafter, referring to Figure 15, the same components as those in the learning model creation device 70 shown in Figure 3 will be assigned the same reference numerals and explanations thereof will be omitted as appropriate, and the description will focus on the characteristic parts of the learning model creation device 70B, which is a data analysis device.

As shown in Figure 2, the learning model creation device 70B, which is a data analysis device, receives Vdc data D1, Vpp voltage data D2, and manufacturing details data D3 from the plasma processing device 100. The learning model creation device 70B also receives process data D6 from the outside. The process data D6 is the data included in the manufacturing details data D3 that is necessary for determining whether the product is good or bad using the Mahalanobinus-Taguchi method (hereinafter abbreviated as the "M-T method").

As shown in Figure 15, the learning model creation device 70B includes as its main components a Vdc in-plane distribution creation unit 71V, a DC bias in-plane distribution creation unit 72, a learning model creation unit 73, and a learning model recording unit 74.

The Vdc in-plane distribution creation unit 71V, similar to the Vdc in-plane distribution creation unit 71 of the learning model creation device 70 shown in Figure 3, recognizes multiple measured potentials with recognized position information as multiple position-recognized measured potentials based on the Vdc data D1.

Furthermore, the Vdc in-plane distribution creation unit 71V performs a pass/fail judgment using the M-T method based on the recognized multiple position recognition measurement potentials, the Vpp voltage data D2, and the process data D35, and validates the position recognition measurement potentials that are judged to be good among the multiple position recognition measurement potentials as good judgment measurement potentials, and invalidates the position recognition measurement potentials that are judged to be bad.

Therefore, position recognition measured potentials determined to be defective by the MT method are excluded from processing by the Vdc in-plane distribution creation unit 71V. Position recognition measured potentials determined to be defective are expected to be, for example, measured potentials obtained from a Vdc sensor s19 in a faulty state.

In this way, the Vdc in-plane distribution creation unit 71V narrows down the multiple position determination measurement potentials to multiple pass/fail determination measurement potentials.The Vdc in-plane distribution creation unit 71V then generates Vdc in-plane distribution data D10 based on the multiple pass/fail determination measurement potentials.This Vdc in-plane distribution data D10 becomes the substrate-corresponding in-plane potential distribution data.

In this way, the Vdc in-plane distribution creation unit 71V functions as an in-plane potential distribution data creation unit that derives Vdc in-plane distribution data D10 indicating the in-plane distribution of the negative offset potential Vdc within the etched substrate 10 using only multiple good-judgment measurement potentials based on Vdc data D1 including Vdc sense data D11.

The processing by the DC bias in-plane distribution creation unit 72, the learning model creation unit 73, and the learning model recording unit 74 is performed in the same manner as the DC bias in-plane distribution creation unit 72, the learning model creation unit 73, and the learning model recording unit 74 of the learning model creation device 70 of embodiment 1 shown in Figure 3.

In this way, in the learning model creation device 70B of embodiment 7, the Vdc in-plane distribution creation unit 71V, which is an in-plane potential distribution data creation unit, derives Vdc in-plane distribution data D10, which is substrate-corresponding in-plane potential distribution data, from the multiple position recognition measurement potentials indicated by the Vdc data D1, based on multiple pass/fail judgment measurement potentials narrowed down by pass/fail judgment using the M-T method.

Therefore, the learning model creation device 70B can improve the accuracy of the Vdc in-plane distribution data D10, thereby improving the inference accuracy based on the learned model D5, which is the association data that is finally created.

By including the Vdc in-plane distribution creation unit 71V, the learning model creation device 70B can exclude information from a faulty Vdc sensor s19 and create BV in-plane distribution data D20, which serves as more accurate data for analysis. It also makes it easier to identify a faulty Vdc sensor s19, contributing to reduced maintenance and management costs for the plasma processing apparatus 100.

As with the learning model creation device 70 shown in Figure 3, modified examples are possible for the learning model creation device 70B shown in Figure 15. A modified example of the learning model creation device 70B is configured such that a component equivalent to the learning model creation unit 73 is provided outside the learning model creation device 70B as an external learning model creation unit.

(Manufacturing content inference device 80)
The configuration of the manufacturing content inference device 80 in the plasma processing system 500 of the seventh embodiment is the same as the configuration shown in Fig. 4. Similarly to the first embodiment, the manufacturing content inference device 80 receives the desired in-plane distribution data D4 and the trained model D5 and creates inference data D7.

Therefore, the plasma processing system 500 of embodiment 7 is expected to exhibit inference accuracy greater than that of the plasma processing system 501 of embodiment 1, as the accuracy of the learned model D5 is improved with respect to the manufacturing content inference device 80.

<Eighth Embodiment>
The eighth embodiment defines a method for determining the number of Vdc sensors s19 to be set in the plasma processing apparatus 100.

Figure 16 is an explanatory diagram showing a schematic planar structure of a wafer 60 used as the substrate 10 to be etched.

As shown in the figure, the wafer 60 that serves as the substrate for actual use is circular in plan view, and the wafer 60 is divided into multiple dies (not shown). Each of the multiple dies is a chip that functions as a different device.

16, the diameter of the circular wafer 60 in plan view is R60, and sin 45° = cos 45° ≈ 0.707 is used. Therefore, the length L60 of each side of the largest square that can be secured within the wafer 60 relative to the wafer diameter R60 is calculated as {L60 = R60 × 0.707 ... (1)}. Furthermore, the area SX of the largest square within the wafer 60 is calculated as {SX = (R × 0.707) ² ... (2)}. Assuming that multiple dies are cut out from the largest square within the wafer 60, at least two Vdc sensors s19 must be mounted on each die, depending on the density of the pattern.

Therefore, in embodiment 8, the minimum required number N19 of Vdc sensors when multiple Vdc sensors s19 are installed is determined by the following equation (3).

N19={(R×0.707) ² /DX}×2…(3)
In equation (3), DX represents the maximum area among the areas of the multiple dies.

Thus, in the plasma processing system 500 of embodiment 8, when the maximum square area within the planar structure of the wafer 60 is SX and the maximum area of each of the multiple dies is DX, the number NV of the multiple Vdc sensors s19 is set to satisfy the conditional equation {NV≧=N19=(SX/DX)×2...(4)}.

In the method of determining the set number NV in embodiment 6, if the wafer 60 has a wafer diameter R60 of 6 inches and the die size is a square of 2 cm x 2 cm, the minimum required number N19 of Vdc sensors s19 is 58.

To process 58 measured potentials in combination with manufacturing details data D3, the data feature quantity is 58 x (number of process data items). Here, the manufacturing details data D3 includes the measured Vpp voltage indicated by Vpp voltage data D2, the etching gas type indicated by gas type data D31, the etching gas flow rate indicated by gas flow rate data D32, the etching gas pressure indicated by RF output data D34, the electrode distance between the anode electrode 2 and the cathode electrode 3 indicated by process data D35, and the RF input power indicated by RF output data D34. Here, it is assumed that there is only one type of etching gas type.

In this case, the number of items required for the manufacturing content data D3 will be six, and the minimum number of features for the processed data will be 348. To predict the optimal manufacturing content for obtaining the desired in-plane distribution data D4 from data of this scale, a machine learning model using regression analysis is almost essential.

As for the specific regression analysis method, any regression analysis method used in machine learning, such as multiple regression analysis, ridge regression analysis, lasso regression analysis, or logistic regression analysis, can be selected.

In this way, the plasma processing apparatus 100 in the plasma processing system 500 of embodiment 8 sets the set number NV of multiple Vdc sensors s19 to satisfy the above-mentioned conditional expression (4), thereby minimizing the number of Vdc sensors s19 and enabling the in-plane distribution of negative potential corresponding to the actual substrate to be recognized at a practical level.

Furthermore, by calculating the minimum required number N19 of Vdc sensors s19 based on equation (3), the plasma processing system 500 of embodiment 8 can easily determine that, of the various data analysis methods used by the plasma processing system 500, it is preferable to perform data processing using a machine learning method using regression analysis from the beginning, thereby reducing the effort and time required to consider data analysis processing methods.

<Application range of plasma processing apparatus 100>
The plasma processing apparatus 100 supplies manufacturing gases from a plurality of gas supply holes provided in the anode electrode 2, which also serves as a shower head SH for introducing etching gases. In the above-described first to eighth embodiments, by supplying an etching gas as a manufacturing gas, the plasma processing apparatus 100 can be used as a shape processing apparatus such as an RIE etching apparatus.

In another aspect, the plasma processing apparatus 100 can be used as a thin-film manufacturing apparatus by supplying a film-forming gas as a manufacturing gas from the gas supply hole described above, using the etching chamber 1 as a film-forming chamber, and using the substrate 10 to be etched as a thin-film deposition substrate 22 to generate cations 7 and activated radicals 8 of the film-forming gas.

In this way, the plasma processing apparatus 100 used in the plasma processing system 500 can be used as a shape processing apparatus such as an etching apparatus by using an etching gas as the manufacturing gas, and can be used as a thin film manufacturing apparatus by using a film formation gas as the manufacturing gas.

<Others>
Although the present disclosure has been described in detail, the above description is illustrative in all respects and does not limit the present disclosure to the above. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present disclosure.

1 Etching chamber, 2 Anode electrode, 3, 3S Cathode electrode, 3d Segmented electrode, 10 Etched substrate, 10S Sensor-embedded substrate, 18 Vpp measurement voltmeter, 19, 19B, 19C Vdc sensor substrate, 20 Resist, 21 Etched material, 70, 70V Learning model creation device, 71, 71V Vdc in-plane distribution creation unit, 72 DC bias in-plane distribution creation unit, 73 Learning model creation unit, 74 Learning model recording unit, 80 Manufacturing content inference device, 81 Inference unit, 82 Processing content determination unit, 100-104 Plasma processing device, 150 Vdc measurement voltmeter, 190 Vdc sensor assembly, 500-504 Plasma processing system, s19 Vdc sensor.

Claims (14)

A plasma processing system having a plasma processing apparatus that generates plasma in a chamber and a data analysis apparatus,
The plasma processing apparatus includes:
a lower electrode provided in the chamber and connected to an AC power source;
an upper electrode provided in the chamber opposite the lower electrode and connected to a reference potential;
a substrate for actual use that is disposed on the lower electrode side of the upper electrode and the lower electrode;
a plurality of potential measurement sensors provided corresponding to a plurality of locations on a formation surface of the actual use substrate, each of the potential measurement sensors being configured to measure a negative potential at a corresponding location on the actual use substrate;
The actual substrate is a substrate to be manufactured,
Measured potential data indicating a plurality of measured potentials measured using the plurality of potential measuring sensors is provided to the data analysis device;
The data analysis device
an in-plane potential distribution data creation unit that obtains substrate-corresponding in-plane potential distribution data that indicates an in-plane distribution of negative potential within the actually used substrate based on the measured potential data;
a data analysis unit that obtains correlation data indicating a correlation between analysis data reflecting the substrate-corresponding in-plane potential distribution data and manufacturing content data indicating manufacturing content for the actually used substrate when the measured potential data is obtained,
Plasma treatment system. 10. The plasma processing system of claim 1,
The plasma processing apparatus includes:
an upper electrode voltmeter for measuring a potential of the upper electrode, wherein upper electrode measurement data indicating the upper electrode potential measured by the upper electrode voltmeter is provided to the data analyzer;
The data analysis unit in the data analysis device
a bias potential distribution creating unit that calculates a plurality of bias potentials that are difference values between the upper electrode potential and the plurality of measured potentials based on the upper electrode measurement data and the substrate-corresponding in-plane potential distribution data, and obtains bias in-plane distribution data indicating the plurality of bias potentials as the analysis data;
a related data creating unit that analyzes a relationship between the bias in-plane distribution data and the manufacturing content data, and obtains the related data indicating the relationship between the bias in-plane distribution data and the manufacturing content data,
Plasma treatment system. 10. The plasma processing system of claim 1 ,
the lower electrode has a plurality of divided electrodes;
The plasma processing apparatus includes:
further comprising a plurality of lower electrode voltmeters provided corresponding to the plurality of divided electrodes, each of the lower electrode voltmeters measuring a voltage of a corresponding divided electrode among the plurality of divided electrodes;
the plurality of potential measuring sensors include the plurality of segmented electrodes;
The substrate to be used is placed on the lower electrode.
Plasma treatment system. 10. The plasma processing system of claim 1 ,
the actual use substrate includes a sensor-embedded substrate incorporating the plurality of potential measurement sensors,
The substrate to be used is placed on the lower electrode.
Plasma treatment system. 10. The plasma processing system of claim 1 ,
The plasma processing apparatus includes:
a sensor substrate having the plurality of potential measuring sensors built in on the lower electrode;
The substrate for actual use is placed on the sensor substrate.
Plasma treatment system. 6. The plasma processing system according to claim 1, further comprising:
The plurality of potential measuring sensors include:
The negative potential detecting section is arranged in correspondence with a negative potential target region in which a large fluctuation in the negative potential of the actual use substrate is predicted based on the shape of the actual use substrate or the density of a resist pattern to be formed above the actual use substrate.
Plasma treatment system. 10. The plasma processing system according to claim 1, 2, 4, or 5,
the plurality of potential measuring sensors are arranged in a matrix;
a first number of scanning lines arranged along one of a row direction and a column direction of the plurality of potential measuring sensors;
a second number of output lines provided along the other of the row direction and the column direction of the plurality of potential measuring sensors;
Each of the plurality of potential measuring sensors includes a charge storage capacitor and
a charge extraction transistor having one electrode connected to the charge storage capacitor, a control electrode connected to a corresponding one of the first number of scanning lines, and a other electrode connected to a corresponding one of the second number of output lines;
Plasma treatment system. 6. The plasma processing system according to claim 1, further comprising:
the actual substrate is a circular wafer in a plan view, the wafer is divided into a plurality of dies,
The maximum square area within the planar structure within the wafer is defined as SX,
When the maximum area of the plurality of dies is DX,
The number N of the plurality of potential measuring sensors is
It is set so as to satisfy the conditional expression {NV≧(SX/DX)×2}.
Plasma treatment system. 6. The plasma processing system according to claim 1, further comprising:
The plasma processing apparatus includes:
a gas supply hole for supplying a manufacturing gas used in manufacturing the substrate into the chamber;
The manufacturing gas includes an etching gas or a film-forming gas.
Plasma treatment system. 6. The plasma processing system according to claim 1, further comprising:
In the data analysis device,
the in-plane potential distribution data creation unit determines whether or not the plurality of measured potentials are abnormal by determining whether or not they are good using a Mahalanobinus-Taguchi method, and derives the substrate-corresponding in-plane potential distribution data by excluding measured potentials determined to be abnormal from among the plurality of measured potentials;
Plasma treatment system. 6. The plasma processing system according to claim 1, further comprising:
the data analysis unit includes a learning model creation unit,
the learning model creation unit performs machine learning using the analysis data as input data and the manufacturing content data as training data, and creates a learned model for estimating the manufacturing content of the actually-used substrate corresponding to the analysis data;
The association data is the trained model.
Plasma treatment system. 10. The plasma processing system of claim 1,
the data analysis unit includes a learning model recording unit,
the data analysis device receives a trained model from an external source, the trained model is obtained by performing machine learning using the analysis data as input data and the manufacturing content data as training data, and is data for estimating manufacturing content of the actually-used substrate corresponding to the analysis data,
the learning model recording unit records the learned model,
The association data is the trained model.
Plasma treatment system. 12. The plasma processing system of claim 11 ,
Further comprising a manufacturing content inference device,
The manufacturing content inference device
an inference unit that receives desired in-plane distribution data including in-plane potential distribution data corresponding to the substrate desired at the time of manufacturing the actually-used substrate, and uses the trained model to estimate, as inference data, data indicating manufacturing details for the actually-used substrate corresponding to the desired in-plane distribution data;
Plasma treatment system. A method for manufacturing a trained model using a plasma processing apparatus that generates plasma in a chamber and a trained model creation apparatus,
The plasma processing apparatus includes:
a lower electrode provided in the chamber and connected to an AC power source;
an upper electrode provided in the chamber opposite the lower electrode and connected to a reference potential;
a substrate for actual use that is disposed on the lower electrode side of the upper electrode and the lower electrode;
a plurality of potential measurement sensors provided corresponding to a plurality of locations on a formation surface of the actual use substrate, each of the potential measurement sensors being configured to measure a negative potential at a corresponding location on the actual use substrate;
The actual substrate is a substrate to be manufactured,
Measured potential data indicating a plurality of measured potentials measured using the plurality of potential measuring sensors is obtained;
The learning model creation device,
(a) obtaining substrate-corresponding in-plane potential distribution data indicating an in-plane distribution of negative potential within the actually used substrate based on the measured potential data;
(b) performing machine learning using analysis data reflecting the substrate-corresponding in-plane potential distribution data as input data and manufacturing content data indicating the manufacturing content of the actually-used substrate when the analysis data was obtained as training data, and creating a trained model for estimating the manufacturing content of the actually-used substrate corresponding to the analysis data;
A method for producing a trained model.