JP7718246B2 - Multilayer wiring board and method of manufacturing the same - Google Patents

Description

The present invention relates to a multilayer wiring board and a method for manufacturing a multilayer wiring board.

In recent years, as electronic devices have become more sophisticated and smaller, there has been a demand for higher density semiconductor modules to be installed in these devices. To address this demand, improvements to the manufacturing processes for forming multilayer wiring and fine wiring have been investigated.
In particular, recent multilayer wiring boards often employ a glass core substrate, with a structure in which a conductor layer, an insulating resin layer, and another conductor layer are laminated in this order on both sides of the substrate.
However, when the glass core substrate has a thickness of about 100 μm, cracks tend to occur during the manufacturing process.

For this reason, in Patent Document 1, a carrier substrate is used as a support to prevent cracking of a thin glass core substrate with through holes in a manufacturing process, and a resin layer having "mold releasability" is used to bond the glass core substrate and the carrier substrate.
Specifically, an acrylic resin that exhibits releasability upon exposure to ultraviolet light has been proposed as the resin layer.

By adopting this type of laminate structure, the risk of cracks or defects occurring in the thin glass core substrate with through holes during the manufacturing process is reduced.

Patent No. 6176253

However, while Patent Document 1 examines the adhesion and releasability at the interface between the glass core substrate and the resin layer, it does not examine the peelability at the side of the laminate between the glass core substrate and the resin layer or the carrier substrate.
In particular, the relationship between the process of forming the multilayer wiring board and the state of the side surface of the laminate or peelability has not been considered at all, which may cause problems when peeling the carrier substrate from the glass core substrate on which the multilayer wiring layer has been formed.
Therefore, an object of the present invention is to provide a technique for stably peeling a carrier substrate from a glass core substrate.

In order to solve the above-mentioned problems, one representative multilayer wiring board of the present invention is a multilayer wiring board in which a glass core substrate is provided above a carrier substrate via a release layer,
When the distance that the side of the carrier substrate is set back toward the center compared to the side of the glass core substrate is G, the thickness of the carrier substrate is Tc, and the thickness of the peeling layer 2 is Ta, G, Tc, and Ta satisfy the following formula (1).
G>0.5×(Ta+Tc)・・・・・・(1)

According to the present invention, it is possible to provide a technique for stably carrying out the process of peeling and removing a carrier substrate from a glass core substrate.
Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments.

FIG. 1 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a conventional multilayer wiring board. FIG. 2 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a conventional multilayer wiring board. FIG. 3 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a conventional multilayer wiring board. FIG. 4 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a conventional multilayer wiring board. FIG. 5 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a conventional multilayer wiring board. FIG. 6 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a multilayer wiring board according to the present invention. FIG. 7 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a multilayer wiring board according to the present invention. FIG. 8 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a multilayer wiring board according to the present invention. FIG. 9 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a multilayer wiring board according to the present invention. FIG. 10 is a diagram illustrating a manufacturing process for peeling off a carrier substrate using a multilayer wiring board according to the present invention. FIG. 11 is a cross-sectional view of a multilayer wiring board for explaining the second embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are designated by the same reference numerals.
In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

In this disclosure, "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in a plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in a plate-shaped member. The "upper surface" and "lower surface" may also be referred to as the "first surface" and "second surface."

Furthermore, the term "side surface" refers to a surface or thickness portion of a layer included in a plate-like member or a layer included in a plate-like member. Furthermore, a portion of a surface and a side surface may be collectively referred to as an "edge portion."
Furthermore, "upward" refers to the direction vertically upward when the plate-like member or layer is placed horizontally. Furthermore, "upward" and its opposite, "downward," are sometimes referred to as the "positive Z-axis direction" and the "negative Z-axis direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

Furthermore, "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction.
Furthermore, "center" means the center of a surface or layer, not the periphery, and "toward the center" means the direction from the periphery of the surface or layer toward the center of the planar shape of the surface or layer.

<Conventional example>
First, problems with the conventional example will be described with reference to FIGS.
FIG. 1 is a diagram illustrating the attachment of a carrier substrate according to a conventional example.
In this disclosure, the term "carrier method" refers to a method for manufacturing a multilayer wiring substrate, which includes the steps of attaching a glass core substrate to a carrier substrate, which serves as a support, forming through holes and multilayer wiring in the glass core substrate, and then peeling off the carrier substrate.

(Glass core substrate 1)
FIG. 1 is a cross-sectional view of a glass core substrate 1 above a carrier substrate 3 with through holes 5 formed therein.
1, a glass core substrate 1 is made of alkali-free glass having a thickness of about 100 μm and has through holes 5. The glass core substrate 1 is also bonded to a carrier substrate 3, which serves as a support, via a release layer 2.
Before proceeding to the next step, the glass core substrate 1 is subjected to ultrasonic cleaning or the like to remove contaminants from its surface.
In the drawings of this disclosure, only one through hole 5 is shown in the glass core substrate 1, but this is for the sake of convenience in order to clearly show the structure of the multilayer wiring board, and does not indicate that there is only one through hole formed in the glass core substrate 1 that is the subject of the present invention. Normally, multiple interposers are formed in one glass core substrate, and therefore many through holes are formed therein.

(Seed Layer Formation)
Next, the step of forming the seed layer will be described with reference to FIG.
Figure 2 is a cross-sectional view of a metal film (in the range of 10 nm or more and 1000 nm or less) that will become a seed layer 4 formed by sputtering or the like on the first surface (the surface opposite to the surface bonded to the carrier substrate 3), which is the upper surface of the glass core substrate 1.
The material of the metal film is, for example, Ti, Cu, electroless Ni, etc., and at least one metal layer selected from these is formed on the side surface of the through hole.

Next, a photoresist 6 pattern is formed on the top surface of the metal film that will become the seed layer 4. For example, a dry photoresist (RD1225) manufactured by Showa Denko Materials Co., Ltd. is used, and a lamination process is performed on the first surface. The desired pattern is then drawn, and the photoresist is developed, thereby exposing the seed layer 4 in the desired pattern.

(Formation of first wiring)
Next, the formation of the first wiring 8 will be described with reference to Fig. 4. Power is supplied to the seed layer 4, and electrolytic copper plating is performed to a thickness of 2 µm or more and 15 µm or less. After plating, the dry film resist that is no longer needed is dissolved and peeled off, and the seed layer 4 is etched away, thereby forming the first wiring 8.

(Formation of Interlayer Insulation Layer, Second Release Layer, and Second Carrier Substrate)
Next, the formation of the interlayer insulating layer, the second release layer, and the second carrier substrate will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing, following Fig. 4, the seed layer 4 is etched away, and then an insulating resin 7 that will become the interlayer insulating layer is formed on the upper surfaces of the glass core substrate and the first wiring, and then a second carrier substrate 10 is bonded using a second release layer 9.
For example, insulating resin (ABF-GXT31, 32.5 μm thick) manufactured by Ajinomoto Fine-Techno Co., Inc. is laminated as the interlayer insulating layer, and processing is performed so that the first wiring 8 is reliably embedded in the insulating resin 7. Lamination is performed using a vacuum press laminating device, and it is desirable to heat the substrate to 100°C and apply a first press of ²⁰ kgf/cm², and then heat the substrate to 100°C and apply a second press of 12 kgf/ ^cm² .
The reason for adhering the second carrier substrate is to make it easier to handle the glass core substrate 1 after the carrier substrate 3 is peeled off.

Therefore, the next step is to peel the carrier substrate 3 from the glass core substrate 1 by utilizing the peel layer 2 .
The peeling step of the carrier substrate 3 can be carried out by a method of reducing the adhesive strength of the adhesive layer of the release layer 2 by irradiating it with a laser or by heating it, or by a method of applying a physical force.
However, as shown in Figures 4 and 5, in the conventional example, the seed layer 4 formed by sputtering and the plating used in forming the first wiring adhere to the side surface of the wiring substrate, making it difficult to stably peel off the carrier substrate 3.

First Embodiment
Next, a first embodiment of the present invention will be described with reference to Figures 6 to 10. The first embodiment differs from the conventional example in that the area of the glass core substrate 1 is larger than the area of the adhesive-attached carrier substrate 3.
6 to 10 are cross-sectional views showing the manufacturing process of a multilayer wiring board when a configuration is adopted in which the area of the glass core substrate 1 is larger than the area of the adhesive-attached carrier substrate 3. In the following description, components that are the same as or equivalent to those in the above-mentioned conventional example are given the same reference numerals, and their description will be simplified or omitted.

7, the carrier substrate 3 has a smaller area than the glass core substrate 1. In other words, if the side surfaces of the glass core substrate 1 and the carrier substrate 3 are sufficiently recessed toward the center compared to the side surfaces of the glass core substrate 1, the seed layer can be formed by sputtering without adhering to the side surfaces of the carrier substrate or the release layer.
Therefore, even in the plating step for forming the first wiring shown in FIG. 9, the plating material does not adhere to the side surfaces of the carrier substrate 3 or the release layer 2.
As a result, in the peeling process of the multilayer wiring board shown in Figure 10, since the seed layer 4 and plating layer are not adhered to the sides of the carrier substrate 3 and the peeling layer 2, the process of peeling and removing the carrier substrate 3 from the glass core substrate 1 can be carried out stably.

Second Embodiment
Next, a second embodiment will be described with reference to FIG.
The second embodiment differs from the first embodiment in that the distance that the side surface of the carrier substrate 3 is set back toward the center compared to the side surface of the glass core substrate 1 is defined in relation to the thickness of the release layer 2 and the thickness of the carrier substrate 3. In the following description, components that are the same as or equivalent to those in the above-mentioned conventional example are given the same reference numerals, and their description will be simplified or omitted.
11 is an explanatory diagram for explaining the second embodiment, in which the distance that the side surface of the carrier substrate 3 is set back toward the center compared to the side surface of the glass core substrate 1 is defined as G. In this case, the thickness of the carrier substrate is defined as Tc, and the thickness of the release layer 2 is defined as Ta.
It should be noted that G means the shortest distance that the side surface of the carrier substrate is set back toward the center compared to the side surface of the glass core substrate.
In the second embodiment, the relationship between G, Tc, and Ta satisfies the following formula (1).
G>0.5×(Ta+Tc)・・・・・・(1)
If the above formula (1) is satisfied, the seed layer 4 can be formed without being attached to the side surfaces of the carrier substrate or the release layer due to the wraparound of the sputtering.

Third Embodiment
Next, a third embodiment will be described. The third embodiment differs from the second embodiment in that the distance G by which the side surface of the carrier substrate is set back toward the center compared to the side surface of the glass core substrate is defined in relation to the area ratio of the carrier substrate 3 to the glass core substrate 1.
In other words, when the carrier substrate and the glass core substrate are made to be approximately similar in shape and are stacked with the center points of their respective faces overlapping, the area of the carrier substrate 3 can be set smaller than the area of the glass core substrate 1, and the side of the carrier substrate can be controlled so that it recedes toward the center compared to the side of the glass core substrate.
In the third embodiment, the area of the carrier substrate 3 is set to 99% or less of the area of the glass core substrate 1 .
In this way, by setting the area ratio when the center points of the surfaces of the carrier substrate 3 and the glass core substrate 1 are overlapped and stacked, the seed layer 4 can be formed without adhering to the sides of the carrier substrate or the release layer due to the sputtering wraparound.

<Fourth embodiment>
Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment in that the distance G, by which the side surface of the carrier substrate 3 is recessed toward the center compared to the side surface of the glass core substrate 1, is specified to be 0.2 mm or more. By specifying the distance G, by which the side surface of the carrier substrate 3 is recessed from the side surface of the glass core substrate 1, as an absolute value, the seed layer 4 can be formed without being deposited on the side surfaces of the carrier substrate 3 or the release layer 2 due to the wraparound of sputtering.

<Example>
Examples according to embodiments of the present invention and comparative examples will be described below with reference to Table 1.
In the examples and comparative examples shown in Table 1, the distance that the side of the carrier substrate 3 is set back toward the center compared to the side of the glass core substrate 1 is varied, a seed layer is formed by sputtering, and then plating is applied, and the stability of peeling in each case is evaluated.
The assumed conditions for sputtering and plating are as follows:
(Sputtering conditions)
An in-line sputtering device manufactured by ULVAC was used. Target: After laminating Ti (adhesion layer) on glass, a Cu film was formed. Vacuum ultimate pressure: 8.0 × 10 ^-4 Pa or less. Film formation pressure: Ar flow rate was adjusted to 0.1 Pa. Power:
Ti: 2.3kW Cu: 3.8kW
Film formation pressure: 0.1 Pa
Conveying speed:
The target film thickness was set to Ti: 150 nm, Cu: 600 nm, and the conveying speed was set (plating conditions).
Uses a batch-type electroplating device. Plating solution: Copper sulfate plating solution (main composition: copper sulfate, sulfuric acid)
Liquid temperature: normal temperature (below 30℃)
The current density ^{was set} to 1 A/dm2, and the plating time was adjusted to achieve a height of 15 μm.

As is clear from Table 1 above, when formula (1) is satisfied in the second embodiment, or when the area of the glass core substrate 1 is 99% or less of the area of the carrier substrate 3 in the third embodiment and the area ratio is 1% or more, it can be seen that good results can be obtained in terms of peel stability.
It can also be seen that in the fourth embodiment, good results can be obtained in terms of peel stability by setting the distance G, by which the side of the carrier substrate is recessed toward the center compared to the side of the glass core substrate, to 0.2 mm or more.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention.
For example, in the first to fourth embodiments, the relationship between the sizes of the glass core substrate 1, the carrier substrate 3, and the release layer 2 has been described.
However, it is also possible to apply the size relationship between the glass core substrate 1, the carrier substrate 3, and the release layer 2 to the glass core substrate 1, the second carrier substrate 10, and the second release layer 9, so that the second carrier substrate can be stably released from the insulating resin 7.

1: Glass core substrate 2: Release layer 3: Carrier substrate 4: Seed layer 5: Through hole 6: Photoresist 7: Insulating resin 8: First wiring 9: Second release layer 10: Second carrier substrate

Claims (4)

A multilayer wiring substrate in which a glass core substrate is provided above a carrier substrate via a release layer,
A multilayer wiring board characterized in that, when the distance that the side of the carrier substrate is set back toward the center compared to the side of the glass core substrate is G, the thickness of the carrier substrate is Tc, and the thickness of the release layer is Ta, G, Tc, and Ta satisfy the following formula (1).
G>0.5×(Ta+Tc)・・・・・・(1) 2. The multilayer wiring board according to claim 1,
A multilayer wiring board characterized in that the carrier substrate and the glass core substrate are approximately similar in shape and are stacked with the center points of their respective faces overlapping, and the area of the carrier substrate is 99% or less of the area of the glass core substrate. 2. The multilayer wiring board according to claim 1,
A multilayer wiring board, characterized in that the side surfaces of the carrier substrate are recessed by 0.2 mm or more toward the center compared to the side surfaces of the glass core substrate. A method for manufacturing a multilayer wiring substrate, comprising providing a glass core substrate above a carrier substrate via a release layer, providing a wiring layer and an insulating resin layer above the glass core substrate, providing a second release layer and a second carrier substrate above the insulating resin layer, and then peeling off the carrier substrate,
a first step of forming the carrier substrate and the glass core substrate such that G, Tc, and Ta satisfy the following formula (1), where G is a distance that a side surface of the carrier substrate is set back toward a center compared to a side surface of the glass core substrate, Tc is a thickness of the carrier substrate , and Ta is a thickness of the release layer;
G>0.5×(Ta+Tc)・・・・・・(1)
a second step of providing a seed layer above the glass core substrate by sputtering after the first step;
a third step of forming wiring by plating after the second step;
A method for manufacturing a multilayer wiring board, comprising a fourth step of peeling the carrier substrate from the glass core substrate after the third step.