JP7722641B2 - Semiconductor wafer manufacturing method - Google Patents

Description

The present invention relates to a semiconductor wafer manufacturing method. Specifically, it relates to a semiconductor wafer manufacturing method that can efficiently process small-diameter semiconductor wafers used in minimal fab systems, producing multiple small-diameter semiconductor wafers from large-diameter semiconductor wafers, such as 6-inch diameter wafers, and can also be used in processing equipment for large-diameter semiconductor wafers.

In recent years, a manufacturing method known as the minimal fab system has been proposed for semiconductor manufacturing fabs. This minimizes fab construction costs, device manufacturing costs, and manufacturing time by standardizing as much of the processing equipment as possible for each manufacturing process, transporting small-diameter wafers in sealed transport containers that hold a single wafer, and maintaining a clean atmosphere in the processing section of the processing equipment and the sealed container (see Patent Document 1).

In this minimal fab system, semiconductor chips are manufactured using small-diameter semiconductor wafers of 0.5 inches (approximately 12.5 mm) rather than large-diameter semiconductor wafers, such as those with a diameter of 300 mm.

Semiconductor wafers include silicon wafers, epitaxial wafers, SOI wafers, and compound semiconductor materials such as GaAs, SiC, GaN, sapphire, diamond, and InP.

In addition, the minimal fab system is expected to enable efficient production of a wide variety of semiconductor chips in small quantities while significantly reducing the initial investment required to build a line.

Methods for producing semiconductor wafers for minimal fab systems include, for example, mechanically punching out large-diameter semiconductor wafers (e.g., silicon wafers) and cutting them out using a laser beam.

For example, in the silicon wafer manufacturing method described in Patent Document 2, a large-diameter silicon wafer is divided using anisotropic plasma etching, thereby simultaneously cutting out multiple small-diameter silicon wafers.

JP 2012-54414 A JP 2016-131178 A

Here, the method for manufacturing small-diameter semiconductor wafers for minimal fab systems involves slicing large-diameter semiconductor wafers, and then performing various processes on each small-diameter semiconductor wafer to ensure they meet product quality.

As a result, after cutting multiple small-diameter semiconductor wafers from a single large-diameter semiconductor wafer, it was inefficient to finish each of them to product quality.

In addition, for large-diameter semiconductor wafers such as those with a diameter of 6 inches, various processing methods and equipment have already been established to achieve product quality, and there is a demand for utilizing equipment designed for manufacturing large-diameter semiconductor wafers in the manufacturing process for small-diameter semiconductor wafers.

The present invention was devised in light of the above points, and aims to provide a semiconductor wafer manufacturing method that can efficiently process small-diameter semiconductor wafers used in minimal fab systems, by producing multiple small-diameter semiconductor wafers from large-diameter semiconductor wafers, such as those with a diameter of 6 inches, and that can also be used in processing equipment for large-diameter semiconductor wafers.

In order to achieve the above object, the semiconductor wafer manufacturing method of the present invention is a semiconductor wafer manufacturing method for manufacturing a second semiconductor wafer having a smaller diameter than the first semiconductor wafer from the first semiconductor wafer, the method comprising: a singulation step of cutting a plurality of the second semiconductor wafers from the first semiconductor wafer, and separating the first semiconductor wafer into a frame-shaped portion obtained by removing the second semiconductor wafer from the first semiconductor wafer, and the second semiconductor wafer; a wafer thickness adjustment step of wet-etching the second semiconductor wafer to adjust the thickness of the second semiconductor wafer; a first mirror polishing step of arranging the second semiconductor wafer in a plurality of hole portions in the frame-shaped portion obtained by removing the second semiconductor wafer, and adhering a predetermined adhesive tape material to a first surface of the frame-shaped portion and the second semiconductor wafer to integrate them, and mirror polishing a second surface of the second semiconductor wafer, which is opposite to the first surface;
and a second mirror polishing step of adhering the specified tape material to the frame-shaped portion and the second surface of the second semiconductor wafer to integrate them, and mirror polishing the first surface of the second semiconductor wafer.

Here, in the singulation process, multiple second semiconductor wafers are cut out from the first semiconductor wafer, and the resulting frame-shaped portion is formed by removing the second semiconductor wafer from the first semiconductor wafer, and the second semiconductor wafer. This allows multiple small-diameter second semiconductor wafers to be produced from a single large-diameter first semiconductor wafer, and a single frame-shaped portion is formed by removing the second semiconductor wafer from the first semiconductor wafer.

In addition, in the wafer thickness adjustment process by etching, wet etching is performed on the second semiconductor wafer to adjust the thickness of the second semiconductor wafer, thereby making it possible to adjust the thickness of the second semiconductor wafer to a thickness that matches the desired product quality.

In addition, in the first mirror polishing process, second semiconductor wafers are placed in the multiple holes in the frame-shaped portion where the second semiconductor wafers were removed, and a specified adhesive tape material is applied to the first surface of the frame-shaped portion and the second semiconductor wafers to integrate them. This allows the single frame-shaped portion and multiple second semiconductor wafers to be combined and joined together with the specified tape, similar to the shape before the multiple second semiconductor wafers were cut out from the first semiconductor wafer. This makes it possible to process the structure in which the frame-shaped portion and multiple second semiconductor wafers are integrated together with the specified tape material.

In addition, in the first mirror polishing process, second semiconductor wafers are placed in the multiple holes in the frame-shaped portion from which the second semiconductor wafers were removed, and a predetermined adhesive tape is adhered to the first surfaces of the frame-shaped portion and the second semiconductor wafers to integrate them. Then, the second surface of the second semiconductor wafer, opposite the first surface, is mirror polished. This allows the second surfaces of the multiple second semiconductor wafers, to which the predetermined tape is not adhered, to be mirror polished collectively. Furthermore, because the external shape of the structure integrating the frame-shaped portion and multiple second semiconductor wafers is the same as that of the large-diameter first semiconductor wafer, transport equipment, mirror polishing processes, and equipment for first semiconductor wafers can be applied. In other words, processing can be performed without using specialized equipment for transporting or processing second semiconductor wafers.

Furthermore, in the second mirror polishing process, a specified tape material is adhered to the frame-shaped portion and the second surface of the second semiconductor wafer to integrate them, thereby creating a structure in which the frame-shaped portion and multiple second semiconductor wafers are integrated with the specified tape material, and in particular, it becomes possible to perform processing on the first surfaces of multiple second semiconductor wafers all at once.

Furthermore, in the second mirror polishing process, a predetermined tape material is adhered to the frame-shaped portion and the second surface of the second semiconductor wafer to integrate them, and the first surface of the second semiconductor wafer is then mirror polished. This allows the first surfaces of the multiple second semiconductor wafers in the structure integrating the frame-shaped portion and multiple second semiconductor wafers to be mirror polished together. Furthermore, because the external shape of the structure integrating the frame-shaped portion and multiple second semiconductor wafers is the same as that of the large-diameter first semiconductor wafer, it is possible to apply transport equipment, mirror polishing processes, and equipment for first semiconductor wafers. In other words, processing can be performed without using specialized equipment for transporting or processing second semiconductor wafers.

Furthermore, if a frame thickness adjustment process is included in which the frame is wet-etched to adjust the thickness of the frame in accordance with the amount of etching of the second semiconductor wafer in the wafer thickness adjustment process by etching, the thickness of the frame can be adjusted to match the thickness of the second semiconductor wafer, the thickness of which has already been adjusted. This allows the integrated structure, in which the frame and multiple second semiconductor wafers have a relatively uniform thickness, to be used in various processing steps from this process onwards. That is, for example, it becomes possible to perform mirror polishing on an integrated structure in which the frame and multiple second semiconductor wafers have a uniform thickness without the need for processing such as grinding.

Furthermore, in the first mirror polishing step, if the frame-shaped portion and the second semiconductor wafer are ground after the frame-shaped portion and the second semiconductor wafer are integrated by adhering a specified tape material and before the second surface is mirror polished, when the frame-shaped portion and the multiple second semiconductor wafers whose thicknesses have already been adjusted are integrated, the frame-shaped portion can be ground to significantly change its thickness. That is, when the multiple second semiconductor wafers are cut out and then wet-etched to adjust their thickness, the frame-shaped portion can be ground directly to reduce its thickness and bring it closer to the thickness of the second semiconductor wafer without adjusting its thickness through wet etching. Furthermore, by further grinding after the frame-shaped portion has reached a thickness approximately equal to that of the second semiconductor wafer, the second semiconductor wafer can be ground together with the frame-shaped portion, thereby making the thickness of the frame-shaped portion and the multiple second semiconductor wafers uniform.

Furthermore, if a first chamfering process of chamfering the second semiconductor wafer is performed after the singulation process, a chamfered portion can be formed on the second semiconductor wafer. Note that the term "chamfered portion" here refers to a processed portion that has a shape similar to that of a rounded corner.

Furthermore, if an edge processing step of mirror-finishing the edge of the second semiconductor wafer is performed after the wafer thickness adjustment step by etching, the unevenness of the edge of the second semiconductor wafer can be reduced, and the smoothness of the edge can be improved. This makes it less likely for particles to adhere to the edge portion of the second semiconductor wafer, and also prevents the edge from hitting a storage case or the like, thereby preventing the generation of particles originating from the case.

Furthermore, after the singulation process, a second chamfering process is provided in which the second semiconductor wafer is chamfered so that the length of the bevel of the peripheral edge of the second surface in the diameter direction of the second semiconductor wafer is longer than the length of the bevel of the peripheral edge of the first surface in the diameter direction. When the length of the bevel of the peripheral edge of the second surface in the diameter direction is to be matched by grinding, the second surface can be ground while forming a chamfer in the second semiconductor wafer. In other words, the length of the bevel of the peripheral edge of the first surface in the diameter direction of the second semiconductor wafer can be matched by grinding.

The semiconductor wafer manufacturing method of the present invention is a method for manufacturing multiple small-diameter semiconductor wafers from large-diameter semiconductor wafers, such as those with a diameter of 6 inches, for use in minimal fab systems. This method allows for efficient processing of small-diameter semiconductor wafers and can also be used in processing equipment for large-diameter semiconductor wafers.

1A and 1B are explanatory diagrams relating to a first embodiment of the present invention, in which FIG. 1A is a schematic plan view showing a state in which a second semiconductor wafer W2 has been cut out from a first semiconductor wafer W1, and FIG. 1B is a partial schematic cross-sectional view showing the flow of each process. 1B is a partial schematic cross-sectional view showing the flow of each step according to the first embodiment of the present invention. 10A and 10B are explanatory diagrams relating to a second embodiment of the present invention, in which FIG. 10A is a schematic plan view showing a state in which a second semiconductor wafer W2 has been cut out from a first semiconductor wafer W1, and FIG. 10B is a partial schematic cross-sectional view showing the flow of each process. 3B, which are partial schematic cross-sectional views showing the flow of each step according to the second embodiment of the present invention. 10A and 10B are partial schematic cross-sectional views showing a step of aligning the length of the bevel on surface A and the length of the bevel on surface B in the diameter direction of the second semiconductor wafer W2 during grinding processing. 1 is a schematic diagram showing the shape of a silicon wafer on which a top-bottom asymmetric bevel is formed on the front and back surfaces. FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a mode for carrying out the present invention (hereinafter referred to as an "embodiment") will be described with reference to the drawings.
In this embodiment, the positions of the A-side and the B-side, which are the front and back sides of the first silicon wafer W1 and the second silicon wafer W2, may be reversed in each drawing, and the "A-side" and the "B-side" are indicated as necessary in each drawing. In the following description, members having the same functions are denoted by the same or related reference numerals, and repeated description thereof will be omitted.

[First embodiment of the present invention]

[1. Singulation process]
In the first embodiment of the present invention, a singulation process is performed in which a first semiconductor wafer W1 having a large diameter is cut into a plurality of second semiconductor wafers W2 having a small diameter (see the diagram of symbol S1 in Figures 1(a) and 1(b)).

Note that Figure 1(a) is a schematic plan view showing the state in which the second semiconductor wafer W2 has been cut out from the first semiconductor wafer W1, and Figure 1(b) is a partial schematic cross-sectional view showing the flow of each process. Also, in Figures 1(a) and 1(b), the large-diameter wafer before being cut out into the second semiconductor wafer W2 corresponds to the first semiconductor wafer W1.

Here, the first semiconductor wafer W1 is an etched wafer with a diameter of 6 inches. Note that in the present invention, the type of large-diameter first semiconductor wafer W1 is not limited to an etched wafer, and lapped wafers, polished wafers, etc. may be used as appropriate. Furthermore, the size of the first semiconductor wafer is not limited to a diameter of 6 inches, and semiconductor wafers of different diameters may be used.

In this singulation process, a laser is used to cut out multiple small-diameter second semiconductor wafers W2 from a large-diameter first semiconductor wafer W1. The second semiconductor wafer W2 then undergoes multiple processes to ultimately become a small-diameter semiconductor wafer measuring 0.5 inches (approximately 12.5 mm).

This singulation process separates one first semiconductor wafer W1 into multiple second semiconductor wafers W2 and a frame-shaped portion 1 formed after the second semiconductor wafers W2 have been cut out (see the diagram marked S1 in Figures 1(a) and 1(b)). During this singulation process, it is also possible to perform laser processing to create a line orientation flat on side B, which will be described later.

The upper frame portion 1 is circular with an outer diameter of 6 inches, and multiple holes 10 are formed in it when the second semiconductor wafer W2 is cut out (see the diagram designated S1 in Figures 1(a) and 1(b)).

Here, in the singulation process, it is not necessary to use a laser to cut out multiple small-diameter second semiconductor wafers W2 from the first semiconductor wafer W1; as long as the second semiconductor wafers W2 can be cut out, the method is not particularly limited.

For example, instead of using a laser, a punching method using mechanical processing or a cutting method using plasma etching can be used. Furthermore, a cutting method developed by the inventors that combines cup wheel cutting and plasma etching (see, for example, JP 2021-57509 A) can also be used.

[2. Chamfering step of second semiconductor wafer W2]
The second semiconductor wafer W2 separated from the first semiconductor wafer W1 is subjected to chamfering. In this process, each second semiconductor wafer W2 is mechanically chamfered using a chamfering grindstone or polishing tape. As a result, bevels (chamfered portions) are formed on the peripheral edges of the front and back surfaces of the second semiconductor wafer W2 (see the diagram of symbol S2 in FIG. 1(b)).

Here, it is not necessary to chamfer the second semiconductor wafer W2. However, by forming bevels on the peripheral edges of the front and back surfaces of the second semiconductor wafer W2, the final small-diameter 0.5-inch semiconductor wafer can be stably placed in a dedicated transport container and problems in each processing section caused by leaving corners can be avoided. For this reason, it is preferable to chamfer the second semiconductor wafer W2.

[3. Thickness adjustment process by wet etching]
Following the chamfering of the second semiconductor wafer W2, the second semiconductor wafer W2 and the frame portion 1 are subjected to a process of adjusting the thickness thereof by wet etching.

First, the second semiconductor wafer W2 is subjected to wet etching to achieve the desired thickness. The second semiconductor wafer W2 is thinned by the wet etching process and processed to a uniform thickness (see the diagram indicated by symbol S3 in Figure 1(b)).

The wet etching conditions can be set as appropriate. The wet etching process can be performed either individually or in batches on the second semiconductor wafers W2. This wet etching process clarifies the amount of etching performed on the second semiconductor wafers W2.

Next, wet etching is performed on the frame-shaped portion 1 to adjust its thickness (not shown). Here, wet etching is performed on the frame-shaped portion 1, with the target etching amount being the same as that used to process the second semiconductor wafer W2. This makes it possible to make the thickness of the frame-shaped portion 1 and the thickness of the multiple second semiconductor wafers W2 approximately the same.

[4. Mirror-finishing process of the edge of the second semiconductor wafer W2]
The second semiconductor wafer W2 that has undergone the thickness adjustment process is subjected to a mirror polishing process for the edge, in which the chamfered end face (edge) of the second semiconductor wafer W2 is mirror polished using an abrasive cloth and an abrasive material (see the diagram of symbol S4 in FIG. 1(b)).

Here, it is not necessary to mirror-polish the edge of the second semiconductor wafer W2. However, it is possible to increase the smoothness of the edge of the second semiconductor wafer W2 and make it less likely for particles to adhere to the edge portion. Furthermore, for small-diameter 0.5-inch semiconductor wafers after processing, the edge comes into contact with the inner wall of a dedicated storage case or transport container, which can prevent the generation of particles originating from the inner wall of the case. For this reason, it is preferable to mirror-polish the edge of the second semiconductor wafer W2.

[5. Attaching tape to side B]
Next, a plurality of second semiconductor wafers W2 are placed inside the holes 10 of the frame-shaped portion 1, and in this state, a fixing tape 2 is attached to one of the front and back surfaces of the frame-shaped portion 1 and the second semiconductor wafers W2, thereby integrating the frame-shaped portion 1 and the plurality of second semiconductor wafers W2 (see the diagram of symbol S5 in Figure 1(b)).

For convenience, the surfaces of the frame portion 1 and the second semiconductor wafer W2 to which the fixing tape 2 is attached will be referred to as "side B," and the surfaces to which the fixing tape 2 is not attached will be referred to as "side A." Furthermore, in subsequent processes, the surfaces to which the fixing tape 2 is attached in this process will be referred to as "side B," and the surfaces to which the fixing tape 2 is not attached in this process will be referred to as "side A."

The frame 1 and second semiconductor wafer W2, each with this fixing tape 2 attached to its respective B side, are supported on the B side by the fixing tape 2, allowing processing to be performed integrally on the A side, the side opposite to the B side. In other words, multiple second semiconductor wafers W2 can be processed collectively.

This fixing tape 2 is a single piece of tape that is large enough to cover the outer shape of the frame-shaped part 1, i.e., the entire surface of a 6-inch diameter wafer.

The fixing tape 2 may be, for example, a backgrind tape used to fix a semiconductor wafer during a grinding process and protect the surface opposite to the surface to be ground.

Here, the type of fixing tape 2 is not limited to backgrind tape, and any tape that can fix the frame portion 1 and the second semiconductor wafer W2 in an integrated state and has physical properties that can withstand polishing processes, etc., can be used as appropriate.

[6. A-side polishing]
Next, the frame-shaped part 1 and the second semiconductor wafer W2, which have been integrated with the fixing tape 2, are subjected to mirror polishing on their sides A. Here, the sides A of the frame-shaped part 1 and the second semiconductor wafer W2 are faced downward, and are brought into contact with a polishing device (not shown) placed below the frame-shaped part 1 and the second semiconductor wafer W2, thereby performing mirror polishing (see the diagram indicated by reference symbol S6 in FIG. 2). The polishing device may be a polishing device for semiconductor wafers with a diameter of 6 inches.

As a result, the frame 1 and side A of the second semiconductor wafer W2 are mirror-finished, resulting in an extremely smooth mirror-finished surface. Furthermore, by supporting side B with the fixing tape 2, the sides A of multiple second semiconductor wafers W2 can be mirror-finished all at once.

[7. Attaching A-side tape]
Next, fixing tape 2 is attached to the mirror-finished frame portion 1 and surface A of the second semiconductor wafer W2 so that surface A is also supported (see the drawing of reference numeral S7 in FIG. 2).

Then, the fixing tape 2 attached to the frame-shaped portion 1 and the second semiconductor wafer W2 on side B is peeled off, exposing side B while the frame-shaped portion 1 and the second semiconductor wafer W2 remain integrated by the fixing tape 2 attached to side A (see the diagram indicated by symbol S8 in Figure 2).

[8. B-side polishing]
Next, the frame-shaped part 1 and the second semiconductor wafer W2, which are integrated with the fixing tape 2 attached to the side A, are mirror-polished on the side B. Here, the side B of the frame-shaped part 1 and the second semiconductor wafer W2 are faced downward, and the side B of the frame-shaped part 1 and the second semiconductor wafer W2 is brought into contact with a polishing device (not shown) placed below, and mirror-polished (see the diagram of reference symbol S9 in FIG. 2). The polishing device may be a polishing device for semiconductor wafers with a diameter of 6 inches.

As a result, the frame 1 and side B of the second semiconductor wafer W2 are mirror-finished, resulting in an extremely smooth mirror-finished surface. Furthermore, by supporting side A with the fixing tape 2, the B sides of multiple second semiconductor wafers W2 can be mirror-finished all at once.

By following the above process, multiple second semiconductor wafers W2 are cut from a large-diameter first semiconductor wafer W1, and the thickness of these wafers is adjusted to produce small-diameter 0.5-inch semiconductor wafers with mirror-finished surfaces A and B.

In this first embodiment of the present invention, by placing a second semiconductor wafer W2 inside the hole 10 of the frame 1 and attaching a fixing tape 2 to one side, multiple second semiconductor wafers W2 can be mirror-finished all at once, thereby improving manufacturing efficiency.

Furthermore, in the first embodiment of the present invention, after the B side of the multiple second semiconductor wafers W2 has been mirror-finished, they can be transported with the fixing tape 2 still attached, i.e., with the frame portion 1 and the multiple second semiconductor wafers W2 integrated together, using a transport device for 6-inch diameter semiconductor wafers, etc.

This means that existing transport equipment for 6-inch diameter semiconductor wafers can be used. Furthermore, when performing mirror polishing, existing polishing equipment for 6-inch diameter semiconductor wafers can also be used.

In this way, in the first embodiment of the present invention, existing equipment used in the manufacturing process of the large-diameter first semiconductor wafer W1, which is the source of the frame-shaped portion 1, can be applied to the processing of multiple second semiconductor wafers W2.

Next, we will explain the second embodiment of the present invention. Below, we will omit explanations of content that overlaps with the first embodiment of the present invention described above.

[Second embodiment of the present invention]

[1. Singulation process]
In the second embodiment of the present invention, similarly to the first embodiment of the present invention, a singulation step is performed in which a first semiconductor wafer W1 having a large diameter is cut into a plurality of second semiconductor wafers W2 having a small diameter (see the diagrams indicated by reference symbol S1 in FIGS. 3( a) and 3(b)). The first semiconductor wafer W1 is an etched wafer having a diameter of 6 inches.

Furthermore, during this singulation process, it is also possible to perform laser processing to create a line orientation flat on surface B, as described below.

[2. Chamfering step of second semiconductor wafer W2]
As in the first embodiment of the present invention, the second semiconductor wafer W2 separated from the first semiconductor wafer W1 is subjected to chamfering, thereby forming bevels (chamfered portions) on the peripheral edges of the front and back surfaces of the second semiconductor wafer W2 (see the diagram of symbol S2 in FIG. 3(b)).

In addition, in the second embodiment of the present invention, the bevel may be formed so that the length of the bevel 20 (the length along the diameter of the second semiconductor wafer W2) of the peripheral edge of the second semiconductor wafer W2 on the side A (the side to which the fixing tape 2 is not attached in the step in which the fixing tape 2 is first used) which is ground in a subsequent grinding step is longer than the length of the bevel 21 (the length along the diameter of the second semiconductor wafer W2; the portion indicated by the symbol X in Figure 5(a)) on the side B (the side to which the fixing tape 2 is attached in the step in which the fixing tape 2 is first used) of the second semiconductor wafer W2 (see Figure 5(a)).

In this way, in the chamfering process, the length of the bevel 20 on the peripheral edge of the second semiconductor wafer W2 on the surface A side along the diameter direction of the second semiconductor wafer W2 is formed longer than the length of the bevel 21 on the surface B side. This makes it easier to grind the surface A side in the subsequent grinding process (grinding to the position of the dotted line indicated by symbol Y in Figure 5(a)) and to make the length of the bevel 21 on the peripheral edge of the surface A side and the length of the bevel 22 on the peripheral edge of the surface B side the same after the grinding process (see Figure 5(b)).

By adopting this configuration, the length of the flat portion 23 on side A and the length of the flat portion 24 on side B in the diameter direction of the second semiconductor wafer W2 are different before the grinding process. After the grinding process, a second semiconductor wafer W2 can be formed in which the length of the flat portion 25 on side A and the length of the flat portion 24 on side B are the same.

Here, it is not necessary to chamfer the second semiconductor wafer W2. However, by forming bevels on the peripheral edges of the front and back surfaces of the second semiconductor wafer W2, the final small-diameter 0.5-inch semiconductor wafer can be stably placed in a dedicated transport container and problems in each processing section caused by leaving corners can be avoided. For this reason, it is preferable to chamfer the second semiconductor wafer W2.

In addition, as shown in Figure 6, the present invention also makes it possible to form bevels 90, 91 of different shapes on the peripheral edges of the front and back surfaces of the second silicon wafer W2, thereby producing a second silicon wafer W2 with an asymmetrical bevel formed in the top and bottom.

[3. Thickness adjustment process by wet etching]
Following the chamfering of the second semiconductor wafer W2, the second semiconductor wafer W2 is subjected to a process of adjusting its thickness by wet etching. In the second embodiment of the present invention, the thickness of the frame portion 1 is not adjusted by wet etching.

Here, the second semiconductor wafer W2 is subjected to wet etching to achieve the desired thickness. The second semiconductor wafer W2 is thinned by the wet etching process and processed to a uniform thickness (see the diagram indicated by symbol S3 in Figure 3(b)).

[4. Mirror-finishing process of the edge of the second semiconductor wafer W2]
The second semiconductor wafer W2 is subjected to a mirror-finishing process for its edge in the same manner as in the first embodiment of the present invention. Here, a polishing cloth and a polishing material are used to mirror-polish the chamfered end face (edge) of the second semiconductor wafer W2 (see the diagram of symbol S4 in FIG. 3(b)).

[5. Attaching tape to side B]
Next, a plurality of second semiconductor wafers W2 are placed inside the holes 10 of the frame-shaped portion 1, and in this state, a fixing tape 2 is attached to one of the front and back surfaces of the frame-shaped portion 1 and the second semiconductor wafers W2, thereby integrating the frame-shaped portion 1 and the plurality of second semiconductor wafers W2 (see the diagram of symbol S5 in Figure 3(b)).

In this case, in the previous step, only the second semiconductor wafer W2 was subjected to a process of adjusting its thickness by wet etching, so the thickness of the frame portion 1 is greater in the thickness direction than the thickness of the multiple second semiconductor wafers W2 (see the diagram indicated by symbol S5 in Figure 3(b)).

Furthermore, if the chamfering process for the second semiconductor wafer W2 is performed so that the length of the bevel on the peripheral edge on the side A is longer than the length of the bevel on the side B, the side B sides of the multiple second semiconductor wafers W2 are attached to the fixing tape 2.

The frame part 1 and second semiconductor wafer W2, each with this fixing tape 2 attached to their respective B sides, are supported on the B side by the fixing tape 2, making it possible to process the A side, the side opposite to the B side, as a single unit.

[6. A-side grinding]
Next, the frame-shaped part 1 and the second semiconductor wafer W2, which have been integrated with the fixing tape 2, are subjected to a grinding process on their side A. Here, the side A of the frame-shaped part 1 and the second semiconductor wafer W2 face upward, and a grinding machine (not shown) placed above them is brought into contact with the side A of the frame-shaped part 1 and the second semiconductor wafer W2 to perform surface grinding (see the diagram of reference symbol S6 in FIG. 4). The grinding machine can be a surface grinding plate for semiconductor wafers with a diameter of 6 inches.

In this surface grinding, the thicker side A of the frame-shaped portion 1 is ground first. The surface grinder then reaches the height position of side A of the second semiconductor wafer W2 (the height of the dotted line indicated by symbol Y in the diagram of symbol S6 in Figure 4), and both sides A of the frame-shaped portion 1 and the second semiconductor wafer W2 are ground together, making the thicknesses of the frame-shaped portion 1 and the second semiconductor wafer W2 uniform and enabling the thicknesses of multiple second semiconductor wafers W2 to be made uniform.

Furthermore, if the chamfering process for the second semiconductor wafer W2 is performed so that the length of the bevel on the peripheral edge on the surface A side is longer than the length of the bevel on the surface B side, the surface A of the second semiconductor wafer W2 is ground, and the length of the bevel on the peripheral edge on the surface A side can be shortened by grinding. Furthermore, by adjusting the grinding conditions, the length of the bevel on the peripheral edge on the surface A side can be made to match the length of the bevel on the peripheral edge on the surface B side.

In this way, the grinding process can match the lengths of the bevels on the front and back surfaces of the second semiconductor wafer W2, forming a bevel that is approximately symmetrical in the thickness direction.

[7. A-side polishing]
Next, as in the first embodiment of the present invention, mirror polishing is performed on the side A of the frame part 1 and the second semiconductor wafer W2 that have been integrated with the fixing tape 2. Here, the side A of the frame part 1 and the second semiconductor wafer W2 are faced downward, and the side A of the frame part 1 and the second semiconductor wafer W2 are brought into contact with a polishing device (not shown) disposed below the frame part 1 and the second semiconductor wafer W2, and mirror polishing is performed (see the diagram of symbol S7 in FIG. 4).

[8. Attaching A-side tape]
Next, as in the first embodiment of the present invention, fixing tape 2 is attached to the mirror-finished frame portion 1 and surface A of the second semiconductor wafer W2 so as to support the surface A as well (see the diagram of symbol S8 in FIG. 4).

Then, the fixing tape 2 attached to the frame-shaped portion 1 and the second semiconductor wafer W2 on side B is peeled off, exposing side B while the frame-shaped portion 1 and the second semiconductor wafer W2 remain integrated by the fixing tape 2 attached to side A (see the diagram indicated by reference numeral S9 in Figure 2).

[9. B-side polishing]
Next, the frame-shaped part 1 and the second semiconductor wafer W2, which are integrated with the fixing tape 2 attached to the surface A, are subjected to mirror polishing on the surface B. Here, the surface B of the frame-shaped part 1 and the second semiconductor wafer W2 is faced downward, and the surface B of the frame-shaped part 1 and the second semiconductor wafer W2 is brought into contact with a polishing device (not shown) placed below the surface A, and mirror polished (see the diagram of symbol S9 in FIG. 2).

In the second embodiment of the present invention, following the above process, multiple second semiconductor wafers W2 are cut out from a large-diameter first semiconductor wafer W1, and the thickness of these wafers is adjusted to produce small-diameter 0.5-inch semiconductor wafers with mirror-finished surfaces A and B.

In this second embodiment of the present invention, thickness adjustment is performed on only the second semiconductor wafer W2 by wet etching, and then a grinding process is performed to make the frame-shaped portion 1 and the second semiconductor wafer W2 uniform in thickness, and also to make the thicknesses of multiple second semiconductor wafers W2 uniform. Furthermore, by using the fixing tape 2, the frame-shaped portion 1 and multiple second semiconductor wafers W2 can be processed together efficiently.

In addition, in the second embodiment of the present invention, by placing a second semiconductor wafer W2 inside the hole 10 of the frame portion 1 and attaching a fixing tape 2 to one side, multiple second semiconductor wafers W2 can be mirror-finished all at once, thereby improving manufacturing efficiency.

Furthermore, in the second embodiment of the present invention, after the B side of the multiple second semiconductor wafers W2 has been mirror-finished, they can be transported with the fixing tape 2 still attached, i.e., with the frame 1 and the multiple second semiconductor wafers W2 integrated together, using a transport device for 6-inch diameter semiconductor wafers, etc.

This means that existing transport equipment for 6-inch diameter semiconductor wafers can be used. Furthermore, when performing mirror polishing, existing polishing equipment for 6-inch diameter semiconductor wafers can also be used.

In this way, in the second embodiment of the present invention, existing equipment used in the manufacturing process of the large-diameter first semiconductor wafer W1, which is the source of the frame-shaped portion 1, can be applied to the processing of multiple second semiconductor wafers W2.

As described above, the semiconductor wafer manufacturing method according to the present invention is a method for manufacturing multiple small-diameter semiconductor wafers from large-diameter semiconductor wafers, such as those with a diameter of 6 inches, for use in minimal fab systems. This method can efficiently process small-diameter semiconductor wafers and can also be used in processing equipment for large-diameter semiconductor wafers.

The terms and expressions used in this specification and claims are for explanatory purposes only and are not intended to be limiting in any way. They are not intended to exclude terms and expressions equivalent to the features described in this specification and claims, or portions thereof. It goes without saying that various modifications are possible within the scope of the technical concept of the present invention.

W1: First semiconductor wafer W2: Second semiconductor wafer 1: Frame portion 10: Hole portion 2: Fixing tape

Claims (6)

A method for manufacturing a semiconductor wafer, comprising the steps of: manufacturing a second semiconductor wafer from a first semiconductor wafer; and the second semiconductor wafer has a smaller diameter than the first semiconductor wafer;
a singulation step of cutting the first semiconductor wafer into a plurality of second semiconductor wafers and separating the first semiconductor wafer into a frame-shaped portion obtained by removing the second semiconductor wafer from the first semiconductor wafer and the second semiconductor wafer;
a wafer thickness adjusting step of performing wet etching on the second semiconductor wafer to adjust the thickness of the second semiconductor wafer;
a first mirror polishing step of placing the second semiconductor wafer in a plurality of holes in the frame-shaped portion from which the second semiconductor wafer was removed, adhering a predetermined adhesive tape material to a first surface of the frame-shaped portion and the second semiconductor wafer to integrate them, and mirror polishing a second surface of the second semiconductor wafer opposite to the first surface;
a second mirror polishing step of adhering the predetermined tape material to the frame-shaped portion and the second surface of the second semiconductor wafer to integrate them, and mirror polishing the first surface of the second semiconductor wafer. 2. The method for manufacturing a semiconductor wafer according to claim 1, further comprising a frame-shaped portion thickness adjustment step of performing wet etching on the frame-shaped portion to adjust the thickness of the frame-shaped portion in accordance with an etching amount of the second semiconductor wafer in the wafer thickness adjustment step by etching. 2. The method for manufacturing a semiconductor wafer according to claim 1, wherein in the first mirror polishing step, after the predetermined tape material is adhered to integrate the frame-shaped portion and the second semiconductor wafer, and before the second surface is mirror polished, the frame-shaped portion and the second surface of the second semiconductor wafer are ground. The method for producing a semiconductor wafer according to claim 1 , further comprising a first chamfering step of chamfering the second semiconductor wafer after the singulation step. 5. The method for producing a semiconductor wafer according to claim 1, further comprising, after the wafer thickness adjustment step by etching, an edge processing step of mirror-finishing an edge of the second semiconductor wafer. a second chamfering step of chamfering the second semiconductor wafer after the singulation step so that the length of the bevel of the peripheral edge of the second surface in the diameter direction of the second semiconductor wafer is longer than the length of the bevel of the peripheral edge of the first surface in the diameter direction;
4. The method for manufacturing a semiconductor wafer according to claim 3, wherein the grinding is performed to match the length of the bevel of the peripheral edge of the second surface in the diameter direction with the length of the bevel of the peripheral edge of the first surface in the same diameter direction.