JP7724679B2 - Delay pulse generation circuit - Google Patents

Description

The present invention relates to a delay pulse generation circuit.

Patent Document 1 describes that a delay-locked loop (DLL) is incorporated into a signal path and the output of a driver is fed back, thereby adjusting the signal delay by the DLL.
Patent Document 1: International Publication No. 2011-034861

A first aspect of the present invention provides a delay pulse generation circuit that receives a clock signal and outputs a delayed pulse signal. The delay pulse generation circuit may include a delay circuit that receives a clock signal and a delayed pulse signal and generates a delayed signal by delaying the clock signal based on a first control signal that changes to one logic when the clock signal changes to a first logic and to the other logic when the delayed pulse signal changes to the first logic, and a second control signal that changes to one logic when the delayed pulse signal changes to the first logic and to the other logic when the delayed pulse signal changes to the second logic, or based on a first control signal that changes to one logic when the clock signal changes to the first logic and to the other logic the next time the clock signal changes or the delayed pulse signal changes to the first logic, whichever occurs first, and a second control signal that changes to one logic when the clock signal next changes or the delayed pulse signal changes to the first logic, whichever occurs later, and to the other logic the next time the clock signal next changes or the delayed pulse signal changes to the first logic, whichever occurs later. The delay pulse generation circuit may include a driver that outputs a delay pulse signal according to the delay signal.

The delay circuit may include a charge pump that outputs a current in response to the first control signal and the second control signal. The delay circuit may include a delay unit that outputs a delayed signal obtained by delaying the clock signal in response to the current output by the charge pump.

The delay circuit may have a capacitor connected between a node to which the output of the charge pump is connected and a reference potential. The charge pump may change the direction of current in response to a first control signal and a second control signal to charge or discharge the capacitor.

The delay circuit may have a signal generating unit that generates a first pulse signal that rises when the clock signal changes, and a second pulse signal that rises when the delayed pulse signal changes. The delay circuit may have a latch unit that outputs one of a first control signal and a second control signal in response to the first pulse signal and the second pulse signal. The charge pump may receive one of the first control signal and the second control signal output from the latch unit, receive the clock signal as the other of the first control signal and the second control signal, and output a current in response to the first control signal and the second control signal.

The signal generating unit may have a first pulse generating unit including a first pulse generating delay unit to which a clock signal is input, and a first pulse generating AND unit that receives the clock signal as input to one input, a signal obtained by delaying the clock signal by the first pulse generating delay unit as input to the other input, and outputs a first pulse signal. The signal generating unit may have a second pulse generating unit including a second pulse generating delay unit to which a delayed pulse signal is input, and a second pulse generating AND unit that receives the delayed pulse signal as input to one input, a signal obtained by delaying the delayed pulse signal by the second pulse generating delay unit as input to the other input, and outputs a second pulse signal.

The latch unit may perform SR latching in response to the first pulse signal and the second pulse signal, and output one of the first control signal and the second control signal.

The delay circuit may receive a delayed pulse signal output from or input to the driver.

Note that the above summary of the invention does not list all of the necessary features of the present invention. Subcombinations of these features may also constitute inventions.

1 shows an example of the configuration of a delay pulse generating circuit 10 according to this embodiment. 1 shows a first configuration example of the delay circuit 300. 10 shows a more detailed configuration example of the signal generating unit 310. 10 shows a more detailed configuration example of the charge pump 320. 10 shows an example of the configuration of the delay unit 340. 2 shows an example of the configuration of the pulse width adjustment unit 400. 1 shows an example of a timing chart of the delay circuit 300 of the present embodiment. 10 shows another example of a timing chart of the delay circuit 300 of the present embodiment. A second configuration example of the delay circuit 300 is shown. 10 shows an example of a timing chart of the delay circuit 300 of the second configuration example. 1 shows an example of a timing chart of the delay circuit 300 of the delay pulse generating circuit 10 of the present embodiment. 10 shows another example of a timing chart of the delay circuit 300 of the delay pulse generating circuit 10 of the present embodiment. 10 shows another example of the signal generating section 310 of the delay circuit 300. 10 shows an example of a timing chart of another example of the signal generating unit 310. 2 shows a delay circuit 300 as a comparative example. 10 shows a timing chart of a delay circuit 300 of a comparative example.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

Figure 1 shows an example configuration of a delay pulse generation circuit 10 according to this embodiment. The delay pulse generation circuit 10 receives a clock signal CKREF, delays the clock signal CKREF, and generates and outputs a delay pulse signal OUT. The delay pulse generation circuit 10 can be used as a current driver for outputting optical pulses included in systems such as ToF (Time of Flight), which measure the time it takes for light to be emitted and reflected back. The delay pulse generation circuit 10 includes an input buffer 200, a dummy input buffer 600, a delay circuit 300, a pulse width adjustment unit 400, and a driver 500.

The input buffer 200 has an input connected to the input terminal 100 and an output connected to the delay circuit 300. The input buffer 200 outputs the clock signal CKREF input to the input terminal 100 to the delay circuit 300. The input of the dummy input buffer 600 is connected to the output of the driver 500 and an output connected to the delay circuit 300. The dummy input buffer 600 outputs the delayed pulse signal output from the output terminal 700 of the delay pulse generation circuit 10 to the delay circuit 300. The dummy input buffer 600 may be arranged to adjust the phase of the signal to the input buffer 200, etc.

Delay circuit 300 delays the input clock signal CKREF and outputs a delayed signal. One example of delay circuit 300 is a delay-locked loop (DLL) circuit. Delay circuit 300 generates a delayed signal by delaying clock signal CKREF based on a first control signal and a second control signal. A more detailed configuration is described in Figures 2 to 5.

The pulse width adjustment unit 400 is connected to the driver 500, converts the delay signal from the delay circuit 300 to a predetermined pulse width, and generates and outputs a delayed pulse signal OUT corresponding to the delay signal. A more detailed configuration is described in Figure 6.

The driver 500 is connected to the output terminal 700 and the dummy input buffer 600, and receives and outputs the delayed pulse signal OUT from the pulse width adjustment unit 400.

Figure 2 shows a first configuration example of the delay circuit 300. In Figure 2, the input terminal 100 and output terminal 700 are shown for illustrative purposes, and the configuration of the delay pulse generation circuit 10 other than the delay circuit 300, input terminal 100, and output terminal 700 is omitted. The delay circuit 300 has a signal generation unit 310, a charge pump 320, a capacitor 330, and a delay unit 340.

The signal generating unit 310 has an input connected to the input terminal 100 and the output of the driver 500, and an output connected to the charge pump 320. The signal generating unit 310 generates a first control signal CKUP and a second control signal CKDN according to the input clock signal CKREF and delayed pulse signal OUT, and outputs these to the charge pump 320. The signal generating unit 310 has a first pulse generating unit 312, a second pulse generating unit 314, and a latch unit 316.

The first pulse generating unit 312 has an input connected to the input terminal 100 and an output connected to the latch unit 316. The first pulse generating unit 312 generates a first pulse signal that rises when the input clock signal CKREF changes. The first pulse generating unit 312 may output the first pulse signal to one input of the latch unit 316.

The second pulse generating unit 314 has an input connected to the output terminal 700 and an output connected to the latch unit 316. The second pulse generating unit 314 generates a second pulse signal that rises when the delayed pulse signal OUT changes. The second pulse generating unit 314 may output the second pulse signal to the other input of the latch unit 316.

The output of the latch unit 316 is connected to the charge pump 320. The latch unit 316 outputs one of the first control signal CKUP and the second control signal CKDN in response to the input first pulse signal and second pulse signal. The latch unit 316 may perform SR latching in response to the first pulse signal and the second pulse signal, and output the first control signal CKUP and the second control signal CKDN. In this embodiment, the latch unit 316 outputs the first control signal CKUP, as an example.

The output of the charge pump 320 is connected to a node between the capacitor 330 and the delay unit 340. The charge pump 320 outputs a current I_UP/I_DN in response to a first control signal CKUP and a second control signal CKDN. The charge pump 320 may change the direction of the current I_UP/I_DN in response to the first control signal CKUP and the second control signal CKDN to charge or discharge the capacitor 330.

Capacitor 330 is connected between a node to which the output of charge pump 320 is connected and a reference potential (for example, ground potential). Capacitor 330 may be charged or discharged according to the current I_UP/I_DN from charge pump 320. Capacitor 330 may filter the voltage VCAP at the node to which the output of charge pump 320 is connected.

The delay unit 340 is connected to the input terminal 100 and the output terminal 700, and outputs a delayed signal obtained by delaying the clock signal CKREF according to the current I_UP/I_DN output by the charge pump 320 to the output terminal 700.

Figure 3 shows a more detailed example configuration of the signal generation unit 310. The signal generation unit 310 can pulse the edges at which the input clock signal CKREF changes and the edges at which the delayed pulse signal OUT changes, and input these to the latch unit 316, which can then generate the first control signal CKUP for the charge pump 320.

The first pulse generating unit 312 has multiple buffers and a logical product unit. The multiple buffers are connected in series between the input terminal 100 and the logical product unit. The multiple buffers output a signal CKREFd, which is a delayed version of the clock signal CKREF, to one input of the logical product unit. The multiple buffers delay the clock signal CKREF within a predetermined range, thereby generating a first pulse signal Set_N with a pulse width within the range in which the subsequent latch unit 316 can operate. The logical product unit receives the delayed clock signal CKREF from the multiple buffers at one input and the clock signal CKREF at the other input, and outputs the first pulse signal Set_N to the latch unit 316 by logical product. The logical product unit may be a NAND circuit.

The second pulse generating unit 314 has multiple buffers and a logical product unit. The multiple buffers are connected in series between the output of the driver 500 and the logical product unit. The multiple buffers output a signal OUTd, which is a delayed version of the delayed pulse signal OUT, to one input of the logical product unit. The multiple buffers delay the delayed pulse signal OUT within a predetermined range, thereby generating a second pulse signal Reset_N with a pulse width within a range in which the downstream latch unit 316 can operate. The logical product unit receives the delayed pulse signal OUT, which has been delayed by the multiple buffers, at one input, and the delayed pulse signal OUT at the other input, and outputs the second pulse signal Reset_N to the latch unit 316 through a logical product. The logical product unit may be a NAND circuit.

As an example, latch unit 316 is a negative logic SR latch circuit that combines two NAND circuits. When the first pulse signal Set_N and the second pulse signal Reset_N input to latch unit 316 are both high, cross-feedback maintains the previous state of output Q. If the first pulse signal Set_N goes low while the second pulse signal Reset_N is high, output Q goes high, and remains high even when the first pulse signal Set_N returns to high. Similarly, if the first pulse signal Reset_N goes low while the first pulse signal Set_N is high, output Q goes low, and remains low even after the second pulse signal Reset_N returns to high. With this configuration, the signal generating unit 310 can, for example, output the first control signal CKUP high from the first edge of the clock signal CKREF to the first edge of the delayed pulse signal OUT, regardless of the duty cycle of the input signal.

Figure 4 shows a more detailed configuration example of the charge pump 320. The charge pump 320 may receive one of the first control signal CKUP and the second control signal CKDN output from the latch unit 316, and the clock signal CKREF as the other of the first control signal CKUP and the second control signal CKDN, and output a current I_UP/I_DN in response to the first control signal CKUP and the second control signal CKDN. The charge pump 320 includes an inverter 1000, a first current source 1002, a second current source 1004, a first transistor 1010, and a second transistor 1020.

Inverter 1000 may be connected between terminal UP, which receives first control signal CKUP, and first transistor 1010, and may invert the logic level of the input first control signal CKUP and output it. First current source 1002 may be connected to first transistor 1010 and may pass current I_UP to first transistor 1010, the magnitude of which corresponds to signal CNT_IUP. First transistor 1010 is connected to the output, and controls the flow of current I_UP toward the output in response to the first control signal CKUP flowing from inverter 1000 to its control terminal (gate terminal).

The second current source 1004 may be connected to the second transistor 1020 and may cause the second transistor 1020 to flow a current I_DN whose magnitude corresponds to the signal CNT_IDN. The second transistor 1020 is connected to the output and controls the flow of the current I_DN from the output to the second current source 1004 in accordance with a second control signal flowing from terminal DN to the control terminal. With this configuration, the charge pump 320 may, for example, output the current I_UP when only the first control signal CKUP is high, sink the current I_DN when only the second control signal CKDN is high, and output the current difference (I_UP - I_DN) when both the first control signal CKUP and the second control signal CKDN are high.

The magnitude of the current I_UP of the first current source 1002 can be controlled by the signal CNT_IUP, and the magnitude of the current I_DN of the second current source 1004 can be controlled by the signal CNT_IDN. As a result, the charge pump 320 controls the ratio of the current I_UP of the first current source 1002 to the current I_DN of the second current source 1004 according to the input conditions of the clock signal CKREF and the delay time required for the delayed pulse signal OUT.

Figure 5 shows an example configuration of the delay unit 340. The delay unit 340 includes a third transistor 1030, a fourth transistor 1040, a resistor 1050, a fifth transistor 1060, a sixth transistor 1070, and multiple inverters 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150. The third transistor 1030 is connected between a power supply and the fourth transistor 1040, and its control terminal is connected to the control terminal of the fifth transistor 1060 and a node between the third transistor 1030 and the fourth transistor 1040. The fourth transistor 1040 is connected to one end of the resistor 1050, and its control terminal is connected to the capacitor 330. The other end of the resistor 1050 is connected to a reference potential. The fifth transistor 1060 is connected between a power supply and one end of the sixth transistor 1070. The other end of the sixth transistor 1070 is connected to a reference potential, and the control terminal is connected to a node between one end of the fifth transistor 1060 and the sixth transistor 1070. Multiple inverters 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150 are each connected between the node between one end of the fifth transistor 1060 and the sixth transistor 1070 and the reference potential, and are connected in multiple stages in series between the input terminal 100 and the output terminal 700.

Delay unit 340 receives voltage VCAP, which is charged/discharged across capacitor 330, via fourth transistor 1040 and resistor 1050 and generates a current. Delay unit 340 supplies the generated current to multiple inverters 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150 via a current mirror formed by third transistor 1030 and fifth transistor 1060. The larger the supplied current, the smaller the delay of multiple inverters 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150; and the smaller the supplied current, the larger the delay of multiple inverters 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150.

In this embodiment, eight inverter stages 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150 are used, but the inverters in the delay unit 340 may have nine or more or fewer than eight stages depending on the circuit application. It is also possible to output signals from each inverter 1080, 1090, 1100, 1110, 1120, 1130, 1140, and 1150 to generate a multi-phase clock.

Figure 6 shows an example configuration of the pulse width adjustment unit 400. The pulse width adjustment unit 400 has a pulse width adjustment delay unit 401 and a pulse width adjustment logical product unit 402. The pulse width adjustment delay unit 401 is connected between the input and the pulse width adjustment logical product unit 402, receives a delayed signal from the delay circuit 300, delays it by a predetermined pulse width, and outputs it to the pulse width adjustment logical product unit 402. The pulse width adjustment logical product unit 402 is connected between the input and the output, and the pulse width adjustment logical product unit 402 performs a logical product between the delayed signal at one input and the signal from the pulse width adjustment delay unit 401 at the other input, generates and outputs a delayed pulse signal OUT.

Figure 7 shows an example timing chart of the delay circuit 300 of this embodiment. In the timing chart, CKREF represents the input clock signal CKREF, OUT represents the delayed pulse signal OUT output from the output terminal 700, SET represents the signal output from the first pulse generating unit 312, RESET represents the signal output from the second pulse generating unit 314, CKUP represents the signal output from the latch unit 316, CKDN represents the clock signal CKREF input to the charge pump 320, the output current represents the current output from the charge pump 320, and VCAP represents the voltage of the capacitor 330.

In Figure 7, because the delay of the delayed pulse signal OUT relative to the clock signal CKREF is large, the delayed pulse signal OUT changes to high after the clock signal CKREF goes low. The signal generating unit 310 detects the first edges (hereinafter, odd-numbered edges) of the clock signal CKREF and the delayed pulse signal OUT, and a first control signal CKUP corresponding to the detection is input to the charge pump 320 along with a second control signal CKDN corresponding to the timing of the change in the clock signal CKREF. The first control signal CKUP changes to one logic (first logic) when the clock signal CKREF changes to the first logic (high, for example), and changes to the other logic (second logic (low, for example)) when the delayed pulse signal OUT changes to the first logic. The second control signal CKDN changes to one logic (first logic) when the clock signal CKREF changes to the first logic, and changes to the other logic (second logic) when the clock signal CKREF changes to the second logic.

The charge pump 320 charges the capacitor 330 with a current I_UP from the first edge of the clock signal CKREF to the first edge of the delayed pulse signal OUT in response to the first control signal CKUP. Meanwhile, the charge pump 320 discharges a current I_DN from the capacitor 330 from the first edge to the second edge (hereafter referred to as the even-numbered edges) of the clock signal CKREF in response to the second control signal CKDN. The current values of the currents I_UP and I_DN are set based on the delay relationship between the clock signal CKREF and the delayed pulse signal OUT. In this embodiment, when the second edge of the clock signal CKREF is earlier than the delay time of the delayed pulse signal OUT, the current values may be set such that the current I_UP is less than the current I_DN. Therefore, charge pump 320 discharges the current difference I_UP-I_DN from capacitor 330 from the first edge of clock signal CKREF to the first edge of delayed pulse signal OUT, reducing voltage VCAP, and then charges capacitor 330 with current I_UP from the second edge of clock signal CKREF to the first edge of delayed pulse signal OUT, raising voltage VCAP back to its original level. The decrease in VCAP voltage during discharge increases the delay.

This allows the delay time to be kept constant even if the second edge of the clock signal CKREF is earlier than the delay time. Here, the timing from the second edge to the third edge of the clock signal CKREF is unrelated to the delay control, making it possible to keep the delay constant regardless of the period (frequency) of the clock signal CKREF.

Figure 8 shows another example of a timing chart for the delay circuit 300 of this embodiment. The symbols in Figure 8 represent the same signals as in Figure 7.

In FIG. 8, because the delay of the delayed pulse signal OUT relative to the clock signal CKREF is small, the delayed pulse signal OUT changes to high before the clock signal CKREF goes low. The signal generation unit 310 detects the first edges (the parts that change to high) of the clock signal CKREF and the delayed pulse signal OUT, and a first control signal CKUP corresponding to the detection is input to the charge pump 320 along with a second control signal CKDN corresponding to the timing of the change in the clock signal CKREF.

Charge pump 320 charges capacitor 330 with current I_UP from the first edge of clock signal CKREF to the first edge of delayed pulse signal OUT in response to first control signal CKUP. Meanwhile, charge pump 320 discharges current I_DN from capacitor 330 from the first edge to the second edge of clock signal CKREF in response to second control signal CKDN. In this embodiment, if the second edge of clock signal CKREF is later than the delay time of delayed pulse signal OUT, current I_UP may be set to be greater than current I_DN. Therefore, charge pump 320 charges capacitor 330 with the current difference I_UP-I_DN from the first edge of clock signal CKREF to the first edge of delayed pulse signal OUT, thereby increasing voltage VCAP. Then, charge pump 320 discharges current I_DN from capacitor 330 from the first edge of delayed pulse signal OUT to the second edge of clock signal CKREF, thereby decreasing voltage VCAP and restoring it to its original level.

In this embodiment, the delay circuit 300 can utilize a feedback system to ensure that the amount of charge charged and discharged by the charge pump 320 remains constant. For example, when the delay of the delayed pulse signal OUT relative to the clock signal CKREF is large, the high period of the first control signal becomes longer, increasing the period during which the current I_UP flows, thereby increasing the amount of charge stored in the capacitor 330 and raising the VCAP voltage. On the other hand, when the delay of the delayed pulse signal OUT is small, the high period of the first control signal becomes shorter, reducing the period during which the current I_UP flows, thereby reducing the amount of charge stored in the capacitor 330 and lowering the VCAP voltage. The amount of charge stored in the capacitor 330 is determined by the current I_UP and the delay time of the delayed pulse signal OUT, while the amount of charge discharged from the capacitor 330 is determined by the current I_DN and the period from the first edge to the second edge of the clock signal CKREF. In other words, current I_UP x delay time = current I_DN x (the period from the first edge to the second edge of the clock signal CKREF), and by appropriately setting the magnitudes of current I_UP and current I_DN, the delay time can be freely adjusted.

In the delay circuit 300 of this embodiment, the timing from the second edge to the third edge of the clock signal CKREF is unrelated to delay control, making it possible to maintain a constant delay independent of the cycle (frequency) of the clock signal CKREF. The delay circuit 300 operates by detecting the edges of the input signal using the signal generation unit 310, so even if the period from the first edge to the second edge of the clock signal CKREF is shorter than the delay time, it can maintain a constant delay time independent of the frequency of the clock signal CKREF. Furthermore, it is independent of the duty cycle of the delayed pulse signal OUT.

Figure 9 shows a second configuration example of the delay circuit 300. The delay circuit 300 of the second configuration example has the same configuration and operation as the delay circuit 300 of the first configuration example, except for the connection between the signal generation unit 310 and the charge pump 320. The signal generation unit 310 may output a first control signal CKDN to terminal DN of the charge pump 320, and output a second control signal CKUP to terminal UP of the charge pump 320.

Figure 10 shows an example timing chart for the delay circuit 300 of the second configuration example. The symbols in Figure 9 represent the same signals as those in Figure 7, except that CKDN represents the signal output from the latch unit 316, and CKUP represents the clock signal CKREF input to the charge pump 320. In the delay circuit 300 of the second configuration example, the input destinations of the first control signal and the second control signal are swapped compared to the first configuration example, and therefore the magnitude and timing of the output current of the charge pump 320 are changed.

From the first edge to the second edge of the clock signal CKREF, capacitor 330 is charged with a current difference (I_UP - I_DN), causing the VCAP voltage to rise. Thereafter, current I_UP stops, and only current I_DN is supplied to capacitor 330 until the first edge of the delayed pulse signal OUT, during which time the VCAP voltage decreases and returns to its original level. In this case, current I_DN x delay time = I_UP x (period from the first edge to the second edge of the clock signal CKREF), and the delay time can be freely adjusted by appropriately setting the magnitudes of current I_UP and current I_DN.

Figure 11 shows another example of a timing chart for the delay circuit 300 of the delay pulse generation circuit 10 of this embodiment. In the timing chart, CKREF represents the input clock signal CKREF, OUT represents the delayed pulse signal OUT output from the output terminal 700, CKUP represents the second control signal, CKDN represents the first control signal, output current represents the current output from the charge pump 320, and VCAP represents the voltage of the capacitor 330. The timing chart of this embodiment may have the same configuration and operation as the delay circuit 300 of the first or second configuration example, except that during the period when current I_DN and current I_UP of the charge pump 320 flow simultaneously, the current with the smaller absolute value of the current value is stopped, and only the difference flows from current I_DN.

In this embodiment, the first control signal CKDN changes to one logic (e.g., the first logic) when the clock signal CKREF changes to the first logic, and changes to the other logic (e.g., the second logic) the next time the clock signal CKREF changes or the delayed pulse signal OUT changes to the first logic, whichever occurs first; the second control signal CKUP changes to one logic (e.g., the first logic) the next time the clock signal CKREF changes or the delayed pulse signal OUT changes to the first logic, whichever occurs first; and changes to the other logic (the second logic) the next time the clock signal CKREF changes or the delayed pulse signal OUT changes to the first logic, whichever occurs later.

The first control signal CKDN goes high on the first edge (hereafter, odd-numbered edges) of the clock signal CKREF and goes low on the second edge (hereafter, even-numbered edges) of the clock signal CKREF. The second control signal goes high on the second edge of the clock signal CKREF and goes low on the first edge of the delayed pulse signal OUT. When the first control signal CKDN is high, the charge pump 320 flows only the current I_DN, reducing the voltage VCAP. When the second control signal CKUP is high, the charge pump 320 flows only the current I_UP, increasing the voltage VCAP and returning it to its original level. The delay circuit 300 of this embodiment may be configured as appropriate.

Note that while Figure 11 shows the case where the second edge of the clock signal CKREF is earlier than the first edge of the delayed pulse signal, if the second edge of the clock signal CKREF is later than the first edge of the delayed pulse signal, the first control signal changes to one logic (first logic) when the clock signal CKREF changes to the first logic, and changes to the other logic (second logic) when the delayed pulse signal OUT changes to the first logic, and the second control signal changes to one logic (first logic) when the delayed pulse signal OUT changes to the first logic, and changes to the other logic (second logic) when the clock signal CKREF next changes.

Figure 12 shows another example of a timing chart for the delay circuit 300 of the delay pulse generation circuit 10 of this embodiment. In the timing chart, CKREF represents the input clock signal CKREF, OUT represents the delayed pulse signal OUT output from the output terminal 700, CKUP represents the first control signal, CKDN represents the second control signal, output current represents the current output from the charge pump 320, and VCAP represents the voltage of the capacitor 330. The timing chart of this embodiment may have the same configuration and operation as the delay circuit 300 of the first or second configuration example, except that during the period when the current I_DN and current I_UP of the charge pump 320 flow simultaneously, the current with the smaller absolute value is stopped, and only the difference is allowed to flow from current I_UP.

The first control signal CKUP goes high on the first edge (hereafter, odd-numbered edges) of the clock signal CKREF and goes low on the second edge (hereafter, even-numbered edges) of the clock signal CKREF. The second control signal CKDN goes high on the second edge of the clock signal CKREF and goes low on the first edge (hereafter, odd-numbered edges) of the delayed pulse signal OUT. The charge pump 320 flows only current I_UP while the first control signal CKREF is high, increasing the voltage VCAP, and flows only current I_DN while the second control signal CKDN is high, decreasing the voltage VCAP and returning it to its original level. The delay circuit 300 of this embodiment may be configured as appropriate.

Figure 13 shows another example of the signal generation unit 310 of the delay circuit 300. The other example signal generation unit 310 has a first flip-flop unit 1300, a second flip-flop unit 1310, and an exclusive OR unit 1320. The first flip-flop unit 1300 is connected between the input terminal 100 and the exclusive OR unit 1320. The first flip-flop unit 1300 is composed of a DFF (delay flip-flop), receives a clock signal CKREF as an input, and outputs a signal CKREF_FF to the exclusive OR unit 1320. The second flip-flop unit 1310 is composed of a DFF (delay flip-flop), receives a delayed pulse signal OUT as an input, and outputs a signal OUT_FF to the exclusive OR unit 1320. The exclusive OR unit 1320 takes the exclusive OR of two inputs and outputs the first control signal CKUP. In another example, the signal generation unit 310 (not shown) outputs the input clock signal CKREF as the second control signal CKDN, similar to the first configuration example.

Figure 14 shows an example timing chart of another example of the signal generating unit 310. The signal CKREF_FF changes between high and low when the clock signal CKREF goes high; for example, it goes high at the first edge of the clock signal CKREF and goes low at the third edge. The signal OUT_FF changes between high and low when the delayed pulse signal OUT goes high; for example, it goes high at the first edge of the delayed pulse signal OUT and goes low at the third edge. The first control signal CKUP is the exclusive OR of the signals CKREF_FF and OUT_FF, and goes high at the first edge of the signal CKREF_FF, low at the first edge of the signal OUT_FF, high at the second edge of the signal CKREF_FF, and low at the second edge of the signal OUT_FF.

In this way, the signal generating unit 310 of this embodiment can generate the first control signal CKUP without pulsing the edges of the clock signal CKREF and the delayed pulse signal OUT.

The present embodiment shown in Figures 1 to 14, as described above, enables a delay-locked loop that generates a fixed delay signal from an input clock signal CKREF based on the time between two edges of the clock signal CKREF to operate correctly even when the period from the first edge to the second edge of the clock signal CKREF is shorter than the required delay time. When the conditions for the clock signal CKREF are a fixed input pulse width but a variable period, the delay circuit 300 can operate correctly even when the pulse width of the clock signal CKREF is shorter than the delay time required for the output of the driver 500. By feeding back the output of the driver 500 to the delay circuit 300, the delay is adjusted in the delay circuit 300, and the delay from the input terminal 100 to the output of the driver 500 can be kept constant regardless of environmental factors such as manufacturing variations in the input buffer 200, pulse width adjustment unit 400, and driver 500, or fluctuations in the power supply voltage, such as temperature.

Note that the logic (high and low) relationships in the timing charts shown in Figures 7 to 8, 10 to 12, and 14 above are examples, and the logic may be reversed. For example, the logic of the clock signal CKREF and the delayed pulse signal OUT may be reversed. Also, while an example has been shown in which the output of the driver 500 is input to the signal generation unit 310, a signal input to the driver 500 (e.g., a signal between the pulse width adjustment unit 400 and the driver 500) may be input to the signal generation unit 310 as a delayed pulse signal. Also, while an example has been shown in which MOS transistors are used in Figures 4 and 5 in this embodiment, bipolar transistors may also be used. Also, although the first and second edges are used as the edges of the clock signal CKREF that serve as the reference in the signal generation unit 310, the second and third edges may also be used.

Figure 15 shows a delay circuit of a comparative example. The delay circuit of the comparative example has a configuration and operation similar to that of delay circuit 300 of Figure 2, except that it has a logical product unit 1510 instead of signal generation unit 310. Logical product unit 1510 is connected between the input terminal and output terminal and charge pump 1520, and takes the logical product of the input clock signal CKREF and delayed pulse signal OUT to output one control signal CKUP. Charge pump 1520 receives one control signal CKUP and the other control signal (clock signal CKREF), and charges/discharges capacitor 1530 in accordance with these control signals. Delay unit 1500 provides a delay in accordance with the voltage of capacitor 1530.

Figure 16 shows a timing chart of a delay circuit of a comparative example. One control signal, CKUP, goes high at the first edge of the clock signal CKREF and low at the second edge. If the pulse width of the clock signal CKREF is shorter than the delay time of the delayed pulse signal, the second edge of the clock signal CKREF will precede the first edge of the delayed pulse signal OUT, preventing proper operation. The order of the first edge of the delayed pulse signal OUT and the second edge of the clock signal CKREF will be reversed, resulting in failure to control the current I_UP. Even if the delay amount of the delayed pulse signal OUT changes, if the second edge of the clock signal CKREF precedes the first edge of the delayed pulse signal OUT, the currents I_UP and I_DN will always be output simultaneously. Setting I_UP current > I_DN current creates the problem of the loop ultimately stabilizing at a position earlier than the desired delay. If the desired delay cannot be obtained, the propagation delay adjusted by delay circuit 300 will be smaller than the minimum delay of the system itself, forcing the delay circuit to always operate at the fastest delay, making it impossible to adjust the delay using delay circuit 300.

The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," or the like, and it should be noted that processes can be performed in any order, unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that it is necessary to perform the processes in that order.

10 Delay pulse generating circuit 100 Input terminal 200 Input buffer 600 Dummy input buffer 300 Delay circuit 310 Signal generating section 312 First pulse generating section 314 Second pulse generating section 316 Latch section 320 Charge pump 330 Capacitor 340 Delay section 400 Pulse width adjusting section 401 Pulse width adjusting delay section 402 Pulse width adjusting logical product section 500 Driver 700 Output terminal 1000 Inverter 1002 First current source 1004 Second current source 1010 First transistor 1020 Second transistor 1030 Third transistor 1040 Fourth transistor 1050 Resistor 1060 Fifth transistor 1070 Sixth transistor 1090 Inverter 1100 Inverter 1110 Inverter 1120 Inverter 1130 Inverter 1140 Inverter 1150 Inverter 1300 First flip-flop section 1310 Second flip-flop unit 1320, exclusive OR unit 1500, delay unit 1510, logical AND unit 1520, charge pump 1530, capacitor

Claims (6)

A delay pulse generating circuit that receives a clock signal and outputs a delay pulse signal,
The clock signal and the delayed pulse signal are input,
based on a first control signal which changes to one logic when the clock signal changes to a first logic and to the other logic when the delayed pulse signal changes to the first logic, and a second control signal which changes to one logic when the clock signal changes to the first logic and to the other logic when the clock signal changes to a second logic, or based on a first control signal which changes to one logic when the clock signal changes to the first logic and to the other logic when the clock signal next changes or when the delayed pulse signal changes to the first logic, whichever occurs first, and a second control signal which changes to one logic when the clock signal next changes or when the delayed pulse signal changes to the first logic, whichever occurs later, and to the other logic when the clock signal next changes or when the delayed pulse signal changes to the first logic,
a delay circuit that generates a delayed signal by delaying the clock signal;
a driver that outputs a delay pulse signal in response to the delay signal,
The delay circuit
a charge pump that outputs a current in response to the first control signal and the second control signal;
a delay unit that outputs the delayed signal by delaying the clock signal in accordance with the current output by the charge pump;
a signal generating unit that generates a first pulse signal that rises when the clock signal changes and a second pulse signal that rises when the delayed pulse signal changes;
a latch unit that outputs one of the first control signal and the second control signal in response to the first pulse signal and the second pulse signal,
the charge pump receives as input one of the first control signal and the second control signal output from the latch unit, receives as input the clock signal as the other of the first control signal and the second control signal, and outputs a current in response to the first control signal and the second control signal. the delay circuit has a capacitor connected between a node to which the output of the charge pump is connected and a reference potential;
The delay pulse generating circuit according to claim 1 , wherein the charge pump changes a direction of a current in response to the first control signal and the second control signal to charge or discharge the capacitor. The delay circuit
a signal generating unit that generates a first pulse signal that rises when the clock signal changes and a second pulse signal that rises when the delayed pulse signal changes;
a latch unit that outputs one of the first control signal and the second control signal in response to the first pulse signal and the second pulse signal,
3. The delay pulse generation circuit according to claim 2, wherein the charge pump receives one of the first control signal and the second control signal output from the latch unit, receives the clock signal as the other of the first control signal and the second control signal, and outputs a current in response to the first control signal and the second control signal. The signal generation unit
a first pulse generating unit including a first pulse generating delay unit to which the clock signal is input, and a first pulse generating AND unit to which the clock signal is input at one input and a signal obtained by delaying the clock signal by the first pulse generating delay unit is input at the other input, and which outputs the first pulse signal;
4. The delay pulse generation circuit according to claim 1, further comprising: a second pulse generation delay unit to which the delayed pulse signal is input; and a second pulse generation logical AND unit to which the delayed pulse signal is input and which receives a signal obtained by delaying the delayed pulse signal by the second pulse generation delay unit and which outputs the second pulse signal. 5. The delayed pulse generating circuit according to claim 3 , wherein the latch section performs SR latching in response to the first pulse signal and the second pulse signal, and outputs one of the first control signal and the second control signal. The delay pulse generating circuit according to claim 1 , wherein the delay circuit receives the delayed pulse signal output from the driver or input to the driver.