JP7725166B2 - Integrated non-volatile memory electrode thin film resistor cap and etch stop - Google Patents

Description

Embodiments of the present invention relate generally to the field of semiconductor devices, and more particularly to non-volatile solid-state memory devices.

Some advanced-node (14 nm and beyond) semiconductor devices may be fabricated using metal hardmask etching techniques that utilize metal-removing wet etchants. Such techniques may be incompatible with solid-state non-volatile memory (NVM) cells that use metal top electrodes. Furthermore, these metal top electrodes may be too conductive for optimal or desired NVM device operation. For example, resistive random access memory (RRAM) cells may require current control or current-limiting devices (e.g., transistors or the like) to control filament formation and enforce current compliance. In another example, NVM cells may experience current overshoot due to fast negative differential resistance switching or the like. This current overshoot may affect the endurance of the NVM cell and may adversely affect components surrounding the NVM cell.

In one embodiment of the present invention, a nonvolatile memory (NVM) is presented. The NVM includes a top state influencing electrode in contact with a state changing structure. The top state influencing electrode affects a detectable attribute of the state changing structure. The detectable attribute of the state changing structure represents a data value stored by the NVM. The NVM further includes a top wire and a first thin film resistor (TFR) between the top state influencing electrode and the top wire and in contact with the top state influencing electrode and the top wire, respectively.

In another embodiment of the present invention, an integrated circuit (IC) device manufacturing method is presented. The method includes forming a bottom state influencing electrode over and in-line with a bottom wire. The method includes forming a state change structure over the bottom state influencing electrode. The method further includes forming a top state influencing electrode directly over the state change structure. The top state influencing electrode affects a detectable attribute of the state change structure. The detectable attribute of the state change structure represents a data value. The method further includes forming a thin film resistor (TFR) directly over the top state influencing electrode.

In yet another embodiment of the present invention, an integrated circuit (IC) device manufacturing method is presented. The method includes forming a bottom thin film resistor (TFR) directly on a bottom wire. The method further includes forming a bottom state-affecting electrode directly on the TFR in-line with the bottom wire. The bottom TFR electrically connects the bottom wire and the bottom state-affecting electrode in series. The method further includes forming a state-change structure on the bottom state-affecting electrode. The method further includes forming a top state-affecting electrode directly on the state-change structure. The top state-affecting electrode affects a detectable attribute of the state-change structure. The detectable attribute of the state-change structure represents a data value. The method further includes forming a top TFR directly on the top state-affecting electrode.

These and other embodiments, features, aspects and advantages will be more fully understood with reference to the following description, appended claims and accompanying drawings.

So that the above-mentioned features of the present invention can be achieved and understood in detail, a more particular description of the invention briefly outlined above can be had by reference to the embodiments of the invention illustrated in the accompanying drawings.

It should be noted, however, that the attached drawings depict only typical embodiments of the present invention and therefore should not be considered as limiting the scope of the present disclosure, as the present invention may embrace other embodiments that are equally effective.

1A-1C illustrate cross sections of phase change random access memory (PCRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of RRAM cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of magnetoresistive random access memory (MRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of ferroelectric RAM (FRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of electrochemical RAM (ECRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop, according to various embodiments of the present invention. 1A-1C are cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells with an integrated thin-film resistor and etch stop according to various embodiments of the present invention; FIG. 1D illustrates an integrated circuit (IC) device manufacturing method according to various embodiments of the present invention; 1A-1C illustrate cross sections of RRAM cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of ferroelectric RAM (FRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of magnetoresistive random access memory (MRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate integrated circuit (IC) device fabrication methods including non-volatile memory cells with integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of conductive bridge RAM (CBRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of conductive bridge RAM (CBRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention. 1A-1C illustrate cross sections of electrochemical RAM (ECRAM) cells including integrated thin film resistors and etch stops according to various embodiments of the present invention.

The drawings are not necessarily drawn to scale. The drawings are merely schematic and are not intended to portray specific parameters of the invention. The drawings are intended to depict only exemplary embodiments of the invention. Like numbers represent like elements throughout the drawings.

This specification discloses detailed embodiments of the claimed structures and methods. However, it is understood that the disclosed embodiments are merely examples of the claimed structures and methods, which may be embodied in various forms. These exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description and drawings, well-known features and technical details may be omitted to avoid unnecessarily obscuring the presented embodiments.

Exemplary fabrication steps for forming an IC device including one or more PCM memory cells 100 are illustrated and described in more detail below with reference to the drawings, in which like components are numbered alike. While some components of the IC device may be referred to in the singular throughout this description, it should be noted that more than one component may be included within an IC device. The specific components and cross-sectional orientations shown in the drawings have been selected to best illustrate the various embodiments described herein.

The nonvolatile memory cell includes a thin-film resistor (TFR) in series between the top state-affecting electrode and the top wire. This TFR limits or generally reduces current flow from the top wire at the top state-affecting electrode, thereby improving the durability of the nonvolatile memory cell and limiting adverse effects on components adjacent to the nonvolatile memory cell. The TFR also serves as an etch stop when forming the top wire trench associated with the fabrication of the top wire. In some nonvolatile memory cells where symmetry of the cell is desired, an additional TFR can be formed between the bottom wire and the bottom state-affecting electrode. Figure 1 illustrates a cross-section of a phase change random access memory (PCRAM) cell including an integrated thin-film resistor and etch stop according to various embodiments of the present invention.

Figure 1 illustrates a cross section of a PCRAM cell 100 including an integrated TFR and etch stop 112, referred to herein as TFR 112, in accordance with various embodiments of the present invention.

PCRAM is a nonvolatile solid-state memory technology that utilizes thermally assisted, reversible switching of phase-change materials (PCMs), particularly chalcogenide compounds such as germanium-antimony-tellurium (GST), between states with different electrical resistances. The basic storage unit ("cell") can be programmed into several different states or levels that exhibit different resistive properties. These programmable cell states can be used to represent different data values, thereby enabling the storage of information.

In PCM devices, each cell can be set to at least two states: a "SET" state and a "RESET" state, allowing for the storage of one bit per cell. In the RESET state, which corresponds to the fully amorphous state of the phase-change material, the cell has a very high electrical resistance. By heating above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully crystalline state. This low-resistance state provides the cell's SET state. If the cell is then heated above the melting point of the phase-change material, the material returns to the fully amorphous RESET state after rapid cooling. In multilevel PCM devices, cells can be set to s > 2 programmable states, allowing for the storage of more than one bit per cell. The different programmable states correspond to different relative proportions of amorphous and crystalline phases in the volume of the phase-change material. Specifically, in addition to the two states used for single-level operation, multi-level cells utilize intermediate states in which the cell contains different volumes of amorphous phase within an otherwise crystalline PCM. Because these two material phases exhibit a large resistance contrast, variations in the size of the amorphous phase within the total cell volume produce corresponding variations in cell resistance.

Reading and writing data in PCM cells is accomplished by applying an appropriate voltage to the phase change material via a pair of electrodes associated with each cell. During a write operation, the resulting programming signal Joule heats the phase change material to the appropriate temperature, which induces the desired cell state after cooling. Reading a PCM cell is performed using the cell resistance as a metric of the cell state. Application of a read voltage causes a current to flow through the cell, and this read current depends on the cell's resistance. Therefore, measuring the cell's read current provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing this resistance metric to predetermined reference levels for s programmable cell states.

The PCRAM cell 100 includes a volume of PCM 102 interposed between a top electrode 106 and a heater layer and bottom electrode 130. The cell state shown represents an intermediate state in which the material 102 contains both crystalline and amorphous phases. The amorphous phase is indicated by the shaded hemispherical volume 104 above the bottom electrode 130. The crystalline phase 105 occupies the remainder of the PCM 102 volume. When a read voltage is applied to read the programmed cell state, the resulting read current flows primarily through this current path from the crystalline phase 105 to the bottom electrode 130, rather than through the highly resistive amorphous phase 104.

The PCRAM cell 100 includes a TFR 112 located on top of the top electrode 106. In some implementations, the conductivity of the electrode 106 and/or the bottom electrode 130 may be too high to allow the phase change material to amorphize at low drive currents. This high conductivity can lead to electromigration due to a sudden surge in current during device resistance state switching. Therefore, the inclusion of the TFR 112 serves as a current reduction measure to limit current from the surrounding operating integrated circuit during PCM 102 switching. Limiting current through the PCM 102 volume with the TFR 112 can improve the durability of the PCRAM cell 100 and limit adverse effects on components adjacent to the PCRAM cell 100. Additionally, the TFR 112 can act as a thermal barrier during PCM 102 switching operations. Heat generated within the PCM volume 102 is typically conducted and lost through the top electrode 106. The TFR 112 reduces this heat loss and the current required to switch the state of the PCM volume 102 of the PCRAM cell 100.

TFR 112 is typically a film or sheet that covers the entire surface of the NVM cell's top or bottom state-affecting electrode between that electrode and its corresponding respective top wire 140 or bottom wire 150. Thus, when applicable, top wire 140 or bottom wire 150 is electrically connected in series from the top or bottom state-affecting electrode by TFR 112, respectively.

The TFR 112 is formed of a semiconductor, dielectric, or insulator material having a resistance between 1 kilohm and 10 megaohms, for example. The TFR 112 can be aluminum nitride (AlN) or other similar materials. Generally, the resistance of the TFR 112 is determined by the resistance across the memory cell (excluding the TFR 112). If the resistance of the cell (excluding the TFR 112) is on the conductive side (memory cell resistance has a resistance similar to TaN, for example), the TFR 112 can be formed of a semiconductor. Typically, the target resistance of the TFR 112 can be 1/1000 to 1/10 of the resistance of the memory cell's lowest resistance state. For example, if the lowest resistance across the PCRAM cell 100 (excluding the TFR 112) is 1 megaohm, the TFR 112 can have a resistance of 25 kiloohms. If the resistance of the TFR 112 is too large, the TFR 112 may dominate the cell and the voltage demands may become too large; if the resistance of the TFR 112 is too small, the TFR 112 may not be suitable as a ballast resistor.

An encapsulation spacer 108 may be placed on the side walls or lateral boundaries of the PCM 102 volume, the top electrode 106, and the TFR 112, or may be otherwise connected to the side walls or lateral boundaries of the PCM 102 volume, the top electrode 106, and the TFR 112. The top surface of the encapsulation spacer 108 may be coplanar with the top surface of the TFR 112, and the bottom surface of the encapsulation spacer 108 may be coplanar with the bottom surface of the PCM volume 102.

In some implementations, the encapsulation spacer 108 can be omitted and instead, an ILD 730 can be formed, for example, as shown in FIG. 12 (i.e., the ILD 730 can contact the sidewalls or lateral boundaries of the volume of the PCM 102, the sidewalls or lateral boundaries of the top electrode 106, and the sidewalls or lateral boundaries of the TFR 112).

A top wire 140 may be connected to the top surface of the TFR 112, and a bottom wire 150 may be connected to the bottom electrode 130. As known in the art, the top wire 140, the bottom wire 150, or both may be electrically connected to other components of the IC device, such as a memory controller or the like.

Figure 2 shows a cross section of an RRAM cell 200 including a TFR 112 according to various embodiments of the present invention.

RRAM is a non-volatile solid-state memory technology that exploits the change in resistance switching of insulators, such as binary metal oxides, under an applied electric field. The basic storage unit ("cell") can be programmed into several different states or levels, which exhibit different resistance properties. These programmable cell states can be used to represent different data values, thereby enabling the storage of information.

RRAM architecture typically consists of a resistance-switching memory cell with a metal-insulator-metal structure, commonly referred to as an MIM structure. This structure includes an insulating layer (I) sandwiched between two metal (M) electrodes. Applying a voltage pulse across an RRAM cell can cause the device to transition from a high resistance state (HRS) or OFF state, commonly referred to as a logic "0," to a low resistance state (LRS) or ON state, commonly referred to as a logic "1," and vice versa.

RRAM cells fabricated in this manner are typically initially in the HRS state; when a voltage (e.g., a high-voltage pulse) is applied to switch the device from the HRS to the LRS state, a conductive path, sometimes called a filament, can be formed in the switching layer, switching the RRAM cell to the LRS state. This process, which occurs through a soft breakdown of the metal-insulator-metal (MIM) structure, is commonly called "electroforming," and the voltage at which this process occurs is called the forming voltage. To switch the RRAM cell from the LRS to the HRS state, a voltage pulse called the RESET voltage is applied.

To read data from an RRAM cell, a read voltage is applied that does not disturb the cell's current state to determine whether the cell is in a logic 0 (HRS) or logic 1 (LRS) state. RRAM is a nonvolatile memory because both the LRS and HRS retain their corresponding respective values after the applied voltage is removed.

The switching of an RRAM cell is based on the growth of a conductive filament (CF) in an insulating layer. The CF is a channel with a diameter on the order of nanometers that connects the top and bottom electrodes of the memory cell. A low LRS with high conductivity is obtained when the CF is connected between the electrodes, and a high RRS is obtained when the filament is broken and there is a discontinuity between the electrodes.

In multilevel RRAM devices, cells can be set to s > 2 programmable states, allowing for the storage of more than one bit per cell. The different programmable states correspond to different relative percentages of CFs within the volume of insulating material. Specifically, in addition to the two states used for single-level operation, multilevel cells utilize intermediate states in which the cell contains different volumes of a specific CF or different numbers of distinct CFs. Because the LRS and HRS exhibit a large resistance contrast, a variation in the size of a single CF or an increase in the number of distinct CFs within the total cell volume produces a corresponding variation in cell resistance.

The RRAM cell 200 includes an insulator material 202 interposed between a top electrode 206 and a bottom electrode 210. The cell state shown represents an intermediate state in which a CF 204 is formed in the insulator 202. When a read voltage is applied to read the programmed cell state, the resulting read current flows primarily through the current path from the top electrode 206 to the bottom electrode 210 through the CF 204, rather than through the highly resistive insulator material 202 in which the CF 204 is not formed.

The RRAM cell 200 further includes a TFR 112 located on the top surface of the top electrode 206. In some implementations, the conductivity of the top electrode 206 may be too high to drive optimal or desired state-change behavior within the insulator 202, so the TFR 112 acts as a current reduction means to limit or generally reduce the current through the insulator 202 from the top electrode 206. The TFR 112 can act as a ballast resistor when the filament 204 of the RRAM cell 200 is formed. As soon as a connection is made, the current at a given voltage increases sharply, and the TFR 112 acts as the overall ballast resistor for the cell 200. Limiting the current through the insulator 202 with the TFR 112 can improve the durability of the RRAM cell 200 and limit adverse effects on components adjacent to the RRAM cell 200.

An encapsulation spacer 208 may be placed on the sidewalls or lateral boundaries of the MIM stack and the TFR 112, or may be otherwise connected to the sidewalls or lateral boundaries of the MIM stack and the TFR 112. The top surface of the encapsulation spacer 208 may be coplanar with the top surface of the TFR 112, and the bottom surface of the encapsulation spacer 208 may be coplanar with the bottom surface of the bottom electrode 210.

In some implementations, the encapsulation spacer 208 can be omitted and instead, an ILD 730 can be formed, for example, as shown in FIG. 12 (i.e., the ILD 730 can contact the sidewalls or lateral boundaries of the MIM stack and the sidewalls or lateral boundaries of the TFR 112).

A top wire 140 may be connected to the top surface of the TFR 112, and a bottom wire 150 may be connected to the bottom electrode 210. As known in the art, the top wire 140, the bottom wire 150, or both may be electrically connected to other components of the IC device, such as a memory controller or the like.

Figure 3 shows a cross section of an MRAM cell 300 including a TFR 112 according to various embodiments of the present invention.

MMRAM is a non-volatile solid-state memory technology that utilizes the change in resistance switching of an insulator relative to the magnetic orientation of two ferromagnetic plates. The basic storage unit ("cell") can be programmed into at least two different states or levels that exhibit different resistance characteristics. These programmable cell states can be used to represent different data values, thereby enabling the storage of information.

MMRAM architectures typically rely on a magnetic tunnel junction (MTJ) structure in which two ferromagnetic layers are separated by a dielectric spacer layer, sometimes called a tunnel barrier. When the tunnel barrier is very thin, typically <2 nm, quantum mechanical tunneling of electrons through the barrier causes the MTJ to behave like a resistor, with a resistance that depends exponentially on the barrier thickness and proportional to the inverse of the in-plane barrier area. The tunnel current is spin-polarized due to the asymmetric band structure of the ferromagnetic electrodes, resulting in tunnel magnetoresistance.

The relative orientation of the magnetization of these two layers determines the resistance of the MTJ device. For most materials, LRS exists when the magnetizations of the two layers are parallel, because majority band electrons can tunnel into the majority band on the other side of the barrier. HRS exists when the orientation is antiparallel, because majority band electrons must tunnel into the minority band of the opposite layer.

One of these ferromagnetic layers is the free layer, sometimes called the recording or storage layer, which holds the stored information. The tunnel barrier is typically a nonmagnetic insulating layer that provides a means to switch and read the state of the free layer via a spin-polarized tunneling current. The other ferromagnetic layer is the fixed or reference layer, which provides a stable reference magnetization direction for reading and switching the free layer. This fixed layer is designed to have a much higher magnetic anisotropy than the free layer so that it never switches during memory operations.

Data can be written to an MRAM cell by passing current through wires above and below the MRAM cell, thereby inducing a magnetic field that is accepted by the free layer.

Reading data from an MRAM cell can be accomplished by measuring the cell's electrical resistance. Due to tunneling magnetoresistance, the cell's electrical resistance varies with the relative orientation of the magnetization of the two plates. By determining the resistance within a particular MRAM cell, the polarity of the magnetization of the free layer can be determined.

The MRAM cell 300 includes a barrier layer 302 interposed between a top ferromagnetic free layer 304 and a bottom ferromagnetic pinned layer 310. The MRAM cell 300 further includes a top electrode 306 connected to the top surface of the top ferromagnetic free layer 304, and may also include a bottom electrode 312 connected to the bottom surface of the bottom ferromagnetic pinned layer 310. The cell state shown represents the HRS state, in which the magnetic orientation between the top ferromagnetic free layer 304 and the bottom ferromagnetic pinned layer 310 is antiparallel.

The MRAM cell 300 further includes a TFR 112 disposed on the top surface of the top electrode 306. In some implementations, the conductivity of the top electrode 306 may be too high to drive optimal or desired state-change behavior in the ferromagnetic free layer 304, so the TFR 112 acts as a current reduction means to limit or generally reduce the current through the top electrode 306 that affects the ferromagnetic free layer 304. Limiting the current through the top electrode 306 by the TFR 112 can improve the durability of the MRAM cell 300 and limit adverse effects on components adjacent to the MRAM cell 300.

The encapsulation spacer 308 may be placed on the sidewalls or lateral boundaries of the MTJ stack, the top electrode 306, and the TFR 112, or may be otherwise connected to the sidewalls or lateral boundaries of the MTJ stack, the top electrode 306, and the TFR 112. The top surface of the encapsulation spacer 308 may be coplanar with the top surface of the TFR 112, and the bottom surface of the encapsulation spacer 308 may be coplanar with the bottom surface of the bottom electrode 312.

In some implementations, the encapsulation spacer 308 can be omitted and instead, an ILD 730 can be formed, for example, as shown in FIG. 12 (i.e., the ILD 730 can contact the sidewalls or lateral boundaries of the MTJ stack, the sidewalls or lateral boundaries of the top electrode 306, the sidewalls or lateral boundaries 330, and the sidewalls or lateral boundaries of the TFR 112).

A top wire 140 may be connected to the top surface of the TFR 112, and a bottom wire 150 may be connected to the bottom electrode 312. As known in the art, the top wire 140, the bottom wire 150, or both may be electrically connected to other components of the IC device, such as a memory controller or the like.

Figure 4 shows a cross section of an FRAM cell 400 including a TFR resistor 112 according to various embodiments of the present invention.

FRAM is a non-volatile solid-state memory technology that utilizes the presence or absence of an electric charge in a capacitor containing a ferroelectric dielectric between electrodes. This basic storage unit ("cell") can be programmed into at least two different states or levels that exhibit different charge characteristics. These programmable cell states can be used to represent different data values, thereby enabling the storage of information.

A FRAM architecture can consist of a grid of such capacitors and their associated wiring and signaling transistors. Each cell typically operates with one signaling transistor. Data can be stored as the presence or absence of charge in a ferroelectric capacitor, with the absence of charge generally representing a "0" and the presence of charge representing a "1." Writing is accomplished by applying a field across the ferroelectric layer by storing charge on electrodes on either side of the layer; this field forces the atoms within into an "up" or "down" orientation (depending on the polarity of the charge), thereby storing a "1" or a "0." Reading a cell can be accomplished by a signaling transistor forcing the cell into a particular state, e.g., a "0." If the cell already holds a "0," nothing happens on the output line. If the cell holds a "1," a brief current pulse appears at the output as the atoms in the film reorient and push electrons out of the metal on the "down" side. The presence of this pulse indicates that the cell was holding a "1." Because this process overwrites the cells, reading FRAM is a destructive process, requiring the cells to be rewritten.

FRAM cell 400 includes a ferroelectric layer 408 interposed between a top electrode 406 and a bottom electrode 410. FRAM cell 400 can operate with a switching transistor, as known in the art. The cell state shown represents a charged state in which a charge is present in ferroelectric layer 408, which typically represents cell 400 storing a "1."

The FRAM cell 400 further includes a TFR 112 disposed on the top surface of the top electrode 406. In some implementations, the conductivity of the top electrode 406 may be too high to drive optimal or desired state-change behavior in the ferroelectric layer 408, so the TFR 112 acts as a current reduction means to limit or generally reduce the current through the top electrode 406, thereby reducing the charge across the ferroelectric layer 408. Limiting the current through the top electrode 406 with the TFR 112 can improve the durability of the FRAM cell 400 and limit adverse effects on components adjacent to the FRAM cell 400.

The encapsulation spacer 408 may be placed on the sidewalls or lateral boundaries of the capacitor stack and the sidewalls or lateral boundaries of the TFR 112, or may be otherwise connected to the sidewalls or lateral boundaries of the capacitor stack and the sidewalls or lateral boundaries of the TFR 112. The top surface of the encapsulation spacer 408 may be coplanar with the top surface of the TFR 112, and the bottom surface of the encapsulation spacer 408 may be coplanar with the bottom surface of the bottom electrode 410.

In some implementations, the encapsulation spacer 408 can be omitted and instead, an ILD 730 can be formed, for example, as shown in FIG. 12 (i.e., the ILD 730 can contact the sidewalls or lateral boundaries of the capacitor stack and the sidewalls or lateral boundaries of the TFR 112).

A top wire 140 may be connected to the top surface of the TFR 112, and a bottom wire 150 may be connected to the bottom electrode 410. As known in the art, the top wire 140, the bottom wire 150, or both may be electrically connected to other components of the IC device, such as a memory controller or the like.

Figure 5 shows a cross section of an ECRAM cell 500 including a TFR 112 according to various embodiments of the present invention.

ECRAM is a nonvolatile solid-state memory technology that utilizes the change in resistance of mixed ionic electronic conductor materials due to the addition or removal of ions. In some mixed ionic electronic conductor materials, this change occurs through the introduction or removal of charge carriers. In other mixed ionic electronic conductor materials, this change occurs through an electronic transition (e.g., a Mott transition). This basic storage unit ("cell") can be programmed into at least two different states or levels that exhibit different resistance characteristics. These programmable cell states can be used to represent different data values, thereby enabling the storage of information.

An ECRAM can include a bottom electrode, a first mixed ionic and electronic conductor, a barrier, a second mixed ionic and electronic conductor, and a top electrode. Resistance across the cell is tuned by ionic exchange between the first and second mixed ionic and electronic conductors across the barrier when an electric field is applied. This charge transfer process allows for both maintaining a state when no power is applied and programming distinct states.

When an appropriate high-voltage write or programming pulse is applied, ions undergo charge transfer and migrate across the barrier. After programming, the ions relax. This high programming pulse draws ions out of one of the mixed ionic and electronic conductors, lowering the resistance of that conductor and thereby programming the cell to the LRS. If a low programming pulse is applied, insufficient ions are transferred from the first mixed ionic and electronic conductor, and the cell state remains in the HRS. To ensure that the cell is in the HRS, the cell can be reset after programming by applying a reset voltage.

To read data from an ECRAM cell, a read voltage is applied that does not disturb the cell's current state to determine whether the cell is in a logic 0 (HRS) or logic 1 (LRS) state. ECRAM is a nonvolatile memory because both the LRS and HRS retain their corresponding values after the applied voltage is removed.

ECRAM cell 500 includes a bottom electrode 510, a first mixed ionic and electronic conductor 512, a conductive ion barrier 520, a second mixed ionic and electronic conductor 514, and a top electrode 506. The resistance across cell 500 is tuned by ion exchange between first mixed ionic and electronic conductor 512 and second mixed ionic and electronic conductor 514 across barrier 520 when an electric field is applied, for example, to top electrode 506 or bottom electrode 510. This charge transfer process allows both the maintenance of states when no power is applied and the programming of distinct states.

When an appropriate high-voltage write or programming pulse is applied, for example, to the top electrode 506 or bottom electrode 510, ions undergo charge transfer and migrate across the barrier 520. For example, as shown, a high write voltage is applied to the top electrode 506, drawing ions out of the second mixed ionic and electronic conductor 514, which migrate across the barrier 520 into the first mixed ionic and electronic conductor 512. As a result, the resistance of the second mixed ionic and electronic conductor 514 decreases, thereby programming the cell to the LRS.

To read data from ECRAM cell 500, a read voltage that does not disturb the cell's current state is applied, for example, to top electrode 506 or bottom electrode 510, to determine whether the cell is in a logic 0 (HRS) or logic 1 (LRS) state. ECRAM is a nonvolatile memory because both LRS and HRS retain their corresponding respective values after the applied voltage is removed.

The ECRAM cell 500 further includes a TFR 112 located on top of the top electrode 506. The TFR 112 can mitigate the voltage flux imparted by relaxing ions. In an ECRAM, after programming the cell 500, ions may relax across the barrier 520 again, causing the cell 500 to retain a certain voltage. In some applications, the TFR 112 can mitigate this effect of ions relaxing across the barrier 520 again. Additionally, if the cell 500 forms a short across the barrier 520, the TFR 112 provides a base resistance value that identifies dropout, for example, from a neural net. Furthermore, in some implementations, the conductivity of the top electrode 506 may be too high to drive optimal or desired state-change behavior between the mixed ionic-electronic conductors 512, 514, and the TFR 112 acts as a current reduction means, limiting or generally reducing the current across the top electrode 506. By limiting the current through the top electrode 506 with the TFR 112, the durability of the ECRAM cell 500 can be improved and adverse effects on components adjacent to the ECRAM cell 500 can be limited.

The encapsulation spacer 508 may be placed on the sidewalls or lateral boundaries of the mixed ionic and electronic conductors 512, 514, the barrier 520, the bottom electrode 510, the top electrode 506, and the TFR 112, or may be otherwise connected to the sidewalls or lateral boundaries of the mixed ionic and electronic conductors 512, 514, the barrier 520, the bottom electrode 510, the top electrode 506, and the TFR 112. The upper surface of the encapsulation spacer 508 may be coplanar with the upper surface of the TFR 112, and the lower surface of the encapsulation spacer 508 may be coplanar with the lower surface of the bottom electrode 510.

In some implementations, the encapsulation spacer 508 can be omitted and instead, an ILD 730 can be formed, for example, as shown in FIG. 12 (i.e., the ILD 730 can contact the sidewalls or lateral boundaries of the mixed ionic and electronic conductors 512, 514, the barrier 520, the bottom electrode 510, the top electrode 506, and the TFR 112).

A top wire 140 may be connected to the top surface of the TFR 112, and a bottom wire 150 may be connected to the bottom electrode 510. As known in the art, the top wire 140 and/or the bottom wires 150, 150' may be electrically connected to other components of the IC device, such as a memory controller or the like.

1 through 5 illustrate different solid-state NVM cells, each of which includes a top state-affecting electrode. The term "top state-affecting electrode" is defined herein as a top conductive electrode within an NVM cell that is in direct contact with a state- or attribute-changing material or structure also within the NVM cell (i.e., theoretically, there is no resistance/impedance between the electrode and the state- or attribute-changing material or structure) and that affects the state, attribute, etc., of the state- or attribute-changing material or structure to which it is directly connected. Wiring features generally above an NVM cell, such as top wire 140, should not be construed as a top state-affecting electrode because top wire 140 is generally not part of the NVM cell and because top wire 140 is only indirectly connected to an attribute-changing material or structure within the NVM cell (i.e., there is resistance/impedance between top wire 140 and the state- or attribute-changing material or structure, e.g., through top electrode 106, 206, 306, 406, 506, etc.).

For example, in FIG. 1 , top electrode 106 is a top state-affecting electrode because it is the top conductive electrode in PCRAM cell 100, which is in direct contact with PCM 102 and changes state (i.e., resistance) based on the phase of the PCM 102 material. For FIG. 2 , top electrode 206 is a top state-affecting electrode because it is the top conductive electrode in RRAM cell 200, which is in direct contact with insulator 202 and changes state (i.e., resistance) based on the growth of CF 204 in insulator 202. For FIG. 3 , top electrode 306 is a top state-affecting electrode because it is the top conductive electrode in MRAM cell 300, which is in direct contact with ferromagnetic free layer 304 and changes state (i.e., polarity) that drives a change in the resistance of insulator 302. For Figure 4, top electrode 406 is the top state-affecting electrode because top electrode 406 is the top conductive electrode in FRAM cell 400; this electrode is in direct contact with ferroelectric layer 408 and changes state (i.e., whether the atoms in ferroelectric layer 408 are oriented "up" or "down") based on the presence of an electric field across ferroelectric layer 408. For Figure 5, top electrode 506 is the top state-affecting electrode because top electrode 506 is the top conductive electrode in ECRAM cell 500; this electrode is in direct contact with mixed ionic and electronic conductor 514 and changes state (i.e., a decrease in ions making the material more conductive) that drives a resistance change in conductive mixed ionic and electronic conductor 514. For Figure 19, top electrode 906 is the top state-affecting electrode. This is because the top electrode 906 is the top conductive electrode in the CBRAM cell 900; it is in direct contact with the solid electrolyte 902 and changes state (i.e., resistance) based on the growth of the CF 904 in the solid electrolyte 902.

6 through 14 illustrate cross-sectional views of manufacturing stages of a manufacturing method for forming an IC device including one or more solid-state NVM cells including a TFR 112, according to various embodiments of the present invention. In the exemplary manufacturing stages shown, an RRAM cell 200 including a TFR 112 is fabricated. Similar techniques may be utilized to fabricate the remaining types of NVM cells contemplated herein. While such techniques may be described with respect to FIGS. 6 through 13, the techniques relate to the particular type of NVM cell to which reference is made.

Figure 6 illustrates a cross-sectional view of a manufacturing stage 600 of a manufacturing method for forming an IC device including an NVM cell that includes a TFR 112, according to various embodiments of the present invention.

At step 600, bottom wires 150 may be formed on a substrate 700. The bottom wires 150 may be formed of materials utilized for IC device wires, such as copper, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, or the like. The substrate 700 is typically formed from a dielectric material. In preferred embodiments, the substrate 700 may be formed from a low-k dielectric material (i.e., a material having a small dielectric constant compared to silicon dioxide). In some embodiments, the substrate 700 may be an interlayer dielectric (ILD) layer beneath which additional layers of an IC device have previously been fabricated.

The bottom wire 150 may be formed in the substrate 700 by any method known in the art. For example, a trench may be formed in the substrate 700 by known photolithography techniques, and then the trench may be filled with the bottom wire 150 material. Chemical mechanical planarization or other known methods may be used to remove excess bottom wire 150 material from the top surface of the substrate 700.

As is known in the art, one or more electrical paths may electrically connect bottom wire 150 to other components of an IC device. For example, one or more electrical paths may connect bottom wire 150 to a memory controller or the like. In this manner, bottom wire 150 may electrically connect components of an IC device to the NVM cell.

Figure 7 illustrates a cross-sectional view of a manufacturing stage 602 of a manufacturing method for forming an IC device including an NVM cell that includes a TFR 112, according to various embodiments of the present invention.

In step 602, a heating layer 704 can be formed on the substrate 700 and the bottom wire 150, and a bottom electrode 130 can be formed within the heating layer 704.

The heating layer 704 may be, for example, a silicon-based layer, such as a silicon layer or a silicon nitride layer. The bottom electrode 130 is formed in the heating layer 704 by any method known in the art. For example, known photolithography techniques may be used to form a trench in the heating layer 704, which may then be filled with the bottom electrode 130 material. Chemical mechanical planarization or other known methods may be used to remove excess bottom electrode 130 material from the top surface of the heating layer 704. The bottom electrode 130 material may be any generally conductive material used as an electrode, such as, for example, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, or the like.

In one embodiment, the trench is formed through the heating layer 704, thereby exposing a portion of the top surface of the bottom wire 150 previously formed in the substrate 700, so that the bottom electrode 130 can contact the bottom wire 150.

For clarity, some of the NVM cells contemplated herein, such as PCM cell 100, RRAM cell 200, CBRAM 900, and the like, may utilize a heating layer 704. However, other NVM cells, such as MRAM cell 300, FRAM cell 400, and ECRAM 500, may not utilize a heating layer 704. As such, fabrication of the heating layer 704 and/or bottom electrode 130 formed within the heating layer 704 may be an optional fabrication step depending on the desired NVM cell to be fabricated.

Figure 8 illustrates a cross-sectional view of a manufacturing stage 604 of a manufacturing method for forming an IC device including an NVM cell that includes a TFR 112, according to various embodiments of the present invention.

In step 604, the NVM cell build-up layers are fabricated. For example, to fabricate the RRAM cell 200, as shown, a bottom electrode material layer 710 is formed on the heating layer 704, an insulator material layer 712 is formed on the bottom electrode material layer 710, a top electrode material layer 714 is formed on the insulator material layer 712, an etch stop TFR layer 716 is formed on the top electrode material layer 714, and/or a capping layer 718 is formed on the etch stop TFR layer 716.

The bottom electrode material layer 710 may be formed on the heating layer 704 by depositing a conductive electrode material, such as titanium nitride, on the heating layer 704, on the electrode 130, or both. The bottom electrode material layer 710 may be formed to a thickness between 5 and 75 nm. In a preferred embodiment, the bottom electrode material layer 710 may be formed to a thickness between 20 and 30 nm.

The insulator material layer 712 may be formed on the bottom electrode material layer 710 by depositing a dielectric material, such as silicon nitride, on the bottom electrode material layer 710. The insulator material layer 712 may be formed to a thickness between 10 and 100 nm. In a preferred embodiment, the insulator material layer 712 may be formed to a thickness between 40 and 50 nm.

The top electrode material layer 714 is formed on the insulator material layer 712 by depositing a conductive electrode material, such as titanium nitride, on the insulator material layer 712. Although not required, the top electrode material layer 714 is typically formed of the same material as the bottom electrode material layer 710. The top electrode material layer 714 may be formed to a thickness between 5 and 75 nm. In a preferred embodiment, the top electrode material layer 714 may be formed to a thickness between 15 and 25 nm.

An etch stop TFR layer 716 is formed on the top electrode material layer 714 by depositing a resistive material, such as aluminum gallium nitride (AlGaN), nitride-rich tantalum nitride, or the like, on the top electrode material layer 714. The etch stop TFR layer 716 may be formed to a thickness between 1 and 20 nm. In a preferred embodiment, the etch stop TFR layer 716 may be formed to a thickness between 2 and 10 nm.

Capping layer 718 is formed on etch-stop TFR layer 716 by depositing a dielectric material, such as silicon nitride or the like, on etch-stop TFR layer 716. Capping layer 718 may be formed to a thickness between 10 and 80 nm. In a preferred embodiment, capping layer 718 may be formed to a thickness between 30 and 40 nm.

In an embodiment of PCRAM cell 100, the cell build-up layers can be fabricated by depositing a phase change material layer on the heating layer 704, depositing a top electrode material layer on the phase change material layer, depositing an etch stop TFR layer on the top electrode material layer, and depositing a capping layer on the etch stop TFR layer.

In embodiments of MRAM cell 300, the cell build-up layers can be fabricated by depositing a ferromagnetic pinned material layer on the substrate and/or the bottom wires, depositing a barrier material layer on the ferromagnetic pinned material layer, depositing a top ferromagnetic free layer on the barrier material layer, depositing an etch-stop TFR layer on the top electrode material layer, and depositing a capping layer on the etch-stop TFR layer.

In embodiments of FRAM cell 400, the cell build-up layers can be fabricated by depositing a bottom electrode material layer on the substrate and/or on the bottom wires, depositing a ferroelectric material layer on the bottom electrode material layer, depositing a top electrode material layer on the ferroelectric material layer, depositing an etch-stop TFR layer on the top electrode material layer, and depositing a capping layer on the etch-stop TFR layer.

In an embodiment of the ECRAM cell 500, the cell build-up layers can be fabricated by depositing a bottom electrode material layer on the substrate and bottom wires, depositing a mixed ionic and electronic conductor material layer on the bottom electrode material layer, depositing a barrier material on the mixed ionic and electronic conductor material layer, depositing a mixed ionic and electronic conductor material layer on the barrier layer, depositing a top electrode material layer on the mixed ionic and electronic conductor material layer, depositing an etch stop TFR layer on the gate electrode material layer, and depositing a capping layer on the etch stop TFR layer.

In an embodiment of the CBRAM cell 900, the cell build-up layers can be fabricated by depositing a bottom electrode material layer on the substrate/heating layer, depositing a solid electrolyte material layer on the bottom electrode material layer, depositing a top electrode material layer on the solid electrolyte material layer, depositing an etch stop TFR layer on the gate electrode material layer, and depositing a capping layer on the etch stop TFR layer.

Additionally, known photolithography layers, such as a mask layer and a developer layer, can be formed on the capping layer, and the developer layer can be formed on the mask layer.

Figure 9 illustrates a cross-sectional view of a manufacturing stage 606 of a manufacturing method for forming an IC device including an NVM cell including a TFR 112 according to various embodiments of the present invention. In stage 606, etching techniques are used to remove unwanted or exposed portions of the cell build-up layer while maintaining desired portions of the cell build-up layer to form a cell stack 711.

Using known photolithography techniques, the mask layer is developed or patterned to leave portions of the mask layer above the top layer of the cell build-up layer, thereby defining the underlying cell build-up layer and protecting the underlying cell build-up layer from the etchants of a chemical etch or the high-energy kinetic (ion, electron, or photon) beam of a dry etch, thereby maintaining the desired underlying cell build-up layer protected, these layers effectively forming the cell stack 711. This etching technique typically removes the undesired portions of the cell build-up layer, typically exposing the heating layer 704 (if present) or the substrate 700 (if the heating layer 704 is not present) in areas generally outside the formed cell stack 711.

The etching technique utilized in step 606 can be a physical or dry etching technique, or a chemical wet etching technique. In a preferred embodiment, the etching technique in step 606 is a physical dry etching technique, which poses less risk of damage to the material of the formed cell stack 711 (e.g., the absence of a chemical etchant may limit the lateral etching experienced by the material of the cell stack 711).

In the embodiment of the RRAM cell 200, as shown, the cell stack 711 includes a bottom electrode 210 formed from a retained portion of the bottom electrode material layer 710, an insulator material 202 formed from a retained portion of the insulator material layer 712, a top electrode 206 formed from a retained portion of the top electrode material layer 714, a TFR 112 formed from a retained portion of the etch stop TFR layer 716, and a cap 718' formed from a retained portion of the capping layer 718.

In an embodiment of the PCRAM cell 100, the cell stack 711 may include a volume of PCM 102 formed from a retained portion of the phase change material layer, a top electrode 106 formed from a retained portion of the top electrode material layer, a TFR 112 formed from a retained portion of the etch stop TFR layer 716, and a cap 718' formed from a retained portion of the capping layer 718.

In an embodiment of the MRAM cell 300, the cell stack 711 may include a bottom ferromagnetic pinned layer 310 formed from a retained portion of the ferromagnetic pinned material layer, a barrier layer 302 formed from a retained portion of the barrier material layer, a top ferromagnetic free layer 304 formed from a retained portion of the top ferromagnetic free layer, a TFR 112 formed from a retained portion of the etch stop TFR layer 716, and a cap 718' formed from a retained portion of the capping layer 718.

In an embodiment of the FRAM cell 400, the cell stack 711 may include a bottom electrode 410 formed from a retained portion of the bottom electrode material layer, a ferroelectric layer 408 formed from a retained portion of the ferroelectric material layer, a top electrode 406 formed from a retained portion of the top electrode material layer, a TFR 112 formed from a retained portion of the etch-stop TFR layer 716, and a cap 718' formed from a retained portion of the capping layer 718.

In an embodiment of the ECRAM cell 500, the cell stack 711 may include a bottom electrode 510 formed from a retained portion of the bottom electrode material layer, may include a mixed ionic and electronic conductor 512 formed from a retained portion of the mixed ionic and electronic conductor material layer, may include a barrier 520 formed from a retained portion of the barrier material layer, may include a mixed ionic and electronic conductor 514 formed from a retained portion of the mixed ionic and electronic conductor material layer, may include a top electrode 506 formed from a retained portion of the top electrode material layer, may include a TFR 112 formed from a retained portion of the etch stop TFR layer 716, and may include a cap 718' formed from a retained portion of the capping layer 718.

In the CBRAM cell 900 embodiment, the cell stack 711 includes a bottom electrode 910 formed from a retained portion of the bottom electrode material layer 710, a solid electrolyte 902 formed from a retained portion of the solid electrolyte layer, a top electrode 906 formed from a retained portion of the top electrode material layer 714, a TFR 112 formed from a retained portion of the etch-stop TFR layer 716, and a cap 718' formed from a retained portion of the capping layer 718.

Figure 10 illustrates a cross-sectional view of a manufacturing stage 608 of a manufacturing method for forming an IC device including an NVM cell including a TFR 112 according to various embodiments of the present invention. In stage 608, an encapsulation layer 720 is formed on the exposed areas of the heating layer 704 (if present) or on the exposed areas of the substrate 700 (if the heating layer 704 is not present), as well as on and around the cell stack 711.

The encapsulation layer 720 is a dielectric material layer that prevents or limits shorting between the various cell layers. For example, the spacer 208 formed from the encapsulation layer 720 prevents contact between the bottom electrode 210 and the top electrode 206. The encapsulation layer 720 can be formed by depositing a conformal dielectric insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, aluminum nitride, or the like, on the exposed regions of the heating layer 704 (if present) or on the exposed regions of the substrate 700 (if the heating layer 704 is not present), as well as on and around the cell stack 711. For example, the encapsulation layer 720 can be formed by depositing a blanket dielectric material layer on the previously exposed regions of the heating layer 704 (if present) or on the exposed regions of the substrate 700 (if the heating layer 704 is not present), the sidewalls or sides of the cell stack 711, and the top surface of the cell stack 711.

The thickness of the encapsulation layer 720 may be sufficient to protect the cell stack 720 during subsequent etching of the unwanted portions of the encapsulation spacer layer 720, such that the unwanted encapsulation spacer layer 720 is removed from those areas but maintained on the sidewalls or lateral surfaces of the cell stack 711. For example, the encapsulation layer 720 may be formed to a thickness between 2 and 100 nm. In a preferred embodiment, the encapsulation layer 720 may be formed to a thickness between 40 and 70 nm.

Figure 11 illustrates a cross-sectional view of a manufacturing stage 610 of a manufacturing method for forming an IC device including an NVM cell including a TFR 112 according to various embodiments of the present invention. At stage 610, unwanted portions of the encapsulation layer 720 are etched away, while retaining desired portions of the encapsulation layer 720' on the sidewalls of the cell stack 711.

Known directional etching techniques can be used to etch or otherwise remove the unwanted portions of the encapsulation layer 720. As shown in the cross-sectional view of FIG. 11, these unwanted portions of the encapsulation layer 720 may be generally horizontal (i.e., the layer portions have a width greater than their height). This directional etching process can preserve the desired portions of the encapsulation layer 720' that are on the sidewalls of the cell stack 711. As shown in the cross-sectional view of FIG. 11, these desired portions of the encapsulation layer 720' may be generally vertical (i.e., the layer portions have a height greater than their width).

The etching technique utilized in step 610 can be a physical or dry etching technique, or a chemical wet etching technique. In a preferred embodiment, the etching technique of step 610 is a chemical wet etching technique. As such, the heating layer 704 (if present) and the substrate 700 (if the heating layer 704 is not present) can be configured to act as an etch stop.

For clarity, in some implementations, steps 608 and 610 may be omitted, for example, if it is desired that ILD 730, as shown in FIG. 12, surround cell stack 711.

12 illustrates a cross-sectional view of a manufacturing stage 611 of a manufacturing method for forming an IC device including an NVM cell with a TFR 112 according to various embodiments of the present invention. In stage 611, an ILD 730 is formed on the heating layer 704 (if present) or on the substrate 700 (if the heating layer 704 is not present), as well as on the retained portion of the encapsulation layer 720' (if present) and on the cap 718'. If no encapsulation spacer is present, in stage 611, an ILD 730 is formed on the heating layer 704 (if present) or on the substrate 700 (if the heating layer 704 is not present), as well as on and around the cell stack 711.

The ILD 730 may be formed by depositing a blanket layer of a dielectric material, such as a low-k dielectric material, over the heating layer 704, the substrate 700, the retained portion of the encapsulation layer 720', and the cap 718', as appropriate or desired. The ILD 730 may be formed to a thickness generally greater than the height of the top surface of the cap 718' or to a thickness generally greater than the height of the top surface of the cap 718'.

In alternative embodiments, the ILD 730 can be formed to a thickness that is generally coplanar with the upper surface of the cap 718'. In these embodiments, a VIA (Vertical Interconnect Access) 746, illustratively shown in FIG. 14, can be formed through the ILD 730 to contact the bottom wire 150, and another or second ILD layer can be formed over the ILD 730 and the VIA 746. Subsequently, a top wire 140 can be formed through the second ILD layer to contact the VIA 746, and the top wire 140 can be formed through the second ILD layer to contact the TFR 112, as illustratively shown in FIG. 14.

Figure 13 illustrates a cross-sectional view of a manufacturing stage 612 of a manufacturing method for forming an IC device including an NVM cell including a TFR 112, according to various embodiments of the present invention. At stage 612, wiring trenches 732, 734 are formed in the ILD 730 using the TFR 112 in the cell stack 711 as an etch stop.

The wiring trenches 732, 734 may be formed by known selective removal techniques to remove unwanted portions of the ILD 730 generally above the bottom wire 150, or unwanted portions of the ILD 730 generally above the cell stack 711, or both. The wiring trenches 734 generally each expose at least a portion of the underlying conductive structure. The wiring trench 732 generally exposes the top surface of the TFR 112 in the cell 711 and planarizes the top surface of the encapsulation layer 720' portion with the top surface of the TFR 112, thereby forming encapsulation spacers 108, 208, 308, 408, 508, or the like, depending on the NVM cell being fabricated.

In a preferred embodiment, as shown, the wire trench 732 exposes the entire top surface of the NVM cell (i.e., the top surface of the encapsulation spacer (if present) and the top surface of the TFR 112).

Known etching techniques can be used to form wiring trenches with perpendicular sidewalls (i.e., sidewalls parallel to the sidewalls of the NVM cells), or, as shown, with sloped sidewalls.

In accordance with an embodiment of the present invention, TFR 112 is utilized as a stop layer for the etch that forms wiring trench 732. In this manner, the next higher level wiring trench 732 is formed utilizing an etch stop embedded in or otherwise included in the NVM cell.

The etching technique utilized in step 612 can be a physical or dry etching technique, or a chemical wet etch. In a preferred embodiment, the etching technique of step 612 is a chemical wet etch, with TFR 112 configured as a wet etchant stop. Thus, TFR 112 can be configured to be an etch stop layer for different types of etches, as desired.

Figure 14 illustrates a cross-sectional view of a manufacturing stage 614 of a manufacturing method for forming an IC device including an NVM cell including a TFR 112 according to various embodiments of the present invention. At stage 614, a top wire 140 is formed in each of the wiring trenches 732, 734. The top wire 140 may be formed by depositing a conductive material in each of the wiring trenches 732, 734.

As shown in the wiring structure on the right side of FIG. 14 , the top wire 140 can be directly connected to the TFR 112 of the NVM cell. For example, the wire 140 contacts the entire top surface of the TFR 112 and the entire top surface of the spacers 108, 208, 308, 408, 508, etc., depending on the particular NVM cell being fabricated. In some implementations, this top wire 140 contacts the entire top surface of the TFR 112 and also contacts at least a portion of the top surface of each adjacent encapsulating spacer 108, 208, 308, 408, 508, etc. Because the top wire 140 contacts or connects to the TFR 112 of the NVM cell instead of directly contacting a top state-affecting electrode, the current entering the NVM cell from the top wire 150 is reduced by the resistance of the TFR 112 (which can be adjusted based on the material selection of the TFR 112). By limiting the current entering the NVM cell with TFR 112, the endurance of the NVM cell can be improved and adverse effects on components adjacent to the NVM cell can be limited.

As is known in the art, one or more electrical paths within an IC device may electrically connect top wire 140 to other components of the IC device. For example, one or more electrical paths may connect top wire 140 to a memory controller or the like. In this manner, components of the IC device may be electrically connected to the fabricated NVM cell.

In some implementations, it may be beneficial for the NVM cell to be symmetrical about the horizontal bisector. Therefore, a second TFR 112 can be added at the bottom of the cell between the bottom wire 150 and the bottom state-affecting electrode. The term "bottom state-affecting electrode" is defined herein as the bottom conductive electrode in the NVM cell that is located inversely of the top state-affecting electrode across the horizontal bisector of the NVM cell.

In FIG. 15, an RRAM cell 200 includes a TFR 112 between the top electrode 206 and the top wire 140 and between the bottom electrode 210 and the bottom wire 150, in accordance with various embodiments of the present invention. The bottom electrode 210 should be interpreted as a bottom state-affecting electrode because it is the bottom conductive electrode in the cell 200 that is the inverse of the top electrode 206 (i.e., the top state-affecting electrode) across the horizontal bisector 691. To fabricate such a cell 200, an additional etch-stop TFR layer 716 can be formed between the bottom electrode material layer 710 and the heating layer 704 (if present) or between the bottom electrode material layer 710 and the substrate 700 (if the heating layer 704 is not present), in addition to other fabrication steps contemplated herein.

Encapsulation spacers 208 may be placed on or otherwise connected to the sidewalls or lateral boundaries of the cell layer sidewalls and the sidewalls or lateral boundaries of the symmetrical top and bottom TFR 112 layers. The top surface of the encapsulation spacer 208 may be coplanar with the top surface of the top TFR 112, and the bottom surface of the encapsulation spacer 208 may be coplanar with the bottom surface of the bottom TFR 112. The top wire 140 may be connected to the top surface of the TFR 112, and the bottom wire 150 may be connected to the bottom TFR 112.

In FIG. 16, the FRAM cell 400 includes a TFR 112 between the top electrode 406 and the top wire 140, and a TFR 112 between the bottom electrode 410 and the bottom wire 150, in accordance with various embodiments of the present invention. The bottom electrode 410 should be interpreted as a bottom state-affecting electrode because it is the bottom conductive electrode in the cell 400 that is the inverse of the top electrode 406 (i.e., the top state-affecting electrode) across the horizontal bisector 691. To fabricate such a cell 400, an additional etch-stop TFR layer 716 can be formed between the bottom electrode material layer 710 and the substrate 700, in addition to other fabrication steps contemplated herein.

Encapsulation spacers 408 may be placed on or otherwise connected to the sidewalls or lateral boundaries of the cell layer sidewalls and the sidewalls or lateral boundaries of the symmetrical top and bottom TFR 112 layers. The top surface of the encapsulation spacer 408 may be coplanar with the top surface of the top TFR 112, and the bottom surface of the encapsulation spacer 408 may be coplanar with the bottom surface of the bottom TFR 112. The top wire 140 may be connected to the top surface of the TFR 112, and the bottom wire 150 may be connected to the bottom TFR 112.

In FIG. 17, MRAM cell 300 includes TFR 112 between top electrode 206 and top wire 140 and between bottom electrode 312 and bottom wire 150, in accordance with various embodiments of the present invention. Bottom electrode 312 should be interpreted as a bottom state-affecting electrode because it is the bottom conductive electrode in cell 300 that is the inverse of top electrode 306 (i.e., the top state-affecting electrode) across horizontal bisector 691. To fabricate such a cell 300, an additional etch-stop TFR layer 716 can be formed between bottom electrode material layer 710 and substrate 700, in addition to other fabrication steps contemplated herein.

Encapsulation spacers 308 may be placed on or otherwise connected to the sidewalls or lateral boundaries of the cell layer sidewalls and the sidewalls or lateral boundaries of the symmetrical top and bottom TFR 112 layers. The top surface of the encapsulation spacer 308 may be coplanar with the top surface of the top TFR 112, and the bottom surface of the encapsulation spacer 308 may be coplanar with the bottom surface of the bottom TFR 112. The top wire 140 may be connected to the top surface of the TFR 112, and the bottom wire 150 may be connected to the bottom TFR 112.

Figure 18 illustrates an integrated circuit (IC) device fabrication method 800 according to various embodiments of the present invention. Method 800 can be utilized to form an IC device, such as a processor, microprocessor, memory, FPGA, or the like, that includes at least one NVM memory cell that includes a TFR 112 between a top state-affecting electrode and a top wire 140.

Method 800 begins at block 802, followed by forming an NVM cell stack (block 804). For example, depending on the type of NVM cell being fabricated, an NVM cell stack 711 may be formed on the substrate 700 or on the heating layer 704/bottom electrode 130, as appropriate.

In embodiments of the PCRAM 100, the cell stack 711 can be formed by forming a volume of PCM 102 on the heating layer 704/bottom electrode 130, forming a top electrode 106 on the PCM 102 volume, and forming a TFR 112 on the top electrode 106. In some embodiments, the cell stack 711 can be further formed by forming a cap 718' on the TFR 112.

In embodiments of the RRAM 200, the cell stack 711 can be formed by forming a bottom electrode 210 on the heating layer 704/bottom electrode 130, forming an insulator 204 on the bottom electrode 210, forming a top electrode 206 on the insulator 204, and forming a TFR 112 on the top electrode 206. In some embodiments, the cell stack 711 can be further formed by forming a cap 718' on the TFR 112.

In embodiments of the MRAM cell 300, the cell stack 711 can be formed by forming a bottom electrode 312 on the substrate 700 and/or the bottom wire 150, forming a bottom ferromagnetic pinned layer 310 on the bottom electrode 312, forming a barrier layer 302 on the bottom ferromagnetic pinned layer 310, forming a top ferromagnetic free layer 304 on the barrier layer 302, forming a top electrode 306 on the top ferromagnetic free layer 304, and forming a TFR 112 on the top electrode 306. In some embodiments, the cell stack 711 can be further formed by forming a cap 718' on the TFR 112.

In embodiments of the FRAM cell 400, the cell stack 711 can be formed by forming a bottom electrode 410 on the substrate 704, or on the bottom wire 150, or both, forming a ferroelectric layer 408 on the bottom electrode 410, forming a top electrode 406 on the ferroelectric layer 408, and forming a TFR 112 on the top electrode 406. In some embodiments, the cell stack 711 can be further formed by forming a cap 718' on the TFR 112.

In embodiments of the ECRAM cell 500, the cell stack 711 can be formed by forming a bottom electrode 510 on the substrate 704 and on the bottom wires 150, forming a mixed ionic and electronic conductor 512 on the bottom electrode 510, forming a barrier 520 on the mixed ionic and electronic conductor 512, forming a mixed ionic and electronic conductor 514 on the barrier 520, forming a top electrode 506 on the mixed ionic and electronic conductor 514, and forming a TFR 112 on the top electrode 506. In some embodiments, the cell stack 711 can be further formed by forming a cap 718' on the TFR 112.

In some implementations, the cell stack 711 may be formed by forming an NVM cell stack layer (block 808), forming a top electrode layer on the cell stack layer (block 810), and forming a TFR layer on the top electrode layer (block 812). For example, in an embodiment of the PCRAM cell 100, the cell stack 711 may be formed by forming a phase change material layer on the heating layer 704, forming a top electrode material layer on the heating layer, forming an etch stop TFR layer 716 on the top electrode material layer, and forming a capping layer 718 on the etch stop TFR layer 716.

In an embodiment of the RRAM 200, the cell stack 711 can be formed by forming a bottom electrode material layer 710 on the heating layer 704, forming an insulator material layer 712 on the bottom electrode material layer 710, forming a top electrode material layer 714 on the insulator material layer 712, forming an etch stop TFR layer 716 on the top electrode material layer 714, and forming a capping layer 718 on the etch stop TFR layer 716.

In an embodiment of the MRAM cell 300, the cell stack 711 can be formed by forming a bottom electrode material layer, forming a ferromagnetic pinned material layer on the bottom electrode material layer, forming a barrier material layer on the ferromagnetic pinned material layer, forming a top ferromagnetic free layer on the barrier material layer, forming a top electrode material layer on the top ferromagnetic free layer, forming an etch stop TFR layer 716 on the top electrode material layer, and forming a capping layer 718.

In an embodiment of the FRAM cell 400, the cell stack 711 can be formed by forming a bottom electrode material layer, forming a ferroelectric material layer on the bottom electrode material layer, forming a top electrode material layer on the ferroelectric material layer, forming an etch stop TFR layer 716 on the top electrode material layer, and forming a capping layer 718 on the etch stop TFR layer 716.

In an embodiment of the ECRAM cell 500, the cell stack 711 can be formed by forming a bottom electrode material layer on the substrate and on the first bottom wire, depositing a mixed ionic and electronic conductor material layer on the bottom electrode material layer, depositing a barrier material on the mixed ionic and electronic conductor material layer, depositing a mixed ionic and electronic conductor material layer on the barrier layer, depositing a top electrode material layer on the mixed ionic and electronic conductor material layer, depositing an etch stop TFR layer 716 on the gate electrode material layer, and depositing a capping layer 718 on the etch stop TFR layer 716.

In some implementations, cell stack 711 can be further formed by etching away undesired NVM cell stack layer portions and retaining desired NVM cell stack layer portions to form an NVM cell stack (block 814). For example, in an embodiment of PCRAM cell 100, cell stack 711 can be formed by retaining the volume of PCM 102 and removing undesired phase change material layer portions, retaining top electrode 106 and removing undesired top electrode material layer portions, retaining TFR 112 and removing undesired etch stop TFR layer 716 portions, or retaining cap 718' and removing undesired capping layer 718 portions, or combinations thereof.

In an embodiment of the RRAM cell 200, the cell stack 711 can be formed by retaining the bottom electrode 210 and removing unwanted portions of the bottom electrode material layer 710, by retaining the insulator material 202 and removing unwanted portions of the insulator material layer 712, by retaining the top electrode 206 and removing unwanted portions of the top electrode material layer 714, by retaining the TFR 112 and removing unwanted portions of the etch stop TFR layer 716, and by retaining the cap 718' and removing unwanted portions of the capping layer 718.

In an embodiment of the MRAM cell 300, the cell stack 711 can be formed by retaining the bottom electrode 312 and removing unwanted portions of the bottom electrode layer material, by retaining the ferromagnetic pinned layer 310 and removing unwanted portions of the ferromagnetic pinned material layer, by retaining the barrier layer 302 and removing unwanted portions of the barrier material layer, by retaining the top ferromagnetic free layer 304 and removing unwanted portions of the top ferromagnetic free layer, by retaining the TFR 112 and removing unwanted portions of the etch stop TFR layer 716, and by retaining the cap 718' and removing unwanted portions of the capping layer 718.

In an embodiment of the FRAM cell 400, the cell stack 711 can be formed by retaining the bottom electrode 410 and removing unwanted portions of the bottom electrode material layer, by retaining the ferroelectric layer 408 and removing unwanted portions of the ferroelectric material layer, by retaining the top electrode 406 and removing portions of the top electrode material layer, by retaining the TFR 112 and removing unwanted portions of the etch stop TFR layer 716, and by retaining the cap 718' and removing unwanted portions of the capping layer 718.

In embodiments of the ECRAM cell 500, the cell stack 711 can be formed by retaining the bottom electrode 510 and removing the unwanted portions of the bottom electrode material layer, by retaining the mixed ionic and electronic conductor 512 and removing the unwanted portions of the mixed ionic and electronic conductor material layer, by retaining the barrier 520 and removing the unwanted portions of the barrier material layer, by retaining the mixed ionic and electronic conductor 514 and removing the unwanted portions of the mixed ionic and electronic conductor material layer, by retaining the top electrode 506 and removing the unwanted portions of the top electrode material layer, by retaining the TFR 112 and removing the unwanted portions of the etch stop TFR layer 716, and by retaining the cap 718' and removing the unwanted portions of the capping layer 718.

In an embodiment of the CBRAM cell 900, the cell stack 711 can be formed by retaining the bottom electrode 910 and removing unwanted portions of the bottom electrode material layer 710, by retaining the solid electrolyte 902 and removing unwanted portions of the solid electrolyte layer, by retaining the top electrode 906 and removing unwanted portions of the top electrode material layer 714, by retaining the TFR 112 and removing unwanted portions of the etch stop TFR layer 716, and by retaining the cap 718' and removing unwanted portions of the capping layer 718.

The method 800 may continue by forming an encapsulation spacer on the sidewall of the NVM stack (block 816). For example, forming an encapsulation spacer 108, 208, 308, 408, 508, or the like on the sidewall of the NVM stack 711. The encapsulation spacer may be formed by forming an encapsulation layer on the substrate 700 or on the heating layer 704, as appropriate, and forming the encapsulation layer around the NVM stack (block 818).

The encapsulation spacer can be further formed by removing unwanted portions of the encapsulation layer (block 820). For example, the unwanted encapsulation layer portions are removed by chemical or physical etching. The desired or retained encapsulation layer portions effectively form encapsulation spacers 108, 208, 308, 408, 508, or the like, located on the sidewalls or flanks of the NVM stack (block 822).

The method 800 may continue by forming a top wire on the TFR 112, the encapsulating spacer, or both (block 824). For example, the top wire 140 may be formed in an ILD 730 formed above the top surface of the TFR 112 and above the top surface of the encapsulating spacer. Using the top surface of the TFR 112 as an etch stop, a wire trench 732 may be formed in the ILD 730 (block 826), thereby exposing the top surface of the TFR 112 and at least a portion of the top surface of the spacer 108, 208, 308, 408, 508, or the like. The top wire 150 may be formed by depositing a conductive material in the wire trench 732 such that the conductive material contacts the top surface of the TFR 112 and at least a portion of the spacer (block 828). Chemical-mechanical polishing may be used to planarize the top surfaces of the top wire 140 and the ILD 730. Method 800 may end at block 830.

Figure 19 shows a cross section of a CBRAM cell 900 including a TFR 112 according to various embodiments of the present invention.

CBRAM is a non-volatile solid-state memory technology that utilizes the growth of reversible conductive filaments (CFs) between metal plates, making the device low-resistivity. This basic storage unit ("cell") can be programmed into several different states or levels, which exhibit different resistive properties. These programmable cell states can be used to represent different data values, thereby enabling the storage of information.

A CBRAM cell may include a top electrode (anode) that is a sacrificial metal layer such as copper, silver, or the like. The cell further includes a thin film of a solid electrolyte such as GeS2, AlOx, GdOx, or MOx that forms an insulator layer sandwiched between the top and bottom electrodes. The bottom electrode (cathode) is made of an inert metal such as tungsten, platinum, or the like.

In a single-level CBRAM device, each cell can be set to one of s = 2 states: LRS and HRS, allowing for the storage of one bit per cell. When a voltage of a particular polarity is applied across the device, ions of the sacrificial active metal diffuse through the electrolyte and are reduced at the cathode. This leads to the formation of a conductive filament (CF) connecting the top and bottom electrodes, placing the device in the LRS or ON state. When a voltage of the opposite polarity is applied, the CF disappears and the device returns to the HRS or OFF state. These different states (LRS/HRS) represent the bit (1 or 0) stored in the cell.

Reading and writing data in a CBRAM cell is accomplished by applying appropriate voltages to the cell. During a write operation, the resulting programming signal either forms or does not form a CF to induce the desired cell state. Reading a CBRAM cell is performed using the cell resistance as a metric of the cell state. Applying a read voltage causes a current to flow through the cell, and this read current depends on the cell's resistance. Therefore, measuring the cell's read current provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing this resistance metric to a predetermined reference level for the programmable cell state.

The CBRAM cell 900 includes a solid electrolyte 902 disposed between a top electrode 906 and a bottom electrode 910. The cell state shown represents an intermediate state in which a CF 904 is formed in the insulator 902. When a read voltage is applied to read the programmed cell state, the resulting read current flows primarily through the current path through the CF 904 between the top electrode 906 and the bottom electrode 910, rather than through the solid electrolyte 902 where the CF 904 is not formed.

The CBRAM cell 900 further includes a TFR 112 located on top of the top electrode 906. The TFR 112 can mitigate the voltage flux imparted by relaxing ions. In ECRAM, after programming the cell 500, ions may relax across the barrier 520 again, causing the cell 500 to retain a certain voltage. In some applications, the TFR 112 can mitigate this effect of ions relaxing across the barrier 520 again. Additionally, if the cell 500 forms a short across the barrier 520, the TFR 112 provides a base resistance for discrimination, for example, to drop from a neural net. Furthermore, in some implementations, the conductivity of the top electrode 906 may be too high to drive optimal or desired state-change behavior in the solid electrolyte 902, and the TFR 112 acts as a current reduction means to limit or generally reduce the current flowing from the top electrode 906 through the solid electrolyte 902. The TFR 112 can act as a ballast resistor when the CF 904 of the CBRAM cell 900 is formed. As soon as the CF 904 connection is made between the electrodes, the current at a given voltage increases sharply, and the TFR 112 acts as the overall ballast resistor for the cell 900. This limitation of the current through the insulator 904 by the TFR 112 can improve the durability of the CBRAM cell 900 and limit adverse effects on components adjacent to the CBRAM cell 900.

An encapsulation spacer 908 may be placed on the sidewalls or lateral boundaries of the MIM stack and the TFR 112, or may be otherwise connected to the sidewalls or lateral boundaries of the MIM stack and the TFR 112. The top surface of the encapsulation spacer 908 may be coplanar with the top surface of the TFR 112, and the bottom surface of the encapsulation spacer 908 may be coplanar with the bottom surface of the bottom electrode 910.

In some implementations, the encapsulation spacer 908 can be omitted and instead, an ILD 730 can be formed, for example, as shown in FIG. 12 (i.e., the ILD 730 can contact the sidewalls or lateral boundaries of the MIM stack and the sidewalls or lateral boundaries of the TFR 112).

A top wire 140 may be connected to the top surface of the TFR 112, and a bottom wire 150 may be connected to the bottom electrode 910. As known in the art, the top wire 140 and/or the bottom wire 150 may be electrically connected to other components of the IC device, such as a memory controller or the like.

In FIG. 20, a CBRAM cell 900 includes a TFR 112 between the top electrode 906 and the top wire 140 and between the bottom electrode 910 and the bottom wire 150, in accordance with various embodiments of the present invention. The bottom electrode 910 should be interpreted as a bottom state-affecting electrode because it is the bottom conductive electrode in the cell 900 that is the inverse of the top electrode 906 (i.e., the top state-affecting electrode) across the horizontal bisector 691. To fabricate such a cell 900, an additional etch-stop TFR layer 716 can be formed between the bottom electrode 910 material layer and the heating layer 704 (if present) or between the bottom electrode 910 material layer and the substrate 700 (if the heating layer 704 is not present), in addition to other fabrication steps contemplated herein.

Encapsulation spacers 908 may be placed on the sidewalls or lateral boundaries of the cell layer sidewalls and the lateral boundaries of the symmetrical top and bottom TFR 112 layers, or may be otherwise connected to the sidewalls or lateral boundaries of the cell layer sidewalls and the lateral boundaries of the symmetrical top and bottom TFR 112 layers. The top surface of the encapsulation spacer 908 may be coplanar with the top surface of the top TFR 112, and the bottom surface of the encapsulation spacer 908 may be coplanar with the bottom surface of the bottom TFR 112. The top wire 140 may be connected to the top surface of the TFR 112, and the bottom wire 150 may be connected to the bottom TFR 112.

In FIG. 21, an ECRAM cell 500 includes a TFR 112 between the top electrode 506 and the top wire 140 and between the bottom electrode 510 and the bottom wire 150, in accordance with various embodiments of the present invention. The bottom electrode 510 should be interpreted as a bottom state-affecting electrode because it is the bottom conductive electrode in the cell 500 that is the inverse of the top electrode 506 (i.e., the top state-affecting electrode) across the horizontal bisector 691. To fabricate such a cell 500, an additional etch-stop TFR layer 716 can be formed between the bottom electrode 510 material layer and the substrate 700, in addition to other fabrication steps contemplated herein.

The encapsulation spacer 508 may be placed on the sidewalls or lateral boundaries of the cell layer sidewalls and the lateral boundaries of the symmetrical top and bottom TFR 112 layers, or may be otherwise connected to the sidewalls or lateral boundaries of the cell layer sidewalls and the lateral boundaries of the symmetrical top and bottom TFR 112 layers. The top surface of the encapsulation spacer 508 may be coplanar with the top surface of the top TFR 112, and the bottom surface of the encapsulation spacer 508 may be coplanar with the bottom surface of the bottom TFR 112. The top wire 140 may be connected to the top surface of the top TFR 112, and the bottom wire 150 may be connected to the bottom surface of the bottom TFR 112.

The accompanying figures and this description illustrate and describe embodiments of the present invention and their features and components. Those skilled in the art will recognize that the specific names used in this description are for convenience only, and that the present invention should not be limited by the specific processes identified or implied by such names. Accordingly, the embodiments described herein are intended in all respects to be illustrative and not restrictive, and reference should be made to the appended claims to determine the scope of the invention.

For clarity, the top surfaces of the various encapsulation spacers contemplated herein need not be coplanar with the top surface of the top TFR 112. In alternative embodiments, the top surfaces of the various encapsulation spacers may be coplanar with the bottom surface of the top TFR 112, may be located between the top surface of the top state-affecting electrode and the bottom surface of the top state-affecting electrode, or may be located in other similar locations. In general, the top surfaces of the encapsulation spacers contemplated herein may be higher than the top surface of the top state-change structure, and the bottom surfaces of the encapsulation spacers contemplated herein may be lower than the bottom surface of the lowest state-change structure in the cell.

Unless otherwise stated, or in addition to what is described herein, the terms "deposit," "depositing," "deposited," and the like, may include any now known or later developed technique suitable for depositing materials, including, but not limited to, CVD, LPCVD, PECVD, semi-atmosphere CVD (SACVD), high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitridation, spin-on deposition, physical vapor deposition (PVD), atomic level deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, or evaporation.

References herein to terms such as "vertical," "horizontal," and the like are made for illustrative purposes to establish a frame of reference and are not intended to be limiting. As used herein, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of the substrate 700, regardless of the substrate 700's actual spatial orientation. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Terms such as "on," "above," "below," "side" (as with respect to "sidewall," etc.), "higher," "lower," "over," "beneath," and "under" are defined with respect to the horizontal plane. It is understood that various other frames of reference may be used to describe the present invention without departing from the scope of the present invention.

Claims (12)

1. A non-volatile memory (NVM) including a non-volatile memory (NVM) cell ,
The NVM cell comprises:
a state change structure;
a top state-influencing electrode in contact with the state-change structure, the top state-influencing electrode changing a detectable attribute of the state-change structure, the detectable attribute of the state-change structure representing a data value;
a first thin film resistor (TFR) on the top state-affecting electrode and in contact with the top state-affecting electrode ;
a bottom state-affecting electrode in contact with the state-change structure;
a second TFR below the bottom state-affecting electrode and in contact with the bottom state-affecting electrode;
the NVM cell including:
a top wire over the NVM cell in contact with the first TFR;
a bottom wire beneath the NVM cell in contact with the second TFR;
Including NVM. The NVM of claim 1, wherein the first TFR electrically connects the top wire and the top state-affecting electrode in series. further comprising encapsulation spacers on the sidewalls of the state-change structure, on the sidewalls of the top state-affecting electrode, on the sidewalls of the bottom state-affecting electrode, and on the sidewalls of the first and second TFRs.
The NVM of claim 1 .
The NVM of claim 3, wherein the top wire is further connected to the encapsulation spacer. The NVM of claim 1, wherein the first TFR reduces current from the top wire to the top state-affecting electrode. The NVM of claim 1 , wherein the second TFR reduces current from the bottom state-affecting electrode to the bottom wire. 1. An integrated circuit (IC) device manufacturing method comprising:
forming a bottom thin film resistor (TFR) directly on the bottom wire;
forming a bottom state-affecting electrode in-line with the bottom wire directly on the bottom TFR, the bottom TFR electrically connecting the bottom wire and the bottom state-affecting electrode in series;
forming a state-change structure on the bottom state-affecting electrode;
forming a top state-affecting electrode directly on the state-change structure, the top state-affecting electrode changing a detectable attribute of the state-change structure, the detectable attribute of the state-change structure representing a data value; and forming a top TFR directly on the top state-affecting electrode. 8. The IC device manufacturing method of claim 7, further comprising: forming an encapsulation spacer on at least one sidewall of the bottom TFR, on a sidewall of the bottom state-affecting electrode, on a sidewall of the state-change structure, on a sidewall of the top state-affecting electrode, and on a sidewall of the top TFR . The IC device manufacturing method of claim 7 or 8 , further comprising: forming a cap directly on the top TFR. 10. The IC device manufacturing method of claim 9 , further comprising: forming a blanket inter-level dielectric (ILD) layer having a top surface on the top surface of the cap. further comprising etching a top wire trench in the ILD using the top TFR as an etch stop, the etching exposing a top surface of the top TFR.
11. The IC device manufacturing method of claim 10 . forming a top wire in the top wire trench and on the exposed top surface of the top TFR, the top TFR electrically connecting the top wire and the top state-affecting electrode in series;
12. The IC device manufacturing method of claim 11.