JP7726320B2 - Image pickup element and image pickup device - Google Patents

Description

The present invention relates to a solid-state imaging device and an imaging device using the same.

Patent Document 1 below discloses a solid-state imaging device that includes a plurality of pixels, at least two of which each include (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance portion, and (c) an input portion to an amplifier, and a connecting switch that selectively connects the charge-voltage conversion regions together.

Special Publication No. 2008-546313

In the conventional solid-state imaging device, by turning on the connection switch and connecting the charge-voltage conversion regions, the number of saturated electrons in all connected charge-voltage conversion regions is increased, thereby expanding the dynamic range.

Furthermore, in the conventional solid-state imaging device, by turning off the connection switch and isolating the charge-voltage conversion region from other charge-voltage conversion regions, the charge-voltage conversion capacity decreases and the charge-voltage conversion coefficient increases, thereby increasing the signal-to-noise ratio during high-sensitivity readout.

However, with the conventional solid-state imaging device, even if the connection switch was turned off, the signal-to-noise ratio during high-sensitivity readout could not be significantly increased.

The present invention was made in consideration of these circumstances, and aims to provide a solid-state imaging element that can expand the dynamic range and improve the signal-to-noise ratio during high-sensitivity readout, as well as an imaging device using the same.

The following aspects are presented as means for solving the above problem. A solid-state imaging device according to the first aspect includes a plurality of pixel blocks each having one photoelectric conversion unit, a node, and a transfer switch corresponding to the one photoelectric conversion unit for transferring charge from the photoelectric conversion unit to the node; an electrical connection unit provided between the node of one of the pixel blocks and the node of another of the pixel blocks; and a plurality of link switches provided in the connection unit, one for each of the pixel blocks.

The pixel block may have only one photoelectric conversion unit and be composed of one pixel, or may have two or more photoelectric conversion units and be composed of multiple pixels. This also applies to the various aspects described below.

A solid-state imaging device according to a second aspect is similar to the first aspect in that it includes a control unit that controls the connection switch, and the control unit controls the connection switch so that the connection unit is electrically disconnected from the node of the pixel block in a first operating mode, and the control unit controls the connection switch so that the connection unit is electrically connected to the node of the pixel block in a second operating mode.

In the solid-state imaging device according to the third aspect, in the second aspect, the control unit controls the connecting switches in the second operating mode so that one or more predetermined number of the connecting switches that are in an on state are electrically connected to the node of the pixel block.

The solid-state imaging device according to the fourth aspect is the first aspect, wherein the nodes of three or more of the plurality of pixel blocks are connected in a daisy chain fashion by a plurality of the connection portions.

A solid-state imaging device according to a fifth aspect is the same as that of the fourth aspect, but includes a control unit that controls the connection switch, and in a first operating mode, the control unit controls the connection switch so that the connection portion is electrically disconnected from the node of one of the three or more pixel blocks, and in a second operating mode, the control unit controls the connection switch so that the connection portion is electrically connected to the node of the one of the three or more pixel blocks.

A solid-state imaging device according to a sixth aspect is the fifth aspect, wherein the control unit controls the connecting switches in the second operating mode so that a predetermined number of one or more of the connecting switches that are in an on state are electrically connected to the node of one of the three or more pixel blocks.

The solid-state imaging device according to the seventh aspect is any one of the first to sixth aspects, wherein each pixel block has a plurality of photoelectric conversion units and a plurality of transfer switches.

The solid-state imaging device according to the eighth aspect comprises a plurality of pixel blocks each having a plurality of photoelectric conversion units, a node, and a plurality of transfer switches respectively corresponding to the plurality of photoelectric conversion units and transferring electric charges from the plurality of photoelectric conversion units to the node, and a plurality of connecting switches provided between the nodes of two adjacent pixel blocks.

A solid-state imaging device according to a ninth aspect is the same as that of the eighth aspect, and further includes a control unit that controls the connecting switches, wherein the control unit controls the connecting switches in a first operating mode so that none of the connecting switches that are in an on state are electrically connected to the node of one of the two pixel blocks, and the control unit controls the connecting switches in a second operating mode so that one or more predetermined number of the connecting switches that are in an on state are electrically connected to the node of the one pixel block.

The solid-state imaging device according to the tenth aspect is the eighth aspect, wherein the nodes of three or more of the plurality of pixel blocks are connected in a daisy chain fashion by two or more sets of the plurality of connecting switches.

The solid-state imaging device according to an eleventh aspect is the same as the tenth aspect, but includes a control unit that controls the connecting switches, and in a first operating mode, the control unit controls the connecting switches so that none of the connecting switches that are in an on state are electrically connected to the node of one of the three or more pixel blocks, and in a second operating mode, the control unit controls the connecting switches so that one or more predetermined number of the connecting switches that are in an on state are electrically connected to the node of the one pixel block.

A solid-state imaging device according to a twelfth aspect is any one of the seventh to eleventh aspects, wherein the transfer switches are transistors, and in each pixel block, a diffusion region serving as the source or drain of one of the transfer switches and a diffusion region serving as the source or drain of another of the transfer switches are shared by a single diffusion region provided between one of the photoelectric conversion units and another of the photoelectric conversion units, and in each pixel block, the gate electrode of the one transfer switch is arranged on the photoelectric conversion unit side of the one diffusion region, and in each pixel block, the gate electrode of the other transfer switch is arranged on the other photoelectric conversion unit side of the one diffusion region.

A solid-state imaging device according to a thirteenth aspect is any one of the seventh to twelfth aspects, wherein the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are each two.

A solid-state imaging device according to a fourteenth aspect is the thirteenth aspect, wherein the number of the plurality of linking switches is two, and the amount of positional deviation in a predetermined direction between one of the plurality of linking switches and another of the plurality of linking switches is greater than the pitch in the predetermined direction of the plurality of photoelectric conversion units but less than twice the pitch.

A solid-state imaging device according to a fifteenth aspect is any one of the first to fourteenth aspects, wherein the number of the plurality of linking switches is two, and the value of the capacitance between the connection between the plurality of linking switches and the reference potential when the plurality of linking switches are off is within a range of ±20% of the value of the capacitance between the node and the reference potential when the plurality of linking switches are off.

A solid-state imaging device according to a sixteenth aspect is any one of the first to fifteenth aspects, in which the number of the plurality of linking switches is two, the width of at least a portion of the wiring constituting the connection between the plurality of linking switches when the plurality of linking switches are off is wider than the width of the other wiring within the pixel block, a MOS capacitor is connected to the connection, and a diffusion capacitor that is not part of each of the linking switches is connected to the connection.

A solid-state imaging device according to a seventeenth aspect includes a plurality of pixel blocks each having one photoelectric conversion unit, a first node, and one transfer switch corresponding to the one photoelectric conversion unit for transferring charge from the photoelectric conversion unit to the first node; two second nodes corresponding to the first node of one of the pixel blocks and the first node of another of the pixel blocks, respectively; two first switch units electrically connecting and disconnecting the first node of one of the pixel blocks and the first node of the other of the pixel blocks to the two second nodes, respectively; and a second switch unit electrically connecting and disconnecting the two second nodes.

The solid-state imaging device according to the eighteenth aspect is the seventeenth aspect, and further includes a control unit that controls the first switch units and the second switch units. In a first operating mode, the control unit controls the first switch units so that the first switch units that electrically connect and disconnect the first node of the one pixel block and the corresponding second node are turned off. In a second operating mode, the control unit controls the first switch units and the second switch units so that one or more predetermined number of the first switch units and the second switch units that are in the on state are electrically connected to the first node of the one pixel block.

A solid-state imaging device according to a 19th aspect is the 17th aspect, and further includes three or more first switch units that electrically connect and disconnect the first nodes of three or more pixel blocks among the plurality of pixel blocks to three or more second nodes corresponding to these three or more first nodes, and the three or more second nodes are connected in a daisy chain manner by a plurality of second switch units.

A solid-state imaging device according to a twentieth aspect is the same as that of the nineteenth aspect, and further includes a control unit that controls the first switch units and the second switch units. In a first operating mode, the control unit controls the first switch unit of one of the three or more pixel blocks so that the first switch unit that electrically connects and disconnects the first node of one of the three or more pixel blocks to the corresponding second node is turned off. In a second operating mode, the control unit controls the first switch unit and the second switch unit so that one or more predetermined number of the first switch units and the second switch units that are in the on state are electrically connected to the first node of the one of the three or more pixel blocks.

The solid-state imaging device according to the 21st aspect is any one of the 17th to 20th aspects, wherein each pixel block has a plurality of photoelectric conversion units and a plurality of transfer switches.

A solid-state imaging device according to a 22nd aspect is the 21st aspect, wherein the transfer switches are transistors, and in each pixel block, a diffusion region serving as the source or drain of one of the transfer switches and a diffusion region serving as the source or drain of another of the transfer switches are shared by a single diffusion region provided between one of the photoelectric conversion units and another of the photoelectric conversion units, and in each pixel block, the gate electrode of the one transfer switch is arranged on the photoelectric conversion unit side of the one diffusion region, and in each pixel block, the gate electrode of the other transfer switch is arranged on the other photoelectric conversion unit side of the one diffusion region.

The solid-state imaging device according to the 23rd aspect is the 21st or 22nd aspect, wherein the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are each two.

A solid-state imaging device according to the 24th aspect is any one of the 17th to 23rd aspects, wherein the value of the capacitance between the second node and the reference potential when each of the first switch units and each of the second switch units is in the off state is within a range of ±20% of the value of the capacitance between the first node and the reference potential when the first switch unit is in the off state.

A solid-state imaging device according to the 25th aspect is any one of the 17th to 24th aspects, and satisfies one or more of the following: the width of at least a portion of the wiring connected to the second node is wider than the width of other wiring within the pixel block; a MOS capacitor is connected to the second node; and a diffusion capacitor that is not part of either the first switch unit or the second switch unit is connected to the second gate.

The imaging device according to the 26th aspect is equipped with a solid-state imaging element according to any one of the first to 25th aspects.

An imaging device according to a 27th aspect includes a solid-state imaging element according to any one of the second, third, fifth, sixth, ninth, eleventh, eighteenth and twentieth aspects, and a control means for switching between the first operating mode and the second operating mode depending on the set value of ISO sensitivity.
As means for solving the above problems, the following aspects are also presented: An imaging element according to a first surface includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and that is arranged adjacent to the first photoelectric conversion unit in the column direction, a first diffusion unit to which the electric charges converted by the first photoelectric conversion unit are transferred, a second diffusion unit to which the electric charges converted by the second photoelectric conversion unit are transferred, a first transistor electrically connected to the first diffusion unit via a first wiring, and a second transistor electrically connected to the second diffusion unit via a second wiring, wherein the first transistor and the second transistor are connected in series in a connection path that electrically connects the first diffusion unit and the second diffusion unit.
The second surface imaging element is the imaging element of the first surface, and includes a first reset transistor for electrically connecting the first diffusion portion to a supply portion to which a predetermined voltage is supplied, and a second reset transistor for electrically connecting the second diffusion portion to the supply portion.
The imaging element according to the third surface is the imaging element according to the first surface, further comprising a first reset transistor for resetting the voltage of the first diffusion portion and a second reset transistor for resetting the voltage of the second diffusion portion.
The fourth surface imaging element is an imaging element of the second or third surface, in which the first transistor is formed using at least a part of the diffusion portion that forms the first reset transistor, and the second transistor is formed using at least a part of the diffusion portion that forms the second reset transistor.
An imaging element according to a fifth aspect is an imaging element according to any one of the second to fourth aspects, wherein either the drain of the first transistor or the source of the first transistor is formed using at least a part of a diffusion portion that forms either the drain of the first reset transistor or the source of the first reset transistor, and either the drain of the second transistor or the source of the second transistor is formed using at least a part of a diffusion portion that forms either the drain of the second reset transistor or the source of the second reset transistor.
An imaging element according to a sixth aspect is an imaging element according to any one of the second to fifth aspects, wherein either the drain of the first transistor or the source of the first transistor forms either the drain of the first reset transistor or the source of the first reset transistor, and either the drain of the second transistor or the source of the second transistor forms either the drain of the second reset transistor or the source of the second reset transistor.
The imaging element having the seventh surface is an imaging element having any one of the second to sixth surfaces, in which the distance from the first diffusion portion to the gate of the first transistor is longer than the distance from the first diffusion portion to the gate of the first reset transistor, and the distance from the second diffusion portion to the gate of the second transistor is longer than the distance from the first diffusion portion to the gate of the second reset transistor.
An imaging element having an eighth surface is an imaging element having any one of the second to seventh surfaces, in which the gate of the first transistor is positioned farther from the first diffusion portion than the gate of the first reset transistor, and the gate of the second transistor is positioned farther from the second diffusion portion than the gate of the second reset transistor.
The imaging element according to the ninth aspect is an imaging element according to any one of the second to eighth aspects, which comprises a first amplifying transistor having a gate electrically connected to the first diffusion portion, and a second amplifying transistor having a gate electrically connected to the second diffusion portion.
The imaging element according to the tenth aspect is the imaging element according to the ninth aspect, wherein the gate of the first amplifying transistor is larger than the gate of the first transistor, and the gate of the second amplifying transistor is larger than the gate of the second transistor.
An imaging element according to an eleventh aspect is an imaging element according to the ninth or tenth aspect, wherein the gate width of the first amplifying transistor is larger than the gate width of the first transistor, and the gate width of the second amplifying transistor is larger than the gate width of the second transistor.
The imaging element according to the twelfth aspect is an imaging element according to any one of the ninth to eleventh aspects, wherein the gate length of the first amplifying transistor is greater than the gate length of the first transistor, and the gate length of the second amplifying transistor is greater than the gate length of the second transistor.
An imaging element according to the thirteenth aspect is an imaging element according to any one of the ninth to twelfth aspects, in which the gate of the first amplifying transistor is larger than the gate of the first reset transistor, and the gate of the second amplifying transistor is larger than the gate of the second reset transistor.
An imaging element according to the fourteenth surface is an imaging element according to any one of the ninth to thirteenth surfaces, in which the gate width of the first amplifying transistor is larger than the gate width of the first reset transistor, and the gate width of the second amplifying transistor is larger than the gate width of the second reset transistor.
The imaging element according to the fifteenth aspect is an imaging element according to any one of the ninth to fourteenth aspects, wherein the gate length of the first amplifying transistor is greater than the gate length of the first reset transistor, and the gate length of the second amplifying transistor is greater than the gate length of the second reset transistor.
The imaging element according to the 16th surface is an imaging element according to any one of the 9th to 15th surfaces, wherein the distance from the gate of the first reset transistor to the gate of the first transistor is shorter than the distance from the gate of the first amplifying transistor to the gate of the first transistor, and the distance from the gate of the second reset transistor to the gate of the second transistor is shorter than the distance from the gate of the second amplifying transistor to the gate of the second transistor.
The imaging element according to the seventeenth aspect is an imaging element according to any one of the ninth to sixteenth aspects, in which the gate of the first transistor is positioned farther from the gate of the first amplifying transistor than the gate of the first reset transistor, and the gate of the second transistor is positioned farther from the gate of the second amplifying transistor than the gate of the second reset transistor.
The imaging element according to the 18th surface is an imaging element according to any one of the 9th to 17th surfaces, which comprises a first selection transistor electrically connected to the first amplification transistor and a second selection transistor electrically connected to the second amplification transistor.
The imaging element according to the 19th surface is the imaging element according to the 18th surface, in which the gate of the first amplifying transistor is larger than the gate of the first selection transistor, and the gate of the second amplifying transistor is larger than the gate of the second selection transistor.
The imaging element according to the 20th surface is an imaging element according to the 18th or 19th surface, in which the gate width of the first amplifying transistor is larger than the gate width of the first selection transistor, and the gate width of the second amplifying transistor is larger than the gate width of the second selection transistor.
The imaging element according to the 21st surface is an imaging element according to any one of the 18th to 20th surfaces, in which the gate length of the first amplifying transistor is greater than the gate length of the first selection transistor, and the gate length of the second amplifying transistor is greater than the gate length of the second selection transistor.
The imaging element having the 22nd surface is an imaging element having any of the 18th to 21st surfaces, in which the first amplifying transistor is formed using at least a part of the diffusion portion that forms the first selection transistor, and the second amplifying transistor is formed using at least a part of the diffusion portion that forms the second selection transistor.
The imaging element according to the 23rd surface is an imaging element according to any one of the 18th to 22nd surfaces, in which the first amplifying transistor and the first selecting transistor are formed so as to share at least a portion of one diffusion region, and the second amplifying transistor and the second selecting transistor are formed so as to share at least a portion of one diffusion region.
The imaging element according to the 24th surface is an imaging element according to the 18th or 23rd surface, wherein either the drain of the first amplifying transistor or the source of the first amplifying transistor is formed using at least a part of the diffusion portion that forms either the drain of the first selection transistor or the source of the first selection transistor, and either the drain of the second amplifying transistor or the source of the second amplifying transistor is formed using at least a part of the diffusion portion that forms either the drain of the second selection transistor or the source of the second selection transistor.
An imaging element according to the 25th surface is an imaging element according to any one of the 18th to 24th surfaces, wherein either the drain of the first amplifying transistor or the source of the first amplifying transistor forms either the drain of the first selection transistor or the source of the first selection transistor, and either the drain of the second amplifying transistor or the source of the second amplifying transistor forms either the drain of the second selection transistor or the source of the second selection transistor.
The imaging element according to the 26th surface is an imaging element according to any one of the 18th to 25th surfaces, wherein the distance from the gate of the first reset transistor to the gate of the first transistor is shorter than the distance from the gate of the first selection transistor to the gate of the first transistor, and the distance from the gate of the second reset transistor to the gate of the second transistor is shorter than the distance from the gate of the second selection transistor to the gate of the second transistor.
An imaging element according to the 27th surface is an imaging element according to any one of the 18th to 26th surfaces, in which the gate of the first transistor is positioned farther from the gate of the first selection transistor than the gate of the first reset transistor, and the gate of the second transistor is positioned farther from the gate of the second selection transistor than the gate of the second reset transistor.
The imaging element according to the 28th surface is an imaging element according to the first surface, which includes a first amplifying transistor having a gate electrically connected to the first diffusion portion, and a second amplifying transistor having a gate electrically connected to the second diffusion portion.
The imaging element according to the 29th aspect is the imaging element according to the 28th aspect, wherein the gate of the first amplifying transistor is larger than the gate of the first transistor, and the gate of the second amplifying transistor is larger than the gate of the second transistor.
The imaging element according to the 30th aspect is an imaging element according to the 28th or 29th aspect, wherein the gate width of the first amplifying transistor is larger than the gate width of the first transistor, and the gate width of the second amplifying transistor is larger than the gate width of the second transistor.
The imaging element according to the 31st aspect is an imaging element according to any one of the 28th to 30th aspects, in which the gate length of the first amplifying transistor is greater than the gate length of the first transistor, and the gate length of the second amplifying transistor is greater than the gate length of the second transistor.
The imaging element having the 32nd surface is an imaging element having any one of the 28th to 31st surfaces, in which the distance from the first diffusion portion to the gate of the first transistor is longer than the distance from the first diffusion portion to the gate of the first amplifying transistor, and the distance from the second diffusion portion to the gate of the second transistor is longer than the distance from the first diffusion portion to the gate of the second amplifying transistor.
An imaging element with a 33rd surface is an imaging element with any one of the 28th to 32nd surfaces, in which the gate of the first transistor is positioned farther from the first diffusion portion than the gate of the first amplifying transistor, and the gate of the second transistor is positioned farther from the second diffusion portion than the gate of the second amplifying transistor.
The imaging element according to the 34th surface is an imaging element according to any one of the 28th to 33rd surfaces, which comprises a first selection transistor electrically connected to the first amplification transistor and a second selection transistor electrically connected to the second amplification transistor.
The imaging element according to the 35th surface is the imaging element according to the 34th surface, in which the gate of the first amplifying transistor is larger than the gate of the first selection transistor, and the gate of the second amplifying transistor is larger than the gate of the second selection transistor.
The imaging element according to the 36th surface is an imaging element according to the 34th or 35th surface, in which the gate width of the first amplifying transistor is larger than the gate width of the first selection transistor, and the gate width of the second amplifying transistor is larger than the gate width of the second selection transistor.
The imaging element according to the 37th surface is an imaging element according to any one of the 34th to 36th surfaces, in which the gate length of the first amplifying transistor is greater than the gate length of the first selection transistor, and the gate length of the second amplifying transistor is greater than the gate length of the second selection transistor.
The imaging element according to the 38th surface is an imaging element according to any one of the 34th to 37th surfaces, wherein the first amplifying transistor is formed using at least a part of the diffusion portion that forms the first selection transistor, and the second amplifying transistor is formed using at least a part of the diffusion portion that forms the second selection transistor.
The imaging element according to the 39th surface is an imaging element according to the 34th or 38th surface, wherein either the drain of the first amplifying transistor or the source of the first amplifying transistor is formed using at least a part of the diffusion portion that forms either the drain of the first selection transistor or the source of the first selection transistor, and either the drain of the second amplifying transistor or the source of the second amplifying transistor is formed using at least a part of the diffusion portion that forms either the drain of the second selection transistor or the source of the second selection transistor.
An imaging element according to the 40th surface is an imaging element according to any one of the 34th to 39th surfaces, wherein either the drain of the first amplifying transistor or the source of the first amplifying transistor forms either the drain of the first selection transistor or the source of the first selection transistor, and either the drain of the second amplifying transistor or the source of the second amplifying transistor forms either the drain of the second selection transistor or the source of the second selection transistor.
The imaging element according to the 41st surface is an imaging element according to any one of the 34th to 40th surfaces, wherein the distance from the gate of the first amplifying transistor to the gate of the first transistor is shorter than the distance from the gate of the first selection transistor to the gate of the first transistor, and the distance from the gate of the second amplifying transistor to the gate of the second transistor is shorter than the distance from the gate of the second selection transistor to the gate of the second transistor.
The imaging element having the 42nd surface is an imaging element having any one of the 34th to 41st surfaces, in which the gate of the first transistor is positioned farther from the gate of the first selection transistor than the gate of the first amplification transistor, and the gate of the second transistor is positioned farther from the gate of the second selection transistor than the gate of the second amplification transistor.
The imaging element according to the 43rd surface is an imaging element according to any one of the 1st to 42nd surfaces, in which the first transistor and the second transistor are electrically connected in the connection path via a third transistor.
The 44th image sensor is the image sensor according to the 43rd surface, wherein the first transistor, the second transistor, and the third transistor are connected in series in the connection path.
The imaging element according to the 45th surface is an imaging element according to any one of the 1st to 42nd surfaces, in which the first transistor and the second transistor are electrically connected via a plurality of transistors connected in series in the connection path.
The imaging element with the 46th surface is an imaging element with any one of the 1st to 45th surfaces, and includes a photoelectric conversion unit that converts light into electric charges, a third photoelectric conversion unit that is arranged next to the first photoelectric conversion unit, and a fourth photoelectric conversion unit that converts light into electric charges, that is arranged next to the second photoelectric conversion unit, and the first diffusion unit transfers the electric charges converted by the third photoelectric conversion unit, and the second diffusion unit transfers the electric charges converted by the fourth photoelectric conversion unit.
The 47th surface imaging element is an imaging element having the 46th surface, in which the third photoelectric conversion unit is arranged next to the first photoelectric conversion unit in the column direction, and the fourth photoelectric conversion unit is arranged next to the second photoelectric conversion unit in the column direction.
The imaging element with the 48th surface is an imaging element with the 46th or 47th surface, which is provided with a first transfer transistor that transfers the charges converted in the first photoelectric conversion unit to the first diffusion unit, a second transfer transistor that transfers the charges converted in the second photoelectric conversion unit to the second diffusion unit, a third transfer transistor that transfers the charges converted in the third photoelectric conversion unit to the first diffusion unit, and a fourth transfer transistor that transfers the charges converted in the fourth photoelectric conversion unit to the second diffusion unit.
The imaging element with the 49th surface is an imaging element with the 48th surface, wherein the first transfer transistor and the third transfer transistor are arranged so that the direction in which the charges converted by the first photoelectric conversion unit are transferred from the first photoelectric conversion unit to the first diffusion unit is different from the direction in which the charges converted by the third photoelectric conversion unit are transferred from the third photoelectric conversion unit to the first diffusion unit, and the second transfer transistor and the fourth transfer transistor are arranged so that the direction in which the charges converted by the second photoelectric conversion unit are transferred from the second photoelectric conversion unit to the second diffusion unit is different from the direction in which the charges converted by the fourth photoelectric conversion unit are transferred from the fourth photoelectric conversion unit to the second diffusion unit.
The imaging element according to the 50th surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit controls so that the first transistor is turned off at the first timing and so that the second transistor is turned off at the second timing.
The imaging element according to the 51st surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit controls so that the first transistor is off and the second transistor is off at the first timing, and so that the first transistor is off and the second transistor is off at the second timing.
The imaging element according to the 52nd surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit controls so that at the first timing, the first transistor is on and the second transistor is off, and at the second timing, the control unit controls so that the first transistor is off and the second transistor is on.
The imaging element according to the 53rd surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted in the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted in the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit controls so that the first transistor is on and the second transistor is on at the first timing, and so that the first transistor is on and the second transistor is on at the second timing.
An imaging element according to a 54th surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes either one of a first mode in which the control unit controls so that the first transistor is off at the first timing and so that the second transistor is off at the second timing, and a second mode in which the control unit controls so that the first transistor is on and the second transistor is off at the first timing and so that the first transistor is off and the second transistor is on at the second timing.
An imaging element according to a 55th surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted in the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted in the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes either one of a first mode in which, at the first timing, the first transistor is controlled to be off and the second transistor is controlled to be off, and at the second timing, the first transistor is controlled to be off and the second transistor is controlled to be off, and a second mode in which, at the first timing, the first transistor is controlled to be on and the second transistor is controlled to be off, and at the second timing, the first transistor is controlled to be off and the second transistor is controlled to be on.
An imaging element according to a 56th surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted in the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted in the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes either one of a first mode in which the control unit controls so that the first transistor is off at the first timing and so that the second transistor is off at the second timing, and a second mode in which the control unit controls so that the first transistor is on and the second transistor is on at the first timing and so that the first transistor is on and the second transistor is on at the second timing.
An imaging element according to a 57th surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes either a first mode in which, at the first timing, the first transistor is controlled to be off and the second transistor is controlled to be off, and at the second timing, the first transistor is controlled to be off and the second transistor is controlled to be off, or a second mode in which, at the first timing, the first transistor is controlled to be on and the second transistor is controlled to be on, and at the second timing, the first transistor is controlled to be on and the second transistor is controlled to be on.
An imaging element according to a 58th surface is an imaging element according to any one of the 1st to 49th surfaces, and is provided with a control unit that controls so that a first timing at which the charges converted in the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted in the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes either a first mode in which, at the first timing, the first transistor is controlled to be on and the second transistor is controlled to be off, and at the second timing, the first transistor is controlled to be off and the second transistor is controlled to be on, or a second mode in which, at the first timing, the first transistor is controlled to be on and the second transistor is controlled to be on, and at the second timing, the first transistor is controlled to be on and the second transistor is controlled to be on.
An imaging element according to a 59th aspect is an imaging element according to any one of the 1st to 49th aspects, and includes a control unit that controls so that a first timing at which charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes one of a first mode in which the control unit controls so that the first transistor is off at the first timing and so that the second transistor is off at the second timing, a second mode in which the control unit controls so that the first transistor is on and the second transistor is off at the first timing and so that the first transistor is off and the second transistor is on at the second timing, and a third mode in which the control unit controls so that the first transistor is on and the second transistor is on at the first timing and so that the first transistor is on and the second transistor is on at the second timing.
An imaging element according to a 60th aspect is an imaging element according to any one of the 1st to 49th aspects, which includes a control unit that controls so that a first timing at which charges converted in the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which charges converted in the second photoelectric conversion unit are transferred to the second diffusion unit are different timings, and the control unit executes one of a first mode in which the control unit controls so that the first transistor is off and the second transistor is off at the first timing, and so that the first transistor is off and the second transistor is off at the second timing; a second mode in which the control unit controls so that the first transistor is on and the second transistor is off at the first timing, and so that the first transistor is off and the second transistor is on at the second timing; and a third mode in which the control unit controls so that the first transistor is on and the second transistor is on at the first timing, and so that the first transistor is on and the second transistor is on at the second timing.
An imaging device according to a sixty-first aspect includes an imaging element according to any one of the first to sixtieth aspects.
An imaging device according to a sixty-second aspect is the imaging device according to the sixty-first aspect, further comprising an imaging control unit that controls the imaging element.
An imaging device according to a sixty-third aspect is the imaging device according to the sixty-second aspect, wherein the imaging control unit controls an operation of the first transistor and an operation of the second transistor.
An imaging device according to a 64th aspect is the imaging device according to the 63rd aspect, wherein the imaging control unit controls the operation of the first transistor and the operation of the second transistor based on a set ISO sensitivity.
An imaging device according to a sixty-fifth aspect is the imaging device according to any one of the sixty-first to sixty-fourth aspects, further comprising a drive unit for driving a photographing lens that emits light to the imaging element.
An imaging device according to a sixty-sixth aspect is the imaging device according to the sixty-fifth aspect, further comprising the photographing lens.

The present invention provides a solid-state imaging element that can expand the dynamic range and improve the signal-to-noise ratio during high-sensitivity readout, as well as an imaging device using the same.

1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention; FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device in FIG. 1 . FIG. 3 is an enlarged circuit diagram showing the vicinity of three pixel blocks in FIG. 2. FIG. 4 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 3; FIG. 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block in FIG. 4. 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2 . 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2 . 10 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 2 . FIG. 10 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device according to a comparative example. FIG. 10 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 9; FIG. 10 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device of an electronic camera according to a second embodiment of the present invention. FIG. 12 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 11 . FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a third embodiment of the present invention. FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a fourth embodiment of the present invention. FIG. 15 is an enlarged circuit diagram showing the vicinity of four pixel blocks in FIG. 14. 15 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 14. 15 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 14. 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 14. 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 14. 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. 14. FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a fifth embodiment of the present invention.

The solid-state imaging element and imaging device according to the present invention will be described below with reference to the drawings.

[First embodiment]
FIG. 1 is a schematic block diagram showing an electronic camera 1 according to a first embodiment of the present invention.

The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices, such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, and electronic cameras such as video cameras that capture moving images.

A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of this photographing lens 2 are driven by a lens control unit 3. The imaging surface of a solid-state image sensor 4 is located in the image space of this photographing lens 2.

The solid-state image sensor 4 is driven by commands from the image capture control unit 5 and outputs a digital image signal. During normal actual shooting (still image shooting), the image capture control unit 5 controls the solid-state image sensor 4 to perform a predetermined readout operation after, for example, performing a so-called global reset in which all pixels are reset simultaneously, followed by exposure using a mechanical shutter (not shown). In electronic viewfinder mode or video shooting, the image capture control unit 5 controls the solid-state image sensor 4 to perform a predetermined readout operation while using, for example, a so-called rolling electronic shutter. In these cases, the image capture control unit 5 controls the solid-state image sensor 4 to perform a readout operation in each operating mode, as described below, depending on the ISO sensitivity setting. The digital signal processing unit 6 performs image processing, such as digital amplification, color interpolation, and white balance adjustment, on the digital image signal output from the solid-state image sensor 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in memory 7. Memory 7 is connected to bus 8. The bus 8 is also connected to the lens control unit 3, imaging control unit 5, CPU 9, display unit 10 such as an LCD panel, recording unit 11, image compression unit 12, and image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set using the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

When an instruction to select electronic viewfinder mode, video recording, or normal main shooting (still image recording) is issued via the operation unit 14, the CPU 9 within the electronic camera 1 drives the imaging control unit 5 accordingly. At this time, the lens control unit 3 adjusts the focus and aperture as appropriate. The solid-state image sensor 4 is driven by commands from the imaging control unit 5 to output a digital image signal. The digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and then stored in memory 7. In electronic viewfinder mode, the CPU 9 displays the image signal on the display unit 10, and during video recording, the CPU 9 records the image signal on the recording medium 11a. During normal main shooting (still image recording), the CPU 9 processes the digital image signal from the solid-state image sensor 4 in the digital signal processing unit 6 and stores it in memory 7. Based on commands from the operation unit 14, the CPU 9 then performs the desired processing as necessary via the image processing unit 13 or image compression unit 12, and then outputs the processed signal to the recording unit 11, which records the signal on the recording medium 11a.

Figure 2 is a circuit diagram showing the general configuration of the solid-state imaging element 4 in Figure 1. Figure 3 is a circuit diagram showing an enlarged view of the vicinity of three pixel blocks BL arranged in succession in the column direction in Figure 2. Figure 4 is a schematic plan view showing the vicinity of the three pixel blocks BL shown in Figure 3. Figure 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block BL in Figure 4. In this embodiment, the solid-state imaging element 4 is configured as a CMOS-type solid-state imaging element, but is not limited to this and may be configured as, for example, another XY-address type solid-state imaging element.

As shown in Figures 2 to 4, the solid-state imaging device 4 includes pixel blocks BL arranged in a two-dimensional matrix of N rows and M columns, each having two pixels PX (PXA, PXB); multiple connecting transistors SWa and SWb serving as connecting switches per pixel block BL; a vertical scanning circuit 21; control lines 22 to 27 provided for each row of pixel blocks BL; multiple (M) vertical signal lines 28 provided for each column of pixels PX (for each column of pixel blocks BL) and receiving signals from the pixels PX (pixel blocks BL) in the corresponding column; a constant current source 29 provided for each vertical signal line 28; a column amplifier 30, a CDS circuit (correlated double sampling circuit) 31, an A/D converter 32, and a horizontal readout circuit 33, all of which are provided corresponding to each vertical signal line 28.

The column amplifier 30 may be an analog amplifier or a so-called switched capacitor amplifier. Also, the column amplifier 30 does not necessarily have to be provided.

For convenience of illustration, Figure 2 shows M = 2, but in reality the number of columns M can be any larger number. The number of rows N is also not limited. When distinguishing pixel blocks BL by row, the pixel block BL in the jth row is indicated by the symbol BL(j). This also applies to other elements and the control signals described below. Figures 2 and 3 show three rows, pixel blocks BL(n-1) to BL(n+1), in rows n-1 to n+1.

In the drawings, the pixel in the pixel block BL at the bottom in Figures 2 and 3 is designated PXA, and the pixel in the top in Figures 2 and 3 is designated PXB, to distinguish between them. However, when describing them without distinguishing between them, the symbol PX may be used to refer to both. In the drawings, the photodiode in pixel PXA is designated PDA, and the photodiode in pixel PXB is designated PDB, to distinguish between them. However, when describing them without distinguishing between them, the symbol PD may be used to refer to both. Similarly, the transfer transistor in pixel PXA is designated TXA, and the transfer transistor in pixel PXB is designated TXB, to distinguish between them. However, when describing them without distinguishing between them, the symbol TX may be used to refer to both. In this embodiment, the photodiodes PD of pixel PX are arranged in a two-dimensional matrix of 2N rows and M columns.

In this embodiment, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charge in response to incident light, and a transfer transistor TX as a transfer switch that transfers charge from the photodiode PD to a node P.

In this embodiment, multiple pixels PX form a pixel block BL, with each pair of pixels PX (PXA, PXB) having photodiodes PD aligned in the column direction. As shown in Figures 2 and 3, for each pixel block BL, the two pixels PX (PXA, PXB) belonging to that pixel block BL share a set of node P, amplifier transistor AMP, reset transistor RST, and select transistor SEL. A capacitance (charge-voltage conversion capacitance) is formed between node P and a reference potential, and this capacitance converts the charge transferred to node P into a voltage. The amplifier transistor AMP constitutes an amplifier unit that outputs a signal corresponding to the potential of node P. The reset transistor RST constitutes a reset switch that resets the potential of node P. The select transistor SEL constitutes a selector unit for selecting the pixel block BL. The photodiode PD and transfer transistor TX are not shared by two pixels PX (PXA, PXB) but are provided for each pixel PX. In Figures 2 and 3, n indicates the row of the pixel block BL. For example, the pixel PX (PXA) on the first row and the pixel PX (PXB) on the second row form the pixel block BL on the first row, and the pixel PX (PXA) on the third row and the pixel PX (PXB) on the fourth row form the pixel block BL on the second row.

In the present invention, a pixel block BL may be configured, for example, for every three or more pixels PX in which photodiodes PD are arranged sequentially in the column direction.

Although not shown in the drawings, in this embodiment, multiple types of color filters, each of which transmits light of a different color component, are arranged in a predetermined color array (e.g., Bayer array) on the light incident side of the photodiode PD of each pixel PX. The pixel PX outputs an electrical signal corresponding to each color through color separation by the color filters.

For each pair of pixel blocks BL adjacent to each other in the column direction, two linking transistors SWa and SWb are arranged in series as two linking switches in an electrical connection path (connection section) provided between node P of one pixel block BL and node P of the other pixel block BL, the connection path (connection section) being unique between the two. As a result, in this embodiment, the nodes P of three or more pixel blocks BL are connected in a daisy-chain fashion by multiple connection paths (connection sections). Of the two linking transistors SWa and SWb, linking transistor SWa is arranged on the side of node P of the lower pixel block BL in Figures 2 and 3, and linking transistor SWb is arranged on the side of node P of the upper pixel block BL in Figures 2 and 3.

For example, two coupling transistors SWa(n) and SWb(n) are arranged in series in a unique electrical connection path between node P(n) of pixel block BL(n) in the nth row and node P(n+1) of pixel block BL in the n+1th row. As shown in FIG. 4, coupling transistor SWa(n) is formed within the pixel block BL(n), while coupling transistor SWb(n) is formed within the pixel block BL(n+1). However, the same (n) is added to the end of the reference numerals of these coupling transistors SWa(n) and SWb(n) to indicate that they are arranged in series in the same unique connection path. Note that, although three or more coupling switches may be arranged in series in each unique connection path in the present invention, it is preferable to arrange two coupling transistors SWa and SWb in series in each unique connection path, as in this embodiment, for structural simplicity.

In Figures 2 and 3, VDD is the power supply potential. In this embodiment, transistors TXA, TXB, AMP, RST, SEL, SWa, and SWb are all nMOS transistors.

The gates of the transfer transistors TXA for each row are connected in common to a control line 26, to which a control signal φTXA is supplied from the vertical scanning circuit 21. The gates of the transfer transistors TXB for each row are connected in common to a control line 25, to which a control signal φTXB is supplied from the vertical scanning circuit 21. The gates of the reset transistors RST for each row are connected in common to a control line 24, to which a control signal φRST is supplied from the vertical scanning circuit 21. The gates of the select transistors SEL for each row are connected in common to a control line 23, to which a control signal φSEL is supplied from the vertical scanning circuit 21. The gates of the connecting transistors SWa for each row are connected in common to a control line 22, to which a control signal φSWa is supplied from the vertical scanning circuit 21. The gates of the connecting transistors SWb for each row are connected in common to a control line 27, to which a control signal φSWb is supplied from the vertical scanning circuit 21. For example, a control signal φTXA(n) is supplied to the gate of the transfer transistor TXA(n), a control signal φTXB(n) is supplied to the gate of the transfer transistor TXB(n), a control signal φRST(n) is supplied to the gate of the reset transistor RST(n), a control signal φSEL(n) is supplied to the gate of the selection transistor SEL(n), a control signal φSWa(n) is supplied to the gate of the linking transistor SWa(n), and a control signal φSWb(n) is supplied to the gate of the linking transistor SWb(n).

Each transistor TXA, TXB, RST, SEL, SWa, and SWb is turned on when the corresponding control signal φTXA, φTXB, φRST, φSEL, φSWa, or φSWb is high level (H), and turned off when the corresponding control signal is low level (L).

Under the control of the imaging control unit 5 in FIG. 1, the vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb for each row of the pixel block BL, controlling the pixel block BL and the connecting transistors SWa and SWb to perform still image readout operations, video readout operations, and the like. This control performs readout operations in various operation modes, described below, depending on, for example, the ISO sensitivity setting. Through this control, each vertical signal line 28 is supplied with a signal (analog signal) from the pixel PX of the corresponding column.

In this embodiment, the vertical scanning circuit 21 constitutes a control unit that switches between the various operation modes described below in response to commands (control signals) from the imaging control unit 5 in Figure 1.

The signals read out to the vertical signal lines 28 are amplified by the column amplifiers 30 for each column, and then processed by the CDS circuit 31 to obtain the difference between the optical signal (a signal containing optical information photoelectrically converted by the pixel PX) and the dark signal (a differential signal containing a noise component to be subtracted from the optical signal), before being converted into a digital signal by the A/D converter 32, which then stores the digital signal. The digital image signals stored in each A/D converter 32 are horizontally scanned by the horizontal readout circuit 33, converted into a predetermined signal format as necessary, and output to the outside (digital signal processing unit 6 in Figure 1).

The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and samples the output signal of the column amplifier 30 as a dark signal when φDARKC is high (H). It also receives a light signal sampling signal φSIGC from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1, and samples the output signal of the column amplifier 30 as an optical signal when φSIGC is H. The CDS circuit 31 then outputs a signal corresponding to the difference between the sampled dark signal and optical signal, based on the clock and pulses from the timing generation circuit. A known configuration can be used for this CDS circuit 31.

The structure of the pixel block BL will now be described with reference to Figures 4 and 5. In reality, color filters, microlenses, etc. are arranged above the photodiode PD, but these are omitted in Figures 4 and 5. Note that the layout of power lines, ground lines, control lines 22 to 27, etc. is omitted in Figures 4 and 5.

In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and elements in pixel block BL, such as photodiode PD, are disposed in the P-type well. In Figure 5, reference numerals 41 to 49 indicate N-type impurity diffusion regions that form part of each of the aforementioned transistors. Reference numerals 61 to 67 indicate gate electrodes of each transistor made of polysilicon. Diffusion regions 42 and 45 are regions to which power supply voltage VDD is applied via a power supply line (not shown).

The photodiodes PDA(n) and PDB(n) are buried photodiodes consisting of an N-type charge storage layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) located on the surface side of the N-type charge storage layer. The photodiodes PDA(n) and PDB(n) photoelectrically convert incident light and store the resulting charge in the charge storage layer.

The transfer transistor TXA(n) is an nMOS transistor with the charge storage layer of the photodiode PDA(n) as its source, the diffusion region 41 as its drain, and the gate electrode 61 as its gate. The transfer transistor TXB(n) is an nMOS transistor with the charge storage layer of the photodiode PDB(n) as its source, the diffusion region 41 as its drain, and the gate electrode 62 as its gate. The diffusion region 41 is provided between the photodiode PDA(n) and the photodiode PDB(n). The diffusion region 41 serves as both the diffusion region that serves as the drain of the transfer transistor TXA(n) and the diffusion region that serves as the drain of the transfer transistor TXB(n). The gate electrode 61 of the transfer transistor TXA(n) is located on the photodiode PDA(n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB(n) is located on the photodiode PDB(n) side of the diffusion region 41.

The amplification transistor AMP(n) is an nMOS transistor with diffusion region 42 as its drain, diffusion region 43 as its source, and gate electrode 63 as its gate. The selection transistor SEL(n) is an nMOS transistor with diffusion region 43 as its drain, diffusion region 44 as its source, and gate electrode 64 as its gate. Diffusion region 44 is connected to vertical signal line 28. The reset transistor RST(n) is an nMOS transistor with diffusion region 45 as its drain, diffusion region 46 as its source, and gate electrode 65 as its gate.

Linking transistor SWa(n) is an nMOS transistor with diffusion region 46 as its source, diffusion region 47 as its drain, and gate electrode 66 as its gate. Linking transistor SWb(n-1) is an nMOS transistor with diffusion region 48 as its drain, diffusion region 49 as its source, and gate electrode 67 as its gate.

The gate electrode 63 and diffusion regions 41 and 46 of pixel block BL(n) and the diffusion region 48 of linking transistor SWb(n-1) are electrically connected to each other and conductively via wiring 71(n). In this embodiment, node P(n) corresponds to wiring 71(n) and all of the locations electrically connected to and conductive with it.

The structure of pixel blocks BL other than those in the nth row is the same as the structure of the pixel block BL(n) in the nth row described above. The structure of connecting transistors SWa other than connecting transistor SWa(n) is the same as the structure of connecting transistor SWa(n) described above. The structure of connecting transistors SWb other than connecting transistor SWb(n) is the same as the structure of connecting transistor SWb(n) described above.

For the two linking transistors SWa and SWb arranged in series in each unique connection path, the diffusion region 47 of the linking transistor SWa and the diffusion region 49 of the linking transistor SWb are connected by wiring 72. For example, the diffusion region 47 of the linking transistor SWa(n-1) and the diffusion region 49 of the linking transistor SWb(n-1) are electrically connected by wiring 72(n-1). Wiring 72(n-1) forms the connection between the linking transistors SWa(n-1) and SWb(n-1) when the linking transistors SWa(n-1) and SWb(n-1) are off. The diffusion region 47 of the linking transistor SWa(n) and the diffusion region 49 of the linking transistor SWb(n) are electrically connected by wiring 72(n). Wiring 72(n) forms a connection between the linking transistors SWa(n) and SWb(n) when the linking transistors SWa(n) and SWb(n) are off.

As shown in FIG. 4, the column-direction misalignment between the two linking transistors SWa and SWb arranged in series in each unique connection path is denoted by Ls, and the column-direction pitch of the photodiodes PD is denoted by Pg. In the present invention, the relationship between the pitch Pg and the misalignment Ls is not limited, but to reduce the capacitance value Cfd1 of the capacitance CA described below, it is preferable that pg<Ls<2×Pg. In this embodiment, for example, the linking transistor SWb(n-1) is disposed near the linking transistor SWa(n), and the misalignment Ls is set to be slightly less than 2×Pg, thereby minimizing the length of the wiring 71(n) and minimizing the capacitance value Cfd1 of the capacitance CA(n) described below.

In Figures 2 to 5, CA(n) is the capacitance between node P(n) and the reference potential when the linking transistors SWa(n) and SWb(n-1) are off. The capacitance value of capacitance CA(n) is Cfd1. CB(n) is the capacitance between wiring 72(n) and the reference potential when the linking transistors SWa(n) and SWb(n) are off. The capacitance value of capacitance CB(n) is Cfd2. These points also apply to the other rows of pixel block BL.

Capacitance CA(n) is composed of the capacitance of the drain diffusion regions 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region 46 of the reset transistor RST(n), the capacitance of the source diffusion region 46 of the linking transistor SWa(n), the capacitance of the drain diffusion region 48 of the linking transistor SWb(n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n), and the sum of these capacitance values is the capacitance value Cfd1 of capacitance CA(n). This is also true for the other rows of the pixel block BL.

Here, the channel capacitance value of the linking transistor SWa when it is on and the channel capacitance value of the linking transistor SWb when it is on are both Csw. Typically, the capacitance value Csw is smaller than the capacitance values Cfd1 and Cfd2.

Now, focusing on pixel block BL(n), if both linking transistors SWa(n) and SWb(n-1) are turned off (i.e., the on-state linking transistors SWa and SWb are not electrically connected to node P(n), and the connection path through which linking transistors SWa and SWb are provided is not electrically connected to node P(n)), the capacitance (charge-voltage conversion capacitance) between node P(n) and the reference potential becomes capacitance CA(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes Cfd1. This state corresponds to the state during period T2 in Figure 6, which shows the first operating mode described below.

Furthermore, focusing on pixel block BL(n), when linking transistor SWa(n) is turned on, if none of the linking transistors SWa and SWb that are on except for linking transistor SWa(n) are electrically connected to node P(n) (specifically, if linking transistors SWb(n-1) and SWb(n) are off), the capacitance (charge-voltage conversion capacitance) between node P(n) and the reference potential is the sum of capacitance CA(n) plus capacitance CB(n) and the channel capacitance of linking transistor SWa(n) when it is on. Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) is Cfd1 + Cfd2 + Csw ≈ Cfd1 + Cfd2. This state corresponds to the state during period T2 in Figure 7, which shows the second A operating mode, described below.

Furthermore, focusing on pixel block BL(n), when both linking transistors SWa(n) and SWb(n) are turned on, if none of the linking transistors SWa and SWb that are on are electrically connected to node P(n) (specifically, if linking transistors SWb(n-1) and SWa(n+1) are off), the charge-voltage conversion capacitance of node P(n) is the sum of capacitance CA(n), capacitance CB(n), the channel capacitance of linking transistors SWa(n) and SWb(n) when they are on, and capacitance CA(n+1). Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) is 2×Cfd1+Cfd2+2×Csw≈2×Cfd1+Cfd2. This state corresponds to the state during period T2 in Figure 8, which shows the second B operating mode described below.

In this way, if none of the linking transistors SWa and SWb are in the on state and electrically connected to node P(n), the capacitance value of the charge-voltage conversion capacitance of node P(n) will be minimized, and the charge-voltage conversion coefficient due to that charge-voltage conversion capacitance will be large, enabling readout with the highest S/N ratio.

On the other hand, by increasing the number of on-state linking transistors electrically connected to node P(n) among the linking transistors SWa and SWb to a desired number greater than or equal to one, the capacitance value of the charge-voltage conversion capacitance of node P(n) can be increased to a desired value, allowing a larger amount of signal charge to be handled, thereby increasing the number of saturation electrons. This allows the dynamic range to be expanded.

The above describes node P(n) of pixel block BL(n), but the same applies to nodes P of other pixel blocks BL.

Figure 6 is a timing chart illustrating the first operating mode of the solid-state imaging device 4 shown in Figure 2. This first operating mode is an example of an operation in which each pixel block BL is selected row by row. When none of the connecting transistors SWa and SWb are electrically connected to the node P of the selected pixel block BL in the on-state (when the charge-voltage conversion capacity of the node P is at its minimum), the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby sequentially reading out the signals of each photodiode PDA and PDB of the selected pixel block BL row by row. In the example shown in Figure 6, signals from all pixels PXA and PXB are read out. However, this is not limiting; for example, thinning-out readout, in which pixel rows are thinned out and readout, may also be performed. This also applies to the examples shown in Figures 7 and 8, described below.

Figure 6 shows a situation in which pixel block BL(n-1) in the n-1th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the n+1th row is selected in period T3. The operation is the same when pixel block BL in any row is selected, so here we will only explain the operation when pixel block BL(n) in the nth row is selected.

Before period T2 begins, exposure of photodiodes PDA(n) and PDB(n) has already been completed during a specified exposure period. During normal actual shooting (still image shooting), this exposure is performed by a mechanical shutter (not shown) after a so-called global reset, which resets all pixels simultaneously. In electronic viewfinder mode or when shooting video, the exposure is performed by a so-called rolling electronic shutter operation. Immediately before period T2 begins, all transistors SEL, RST, TXA, TXB, SWa, and SWb are off.

During period T2, φSEL(n) on the nth row is set to H, turning on the select transistor SEL(n) in the nth row pixel block BL(n), and selecting the nth row pixel block BL(n).

Furthermore, during period T2, φSWa(n) and φSWb(n-1) are set to L, turning off the linking transistors SWa(n) and SWb(n-1). As a result, during period T2, none of the linking transistors SWa and SWb are in the on state and electrically connected to node P(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes Cfd1, which is the minimum.

For a fixed period of time immediately after the start of period T2, φRST(n) is set to H, the reset transistor RST(n) in the nth row is temporarily turned on, and the potential of node P(n) is temporarily reset to the power supply potential VDD.

For a fixed period of time from time t1 onward during period T2, the dark signal sampling signal φDARKC is set to H, and the potential appearing at node P(n) is amplified by the amplifier transistor AMP(n) on the nth row, passes through the select transistor SEL(n) and vertical signal line 28, and is further amplified by the column amplifier 30. The signal is then sampled as a dark signal by the CDS circuit 31.

For a fixed period of time from time t2 onwards during period T2, φTXA(n) is set to H, turning on the transfer transistor TXA(n) in the nth row. This causes the signal charge accumulated in the photodiode PDA(n) in the pixel block BL(n) in the nth row to be transferred to the charge-voltage conversion capacitance of node P(n). The potential of node P(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of node P(n).

At a later time t3 during period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at node P(n) is amplified by the amplifier transistor AMP(n) on the nth row, passes through the select transistor SEL(n) and vertical signal line 28, and is further amplified by the column amplifier 30. The signal is then sampled as an optical signal by the CDS circuit 31.

After φSIGC goes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a fixed period from time t1 and the optical signal sampled over a fixed period from time t3. The A/D converter 32 converts the signal corresponding to this difference into a digital signal and stores it. The digital image signal stored in each A/D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital image signal.

Then, from time t4 during period T2, for a fixed period of time, φRST(n) is set to H, the reset transistor RST(n) in the nth row is temporarily turned on, and the potential of node P(n) is temporarily reset to the power supply potential VDD.

For a fixed period of time from time t5 onwards during period T2, the dark signal sampling signal φDARKC is set to H, and the potential appearing at node P(n) is amplified by the amplifier transistor AMP(n) on the nth row, passes through the select transistor SEL(n) and vertical signal line 28, and is further amplified by the column amplifier 30. The signal is then sampled as a dark signal by the CDS circuit 31.

From time t6 onwards during period T2, φTXB(n) is set to H and the transfer transistor TXB(n) in the nth row is turned on for a fixed period of time. This causes the signal charge accumulated in the photodiode PDB(n) in the pixel block BL(n) in the nth row to be transferred to the charge-voltage conversion capacitance of node P(n). The potential of node P(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of node P(n).

At a later time t7 during period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at node P(n) is amplified by the amplifier transistor AMP(n) on the nth row, passes through the select transistor SEL(n) and vertical signal line 28, and is further amplified by the column amplifier 30. The signal is then sampled as an optical signal by the CDS circuit 31.

After that, after φSIGC goes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a fixed period from time t5 and the light signal sampled over a fixed period from time t7. The A/D converter 32 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A/D converter 32 is horizontally scanned by the horizontal readout circuit 33 and output as a digital image signal to the outside (digital signal processing unit 6 in Figure 1).

In this way, in the first operating mode, none of the connecting transistors SWa, SWb are on and electrically connected to node P of the selected pixel block BL, so the capacitance value of the charge-voltage conversion capacitance of node P of the selected pixel block BL is minimized, and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance is large, enabling readout with the highest S/N ratio. For example, when the ISO sensitivity setting is highest, the imaging control unit 5 issues a command to perform the first operating mode.

Figure 7 is a timing chart showing the 2A operation mode of the solid-state imaging device 4 shown in Figure 2. The 2A operation mode is one of the second operation modes. This second operation mode is an example of an operation in which each pixel block BL is selected row by row, and while a predetermined number of at least one of the linking transistors SWa and SWb that are in the on state are electrically connected to the node P of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby sequentially reading out the signals of each photodiode PDA and PDB of the selected pixel block BL row by row. The 2A operation mode is an example of an operation in the second operation mode in which the predetermined number is one.

As with Figure 6, Figure 7 also shows a situation in which pixel block BL(n-1) on the n-1th row is selected during period T1, pixel block BL(n) on the nth row is selected during period T2, and pixel block BL(n+1) on the n+1th row is selected during period T3. The differences between the second A operating mode shown in Figure 7 and the first operating mode shown in Figure 6 are explained below.

In the second A operating mode shown in FIG. 7, during period T2 when the nth row pixel block BL(n) is selected, φSWa(n) is set to H and φSWb(n-1) is set to L, turning on the connecting transistor SWa(n) and turning off the connecting transistor SWb(n-1). As a result, during period T2, one of the connecting transistors SWa and SWb that is in the on state (here, the connecting transistor SWa(n)) is electrically connected to node P(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of node P(n) is Cfd1 + Cfd2 + Csw ≈ Cfd1 + Cfd2, which is one level larger than the first operating mode shown in FIG. 6.

Here, we have explained the period T2 in which the pixel block BL(n) in the nth row is selected, but the same applies to the periods in which other pixel blocks BL are selected.

In this way, in the second A operating mode, one of the linking transistors SWa, SWb that is in the on state is electrically connected to node P of the selected pixel block BL, so that the capacitance value of the charge-voltage conversion capacitance of node P of the selected pixel block BL increases by one step, so to speak, and the number of saturated electrons in the charge-voltage conversion capacitance of node P can be increased by one step. This makes it possible to expand the dynamic range by one step. For example, when the ISO sensitivity setting is one step lower than the highest value, the imaging control unit 5 issues a command to perform the second A operating mode.

Figure 8 is a timing chart showing the second B operating mode of the solid-state imaging device 4 shown in Figure 2. The second B operating mode is another operating mode of the second operating modes, and is an example of an operation in which the predetermined number is two.

As with Figures 6 and 7, Figure 8 also shows a situation in which pixel block BL(n-1) on the n-1th row is selected during period T1, pixel block BL(n) on the nth row is selected during period T2, and pixel block BL(n+1) on the n+1th row is selected during period T3. The differences between operation mode 2B shown in Figure 8 and the first operation mode shown in Figure 6 and operation mode 2A shown in Figure 7 are explained below.

In the second B operating mode shown in FIG. 8, during period T2 when the nth row pixel block BL(n) is selected, φSWa(n) and φSWb(n) are set to H and φSWb(n-1) and φSWa(n+1) are set to L, turning on the connecting transistors SWa(n) and SWb(n) and turning off the connecting transistors SWb(n-1) and SWa(n+1). As a result, during period T2, two of the connecting transistors SWa and SWb that are in the on state (here, connecting transistors SWa(n) and SWb(n)) are electrically connected to node P(n) of the selected pixel block BL(n). Therefore, as mentioned above, the capacitance value of the charge-voltage conversion capacitance of node P(n) is 2 x Cfd1 + Cfd2 + 2Csw ≈ 2 x Cfd1 + Cfd2, which is two stages larger than the first operating mode shown in Figure 6.

Here, we have explained the period T2 in which the pixel block BL(n) in the nth row is selected, but the same applies to the periods in which other pixel blocks BL are selected.

In this way, in the second B operating mode, two of the connecting transistors SWa and SWb that are on are electrically connected to node P of the selected pixel block BL, so the capacitance value of the charge-voltage conversion capacitance of node P of the selected pixel block BL increases by two steps, and the number of saturated electrons in the charge-voltage conversion capacitance of node P can be increased by two steps. This allows the dynamic range to be expanded by two steps. For example, when the ISO sensitivity setting is two steps lower than the highest value, the imaging control unit 5 issues a command to execute the second B operating mode.

In addition, in the second operating mode, the predetermined number may be three or more.

Here, we will explain a solid-state imaging device according to a comparative example that is compared with the solid-state imaging device 4 of this embodiment. Figure 9 is a circuit diagram showing the vicinity of three pixel blocks BL of this solid-state imaging device according to this comparative example, and corresponds to Figure 3. Figure 10 is a schematic plan view showing the vicinity of the three pixel blocks BL shown in Figure 9, and corresponds to Figures 4 and 5. In Figures 9 and 10, elements that are the same as or correspond to elements in Figures 3, 4, and 5 are given the same reference numerals, and redundant explanations will be omitted. Note that although reference numerals are not given to diffusion regions and gate electrodes in Figure 10, these reference numerals are the same as those in Figure 5, so please refer to Figure 5.

This comparative example differs from the present embodiment in that each linking transistor SWb has been removed, and the removed linking transistor SWb is short-circuited by wiring 171, which includes wiring 71 and 72. For example, in the present embodiment, linking transistor SWb(n-1) has been removed, and wiring 171(n), which includes wiring 71(n) and 72(n-1), electrically connects and provides conduction between the gate electrode 63 and diffusion regions 41 and 46 of pixel block BL(n) and the diffusion region 47 of linking transistor SWa(n-1).

In Figures 9 and 10, CAB(n) is the capacitance between node P(n) and the reference potential when the linking transistors SWa(n) and SWa(n-1) are off. The capacitance value of capacitance CAB(n) is Cfd. These points also apply to the other rows of pixel block BL.

Capacitance CAB(n) is composed of the capacitance of the drain diffusion regions 41 of the transfer transistors TXA(n) and TXB(n), the source diffusion region 46 of the reset transistor RST(n), the source diffusion region 46 of the linking transistor SWa(n), the drain diffusion region 47 of the linking transistor SWa(n-1), the capacitance of the gate electrode 63 of the amplification transistor AMP(n), and the wiring capacitance of the wiring 171(n), and the sum of these capacitance values is the capacitance value Cfd of capacitance CAB(n). This is also true for the other rows of the pixel block BL.

The wiring capacitance of wiring 171(n) is approximately equal to the sum of the wiring capacitance (stray capacitance) of wiring 71(n) and the wiring capacitance of wiring 171(n). Therefore, the capacitance value Cfd of capacitance CAB(n) is approximately equal to the sum of the capacitance value Cfd1 of capacitance CA(n) and the capacitance value Cfd2 of capacitance CB(n) described above in this embodiment, so Cfd ≒ Cfd1 + Cfd2.

In this comparative example, focusing on pixel block BL(n), when both linking transistors SWa(n) and SWa(n-1) are turned off, the charge-voltage conversion capacitance of node P(n) becomes capacitance CAB(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes Cfd, the smallest in the comparative example, and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance becomes large, enabling readout with the highest S/N ratio in the comparative example.

In this comparative example, focusing on pixel block BL(n), when a predetermined number of one or more of the linking transistors SWa that are in the on state are electrically connected to node P(n), the capacitance value of the charge-voltage conversion capacitance of node P(n) increases in accordance with the number of linking transistors that are in the on state, thereby increasing the number of saturation electrons. This allows for an expansion of the dynamic range.

However, in this comparative example, the capacitance value of the charge-voltage conversion capacitance of node P(n) cannot be made smaller than Cfd ≒ Cfd1 + Cfd2. Therefore, according to this comparative example, the charge-voltage conversion coefficient cannot be made very large, and reading cannot be performed with a very high S/N ratio.

In contrast, in this embodiment, the linking transistor SWb is added, so as described above, the minimum capacitance value of the charge-voltage conversion capacitance of node P(n) can be set to Cfd1 ≒ Cfd - Cfd2, making it smaller than the comparative example.

Therefore, according to this embodiment, it is possible to expand the dynamic range and improve the S/N ratio during high-sensitivity readout compared to the comparative example.

In this embodiment, linking transistors SWa and SWb are provided between every two adjacent nodes P in the column direction, but the present invention is not necessarily limited to this. For example, between every qth (q is an integer of 2 or greater) node P in the column direction and the adjacent node P below that node P in the figure, linking transistors SWa and SWb may not be provided, and the gap between them may always be open. In this case, the smaller the number q, the smaller the maximum number of the predetermined number in the second operating mode, and the degree of expansion of the dynamic range decreases, but the signal-to-noise ratio during high-sensitivity readout can be improved compared to the comparative example.

Note that the operational examples described with reference to Figures 6 to 8 are examples of operations in which the signal charge of the photodiode PD of each pixel PX is read out without being mixed with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be read out by mixing it with the signal charge of the photodiode PD of other pixels PX of the same color.

For example, if the coupling transistors SWa(n-1), SWb(n-1), SWa(n), and SWb(n) are turned on to connect nodes P(n-1), P(n), and P(n+1) to each other, and TXA(n-1), TXA(n), and TXA(n+1) are turned on simultaneously, the signal charges of the photodiodes PDA(n-1), PDA(n), and PDA(n-1) of the three same-color pixels PXA(n-1), PXA(n), and PXA(n-1) in a Bayer array or the like are averaged at the mutually connected nodes P(n-1), P(n), and P(n+1), thereby realizing the same-color three-pixel mixed readout function. In this case, by turning off the connecting transistors SWb(n-2) and SWa(n+1) and minimizing the number of on-state connecting transistors electrically connected to nodes P(n-1), P(n), and P(n+1), the charge-voltage conversion capacitance value at the connected nodes P(n-1), P(n), and P(n+1) is minimized, enabling same-color three-pixel mixed readout with the highest S/N ratio. On the other hand, if one or more on-state connecting transistors in addition to the connecting transistors SWa(n-1), SWb(n-1), SWa(n), and SWb(n) are electrically connected to nodes P(n-1), P(n), and P(n+1), the charge-voltage conversion capacitance value at the connected nodes P(n-1), P(n), and P(n+1) increases accordingly, thereby expanding the dynamic range of same-color three-pixel mixed readout.

Second Embodiment
Fig. 11 is a circuit diagram showing the vicinity of three pixel blocks BL of a solid-state imaging device of an electronic camera according to a second embodiment of the present invention, and corresponds to Fig. 3. Fig. 12 is a schematic plan view showing the vicinity of the three pixel blocks BL shown in Fig. 9, and corresponds to Figs. 4 and 5. In Figs. 11 and 12, elements that are the same as or correspond to elements in Figs. 3, 4 and 5 are given the same reference numerals, and duplicated explanations will be omitted.

This embodiment differs from the first embodiment in that a regulating capacitance CB' having a capacitance value Cfd3 is added to each wiring 72. Because capacitance CB(n) is the capacitance between wiring 72(n) and the reference potential when the linking transistors SWa(n) and SWb(n) are off, regulating capacitance CB'(n) is also included in capacitance CB(n). However, to clearly indicate that regulating capacitance CB' is a component that adds capacitance value Cfd3 to the capacitance CB(n) having capacitance value Cfd2 in the first embodiment, regulating capacitance CB' is shown separately from capacitance CB(n) in FIGS. 11 and 12. In the first embodiment, capacitance value CB(n) is Cfd2, whereas in this embodiment, capacitance value CB(n) is Cfd2 + Cfd3. These points also apply to other capacitances CB, wiring 72, and regulating capacitances CB'.

This embodiment provides the same advantages as the first embodiment, and by providing an adjustment capacitor CB', the capacitance value of capacitor CB can be set to any desired capacitance value.

Specifically, the adjustment capacitance CB' can be configured by one or a combination of two or more of the following: (i) making the width of at least a portion of the wiring 72 wider than the wiring width of the other wirings in the pixel block BL, thereby making the area of the wiring 72 wider than the area of the wiring 72 in the first embodiment; (ii) connecting a MOS capacitance to the wiring 72; (iii) connecting a diffusion capacitance that is not part of the linking transistors SWa and SWb; (iv) making the area of the drain diffusion region 47 of the linking transistor SWa wider than the area of the drain diffusion region 47 in the first embodiment; and (v) making the area of the source diffusion region 49 of the linking transistor SWb wider than the area of the source diffusion region 49 in the first embodiment.

Here, an example of setting the capacitance value Cfd3 of the adjustment capacitance CB' will be described. It is desirable for the capacitance value of the charge-voltage conversion capacitance of node P to be an integer multiple of the reference capacitance value. However, in the structure of the first embodiment described above, if the adjustment capacitance CB' is not added, the capacitance value Cfd2 of capacitance CB will generally be smaller than the capacitance value Cfd1 of capacitance CA. Therefore, for example, to make the capacitance value of the charge-voltage conversion capacitance of node P(n) twice the reference capacitance value, the linking transistors SWa(n) and SWb(n) are turned on, the capacitance value of the charge-voltage conversion capacitance of node P(n) is set to 2×Cfd1+Cfd2+2×Csw, and two pixel blocks BL(n) and BL(n+1) are used.

In contrast, in this embodiment, if the adjustment capacitor CB' is formed so that its capacitance value Cfd3 is Cfd1 - Cfd2, the capacitance value of capacitor CB' becomes cfd2 + Cfd3 = Cfd1. Therefore, to make the capacitance value of the charge-voltage conversion capacitor of node P(n) twice the reference capacitance value, it is sufficient to turn on the linking transistor SWa(n), and use only one pixel block BL(n). Furthermore, when handling even larger amounts of saturated charge, the number of linked pixel blocks BL can be significantly reduced.

This setting example of the capacitance value Cfd3 of the adjustment capacitor CB' is merely an example and is not limited to this.

In order to bring the capacitance value of the charge-voltage conversion capacitance of node P close to an integer multiple of the reference capacitance value, it is preferable that the capacitance value of capacitance CB be within a range of ±20% of the capacitance value of capacitance CA, and more preferably within a range of ±10% of the capacitance value of capacitance CA.

[Third embodiment]
Fig. 13 is a circuit diagram showing the schematic configuration of a solid-state image sensor 84 of an electronic camera according to a third embodiment of the present invention, and corresponds to Fig. 2. In Fig. 13, elements that are the same as or correspond to elements in Fig. 2 are given the same reference numerals, and redundant explanations will be omitted.

This embodiment differs from the first embodiment in that, in the first embodiment, the photodiodes PDB and transfer transistors TXB are removed from each pixel block BL, and each pixel block BL is replaced by a pixel PXA. However, in this embodiment, the column density of the photodiodes PDA is double the column density of the photodiodes PDA in the first embodiment, and is the same as the column density of the photodiodes PDA and PDB as a whole in the first embodiment. In this embodiment, n indicates the row of the pixel block BL as well as the row of the pixel PXA.

In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in the present embodiment, each pixel block BL is composed of one pixel PX (PXA). Furthermore, in the first embodiment, the two pixels PX (PXA, PXB) belonging to a pixel block BL share a set of node P, amplification transistor AMP, reset transistor RST, and selection transistor SEL, whereas in the present embodiment, each pixel PX (in this embodiment, only PXA) has its own set of node P, amplification transistor AMP, reset transistor RST, and selection transistor SEL.

Essentially, the description of the first embodiment applies to this embodiment by replacing pixel block BL with pixel PXA. Therefore, a detailed description of this embodiment will be omitted here.

This embodiment also offers the same advantages as the first embodiment.

In addition, in the present invention, modifications similar to those made to the first embodiment to obtain this present embodiment may also be applied to the second embodiment.

[Fourth embodiment]
Fig. 14 is a circuit diagram showing the schematic configuration of a solid-state image sensor 94 of an electronic camera according to a fourth embodiment of the present invention, and corresponds to Fig. 2. Fig. 15 is a circuit diagram showing an enlarged view of the vicinity of four pixel blocks BL arranged in succession in the column direction in Fig. 14, and corresponds to Fig. 3. In Figs. 14 and 15, elements that are the same as or correspond to elements in Figs. 2 and 3 are given the same reference numerals, and redundant explanations will be omitted. This embodiment differs from the first embodiment in the points described below.

In this embodiment, the first coupling transistor SWa, second coupling transistor SWb, and wiring 71 and 72 of the first embodiment are removed, and instead a first transistor SWA serving as a first switch unit that electrically connects and disconnects a first node Pa and a corresponding second node Pb, a second transistor SWB serving as a second switch unit that electrically connects and disconnects two second nodes Pb, and wiring 97 and 98 are provided.

The first node Pa(n) of the pixel block BL(n) corresponds to the node P(n) in the first embodiment. The transfer transistor TXA(n) transfers charges from the photodiode PDA(n) to the first node Pa(n), and the transfer transistor TXB(n) transfers charges from the photodiode PDB(n) to the first node Pa(n). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa(n) and a reference potential, and this capacitance converts the charges transferred to the first node Pa(n) into a voltage. The amplification transistor AMP(n) outputs a signal corresponding to the potential of the first node Pa(n). The reset transistor RST(n) resets the potential of the first node Pa(n). These points are similar for the other rows of the pixel block BL.

The first transistor SWA(n) constitutes a first switch unit that electrically connects and disconnects the first node Pa(n) and the corresponding second node Pb(n). Such a first switch unit can be configured by combining switches such as multiple transistors, but to simplify the structure, it is preferable to configure it with a single first transistor SWA(n), as in this embodiment. These points also apply to the other first transistors SWA.

Each second transistor SWB constitutes a second switch unit that electrically connects and disconnects the second node Pb corresponding to the first node Pa of one pixel block BL to the second node Pb corresponding to the first node Pa of the other pixel block BL for each two pixel blocks BL that are adjacent to each other in the column direction. In this embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy-chain fashion by multiple second switch units. While the second switch unit described above can be constructed by combining multiple switches such as transistors, it is preferable to construct it with a single second transistor SWB, as in this embodiment, to simplify the structure.

For example, the second transistor SWB(n) is configured to electrically connect and disconnect the second node Pb(n) corresponding to the first node Pa(n) of the pixel block BL(n) in the nth row and the second node Pb(n-1) corresponding to the first node Pa(n-1) of the pixel block BL(n-1) in the n-1th row. This also applies to the other second transistors SWB.

The gate electrode of the amplification transistor AMP(n), the source region of the reset transistor RST(n), the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), and the source diffusion region of the first transistor SWA(n) of the pixel block BL(n) are electrically connected to one another and conductively via wiring 97(n). The first node Pa(n) corresponds to wiring 97(n) and the entire area electrically connected to and conductive with it. This also applies to the other rows of the pixel block BL.

The drain diffusion region of the first transistor SWA(n), the drain diffusion region of the second transistor SWB(n), and the source diffusion region of the second transistor SWB(n+1) are electrically connected to each other and conductively via wiring 98(n). The second node Pb(n) corresponds to wiring 98(n) and the entire area electrically connected to and conductive with it. This also applies to the other first transistors SWA and other second transistors SWB.

The gates of the first transistors SWA are connected in common to a control line 95 for each row, to which a control signal φSWA is supplied from the vertical scanning circuit 21. The gates of the second transistors SWB are connected in common to a control line 96 for each row, to which a control signal φSWB is supplied from the vertical scanning circuit 21.

In Figures 14 and 15, CC(n) is the capacitance between the first node Pa(n) and the reference potential when the first transistor SWA(n) is off. The capacitance value of capacitance CC(n) is Cfd1'. CD(n) is the capacitance between wiring 98(n) and the reference potential when the first transistor SWA(n) and second transistors SWB(n) and SWB(n+1) are off. The capacitance value of capacitance CD(n) is Cfd2'. These points also apply to the other first transistors SWA and other second transistors SWB.

Capacitance CC(n) is composed of the capacitance of the drain diffusion regions of transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of reset transistor RST(n), the capacitance of the source diffusion region of first transistor SWA(n), the capacitance of the gate electrode of amplifier transistor AMP(n), and the wiring capacitance of wiring 97(n), and the sum of these capacitance values is capacitance value Cfd1' of capacitance CC(n). This is also true for the other rows of pixel block BL.

Note that the capacitance of the source diffusion region of the second transistor SWB(n) is not a component of the capacitance CC(n), so the capacitance value Cfd1' of the capacitance CC(n) is smaller by that amount. In contrast, in the first embodiment, not only the capacitance of the source diffusion region 46 of the linking transistor SWa(n) but also the capacitance of the drain diffusion region 48 of the linking transistor SWb(n-1) are components of the capacitance CB, so the capacitance value Cfd1 of the capacitance CB is larger by that amount. In other words, the capacitance value Cfd1' in this embodiment is smaller than the capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance.

Here, the channel capacitance value of the first transistor SWA when it is on and the channel capacitance value of the second transistor SWB when it is on are both denoted as Csw. Typically, the capacitance value Csw is smaller than the capacitance values Cfd1' and Cfd2'.

Now, focusing on pixel block BL(n), when the first transistor SWA(n) is turned off (i.e., none of the first transistors SWA and second transistors SWB that are on are electrically connected to the first node Pa(n)), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential becomes capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1'. This state corresponds to the state of period T2 in Figure 16, which shows the first operating mode described below.

Furthermore, focusing on pixel block BL(n), when the first transistor SWA(n) is turned on, if none of the first transistors SWA and second transistors SWB that are turned on except for the first transistor SWA(n) are electrically connected to the first node Pa(n) (specifically, if the second transistors SWB(n) and SWB(n+1) are turned off), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the sum of capacitance CC(n) and capacitance CD(n) and the channel capacitance of the first transistor SWA(n) when it is turned on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1' + Cfd2' + Csw ≈ Cfd1' + Cfd2'. This state corresponds to the state during period T2 in Figure 17, which shows the second A operating mode, described below.

Furthermore, focusing on pixel block BL(n), when the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, if none of the first transistors SWA and second transistors SWB that are on other than transistors SWA(n) and SWB(n+1) are electrically connected to the first node Pa(n) (specifically, if transistors SWB(n), SWA(n+1), and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) is the capacitance CC(n) plus capacitance CD(n), capacitance CD(n+1), and the channel capacitance of transistors SWA(n) and SWB(n+1) when they are on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1' + 2 x Cfd2' + 2 x Csw ≈ Cfd1' + 2 x Cfd2'. This state corresponds to the state of period T2 in Figure 18, which shows the second B operating mode described below.

Furthermore, focusing on pixel block BL(n), when the first transistors SWA(n), SWA(n+1) and the second transistor SWB(n+1) are turned on, if none of the first transistors SWA and second transistors SWB that are on other than transistors SWA(n), SWA(n+1), and SWB(n+1) are electrically connected to the first node Pa(n) (specifically, if transistors SWB(n) and SWB(n+2) are off), the charge-voltage conversion capacitance of the first node Pa(n) is calculated by adding capacitance CD(n), capacitance CD(n+1), capacitance CC(n+1) and the channel capacitance of transistors SWA(n), SWA(n+1), and SWB(n+1) when they are on to capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is 2 x Cfd1' + 2 x Cfd2' + 3 x Csw ≈ 2 x Cfd1' + 2 x Cfd2'. This state corresponds to the state of period T2 in Figure 19, which shows the second C operating mode described below.

Furthermore, focusing on pixel block BL(n), when the first transistor SWA(n) and the second transistors SWB(n+1), SWB(n+2) are turned on, if none of the first transistors SWA and second transistors SWB that are on are electrically connected to the first node Pa(n) (specifically, if transistors SWA(n+1), SWA(n+2), SWB(n), SWB(n+3) are off), the charge-voltage conversion capacitance of the first node Pa(n) is calculated by adding capacitance CD(n), capacitance CD(n+1), capacitance CD(n+2) and the channel capacitance of transistors SWA(n), SWB(n+1), SWB(n+2) when they are on to capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1' + 3 x Cfd2' + 3 x Csw ≈ Cfd1' + 3 x Cfd2'. This state corresponds to the state of period T2 in Figure 20, which shows the second C operating mode described below.

In this way, if none of the first transistors SWA and second transistors SWB are electrically connected to the first node Pa(n) in an on-state, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes the minimum capacitance value Cfd1', and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance becomes large, enabling readout with the highest S/N ratio. As mentioned above, since the capacitance value Cfd1' is smaller than the minimum capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance, this embodiment achieves an even larger charge-voltage conversion coefficient than the first embodiment, enabling readout with an even higher S/N ratio.

On the other hand, by increasing the number of on-state transistors electrically connected to the first node Pa(n) among the first transistors SWA and second transistors SWB to a desired number greater than one, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) can be increased to a desired value, allowing a larger amount of signal charge to be handled, thereby increasing the number of saturation electrons. This allows the dynamic range to be expanded.

The above describes the first node Pa(n) of pixel block BL(n), but the same applies to the first nodes Pa of other pixel blocks BL.

Figure 16 is a timing chart illustrating the first operating mode of the solid-state imaging device 94 shown in Figure 14. This first operating mode is an example of an operation in which each pixel block BL is selected row by row. When none of the first transistors SWA and second transistors SWB are electrically connected to the first node Pa of the selected pixel block BL (i.e., when the charge-voltage conversion capacity of the first node Pa is at its minimum), the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on. The signals of each photodiode PDA and PDB of the selected pixel block BL are read out row by row. In the example shown in Figure 16, signals from all pixels PXA and PXB are read out. However, this is not limiting; for example, thinning-out readout, in which pixel rows are thinned out and readout, may also be performed. This also applies to the examples shown in Figures 17 to 20, which will be described later.

The operation of the first operating mode shown in Figure 16 is clear from the explanation so a detailed explanation will be omitted.

Figure 17 is a timing chart showing the 2A operation mode of the solid-state imaging device 94 shown in Figure 14. The 2A operation mode is one of the second operation modes. This second operation mode is an example of an operation in which each pixel block BL is selected row by row, and a predetermined number of at least one on-state transistors among each first transistor SWA and each second transistor SWB is electrically connected to the first node Pa of the selected pixel block BL. The transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby sequentially reading out signals from each photodiode PDA and PDB of the selected pixel block BL row by row. The 2A operation mode is an example of an operation in the second operation mode in which the predetermined number is one (one of the first transistors SWA).

The operation of the second A operating mode shown in Figure 17 is clear from the explanation so a detailed explanation will be omitted.

Figure 18 is a timing chart showing the second B operating mode of the solid-state imaging device 94 shown in Figure 14. The second B operating mode is another of the second operating modes, and is an example of an operation in which the predetermined number is two (one for the first transistor SWA and one for the second transistor SWB). The operation of the second B operating mode shown in Figure 18 is clear from the explanation so far, so a detailed explanation will be omitted.

Figure 19 is a timing chart showing the second C operating mode of the solid-state imaging device 94 shown in Figure 14. The second C operating mode is yet another of the second operating modes, and is an example of operation in which the predetermined number is three (two first transistors SWA and one second transistor SWB). The operation of the second C operating mode shown in Figure 19 is clear from the explanation so far, so a detailed explanation will be omitted.

Figure 20 is a timing chart showing the second D operation mode of the solid-state imaging device 94 shown in Figure 14. The second D operation mode is yet another of the second operation modes, and is an example of operation in which the predetermined number is three (one for the first transistor SWA and two for the second transistor SWB). The operation of the second D operation mode shown in Figure 20 is clear from the explanation so far, so a detailed explanation will be omitted.

According to this embodiment, like the first embodiment, the dynamic range can be expanded and the S/N ratio during high-sensitivity readout can be improved compared to the comparative example. Furthermore, according to this embodiment, the charge-voltage conversion coefficient is even larger than in the first embodiment, enabling high-sensitivity readout with an even higher S/N ratio.

In this embodiment, a second transistor SWB is provided between every two adjacent second nodes Pb in the column direction. However, this is not necessarily limited to this. For example, a second transistor SWB may not be provided between a second node Pb every r (where r is an integer greater than or equal to 2) rows in the column direction and a second node Pb adjacent to the second node Pb below the second node Pb in the figure, leaving the gap open. In this case, the smaller the value of r, the smaller the maximum predetermined number in the second operating mode, reducing the degree of dynamic range expansion. However, the signal-to-noise ratio during high-sensitivity readout can be improved compared to the comparative example. Furthermore, a second transistor SWB may not be provided between a second node Pb every s (where s is an integer greater than or equal to 1) rows in the column direction and a second node Pb adjacent to the second node Pb below the second node Pb in the figure, leaving the gap electrically shorted. Furthermore, for example, second transistors SWB may be provided only between every u second nodes Pb (where u is an integer greater than or equal to 1) arranged in the column direction and the second node Pb adjacent to the second node Pb on the lower side in the figure, while second nodes Pb other than every u second nodes arranged in the column direction may be electrically short-circuited to the second node Pb adjacent to the second node Pb on the lower side in the figure.

As with the second embodiment, in this embodiment, an adjustment capacitor may be provided on the wiring 98. Also, in this embodiment, the capacitance value of the capacitor CD may be set to a value within a range of ±20% of the capacitance value of the capacitor CC, or may be set to a value within a range of ±10% of the capacitance value of the capacitor CC. These points also apply to the fifth embodiment described below.

Note that the operation examples shown in Figures 16 to 20 are examples of operations in which the signal charge of the photodiode PD of each pixel PX is read out without being mixed with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be read out by mixing it with the signal charge of the photodiode PD of other pixels PX of the same color.

For example, when the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1) are turned on to connect the first nodes Pa(n-1), Pa(n), Pa(n+1) to each other, and TXA(n-1), TXA(n), TXA(n+1) are turned on simultaneously, the signal charges of the photodiodes PDA(n-1), PDA(n), PDA(n-1) of the three same-color pixels PXA(n-1), PXA(n), PXA(n-1) in a Bayer array or the like are averaged at the connected first nodes Pa(n-1), Pa(n), Pa(n+1), thereby realizing the same-color three-pixel mixed readout function. At this time, by turning off the second transistors SWB(n-2), SWB(n+2) and minimizing the number of first or second transistors in the on state that are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) is minimized, and same-color three-pixel mixed readout can be performed with the highest S/N ratio. On the other hand, if one or more on-state transistors among the first transistors SWA(n-1), SWA(n), SWA(n+1) and second transistors SWB(n), SWB(n+1) are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), in addition to the first transistors SWA(n-1), SWA(n), SWA(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) increases in accordance with the number of on-state transistors, thereby expanding the dynamic range of same-color three-pixel mixed readout.

Fifth Embodiment
Fig. 21 is a circuit diagram showing a schematic configuration of a solid-state image sensor 104 of an electronic camera according to a fifth embodiment of the present invention, and corresponds to Fig. 14. In Fig. 21, elements that are the same as or correspond to elements in Fig. 14 are given the same reference numerals, and redundant explanations will be omitted.

This embodiment differs from the fourth embodiment in that, in the fourth embodiment, the photodiodes PDB and transfer transistors TXB are removed from each pixel block BL, and each pixel block BL is replaced by a pixel PXA. However, in this embodiment, the column density of the photodiodes PDA is twice the column density of the photodiodes PDA in the fourth embodiment, and is the same as the column density of the photodiodes PDA and PDB as a whole in the fourth embodiment. In this embodiment, n indicates the row of the pixel block BL as well as the row of the pixel PXA.

In other words, in the fourth embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in the present embodiment, each pixel block BL is composed of one pixel PX (PXA). Furthermore, in the fourth embodiment, the two pixels PX (PXA, PXB) belonging to a pixel block BL share a set of a first node Pa, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL, whereas in the present embodiment, each pixel PX (in this embodiment, only PXA) has a set of a first node Pa, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL.

Essentially, the description of the fourth embodiment applies to this embodiment by replacing pixel block BL with pixel PXA. Therefore, a detailed description of this embodiment will be omitted here.

This embodiment also offers the same advantages as the fourth embodiment.

The above describes various embodiments and variations of the present invention, but the present invention is not limited to these.

4 Solid-state imaging element BL Pixel block PX Pixel PD Photodiode TXA, TXB Transfer transistor P Node AMP Amplification transistor SWa, SWb Connecting transistor

Claims (66)

a first photoelectric conversion unit that converts light into electric charges;
a second photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit in the column direction;
a first diffusion section to which the charges converted by the first photoelectric conversion section are transferred;
a second diffusion section to which the charges converted by the second photoelectric conversion section are transferred;
a first transistor electrically connected to the first diffusion region via a first wiring ;
a second transistor electrically connected to the second diffusion region via a second wiring ;
the first transistor and the second transistor are connected in series in a connection path that electrically connects the first diffusion portion and the second diffusion portion;
Image sensor. 2. The imaging device according to claim 1,
a first reset transistor for electrically connecting the first diffusion portion and a supply portion to which a predetermined voltage is supplied;
a second reset transistor for electrically connecting the second diffusion portion and the supply portion;
An imaging element comprising: 2. The imaging device according to claim 1,
a first reset transistor for resetting a voltage of the first diffusion portion;
a second reset transistor for resetting the voltage of the second diffusion region;
An imaging element comprising: 4. The imaging device according to claim 2,
the first transistor is formed using at least a portion of a diffusion portion forming the first reset transistor;
the second transistor is formed using at least a portion of a diffusion portion forming the second reset transistor;
Image sensor. 5. The imaging device according to claim 2,
one of the drain of the first transistor and the source of the first transistor is formed using at least a part of a diffusion portion forming one of the drain of the first reset transistor and the source of the first reset transistor;
one of the drain of the second transistor and the source of the second transistor is formed using at least a part of a diffusion portion forming one of the drain of the second reset transistor and the source of the second reset transistor;
Image sensor. 6. The imaging device according to claim 2,
one of the drain of the first transistor and the source of the first transistor forms one of the drain of the first reset transistor and the source of the first reset transistor;
one of the drain of the second transistor and the source of the second transistor forms one of the drain of the second reset transistor and the source of the second reset transistor;
Image sensor. 7. The imaging device according to claim 2,
a distance from the first diffusion portion to the gate of the first transistor is longer than a distance from the first diffusion portion to the gate of the first reset transistor;
a distance from the second diffusion region to the gate of the second transistor is longer than a distance from the first diffusion region to the gate of the second reset transistor;
Image sensor. The imaging device according to any one of claims 2 to 7,
a gate of the first transistor is disposed at a position farther from the first diffusion portion than a gate of the first reset transistor;
a gate of the second transistor is disposed at a position farther from the second diffusion region than a gate of the second reset transistor;
Image sensor. 9. The imaging device according to claim 2,
a first amplification transistor having a gate electrically connected to the first diffusion portion;
a second amplification transistor having a gate electrically connected to the second diffusion region;
An imaging element comprising: 10. The imaging device according to claim 9,
the gate of the first amplifying transistor is larger than the gate of the first transistor;
The gate of the second amplifying transistor is larger than the gate of the second transistor.
Image sensor. 11. The imaging device according to claim 9,
a gate width of the first amplification transistor is larger than a gate width of the first transistor;
a gate width of the second amplification transistor is larger than a gate width of the second transistor;
Image sensor. The imaging device according to any one of claims 9 to 11,
a gate length of the first amplifying transistor is greater than a gate length of the first transistor;
The gate length of the second amplification transistor is greater than the gate length of the second transistor.
Image sensor. The imaging device according to any one of claims 9 to 12,
the gate of the first amplifying transistor is larger than the gate of the first reset transistor;
The gate of the second amplifying transistor is larger than the gate of the second reset transistor.
Image sensor. The imaging device according to any one of claims 9 to 13,
a gate width of the first amplification transistor is larger than a gate width of the first reset transistor;
a gate width of the second amplification transistor is larger than a gate width of the second reset transistor;
Image sensor. 15. The imaging device according to claim 9,
a gate length of the first amplifying transistor is greater than a gate length of the first reset transistor;
The gate length of the second amplifying transistor is greater than the gate length of the second reset transistor.
Image sensor. 16. The imaging device according to claim 9,
a distance from a gate of the first reset transistor to a gate of the first transistor is shorter than a distance from a gate of the first amplification transistor to a gate of the first transistor;
a distance from a gate of the second reset transistor to a gate of the second transistor is shorter than a distance from a gate of the second amplification transistor to a gate of the second transistor;
Image sensor. 17. The imaging device according to claim 9,
a gate of the first transistor is disposed at a position farther from the gate of the first amplification transistor than a gate of the first reset transistor;
a gate of the second transistor is disposed at a position farther from the gate of the second amplifier transistor than a gate of the second reset transistor;
Image sensor. 18. The imaging device according to claim 9,
a first selection transistor electrically connected to the first amplification transistor;
a second selection transistor electrically connected to the second amplification transistor;
An imaging element comprising: 19. The imaging device according to claim 18,
the gate of the first amplification transistor is larger than the gate of the first selection transistor;
The gate of the second amplification transistor is larger than the gate of the second selection transistor.
Image sensor. 20. The imaging device according to claim 18 or 19,
a gate width of the first amplification transistor is larger than a gate width of the first selection transistor;
a gate width of the second amplification transistor is larger than a gate width of the second selection transistor;
Image sensor. 21. The imaging device according to claim 18,
a gate length of the first amplification transistor is greater than a gate length of the first selection transistor;
The gate length of the second amplification transistor is greater than the gate length of the second selection transistor.
Image sensor. 22. The imaging device according to claim 18,
the first amplification transistor is formed using at least a part of a diffusion portion forming the first selection transistor;
the second amplification transistor is formed using at least a part of a diffusion portion forming the second selection transistor;
Image sensor. 23. The imaging device according to claim 18,
the first amplification transistor and the first selection transistor are formed by sharing at least a part of one diffusion region;
the second amplification transistor and the second selection transistor are formed by sharing at least a part of one diffusion region;
Image sensor. 24. The imaging device according to claim 18 or claim 23,
one of the drain of the first amplification transistor and the source of the first amplification transistor is formed using at least a part of a diffusion portion forming one of the drain of the first selection transistor and the source of the first selection transistor;
one of the drain of the second amplification transistor and the source of the second amplification transistor is formed using at least a part of a diffusion portion forming one of the drain of the second selection transistor and the source of the second selection transistor.
Image sensor. 25. The imaging device according to claim 18,
one of the drain of the first amplification transistor and the source of the first amplification transistor forms one of the drain of the first selection transistor and the source of the first selection transistor;
one of the drain of the second amplification transistor and the source of the second amplification transistor forms one of the drain of the second selection transistor and the source of the second selection transistor;
Image sensor. 26. The imaging device according to claim 18,
a distance from a gate of the first reset transistor to a gate of the first transistor is shorter than a distance from a gate of the first selection transistor to a gate of the first transistor;
a distance from a gate of the second reset transistor to a gate of the second transistor is shorter than a distance from a gate of the second selection transistor to a gate of the second transistor;
Image sensor. 27. The imaging device according to claim 18,
a gate of the first transistor is disposed at a position farther from the gate of the first selection transistor than a gate of the first reset transistor;
a gate of the second transistor is disposed at a position farther from the gate of the second selection transistor than a gate of the second reset transistor;
Image sensor. 2. The imaging device according to claim 1,
a first amplification transistor having a gate electrically connected to the first diffusion portion;
a second amplification transistor having a gate electrically connected to the second diffusion region;
An imaging element comprising: 29. The imaging device according to claim 28,
the gate of the first amplifying transistor is larger than the gate of the first transistor;
The gate of the second amplifying transistor is larger than the gate of the second transistor.
Image sensor. 30. The imaging device according to claim 28 or 29,
a gate width of the first amplification transistor is larger than a gate width of the first transistor;
a gate width of the second amplification transistor is larger than a gate width of the second transistor;
Image sensor. 31. The imaging device according to claim 28,
a gate length of the first amplifying transistor is greater than a gate length of the first transistor;
The gate length of the second amplification transistor is greater than the gate length of the second transistor.
Image sensor. 32. The imaging device according to claim 28,
a distance from the first diffusion portion to the gate of the first transistor is longer than a distance from the first diffusion portion to the gate of the first amplification transistor;
a distance from the second diffusion region to the gate of the second transistor is longer than a distance from the first diffusion region to the gate of the second amplification transistor;
Image sensor. 33. The imaging device according to claim 28,
a gate of the first transistor is disposed at a position farther from the first diffusion region than a gate of the first amplification transistor;
a gate of the second transistor is disposed at a position farther from the second diffusion region than a gate of the second amplification transistor;
Image sensor. 34. The imaging device according to claim 28,
a first selection transistor electrically connected to the first amplification transistor;
a second selection transistor electrically connected to the second amplification transistor;
An imaging element comprising: 35. The imaging device according to claim 34,
the gate of the first amplification transistor is larger than the gate of the first selection transistor;
The gate of the second amplification transistor is larger than the gate of the second selection transistor.
Image sensor. 36. The imaging device according to claim 34 or 35,
a gate width of the first amplification transistor is larger than a gate width of the first selection transistor;
a gate width of the second amplification transistor is larger than a gate width of the second selection transistor;
Image sensor. 37. The imaging device according to claim 34,
a gate length of the first amplification transistor is greater than a gate length of the first selection transistor;
The gate length of the second amplification transistor is greater than the gate length of the second selection transistor.
Image sensor. 38. The imaging device according to claim 34,
the first amplification transistor is formed using at least a part of a diffusion portion forming the first selection transistor;
the second amplification transistor is formed using at least a part of a diffusion portion forming the second selection transistor;
Image sensor. 39. The imaging device according to claim 34 or claim 38,
one of the drain of the first amplification transistor and the source of the first amplification transistor is formed using at least a part of a diffusion portion forming one of the drain of the first selection transistor and the source of the first selection transistor;
one of the drain of the second amplification transistor and the source of the second amplification transistor is formed using at least a part of a diffusion portion forming one of the drain of the second selection transistor and the source of the second selection transistor.
Image sensor. 40. The imaging device according to claim 34,
one of the drain of the first amplification transistor and the source of the first amplification transistor forms one of the drain of the first selection transistor and the source of the first selection transistor;
one of the drain of the second amplification transistor and the source of the second amplification transistor forms one of the drain of the second selection transistor and the source of the second selection transistor;
Image sensor. 41. The imaging device according to claim 34,
a distance from a gate of the first amplification transistor to a gate of the first transistor is shorter than a distance from a gate of the first selection transistor to a gate of the first transistor;
a distance from a gate of the second amplification transistor to a gate of the second transistor is shorter than a distance from a gate of the second selection transistor to a gate of the second transistor;
Image sensor. 42. The imaging device according to claim 34,
a gate of the first transistor is disposed at a position farther from the gate of the first selection transistor than a gate of the first amplification transistor;
a gate of the second transistor is disposed at a position farther from the gate of the second selection transistor than a gate of the second amplification transistor;
Image sensor. 43. The imaging device according to claim 1,
the first transistor and the second transistor are electrically connected to each other in the connection path via a third transistor;
Image sensor. 44. The imaging device according to claim 43,
the first transistor, the second transistor, and the third transistor are connected in series in the connection path;
Image sensor. 43. The imaging device according to claim 1,
the first transistor and the second transistor are electrically connected via a plurality of transistors connected in series in the connection path;
Image sensor. 46. The imaging device according to claim 1,
a third photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit;
a fourth photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the second photoelectric conversion unit;
Equipped with
the first diffusion unit receives the charges converted by the third photoelectric conversion unit,
The second diffusion unit receives the charges converted by the fourth photoelectric conversion unit.
Image sensor. 47. The imaging device according to claim 46,
the third photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the column direction,
the fourth photoelectric conversion unit is disposed adjacent to the second photoelectric conversion unit in the column direction.
Image sensor. 48. The imaging device according to claim 46 or 47,
a first transfer transistor that transfers the charges converted by the first photoelectric conversion unit to the first diffusion unit;
a second transfer transistor that transfers the charges converted by the second photoelectric conversion unit to the second diffusion unit;
a third transfer transistor that transfers the charges converted by the third photoelectric conversion unit to the first diffusion unit;
a fourth transfer transistor that transfers the charges converted by the fourth photoelectric conversion unit to the second diffusion unit;
An imaging element comprising: 49. The imaging device according to claim 48,
the first transfer transistor and the third transfer transistor are arranged such that a direction in which the charges converted by the first photoelectric conversion unit are transferred from the first photoelectric conversion unit to the first diffusion unit is different from a direction in which the charges converted by the third photoelectric conversion unit are transferred from the third photoelectric conversion unit to the first diffusion unit;
the second transfer transistor and the fourth transfer transistor are arranged such that a direction in which the charges converted by the second photoelectric conversion unit are transferred from the second photoelectric conversion unit to the second diffusion unit is different from a direction in which the charges converted by the fourth photoelectric conversion unit are transferred from the fourth photoelectric conversion unit to the second diffusion unit.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit controls the first transistor to be turned off at the first timing, and controls the second transistor to be turned off at the second timing;
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit controls the first transistor to be turned off and the second transistor to be turned off at the first timing, and controls the first transistor to be turned off and the second transistor to be turned off at the second timing;
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing;
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing;
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be off at the first timing and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing and the first transistor to be off and the second transistor to be on at the second timing.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be off and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be off at the first timing and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing and the first transistor to be on and the second transistor to be on at the second timing.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be off and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be off at the first timing and the second transistor to be off at the second timing, a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing and the first transistor to be off and the second transistor to be on at the second timing, and a third mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing and the first transistor to be on and the second transistor to be on at the second timing.
Image sensor. 50. The imaging device according to claim 1,
a control unit that controls a first timing at which the charges converted by the first photoelectric conversion unit are transferred to the first diffusion unit and a second timing at which the charges converted by the second photoelectric conversion unit are transferred to the second diffusion unit so that the first timing and the second timing are different from each other;
the control unit executes one of a first mode in which the control unit controls the first transistor to be off and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be off at the second timing; a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing; and a third mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing.
Image sensor. An imaging device comprising the imaging element according to any one of claims 1 to 60. 62. The imaging device of claim 61,
An imaging device comprising an imaging control unit that controls the imaging element. 63. The imaging device of claim 62,
the imaging control unit controls an operation of the first transistor and an operation of the second transistor.
Imaging device. 64. The imaging device of claim 63,
the imaging control unit controls the operation of the first transistor and the operation of the second transistor based on a set ISO sensitivity.
Imaging device. 65. The imaging device according to any one of claims 61 to 64,
an imaging device including a driving unit for driving a photographing lens that emits light to the imaging element; 66. The imaging device of claim 65,
An imaging device comprising the above-mentioned photographic lens.