JP7726758B2

JP7726758B2 - Semiconductor Devices

Info

Publication number: JP7726758B2
Application number: JP2021192774A
Authority: JP
Inventors: 彩新留; 瑛祐梶原; 雅彦蔵口
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2021-06-08
Filing date: 2021-11-29
Publication date: 2025-08-20
Anticipated expiration: 2041-11-29
Also published as: JP2022187961A

Description

本発明の実施形態は、半導体装置に関する。 An embodiment of the present invention relates to a semiconductor device.

半導体装置において、安定した特性が望まれる。 Stable characteristics are desired in semiconductor devices.

特開２０１２－１７５０１８号公報JP 2012-175018 A

本発明の実施形態は、特性を安定化できる半導体装置を提供する。 Embodiments of the present invention provide a semiconductor device that can stabilize characteristics.

本発明の実施形態によれば、半導体装置は、第１電極、第２電極、第３電極、第１半導体領域、第２半導体領域、第１導電部材及び絶縁部材を含む。前記第１電極から前記第２電極への方向は第１方向に沿う。前記第３電極の前記第１方向における位置は、前記第１電極の前記第１方向における位置と、前記第２電極の前記第１方向における位置と、の間にある。前記第１半導体領域は、Ａｌ_ｘ１Ｇａ_１－ｘ１Ｎ（０≦ｘ１＜１）を含む。前記第１半導体領域は、第１部分領域、第２部分領域、第３部分領域、第４部分領域、第５部分領域及び第６部分領域を含む。前記第１部分領域から前記第１電極への方向、前記第２部分領域から前記第２電極への方向、及び、前記第３部分領域から前記第３電極への方向は、前記第１方向と交差する第２方向に沿う。前記第４部分領域は、前記第１方向において、前記第１部分領域と前記第３部分領域との間にある。前記第５部分領域は、前記第１方向において、前記第３部分領域と前記第２部分領域との間にある。前記第６部分領域は、前記第１方向において、前記第５部分領域と前記第２部分領域との間にある。前記第２半導体領域は、Ａｌ_ｘ２Ｇａ_１－ｘ２Ｎ（０＜ｘ２≦１、ｘ１＜ｘ２）を含む。前記第２半導体領域は、第１半導体部分、第２半導体部分及び第３半導体部分を含む。前記第４部分領域から前記第１半導体部分への方向は、前記第２方向に沿う。前記第１導電部材は、前記第１電極及び前記第３電極の第１の１つと電気的に接続される。または、前記第１の１つと電気的に接続されることが可能である。前記第１導電部材は、前記第１方向における第１導電端部を含む。前記第１導電端部の前記第１方向における位置は、前記第３電極の前記第１方向における前記位置と、前記第２電極の前記第１方向における位置と、の間にある。前記絶縁部材は、第１窒化物領域及び第２窒化物領域を含む。前記第２半導体部分は、前記第２方向において、前記第５部分領域と前記第１窒化物領域との間にある。前記第３半導体部分は、前記第２方向において、前記第６部分領域と前記第２窒化物領域との間にある。前記第１窒化物領域は、シリコン及び窒素を含む。前記第２窒化物領域は、シリコン及び窒素を含む。前記第１窒化物領域における窒素の濃度に対するシリコンの濃度の第１比は、前記第２窒化物領域における窒素の濃度に対するシリコンの濃度の第２比よりも低い。前記第１窒化物領域は、第１窒化物端部を含む。前記第１窒化物端部は、前記第２半導体領域と接し、前記第１方向において前記第２窒化物領域と対向する。前記第１窒化物端部の前記第１方向における位置は、前記第１導電端部の前記第１方向における前記位置と、前記第２電極の前記第１方向における前記位置と、の間にある。 According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first conductive member, and an insulating member. The direction from the first electrode to the second electrode is along a first direction. The position of the third electrode in the first direction is between the position of the first electrode in the first direction and the position of the second electrode in the first direction. The first semiconductor region includes Al _x1 Ga _1-x1 N (0≦x1<1). The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region. The direction from the first partial region to the first electrode, the direction from the second partial region to the second electrode, and the direction from the third partial region to the third electrode are along a second direction intersecting the first direction. The fourth partial region is between the first partial region and the third partial region in the first direction. The fifth partial region is located between the third partial region and the second partial region in the first direction. The sixth partial region is located between the fifth partial region and the second partial region in the first direction. The second semiconductor region includes Al _x2 Ga _1-x2 N (0 < x2 ≦ 1, x1 < x2). The second semiconductor region includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The first conductive member is electrically connected to a first one of the first electrode and the third electrode. Alternatively, it can be electrically connected to the first one. The first conductive member includes a first conductive end in the first direction. The position of the first conductive end in the first direction is between the position of the third electrode in the first direction and the position of the second electrode in the first direction. The insulating member includes a first nitride region and a second nitride region. The second semiconductor portion is between the fifth sub-region and the first nitride region in the second direction. The third semiconductor portion is between the sixth sub-region and the second nitride region in the second direction. The first nitride region includes silicon and nitrogen. The second nitride region includes silicon and nitrogen. A first ratio of a silicon concentration to a nitrogen concentration in the first nitride region is lower than a second ratio of a silicon concentration to a nitrogen concentration in the second nitride region. The first nitride region includes a first nitride end. The first nitride end contacts the second semiconductor region and faces the second nitride region in the first direction. A position of the first nitride end in the first direction is between the position of the first conductive end in the first direction and the position of the second electrode in the first direction.

図１は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. 図２は、半導体装置の特性を例示するグラフ図である。FIG. 2 is a graph illustrating the characteristics of the semiconductor device. 図３は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 3 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図４は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図５は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図６は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図７は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図８は、第１実施形態に係る半導体装置を例示する模式的断面図である。FIG. 8 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 図９は、第２実施形態に係る半導体装置を例示する模式的断面図である。FIG. 9 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. 図１０は、第３実施形態に係る半導体装置を例示する模式的断面図である。FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. 図１１は、第３実施形態に係る半導体装置を例示する模式的断面図である。FIG. 11 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. 図１２は、第４実施形態に係る半導体装置を例示する模式的断面図である。FIG. 12 is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment. 図１３は、第４実施形態に係る半導体装置を例示する模式的断面図である。FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.

以下に、本発明の各実施の形態について図面を参照しつつ説明する。
図面は模式的または概念的なものであり、各部分の厚さと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing.
In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

（第１実施形態）
図１は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図１に示すように、実施形態に係る半導体装置１１０は、第１電極５１、第２電極５２、第３電極５３、第１半導体領域１０、第２半導体領域２０、第１導電部材６１、及び、絶縁部材４０を含む。 (First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.
As shown in FIG. 1 , the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor region 10, a second semiconductor region 20, a first conductive member 61, and an insulating member 40.

第１電極５１から第２電極５２への方向は第１方向に沿う。第１方向をＸ軸方向とする。Ｘ軸方向に対して垂直な１つの方向をＺ軸方向とする。Ｘ軸方向及びＺ軸方向に対して垂直な方向をＹ軸方向とする。 The direction from the first electrode 51 to the second electrode 52 is along the first direction. The first direction is the X-axis direction. One direction perpendicular to the X-axis direction is the Z-axis direction. The direction perpendicular to the X-axis and Z-axis directions is the Y-axis direction.

第３電極５３の第１方向（Ｘ軸方向）における位置は、第１電極５１の第１方向における位置と、第２電極５２の第１方向における位置と、の間にある。１つの例において、第３電極５３の少なくとも一部が、第１方向において、第１電極５１と第２電極５２との間にある。 The position of the third electrode 53 in the first direction (X-axis direction) is between the position of the first electrode 51 in the first direction and the position of the second electrode 52 in the first direction. In one example, at least a portion of the third electrode 53 is between the first electrode 51 and the second electrode 52 in the first direction.

第１半導体領域１０は、Ａｌ_ｘ１Ｇａ_１－ｘ１Ｎ（０≦ｘ１＜１）を含む。組成比ｘ１は、例えば０以上０．２未満である。１つの例において、第１半導体領域１０は、ＧａＮ層である。または、第１半導体領域１０は、Ａｌ組成比が低い（例えば０．２未満）ＡｌＧａＮ層でも良い。 The first semiconductor region 10 contains Al _x1 Ga _1-x1 N (0≦x1<1). The composition ratio x1 is, for example, equal to or greater than 0 and less than 0.2. In one example, the first semiconductor region 10 is a GaN layer. Alternatively, the first semiconductor region 10 may be an AlGaN layer with a low Al composition ratio (for example, less than 0.2).

第１半導体領域１０は、第１部分領域１０ａ、第２部分領域１０ｂ、第３部分領域１０ｃ、第４部分領域１０ｄ、第５部分領域１０ｅ及び第６部分領域１０ｆを含む。第１部分領域１０ａから第１電極５１への方向、第２部分領域１０ｂから第２電極５２への方向、及び、第３部分領域１０ｃから第３電極５３への方向は、第２方向に沿う。第２方向は、例えばＺ軸方向である。例えば、第１部分領域１０ａは、第２方向において第１電極５１と重なる部分である。例えば、第２部分領域１０ｂは、第２方向において第２電極５２と重なる部分である。例えば、第３部分領域１０ｃは、第２方向において第３電極５３と重なる部分である。 The first semiconductor region 10 includes a first partial region 10a, a second partial region 10b, a third partial region 10c, a fourth partial region 10d, a fifth partial region 10e, and a sixth partial region 10f. The direction from the first partial region 10a to the first electrode 51, the direction from the second partial region 10b to the second electrode 52, and the direction from the third partial region 10c to the third electrode 53 are along the second direction. The second direction is, for example, the Z-axis direction. For example, the first partial region 10a is a portion that overlaps with the first electrode 51 in the second direction. For example, the second partial region 10b is a portion that overlaps with the second electrode 52 in the second direction. For example, the third partial region 10c is a portion that overlaps with the third electrode 53 in the second direction.

第４部分領域１０ｄは、第１方向（Ｘ軸方向）において、第１部分領域１０ａと第３部分領域１０ｃとの間にある。第５部分領域１０ｅは、第１方向において、第３部分領域１０ｃと第２部分領域１０ｂとの間にある。第６部分領域１０ｆは、第１方向において、第５部分領域１０ｅと第２部分領域１０ｂとの間にある。第１～第６部分領域１０ａ～１０ｆの互いの境界は不明確で良い。これらの部分領域のそれぞれは、第１半導体領域１０のなかの「部的な位置」でも良い。 The fourth partial region 10d is located between the first partial region 10a and the third partial region 10c in the first direction (X-axis direction). The fifth partial region 10e is located between the third partial region 10c and the second partial region 10b in the first direction. The sixth partial region 10f is located between the fifth partial region 10e and the second partial region 10b in the first direction. The boundaries between the first to sixth partial regions 10a to 10f may be unclear. Each of these partial regions may be a "partial position" within the first semiconductor region 10.

第２半導体領域２０は、Ａｌ_ｘ２Ｇａ_１－ｘ２Ｎ（０＜ｘ２≦１、ｘ１＜ｘ２）を含む。組成比ｘ２は、例えば、０．０５以上１以下である。第２半導体領域２０は、ＡｌＧａＮ層である。第２半導体領域２０におけるＡｌの組成比は、第１半導体領域１０におけるＡｌの組成比よりも高い。 The second semiconductor region 20 includes Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2). The composition ratio x2 is, for example, 0.05 or more and 1 or less. The second semiconductor region 20 is an AlGaN layer. The Al composition ratio in the second semiconductor region 20 is higher than the Al composition ratio in the first semiconductor region 10.

第２半導体領域２０は、第１半導体部分２１、第２半導体部分２２及び第３半導体部分２３を含む。第４部分領域１０ｄから第１半導体部分２１への方向は、第２方向（Ｚ軸方向）に沿う。第５部分領域１０ｅから第２半導体部分２２への方向は、第２方向（Ｚ軸方向）に沿う。第６部分領域１０ｆから第３半導体部分２３への方向は、第２方向（Ｚ軸方向）に沿う。図１に示すように、第２半導体領域２０は、第４半導体部分２４を含んでも良い。第４半導体部分２４は、第２方向において第３部分領域１０ｃと第３電極５３との間にある。第１～第４半導体部分２１～２４の互いの境界は不明確で良い。 The second semiconductor region 20 includes a first semiconductor portion 21, a second semiconductor portion 22, and a third semiconductor portion 23. The direction from the fourth sub-region 10d to the first semiconductor portion 21 is along the second direction (Z-axis direction). The direction from the fifth sub-region 10e to the second semiconductor portion 22 is along the second direction (Z-axis direction). The direction from the sixth sub-region 10f to the third semiconductor portion 23 is along the second direction (Z-axis direction). As shown in FIG. 1, the second semiconductor region 20 may include a fourth semiconductor portion 24. The fourth semiconductor portion 24 is located between the third sub-region 10c and the third electrode 53 in the second direction. The boundaries between the first to fourth semiconductor portions 21 to 24 may be unclear.

第１導電部材６１は、第１電極５１及び第３電極５３の第１の１つと電気的に接続される。または、第１導電部材６１は、上記の第１の１つと電気的に接続されることが可能である。この例では、第１導電部材６１は、接続部材６１Ｓにより、第１電極５１と電気的に接続される。接続部材６１Ｓは、図１に示す断面とは異なる位置に設けられても良い。接続部材６１Ｓは、半導体装置１１０とは別に設けられても良い。 The first conductive member 61 is electrically connected to a first one of the first electrode 51 and the third electrode 53. Alternatively, the first conductive member 61 can be electrically connected to the first one. In this example, the first conductive member 61 is electrically connected to the first electrode 51 by a connection member 61S. The connection member 61S may be provided at a position different from that shown in the cross section of FIG. 1. The connection member 61S may be provided separately from the semiconductor device 110.

第１導電部材６１は、第１方向（Ｘ軸方向）における端部（第１導電端部６１ｅ）を含む。第１導電端部６１ｅの第１方向における位置は、第３電極５３の第１方向における位置と、第２電極５２の第１方向における位置と、の間にある。第１導電端部６１ｅは、第１導電部材６１のうちの、第２電極５２の側の端部である。 The first conductive member 61 includes an end portion (first conductive end portion 61e) in the first direction (X-axis direction). The position of the first conductive end portion 61e in the first direction is between the position of the third electrode 53 in the first direction and the position of the second electrode 52 in the first direction. The first conductive end portion 61e is the end portion of the first conductive member 61 on the side of the second electrode 52.

絶縁部材４０は、第１窒化物領域４１及び第２窒化物領域４２を含む。第２半導体部分２２は、第２方向（Ｚ軸方向）において、第５部分領域１０ｅと第１窒化物領域４１との間にある。第３半導体部分２３は、第２方向において、第６部分領域１０ｆと第２窒化物領域４２との間にある。 The insulating member 40 includes a first nitride region 41 and a second nitride region 42. The second semiconductor portion 22 is located between the fifth sub-region 10e and the first nitride region 41 in the second direction (Z-axis direction). The third semiconductor portion 23 is located between the sixth sub-region 10f and the second nitride region 42 in the second direction.

第１窒化物領域４１は、シリコン及び窒素を含む。第２窒化物領域４２は、シリコン及び窒素を含む。これらの窒化物領域は、例えば、窒化シリコン層である。 The first nitride region 41 contains silicon and nitrogen. The second nitride region 42 contains silicon and nitrogen. These nitride regions are, for example, silicon nitride layers.

第１窒化物領域４１における窒素の濃度に対するシリコンの濃度の比を第１比（Ｓｉ／Ｎｉ）とする。第２窒化物領域４２における窒素の濃度に対するシリコンの濃度の比を第２比（Ｓｉ／Ｎ）とする。これらの濃度の比は、窒素の組成比に対するシリコンの組成比に対応する。実施形態において、第１比は、第２比よりも低い。第１窒化物領域４１は、例えば、相対的にＮリッチの窒化シリコン層である。第２窒化物領域４２は、例えば、相対的にＳｉリッチの窒化シリコン層である。Ｓｉ及び窒素の組成比は、窒化物領域を形成する際の条件（例えばＳｉの原料ガスの流量、及び、窒素の原料ガスの流量）を変更することで、変更できる。 The ratio of the silicon concentration to the nitrogen concentration in the first nitride region 41 is defined as a first ratio (Si/Ni). The ratio of the silicon concentration to the nitrogen concentration in the second nitride region 42 is defined as a second ratio (Si/N). These concentration ratios correspond to the silicon composition ratio to the nitrogen composition ratio. In the embodiment, the first ratio is lower than the second ratio. The first nitride region 41 is, for example, a relatively N-rich silicon nitride layer. The second nitride region 42 is, for example, a relatively Si-rich silicon nitride layer. The Si and nitrogen composition ratios can be changed by changing the conditions for forming the nitride regions (e.g., the flow rates of the Si source gas and the nitrogen source gas).

第１窒化物領域４１は、第１窒化物端部４１ｅを含む。第１窒化物端部４１ｅは、第２半導体領域２０と接し、第１方向（Ｘ軸方向）において第２窒化物領域４２と対向する。第１窒化物端部４１ｅは、第１窒化物領域４１のうちの、第２電極５２の側の端部である。第１窒化物端部４１ｅは、第２窒化物領域４２と接して良い。 The first nitride region 41 includes a first nitride end 41e. The first nitride end 41e contacts the second semiconductor region 20 and faces the second nitride region 42 in the first direction (X-axis direction). The first nitride end 41e is the end of the first nitride region 41 on the second electrode 52 side. The first nitride end 41e may contact the second nitride region 42.

第１窒化物端部４１ｅの第１方向（Ｘ軸方向）における位置は、第１導電端部６１ｅの第１方向における位置と、第２電極５２の第１方向における位置と、の間にある。例えば、第１窒化物端部４１ｅと第２電極５２との間の距離は、第１導電端部６１ｅと第２電極５２との間の距離よりも短い。 The position of the first nitride end 41e in the first direction (X-axis direction) is between the position of the first conductive end 61e in the first direction and the position of the second electrode 52 in the first direction. For example, the distance between the first nitride end 41e and the second electrode 52 is shorter than the distance between the first conductive end 61e and the second electrode 52.

例えば、第１半導体領域１０の第２半導体領域２０に対向する領域において、キャリア領域１０Ｃが形成される。キャリア領域１０Ｃは、例えば２次元電子ガスである。第１電極５１と第３電極５３との間の距離は、第２電極５２と第３電極５３との間の距離よりも短い。 For example, a carrier region 10C is formed in the region of the first semiconductor region 10 facing the second semiconductor region 20. The carrier region 10C is, for example, a two-dimensional electron gas. The distance between the first electrode 51 and the third electrode 53 is shorter than the distance between the second electrode 52 and the third electrode 53.

第１電極５１と第２電極５２との間に流れる電流は、第３電極５３の電位により制御できる。第３電極５３の電位は、例えば、第１電極５１の電位を基準とした電位である。第１電極５１は、例えば、ソース電極として機能する。第２電極５２は、例えば、ドレイン電極として機能する。第３電極５３は、例えば、ゲート電極として機能する。半導体装置１１０は、例えば、ＨＥＭＴ（High Electron Mobility Transistor）である。第１導電部材６１は、例えばフィールドプレートとして機能する。第１導電部材６１が設けられることで、電界の集中が抑制される。 The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 is, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions, for example, as a source electrode. The second electrode 52 functions, for example, as a drain electrode. The third electrode 53 functions, for example, as a gate electrode. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor). The first conductive member 61 functions, for example, as a field plate. The presence of the first conductive member 61 suppresses electric field concentration.

上記のように、実施形態に係る半導体装置１１０においては、組成が異なる窒化物領域が設けられる。第１窒化物領域４１の端（第１窒化物端部４１ｅ）が、第１導電端部６１ｅと第２電極５２との間に設けられる。これにより、例えば、電流コラプスが抑制できる。例えば、高い耐圧を維持できる。実施形態によれば、特性を安定化できる半導体装置が提供できる。 As described above, the semiconductor device 110 according to the embodiment has nitride regions with different compositions. The end of the first nitride region 41 (first nitride end 41e) is provided between the first conductive end 61e and the second electrode 52. This makes it possible to suppress current collapse, for example. For example, it makes it possible to maintain a high breakdown voltage. According to the embodiment, a semiconductor device with stable characteristics can be provided.

例えば、組成が互いに異なる第１窒化物領域４１及び第２窒化物領域４２の代わりに、組成が均一な窒化物領域が第２半導体領域２０の上に設けられる参考例がある。この参考例において、窒化物領域の全体がＮリッチである場合、電流コラプスが大きくなる。一方、参考例において、窒化物領域の全体がＳｉリッチである場合、耐圧が低くなる傾向がある。 For example, in one reference example, instead of the first nitride region 41 and the second nitride region 42 having different compositions, a nitride region with a uniform composition is provided on the second semiconductor region 20. In this reference example, if the entire nitride region is N-rich, current collapse increases. On the other hand, in this reference example, if the entire nitride region is Si-rich, the breakdown voltage tends to decrease.

電流コラプスは、第２電極５２（例えばドレイン電極）の近傍の特性に依存する傾向があることがわかった。一方、耐圧は、第３電極５３（例えばゲート電極）及び第１導電部材６１（例えばフィールドプレート）の近傍の特性に依存する傾向があることがわかった。実施形態においては、第３電極５３と第２電極５２との間の領域において、窒化物領域の組成比を変化させる。これにより、電流コラプスを抑制しつつ高い耐圧が得られる。実施形態によれば、特性を安定化できる半導体装置が提供できる。 It has been found that current collapse tends to depend on the characteristics in the vicinity of the second electrode 52 (e.g., drain electrode). Meanwhile, it has been found that the breakdown voltage tends to depend on the characteristics in the vicinity of the third electrode 53 (e.g., gate electrode) and the first conductive member 61 (e.g., field plate). In the embodiment, the composition ratio of the nitride region is changed in the region between the third electrode 53 and the second electrode 52. This makes it possible to obtain a high breakdown voltage while suppressing current collapse. According to the embodiment, a semiconductor device with stable characteristics can be provided.

例えば、ゲート電極の近傍にＳｉリッチの窒化物領域を適用すると、耐圧が低下し易い。これは、以下が原因であると考えられる。 For example, applying a Si-rich nitride region near the gate electrode tends to reduce the breakdown voltage. This is thought to be due to the following reasons:

窒化物領域における組成比Ｓｉ／Ｎが高く、窒化物領域がＳｉリッチになると、例えば、キャリア領域１０Ｃ（２次元電子ガス）の空乏化電圧が上昇する。このため、ゲート電極の近傍にＳｉリッチの窒化物領域を適用すると、空乏化電圧の上昇に伴って、空乏層がドレイン電極側に広がり難くなる。このため、ゲート電極の近傍にＳｉリッチの窒化物領域を適用するとゲート電極の付近に電界が集中し易くなる。このため、耐圧が低下し易くなる。 When the composition ratio Si/N in the nitride region is high and the nitride region becomes Si-rich, for example, the depletion voltage of the carrier region 10C (two-dimensional electron gas) increases. Therefore, when a Si-rich nitride region is applied near the gate electrode, the depletion layer becomes less likely to spread toward the drain electrode as the depletion voltage increases. Therefore, when a Si-rich nitride region is applied near the gate electrode, the electric field tends to concentrate near the gate electrode. This makes it easier for the breakdown voltage to decrease.

空乏層がドレイン電極に到達すると、ドレイン電極の近傍において電界が集中して、電流コラプスが増大し易くなる。ドレイン電極の近傍にＳｉリッチの窒化物領域を適用することで、空乏層がドレイン電極に到達する電圧を上昇させることができる。これにより電流コラプスを抑制できる。 When the depletion layer reaches the drain electrode, the electric field concentrates near the drain electrode, making it more likely that current collapse will increase. By applying a Si-rich nitride region near the drain electrode, the voltage at which the depletion layer reaches the drain electrode can be increased, thereby suppressing current collapse.

例えば、第３電極５３の近くの窒化物領域におけるＳｉ／Ｎの比を低くし（Ｎリッチ）、第２電極５２の近くの窒化物領域におけるＳｉ／Ｎの比を高く（Ｓｉリッチ）することで、高い耐圧を維持しつつ電流コラプスを抑制できる。 For example, by lowering the Si/N ratio in the nitride region near the third electrode 53 (N-rich) and increasing the Si/N ratio in the nitride region near the second electrode 52 (Si-rich), it is possible to suppress current collapse while maintaining a high breakdown voltage.

図１に示すように、第２電極５２は、第２電極端部５２ｅを含む。第２電極端部５２ｅは、第３半導体部分２３（第２半導体領域２０）及び第２窒化物領域４２と接する。第２電極端部５２ｅは、第２電極５２と第２半導体領域２０とが互いに接する部分の、第３電極５３側の端部に対応する。 As shown in FIG. 1, the second electrode 52 includes a second electrode end 52e. The second electrode end 52e contacts the third semiconductor portion 23 (second semiconductor region 20) and the second nitride region 42. The second electrode end 52e corresponds to the end of the contact portion between the second electrode 52 and the second semiconductor region 20 on the third electrode 53 side.

第１導電端部６１ｅの第１方向（Ｘ軸方向）における位置と、第１窒化物端部４１ｅの第１方向における位置と、の間の第１方向に沿う距離を第１距離Ｌ１とする。第１導電端部６１ｅの第１方向における位置と、第２電極端部５２ｅの第１方向における位置と、の間の第１方向に沿う距離を第２距離Ｌ２とする。実施形態において、第１距離Ｌ１は、０を超える。第１距離Ｌ１は、第２距離Ｌ２未満である。 The distance along the first direction (X-axis direction) between the position of the first conductive end 61e and the position of the first nitride end 41e in the first direction is defined as the first distance L1. The distance along the first direction between the position of the first conductive end 61e in the first direction and the position of the second electrode end 52e in the first direction is defined as the second distance L2. In the embodiment, the first distance L1 is greater than 0. The first distance L1 is less than the second distance L2.

図２は、半導体装置の特性を例示するグラフ図である。
図２は、第２半導体領域２０の上に、上記の第１窒化物領域４１及び第２窒化物領域４２を設けたときの特性を例示している。図２の横軸は、第１距離Ｌ１の第２距離Ｌ２に対する比ＲＬである。比ＲＬが０のときは、第１窒化物端部４１ｅが第１導電端部６１ｅとＺ軸方向において重なる。比ＲＬが１のときは、第１窒化物端部４１ｅが第２電極端部５２ｅとＺ軸方向において重なる。図２の縦軸は、ドレイン電圧ストレスを加えたときの抵抗増加率ＣＣ１である。抵抗増加率ＣＣ１の高低は、電流コラプスの大小に対応する。この例では、第１窒化物領域４１におけるＳｉ／Ｎの比は、０．６９であり、第２窒化物領域４２におけるＳｉ／Ｎの比は、０．８０である。図２において、１つの比ＲＬについて３つの黒丸が示されている。３の黒丸は、１つの比ＲＬの条件に関して取得された３つのデータに対応する。白丸は、３つのデータの中央値に対応する。 FIG. 2 is a graph illustrating the characteristics of the semiconductor device.
FIG. 2 illustrates the characteristics when the first nitride region 41 and the second nitride region 42 are provided on the second semiconductor region 20. The horizontal axis of FIG. 2 represents the ratio RL of the first distance L1 to the second distance L2. When the ratio RL is 0, the first nitride end 41e overlaps with the first conductive end 61e in the Z-axis direction. When the ratio RL is 1, the first nitride end 41e overlaps with the second electrode end 52e in the Z-axis direction. The vertical axis of FIG. 2 represents the resistance increase rate CC1 when a drain voltage stress is applied. The level of the resistance increase rate CC1 corresponds to the magnitude of current collapse. In this example, the Si/N ratio in the first nitride region 41 is 0.69, and the Si/N ratio in the second nitride region 42 is 0.80. In FIG. 2, three black circles are shown for each ratio RL. The three black circles correspond to three data points acquired for one ratio RL condition. The open circle corresponds to the median of the triplicate data.

図２に示すように、この条件の場合、比ＲＬが０．１５よりも低い場合（図中の破線よりも低）、絶縁破壊が生じる。比ＲＬが０．１５以上において、抵抗増加率ＣＣ１が低いと、小さい電流コラプスが得られる。実施形態において、比ＲＬは０．４３以上であることが好ましい。これにより、高い耐圧が得やすい。比ＲＬは０．７以上であることがさらに好ましい。これにより、高い耐圧が安定して得られ、電流コラプスが効果的に抑制できる。比ＲＬは、１未満であることが好ましい。比ＲＬは、例えば、０．９６以下であることが好ましい。 As shown in Figure 2, under these conditions, if the ratio RL is lower than 0.15 (lower than the dashed line in the figure), dielectric breakdown occurs. When the ratio RL is 0.15 or higher and the resistance increase rate CC1 is low, small current collapse is obtained. In this embodiment, the ratio RL is preferably 0.43 or higher. This makes it easier to obtain a high breakdown voltage. It is even more preferable that the ratio RL is 0.7 or higher. This ensures a stable high breakdown voltage and effectively suppresses current collapse. The ratio RL is preferably less than 1. For example, the ratio RL is preferably 0.96 or less.

実施形態において、第１窒化物領域４１における第１比（Ｓｉ／Ｎ）は、例えば、０．７５よりも低いことが好ましい。第１比は、０．７２以下でも良い。 In this embodiment, the first ratio (Si/N) in the first nitride region 41 is preferably lower than 0.75, for example. The first ratio may be 0.72 or less.

実施形態において、第２窒化物領域４２における第２比（Ｓｉ／Ｎ）は、例えば、０．７５以上であることが好ましい。第２比は、０．７５以上０．９６以下でも良い。第２比は、第２比は、０．７８以上０．９６以下でも良い。第２比は、０．７８以上０．９３以下でも良い。第２比は、０．７８以上０．８５以下でも良い。 In this embodiment, the second ratio (Si/N) in the second nitride region 42 is preferably, for example, 0.75 or greater. The second ratio may be 0.75 or greater and 0.96 or less. The second ratio may be 0.78 or greater and 0.96 or less. The second ratio may be 0.78 or greater and 0.93 or less. The second ratio may be 0.78 or greater and 0.85 or less.

図１に示すように、半導体装置１１０は、基体１０ｓ及び窒化物層１１Ｂを含んでも良い。基体１０ｓの上に窒化物層１１Ｂが設けられる。窒化物層１１Ｂの上に第１半導体領域１０が設けられる。第１半導体領域１０の上に第２半導体領域２０が設けられる。基体１０ｓは、例えば、基板である。基体１０ｓは、例えば、シリコン基板またはＳｉＣ基板などでも良い。窒化物層１１Ｂは、例えば、窒化物半導体を含んでも良い。窒化物層１１Ｂは、例えば、Ａｌ、Ｇａ及びＮを含む。窒化物層１１Ｂは、例えば、バッファ層である。 As shown in FIG. 1, the semiconductor device 110 may include a base body 10s and a nitride layer 11B. The nitride layer 11B is provided on the base body 10s. A first semiconductor region 10 is provided on the nitride layer 11B. A second semiconductor region 20 is provided on the first semiconductor region 10. The base body 10s is, for example, a substrate. The base body 10s may be, for example, a silicon substrate or a SiC substrate. The nitride layer 11B may include, for example, a nitride semiconductor. The nitride layer 11B includes, for example, Al, Ga, and N. The nitride layer 11B is, for example, a buffer layer.

図１に示すように、第１窒化物領域４１の第２方向（Ｚ軸方向）に沿う厚さを厚さｔ１とする。厚さｔ１は、例えば、０．５ｎｍ以上３００ｎｍ以下である。第２窒化物領域４２の第２方向に沿う厚さを厚さｔ２とする。厚さｔ２は、例えば、０．５ｎｍ以上３００ｎｍ以下であることが好ましい。このような厚さにより、例えば、所望のしきい値電圧が得やすくなる。このような厚さにより、例えば、高いゲート信頼性が得やすくなる。例えば、厚さｔ１は、１０ｎｍ以上１００ｎｍ以下でも良い。 As shown in FIG. 1, the thickness of the first nitride region 41 along the second direction (Z-axis direction) is defined as thickness t1. Thickness t1 is, for example, 0.5 nm or more and 300 nm or less. The thickness of the second nitride region 42 along the second direction is defined as thickness t2. Thickness t2 is preferably, for example, 0.5 nm or more and 300 nm or less. Such a thickness makes it easier to obtain, for example, a desired threshold voltage. Such a thickness makes it easier to obtain, for example, high gate reliability. For example, thickness t1 may be 10 nm or more and 100 nm or less.

図１に示すように、絶縁部材４０の一部４０ｐは、第３電極５３と第１導電部材６１との間に設けられても良い。絶縁部材４０の一部４０ｐは、例えば、シリコンと、第１元素と、を含む。第１元素は、酸素及び窒素の少なくともいずれかを含む。１つの例において、絶縁部材４０の一部４０ｐは、酸化シリコンを含む。この場合、絶縁部材４０の一部４０ｐは窒素を含まなくても良い。または、第１窒化物領域４１及び第２窒化物領域４２における窒素の濃度は、絶縁部材４０の一部４０ｐにおける窒素の濃度よりも高くても良い。絶縁部材４０の一部４０ｐは、第３電極５３と第１導電部材６１との間を電気的に絶縁する。絶縁部材４０の一部４０ｐは、窒化シリコンでも良い。 As shown in FIG. 1, the portion 40p of the insulating member 40 may be provided between the third electrode 53 and the first conductive member 61. The portion 40p of the insulating member 40 includes, for example, silicon and a first element. The first element includes at least one of oxygen and nitrogen. In one example, the portion 40p of the insulating member 40 includes silicon oxide. In this case, the portion 40p of the insulating member 40 may not include nitrogen. Alternatively, the nitrogen concentration in the first nitride region 41 and the second nitride region 42 may be higher than the nitrogen concentration in the portion 40p of the insulating member 40. The portion 40p of the insulating member 40 electrically insulates the third electrode 53 from the first conductive member 61. The portion 40p of the insulating member 40 may be silicon nitride.

図１に示すように、第２窒化物領域４２の少なくとも一部は、第３半導体部分２３と接する。第１窒化物領域４１の少なくとも一部は、第２半導体部分２２と接する。この例では、第１窒化物領域４１から第２窒化物領域４２への方向は、第１方向（Ｘ軸方向）に沿う。 As shown in FIG. 1, at least a portion of the second nitride region 42 contacts the third semiconductor portion 23. At least a portion of the first nitride region 41 contacts the second semiconductor portion 22. In this example, the direction from the first nitride region 41 to the second nitride region 42 is along the first direction (X-axis direction).

以下、実施形態に係る半導体装置に関してのいくつかの例について説明する。
図３は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図３に示すように、実施形態に係る半導体装置１１０ａにおいては、第２窒化物領域４２の少なくとも一部は、第２方向（Ｚ軸方向）において、第３半導体部分２３と第１窒化物領域４１の一部との間にある。例えば、第１窒化物領域４１の一部が、第２窒化物領域４２の上に設けられる。半導体装置１１０ａにおけるこれ以外の構成は、半導体装置１１０の構成と同様で良い。 Hereinafter, several examples of semiconductor devices according to the embodiments will be described.
FIG. 3 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
3 , in the semiconductor device 110a according to the embodiment, at least a portion of the second nitride region 42 is located between the third semiconductor portion 23 and a portion of the first nitride region 41 in the second direction (Z-axis direction). For example, a portion of the first nitride region 41 is provided on the second nitride region 42. Other configurations of the semiconductor device 110a may be similar to those of the semiconductor device 110.

図４は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図４に示すように、実施形態に係る半導体装置１１０ｂにおいては、第１窒化物領域４１の少なくとも一部は、第２方向（Ｚ軸方向）において、第２半導体部分２２と第２窒化物領域４２の一部との間にある。例えば、第２窒化物領域４２の一部が、第１窒化物領域４１の上に設けられる。半導体装置１１０ｂにおけるこれ以外の構成は、半導体装置１１０の構成と同様で良い。 FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
4 , in the semiconductor device 110b according to the embodiment, at least a portion of the first nitride region 41 is located between the second semiconductor portion 22 and a portion of the second nitride region 42 in the second direction (Z-axis direction). For example, a portion of the second nitride region 42 is provided on the first nitride region 41. Other configurations of the semiconductor device 110b may be similar to those of the semiconductor device 110.

図５は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図５に示すように、実施形態に係る半導体装置１１０ｃにおいては、第３電極５３は、第２方向（Ｚ軸方向）において第１窒化物領域４１の一部と第２窒化物領域４２の一部との間にある。半導体装置１１０ｃにおけるこれ以外の構成は、半導体装置１１０ｂの構成と同様で良い。 FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
5, in the semiconductor device 110c according to the embodiment, the third electrode 53 is located in the second direction (Z-axis direction) between a part of the first nitride region 41 and a part of the second nitride region 42. Other configurations of the semiconductor device 110c may be similar to those of the semiconductor device 110b.

半導体装置１１０ａ～１１０ｃにおいても、例えば、電流コラプスが抑制できる。例えば、高い耐圧を維持できる。特性を安定化できる半導体装置が提供できる。 In semiconductor devices 110a to 110c, for example, current collapse can be suppressed. For example, a high breakdown voltage can be maintained. This allows for the provision of semiconductor devices with stable characteristics.

半導体装置１１０、及び、１１０ａ～１１０ｃにおいて、第１窒化物領域４１の一部は、第２方向（Ｚ軸方向）において第２半導体領域２０と第３電極５３との間にある。第１窒化物領域４１の一部は、第３部分領域１０ｃと第３電極５３との間にある。 In the semiconductor devices 110 and 110a-110c, a portion of the first nitride region 41 is located between the second semiconductor region 20 and the third electrode 53 in the second direction (Z-axis direction). A portion of the first nitride region 41 is located between the third partial region 10c and the third electrode 53.

図６は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図６に示すように、実施形態に係る半導体装置１１１においては、第１導電部材６１は、接続部材６１Ｇにより、第３電極５３と電気的に接続されている。半導体装置１１１におけるこれ以外の構成は、半導体装置１１０の構成と同様で良い。 FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
6 , in the semiconductor device 111 according to the embodiment, the first conductive member 61 is electrically connected to the third electrode 53 by a connecting member 61G. Other configurations of the semiconductor device 111 may be similar to those of the semiconductor device 110.

図７は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図７に示すように、実施形態に係る半導体装置１１２においては、第１導電部材６１及び第２導電部材６２が設けられる。半導体装置１１２におけるこれ以外の構成は、半導体装置１１０の構成と同様で良い。 FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
7, a semiconductor device 112 according to the embodiment is provided with a first conductive member 61 and a second conductive member 62. Other configurations of the semiconductor device 112 may be similar to those of the semiconductor device 110.

既に説明したように、第１導電部材６１は、第１電極５１及び第３電極５３の第１の１つと電気的に接続される。または、第１導電部材６１は、上記の第１の１つと電気的に接続されることが可能である。この例では、第１導電部材６１は、接続部材６１Ｓにより、第１電極５１と電気的に接続される。 As already explained, the first conductive member 61 is electrically connected to a first one of the first electrode 51 and the third electrode 53. Alternatively, the first conductive member 61 can be electrically connected to the first one of the electrodes. In this example, the first conductive member 61 is electrically connected to the first electrode 51 by the connecting member 61S.

第２導電部材６２は、第１電極５１及び第３電極５３の第２の１つと電気的に接続される。または、第２導電部材６２は、上記の第２の１つと電気的に接続されることが可能である。上記の第２の１つは、第１電極５１及び第３電極５３の他方でも良い。この例では、第２導電部材６２は、接続部材６２Ｇにより、第３電極５３と電気的に接続される。 The second conductive member 62 is electrically connected to a second one of the first electrode 51 and the third electrode 53. Alternatively, the second conductive member 62 can be electrically connected to the second one. The second one may also be the other of the first electrode 51 and the third electrode 53. In this example, the second conductive member 62 is electrically connected to the third electrode 53 by the connection member 62G.

第２導電部材６２は、第１方向（Ｘ軸方向）における第２導電端部６２ｅを含む。第２導電端部６２ｅの第１方向における位置は、第３電極５３の第１方向における位置と、第１導電端部６１ｅの第１方向における位置と、の間にある。第２導電部材６２は、第２のフィールドプレートとして機能する。第２導電部材６２が設けられることで、電界の集中がより抑制される。 The second conductive member 62 includes a second conductive end 62e in the first direction (X-axis direction). The position of the second conductive end 62e in the first direction is between the position of the third electrode 53 in the first direction and the position of the first conductive end 61e in the first direction. The second conductive member 62 functions as a second field plate. The presence of the second conductive member 62 further suppresses the concentration of the electric field.

第２導電部材６２の第２方向（Ｚ軸方向）における位置は、第３電極５３の第２方向における位置と、第１導電部材６１の第２方向における位置と、の間にある。 The position of the second conductive member 62 in the second direction (Z-axis direction) is between the position of the third electrode 53 in the second direction and the position of the first conductive member 61 in the second direction.

図８は、第１実施形態に係る半導体装置を例示する模式的断面図である。
図８に示すように、実施形態に係る半導体装置１１３においては、第１導電部材６１、第２導電部材６２及び第３導電部材６３が設けられる。半導体装置１１３におけるこれ以外の構成は、半導体装置１１０～１１２の構成と同様で良い。 FIG. 8 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
8, the semiconductor device 113 according to the embodiment is provided with a first conductive member 61, a second conductive member 62, and a third conductive member 63. Other configurations of the semiconductor device 113 may be similar to those of the semiconductor devices 110 to 112.

第３導電部材６３は、第２電極５２と電気的に接続される。または、第３導電部材６３は、第２電極５２と電気的に接続されることが可能である。この例では、第３導電部材６３は、接続部材６３Ｄにより第２電極５２と電気的に接続される。 The third conductive member 63 is electrically connected to the second electrode 52. Alternatively, the third conductive member 63 can be electrically connected to the second electrode 52. In this example, the third conductive member 63 is electrically connected to the second electrode 52 by the connecting member 63D.

第３導電部材６３は、第１方向（第１方向）における第３導電端部６３ｅを含む。第３導電端部６３ｅは、例えば、第３導電部材６３の第３電極５３の側の端部である。第１窒化物端部４１ｅの第１方向（第１方向）における位置は、第１導電端部６１ｅの第１方向における位置と、第３導電端部６３ｅとの第１方向における位置と、の間にある。 The third conductive member 63 includes a third conductive end 63e in the first direction (first direction). The third conductive end 63e is, for example, the end of the third conductive member 63 on the third electrode 53 side. The position of the first nitride end 41e in the first direction (first direction) is between the position of the first conductive end 61e in the first direction and the position of the third conductive end 63e in the first direction.

半導体装置１１１～１１３においても、例えば、電流コラプスが抑制できる。例えば、高い耐圧を維持できる。特性を安定化できる半導体装置が提供できる。 In semiconductor devices 111-113, for example, current collapse can be suppressed. For example, a high breakdown voltage can be maintained. A semiconductor device with stable characteristics can be provided.

（第２実施形態）
図９は、第２実施形態に係る半導体装置を例示する模式的断面図である。
図９に示すように、実施形態に係る半導体装置１２０も、第１～第３電極５１～５３、第１半導体領域１０、第２半導体領域２０、第１導電部材６１、及び、絶縁部材４０を含む。絶縁部材４０は、第１絶縁膜４５を含む。半導体装置１２０において、第１～第３電極５１～５３、第１半導体領域１０、第２半導体領域２０、及び、第１導電部材６１には、第１実施形態に関して説明した構成を適用できる。 Second Embodiment
FIG. 9 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.
9, the semiconductor device 120 according to the embodiment also includes first to third electrodes 51 to 53, a first semiconductor region 10, a second semiconductor region 20, a first conductive member 61, and an insulating member 40. The insulating member 40 includes a first insulating film 45. In the semiconductor device 120, the configurations described in relation to the first embodiment can be applied to the first to third electrodes 51 to 53, the first semiconductor region 10, the second semiconductor region 20, and the first conductive member 61.

第１絶縁膜４５は、第１絶縁領域４５ａを含む。第１絶縁領域４５ａは、第３部分領域１０ｃと第３電極５３との間に設けられる。第１絶縁領域４５ａは、例えば、ゲート絶縁膜として機能する。 The first insulating film 45 includes a first insulating region 45a. The first insulating region 45a is provided between the third partial region 10c and the third electrode 53. The first insulating region 45a functions, for example, as a gate insulating film.

第１絶縁膜４５は、シリコンと酸素とを含む。第１絶縁膜４５は窒素を含まない。または、第１絶縁膜４５における窒素の濃度は、第２窒化物領域４２における窒素の濃度よりも低い。第１絶縁膜４５は、例えば、酸化シリコン膜（例えば二酸化シリコン膜）である。第１絶縁膜４５が設けられることで、しきい値電圧の変化がより抑制できる。 The first insulating film 45 contains silicon and oxygen. The first insulating film 45 does not contain nitrogen. Alternatively, the nitrogen concentration in the first insulating film 45 is lower than the nitrogen concentration in the second nitride region 42. The first insulating film 45 is, for example, a silicon oxide film (e.g., a silicon dioxide film). By providing the first insulating film 45, changes in the threshold voltage can be further suppressed.

半導体装置１２０においても、第１窒化物領域４１及び第２窒化物領域４２が設けられる。第１窒化物領域４１における窒素の濃度に対するシリコンの濃度の第１比（Ｓｉ／Ｎ）は、第２窒化物領域４２における窒素の濃度に対するシリコンの濃度の第２比（Ｓｉ／Ｎ）よりも低い。第１窒化物端部４１ｅの第１方向（Ｘ軸方向）における位置は、第１導電端部６１ｅの第１方向における位置と、第２電極５２の第１方向における位置と、の間にある。例えば、電流コラプスが抑制できる。例えば、高い耐圧を維持できる。特性を安定化できる半導体装置が提供できる。 The semiconductor device 120 also has a first nitride region 41 and a second nitride region 42. The first ratio of the silicon concentration to the nitrogen concentration (Si/N) in the first nitride region 41 is lower than the second ratio of the silicon concentration to the nitrogen concentration (Si/N) in the second nitride region 42. The position of the first nitride end 41e in the first direction (X-axis direction) is between the position of the first conductive end 61e in the first direction and the position of the second electrode 52 in the first direction. For example, current collapse can be suppressed. For example, a high breakdown voltage can be maintained. A semiconductor device with stable characteristics can be provided.

図９に示すように、この例では、第３電極５３の少なくとも一部は、第１方向（Ｘ軸方向）において第１半導体部分２１と第２半導体部分２２との間にある。第３電極５３はリセス型のゲートである。このような構成により、例えば、高いしきい値が得やすい。例えば、ノーマリオフの特性が得られる。 As shown in FIG. 9 , in this example, at least a portion of the third electrode 53 is located between the first semiconductor portion 21 and the second semiconductor portion 22 in the first direction (X-axis direction). The third electrode 53 is a recessed gate. This configuration makes it easier to obtain, for example, a high threshold voltage. For example, normally-off characteristics can be obtained.

図９に示すように、第１絶縁膜４５は、第２絶縁領域４５ｂ及び第３絶縁領域４５ｃを含んでも良い。第２絶縁領域４５ｂは、第１方向（Ｘ軸方向）において、第１半導体部分２１と第３電極５３との間にある。第３絶縁領域４５ｃは、第１方向において、第３電極５３と第２半導体部分２２との間にある。 As shown in FIG. 9 , the first insulating film 45 may include a second insulating region 45b and a third insulating region 45c. The second insulating region 45b is located between the first semiconductor portion 21 and the third electrode 53 in the first direction (X-axis direction). The third insulating region 45c is located between the third electrode 53 and the second semiconductor portion 22 in the first direction.

図９に示すように、第１絶縁膜４５は、第４絶縁領域４５ｄ及び第５絶縁領域４５ｅを含んでも良い。第１半導体部分２１は、第２方向（Ｚ軸方向）において、第４部分領域１０ｄと第４絶縁領域４５ｄとの間にある。第２半導体部分２２は、第２方向において、第５部分領域１０ｅと第５絶縁領域４５ｅとの間にある。例えば、第１窒化物領域４１は、第２半導体部分２２と、第５絶縁領域４５ｅの一部と、の間にある。 As shown in FIG. 9 , the first insulating film 45 may include a fourth insulating region 45d and a fifth insulating region 45e. The first semiconductor portion 21 is located between the fourth partial region 10d and the fourth insulating region 45d in the second direction (Z-axis direction). The second semiconductor portion 22 is located between the fifth partial region 10e and the fifth insulating region 45e in the second direction. For example, the first nitride region 41 is located between the second semiconductor portion 22 and a portion of the fifth insulating region 45e.

（第３実施形態）
図１０は、第３実施形態に係る半導体装置を例示する模式的断面図である。
図１０に示すように、実施形態に係る半導体装置１３０も、第１～第３電極５１～５３、第１半導体領域１０、第２半導体領域２０、第１導電部材６１、及び、絶縁部材４０を含む。半導体装置１３０において、第３電極５３の一部５３ａから第１窒化物領域４１への方向は、第２方向（例えばＺ軸方向）と交差する。半導体装置１３０におけるこれ以外の構成には、第１実施形態に関して説明した構成を適用できる。 (Third embodiment)
FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment.
10 , the semiconductor device 130 according to the embodiment also includes first to third electrodes 51 to 53, a first semiconductor region 10, a second semiconductor region 20, a first conductive member 61, and an insulating member 40. In the semiconductor device 130, the direction from a portion 53a of the third electrode 53 to the first nitride region 41 intersects with the second direction (e.g., the Z-axis direction). The configuration described in relation to the first embodiment can be applied to other configurations of the semiconductor device 130.

例えば、第１方向（Ｘ軸方向）において、第３電極５３の一部５３ａは、第１窒化物領域４１の複数の部分の間にある。例えば、第３電極５３の一部５３ａは、第２半導体領域２０（第４半導体部分２４）に接して良い。半導体装置１３０は、例えば、高周波用トランジスタである。 For example, in the first direction (X-axis direction), portion 53a of third electrode 53 is located between multiple portions of first nitride region 41. For example, portion 53a of third electrode 53 may be in contact with second semiconductor region 20 (fourth semiconductor portion 24). The semiconductor device 130 is, for example, a high-frequency transistor.

図１１は、第３実施形態に係る半導体装置を例示する模式的断面図である。
図１１に示すように、実施形態に係る半導体装置１３１は、第１～第３電極５１～５３、第１半導体領域１０、第２半導体領域２０、第３半導体領域３０、第１導電部材６１、及び、絶縁部材４０を含む。半導体装置１３１におけるこれ以外の構成には、第１実施形態に関して説明した構成を適用できる。 FIG. 11 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment.
11, the semiconductor device 131 according to the embodiment includes first to third electrodes 51 to 53, a first semiconductor region 10, a second semiconductor region 20, a third semiconductor region 30, a first conductive member 61, and an insulating member 40. The configuration described in relation to the first embodiment can be applied to other components of the semiconductor device 131.

第３半導体領域３０は、第４半導体部分２４と第３電極５３との間に設けられる。第３半導体領域３０は、Ａｌ_ｘ３Ｇａ_１－ｘ３Ｎ（０≦ｘ３＜１）と、第２元素と、を含む。第２元素は、Ｍｇ及びＺｎよりなる群から選択された少なくとも１つを含む。第３半導体領域３０は、例えば、ｐ形のＧａＮ層である。第３半導体領域３０は、例えば、ｐ形のＡｌＧａＮ層である。第３半導体領域３０がｐ形のＡｌＧａＮ層である場合、組成比ｘ３は、例えば、０を超え（例えば０．０５以上）、０．５以下である。半導体装置１３１は、例えば、ＪＦＥＴ型のトランジスタである。 The third semiconductor region 30 is provided between the fourth semiconductor portion 24 and the third electrode 53. The third semiconductor region 30 includes Al _x3 Ga _1-x3 N (0≦x3<1) and a second element. The second element includes at least one selected from the group consisting of Mg and Zn. The third semiconductor region 30 is, for example, a p-type GaN layer. The third semiconductor region 30 is, for example, a p-type AlGaN layer. When the third semiconductor region 30 is a p-type AlGaN layer, the composition ratio x3 is, for example, greater than 0 (for example, 0.05 or more) and 0.5 or less. The semiconductor device 131 is, for example, a JFET transistor.

第３実施形態においても、特性を安定にできる半導体装置が提供される。第３実施形態に係る半導体装置（半導体装置１３０または１３１）の構成が、第２実施形態に適用されても良い。 The third embodiment also provides a semiconductor device that can stabilize characteristics. The configuration of the semiconductor device according to the third embodiment (semiconductor device 130 or 131) may be applied to the second embodiment.

実施形態において、第１電極５１及び第２電極５２の少なくともいずれかは、例えば、Ｔｉ、Ａｌ、Ｃｕ及びＡｕよりなる群から選択された少なくとも１つを含む。例えば、第３電極５３（例えばゲート電極）は、ＴｉＮ、ＷＮ、Ｎｉ、ＴａＮ、Ｎｉ、Ａｕ、Ａｌ、Ｒｕ、Ｗ、及びＴａＳｉＮよりなる群から選択された少なくとも１つを含む。第１～第３導電部材６１～６３の少なくともいずれかは、Ａｌ、Ｃｕ及びＴｉよりなる群から選択された少なくとも１つを含む。 In this embodiment, at least one of the first electrode 51 and the second electrode 52 includes at least one selected from the group consisting of, for example, Ti, Al, Cu, and Au. For example, the third electrode 53 (e.g., a gate electrode) includes at least one selected from the group consisting of TiN, WN, Ni, TaN, Ni, Au, Al, Ru, W, and TaSiN. At least one of the first to third conductive members 61 to 63 includes at least one selected from the group consisting of Al, Cu, and Ti.

実施形態において、Ｓｉ及び窒素の組成比（例えば濃度）は、例えば、ＲＢＳ（Rutherford Backscattering Spectrometry）などにより得られる。 In an embodiment, the composition ratio (e.g., concentration) of Si and nitrogen is obtained, for example, by Rutherford Backscattering Spectrometry (RBS).

第１～第３実施形態において、第２電極５２の第２電極端部５２ｅは、第３半導体部分２３（第２半導体領域２０）、及び、絶縁部材４０（例えば第２窒化物領域４２）と接する。第２電極端部５２ｅは、第２電極５２と第２半導体領域２０とが互いに接する部分の、第３電極５３側の端部に対応する。 In the first to third embodiments, the second electrode end 52e of the second electrode 52 contacts the third semiconductor portion 23 (second semiconductor region 20) and the insulating member 40 (e.g., the second nitride region 42). The second electrode end 52e corresponds to the end of the contact portion between the second electrode 52 and the second semiconductor region 20 on the third electrode 53 side.

（第４実施形態）
図１２は、第４実施形態に係る半導体装置を例示する模式的断面図である。
図１２に示すように、実施形態に係る半導体装置１４０も、第１～第３電極５１～５３、第１半導体領域１０、第２半導体領域２０、第１導電部材６１、及び、絶縁部材４０を含む。半導体装置１４０において、絶縁部材４０は、第３窒化物領域４３を含む。半導体装置１４０におけるこれ以外の構成には、第１実施形態に関して説明した構成を適用できる。 (Fourth embodiment)
FIG. 12 is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.
12, the semiconductor device 140 according to the embodiment also includes first to third electrodes 51 to 53, a first semiconductor region 10, a second semiconductor region 20, a first conductive member 61, and an insulating member 40. In the semiconductor device 140, the insulating member 40 includes a third nitride region 43. The configuration described in relation to the first embodiment can be applied to other configurations of the semiconductor device 140.

第２窒化物領域４２の少なくとも一部は、第１方向（Ｘ軸方向）において、第１窒化物領域４１の少なくとも一部と第３窒化物領域４３の少なくとも一部との間にある。この例では、第２窒化物領域４２は、第１方向（Ｘ軸方向）において、第１窒化物領域４１と第３窒化物領域４３との間にある。 At least a portion of the second nitride region 42 is located between at least a portion of the first nitride region 41 and at least a portion of the third nitride region 43 in the first direction (X-axis direction). In this example, the second nitride region 42 is located between the first nitride region 41 and the third nitride region 43 in the first direction (X-axis direction).

第３窒化物領域４３は、シリコン及び窒素を含む。第３窒化物領域４３における窒素の濃度に対するシリコンの濃度の第３比（Ｓｉ／Ｎ）は、第２比よりも高い。第３窒化物領域４３は、第２窒化物領域４２よりもさらにシリコンリッチの領域である。
このようなシリコン濃度が高い第３窒化物領域４３が第２電極５２（例えばドレイン電極）の近くに設けられる。これにより、第２電極５２の近傍において、空乏化がより抑制される。例えば、電流コラプスがより効果的に抑制される。 The third nitride region 43 contains silicon and nitrogen. A third ratio of the silicon concentration to the nitrogen concentration (Si/N) in the third nitride region 43 is higher than the second ratio. The third nitride region 43 is a region that is even more silicon-rich than the second nitride region 42.
Such a third nitride region 43 having a high silicon concentration is provided near the second electrode 52 (e.g., the drain electrode), which further suppresses depletion in the vicinity of the second electrode 52. For example, current collapse is more effectively suppressed.

第３比は、０．９６よりも高くても良い。第３比は、第２比よりも高い任意の値が適用されて良い。 The third ratio may be greater than 0.96. The third ratio may be any value greater than the second ratio.

第２窒化物領域４２の第２方向（Ｚ軸方向）に沿う厚さを厚さｔ３とする。１つの例において、厚さｔ３は、例えば、０．５ｎｍ以上３００ｎｍ以下である。例えば、所望のしきい値電圧が得やすくなる。例えば、高いゲート信頼性が得やすくなる。厚さｔ３は、厚さｔ１及び厚さｔ２と実質的に同じでも良い。 The thickness of the second nitride region 42 along the second direction (Z-axis direction) is defined as thickness t3. In one example, thickness t3 is, for example, 0.5 nm or more and 300 nm or less. For example, it becomes easier to obtain a desired threshold voltage. For example, it becomes easier to obtain high gate reliability. Thickness t3 may be substantially the same as thickness t1 and thickness t2.

第２窒化物領域４２の少なくとも一部が第３窒化物領域４３の一部と重なっても良い。例えば、Ｚ軸方向において、第２窒化物領域４２の一部が、第２半導体領域２０と、第３窒化物領域４３の一部と、の間にあっても良い。例えば、Ｚ軸方向において、第３窒化物領域４３の一部が、第２半導体領域２０と、第２窒化物領域４２の一部と、の間にあっても良い。 At least a portion of the second nitride region 42 may overlap a portion of the third nitride region 43. For example, in the Z-axis direction, a portion of the second nitride region 42 may be between the second semiconductor region 20 and a portion of the third nitride region 43. For example, in the Z-axis direction, a portion of the third nitride region 43 may be between the second semiconductor region 20 and a portion of the second nitride region 42.

半導体装置１４０の例において、第２電極５２の第２電極端部５２ｅは、第３半導体部分２３（第２半導体領域２０）、及び、絶縁部材４０（例えば第３窒化物領域４３）と接する。 In the example semiconductor device 140, the second electrode end 52e of the second electrode 52 contacts the third semiconductor portion 23 (second semiconductor region 20) and the insulating member 40 (e.g., the third nitride region 43).

図１３は、第４実施形態に係る半導体装置を例示する模式的断面図である。
図１３に示すように、実施形態に係る半導体装置１４１は、第３導電部材６３を含む。半導体装置１４１におけるこれ以外の構成は、半導体装置１４０と同様で良い。 FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment.
13, a semiconductor device 141 according to the embodiment includes a third conductive member 63. Other configurations of the semiconductor device 141 may be similar to those of the semiconductor device 140.

第３導電部材６３は、第２電極５２と電気的に接続される。または、第３導電部材６３は、第２電極５２と電気的に接続されることが可能である。第２電極５２の第２方向（Ｚ軸方向）における位置は、第１半導体領域１０の第２方向における位置と第３導電部材６３の第２方向における位置との間にある。第３窒化物領域４３の少なくとも一部は、第２方向において、第３導電部材６３と重なる。例えば、電流コラプスがより効果的に抑制される。 The third conductive member 63 is electrically connected to the second electrode 52. Alternatively, the third conductive member 63 can be electrically connected to the second electrode 52. The position of the second electrode 52 in the second direction (Z-axis direction) is between the position of the first semiconductor region 10 in the second direction and the position of the third conductive member 63 in the second direction. At least a portion of the third nitride region 43 overlaps with the third conductive member 63 in the second direction. For example, current collapse is more effectively suppressed.

実施形態によれば、特性を安定にできる半導体装置を提供することができる。 According to the embodiment, a semiconductor device with stable characteristics can be provided.

本願明細書において、「電気的に接続される状態」は、複数の導電体が物理的に接してこれら複数の導電体の間に電流が流れる状態を含む。「電気的に接続される状態」は、複数の導電体の間に、別の導電体が挿入されて、これらの複数の導電体の間に電流が流れる状態を含む。 In this specification, "electrically connected" includes a state in which multiple conductors are physically connected and current flows between them. "Electrically connected" also includes a state in which another conductor is inserted between multiple conductors and current flows between them.

本願明細書において、「垂直」及び「平行」は、厳密な垂直及び厳密な平行だけではなく、例えば製造工程におけるばらつきなどを含むものであり、実質的に垂直及び実質的に平行であれば良い。 In this specification, "perpendicular" and "parallel" do not only mean strictly perpendicular and strictly parallel, but also include variations in the manufacturing process, etc., and are sufficient as long as they are substantially perpendicular and substantially parallel.

以上、具体例を参照しつつ、本発明の実施の形態について説明した。しかし、本発明は、これらの具体例に限定されるものではない。例えば、半導体装置に含まれる電極、半導体領域、導電部材、絶縁部材及び基体などの各要素の具体的な構成に関しては、当業者が公知の範囲から適宜選択することにより本発明を同様に実施し、同様の効果を得ることができる限り、本発明の範囲に包含される。 Embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the semiconductor device, such as the electrodes, semiconductor regions, conductive members, insulating members, and base, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from within the known range.

また、各具体例のいずれか２つ以上の要素を技術的に可能な範囲で組み合わせたものも、本発明の要旨を包含する限り本発明の範囲に含まれる。 Furthermore, any combination of two or more elements of each specific example, to the extent technically possible, is also included within the scope of the present invention, as long as it encompasses the gist of the present invention.

その他、本発明の実施の形態として上述した半導体装置を基にして、当業者が適宜設計変更して実施し得る全ての半導体装置も、本発明の要旨を包含する限り、本発明の範囲に属する。 In addition, all semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

その他、本発明の思想の範疇において、当業者であれば、各種の変更例及び修正例に想到し得るものであり、それら変更例及び修正例についても本発明の範囲に属するものと了解される。 In addition, within the scope of the concept of this invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of this invention.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in a variety of other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims.

１０…第１半導体領域、１０Ｃ…キャリア領域、１０ａ～１０ｆ…第１～第６部分領域、１０ｓ…基体、１１Ｂ…窒化物層、２０…第２半導体領域、２１～２４…第１～第４半導体部分、３０…第３半導体領域、４０…絶縁部材、４０ｐ…一部、４１～４３…第１～第３窒化物領域、４１ｅ…第１窒化物端部、４５…第１絶縁膜、４５ａ～４５ｅ…第１～第５絶縁領域、５１～５３…第１～第３電極、５２ｅ…第２電極端部、５３ａ…一部、６１～６３…第１～第３導電部材、６１ｅ～６３ｅ…第１～第３導電端部、６１Ｇ、６１Ｓ、６２Ｇ、６３Ｄ…接続部材、１１０、１１０ａ～１１０ｃ、１１１～１１３、１２０、１３０、１３１、１４０、１４１…半導体装置、ＣＣ１…抵抗増加率、Ｌ１、Ｌ２…第１、第２距離、ＲＬ…比、ｔ１～ｔ３…厚さ 10...First semiconductor region, 10C...Carrier region, 10a-10f...First to sixth partial regions, 10s...Base, 11B...Nitride layer, 20...Second semiconductor region, 21-24...First to fourth semiconductor portions, 30...Third semiconductor region, 40...Insulating member, 40p...Part, 41-43...First to third nitride regions, 41e...First nitride end, 45...First insulating film, 45a-45e...First to fifth insulating regions, 51-53...First to third electrodes, 52e...Second electrode end, 53a...Part, 61-63...First to third conductive members, 61e-63e...First to third conductive end, 61G, 61S, 62G, 63D...Connecting member, 110, 110a-110c, 111-113, 120, 130, 131, 140, 141...semiconductor device; CC1...resistance increase rate; L1, L2...first and second distances; RL...ratio; t1-t3...thickness

Claims

A first electrode;
a second electrode, the direction from the first electrode to the second electrode being along a first direction;
a third electrode, the position of the third electrode in the first direction being between the position of the first electrode in the first direction and the position of the second electrode in the first direction;
a first semiconductor region including Al _x1 Ga _1-x1 N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, a direction from the first partial region to the first electrode, a direction from the second partial region to the second electrode, and a direction from the third partial region to the third electrode are along a second direction intersecting with the first direction, the fourth partial region is between the first partial region and the third partial region in the first direction, the fifth partial region is between the third partial region and the second partial region in the first direction, and the sixth partial region is between the fifth partial region and the second partial region in the first direction;
a second semiconductor region including Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2), the second semiconductor region including a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and the direction from the fourth sub-region to the first semiconductor portion is along the second direction;
a first conductive member electrically connected to a first one of the first electrode and the third electrode, the first conductive member including a first conductive end in the first direction, the position of the first conductive end in the first direction being between the position of the third electrode in the first direction and the position of the second electrode in the first direction;
an insulating member, the insulating member including a first nitride region and a second nitride region, the second semiconductor portion being between the fifth sub-region and the first nitride region in the second direction, the third semiconductor portion being between the sixth sub-region and the second nitride region in the second direction, the first nitride region including silicon and nitrogen, the second nitride region including silicon and nitrogen, a first ratio of a silicon concentration to a nitrogen concentration in the first nitride region being lower than a second ratio of a silicon concentration to a nitrogen concentration in the second nitride region, the first nitride region including a first nitride end, the first nitride end being in contact with the second semiconductor region and facing the second nitride region in the first direction, and a position of the first nitride end in the first direction being between the position of the first conductive end in the first direction and the position of the second electrode in the first direction;
Equipped with
At least a portion of the first nitride region is between the second semiconductor portion and a portion of the second nitride region in the second direction .

The semiconductor device of claim 1, wherein the first ratio is less than 0.75.

The semiconductor device of claim 2, wherein the second ratio is greater than or equal to 0.75 and less than or equal to 0.96.

The semiconductor device of claim 3, wherein the second ratio is 0.78 or greater.

The semiconductor device described in any one of claims 1 to 4, wherein at least a portion of the second nitride region is in contact with the third semiconductor portion.

6. The semiconductor device according to claim 1, wherein a portion of said first nitride region is between said third partial region and said third electrode.

a portion of the first nitride region is between the third partial region and the third electrode;
6. The semiconductor device according to claim 1 , wherein said third electrode is located between said part of said first nitride region and said part of said second nitride region in said second direction.

A first electrode;
a second electrode, the direction from the first electrode to the second electrode being along a first direction;
a third electrode, the position of the third electrode in the first direction being between the position of the first electrode in the first direction and the position of the second electrode in the first direction;
a first semiconductor region including Al _x1 Ga _1-x1 N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, a direction from the first partial region to the first electrode, a direction from the second partial region to the second electrode, and a direction from the third partial region to the third electrode are along a second direction intersecting with the first direction, the fourth partial region is between the first partial region and the third partial region in the first direction, the fifth partial region is between the third partial region and the second partial region in the first direction, and the sixth partial region is between the fifth partial region and the second partial region in the first direction;
a second semiconductor region including Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2), the second semiconductor region including a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and the direction from the fourth sub-region to the first semiconductor portion is along the second direction;
a first conductive member electrically connected to a first one of the first electrode and the third electrode, the first conductive member including a first conductive end in the first direction, the position of the first conductive end in the first direction being between the position of the third electrode in the first direction and the position of the second electrode in the first direction;
an insulating member, the insulating member including a first nitride region and a second nitride region, the second semiconductor portion being between the fifth sub-region and the first nitride region in the second direction, the third semiconductor portion being between the sixth sub-region and the second nitride region in the second direction, the first nitride region including silicon and nitrogen, the second nitride region including silicon and nitrogen, a first ratio of a silicon concentration to a nitrogen concentration in the first nitride region being lower than a second ratio of a silicon concentration to a nitrogen concentration in the second nitride region, the first nitride region including a first nitride end, the first nitride end being in contact with the second semiconductor region and facing the second nitride region in the first direction, and a position of the first nitride end in the first direction being between the position of the first conductive end in the first direction and the position of the second electrode in the first direction;
Equipped with
the insulating member includes a first insulating film including a first insulating region;
the first insulating region is provided between the third partial region and the third electrode,
the first insulating film contains silicon and oxygen;
The semiconductor device, wherein the first insulating film does not contain nitrogen, or the concentration of nitrogen in the first insulating film is lower than the concentration of nitrogen in the second nitride region.

A first electrode;
a second electrode, the direction from the first electrode to the second electrode being along a first direction;
a third electrode, the position of the third electrode in the first direction being between the position of the first electrode in the first direction and the position of the second electrode in the first direction;
a first semiconductor region including Al _x1 Ga _1-x1 N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, a direction from the first partial region to the first electrode, a direction from the second partial region to the second electrode, and a direction from the third partial region to the third electrode are along a second direction intersecting with the first direction, the fourth partial region is between the first partial region and the third partial region in the first direction, the fifth partial region is between the third partial region and the second partial region in the first direction, and the sixth partial region is between the fifth partial region and the second partial region in the first direction;
a second semiconductor region including Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2), the second semiconductor region including a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and the direction from the fourth sub-region to the first semiconductor portion is along the second direction;
a first conductive member electrically connected to a first one of the first electrode and the third electrode, the first conductive member including a first conductive end in the first direction, the position of the first conductive end in the first direction being between the position of the third electrode in the first direction and the position of the second electrode in the first direction;
an insulating member, the insulating member including a first nitride region and a second nitride region, the second semiconductor portion being between the fifth sub-region and the first nitride region in the second direction, the third semiconductor portion being between the sixth sub-region and the second nitride region in the second direction, the first nitride region including silicon and nitrogen, the second nitride region including silicon and nitrogen, a first ratio of a silicon concentration to a nitrogen concentration in the first nitride region being lower than a second ratio of a silicon concentration to a nitrogen concentration in the second nitride region, the first nitride region including a first nitride end, the first nitride end being in contact with the second semiconductor region and facing the second nitride region in the first direction, and a position of the first nitride end in the first direction being between the position of the first conductive end in the first direction and the position of the second electrode in the first direction;
Equipped with
at least a portion of the third electrode is located between the first semiconductor portion and the second semiconductor portion in the first direction;
the insulating member includes a first insulating film including a first insulating region;
the first insulating film further includes a second insulating region and a third insulating region;
the second insulating region is located between the first semiconductor portion and the third electrode in the first direction;
The semiconductor device, wherein the third insulating region is between the third electrode and the second semiconductor portion in the first direction.

the first insulating film further includes a fourth insulating region and a fifth insulating region;
the first semiconductor portion is located between the fourth portion region and the fourth insulating region in the second direction;
The semiconductor device according to claim 9 , wherein the second semiconductor portion is located between the fifth portion region and the fifth insulating region in the second direction.

The semiconductor device of claim 10 , wherein the first nitride region is between the second semiconductor portion and a portion of the fifth insulating region.

A first electrode;
a second electrode, the direction from the first electrode to the second electrode being along a first direction;
a third electrode, the position of the third electrode in the first direction being between the position of the first electrode in the first direction and the position of the second electrode in the first direction;
a first semiconductor region including Al _x1 Ga _1-x1 N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, a direction from the first partial region to the first electrode, a direction from the second partial region to the second electrode, and a direction from the third partial region to the third electrode are along a second direction intersecting with the first direction, the fourth partial region is between the first partial region and the third partial region in the first direction, the fifth partial region is between the third partial region and the second partial region in the first direction, and the sixth partial region is between the fifth partial region and the second partial region in the first direction;
a second semiconductor region including Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2), the second semiconductor region including a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and the direction from the fourth sub-region to the first semiconductor portion is along the second direction;
a first conductive member electrically connected to a first one of the first electrode and the third electrode, the first conductive member including a first conductive end in the first direction, the position of the first conductive end in the first direction being between the position of the third electrode in the first direction and the position of the second electrode in the first direction;
an insulating member, the insulating member including a first nitride region and a second nitride region, the second semiconductor portion being between the fifth sub-region and the first nitride region in the second direction, the third semiconductor portion being between the sixth sub-region and the second nitride region in the second direction, the first nitride region including silicon and nitrogen, the second nitride region including silicon and nitrogen, a first ratio of a silicon concentration to a nitrogen concentration in the first nitride region being lower than a second ratio of a silicon concentration to a nitrogen concentration in the second nitride region, the first nitride region including a first nitride end, the first nitride end being in contact with the second semiconductor region and facing the second nitride region in the first direction, and a position of the first nitride end in the first direction being between the position of the first conductive end in the first direction and the position of the second electrode in the first direction;
A second conductive member ;
Equipped with
the second conductive member is electrically connected to a second one of the first electrode and the third electrode;
the second conductive member includes a second conductive end portion in the first direction,
a position of the second conductive end in the first direction between the position of the third electrode in the first direction and the position of the first conductive end in the first direction ;

The semiconductor device according to claim 12 , wherein the position of the second conductive member in the second direction is between the position of the third electrode in the second direction and the position of the first conductive member in the second direction.

A first electrode;
a second electrode, the direction from the first electrode to the second electrode being along a first direction;
a third electrode, the position of the third electrode in the first direction being between the position of the first electrode in the first direction and the position of the second electrode in the first direction;
a first semiconductor region including Al _x1 Ga _1-x1 N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region, a direction from the first partial region to the first electrode, a direction from the second partial region to the second electrode, and a direction from the third partial region to the third electrode are along a second direction intersecting with the first direction, the fourth partial region is between the first partial region and the third partial region in the first direction, the fifth partial region is between the third partial region and the second partial region in the first direction, and the sixth partial region is between the fifth partial region and the second partial region in the first direction;
a second semiconductor region including Al _x2 Ga _1-x2 N (0<x2≦1, x1<x2), the second semiconductor region including a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and the direction from the fourth sub-region to the first semiconductor portion is along the second direction;
a first conductive member electrically connected to a first one of the first electrode and the third electrode, the first conductive member including a first conductive end in the first direction, the position of the first conductive end in the first direction being between the position of the third electrode in the first direction and the position of the second electrode in the first direction;
an insulating member, the insulating member including a first nitride region and a second nitride region, the second semiconductor portion being between the fifth sub-region and the first nitride region in the second direction, the third semiconductor portion being between the sixth sub-region and the second nitride region in the second direction, the first nitride region including silicon and nitrogen, the second nitride region including silicon and nitrogen, a first ratio of a silicon concentration to a nitrogen concentration in the first nitride region being lower than a second ratio of a silicon concentration to a nitrogen concentration in the second nitride region, the first nitride region including a first nitride end, the first nitride end being in contact with the second semiconductor region and facing the second nitride region in the first direction, and a position of the first nitride end in the first direction being between the position of the first conductive end in the first direction and the position of the second electrode in the first direction;
a third conductive member ;
Equipped with
the third conductive member is electrically connected to the second electrode;
the third conductive member includes a third conductive end portion in the first direction,
A semiconductor device, wherein the position of the first nitride end in the first direction is between the position of the first conductive end in the first direction and the position of the third conductive end in the first direction.

the second electrode includes a second electrode end;
the second electrode end portion is in contact with the third semiconductor portion and the insulating member,
A semiconductor device according to any one of claims 1 to 14, wherein a first distance along the first direction between the position of the first conductive end in the first direction and the position of the first nitride end in the first direction is 0.43 times or more of a second distance along the first direction between the position of the first conductive end in the first direction and the position of the second electrode end in the first direction.

a thickness of the first nitride region along the second direction is 0.5 nm or more and 300 nm or less;
16. The semiconductor device according to claim 1, wherein the thickness of said second nitride region along said second direction is not less than 0.5 nm and not more than 300 nm.

the insulating member further comprises a third nitride region;
at least a portion of the second nitride region is between at least a portion of the first nitride region and at least a portion of the third nitride region in the first direction;
the third nitride region comprises silicon and nitrogen;
a third ratio of the concentration of silicon to the concentration of nitrogen in the third nitride region is greater than the second ratio ;
Further comprising a third conductive member;
the third conductive member is electrically connected to the second electrode;
a position of the second electrode in the second direction is between a position of the first semiconductor region in the second direction and a position of the third conductive member in the second direction;
5. The semiconductor device according to claim 1 , wherein at least a portion of said third nitride region overlaps with said third conductive member in said second direction .

The semiconductor device of claim 17 , wherein the third ratio is greater than 0.96.