JP7729065B2 - Transimpedance Amplifier Circuit - Google Patents

Description

This disclosure relates to a transimpedance amplifier circuit.

In optical transmission systems, wavelength division multiplexing is known, in which two optical fibers are used to transmit and receive an optical signal multiplexed with multiple optical signals of different wavelengths. Coherent reception is also known as a method for efficiently receiving multiplexed optical signals. For example, in an optical receiving device that receives one of multiple optical signals (a single optical signal), the amplifier circuit that amplifies the current signal converted from the single optical signal includes a transimpedance amplifier and an AGC (Auto Gain Control) circuit that variably controls the gain of the transimpedance amplifier and keeps the amplitude of the amplified signal constant. This type of amplifier circuit is capable of outputting a linear output signal with a wide input dynamic range thanks to the variable gain function of the AGC circuit.

International Publication No. 2015/004828 JP 2015-220567 A JP 2015-084474 A Japanese Patent Application Laid-Open No. 2011-217226

For example, when a setting signal that sets the amplitude of the output signal from the amplifier circuit is supplied to the AGC circuit, the loop gain and AGC band of the AGC circuit may fluctuate depending on the set amplitude. Here, the AGC band is calculated as the frequency when the gain of the loop gain characteristic of the AGC loop is "1" (0 dB in decibels).

The present disclosure therefore aims to provide a transimpedance amplifier circuit that suppresses fluctuations in the AGC band due to amplitude settings.

The transimpedance amplifier circuit of the present disclosure includes an amplifier circuit that amplifies an input current signal in accordance with a first gain set by a control signal and converts it into a voltage signal, and a gain control circuit that generates the control signal in accordance with the amplitude of the voltage signal, wherein the gain control circuit includes a detection circuit that generates an amplitude detection signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude reference signal in accordance with a reference voltage, a differential amplifier circuit that generates a differential voltage by adding an offset voltage generated in accordance with an output amplitude setting signal to a differential amplified signal generated by amplifying the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal, and a gain control circuit that amplifies the differential voltage in accordance with a second gain set by the output amplitude setting signal. the gain control circuit generates the control signal in accordance with the charging voltage of the capacitance element; the offset voltage increases as the output amplitude setting signal increases; the amplitude of the voltage signal is set to decrease as the output amplitude setting signal decreases and to increase as the output amplitude setting signal increases; the differential current signal decreases as the differential voltage increases and to increase as the differential voltage decreases; and the second gain is set to decrease as the output amplitude setting signal increases and to increase as the output amplitude setting signal decreases .

This disclosure provides a transimpedance amplifier circuit that suppresses fluctuations in the AGC band due to amplitude settings.

FIG. 1 is a block diagram showing an example of the configuration of a transimpedance amplifier circuit according to the first embodiment. FIG. 2 is a circuit diagram showing an example of the AGC control circuit of FIG. FIG. 3 is a circuit diagram showing an example of the OTA of FIG. FIG. 4 is an explanatory diagram showing an example of a gain control voltage that is set in accordance with an amplitude setting signal. FIG. 5 is a characteristic diagram showing an example of an output current output from the output terminal of the OTA in response to a set gain control voltage. FIG. 6 is a circuit diagram showing an example of the gain control section of FIG. FIG. 7 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. FIG. 8 is a characteristic diagram showing the characteristics shown in FIG. 7 as an AGC band relative to the output amplitude. FIG. 9 is a circuit diagram showing another example of the configuration of the AGC control circuit mounted on the transimpedance amplifier circuit of FIG. FIG. 10 is a characteristic diagram showing an example of the AGC loop gain according to the amplitude setting by the output amplitude setting signal in the AGC control circuit of FIG. FIG. 11 is a characteristic diagram showing the characteristics shown in FIG. 10 as an AGC band with respect to the output amplitude. FIG. 12 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit and the amplitude detection signal when the feedback function of the AGC control circuit of FIG. 2 or FIG. 9 is disabled.

Description of the embodiments of the present disclosure
First, embodiments of the present disclosure will be listed and described.

[1] A transimpedance amplifier circuit according to one aspect of the present disclosure comprises: an amplifier circuit that amplifies an input current signal in accordance with a first gain set by a control signal and converts it into a voltage signal; and a gain control circuit that generates the control signal in accordance with the amplitude of the voltage signal. The gain control circuit comprises: a detection circuit that generates an amplitude detection signal in accordance with the amplitude of the voltage signal; a setting circuit that generates an amplitude reference signal in accordance with a reference voltage; a differential voltage generation circuit that corrects the difference between the voltage of the amplitude detection signal and the voltage of the amplitude reference signal in accordance with an output amplitude setting signal to generate a differential signal; a voltage-controlled current source circuit that amplifies the voltage difference of the differential signals in accordance with a second gain set by the output amplitude setting signal to generate a differential current signal; and a capacitive element that is charged and discharged by the differential current signal. The gain control circuit generates the control signal in accordance with the charging voltage of the capacitive element.

This transimpedance amplifier circuit can maintain a constant AGC band regardless of the amplitude of the set voltage signal. In other words, it is possible to provide a transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude settings.

[2] In the above [1], the gain control circuit may further include a gain control section that generates a gain control voltage for setting the second gain in response to the output amplitude setting signal, and the voltage-controlled current source circuit may include a pair of transistors that amplify the differential signal, and a variable resistor section connected between the drains of the pair of transistors, the variable resistor section having a resistance value that varies in response to the gain control voltage. By changing the resistance value of the variable resistor section connected between the drains of the pair of transistors using the gain control voltage, the gain of the voltage-controlled current source circuit can be changed in response to the gain control voltage using a simple method, and fluctuations in the AGC band due to amplitude setting can be compensated for.

[3] In the above [2], the gain control unit comprises a voltage output node that outputs the gain control voltage, a resistive element connected to the voltage output node, multiple current sources connected in parallel, a thermocode generation unit that generates an output signal according to the value of the output amplitude setting signal, and a switch that changes the number of the multiple current sources connected to the voltage output node according to the output signal, wherein the gain control voltage is generated when currents supplied by the multiple current sources connected to the voltage output node via the switch flow through the resistive element, and the output signal may increase or decrease the number of the multiple current sources connected to the voltage output node by one when the value of the output amplitude setting signal increases or decreases by one. This makes it possible to generate a gain control voltage according to the output amplitude setting signal using simple means.

[4] In any of [1] to [3] above, the differential voltage generation circuit may include a current generation unit that generates an offset current corresponding to the value indicated by the output amplitude setting signal, and a differential amplifier circuit that differentially amplifies the amplitude detection signal and the amplitude reference signal and adds a voltage corresponding to the offset current to the voltage obtained by amplifying the amplitude detection signal. This allows the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal to be reflected in the output of the differential amplifier circuit, and the amplitude of the voltage signal can be set to the amplitude indicated by the output amplitude setting signal.

[Details of the embodiment of the present disclosure]
Specific examples of transimpedance amplifier circuits according to the present disclosure will be described below with reference to the accompanying drawings. In the following description, identical or corresponding elements will be designated by the same reference numerals, and descriptions of these elements may be omitted. Furthermore, the reference numerals for input terminals, output terminals, and nodes will also be used to indicate signals, voltages, or currents.

First Embodiment
[Circuit configuration of transimpedance amplifier circuit]
Fig. 1 is a block diagram showing an example of the configuration of a transimpedance amplifier circuit according to Embodiment 1. The transimpedance amplifier circuit 100 shown in Fig. 1 includes a TIA (Transimpedance Amplifier) 10, a VGA (Variable Gain Amplifier) 20, a BUF (Buffer) 30, a CML (Current Mode Logic) 40, and an AGC control circuit 50.

For example, the transimpedance amplifier circuit 100 is used in a coherent receiver that receives optical signals, and receives at its input terminals InP and InN a differential current signal converted from a single-wavelength optical signal by a photodiode. The transimpedance amplifier circuit 100 amplifies the received current signal and outputs it from the output terminals OutP and OutN as a differential voltage signal. The voltage signals output from the output terminals OutP and OutN are then output to a signal processing circuit such as a DSP (Digital Signal Processor).

TIA10 converts the differential input current signal received at input terminals InP and InN into a voltage signal and outputs it to VGA20. For example, the gain of TIA10 varies in response to the control signal CNTL1 received from the AGC control circuit 50. Note that because the current signal is converted into a voltage signal, the gain of TIA10 is expressed in impedance units such as 1000 Ω. TIA10 includes, for example, an INV (INVERTING amplifier) 11 and resistor elements R11 and R12. INV11 is an example of an inverting amplifier circuit. For example, INV11 is an inverting amplifier circuit that amplifies a differential signal.

INV11, for example, inverts and amplifies a differential voltage signal input between the non-inverting input terminal and the inverting input terminal, and outputs the inverted and amplified differential voltage signal from the inverting output terminal and the non-inverting output terminal. Resistance element R11 is connected, for example, between the non-inverting input terminal and the inverting output terminal of INV11. Resistance element R12 is connected, for example, between the inverting input terminal and the non-inverting output terminal of INV11. The gain of TIA10 varies in response to the control signal CNTL1. Note that TIA10 may, for example, use variable resistance elements for resistance elements R11 and R12, and vary the gain of TIA10 by changing the resistance values of resistance elements R11 and R12 in response to the control signal CNTL1.

VGA20 amplifies the differential voltage signal received from TIA10 and outputs it to BUF30. For example, the gain of VGA20 varies in response to control signals CNTL2, CNTL3, and CNTL4 received from AGC control circuit 50. VGA20 performs non-inverting amplification, for example, but may also perform inverting amplification to invert the logic of the differential voltage signal it outputs. The differential voltage signal is composed of a positive-phase signal (positive-phase component) and a negative-phase signal (negative-phase component). The positive-phase signal and negative-phase signal are 180 degrees out of phase with each other, forming a pair of complementary signals.

For example, when the voltage of the positive-phase signal increases, the voltage of the negative-phase signal decreases; when the voltage of the positive-phase signal decreases, the voltage of the negative-phase signal increases. Furthermore, when the positive-phase signal reaches its peak value, the negative-phase signal reaches its bottom value; and when the positive-phase signal reaches its bottom value, the negative-phase signal reaches its peak value. It is preferable that the positive-phase signal and the negative-phase signal have the same amplitude and the same average value (DC component). By swapping the pair of positive-phase and negative-phase signals, the logic of the differential voltage signal can be inverted. Therefore, in a circuit that amplifies a differential voltage signal, switching between non-inverting amplification and inverting amplification can be easily performed by reconnecting the positive-phase signal wiring and the negative-phase signal wiring. The VGA 20 can also be included within the TIA 10 to amplify the differential voltage signal output from the TIA 10.

BUF30 amplifies the differential voltage signals received from VGA20 and outputs the resulting voltage signals IP and IN to AGC control circuit 50 and CML40. CML40 amplifies the voltage signals IP and IN and outputs the amplified voltage signals to output terminals OutP and OutN. The voltage signals IP and IN and the voltage signals output to output terminals OutP and OutN are all differential voltage signals (hereinafter referred to as differential voltage signals). For example, voltage signal IP is the positive-phase signal of the differential voltage signal, and voltage signal IN is the negative-phase signal of the differential voltage signal. Note that, for example, if the voltage gain and driving capability of VGA20 are sufficiently large, BUF30 may be omitted and VGA20 may supply the differential voltage signals IP and IN.

The AGC control circuit 50 generates control signals CNTL1-CNTL4 that adjust the gain of the TIA 10 and VGA 20 to set the amplitude of the differential voltage signal output from the output terminals OutP and OutN to the amplitude indicated by the output amplitude setting signal OA. The gain of the TIA 10 and VGA 20, set by the control signals CNTL1-CNTL4, is an example of a first gain. The AGC control circuit 50 is an example of a gain control circuit. An example of the AGC control circuit 50 is shown in Figure 2. The AGC control circuit 50 detects the amplitude of the differential voltage signals IP and IN. For example, if the CML 40 performs linear amplification with a constant gain, the amplitude of the differential voltage signals output from the output terminals OutP and OutN changes linearly with the amplitude of the differential voltage signals IP and IN. Therefore, by controlling the amplitude of the differential voltage signals IP and IN, the output amplitude of the differential voltage signals output from the output terminals OutP and OutN can be set to a predetermined value.

[Circuit configuration of AGC control circuit]
2 is a circuit diagram showing an example of the AGC control circuit 50 of FIG. 1. The AGC control circuit 50 includes bipolar transistors Q1P and Q1N that receive differential voltage signals IP and IN output from the BUF 30 of FIG. 1. For example, the bipolar transistor Q1P receives a positive-phase signal IP of the differential voltage signals IP and IN, and the bipolar transistor Q1N receives a negative-phase signal IN of the differential voltage signals IP and IN. The AGC control circuit 50 also includes a current source I51 and a resistor R51 connected to the emitters of the bipolar transistors Q1P and Q1N, and a capacitor C51 connected to the resistor R51. The bipolar transistors Q1P and Q1N have the same electrical characteristics, for example, within the range of allowable manufacturing variations.

Hereinafter, bipolar transistors will also be referred to simply as transistors. Transistors Q1P and Q1N, current source I51, resistor R51, and capacitor C51 function as a detection circuit that detects the amplitude of differential voltage signals IP and IN. An amplitude detection signal PH, set to a voltage corresponding to the amplitude detected by the detection circuit, is output to the gate of p-channel MOS transistor M1P of the differential amplifier circuit. Resistor R51 and capacitor C51 form a low-pass filter, and the amplitude detection signal is averaged and output from the connection node between resistor R51 and capacitor C51. For example, when the amplitude of differential voltage signals IP and IN is constant, amplitude detection signal PH is a DC signal having a voltage value corresponding to the magnitude of the amplitude. Hereinafter, p-channel MOS transistors will also be referred to simply as transistors.

The AGC control circuit 50 also includes a bipolar transistor Q2 that receives a reference voltage Vref, a current source I52 and a resistor R52 connected to the emitter of transistor Q2, and a capacitor C52 connected to resistor R52. Transistor Q2, current source I52, resistor R52, and capacitor C52 have a circuit configuration similar to that of the detection circuit that detects the amplitude of voltage signals IP and IN, and, for example, the electrical characteristics and size of each circuit element are similar to those of the detection circuit within the allowable range of manufacturing variations.

For example, the reference voltage Vref is set to the center voltage of the amplitudes of the differential voltage signals IP and IN. The center voltage of the amplitudes of the differential voltage signals IP and IN is equal to the temporal average value (DC component) of each voltage signal. Note that the reference voltage Vref may be set to the average value obtained by dividing the voltage signals IP and IN output from BUF30 in Figure 1 and applying them to a resistor string. For example, the voltage signal IP may be applied to one end of a series resistor circuit consisting of two resistor elements, and the voltage signal IN may be applied to the other end of the series resistor circuit, and the voltage at the midpoint where the two resistor elements are connected may be used as the reference voltage Vref.

Transistor Q2, current source I52, resistor R52, and capacitor C52 function as a setting circuit that converts the level of reference voltage Vref and generates the converted voltage as an amplitude reference signal. The amplitude reference signal AH is output to the gate of p-channel MOS transistor M1N of the differential amplifier circuit. Resistor R52 and capacitor C52 form a low-pass filter, and the level-converted reference voltage Vref is stabilized and output from the connection node between resistor R52 and capacitor C52. For example, amplitude reference signal AH is a DC signal having a voltage value corresponding to reference voltage Vref. In this way, the amplitude detection signal and amplitude reference signal are each output as DC signals to the differential amplifier circuit. For example, transistors Q1P, Q1N, and Q2 are heterojunction bipolar transistors.

The differential amplifier circuit includes, for example, transistors M1P and M1N, a current source I53 connected to the sources of transistors M1P and M1N, and resistor elements R53, R54, R55, and R56. Resistor elements R53 and R54 are connected in series between the drain of transistor M1P and the ground line GND. Resistor elements R55 and R56 are connected in series between the drain of transistor M1N and the ground line GND. For example, the resistance values of resistor elements R53 and R55 are the same within an allowable range of manufacturing variations, and the resistance values of resistor elements R54 and R56 are the same within an allowable range of manufacturing variations. Transistors M1P and M1N have the same electrical characteristics, for example, within an allowable range of manufacturing variations.

The connection node between resistor elements R53 and R54 receives an offset current Ioffset from DAC (Digital-to-Analog Converter) 52. As a result, an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of resistor element R54 is added to the drain voltage of transistor M1P, which is referenced to the ground potential.

DAC 52 generates an offset current Ioffset corresponding to the digital value indicated by the output amplitude setting signal OA. For example, as the digital value of the output amplitude setting signal OA increases, the current value of the offset current Ioffset increases. The output amplitude setting signal OA is provided, for example, from outside the transimpedance amplifier circuit 100. As described above, in the transimpedance amplifier circuit 100 according to the first embodiment, the output amplitude set by the output amplitude setting signal OA is the output amplitude of the differential voltage signal output from the output terminals OutP and OutN, but the amplitude detected by the detection circuit is the amplitude of the differential voltage signals IP and IN. Therefore, the amplitude of the differential voltage signals IP and IN is set by the offset current Ioffset so that the output amplitude of the differential voltage signal output from the output terminals OutP and OutN is a predetermined value. DAC 52 is an example of a current generator that generates an offset current Ioffset according to the digital value indicated by the output amplitude setting signal OA.

For example, the digital value of the output amplitude setting signal OA is set to a small value when the set amplitude is small, and is set to a large value when the set amplitude is large. The output amplitude setting signal OA is also output to the gain control unit 53.

For example, when the set amplitude is relatively small, DAC 52 receives an output amplitude setting signal OA with a relatively small value and outputs a relatively small offset current Ioffset. When the set amplitude is relatively large, DAC 52 receives an output amplitude setting signal OA with a relatively large value and outputs a relatively large offset current Ioffset. DAC 52 is, for example, a current DAC (IDAC) that outputs a current.

The output amplitude setting signal OA is also output to the gain control unit 53. The gain control unit 53 generates a gain control voltage VG according to the digital value of the output amplitude setting signal OA. For example, when the value of the output amplitude setting signal OA is relatively small (when the set amplitude is small), the gain control unit 53 outputs a relatively low gain control voltage VG. When the value of the output amplitude setting signal OA is relatively large (when the set amplitude is large), the gain control unit 53 outputs a relatively high gain control voltage VG. The gain of the OTA 51, which is controlled by the gain control voltage VG, is an example of a second gain. The OTA 51 will be described later.

The differential amplifier circuit outputs differential voltage signals VIP and VIN, which are generated in response to the voltages of the amplitude detection signal PH, the amplitude reference signal AH, and the offset current Ioffset, from the drains of transistors M1N and M1P. The differential amplifier circuit and DAC52 are an example of a differential voltage generation circuit that generates a differential signal by correcting the difference between the voltage of the amplitude detection signal PH and the voltage of the amplitude reference signal in response to the output amplitude setting signal OA. The correction in response to the output amplitude setting signal OA is performed, for example, as described above, by adding an offset voltage corresponding to the product of the offset current Ioffset and the resistance value of resistor R54 to one of the voltages of the generated differential signal.

The differential voltage signals VIP and VIN are supplied to the differential inputs of OTA (Operational Transconductance Amplifier) 51. By supplying the differentially amplified voltage signals VIP and VIN to OTA 51, the signal-to-noise ratio can be improved compared to when the amplitude detection signal PH and amplitude reference signal AH are supplied directly to OTA 51, thereby improving the accuracy of the AGC function. Furthermore, by adding an offset voltage due to the offset current Ioffset described above to one of the differential voltage signals VIP and VIN, voltage signal VIN, the amplitude of the differential voltage signals IP and IN can be set to be equal to the amplitude value set in accordance with the output amplitude setting signal OA when the voltage values of voltage signals VIP and VIN become equal.

OTA51 receives gain control voltage VG from gain control unit 53 and outputs a differential current signal OUT from the output node in response to differential voltage signals VIP and VIN. OTA51 operates as a variable gain OTA in response to gain control voltage VG, controlling its gain in response to the value of output amplitude setting signal OA. Because OTA51 outputs a current signal in response to the input voltage signal, the gain of OTA51 is expressed in units of conductance, such as 100S. Adjusting the gain of OTA51 compensates for fluctuations in the AGC band that depend on the output amplitude, making it possible to keep the AGC band constant regardless of the value of output amplitude setting signal OA. A specific circuit example of OTA51 is shown in Figure 3. OTA51 is an example of a voltage-controlled current source circuit.

Capacitive element C2 is connected to the output node of OTA51. OTA51 and capacitive element C2 function as an integrating circuit, generating an output voltage OUT at the output node in response to the differential current signal output from OTA51 and the capacitance value of capacitive element C2. The time constant defined by the output impedance of OTA51 and capacitive element C2 forms the dominant pole of the gain characteristic of the AGC loop. The AGC loop in transimpedance amplifier circuit 100 is composed of TIA10, which changes its gain in response to control signal CNTL1, VGA20, which changes its gain in response to control signals CNTL2-CNTL4, BUF30, and AGC control circuit 50, which receives differential voltage signals IP and IN and generates control signals CNTL1-CNTL4.

Gain control unit 54 is connected to the output of OTA 51. Gain control unit 54 generates control signals CNTL1-CNTL4 that control the gain of TIA 10 and VGA 20 according to output voltage OUT, which is the charging voltage of capacitive element C2 connected to the output node of OTA 51.

For example, when the output voltage OUT is relatively low, the gain control unit 54 generates control signals CNTL1-CNTL4 that increase the gain of the TIA 10 and VGA 20. When the output voltage OUT is relatively high, the gain control unit 54 generates control signals CNTL1-CNTL4 that decrease the gain of the TIA 10 and VGA 20.

When the amplitude detection signal PH and amplitude reference signal AH are constant, a smaller offset current Ioffset reduces the voltage value of the voltage signal VIN, and a larger offset current Ioffset increases the voltage value of the voltage signal VIN. The transimpedance amplifier circuit 100 operates by the negative feedback of the AGC loop described above so that the difference between the voltage signals VIN and VIP input to the OTA 51 becomes "0," thereby canceling out the offset voltage due to the offset current Ioffset. As a result, an AGC control circuit 50 can be configured that allows amplitude setting using the digital value of the output amplitude setting signal OA.

[OTA circuit example]
Fig. 3 is a circuit diagram showing an example of the OTA 51 of Fig. 2. The OTA 51 has, for example, p-channel MOS transistors PM1, PM2, PM3, PM4, and PM5, n-channel MOS transistors NM1, NM2, NM3, and NM4, and current sources I11 and I12.

The gates of transistors PM1 and PM2 receive differential voltage signals VIN and VIP from the differential amplifier circuit of FIG. 2. A current source I11 is connected to the source of transistor PM1, and a current source I12 is connected to the source of transistor PM2. The source of transistor PM1 is connected to the source of transistor PM5. The source of transistor PM2 is connected to the drain of transistor PM5. The gate of transistor PM5 receives a gain control voltage VG. Since transistor PM5 functions as a variable resistance element as described below, the source and drain of transistor PM5 may be interchanged. That is, the source of transistor PM1 may be connected to the drain of transistor PM5, and the source of transistor PM2 may be connected to the source of transistor PM5.

The drain of transistor PM1 is connected to the common gate of the current mirror circuit formed by transistors NM1 and NM3. The drain of transistor PM2 is connected to the common gate of the current mirror circuit formed by transistors NM2 and NM4. Furthermore, the drain of transistor NM3 is connected to the common gate of the current mirror circuit formed by transistors PM3 and PM4. The drains of transistors PM4 and NM4 are connected to the output terminal OUT of OTA 51.

The gate of transistor PM1 receives, for example, one of the differential voltage signals VIP and VIN (negative phase signal), VIN. The gate of transistor PM2 receives, for example, the other of the differential voltage signals VIN and VIP (positive phase signal), VIP. Transistors PM1 and PM2 generate differential output current signals in response to the differential voltage signals VIP and VIN. For example, the drain current of transistor PM1 flows through transistor NM1, and the drain current of transistor PM2 flows through transistor NM2. The difference current between the drain current of transistor NM1 and the drain current of transistor NM2 changes in response to the differential voltage between voltage signals VIP and VIN.

One of the differential output current signals flowing through transistor NM1 is supplied to the output terminal OUT via a two-stage current mirror circuit formed by transistors NM1, NM3, PM3, and PM4. The other of the differential output current signals flowing through transistor NM2 is supplied to the output terminal OUT via a current mirror circuit formed by transistors NM2 and NM4. One of the differential current signals is supplied to the output terminal OUT to push current outward, and the other of the differential current signals is supplied to pull current from the outside to the output terminal OUT. In this way, the difference current obtained by subtracting the other differential current signal from one of the differential current signals is output from the output terminal OUT as a differential current signal. Transistors PM4 and NM4 form a push-pull circuit.

Transistor PM5 functions as a variable resistor whose source-drain resistance changes in response to the gain control voltage VG. This allows the gain (gm) of OTA 51 to be controlled by the gain control voltage VG.

Figure 4 is an explanatory diagram showing an example of a gain control voltage VG set in response to the output amplitude setting signal OA. The numerical values at the end of the symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in Figure 4 correspond to the amplitude setting value; the larger the numerical value, the larger the output amplitude setting signal OA supplied to the DAC 52 and the gain control unit 53. The horizontal axis in Figure 4 represents the output amplitude of the differential output voltage output from the output terminals OutP and OutN. In this example, the gain control voltage VG is set so that it increases as the output amplitude increases. When the voltage value of the gain control voltage VG is relatively small, the on-resistance of the p-channel MOS transistor PM5 decreases, and the gain of the OTA 51 increases. When the voltage value of the gain control voltage VG is relatively large, the on-resistance of the p-channel MOS transistor PM5 increases, and the gain of the OTA 51 decreases. An example of the gain control unit 53 that sets the gain control voltage VG is shown in Figure 6.

Figure 5 is a characteristics diagram showing an example of the output current differential current signal Iout output from the output terminal OUT of the OTA 51 in response to the differential input voltage VIP-VIN for a set gain control voltage VG. Figure 5 shows the input/output characteristics of the OTA 51 for four gain control voltages VG indicated by symbols VG1 to VG4. The horizontal axis of Figure 5 represents the differential input voltage VIP-VIN, and the vertical axis represents the differential current signal Iout. The current value of the differential current signal Iout is positive when flowing from the output terminal OUT to the outside, and negative when flowing from the outside to the output terminal OUT. The dashed lines representing the four gain control voltages VG1 to VG4 correspond to the dashed lines attached to symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 in Figure 7, described below.

For example, gain control voltage VG1 is generated when an output amplitude setting signal OA that sets the smallest output amplitude is received. Gain control voltage VG2 is generated when an output amplitude setting signal OA that sets the second smallest output amplitude is received. Gain control voltage VG3 is generated when an output amplitude setting signal OA that sets the second largest output amplitude is received. Gain control voltage VG4 is generated when an output amplitude setting signal OA that sets the largest output amplitude is received.

The gain control voltages VG1, VG2, VG3, and VG4 increase in this order (VG1<VG2<VG3<VG4). In Figure 5, the slope of each dashed line corresponding to the gain control voltages VG1 to VG4 corresponds to the gain of the OTA 51. Therefore, the higher the gain control voltage VG, the smaller the gain of the OTA 51, and the lower the gain control voltage VG, the larger the gain. In other words, the smaller the output amplitude set by the output amplitude setting signal OA, the larger the gain of the OTA 51 can be, and the larger the output amplitude set by the output amplitude setting signal OA, the larger the gain of the OTA 51 can be.

Figure 6 is a circuit diagram showing an example of the gain control unit 53 of Figure 2. The gain control unit 53 includes a thermocode generation unit 531, n current sources I1 to In connected in parallel (n is an integer greater than or equal to 2), n switches SW connecting the current sources I1 to In to a gain control voltage line (voltage output node) VG, and a resistor element RL connected between the gain control voltage line VG and the ground line GND. For example, current source I1 is connected to the gain control voltage line VG via the first switch SW, and current source In is connected to the gain control voltage line VG via the nth switch SW. When all switches SW are turned on, the n current sources I1 to In are connected in parallel to the gain control voltage line VG, and each of the n current sources I1 to In supplies a current to the resistor element RL. The gain control voltage is generated when a current supplied by one of the n current sources I1 to In connected to the voltage output node via the switch SW flows through the resistor element. The gain control voltage VG is output from the voltage output node.

The thermocode generation unit 531 generates n output signals that each control the on/off state (on/off) of a switch SW according to the value of the output amplitude setting signal OA. For example, the first output signal controls the on/off state of the first switch SW, the second output signal controls the on/off state of the second switch SW, and the nth output signal controls the on/off state of the nth switch SW. When a switch SW is turned off, the switch SW is in a non-conductive state (off state). When a switch SW is turned on, the switch SW is in a conductive state (on state). For example, as described in Figures 4 and 5, assume that there are four values for the output amplitude setting signal OA to set four amplitudes. In this case, the thermocode generation unit 531 generates output signals that increase the number of switches SW that are turned on as the value of the output amplitude setting signal OA increases.

For example, when the output amplitude setting signal OA is set to a value that sets the smallest amplitude, only the first output signal is set to turn on the switch SW, and the other output signals are set to turn off the switches SW connected to them. When the output amplitude setting signal OA is set to a value that sets the second smallest amplitude, only the first and second output signals are set to turn on the switches SW connected to them, and the other output signals are set to turn off the switches SW connected to them. In this way, for example, when the value of the output amplitude setting signal OA increases by 1 or to the next largest value, only one switch SW changes from the off state to the on state.

For example, a thermocode can generate 2 ^m output signals according to m values (m is an integer equal to or greater than 1) of the output amplitude setting signal OA. For example, with a thermocode, the number of switches SW turned on increases by one as the digital value A of the output amplitude setting signal OA increases by one. Therefore, when the digital value A increases or decreases by one, only one switch SW is turned on/off accordingly, and the current value flowing through the resistor element RL can be monotonically increased or decreased without being affected by the timing of the output signal X. For example, when two switches SW are controlled simultaneously without using a thermocode, specifically when one switch SW is changed from an off state to an on state and the other switch SW is changed from an on state to an off state, the timing of the respective output signals X may differ, potentially jeopardizing the monotonic change of the gain control voltage VG generated by the resistor element RL. By adjusting the gain of the OTA 51 according to the output amplitude setting signal OA, the AGC band can be kept constant regardless of the value of the output amplitude setting signal OA.

In addition, when n amplitude settings are used, if the gain control voltages VG that provide the desired AGC band are V1 to Vn, I1 to In can be found as follows.
I1=V1/RL
I2=V2/RL-I1
...
In=Vn/RL-Σ(k=1, n-1)Ik
Here, the symbol Σ indicates the current Ik when k is changed from "1" to "n-1", and the symbol Σ indicates that the current Ik is integrated.

[Loop Gain of the First Embodiment]
7 is a characteristic diagram showing an example of the loop gain of the AGC loop in the AGC control circuit 50 of FIG. 2 according to the amplitude setting by the output amplitude setting signal OA. FIG. 7 shows the characteristics of the AGC loop gain when the optical input signal power is kept constant (for example, −15 dBm). When the optical input signal power is kept constant, the magnitude of the differential input current signal received at the input terminals InP and InN is constant. The numerical values at the end of the symbols OA_GC30, OA_GC120, OA_GC210, and OA_GC300 shown in FIG. 7 correspond to the value of the output amplitude setting signal OA, as described in FIG. 4.

As described above, the AGC band can be determined as the frequency at which the gain is "1" (0 dB in decibels) in the loop gain characteristics of the AGC loop. For example, the appropriate range of the AGC band is 100 kHz to 1 MHz. In this embodiment, by changing the gain of the OTA 51 according to the amplitude setting, the AGC band can be set to approximately 300 kHz regardless of the amplitude setting. 300 kHz is located near the center of the appropriate range of the AGC band, ensuring the desired communication performance even when the optical input signal power fluctuates.

Figure 8 is a characteristic diagram showing the characteristics shown in Figure 7 as the AGC band versus output amplitude. As shown in Figure 8, the AGC band can be stabilized to a nearly constant value regardless of the output amplitude set by the output amplitude setting signal OA.

As described above, in this embodiment, by changing the gain of the OTA 51 according to the amplitude setting, the AGC band can be stabilized at a constant level regardless of the set output amplitude. In other words, it is possible to provide a transimpedance amplifier circuit 100 that suppresses fluctuations in the AGC band due to amplitude settings. As a result, sufficient communication performance can be ensured even when the desired output amplitude is set in response to fluctuations in the optical input signal power, and the reliability of the transimpedance amplifier circuit 100 can be improved.

Transistor PM5, whose source-drain resistance changes in response to gain control voltage VG, is connected between the sources of transistors PM1 and PM2, which receive differential voltage signals VIP and VIN. This allows the gain of the voltage-controlled current source circuit to be changed in response to gain control voltage VG using simple means, compensating for fluctuations in the AGC band that depend on the output amplitude.

By using a thermocode to set the number of current sources I1-In connected to the gain control voltage line VG according to the value of the output amplitude setting signal OA, a stable gain control voltage VG can be generated using a simple method, without being affected by the timing of the output signal that switches the current sources I1-In on and off.

By supplying an offset current Ioffset to the connection node of the resistor elements R53 and R54 of the differential amplifier circuit in accordance with the output amplitude setting signal OA, the offset voltage corresponding to the amplitude indicated by the output amplitude setting signal OA can be reflected in the output of the differential amplifier circuit. As a result, the amplitude of the differential voltage signals IP and IN can be set to the output amplitude indicated by the output amplitude setting signal OA.

[Other circuit configurations of AGC control circuits]
Fig. 9 is a circuit diagram showing another example of the configuration of an AGC control circuit mounted on the transimpedance amplifier circuit 100 of Fig. 1. Elements similar to those in Fig. 2 are given the same reference numerals, and detailed description thereof will be omitted. An AGC control circuit 50A shown in Fig. 9 is mounted on the transimpedance amplifier circuit 100 shown in Fig. 1 in place of the AGC control circuit 50 of Fig. 1.

The AGC control circuit 50A has the gain control unit 53 removed from the AGC control circuit 50 in FIG. 2. The OTA 51 has the transistor PM5 removed from the OTA 51 shown in FIG. 3. The rest of the configuration of the AGC control circuit 50A is the same as the configuration of the AGC control circuit 50 in FIG. 2. The AGC control circuit 50A operates in the same way as the AGC control circuit 50 in FIG. 2, except that it does not adjust the gain of the OTA 51 using the output amplitude setting signal OA.

[Loop gain of other AGC control circuits]
Fig. 10 is a characteristic diagram showing an example of the AGC loop gain in response to the amplitude setting by the output amplitude setting signal OA in the AGC control circuit 50A of Fig. 9. Fig. 10 corresponds to Fig. 7 and shows the AGC loop gain characteristics when the optical input signal power is kept constant (for example, -15 dBm). When the optical input signal power is kept constant, the magnitude of the differential input current signal received at the input terminals InP and InN is constant.

If the capacitance value is not adjusted using the output amplitude setting signal OA, the AGC band fluctuates according to the set amplitude. In Figure 10, the AGC band fluctuates from approximately 180 kHz to approximately 1 MHz, with a small margin relative to the appropriate range of 100 kHz to 1 MHz. For this reason, if the optical input signal power fluctuates, it may not be possible to ensure the desired communication performance.

Figure 11 is a characteristic diagram showing the characteristics shown in Figure 10 as the AGC band versus output amplitude. In Figure 11, the AGC band fluctuates depending on the amplitude set by the output amplitude setting signal OA.

[Characteristics when feedback function is disabled]
12 is a characteristic diagram showing the relationship between the output amplitude of the transimpedance amplifier circuit 100 and the differential voltage PH-AH between the amplitude detection signal PH and the amplitude reference signal AH when negative feedback by the AGC control circuit of FIG. 2 or 9 is disabled. As shown in FIG. 12, when negative feedback is disabled, the differential voltage PH-AH increases nonlinearly, in a bow-like manner, as the set amplitude increases. When the setting circuit of the AGC control circuit 50 sets the reference voltage Vref to the average value of the differential voltage signals IP and IN, the differential voltage PH-AH becomes a voltage corresponding to the amplitude of the differential voltage signals IP and IN (half the peak-to-peak value).

The change in AGC band shown in Figure 11 occurs because the gain of the AGC loop fluctuates depending on the amplitude setting, and is due to two main reasons. First, because TIA 10 and VGA 20 are included in the AGC loop, fluctuations in the gain of TIA 10 and VGA 20 due to AGC control cause the AGC loop gain to fluctuate. Second, transistors Q1P and Q1N (e.g., HBTs) in Figures 2 and 9 have diode characteristics between their bases and emitters, and therefore have nonlinear characteristics with respect to the input. For example, the nonlinear relationship between the differential voltage PH-AH and the actual output amplitude in Figure 12 is due to the nonlinear characteristics of transistors Q1P and Q1N.

The above describes embodiments of the present disclosure, but the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. Naturally, these also fall within the technical scope of the present disclosure.

10 TIA
20 VGA
30 BUF
40 CML
50, 50A AGC control circuit 51 OTA
52 DAC
53, 54 Gain control section 100 Transimpedance amplifier circuit 531 Thermocode generation section AH Amplitude reference signal C2 Capacitor element C51, C52 Capacitor elements CNTL1-CNTL4 Control signal I1, In Current source I11, I12 Current source I51, I52, I53 Current source InN, InP Input terminal IN, IP Voltage signal M1N, M1P Transistor MP1, PM2, PM3, PM4, PM5 Transistor NM1, NM2, NM3, NM4 Transistor OA Output amplitude setting signal OUT Output terminal OutN, OutP Output terminal PH Amplitude detection signal Q1N, Q1P Transistor Q2 Transistor R11, R12 Resistor element R51, R52, R53, R54, R55, R56 Resistor elements SW Switch VG Gain control voltage VIP, VIN Voltage signal Vref Reference voltage

Claims (4)

an amplifier circuit that amplifies an input current signal in accordance with a first gain set by a control signal and converts the input current signal into a voltage signal;
a gain control circuit that generates the control signal in response to the amplitude of the voltage signal;
Equipped with
The gain control circuit
a detection circuit for generating an amplitude detection signal in accordance with the amplitude of the voltage signal;
a setting circuit for generating an amplitude reference signal in response to a reference voltage;
a differential amplifier circuit that generates a differential voltage by adding an offset voltage generated in accordance with an output amplitude setting signal to a differential amplified signal that is generated by amplifying a difference between a voltage of the amplitude detection signal and a voltage of the amplitude reference signal;
a voltage controlled current source circuit that amplifies the differential voltage in accordance with a second gain set by the output amplitude setting signal to generate a differential current signal;
a capacitance element that is charged and discharged by the differential current signal;
Equipped with
the gain control circuit generates the control signal in response to a charging voltage of the capacitance element;
the offset voltage increases as the output amplitude setting signal increases,
the amplitude of the voltage signal is set to be smaller when the output amplitude setting signal is smaller, and is set to be larger when the output amplitude setting signal is larger;
the differential current signal decreases as the differential voltage increases and increases as the differential voltage decreases;
the second gain is set to be smaller as the output amplitude setting signal increases, and to be larger as the output amplitude setting signal decreases.
Transimpedance amplifier circuit. The gain control circuit
a gain control section that generates a gain control voltage for setting the second gain in response to the output amplitude setting signal;
The voltage controlled current source circuit comprises:
a pair of transistors for amplifying the differential voltage ;
a variable resistor section connected between the sources of the pair of transistors, the resistance value of which varies in response to the gain control voltage;
2. The transimpedance amplifier circuit of claim 1, comprising: The gain control unit
a voltage output node that outputs the gain control voltage;
a first resistor element connected to the voltage output node;
n current sources (n is an integer of 2 or more) ;
a thermocode generating unit that generates an output signal in accordance with the value of the output amplitude setting signal;
n switches for changing the number of current sources connected to the voltage output node among the n current sources in response to the output signal;
Equipped with
the gain control voltage is generated by a current supplied from one of the n current sources connected to the voltage output node via the n switches in response to the output signal flowing through the first resistor element;
the output signal increases the number of the n current sources connected to the voltage output node by one when the value of the output amplitude setting signal increases by one , and decreases the number of the n current sources connected to the voltage output node by one when the value of the output amplitude setting signal decreases by one.
3. The transimpedance amplifier circuit according to claim 2. the gain control circuit further includes a current generating unit that generates an offset current according to a value indicated by the output amplitude setting signal;
the differential amplifier circuit includes a second resistor element for generating the differential voltage;
the offset voltage is generated by the offset current flowing through the second resistor element.
The transimpedance amplifier circuit according to any one of claims 1 to 3.