JP7729362B2 - Multilayer ceramic capacitors - Google Patents

Description

This invention relates to a multilayer ceramic capacitor.

In recent years, there has been a demand for small, high-capacity multilayer ceramic capacitors. Such multilayer ceramic capacitors have a rectangular parallelepiped-shaped laminate, in which, for example, inner dielectric layers on which the internal electrodes are printed and the internal electrodes are alternately laminated, with outer ceramic layers laminated on the top and bottom surfaces of the laminate. External electrodes are also formed on both end surfaces of the laminate. Some such multilayer ceramic capacitors have dielectric layers called side margins formed on the side surfaces of the laminate to prevent the internal electrodes from connecting to the external electrodes on the side surfaces of the laminate.

Patent Document 1 discloses a method for manufacturing a multilayer ceramic capacitor having the side margins described above. In the method for manufacturing a multilayer ceramic capacitor described in Patent Document 1, ceramic green sheets are first stacked, each having a conductive film formed on its surface that will become the internal electrodes. Next, a mother laminate is formed, and the mother laminate is cut so that the conductive film is exposed on the sides where no external electrodes are formed. This results in a laminate chip. Then, ceramic slurry that will become the side margins is applied to the internal electrodes exposed on both sides of the cut laminate chip. This makes it possible to form internal electrodes across the entire width of the laminate chip, thereby improving the efficiency of capacitance acquisition and reducing capacitance variation.

Japanese Unexamined Patent Publication No. 61-248413

However, with the multilayer ceramic capacitor of Patent Document 1, for example, if the thickness of the side margins, i.e., the dimension along the width direction of the laminate, is reduced in order to achieve a larger capacitance with a smaller multilayer ceramic capacitor size, the side margins do not have sufficient strength. As a result, the multilayer ceramic capacitor of Patent Document 1 has the problem of not being able to achieve sufficient flexural strength. Furthermore, cracks and chips are likely to occur in the side margins, allowing moisture to penetrate through these cracks and chips. This poses the problem of a decrease in the insulation properties of the multilayer ceramic capacitor of Patent Document 1.

The primary objective of this invention is to provide a multilayer ceramic capacitor with improved reliability by improving the strength of the side margins even when the width of the side margins is small.

A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising a laminate including dielectric layers and internal electrodes stacked in a stacking direction, and external electrodes connected to the internal electrodes, wherein the laminate is formed in a shape including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction intersecting the stacking direction, and a first end face and a second end face opposing each other in a length direction intersecting the stacking direction and the width direction, and the laminate comprises an inner layer portion formed by stacking the dielectric layers and the internal electrodes in the stacking direction, outer layer portions arranged to sandwich the inner layer portion in the stacking direction, and side ceramic layers arranged to sandwich the inner layer portion and the outer layer portion in the width direction. the internal electrodes include a first internal electrode exposed at the first end face and a second internal electrode exposed at the second end face; the external electrodes include a first external electrode provided on the first end face and connected to the first internal electrode, and a second external electrode provided on the second end face and connected to the second internal electrode; the side ceramic layers include an inner layer located on the inner layer portion side and outer layers located on the first side surface side and the second side surface side; the Si content of the outer layer is higher than the Si content of the inner layer; the ratio of moles of Si to moles of Ti of the outer layer is 3.0 or more and 7.0 or less; and the ratio of moles of Si to moles of Ti of the inner layer is 1.0 or more and 4.0 or less .
In addition, in the multilayer ceramic capacitor according to the present invention, it is preferable that the exposed surfaces of the first internal electrode and the second internal electrode on the first side surface and the second side surface of the laminate contain more Si than the central portions of the first internal electrode and the second internal electrode.
Furthermore, in the multilayer ceramic capacitor according to the present invention, the ratio of the number of moles of Si to the number of moles of Ti in the side ceramic layers is preferably 1.0 or more and 7.0 or less.
Furthermore, the dimension of the side ceramic layer along the width direction is preferably 5 μm or more and 40 μm or less.
A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising a laminate including dielectric layers and internal electrodes stacked in a stacking direction, and external electrodes connected to the internal electrodes, wherein the laminate is formed in a shape including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction intersecting the stacking direction, and a first end face and a second end face opposing each other in a length direction intersecting the stacking direction and the width direction, and the laminate comprises an inner layer portion formed by stacking the dielectric layers and the internal electrodes in the stacking direction, and outer layer portions arranged to sandwich the inner layer portion in the stacking direction. and side ceramic layers including voids arranged to sandwich the inner layer portion and the outer layer portion in the width direction, the internal electrodes including a first internal electrode exposed at the first end face and a second internal electrode exposed at the second end face, the external electrodes including a first external electrode formed on the first end face and connected to the first internal electrode, and a second external electrode formed on the second end face and connected to the second internal electrode, the side ceramic layers having an inner layer located on the inner layer portion side and outer layers located on the first side face side and the second side face side, the voids in the outer layers being smaller than the voids in the inner layers.

The multilayer ceramic capacitor according to the present invention comprises an inner layer portion formed by stacking dielectric layers and internal electrodes in the stacking direction, outer layer portions arranged to sandwich the inner layer portion in the stacking direction, and side ceramic layers arranged to sandwich the inner layer portion and outer layer portion in the width direction. The internal electrodes include a first internal electrode exposed at the first end face and a second internal electrode exposed at the second end face. The external electrodes include a first external electrode provided on the first end face and connected to the first internal electrode, and a second external electrode provided on the second end face and connected to the second internal electrode. The side ceramic layers include an inner layer located on the inner layer portion side and outer layers located on the first side face and the second side face. Since the Si content of the outer layer is higher than that of the inner layer, the strength of the side margin portion can be improved, thereby improving the flexural strength of the multilayer ceramic capacitor. Furthermore, cracks and chips are less likely to occur in the side margin portion, preventing moisture intrusion and ensuring the insulation of the multilayer ceramic capacitor. As a result, a multilayer ceramic capacitor with improved reliability can be provided.

This invention makes it possible to improve the strength of the side margins even when the width dimension of the side margins is small, thereby providing a multilayer ceramic capacitor with improved reliability.

The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the invention, which proceeds with reference to the drawings.

1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment; 2 is a cross-sectional view taken along line AA in FIG. 1 showing the multilayer ceramic capacitor according to the embodiment. 2 is a cross-sectional view taken along the line BB in FIG. 1 showing the multilayer ceramic capacitor according to the embodiment. 4 is an enlarged view of a portion C in FIG. 3 showing the multilayer ceramic capacitor according to the embodiment. 10 is a diagram showing an image of a Si segregation portion of a side margin portion of the multilayer ceramic capacitor according to the embodiment, taken by WDX. 1 is a diagram showing an image of a Mg segregation portion near the surface of a side margin portion of a multilayer ceramic capacitor according to an embodiment, taken by WDS. 1 is a diagram showing an image of a Ni segregation portion near the surface of a side margin portion of a multilayer ceramic capacitor according to an embodiment, taken by WDS. 1 is a diagram showing an image of a Si segregation portion near the surface of a side margin portion of a multilayer ceramic capacitor according to an embodiment, taken by WDS. 1A and 1B are diagrams for explaining a method for manufacturing a multilayer ceramic capacitor according to the present invention, in which FIG. 1A is a schematic diagram showing ceramic green sheets on which conductive films are formed, and FIG. 1B is a schematic diagram showing how the ceramic green sheets on which conductive films are formed are stacked. 1 is a perspective view showing an example of the appearance of a laminate chip obtained by a method for manufacturing a multilayer ceramic capacitor according to the present invention. FIG. 10 is a diagram showing the relationship between the pore area ratio near the surface of the side margin portion and the Vickers hardness of the surface of the side margin portion.

1. Multilayer Ceramic Capacitor One embodiment of the multilayer ceramic capacitor according to the present invention will be described with reference to Figures 1 to 4. Figure 1 is an external perspective view showing the multilayer ceramic capacitor according to the embodiment. Figure 2 is a cross-sectional view taken along line A-A in Figure 1 showing the multilayer ceramic capacitor according to the embodiment. Figure 3 is a cross-sectional view taken along line B-B in Figure 1 showing the multilayer ceramic capacitor according to the embodiment. Figure 4 is an enlarged view of part C in Figure 3 showing the multilayer ceramic capacitor according to the embodiment.

As shown in FIG. 1, the multilayer ceramic capacitor 10 of this embodiment is generally composed of a laminate 12 and first and second external electrodes 40, 42 formed on both end surfaces of the laminate 12, respectively.

The size of the multilayer ceramic capacitor 10 according to the present invention, when expressed as "length (L) direction dimension x width (W) direction dimension x stacking (T) direction dimension," is typically expected to be, for example, "1.6 mm x 0.8 mm x 0.8 mm," "1.0 mm x 0.5 mm x 0.5 mm," "0.6 mm x 0.3 mm x 0.3 mm," "0.4 mm x 0.2 mm x 0.2 mm," or "0.2 mm x 0.1 mm x 0.1 mm."

As shown in FIG. 1, the laminate 12 is formed in a substantially rectangular parallelepiped shape. The laminate 12 has a first end face 13 and a second end face 14 extending along the width (W) direction and the stacking (T) direction, a first side face 15 and a second side face 16 extending along the length (L) direction and the stacking (T) direction, and a first main face 17 and a second main face 18 extending along the length (L) direction and the width (W) direction. The first end face 13 and the second end face 14 face each other, the first side face 15 and the second side face 16 face each other, and the first main face 17 and the second main face 18 face each other. The first side face 15 and the second side face 16 are perpendicular to the first end face 13 and the second end face 14, and the first main face 17 and the second main face 18 are perpendicular to the first end face 13 and the first side face 15. Furthermore, if the laminate 12 has a substantially rectangular parallelepiped shape, it is preferable that the corners and edges are rounded.

As shown in FIG. 2 , the laminate 12 has a first internal electrode 22 disposed at the interface between the inner layer ceramic layers 20, and a second internal electrode 24 disposed opposite the first internal electrode 22, sandwiching the inner layer ceramic layer 20. The inner layer portion 26 is formed by stacking multiple combinations of such inner layer ceramic layers 20, first internal electrodes 22, and second internal electrodes 24. The outer layer portion 28 and the outer layer portion 30 are provided to sandwich the inner layer portion 26 in the stacking (T) direction. The outer layer portion 28 has multiple outer layer ceramic layers 46, and the outer layer portion 30 has multiple outer layer ceramic layers 48. Side margin portions 32 and 34 are provided to sandwich the inner layer portion 26 and the outer layer portions 28 and 30 in the width (W) direction. These side margin portions 32 and 34 are composed of multiple side margin ceramic layers. In other words, the inner layer portion 26 is the region sandwiched along the stacking (T) direction between the first internal electrode 22b closest to the first main surface 17 and the second internal electrode 24b closest to the second main surface 18. Furthermore, the side margin portions 32, 34 are regions where the first internal electrode 22 and the second internal electrode 24 are not present in a cross section of the laminate 12 viewed from the stacking (T) direction.

Each of the multiple inner ceramic layers 20 is formed so as to be sandwiched between a first internal electrode 22 and a second internal electrode 24. The inner ceramic layers 20 are composed of dielectric ceramic particles with a perovskite structure, primarily composed of a perovskite-type compound containing, for example, Ba and Ti. At least one of Si, Mg, and Ba may also be added as an additive to these primary components. The additive is present between the ceramic particles. The thickness of the inner ceramic layers 20 after firing is 0.2 μm or more and 10 μm or less.

In the laminate 12, the outer ceramic layers 46, 48 constituting the upper and lower outer layer portions 28, 30 are formed from the same dielectric ceramic material as the inner ceramic layers 20. The outer ceramic layers 46, 48 may be formed from a different material than the inner ceramic layers 20. When the outer ceramic layers 46, 48 each have a multi-layer structure, it is preferable that the Si segregation portion of the outer ceramic layers 46, 48 closest to the first and second internal electrodes 22b, 24b be greater than the Si segregation portion of the other outer ceramic layers 46, 48. This improves the flexural strength of the multilayer ceramic capacitor 10 from the stacking (T) direction. The thickness of the outer layer portions 28, 30 after firing is 15 μm or more and 40 μm or less. Each of the outer ceramic layers 46, 48 may have a single-layer structure rather than a multiple-layer structure.

The first internal electrode 22 and the second internal electrode 24 face each other in the stacking (T) direction, with the inner layer ceramic layer 20 interposed between them. Electrostatic capacitance is generated by the portion where the first internal electrode 22 and the second internal electrode 24 face each other, with the inner layer ceramic layer 20 interposed between them.

The inner layer ceramic layers 20 extend in the width (W) and length (L) directions, and each of the multiple first internal electrodes 22 extends in a flat plate shape along the inner layer ceramic layers 20. Each of the multiple first internal electrodes 22 is extended to the first end surface 13 of the laminate 12 and electrically connected to the first external electrode 40. Each of the multiple second internal electrodes 24 extends in a flat plate shape so as to face the first internal electrode 22 across the inner layer ceramic layer 20. Each of the multiple second internal electrodes 24 is extended to the second end surface 14 of the laminate 12 and electrically connected to the second external electrode 42.

The thickness of each of the first and second internal electrodes 22, 24 is, for example, 0.3 μm or more and 2.0 μm or less. The first and second internal electrodes 22, 24 preferably contain Ni. In addition to Ni, they may contain metals such as Cu, Ag, Pd, Ag-Pd alloy, and Au. The first and second internal electrodes 22, 24 may contain the same dielectric particles as the inner ceramic layer 20.

As shown in FIG. 4, Si segregates in the portions of the first and second internal electrodes 22, 24 that include the surfaces closest to the side margins 32, 34. Si has segregated regions in the internal electrodes within a range of at least 0.5 μm from the side margins toward the center in the width (W) direction, forming segregation portions 22a, 24a. In other words, segregation portion 22a is formed on the side margins 32, 34 side of the first internal electrode 22, and segregation portion 24a is formed on the side margins 32, 34 side of the second internal electrode 24. These segregation portions 22a, 24a improve the flexural strength of the multilayer ceramic capacitor 10.

When the laminate 12 is viewed as a cross section in the lamination (T) direction, and the regions where the first internal electrode 22 and the second internal electrode 24 are not present are defined as the side margins 32, 34, the side margins 32, 34 have multiple side margin layers. The Si content of the other side margin layers is higher than that of the side margin layer closest to the internal electrodes 22, 24, which increases the strength of the side margins 32, 34. This improves the flexural strength of the multilayer ceramic capacitor 10. Furthermore, cracks and chips are less likely to occur in the side margins 32, 34, preventing moisture penetration. This ensures the insulation of the multilayer ceramic capacitor 10. As a result, a sufficiently reliable multilayer ceramic capacitor 10 can be obtained.

In addition, when the first internal electrode 22 and the second internal electrode 24 of the laminate 12 include segregation portions 22a and 24a on the side margin portions 32 and 34 side, and the segregation portions 22a and 24a contain Si, the flexural strength of the multilayer ceramic capacitor can be further improved. The side margin portions 32 and 34 each have a multilayer structure including outer layers 32a and 34a located on the first and second side surfaces 15 and 16 side of the laminate 12, and inner layers 32b and 34b located on the first and second internal electrodes 22 and 24 side. The fact that the side margin portions 32 and 34 have a multilayer structure can be easily confirmed by observation with an optical microscope due to the difference in sinterability between the outer layers 32a and 34a and the inner layers 32b and 34b.

The width (W) dimension of the side margin portions 32, 34 after firing is, for example, 5 μm or more and 40 μm or less. More preferably, it is 20 μm or less. Furthermore, the width (W) dimension of the outer layers 32a, 34a is larger than the width (W) dimension of the inner layers 32b, 34b. Specifically, the width (W) dimension of the outer layers 32a, 34a is 5 μm or more and 20 μm or less. The width (W) dimension of the inner layers 32b, 34b is 0.1 μm or more and 20 μm or less.

In this invention, the width (W) direction dimension of the side margins 32, 34 refers to the average dimension calculated from the measurement results of measuring the dimensions of the side margins 32, 34 at multiple locations along the stacking (T) direction. The measurement method is as follows: First, a surface including the width (W) direction and the stacking (T) direction of the multilayer ceramic capacitor 10 (hereinafter referred to as the "WT cross section") is exposed. Next, an optical microscope is used to image the WT cross section so that the width (W) direction ends of the first and second internal electrodes 22, 24 and one of the side margins 32, 34 are within the same field of view. Images are taken at three locations in the stacking (T) direction: the top, center, and bottom. Then, at the top, center, and bottom, multiple line segments parallel to the width (W) direction are drawn from the width (W) direction ends of the first and second internal electrodes 22, 24 toward the first and second side surfaces 15, 16, and the length of each line segment is measured. The average length of the line segments measured in this way is calculated for each of the top, center, and bottom portions. The thickness dimensions of the side margins 32, 34 are then obtained by further averaging these average values.

The side margin portions 32, 34 are made of a dielectric ceramic material with a perovskite structure, primarily composed of _BaTiO3 , for example. Si is added as an additive to these primary components, and portions where the additive segregates exist between ceramic particles. The presence of the segregated Si portions improves the flexural strength of the side margin portions 32, 34. Si is added to the outer layers 32a, 34a in a ratio of 3.0 to 7.0 moles of Si/Ti moles, and to the inner layers 32b, 34b in a ratio of 1.0 to 4.0 moles of Si/Ti moles. In particular, the segregated Si portions in the outer layers 32a, 34a are greater than the segregated Si portions in the inner layers 32b, 34b.

Figure 5 shows images of Si segregation in the side margins of the multilayer ceramic capacitor 10 taken with a wavelength-dispersive X-ray analyzer (hereinafter referred to as WDX). The Si segregation in the side margins 32, 34 can be confirmed by exposing a WT cross section at approximately the center of the laminate 12 in the length (L) direction and then observing it with WDX. Furthermore, it can be seen that Si segregation 22a, 24a is formed on the first and second internal electrodes 22, 24 closest to the side margins 32, 34. Segregation of not only Si but also Mg was also confirmed. Figures 6 to 8 show images of the same location (near the surface of the side margins) of the multilayer ceramic capacitor 10 taken with WDS. Figure 6 shows an image of the Mg segregation, Figure 7 shows an image of the Ni segregation, and Figure 8 shows an image of the Si segregation.

The amount of Ba, which is an additive, between the ceramic particles of the inner ceramic layer 20, the outer layers 32a and 34a, and the inner layers 32b and 34b is as follows:
Inner ceramic layer 20<outer layers 32a, 34a<inner layers 32b, 34b,
is.
Thus, the Ba content differs between the ceramic particles of the inner ceramic layer 20, the outer layers 32a, 34a, and the inner layers 32b, 34b. The difference in Ba content can be detected by TEM analysis.

The content of Ba in the outer layers 32 a, 34 a and the inner layers 32 b, 34 b of the inner layer portion 26 and the side margin portions 32, 34 is such that the molar ratio of Ba to 1 mol of Ti is, at the center value,
The outer layers 32a and 34a are greater than 1.01 and less than or equal to 1.020.
The inner layers 32b and 34b are greater than 1.020 and less than 1.040.
The inner layer portion 26 is greater than 0.99 and less than 1.01.
It is formulated so that

The above-mentioned molar ratios can be confirmed as follows. First, the outer layers 32a, 34a and inner layers 32b, 34b in the side margins 32, 34 of the laminate 12 are polished from the side margins 32, 34 side. Next, the powders of the outer layers 32a, 34a and inner layers 32b, 34b obtained by polishing are dissolved in acid. Then, ICP emission spectroscopy can be performed to confirm whether the outer layers 32a, 34a and inner layers 32b, 34b each have the above-mentioned molar ratio.

The Ba content between the ceramic particles of the inner layers 32b and 34b is increased by more than 100% and less than 140% compared to the Ba content between the ceramic particles of the outer layers 32a and 34a.

The side margins 32, 34 are also formed so that the voids decrease from the internal electrode side toward the side surfaces. That is, the voids in the outer layers 32a, 34a are smaller than the voids in the inner layers 32b, 34b. This prevents moisture from penetrating into the inside of the laminate 12 from the side margins 32, 34, thereby improving the moisture resistance of the multilayer ceramic capacitor 10. Furthermore, the insulation properties of the multilayer ceramic capacitor 10 can be ensured.

(First and second external electrodes 40, 42)
The first external electrode 40 is formed so as to cover the first end face 13 of the laminate 12, and is electrically connected to the first internal electrode 22 extended to the first end face 13 of the laminate 12. The second external electrode 42 is formed so as to cover the second end face 14 of the laminate 12, and is electrically connected to the second internal electrode 24 extended to the second end face 14 of the laminate 12.

As shown in Figures 1 and 2, the first external electrode 40 has a three-layer structure including a base electrode layer 40a, an underlayer plating 40b formed on the surface of the base electrode layer 40a, and an upper layer plating 40c formed on the surface of the underlayer plating 40b. The base electrode layer 40a is provided to cover the entire first end face 13 of the laminate 12, and is also provided to cover from the portion covering the end face 13 to portions of each of the first side face 15 and second side face 16 and each of the first main face 17 and second main face 18.

As shown in Figures 1 and 2, the second external electrode 42 has a three-layer structure including a base electrode layer 42a, an underlayer plating 42b formed on the surface of the base electrode layer 42a, and an upper layer plating 42c formed on the surface of the underlayer plating 42b. The base electrode layer 42a is provided to cover the entire second end face 14 of the laminate 12, and is provided to cover from the portion covering the end face 14 to portions of each of the first side face 15 and the second side face 16, and each of the first main face 17 and the second main face 18.

The base electrode layers 40a, 42a preferably contain Cu formed by baking. In addition to Cu, they may contain, for example, Ni, Ag, Pd, an Ag-Pd alloy, or Au. The base electrode layers 40a, 42a may also be multi-layered. The base electrode layers 40a, 42a may be formed by co-firing with the first internal electrode 22 and the second internal electrode 24, or by post-firing, in which a conductive paste is applied and baked. The base electrode layers 40a, 42a may also be formed by direct plating, or by curing a resin layer containing conductive particles and a thermosetting resin.

The lower layer plating 40b, 42b preferably contains Ni to prevent solder leaching. The upper layer plating 40c, 42c preferably contains Sn to improve mountability. The lower layer plating 40b, 42b may contain, in addition to Ni, or the upper layer plating 40c, 42c may contain, in addition to Sn, for example, Cu, Ag, Pd, an Ag-Pd alloy, or Au. A conductive resin layer for stress relief may be formed between the base electrode layer 40a and the lower layer plating 40b, and between the base electrode layer 42a and the lower layer plating 42b. The first and second external electrodes 40, 42 may also be formed by plating directly onto the laminate 12.

When directly plating the external electrodes 40, 42, and when using Ni for the first and second internal electrodes 22, 24, it is preferable to use Cu, which has good bonding properties with Ni, for the underlayer plating 40b, 42b. Furthermore, it is preferable that the upper layer plating 40c, 42c have a two-layer structure including a first upper layer plating layer formed on the surface of the underlayer plating 40b, 42b, and a second upper layer plating layer formed on the surface of the first upper layer plating. The first upper layer plating preferably contains Ni, which has the function of preventing solder leaching. The second upper layer plating preferably contains Sn or Au, which have good solder wettability.

As shown in FIG. 3 , the side margin portions 32, 34 of the multilayer ceramic capacitor 10 of this embodiment are composed of multiple layers. The side margin portion 32 has an outer layer 32a and an inner layer 32b. The inner layer 32b is disposed between the first and second internal electrodes 22, 24 and the outer layer 32a. The outer layer 32a, which is a side margin layer other than the inner layer 32b, has a higher Si content than the inner layer 32b, which is disposed closest to the first and second internal electrodes 22, 24. The side margin portion 34 has an outer layer 34a and an inner layer 34b. The inner layer 34b is disposed between the first and second internal electrodes 22, 24 and the outer layer. The outer layer 34a, which is a side margin layer other than the inner layer 34b, has a higher Si content than the inner layer 34b, which is disposed closest to the first and second internal electrodes 22, 24. This improves the strength of the side margins 32, 34, thereby improving the flexural strength of the multilayer ceramic capacitor 10. Furthermore, cracks and chips are less likely to occur in the side margins 32, 34, and moisture penetration is prevented, ensuring the insulation of the multilayer ceramic capacitor 10. As a result, a multilayer ceramic capacitor 10 with improved reliability can be provided. In addition, an interface exists between the outer layers 32a, 34a and the inner layers 32b, 34b, and this interface helps to alleviate stress applied to the multilayer ceramic capacitor 10.

In addition, the multilayer ceramic capacitor 10 of this embodiment contains more Si on the surfaces closest to the side margins 32, 34 than on the central portions of the first and second internal electrodes 22, 24. As a result, the strength of the side margins 32, 34 can be further improved.

Furthermore, in the multilayer ceramic capacitor 10 of this embodiment, the Si content in its side margin portions 32, 34, calculated as moles of Si/moles of Ti, is 1.0 or more and 7.0 or less. If the moles of Si/moles of Ti ratio is less than 1.0, the side margin portions 32, 34 will not be sintered sufficiently, resulting in increased porosity and insufficient improvement in flexural strength. On the other hand, if the moles of Si/moles of Ti ratio exceeds 7.0, excessive Si will diffuse into the internal electrodes, resulting in over-sintering and reduced reliability, such as reduced insulation resistance.

Furthermore, in the multilayer ceramic capacitor 10 of this embodiment, the dimensions of the side margins 32, 34 in the width direction of the laminate 10 are 5 μm or more and 40 μm or less. If the side margins 32, 34 exceed 40 μm, the required capacitance cannot be secured. If they are less than 5 μm, the sintering of the side margins 32, 34 does not progress sufficiently, and dense side margins 32, 34 cannot be obtained. If the side margins are not dense, moisture can easily penetrate from the outside.

2. Manufacturing Method of Multilayer Ceramic Capacitor Next, a manufacturing method of a multilayer ceramic capacitor will be described. Fig. 9 is a diagram for explaining the manufacturing method of a multilayer ceramic capacitor of this embodiment, where (a) is a schematic diagram showing ceramic green sheets on which conductive films are formed, and (b) is a schematic diagram showing how the ceramic green sheets on which conductive films are formed are stacked. Fig. 10 is a perspective view showing an example of the appearance of a laminate chip obtained by the manufacturing method of a multilayer ceramic capacitor of this embodiment.

(1) Formation of Laminated Chip First, a perovskite compound containing Ba and Ti is prepared as a dielectric ceramic material. A ceramic slurry is prepared by mixing a dielectric powder obtained from this dielectric ceramic material with additives, such as at least one of Si, Mg, and Ba, as well as an organic binder, an organic solvent, a plasticizer, and a dispersant, in predetermined proportions. The ceramic slurry is then molded into ceramic green sheets 50a and 50b on the surfaces of multiple resin films (not shown). The ceramic green sheets 50b are laminated alternately with the ceramic green sheets 50a. The ceramic green sheets 50a (50b) are molded using, for example, a die coater, a gravure coater, or a microgravure coater.

Next, as shown in Figure 9(a), the conductive paste for the internal electrodes is printed in stripes in the X direction on the surface of the ceramic green sheet 50a (50b) and dried. Hereinafter, the direction in which the conductive paste for the internal electrodes extends in stripes is referred to as the X direction. The width direction of the conductive films 52a, 52b is referred to as the Y direction. In this way, the conductive films 52a (52b) that will become the first internal electrode 22 (second internal electrode 24) are formed. Various printing methods can be used, including screen printing, inkjet printing, and gravure printing. The thickness of the conductive films 52a, 52b is, for example, 1.5 μm or less.

First, a predetermined number of ceramic green sheets without a conductive film that will become the outer layer portion 28 are stacked. Next, as shown in Figure 9(b), multiple ceramic green sheets 50a, 50b with printed conductive films 52a, 52b are shifted in the Y direction and stacked to become the inner layer portion 26. Furthermore, a predetermined number of ceramic green sheets without a conductive film that will become the outer layer portion 30 are stacked on top of the inner layer portion 26, to obtain the mother laminate.

The resulting mother laminate is then pressed. Methods for pressing the mother laminate include rigid pressing and isostatic pressing.

The pressed mother laminate is then cut into a chip shape to obtain the laminate chip 60 shown in Figure 10. Various methods can be used to cut the mother laminate, including press cutting, dicing, and laser cutting.

10, only the conductive film 52a of the ceramic green sheet 50a is exposed on one end surface of the laminate chip 60 obtained by the above steps, and only the conductive film 52b of the ceramic green sheet 50b is exposed on the other end surface.
Furthermore, the conductive film 52 a of the ceramic green sheet 50 a and the conductive film 52 b of the ceramic green sheet 50 b are exposed on both side surfaces of the laminate chip 60 .

(2) Formation of Side Margins Next, a procedure for producing ceramic green sheets for the side margins 32 and 34 will be described.

First, a perovskite-type compound containing Ba and Ti is prepared as the dielectric ceramic material. Dielectric powder obtained from this dielectric ceramic material is mixed with additives, such as at least one of Si, Mg, and Ba, as well as binder resin, organic solvent, plasticizer, and dispersant, in predetermined proportions to produce ceramic slurry.

Si is added to the ceramic slurry that will form the outer layer 32a of the side margin portion 32 (and the outer layer 34a of the side margin portion 34). Specifically, Si is added so that the moles of Si/moles of Ti is 1.0 or greater and 7.0 or less. Si is also added to the ceramic slurry that will form the inner layer 32b of the side margin portion 32 (and the outer layer 34b of the side margin portion 34). Specifically, Si is added so that the moles of Si/moles of Ti is 1.0 or greater and 4.0 or less.

Ba is also added to the ceramic slurry that will form the outer layer 32a of the side margin portion 32 (and the outer layer 34a of the side margin portion 34). Specifically, Ba is added so that the moles of Ba/moles of Ti is 0.00 or greater but less than 0.02. Ba is also added to the ceramic slurry that will form the inner layer 32b of the side margin portion 32 (and the outer layer 34b of the side margin portion 34). Specifically, Ba is added so that the moles of Ba/moles of Ti is 0.02 or greater but less than 0.04.

Furthermore, the amount of polyvinyl chloride (PVC) contained in the ceramic slurry that forms the outer layers 32a, 34a of the side margin portions 32, 34 is greater than the amount of polyvinyl chloride (PVC) contained in the ceramic slurry that forms the inner layers 32b, 34b of the side margin portions 32, 34.

Furthermore, the solvent contained in the ceramic slurry that forms the inner layers 32b, 34b of the side margin portions 32, 34 is appropriately selected to prevent dissolution of the outer layer ceramic green sheet. This inner layer ceramic green sheet also serves to adhere to the laminate chip 60.

Then, the ceramic slurry that will form the outer layers 32a and 34a is applied to the surface of the resin film and dried to obtain ceramic green sheets for the outer layers.

Next, the ceramic slurry that will become the inner layers 32b and 34b is applied to the surface of the outer layer ceramic green sheet and dried to form the inner layer ceramic green sheet. In this way, a two-layer structure ceramic green sheet for the side margin is obtained.

Here, it is preferable that the widthwise dimension of the inner layer ceramic green sheets be smaller than the widthwise dimension of the outer layer ceramic green sheets. Specifically, for example, the thickness after firing of the outer layer ceramic green sheets is formed to be 5 μm or more and 20 μm or less, and the thickness of the inner layer ceramic green sheets is formed to be 0.1 μm or more and 20 μm or less.

In the above, we have explained a case where a two-layer side margin ceramic green sheet is obtained by applying an inner layer ceramic green sheet to the surface of an outer layer ceramic green sheet and drying it. However, this is not limited to this case, and the outer layer ceramic green sheet and the inner layer ceramic green sheet may each be formed in advance, and then they may be bonded together to obtain a two-layer side margin ceramic green sheet. Note that the side margin ceramic green sheet is not limited to two layers, and may have three or more layers.

Next, the side margin ceramic green sheets are peeled off from the resin film.

Next, the inner layer ceramic green sheet of the peeled side margin ceramic green sheet is placed opposite the side of the laminate chip 60 where the conductive films 52a, 52b are exposed, and the sheets are pressed together and punched out to form a layer that will become the side margin 32. Furthermore, for the side of the laminate chip 60 where the layer that will become the side margin 32 is not formed, the inner layer ceramic green sheet is placed opposite the side of the laminate chip 60 where the conductive films 52a, 52b are exposed, and the sheets are pressed together and punched out to form a layer that will become the side margin 34. At this time, it is preferable to apply an organic solvent that will serve as an adhesive to the side of the laminate chip 60 in advance.

Next, the laminate chip 60, on which the layers that will become the side margins 32 and 34 are formed, is degreased under specified conditions in a nitrogen atmosphere, and then sintered at a specified temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to obtain the sintered laminate 12.

Next, an external electrode paste primarily composed of Cu is applied to each of the two end faces of the sintered laminate 12 and baked to form a base electrode 40a connected to the first internal electrode 22 and a base electrode 42a connected to the second internal electrode. Furthermore, Ni-plated underlayers 40b and 42b are formed on the surfaces of the base electrode layers 40a and 42a, and Sn-plated upperlayers 40c and 42c are formed on the surfaces of the underlayers 40b and 42b, thereby forming the first and second external electrodes 40 and 42.

In this manner, the multilayer ceramic capacitor 10 shown in Figure 1 is manufactured.

The side margins 32, 34 may also be formed by applying a ceramic slurry for the side margins to both sides of the laminated chip 60 where the conductive films 52a, 52b are exposed.

That is, ceramic slurry that will become the inner layers 32b and 34b is applied to both sides of the laminate chip 60 where the conductive films 52a and 52b are exposed, and then dried. Furthermore, ceramic slurry that will become the outer layers 32a and 34a is applied to the surfaces of the inner layers 32b and 34b.

In this case, the thickness of each ceramic slurry that will form the outer layers 32a, 34a and the inner layers 32b, 34b can be adjusted by changing the amount of resin contained in each ceramic slurry.

The side margins 32, 34 may also be formed by masking both end surfaces of the laminate chip 60 with resin or the like, dipping the entire laminate chip 60 into a ceramic slurry that will form the inner layers 32b, 34b, drying it, and then dipping it again into a ceramic slurry that will form the outer layers 32a, 34a. In this case, the inner and outer layers are formed on the outer layer portions 28, 30, forming a three-layer structure.

3. Experimental Examples The following describes experimental examples conducted by the inventors to confirm the effects of the present invention. In the experimental examples, samples of multilayer ceramic capacitors according to the following examples and comparative examples were manufactured, and the hardness of the surfaces of the side margins of the multilayer ceramic capacitors was measured and evaluated using a Vickers hardness tester.

(Example)
First, in the example, a sample of the multilayer ceramic capacitor shown in FIG. 1 was manufactured using the above-described method. In this example, the outer dimensions of the multilayer ceramic capacitor were 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height. In the example, a multilayer ceramic capacitor was prepared having a two-layer side margin portion consisting of an inner layer containing Si relative to Ti such that the molar ratio of Si to Ti was 3.5, and an outer layer containing Si relative to Ti such that the molar ratio of Si to Ti was 5. The thickness of the side margin portion was 20 μm. In the example, the thickness of the outer layer was 16 μm, and the thickness of the inner layer was 4 μm.

(Comparative Example)
In the comparative example, a multilayer ceramic capacitor was manufactured under the same conditions as in the example, except that a side margin portion consisting of two layers, an inner layer and an outer layer, was not provided, and instead a side margin portion with a single-layer structure was used in which Si was contained relative to Ti such that the molar number of Si/the molar number of Ti was 3.5.

(Evaluation method)
Five samples of each of the multilayer ceramic capacitors of the examples and comparative examples were prepared, and the hardness of the side margin surface on both sides of the multilayer ceramic capacitor was measured using a Vickers hardness tester. The Vickers hardness measurement conditions were a measurement load of 200 gf and a bottom dead center holding time of 10 s. The pore area ratio near the side margin surface of each sample of the multilayer ceramic capacitor of the examples and comparative examples was also calculated. This pore area ratio was determined by exposing the surface including the side margin and imaging it with an SEM. The image was then processed to measure the pore area. The pore area ratio was calculated by dividing the pore area by the area of the multilayer ceramic capacitor shown in the image.

FIG. 11 is a diagram showing the relationship between the pore area ratio in the vicinity of the surface of the side margin and the Vickers hardness of the surface of the side margin.
As a result of the experiment, as shown in FIG. 11, in the multilayer ceramic capacitor of the example, the pore area ratio near the surface of the side margin portion was 0.3%, and the Vickers hardness of the surface of the side margin portion was 1470 MPa or more and 1680 MPa or less.
On the other hand, as shown in FIG. 11, in the comparative multilayer ceramic capacitor, the pore area ratio near the surface of the side margin portion was 1.9%, and the Vickers hardness of the surface of the side margin portion was 1140 MPa or more and 1270 MPa or less.
From the above, it is clear that the multilayer ceramic capacitor of the example has improved bending strength compared to the multilayer ceramic capacitor of the comparative example.

Note that this invention is not limited to the above-described embodiment, and various modifications may be made within the scope of its essence.

REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 13 First end face 14 Second end face 15 First side face 16 Second side face 17 First main face 18 Second main face 20 Inner layer ceramic layer 22 First internal electrode 22a, 24a Segregation portion 22b First internal electrode closest to first main face 24 Second internal electrode 24b Second internal electrode closest to second main face 26 Inner layer portion 28, 30 Outer layer portion 32, 34 Side margin portion 32a, 34a Outer layer 32b, 34b Inner layer 40 First external electrode 42 Second external electrode 40a, 42a Base electrode layer 40b, 42b Underlayer plating 40c, 42c Upper layer plating 46, 48 Outer layer ceramic layer 50a, 50b Ceramic green sheet 52a, 52b: Conductive film 60: Stacked chip

Claims (4)

A multilayer ceramic capacitor comprising a laminate including dielectric layers and internal electrodes stacked in a stacking direction, and external electrodes connected to the internal electrodes,
The laminate is
the laminate is formed in a shape including a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a width direction that intersects with the stacking direction, and a first end surface and a second end surface that face each other in a length direction that intersects with the stacking direction and the width direction;
an inner layer portion formed by laminating the dielectric layers and the internal electrodes in the lamination direction; outer layer portions arranged to sandwich the inner layer portion in the lamination direction; and side ceramic layers arranged to sandwich the inner layer portion and the outer layer portion in the width direction,
the internal electrodes include a first internal electrode exposed at the first end surface and a second internal electrode exposed at the second end surface,
the external electrodes include a first external electrode provided on the first end face and connected to the first internal electrode, and a second external electrode provided on the second end face and connected to the second internal electrode,
the side ceramic layer has an inner layer located on the inner layer portion side and outer layers located on the first side surface side and the second side surface side, and the Si content of the outer layer is higher than the Si content of the inner layer;
the mole number of Si/mol number of Ti in the outer layer is 3.0 or more and 7.0 or less,
the molar ratio of Si to Ti in the inner layer is 1.0 or more and 4.0 or less;
Multilayer ceramic capacitor.
the exposed surfaces of the first internal electrodes and the second internal electrodes on the first side surface and the second side surface of the laminate contain more Si than central portions of the first internal electrodes and the second internal electrodes;
The multilayer ceramic capacitor according to claim 1 .
the ratio of the mole number of Si to the mole number of Ti in the side ceramic layer is 1.0 or more and 7.0 or less;
3. The multilayer ceramic capacitor according to claim 1.
A multilayer ceramic capacitor as recited in any one of claims 1 to 3, wherein the dimension of the side ceramic layer along the width direction is 5 μm or more and 40 μm or less.