JP7734909B2 - Image Sensor - Google Patents

Description

The present invention relates to an image sensor .

Image sensors generally consist of a photoelectric sensor that converts optical signals into electrical signals, multiple pixels equipped with transistors that control the electrical signals, arranged two-dimensionally in the row and column directions, a column A/D (analog-to-digital) converter that converts the electrical signals of each row and column into digital values, and a scanning circuit that controls each pixel. Furthermore, by using photoelectric films such as organic thin films, quantum dot thin films, and carbon-based thin films in photoelectric sensors, it becomes possible to detect light in wavelength ranges such as infrared light, which could not be detected by the silicon photodiodes used until now. Furthermore, by combining multiple photoelectric films with different properties, it becomes possible to give image sensors a variety of functions.

Fig. 16 is a circuit diagram showing the configuration of a pixel using a photoelectric film. The pixel 100 shown in Fig. 16 is provided with a reset transistor _M0 that resets the photoelectric film 110 to a predetermined voltage, a capacitance _{CH that} stores the photocurrent flowing through the photoelectric film 110 as charge, a transistor _M1 that forms a source follower, and a transistor _M2 that selects a pixel and selectively outputs a voltage proportional to the stored charge to a common signal line D via the source follower. A configuration having three transistors as shown in Fig. 16 is generally called a three-transistor configuration (see, for example, Patent Document 1 and Non-Patent Document 1).

Figure 17 is a block diagram showing an example configuration of an image sensor using the pixels 100 shown in Figure 16. In the image sensor shown in Figure 17, the pixels 100 are arranged two-dimensionally in the row and column directions, and each pixel 100 is controlled row by row by a vertical scanning circuit 101, and signals are extracted sequentially. The signals of the pixels 100 in each selected row are then converted into digital values by multiple A/D converters 102.

Japanese Patent Application Laid-Open No. 2000-165760

Takao Kuroda, "The Essence and Fundamentals of Image Sensors," Corona Publishing, December 21, 2012, pp. 96-110

However, the conventional three-transistor pixel configuration mentioned above has the problem that it is difficult to perform effective correlated double sampling and produces a lot of noise.

FIG. 18 is a waveform diagram showing the terminal voltage V _RST of the capacitance C _H buffered by a source follower formed by the transistor _M1 in the pixel 100. In FIG. 18, the portion surrounded by a dashed line indicates the readout period of the pixel signal. As shown in FIG. 18, the reset signal RST first goes "H", and the terminal voltage V _RST of the capacitance C _H becomes a reset voltage V _RST(n-m) due to the transistor _M0 . Here, n is the row number from which the signal is read out, and m is the exposure time expressed in terms of the number of rows. This reset voltage V _RST(n-m) is expressed by the following equation 1, where V _TH0 is the threshold voltage of the transistor _M0 and V _DD is the power supply voltage.

Next, when the reset signal RST is set to "L" to turn off the transistor _M0 , the voltage V _STD(n-m) that becomes the starting point of exposure after the reset is released is expressed by the following formula 2. Note that V _n(n-m) shown in the following formula 2 is a noise voltage that includes kT/C noise related to the capacitance C _H and an offset voltage due to switch feedthrough.

When exposure begins, the terminal voltage V _SIG(n) during readout is expressed by the following equation 3, starting from the voltage V _STD(n-m) , where I _p is the current excited by light, C _H is the storage capacitance, and T _H is one horizontal period.

Next, after reading out the signal, when the reset signal RST is set to "H", the terminal voltage _VG becomes the voltage shown in the above formula 1, and is therefore expressed by the following formula 4.

Therefore, the output voltage V _CDS(n) obtained by subtracting the voltage V _RST(n) expressed by the above formula 4 from the voltage V _SIG(n) expressed by the above formula 3 is expressed by the following formula 5.

The voltage _VTH of the MOS transistor _M0 shown in the above equation 5 does not appear in the signal obtained after cancellation, so it is possible to avoid the influence of variations in the threshold voltage of the transistor. Similarly, when the voltage of the signal line D is A/D converted, it is read out via a source follower formed by the transistor _M1 , and if the gate-to-source voltage is _VGS1 , the readout voltage is influenced by this voltage. However, since the difference in readout time between the signal voltage V _SIG(n) and the signal voltage V _RST(n) is short, it is thought that the voltage _VGS1 changes very little during this time. For this reason, the voltage _VGS1 is cancelled out by correlated double sampling (CDS), and its influence is very little.

However, as shown in the above formula 5, a pixel having a conventional three-transistor configuration cannot remove the noise Vn _(n-m) that is induced when the reset signal RST is set to "L" to release the reset. For this reason, image sensors having pixels having a conventional three-transistor configuration have a major problem in that they are noisy, and the SNR (Signal to Noise Ratio) decreases, particularly in weak light, resulting in degradation of image quality.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an image sensor that operates with low noise and low power consumption even when the pixel has a three-transistor configuration.

In order to solve the above-mentioned problems, the inventors investigated signal readout from CMOS image sensors and discovered that, rather than simply performing correlated double sampling by taking the voltage difference between the signal voltage of the storage capacitor after exposure and the reset voltage as in the past, correlated double sampling can be performed by taking the voltage difference between the reset signal before exposure begins and the voltage of the storage capacitor immediately after reset is released, and by calculating the difference between these two correlated double sampling signals, it is possible to cancel out the effects of noise and transistor threshold drift, leading to the present invention.

That is, the image sensor according to the present invention comprises a plurality of pixels arranged two-dimensionally in row and column directions, a vertical scanning circuit that selects pixels in a specific row, a plurality of analog-to-digital converters that perform analog-to-digital conversion in column-parallel on signals from each pixel in the row selected by the vertical scanning circuit, and a control unit that controls the pixels, the vertical scanning circuit, and the analog-to-digital converters,
The pixel includes a photoelectric conversion element that converts an optical signal into a current, a capacitance that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage, a reset unit that resets the capacitance to a predetermined voltage, and a voltage buffer unit that receives the voltage of the capacitance as an input,
The control unit controls: (1) a first reset operation in which, in each pixel of a specific row selected by the vertical scanning circuit, the reset unit resets the capacitance to a predetermined voltage and then releases the reset; (2) an operation in which the analog-to-digital converter converts the difference between the first reset voltage extracted by the voltage buffer unit of each pixel of the specific row and the voltage at the time of the reset release into a digital value and stores the value in memory as a reference signal value; (3) an operation in which, after a certain exposure time has elapsed since the reset release, the control unit performs a second reset operation, converting the difference between the voltage extracted by the voltage buffer unit just before the second reset operation and the voltage at the time of the second reset into a digital value and using the analog-to-digital converter as an accumulation signal value; and (4) an operation in which the difference value between the reference signal value stored in memory and the accumulation signal value is output as an analog-to-digital conversion value of the pixel signal.

Furthermore, an image sensing method according to the present invention is a method of performing image sensing using an image sensor having a plurality of pixels arranged two-dimensionally in row and column directions, a vertical scanning circuit that selects pixels in a specific row, a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from each pixel in the row selected by the vertical scanning circuit, and a control unit that controls the pixels, the vertical scanning circuit, and the analog-to-digital converters, wherein the pixels each include a photoelectric conversion element that converts an optical signal into a current, a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage, a reset unit that resets the capacitor to a predetermined voltage, and a voltage buffer unit that receives as input the voltage of the capacitor,
a step of performing a first reset operation by the reset unit for pixels in a specific row selected by the vertical scanning circuit, resetting capacitances of the pixels to a predetermined voltage, and then releasing the set state;
converting a difference between the first reset voltage extracted by the voltage buffer unit and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value;
A second reset operation is performed after a certain exposure time has elapsed since the reset release, and the difference between the voltage immediately before the second reset operation extracted by the voltage buffer unit and the voltage at the time of the second reset is converted into a digital value by the analog-to-digital converter, and this value is used as an accumulation signal value, and the difference value between the reference signal value input to the memory and the accumulation signal value is used as an analog-to-digital conversion value of the pixel signal.

According to the present invention, even in a pixel having a three-transistor configuration, reset noise and drift in the threshold voltage of the transistors can be canceled, so that a high-quality image sensor with less noise can be realized.

1 is a block diagram showing a configuration of an image sensor according to an embodiment of the present invention; 2 is a waveform diagram showing a signal voltage in a pixel 10 of the image sensor 1 shown in FIG. 1. FIG. 10 is a diagram showing output timings of a reset signal RST, a selection signal SEL, and an analog-to-digital conversion signal. FIG. 10 is a diagram illustrating a correlated double sampling method using a memory 13. FIG. 2 is a diagram showing the timing at which signals are output from the pixels 10 in each row. 2 is a circuit diagram showing the configuration of a differential amplifier used in the A/D converter 12. FIG. FIG. 7 is a block diagram showing the configuration of a time domain A/D converter using the differential amplifier 20 shown in FIG. 6 as a comparator. 1A to 1D are circuit diagrams showing a first A/D conversion method. AF are circuit diagrams showing a second A/D conversion method. AF are circuit diagrams showing a third A/D conversion method. 10A is a circuit diagram showing a third A/D conversion method, and FIG. 10B is a waveform diagram showing the relationship between the signal and the reference voltage V _R2 during operation of A. 10A to 10C are circuit diagrams showing a fourth A/D conversion method. 10A to 10C are circuit diagrams showing a fourth A/D conversion method. 5A to 5D are circuit diagrams showing a fifth A/D conversion method. 10A to 10C are circuit diagrams showing a fifth A/D conversion method. FIG. 1 is a circuit diagram showing the configuration of a pixel using a photoelectric film. FIG. 17 is a block diagram showing an example of the configuration of an image sensor using the pixel 100 shown in FIG. 16. 10 is a waveform diagram showing the terminal voltage V _G of the capacitance C _H buffered by a source follower formed by the transistor M ₁ in the pixel 100. FIG.

The following describes in detail the embodiments of the invention, using the accompanying drawings. Note that the present invention is not limited to the embodiments described below.

Figure 1 is a block diagram showing the configuration of an image sensor according to an embodiment of the present invention. As shown in Figure 1, the image sensor 1 of this embodiment includes a plurality of pixels 10, a vertical scanning circuit 11 that selects pixels in a specific row, a plurality of A/D converters 12 that perform column-parallel analog-to-digital conversion of signals from each pixel 10 in the row selected by the vertical scanning circuit 11, a memory 13 that stores output signals from the A/D converters 12, and a control unit 14 that controls the pixels 10, vertical scanning circuit 11, and analog-to-digital converters 12.

The pixel 10 is provided with a photoelectric conversion element that converts an optical signal into a current, a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage, a reset unit that resets the capacitor to a predetermined voltage, and a voltage buffer unit that receives the voltage of the capacitor as an input. The reset unit and voltage buffer unit can be composed of, for example, MOS transistors. Note that either the reset unit or the voltage buffer unit may be composed of a MOS transistor, or both may be composed of MOS transistors.

In the image sensor 1 of this embodiment, multiple pixels 10 are arranged two-dimensionally in the row and column directions, and each pixel 10 is controlled row by row by a vertical scanning circuit 11, and signals are extracted sequentially. The signals from the pixels 10 in each selected row are then converted to digital values by an A/D converter 12, and the output signal from the A/D converter 12 is temporarily stored in memory 13. The difference with the output signal from the A/D converter 12 at any given time is calculated and output as a converted output signal.

At this time, the control unit 14 controls the following operations (1) to (4).
(1) A first reset operation in which, in each pixel 10 in a specific row selected by the vertical scanning circuit 11, the capacitance is reset to a predetermined voltage by the reset unit, and then the reset is released.
(2) The difference between the first reset voltage extracted by the voltage buffer unit of each pixel 10 in a specific row and the voltage at the time of reset release is converted into a digital value by the A/D converter 12, and the value is stored in the memory 13 as a reference signal value.
(3) After a certain exposure time has elapsed since the reset was released, a second reset operation is performed, and the difference between the voltage immediately before the second reset operation extracted by the voltage buffer unit and the voltage at the time of the second reset is converted into a digital value by the A/D converter 12, and this value is used as the accumulation signal value.
(4) An operation of outputting the difference value between the reference signal value stored in the memory 13 and the aforementioned accumulated signal value as an analog-to-digital converted value of the pixel signal.

[Operation]
Fig. 2 is a waveform diagram showing a signal voltage in pixel 10 of image sensor 1 shown in Fig. 1. Fig. 2 shows the terminal voltage _VG of charge storage capacitance _CH buffered by a source follower using transistor _M1 in pixel 10, and the time range shown by the dashed line is the voltage transmission period (pixel signal selection period) from pixel 10 to the common signal line used to control transistor _M3 .

2, in the image sensor 1 of this embodiment, first, in the first reset to start exposure, the reset pulse RST goes to "H", and the terminal voltage V _G becomes a reset voltage V _RST(n-m) due to the transistor _M0 . Here, n is the number of the row from which the signal is read out, and m is the exposure time expressed in terms of the number of rows. This reset voltage V _RST(n-m) is expressed by the following equation 6 using the threshold voltage V _TH(n-m) of the transistor _M0 and the power supply voltage V _DD .

Next, when the reset signal RST is set to "L" to turn off the transistor _M0 and release the reset, the voltage V _STD(n-m) that is the starting point of exposure is expressed as the noise voltage V _n(n-m) , which is the sum of the offset voltage due to switch feedthrough and the kT/C noise related to the capacitance C _H , as in the conventional case, by the following equation 7:

In the image sensor 1 of this embodiment, these two signals are A/D converted. At that time, the voltages are shifted by the gate-source voltage _VGS of the transistor _M1 . Taking this effect into consideration, these voltages are expressed by the following formulas 8 and 9.

Then, as shown in the following Equation 10, when the difference between the two signals expressed by Equations 8 and 9 is taken, only the noise voltage V _n(n−m) remains.

In the image sensor 1 of this embodiment, the A/D converted value representing this noise voltage V _n(n−m) is stored in the memory 13 .

As the exposure time elapses, the terminal voltage V _G in the pixel 10 gradually decreases due to the current excited by light. After the specified exposure time has elapsed, the pixel selection signal SEL is set to "H" to turn on the transistor _M2 , causing the terminal voltage V _G to be output to the common signal line D via the source follower. The input voltage V _{SIG(n)_ADC} of the A/D converter 12 at this time is expressed by the following equation 11, where I _p is the current excited by light, T _H is one horizontal period, and V _GS(n) is the gate-source voltage of the source follower.

Next, when the reset signal RST is set to "H" in the second reset for ending the exposure, the input voltage V _{RST(n)_ADC} of the A/D converter 12 is expressed by the following equation 12.

The output voltage V _{SIG(n) — CDS} obtained by subtracting the input voltage V _{RST(n) —} ADC expressed by the above Equation 12 from the input voltage V _SIG(n) — _ADC expressed by the above Equation 11 is expressed by the following Equation 13.

Here, it is considered that there is almost no fluctuation in the threshold voltage _VTH , or that if the threshold voltage is depleted, the threshold voltage causes almost no fluctuation in the input voltage of the A/D converter 12, and therefore, the above formula 13 can be expressed as the following formula 14.

Thereafter, the voltage V _{STD(n-m)_CDS} stored in memory 13 is read out, and the voltage obtained by taking the difference therebetween is defined as V _{SIG(n)_DCDS} . As shown in the following formula 15, the noise is cancelled out, and only the signal due to light can be extracted.

Figure 3 shows the output timing of the reset signal RST, selection signal SEL, and analog-to-digital conversion signal. As shown in Figure 3, in the image sensor 1 of this embodiment, the first reset signal RST(n-1-m) for row (n-1-m) first goes "H," and then, a short time later, the selection signal SEL(n-1-m) for row (n-1-m) goes "H." Even after the first reset signal RST(n-1-m) goes "L," the signal after reset must be A/D converted, so it remains "H" for a while before going "L." Then, after a short interval, the reset signal RST(n-m) for row (n-m) goes "H," and a short time later the selection signal SEL(n-m) for row (n-m) goes "H," and this process is repeated to sequentially shift the rows.

When the exposure time indicated by row m has elapsed, the selection signal SEL(n-1) first goes "H," extracting the signal voltage V _{SIG(n-1) in which} current excited by light has accumulated, and after A/D conversion, the second reset signal RST(n-1) goes "H." Then, after the reset signal V _RST(n-1) is A/D converted, the selection signal SEL(n-1) goes "L." Next, after a short interval, the selection signal SEL(n) for row n goes "H," and after a slight delay, the reset signal RST(n) for row n goes "H," shifting the rows sequentially. The A/D conversion signals alternately generate a reference signal STD_CDS obtained by correlated double sampling ( _CDS ) and a pixel signal SIG_CDS obtained by correlated double sampling ( _CDS ).

4 is a diagram showing a correlated double sampling method using memory 13. As shown in Fig. 4, a reference signal _{STD_CDS} that has been subjected to correlated double sampling (CDS) is stored in memory 13 and is read out at the timing of generation of a pixel signal _{SIG_CDS} that has been subjected to correlated double sampling (CDS). Then, a difference is taken between the pixel signal _{SIG_CDS} and the reference signal _{STD_CDS} , and a final correlated double sampling (CDS) is performed to remove noise and produce a final converted output.

Figure 5 shows the timing at which signals are output from the pixels 10 in each row. As shown in Figure 5, in the image sensor 1 of this embodiment, a first reset voltage is output to the common line during the first 1/4 horizontal period of one horizontal period, and a reference voltage is output to the common line during the next 1/4 horizontal period.

Then, the exposure period begins, and when the specified exposure period ends (set to two horizontal periods in Figure 4), the signal voltage due to the photocurrent accumulated in the capacitor is output to the common line during the latter 1/4 horizontal period, and the second reset voltage is output to the common line during the latter 1/4 horizontal period. In this way, in the image sensor 1 of this embodiment, the first reset voltage, reference voltage, signal voltage due to the photocurrent, and second reset voltage are output to the common line in 1/4 horizontal period units in this order during one horizontal period to prevent the signals from overlapping.

[A/D converter 12]
Next, the A/D converter 12 for realizing the above-mentioned operation will be described. Fig. 6 is a circuit diagram showing the configuration of a differential amplifier used in the A/D converter 12 shown in Fig. 1. In the differential amplifier 20 shown in Fig. 6, transistors _M1a and _M1b form a differential pair that converts a differential input voltage into a differential current, and transistors _M2a and _M2b form a current mirror that converts the differential current into an output voltage, and the differential input voltage is amplified and appears as an output voltage.

The transistor _M0 provides a bias current for the differential pair, and the voltage _VB is its bias voltage. A switch _S1 is provided between the input and output terminals of the differential amplifier 20. A pair of capacitors _Cs is provided between the signal input terminals _INa and _INb and the output terminal of the differential amplifier 20.

Fig. 7 is a block diagram showing the configuration of a time domain A/D converter using the differential amplifier 20 shown in Fig. 6 as a comparator. As shown in Fig. 7, the differential amplifier 20 amplifies the differential voltage between signal input terminals IN _a and IN _b and generates the amplified signal at the output terminal. The counter 21 counts clocks to update time information, and the output signal of the differential amplifier 20 serves as a stop signal for the counter 21, and the time information at the moment the stop signal appears is stored in the counter 21.

In the image sensor 1 of this embodiment, time information can be obtained using a time-to-digital converter other than the counter 21, which inputs a time-varying code and latches the code at the moment the stop signal appears. The output of the counter 21 is often directly converted into an A/D converted signal, but as shown in Figure 7, a cumulative adder 22 can also be used, where multiple pieces of time information are input to the cumulative adder 22, which then accumulates and adds them, and the resulting average value is output as an A/D converted signal.

The time domain A/D converter shown in FIG. 7 can realize an image sensor with many features, as will be described below, by controlling each switch _S1 of the differential amplifier 20 and applying voltages to the input terminals IN _a and IN _b .

<First A/D conversion method>
8A to 8D are circuit diagrams showing a first A/D conversion method. In the first A/D conversion method, first, sampling is performed on the voltage _VRST1 appearing on the common signal line at reset. Specifically, as shown in FIG. 8A, the voltage _VRST1 appearing on the common signal line at reset is applied to the first signal input terminal _INa , and a reference voltage VRO1 serving as a reference is applied to the second signal input terminal _INb , and _the switch _S1 is closed. At this time, the voltage between the terminals of the capacitors _Csa and _Csb is expressed by the following equation 16, where _Vc is the common input/output voltage of the differential amplifier 20.

Next, the voltage V _STD appearing on the common signal line after reset release and the voltage V _RST1 appearing on the common signal line during reset are converted. Specifically, as shown in Fig. 8B, the switch _S1 is opened, the voltage V _STD appearing on the common signal line after reset release is applied to the first signal input terminal IN _a , and a reference voltage V _R1 whose voltage changes in proportion to time is applied to the second signal input terminal IN _b , and the voltages _Va and V _b appearing at the two input terminals of the differential amplifier 20 are compared. The voltages _Va and V _b at this time are expressed by the following equation 17 using the above equation 16.

The input voltage condition under which the output voltage changes is expressed by the following formula 18, so the difference between the reset voltage V _{STD and the reset voltage V RST1} after reset is taken, and the signal obtained by correlated double sampling (CDS) becomes the converted signal. This correlated double sampled (CDS) signal is then A/D converted into a digital value and stored in the memory 13.

Next, after a certain exposure time has elapsed, signal sampling is performed. Specifically, as shown in Fig. 8C, the voltage V _SIG of the storage capacitance appearing on the common signal line via the source follower is applied to the first signal input terminal IN _a , and a reference voltage V _R02 serving as a reference is applied to the second signal input terminal IN _b , and the switch S ₁ is closed. At this time, the voltage between the terminals of the capacitances C _sa and C _sb is expressed by the following equation 19, where V _c is the common input/output voltage of the differential amplifier 20.

Next, the difference between the voltage V _SIG of the storage capacitor appearing on the common signal line via the source follower and the voltage V _RST2 appearing on the common signal line during the second reset is converted. Specifically, as shown in Fig. 8D, the switch _S1 is opened, the voltage V _RST2 appearing on the common signal line during the second reset is applied to the first signal input terminal IN _a , and a reference voltage V R2 whose voltage changes in proportion to time is applied to the second signal input terminal _{IN b} , and the voltages Va and V _b appearing at the two input terminals of the differential amplifier ₂₀ are compared. The voltages _Va and V _b at this time are expressed by the following equation 20 using the above equation 19.

Since the input voltage condition under which the output voltage changes is expressed by the following equation 21, the difference between the signal voltage V _SIG immediately before the second reset and the second reset voltage V _RST2 is taken, and the signal that has been subjected to correlated double sampling (CDS) becomes the converted signal. This CDS-subjected signal is then A/D converted to a digital value, and the data stored in memory 13 during the A/D conversion operation shown in FIG. 8B is read out, and the difference is taken to become the final A/D-converted value of the pixel signal.

The first A/D conversion method described above performs correlated double sampling (CDS) using the analog voltage sampled on a capacitor, so only two A/D conversions are required. Furthermore, in the A/D conversion shown in Figure 8B, the difference between the first reset voltage and the voltage after reset is released is considered to be extremely small, so the time required for A/D conversion can be shortened. Therefore, this method is effective in shortening conversion time.

<Second A/D Conversion Method>
9A to 9F are circuit diagrams illustrating a second A/D conversion method. In the second A/D conversion method, first, sampling is performed on the voltage _VRST1 appearing on the common signal line at reset. Specifically, as shown in FIG. 9A, the voltage _VRST1 appearing on the common signal line at reset is applied to the first signal input terminal _INa , and a reference voltage VRO1 serving as a reference is applied to the second signal input _{terminal INb} , and the switch _S1 is closed. At this time, the voltage between the terminals of the capacitances _Csa and _Csb is expressed by the aforementioned Equation 16, where _Vc is the common input/output voltage of the differential amplifier 20.

Next, the offset and noise of the comparator 20 are converted. Specifically, as shown in FIG. 9B , the switch _S1 is opened, and the voltage _VRST1 continues to be applied to the first signal input terminal _INa , while a reference voltage _VR1 , which changes in proportion to time, is applied to the second signal input terminal _INb , and the voltages _Va and _Vb appearing at the two input terminals of the differential amplifier 20 are compared. When the switch _S1 is opened, an offset voltage due to switch pulse feedthrough and kT/C noise due to capacitances _Csa and _Csb are generated. Assuming that these non-ideal voltages appear at terminal a and denoted as _ΔV1 , the voltages _Va and _Vb can be expressed by the following equation 22:

The input voltage condition under which the output voltage changes can be expressed by the following equation 23, so the non-ideal voltage _ΔV1 can be A/D converted. Therefore, in the second A/D conversion method, this converted value is temporarily stored in a register or the like.

Next, the voltage V _STD appearing on the common signal line after reset is converted. Specifically, as shown in Fig. 9C, the voltage V _STD appearing on the common signal line after reset is applied to the first signal input terminal IN _a . The voltages _Va and V _b at this time are expressed by the following equation 24.

Since the input voltage conditions under which the output voltage changes are expressed by the following equation 25, the voltage V _STD after reset is subtracted from the reset voltage V _RST1 to convert the correlated double sampled (CDS) signal. However, in this case, a non-ideal voltage _ΔV1 is applied to the voltage after correlated double sampling (CDS). Therefore, in this conversion method, the A/D converted value of the non-ideal voltage _ΔV1 temporarily stored in the register is read out and the difference is calculated. This makes it possible to obtain correlated double sampling (CDS) with the non-ideal voltage _ΔV1 canceled out. The value obtained by calculating this difference is then input to memory 13.

Next, the voltage V _SIG of the storage capacitance appearing on the common signal line via the source follower is sampled. Specifically, after a certain exposure time has elapsed, as shown in FIG. 9D , the voltage V _SIG of the storage capacitance appearing on the common signal line via the source follower is applied to the first signal input terminal IN _a , and a reference voltage V _R02 is applied to the second signal input terminal IN _b , and the switch S ₁ is closed. The voltage between the terminals of the capacitances C _sa and C _sb at this time is expressed by the above-mentioned equation 19, where V _c is the common input/output voltage of the differential amplifier 20.

Next, the offset and noise of the comparator 20 are converted. Specifically, as shown in Fig. 9E, the switch _S1 is opened, and a voltage V _SIG is continuously applied to the first signal input terminal IN _a , while a reference voltage V _R2, which varies in proportion to time, is applied to the second signal input terminal IN _b . The voltages V _a and V _b at this time are expressed by the following equation 26, where ΔV ₂ is the non-ideal voltage.

The input voltage condition under which the output voltage changes can be expressed by the following formula 27, so the non-ideal voltage _ΔV2 can be A/D converted. Therefore, this converted value is temporarily stored in a register or the like.

Next, correlated double sampling (CDS) conversion is performed on the signal level and the second reset voltage _VRST2 . Specifically, as shown in Figure 9F, the voltage _VRST2 that appears on the common signal line during the second reset is applied to the first signal input terminal _INa . At this time, the voltages _Va and _Vb are expressed by the following equation 28.

Since the input voltage condition under which the output voltage changes is expressed by the following equation 29, the signal voltage V _SIG immediately before the second reset is differentially calculated from the second reset voltage V _RST2 , and the correlated double sampled (CDS) signal is converted. However, in this case, the non-ideal voltage _ΔV2 is applied to the correlated double sampled (CDS) voltage. Therefore, in this conversion method, the A/D converted value of the non-ideal voltage _ΔV2 temporarily stored in the register is read out, and the differential is calculated. This allows the correlated double sampled (CDS) signal to be obtained by canceling the non-ideal voltage _ΔV2 .

This correlated double sampled (CDS) voltage is A/D converted to a digital value, and during the A/D conversion operation shown in Figure 9C, the data stored in memory 13 is read out and the difference is taken to become the A/D converted value of the pixel signal.

This second conversion method requires a slightly longer conversion time than the first conversion method described above, but it enables highly accurate A/D conversion by canceling the offset voltage due to switch feedthrough in the comparator and the kT/C noise of the comparator capacitance.

<Third A/D conversion method>
10A-F and 11A are circuit diagrams illustrating a third A/D conversion method, and FIG. 11B is a waveform diagram showing the relationship between the signal and reference voltage V _R2 during operation of FIG. 11A. In the third A/D conversion method, first, sampling of the voltage V _RST1 appearing on the common signal line at reset is performed. Specifically, as shown in FIG. 10A, the voltage V _RST1 appearing on the common signal line at reset is applied to the first signal input terminal IN _a , and a reference voltage V R01 serving as a reference is applied to the second signal input terminal IN _b , _{and switch S 1 is} closed. The voltage between the terminals of capacitances C _sa and C _sb at this time is expressed by the aforementioned Equation 16, where V _c is the common input/output voltage of differential amplifier 20.

Next, conversion (multi-conversion) of the offset and noise of the comparator 20 is performed. Specifically, as shown in Fig. 10B, the switch _S1 is opened, voltage _VRST1 is continuously applied to the first signal input terminal INa, and _a reference voltage _VR1 , whose voltage changes in proportion to time, is applied to the second signal input terminal _INb , and voltages _Va and _Vb appearing at the two input terminals of the differential amplifier 20 are compared.

When switch _S1 is opened, an offset voltage due to switch pulse feedthrough and kT/C noise due to capacitances _Csa and _Csb are generated. Assuming that these non-ideal voltages appear at terminal a and denoted as _ΔV1 , the non-ideal voltage _ΔV1 can be A/D converted from the above-mentioned formulas 22 and 23. In the third A/D conversion method, the operation shown in Fig. 10A and the operation shown in Fig. 10B are repeated alternately multiple times, and the obtained multiple converted values are averaged and temporarily stored in a register or the like.

However, to shorten the conversion time, the operation shown in Fig. 10A may be omitted, and the operation shown in Fig. 10B may be performed multiple times, with the average of the resulting multiple conversion values being taken and temporarily stored in a register or the like. This can effectively reduce noise. Ideally, if the number of conversions is M, the noise voltage _Vn decreases in proportion to the square root of M, as shown in the following equation 30.

Next, the voltage V _STD appearing on the common signal line after reset release is converted (multi-conversion) at the first signal input terminal. Specifically, as shown in FIG. 10C, the voltage V _STD appearing on the common signal line after reset release is applied to the first signal input terminal IN _a . From the above-described Equations 24 and 25, the voltage V _STD after reset release is calculated as a difference with the reset voltage V _RST1 , and the correlated double sampled (CDS) signal is converted.

In this conversion method, the reference voltage V _R1 is also swept multiple times to perform A/D conversion, and the resulting multiple converted values are averaged to obtain the A/D converted value. Because the non-ideal voltage ΔV ₁ is applied to the voltage after correlated double sampling (CDS), the A/D converted value of the non-ideal voltage ΔV ₁ temporarily stored in the register is read out and the difference is calculated to obtain a CDS that cancels the non-ideal voltage ΔV _1. This value is then input to memory 13.

Next, the voltage V _SIG of the storage capacitance appearing on the common signal line via the source follower is sampled. Specifically, after a certain exposure time has elapsed, as shown in FIG. 10D , the voltage V _SIG of the storage capacitance appearing on the common signal line via the source follower is applied to the first signal input terminal IN _a , and a reference voltage V _R02 is applied to the second signal input terminal IN _b , and the switch S ₁ is closed. The voltage between the terminals of the capacitances C _sa and C _sb at this time is expressed by the above-mentioned equation 19, where V _c is the common input/output voltage of the differential amplifier 20.

Next, the offset and noise of the comparator are converted (multi-conversion). Specifically, as shown in FIG. 10E, switch _S1 is opened, voltage V _SIG is continuously applied to the first signal input terminal IN _a , and a reference voltage V _R2 , whose voltage varies in proportion to time, is applied to the second signal input terminal IN _b . At this time, the non-ideal voltage ΔV ₂ can be A/D converted using the above-mentioned Equations 26 and 27.

Furthermore, noise can be effectively reduced by alternately repeating the operation shown in Figure 10D and the operation shown in Figure 10E multiple times, averaging the multiple conversion values obtained, and using the resulting value as the A/D conversion value. In this case as well, to shorten the conversion time, the operation shown in Figure 10D can be omitted, and the operation shown in Figure 10E can be performed multiple times to average the multiple conversion values obtained, and use the resulting value as the A/D conversion value.

10F, a voltage _VRST2 that appears on the common signal line during the second reset is applied to the first signal input terminal _INa , and a threshold voltage _VTH for determining the A/D conversion operation is applied to the second signal input terminal _INb . The voltages V _a and V _b at this time are expressed by the following equation 31.

The input voltage condition under which the output voltage changes is expressed by the following equation 32, so the difference between the signal voltage V _SIG immediately before the second reset and the second reset voltage V _RST2 is taken, and the magnitude of this difference is compared with the threshold voltage V _TH .

If V _RST2 -V _SIG is lower than the threshold voltage V _TH and is a weak signal, the circuit shown in FIG. 11A switches to multi-conversion. At this time, as shown in FIG. 11B, the reference voltage V _R2 is A/D converted multiple times within a limited voltage range slightly wider than the threshold voltage V _TH , and the average of the multiple conversion values obtained is used as the A/D conversion value. This effectively reduces noise. On the other hand, if V _RST2 -V _SIG is higher than the threshold voltage V _TH and is a strong signal, the circuit shown in FIG. 11A switches to single-conversion, and the reference voltage V _R2 sweeps the full-scale voltage range as shown in FIG. 11B.

As described above, this conversion method converts a signal obtained by correlated double sampling (CDS) between the signal _{V_SIG} and the reset signal _{V_RST2} through the operations shown in FIGS. 10D-F and 11A. However, in this case, a non-ideal voltage _ΔV2 is applied to the voltage after correlated double sampling (CDS). Therefore, this conversion method reads out the A/D converted value of the non-ideal voltage _ΔV2 temporarily stored in the register and calculates the difference. This allows for correlated double sampling (CDS) that cancels out the non-ideal voltage _ΔV2 .

This correlated double sampled (CDS) signal is A/D converted to a digital value, and during the A/D conversion operation shown in Figure 10C, the data stored in memory 13 is read out, and the difference is taken to become the A/D converted value of the pixel signal.

This third conversion method takes a little longer to convert than the second conversion method described above, but it not only cancels out the offset voltage due to the comparator's switch feedthrough and the kT/C noise of the comparator's capacitance, but also takes the average of multiple A/D conversion values, thereby reducing noise throughout the circuit even more than the second A/D conversion method described above, enabling extremely low-noise A/D conversion.

<Fourth A/D conversion method>
12A-C and 13A-C are circuit diagrams showing a fourth A/D conversion method. In the fourth A/D conversion method, first, sampling is performed on the voltage _VRST1 that appears on the common signal line at reset. Specifically, as shown in FIG. 12A, the voltage _VRST1 that appears on the common signal line at reset is applied to the first signal input terminal _INa , and a reference voltage _VRO1 is applied to the second signal input terminal _INb , and the switch _S1 is closed. This operation is the same as the operation of the first A/D conversion method shown in FIG. 8A.

Next, the voltage V _STD appearing on the common signal line after reset release is converted to the voltage V _RST1 appearing on the common signal line during reset. Specifically, as shown in FIG. 12B , the switch _S1 is opened, the voltage V _STD appearing on the common signal line after reset release is applied to the first signal input terminal IN _a , and a reference voltage V _R1 whose voltage changes in proportion to time is applied to the second signal input terminal IN _b , and the voltages _Va and V _b appearing at the two input terminals of the differential amplifier 20 are compared. This operation is also the same as the operation of the first A/D conversion method shown in FIG. 8B . The difference between the voltage V _STD after reset release and the reset voltage V _RST1 is then taken, and the correlated double sampled (CDS) signal is converted. The correlated double sampled (CDS) signal is A/D converted to a digital value and input to the memory 13.

Next, signal sampling is performed. Specifically, after a certain exposure time has elapsed, as shown in Fig. 12C, the voltage V _SIG of the storage capacitance appearing on the common signal line via the source follower is applied to the first and second signal input terminals, and the switch _S1 is closed. At this time, the terminal voltages of the capacitances C _sa and C _sb are equal, and are expressed by the following equation 33, where V _c is the common input/output voltage of the differential amplifier 20.

Next, the voltage V _SIG is converted. Specifically, as shown in Fig. 13A, the switch _S1 is opened, the voltage V _SIG is continuously applied to the first signal input terminal IN _a , and a reference voltage V _R2 , which changes in proportion to time, is applied to the second signal input terminal IN _b , and the voltages Va and V _b appearing at the two input terminals of the differential amplifier 20 are compared. _{The voltages Va and V b at this} time are expressed by the following equation 34 using the above equation 33.

The input voltage condition under which the output voltage changes is expressed by the following equation 35, so the voltage _{V_SIG} is A/D converted and the converted value is stored in a register.

Next, the voltage _VRST2 of the storage capacitance appearing on the common signal line via the source follower is sampled. Specifically, as shown in Fig. 13B, the voltage _VRST2 of the storage capacitance appearing on the common signal line via the source follower is applied to the first and second signal input terminals, and the switch _S1 is closed. At this time, the terminal voltages of the capacitances _Csa and _Csb are equal, and are expressed by the following equation 36, where _Vc is the common input/output voltage of the differential amplifier 20.

Next, the voltage _VRST2 is converted. Specifically, as shown in Fig. 13C, the switch _S1 is opened, the voltage _VRST2 is continuously applied to the first signal input terminal, and a reference voltage _VR2 , which changes in proportion to time, is applied to the second signal input terminal, and the voltages _Va and _Vb appearing at the two input terminals of the differential amplifier 20 are compared. The voltages _Va and _Vb at this time are expressed by the following equation 37 using the above equation 36.

The condition of the input voltage at which the output voltage changes is expressed by the following equation 38, so the signal voltage V _RST2 is A/D converted. Next, the digital difference between this converted value and the A/D converted value of the voltage V _SIG stored in the register is taken, and a digital value is obtained by correlated double sampling (CDS). Finally, the data stored in memory 13 during the A/D conversion operation shown in FIG. 12B is read out, and this difference is taken to be the A/D converted value of the pixel signal.

In the fourth A/D conversion method, when two voltages _Va and _Vb are compared, the voltages at the two input terminals of the differential amplifier are close to the common voltage _Vc , so it is possible to restrict the input voltage range of the differential amplifier, thereby lowering the operating voltage of the differential amplifier and enabling the A/D converter to consume less power.

<Fifth A/D conversion method>
14A-D and 15A-C are circuit diagrams showing a fifth A/D conversion method. In the fifth A/D conversion method, first, the voltage _VRST1 appearing on the common signal line at reset is sampled. Specifically, as shown in FIG. 14A, the voltage _VRST1 appearing on the common signal line at reset is applied to the first signal input terminal _INa , and a reference voltage _VRO1 serving as a reference is applied to the second signal input terminal _INb , and the switch _S1 is closed. This operation is the same as the fourth A/D conversion method shown in FIG. 12A.

Next, a multi-conversion is performed between the voltage V _STD appearing on the common signal line after reset release and the voltage V _RST1 appearing on the common signal line during reset. Specifically, as shown in Fig. 14B, the switch _S1 is opened, the voltage V _STD appearing on the common signal line after reset release is applied to the first signal input terminal IN _a , and a reference voltage V _R1 whose voltage changes in proportion to time is applied to the second signal input terminal IN _b , and the voltages _Va and V _b appearing at the two input terminals of the differential amplifier 20 are compared.

The reference voltage V _R1 is then swept multiple times within a limited voltage range and A/D converted, and the resulting multiple A/D converted values are averaged and used as the A/D converted value. The voltage V _STD after reset release is the difference between it _{and the reset voltage V RST1} , and a correlated double sampled (CDS) signal is converted. This correlated double sampled (CDS) voltage is A/D converted to a digital value and input to the memory 13.

Next, signal sampling is performed. Specifically, after a certain exposure time has elapsed, the voltage V SIG of the storage _capacitor appearing on the common signal line via the source follower is applied to the first and second signal input terminals, and the switch S1 is closed, as shown in Fig. _14C . This operation is the same as the operation in Fig. 12C in the fourth conversion method described above.

Next, the magnitude of the voltage V _SIG is determined. Specifically, as shown in Fig. 14D, the switch _S1 is opened, the voltage V _SIG is continuously applied to the first signal input terminal, and the threshold voltage V _TH is temporarily applied to the second signal input terminal. The voltages _Va and _Vb appearing at the two input terminals of the differential amplifier 20 are compared to determine the magnitudes of the voltage V _SIG and the threshold voltage V _TH .

If the determination result shows that the voltage V _SIG is lower than the threshold voltage V _TH and is a weak signal, the circuit shown in FIG. 15A performs multi-conversion, and as shown in FIG. 11B, the reference voltage V _R2 is swept multiple times within a limited voltage range slightly wider than the threshold voltage V _TH , and the average of the multiple conversion values obtained is taken as the A/D conversion value. This effectively reduces noise. On the other hand, if the voltage V _SIG is higher than the threshold voltage V _TH and is a strong signal, the circuit shown in FIG. 15A performs single-conversion, and as shown in FIG. 11B, the reference voltage V _R2 is swept across the full-scale voltage range. In either operation, the voltage V _SIG is A/D converted, and the converted value is stored in a register.

Next, the voltage _VRST2 of the storage capacitor appearing on the common signal line via the source follower is sampled. Specifically, as shown in FIG. 15B, the voltage _VRST2 of the storage capacitor appearing on the common signal line via the source follower is applied to the first and second signal input terminals, and the switch _S1 is closed.

Next, the voltage _VRST2 is multi-converted. Specifically, as shown in FIG. 15C, the switch _S1 is opened, and the voltage _VRST2 is continuously applied to the first signal input terminal _INa , while the reference voltage _VR2 , whose voltage varies in proportion to time, is applied to the second signal input terminal _INb . Then, multiple sweeps are performed within a limited voltage range, and the average of the resulting multiple conversion values is taken as the A/D conversion value. This effectively reduces noise. During this process, the signal voltage _VRST2 is A/D converted.

Next, the digital difference between this converted value and the A/D converted value of the voltage V _SIG stored in the register is taken, and a digital value is obtained by correlated double sampling (CDS). Finally, the data stored in memory 13 during the A/D conversion operation shown in FIG. 14B is read out, and the difference is taken to become the A/D converted value of the pixel signal.

In the fifth A/D conversion method, similar to the fourth A/D conversion method described above, when two voltages Va and _Vb are compared, the voltages at the two input terminals of the differential amplifier are close to the common voltage _{Vc ,} making it possible to restrict the input voltage range of the differential amplifier. As a result, the operating voltage of the differential amplifier can be lowered, and the power consumption of the A/D converter can be reduced. Furthermore, in the fifth A/D conversion method, A/D conversion is performed multiple times and the average value is calculated, which also makes it possible to reduce read noise.

In order to rationally set the sweep range of the reference voltage and the threshold voltage, it is necessary to measure the first reset voltage, the second reset voltage, the voltage immediately after the first reset is released, and the signal voltage before the second reset, rather than the voltage obtained by correlated double sampling (CDS). For this reason, the image sensor of this embodiment stores the A/D converted value of the first reset voltage, the A/D converted value of the second reset voltage, the A/D converted value of the voltage after the first reset, and the A/D converted value before the second reset, and uses this to determine the voltage range of the reference voltage or the threshold voltage, thereby enabling higher accuracy and faster operation.

As described above in detail, the image sensor of this embodiment converts the difference between the first reset voltage extracted by the voltage buffer unit of each pixel in a specific row and the voltage at the time of first reset release into a digital value using an analog-to-digital converter, stores this value in memory as a reference signal value, performs a second reset operation after a certain exposure time has elapsed since reset release, converts the difference between the voltage extracted by the voltage buffer unit just before the second reset operation and the voltage at the time of the second reset into a digital value using an analog-to-digital converter, and sets this value as an accumulation signal value. The difference between the reference signal value and the accumulation signal value stored in memory is output as the analog-to-digital conversion value of the pixel signal. Therefore, even with a three-transistor pixel, reset noise and transistor threshold voltage drift can be canceled out, resulting in high-quality images with little noise.

REFERENCE SIGNS LIST 1 Image sensor 10, 100 Pixel 11, 101 Vertical scanning circuit 12, 102 Analog-to-digital (A/D) converter 13 Memory 14 Control unit 20 Differential amplifier 21 Counter 22 Accumulator 110 Photoelectric film

Claims (7)

A plurality of pixels arranged two-dimensionally in row and column directions;
a vertical scanning circuit for selecting pixels in a specific row;
a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit;
a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter;
and
The pixel is
a photoelectric conversion element that converts an optical signal into an electric current;
a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage;
a reset unit that resets the capacitor to a predetermined voltage;
a voltage buffer unit that receives the voltage of the capacitor as an input;
Equipped with
The analog-to-digital converter
a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals;
a first switch provided between the first input terminal and the first output terminal;
a second switch provided between the second input terminal and the second output terminal;
a first capacitance provided between a first signal input terminal and the first input end;
a second capacitor provided between a second signal input terminal and the second input end;
and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value,
The control unit
a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset;
an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value;
an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and
an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal;
Control the
a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches;
a second step in which the first and second switches are released, the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the first and second output terminals is stored in a memory as a first analog-to-digital converted value;
a third step of applying a voltage of the common signal line immediately before the second reset to the first signal input terminal, applying a second standard reference voltage to the second signal input terminal, and closing the first and second switches;
a fourth step in which the first and second switches are released, a voltage of the common signal line at the second reset time is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the first and second output terminals is converted into a second analog-to-digital converted value;
and
an image sensor that sets a difference value between the first analog-to-digital converted value and the second analog-to-digital converted value stored in the memory as an analog-to-digital converted value of a pixel signal ; A plurality of pixels arranged two-dimensionally in row and column directions;
a vertical scanning circuit for selecting pixels in a specific row;
a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit;
a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter;
and
The pixel is
a photoelectric conversion element that converts an optical signal into an electric current;
a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage;
a reset unit that resets the capacitor to a predetermined voltage;
a voltage buffer unit that receives the voltage of the capacitor as an input;
Equipped with
The analog-to-digital converter
a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals;
a first switch provided between the first input terminal and the first output terminal;
a second switch provided between the second input terminal and the second output terminal;
a first capacitance provided between a first signal input terminal and the first input end;
a second capacitor provided between a second signal input terminal and the second input end;
and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value,
The control unit
a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset;
an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value;
an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and
an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal;
Control the
a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches;
a second step in which the first and second switches are released, the voltage of the common signal line at the first reset time is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the first and second output terminals is temporarily stored in a register as a first analog-to-digital converted value;
a third step of applying a voltage of the common signal line after the first reset is released to the first signal input terminal, applying a reference voltage whose voltage changes in proportion to time to the second signal input terminal, setting time information at the time of generation of a stop signal from the first and second output terminals as a second analog-digital converted value, and storing in memory a difference between the second analog-digital converted value and the first analog-digital converted value stored in the register in the second step as a third analog-digital converted value;
a fourth step of applying a voltage of the common signal line immediately before the second reset to the first signal input terminal, applying a second standard reference signal to the second signal input terminal, and closing the first and second switches;
a fifth step in which the first and second switches are released, a voltage of the common signal line immediately before the second reset is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the output terminal is temporarily stored in a register as a fourth analog-to-digital converted value;
a sixth step in which the voltage of the common signal line at the second reset time is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, time information at the time of generation of a stop signal from the first and second output terminals is set as a fifth analog-to-digital converted value, and a difference value between the fifth analog-to-digital converted value and the fourth analog-to-digital converted value stored in the register in the fourth step is set as a sixth analog-to-digital converted value;
and
an image sensor that sets a difference value between the third analog-to-digital converted value stored in the memory and the sixth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal; A plurality of pixels arranged two-dimensionally in row and column directions;
a vertical scanning circuit for selecting pixels in a specific row;
a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit;
a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter;
and
The pixel is
a photoelectric conversion element that converts an optical signal into an electric current;
a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage;
a reset unit that resets the capacitor to a predetermined voltage;
a voltage buffer unit that receives the voltage of the capacitor as an input;
Equipped with
The analog-to-digital converter
a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals;
a first switch provided between the first input terminal and the first output terminal;
a second switch provided between the second input terminal and the second output terminal;
a first capacitance provided between a first signal input terminal and the first input end;
a second capacitor provided between a second signal input terminal and the second input end;
and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value,
The control unit
a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset;
an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value;
an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and
an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal;
Control the
a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches;
a second step of releasing the first and second switches, applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a reference voltage whose voltage changes in proportion to time to the second signal input terminal, and obtaining a first analog-to-digital converted value from time information at the time of generation of a stop signal at the first and second output terminals;
a step of alternately repeating the first step and the second step a plurality of times, or of varying a reference voltage whose voltage varies in proportion to time a plurality of times in the second step, thereby obtaining a plurality of first analog-to-digital conversion values, and temporarily storing an average value of these values in a register as a final first analog-to-digital conversion value;
a third step in which the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, a plurality of analog-to-digital converted values obtained from time information when a stop signal is generated from the first and second output terminals are averaged to obtain a second analog-to-digital converted value, and a difference value between the averaged value and the first analog-to-digital converted value is stored in memory as a third analog-to-digital converted value;
a fourth step of applying a voltage of the common signal line immediately before the second reset to the first signal input terminal, applying a second standard reference signal to the second signal input terminal, and closing the first and second switches;
a fifth step in which the first and second switches are released, a voltage of the common signal line immediately before the second reset is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, and an average value of a plurality of analog-to-digital converted values obtained from time information when a stop signal is generated from the first and second output terminals is temporarily stored in a register as a fourth analog-to-digital converted value;
a sixth step of applying a voltage of the common signal line at the time of the second reset to the first signal input terminal, applying a threshold voltage to the second signal input terminal, and comparing the voltage of the common signal line immediately before the second reset with the output terminal signal;
a seventh step in which, if the comparison signal obtained in the sixth step is small, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, and an average value of a plurality of analog-to-digital converted values obtained from time information when stop signals are generated from the first and second output terminals is temporarily stored in a register as a fifth analog-to-digital converted value, or, if the comparison signal is large, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and an analog-to-digital converted value obtained from time information when stop signals are generated from the first and second output terminals is temporarily stored in a register as a fifth analog-to-digital converted value;
and
an image sensor that sets a difference value between the third analog-to-digital converted value stored in the memory and the fifth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal; A plurality of pixels arranged two-dimensionally in row and column directions;
a vertical scanning circuit for selecting pixels in a specific row;
a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit;
a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter;
and
The pixel is
a photoelectric conversion element that converts an optical signal into an electric current;
a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage;
a reset unit that resets the capacitor to a predetermined voltage;
a voltage buffer unit that receives the voltage of the capacitor as an input;
Equipped with
The analog-to-digital converter
a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals;
a first switch provided between the first input terminal and the first output terminal;
a second switch provided between the second input terminal and the second output terminal;
a first capacitance provided between a first signal input terminal and the first input end;
a second capacitor provided between a second signal input terminal and the second input end;
and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value,
The control unit
a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset;
an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value;
an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and
an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal;
Control the
a first step in which a voltage of the common signal line at the first reset time is applied to the first and second signal input terminals, and the first and second switches are closed;
a second step in which the first and second switches are released, the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of the stop signals at the first and second output terminals is stored in a memory as a first analog-to-digital converted value;
a third step of applying a voltage of the common signal line immediately before the second reset to the first and second signal input terminals, and closing the first and second switches;
a fourth step in which the first and second switches are released, a voltage of the common signal line immediately before reset is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of the stop signal at the first and second output terminals is set as a second analog-to-digital converted value;
a fifth step in which the voltage of the common signal line at the second reset time is applied to the first and second signal input terminals, and the first and second switches are closed;
a sixth step in which the first and second switches are released, a voltage of the common signal line at the time of the second reset is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, time information at the time of generation of the stop signals at the first and second output terminals is set as a third analog-digital converted value, and a difference value between the third analog-digital converted value and the second analog-digital converted value is set as a fourth analog-digital converted value;
and
an image sensor that sets a difference value between the first analog-to-digital converted value stored in the memory and the fourth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal; A plurality of pixels arranged two-dimensionally in row and column directions;
a vertical scanning circuit for selecting pixels in a specific row;
a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit;
a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter;
and
The pixel is
a photoelectric conversion element that converts an optical signal into an electric current;
a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage;
a reset unit that resets the capacitor to a predetermined voltage;
a voltage buffer unit that receives the voltage of the capacitor as an input;
Equipped with
The analog-to-digital converter
a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals;
a first switch provided between the first input terminal and the first output terminal;
a second switch provided between the second input terminal and the second output terminal;
a first capacitance provided between a first signal input terminal and the first input end;
a second capacitor provided between a second signal input terminal and the second input end;
and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value,
The control unit
a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset;
an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value;
an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and
an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal;
Control the
a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches;
a second step in which the first and second switches are released, the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal multiple times, and an average value of multiple analog-to-digital converted values obtained from time information when stop signals are generated from the first and second output terminals is stored in memory as a first analog-to-digital converted value;
a third step of applying a voltage of the common signal line immediately before the second reset to the first and second signal input terminals, and closing the first and second switches;
a fourth step in which the first and second switches are opened, the voltage of the common signal line immediately before resetting is applied to the first signal input terminal, a threshold voltage is applied to the second signal input terminal, and the magnitude of the voltage of the common signal line immediately before resetting is determined based on the output voltage of the differential amplifier obtained;
a fifth step in which, if the magnitude of the voltage of the common signal line immediately before the reset determined in the fourth step is equal to or less than a threshold value, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, and an average value of a plurality of analog-to-digital converted values obtained from time information when a stop signal is generated at the output terminal is temporarily stored in a register as a second analog-to-digital converted value, or, if the magnitude of the voltage of the common signal line immediately before the reset exceeds a threshold value, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and an analog-to-digital converted value obtained from time information when a stop signal is generated at the first and second output terminals is temporarily stored in a register as a second analog-to-digital converted value;
a sixth step of applying the voltage of the common signal line at the second reset time to the first and second signal input terminals and closing the first and second switches;
a seventh step in which the first and second switches are released, a voltage of the common signal line at reset is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal multiple times, the average value of multiple analog-to-digital converted values obtained from time information when a stop signal is generated at the output terminal is set as a third analog-to-digital converted value, and the difference value between the third analog-to-digital converted value and the second analog-to-digital converted value is set as a fourth analog-to-digital converted value;
and
an image sensor that sets a difference value between the first analog-to-digital converted value stored in the memory and the fourth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal; 6. The image sensor according to claim 1, wherein at least one of the reset section and the voltage buffer section is configured with a MOS transistor. 7. The image sensor according to claim 1, wherein the voltage range and/or threshold voltage of the reference voltage is determined based on one or more of an analog-to-digital conversion value of the first reset voltage, an analog-to-digital conversion value of the voltage after the first reset is released, an analog-to-digital conversion value of the second reset voltage, and an analog-to-digital conversion value before the second reset.