JP7735225B2 - Semiconductor Devices - Google Patents

Description

The embodiment relates to a semiconductor device.

Switch circuits are known for use in mobile devices, etc.

U.S. Pat. No. 10,715,133

Providing high-quality semiconductor devices.

An embodiment of a semiconductor device includes an input terminal and an output terminal, and a plurality of transistors connected in series between the input terminal and the output terminal. The plurality of transistors include a first transistor having a first terminal and a second terminal used in the series connection, and a second transistor having a third terminal and a fourth terminal used in the series connection, a first gate, and a first body, the third terminal of the second transistor being connected to the second terminal. The semiconductor device further includes a third transistor and a first diode connected in series between the first body and the first terminal. The third transistor has a second gate connected to the first gate. The anode of the first diode is located on the first body side of the first body and the first terminal, and the cathode of the first diode is located on the first terminal side of the first body and the first terminal.

FIG. 1 is a block diagram showing an example of the configuration of a wireless device including a switch circuit according to a first embodiment. FIG. 2 is a diagram showing an example of a circuit configuration of a switch circuit according to the first embodiment. FIG. 3 is a diagram for explaining the structure of a transistor of the switch circuit according to the first embodiment. 5A and 5B are diagrams for explaining various currents that flow through the switch circuit according to the first embodiment while the switch circuit is in an off state. 4A and 4B are diagrams for explaining the operation of the switch circuit according to the first embodiment when a first high-frequency signal is input to the switch circuit; 5A and 5B are diagrams for explaining the operation of the switch circuit according to the first embodiment when a second high-frequency signal is input to the switch circuit; 5A and 5B are diagrams for explaining the operation of the switch circuit according to the first embodiment when a third high-frequency signal is input to the switch circuit; FIG. 10 is a diagram showing an example of a graph illustrating the relationship between the high-frequency power of a high-frequency signal and the bias voltages of a first terminal and a body of a transistor when the high-frequency signal is input to the switch circuit according to the first embodiment. FIG. 10 is a diagram showing an example of a graph illustrating the relationship between high-frequency power associated with a high-frequency signal and the power of third-order distortion generated due to the influence of a feedback circuit when the high-frequency signal is input to the switch circuit according to the first embodiment. FIG. 4 is a diagram for explaining another example of the circuit configuration of the switch circuit according to the first embodiment. FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a second embodiment. FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a third embodiment. FIG. 11 is a diagram for explaining the operation of the switch circuit according to the third embodiment when a third high-frequency signal is input to the switch circuit. FIG. 10 is a diagram showing an example of a circuit configuration of a switch circuit according to a fourth embodiment. FIG. 13 is a diagram showing an example of a circuit configuration of a switch circuit according to a fifth embodiment. FIG. 13 is a diagram showing an example of a circuit configuration of a switch circuit according to a sixth embodiment.

The following describes the embodiments with reference to the drawings. In the following description, components with the same function and configuration are assigned common reference symbols. When distinguishing between multiple components that share a common reference symbol, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, the multiple components are assigned only the common reference symbol, without a subscript.

Each functional block can be realized by either hardware or software, or a combination of both. Furthermore, it is not necessary for each functional block to be distinguished as described below. For example, some functions may be performed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional block may be further divided into smaller functional sub-blocks. Furthermore, the names of each functional block and each component in the following description are for convenience only and do not limit the configuration or operation of each functional block and each component.

First Embodiment
A semiconductor device according to a first embodiment will be described below. Hereinafter, this semiconductor device will also be referred to as a switch circuit 1.

[Configuration example]
(1) Wireless Device FIG. 1 is a block diagram showing an example of the configuration of a wireless device WD including a switch circuit 1 according to the first embodiment. The wireless device WD is, for example, a smartphone, a feature phone, a mobile terminal (e.g., a tablet terminal), a personal computer, a game console, a router, a base station, or the like. The wireless device WD transmits and receives signals using communication standards such as LTE (registered trademark) (Long Term Evolution) and/or Wi-Fi. Reference numerals 1a, 1b, 1c, 1d, and 1e shown in FIG. 1 will be referred to in the description of the following embodiments.

In addition to switch circuit 1, wireless device WD includes, for example, antenna ANT, switch circuits 2, 3, and 4, signal processing circuits 5 and 6, and control circuit 7.

The antenna ANT receives high-frequency signals from other devices (e.g., base stations or other wireless devices). The antenna ANT can also transmit high-frequency signals from the wireless device WD to other devices.

The control circuit 7 transmits control signals CNT to, for example, switch circuits 1, 2, 3, and 4, and to signal processing circuits 5 and 6. Whether each of switch circuits 1, 2, 3, and 4 is in an on or off state is controlled by the control signal CNT that the switch circuit receives from the control circuit 7. While a switch circuit is in an on state, the switch circuit is capable of transmitting signals between its first and second terminals. On the other hand, while a switch circuit is in an off state, the switch circuit does not transmit signals between its first and second terminals. The signal processing circuits 5 and 6 each process signals based on the control signal CNT that they receive from the control circuit 7.

The first terminal of switch circuit 1 is connected to antenna ANT, and the second terminal of switch circuit 1 is connected to signal processing circuit 5. Switch circuit 1 receives control signal CNT1 from control circuit 7. While switch circuit 1 is in the on state based on control signal CNT1, it transmits, for example, a high-frequency signal received by wireless device WD via antenna ANT to signal processing circuit 5.

The first terminal of the switch circuit 2 is connected to the signal path between the switch circuit 1 and the signal processing circuit 5. The second terminal of the switch circuit 2 is, for example, grounded.

Switch circuit 2 receives a control signal CNT2 from control circuit 7. For example, switch circuit 2 is in the ON state based on the control signal CNT2 while switch circuit 1 is in the OFF state. While in this ON state, switch circuit 2 fixes the potential of the signal path between switch circuit 1 and signal processing circuit 5 to ground potential.

The signal processing circuit 5 receives the high-frequency signal transmitted via the switch circuit 1 and performs various processes on the high-frequency signal based on the control signal CNT3 received from the control circuit 7.

The first terminal of switch circuit 3 is connected to antenna ANT, and the second terminal of switch circuit 3 is connected to signal processing circuit 6. Switch circuit 3 receives, for example, a control signal CNT2 from control circuit 7. While switch circuit 3 is in the on state based on control signal CNT2, it transmits, for example, a high-frequency signal received by wireless device WD via antenna ANT to signal processing circuit 6. The frequency band of the high-frequency signal transmitted by switch circuit 3 is different, for example, from the frequency band of the high-frequency signal transmitted by switch circuit 1. Switch circuit 1 and switch circuit 3 are selectively turned on, for example, under the control of control circuit 7.

The first end of the switch circuit 4 is connected to the signal path between the switch circuit 3 and the signal processing circuit 6. The second end of the switch circuit 4 is, for example, grounded. The switch circuit 4 receives, for example, a control signal CNT1 from the control circuit 7. For example, the switch circuit 4 is in an ON state based on the control signal CNT1 while the switch circuit 3 is in an OFF state. While in this ON state, the switch circuit 4 fixes the potential of the signal path between the switch circuit 3 and the signal processing circuit 6 to ground potential.

The signal processing circuit 6 receives the high-frequency signal transmitted via the switch circuit 3 and performs various processes on the high-frequency signal based on the control signal CNT4 received from the control circuit 7.

In the above, we have described a case where switch circuits 1 and 3 each transmit a high-frequency signal received by wireless device WD from another device. Switch circuits 1 and 3 are not limited to this. Either switch circuit 1 or 3 may transmit a high-frequency signal that wireless device WD transmits to another device.

The following explanation focuses on switch circuit 1.

(2) Switch Circuit Fig. 2 shows an example of the circuit configuration of the switch circuit 1 according to the first embodiment. In Fig. 2, the circuit symbol for each transistor indicates that one end of the transistor is the drain and the other end is the source, but the drain and source may be interchanged depending on the relationship between the potentials of the two ends. Fig. 2 also shows various voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12, and VR23, but these voltages will be mentioned in the description of an operational example described later.

Switch circuit 1 includes n (n is a natural number) transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn. Each of these transistors is a field effect transistor (FET), such as an n-channel metal oxide semiconductor (MOS) transistor. Unless otherwise specified, the same applies to other components referred to as transistors in this specification. In FIG. 2, the first and second ends of switch circuit 1 are shown as terminals IN and OUT, respectively.

Switch circuit 1 further includes resistors Rg1, Rg2, Rg3, Rg4, Rg5, ..., Rg(n-2), Rg(n-1), and Rgn, as well as resistors Rb1, Rb2, Rb3, Rb4, ..., Rb(n-2), Rb(n-1), and Rbn. Switch circuit 1 further includes resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), Rds(3,1), Rds(3,2), Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), ..., Rds(n-2,1), Rds(n-2,2), Rds(n-1,1), Rds(n-1,2), Rds(n,1), and Rds(n,2).

The resistance values of resistors Rds(1,1), Rds(1,2), Rds(2,1), Rds(2,2), Rds(3,1), Rds(3,2), Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), ..., Rds(n-2,1), Rds(n-2,2), Rds(n-1,1), Rds(n-1,2), Rds(n,1), and Rds(n,2) are, for example, substantially the same R1. Below, we will explain the case where the resistance values of these resistors Rds are substantially the same.

Transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn are connected in series between terminal IN and terminal OUT. More specifically, the first terminal of transistor M1 is connected to terminal IN, and the first terminal of transistor M2 is connected to the second terminal of transistor M1. The first terminal of transistor M3 is connected to the second terminal of transistor M2, and the first terminal of transistor M4 is connected to the second terminal of transistor M3. The same applies to the connection relationships of transistors M4, M5, ..., M(n-2), M(n-1), and Mn, with terminal OUT connected to the second terminal of transistor Mn.

Resistor Rg1 is connected between the gate of transistor M1 (hereinafter also referred to as the control terminal) and the gate of transistor M2. Resistor Rg2 is connected between the gate of transistor M2 and the gate of transistor M3. Resistor Rg3 is connected between the gate of transistor M3 and the gate of transistor M4. The same applies to resistors Rg4, Rg5, ..., Rg(n-2), and Rg(n-1). One end of resistor Rgn is also connected to the gate of transistor Mn. The other end of resistor Rgn is connected to a node to which signal GB is input. Figure 2 shows the control terminal to which signal GB is input to switch circuit 1. Signal GB is, for example, the control signal CNT1 described with reference to Figure 1. Signal GB can be changed between high (H) and low (L) levels, for example, by control circuit 7. In this specification, when the term "level" is used, it refers to a voltage level unless otherwise specified.

Resistor Rb1 is connected between the body of transistor M1 (hereinafter also referred to as the back gate) and the body of transistor M2. Resistor Rb2 is connected between the body of transistor M2 and the body of transistor M3. Resistor Rb3 is connected between the body of transistor M3 and the body of transistor M4. The same applies to resistors Rb4, ..., Rb(n-2), Rb(n-1). One end of resistor Rbn is also connected to the body of transistor Mn. The other end of resistor Rbn is connected to a node to which signal BB is input. Figure 2 also shows a control terminal to which signal BB is input to switch circuit 1. Signal BB is supplied, for example, by control circuit 7. The voltage of signal BB is set, for example, according to the voltage of signal GB.

One end of resistor Rds(1,1) is connected to a first end of transistor M1, one end of resistor Rds(1,2) is connected to the other end of resistor Rds(1,1), and a second end of transistor M1 is connected to the other end of resistor Rds(1,2). One end of resistor Rds(2,1) is connected to a first end of transistor M2, one end of resistor Rds(2,2) is connected to the other end of resistor Rds(2,1), and a second end of transistor M2 is connected to the other end of resistor Rds(2,2). One end of resistor Rds(3,1) is connected to a first end of transistor M3, one end of resistor Rds(3,2) is connected to the other end of resistor Rds(3,1), and a second end of transistor M3 is connected to the other end of resistor Rds(3,2). The same applies to resistors Rds(4,1), Rds(4,2), Rds(5,1), Rds(5,2), ..., Rds(n-2,1), Rds(n-2,2), Rds(n-1,1), Rds(n-1,2), Rds(n,1), and Rds(n,2).

Note that resistors Rg, Rb, and Rds are each formed using, for example, polysilicon.

The switch circuit 1 further includes, as components of the feedback circuit, transistors Tr(1,3), Tr(1,4), Tr(2,1), Tr(2,2), Tr(2,3), Tr(2,4), Tr(3,1), Tr(3,2), Tr(3,3), Tr(3,4), Tr(4,1), Tr(4,2), Tr(4,3), Tr(4,4), Tr(5,1), Tr(5,2), Tr(5,3), Tr(5,4), ..., Tr(n-2,1), Tr(n-2,2), Tr(n-2,3), Tr(n-2,4), Tr(n-1,1), Tr(n-1,2), Tr(n-1,3), Tr(n-1,4), Tr(n,1), and Tr(n,2).

Transistors Tr(1,3) and Tr(1,4) are associated with transistor M1.

The first terminal of transistor Tr(1,3) is connected to the body of transistor M1, and the gate of transistor Tr(1,3) is connected to the gate of transistor M1. The second terminal of transistor Tr(1,3) is connected to the first terminal of transistor Tr(1,4) and the gate of transistor Tr(1,4). Thus, the diode-connected transistor Tr(1,4) is connected to the second terminal of transistor Tr(1,3). The second terminal of transistor Tr(1,4) is connected to the node connecting resistors Rds(2,1) and Rds(2,2).

The following explanation holds for each case where the integer k is from 2 to n-1.
Transistors Tr(k,1), Tr(k,2), Tr(k,3), and Tr(k,4) are associated with transistor Mk.

The first terminal of transistor Tr(k,1) is connected to the body of transistor Mk, and the gate of transistor Tr(k,1) is connected to the gate of transistor Mk. The second terminal of transistor Tr(k,1) is connected to the first terminal of transistor Tr(k,2) and the gate of transistor Tr(k,2). Thus, the diode-connected transistor Tr(k,2) is connected to the second terminal of transistor Tr(k,1). The second terminal of transistor Tr(k,2) is connected to the node connecting resistors Rds(k-1,1) and Rds(k-1,2).

The first terminal of transistor Tr(k,3) is connected to the body of transistor Mk, and the gate of transistor Tr(k,3) is connected to the gate of transistor Mk. The second terminal of transistor Tr(k,3) is connected to the first terminal of transistor Tr(k,4) and the gate of transistor Tr(k,4). Thus, the diode-connected transistor Tr(k,4) is connected to the second terminal of transistor Tr(k,3). The second terminal of transistor Tr(k,4) is connected to the node connecting resistors Rds(k+1,1) and Rds(k+1,2).

Transistors Tr(n,1) and Tr(n,2) are associated with transistor Mn.

The first terminal of transistor Tr(n,1) is connected to the body of transistor Mn, and the gate of transistor Tr(n,1) is connected to the gate of transistor Mn. The second terminal of transistor Tr(n,1) is connected to the first terminal of transistor Tr(n,2) and the gate of transistor Tr(n,2). Thus, the diode-connected transistor Tr(n,2) is connected to the second terminal of transistor Tr(n,1). The second terminal of transistor Tr(n,2) is connected to the node connecting resistors Rds(n-1,1) and Rds(n-1,2).

While signal GB is at H level, transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn are each in the ON state, i.e., switch circuit 1 is in the ON state.

While signal GB is at an L level, transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn are each in the OFF state; that is, switch circuit 1 is in the OFF state. While switch circuit 1 is in the OFF state, due to the connection relationship of resistor Rds described above, a divided voltage of the voltage applied between terminal IN and terminal OUT is applied to transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn, respectively. The voltages applied to transistors M1, M2, M3, M4, M5, ..., M(n-2), M(n-1), and Mn are substantially the same.

When the potential (hereinafter also referred to as the voltage) of the body of transistor M2 is higher than the voltage at the second end of transistor Tr(2,2), current flows from the body through transistors Tr(2,1) and Tr(2,2) while transistors Tr(2,1) and Tr(2,2) are in the on state. When current flows in this manner, the voltage of the body drops. Whether transistor Tr(2,1) is in the on state or off state depends on the voltage at the gate of transistor M2. This is because the gate of transistor Tr(2,1) is connected to the gate of transistor M2.

If the voltage of the body of transistor M2 is higher than the voltage at the second end of transistor Tr(2,4), current flows from the body through transistors Tr(2,3) and Tr(2,4) while transistors Tr(2,3) and Tr(2,4) are in the on state. Even when current flows in this way, the voltage of the body drops. Whether transistor Tr(2,3) is in the on state or off state depends on the voltage at the gate of transistor M2. This is because the gate of transistor Tr(2,3) is connected to the gate of transistor M2.

The above explanation relates to transistors Tr(2,1), Tr(2,2), Tr(2,3), and Tr(2,4) associated with transistor M2. Similar explanations apply to each of the other transistors M in relation to the various transistors Tr associated with that transistor M.

In the above description, for example, the second end of transistor Tr(2,2) was described as being connected to the node connecting resistors Rds(1,1) and Rds(1,2). In this connection relationship, if the resistance value of resistor Rds(1,1) is extremely small, for example, it can also be interpreted that the second end of transistor Tr(2,2) is connected to the first end of transistor M1 without going through a resistive element. If the resistance value of resistor Rds(1,1) is extremely small, for example, the resistance value of resistor Rds(1,2) will differ from the resistance value of resistor Rds(1,1). The same applies to the other transistors Tr described as being connected in a similar manner.

In the above description, for example, a path from the body of transistor M2 to the first end of transistor M1 is described as including transistor Tr(2,1), whose gate is connected to the gate of transistor M2, and diode-connected transistor Tr(2,2), in the order of transistor Tr(2,1), transistor Tr(2,2). However, this embodiment is not limited to this. Transistors Tr(2,1) and Tr(2,2) may also be provided in the reverse order on the path from the body of transistor M2 to the first end of transistor M1. The same applies to the other transistors Tr described as being connected in a similar manner.

In the above, diode-connected transistors such as transistors Tr(1,4), Tr(2,2), Tr(2,4), Tr(3,2), Tr(3,4), ..., Tr(n-1,2), Tr(n-1,4), and Tr(n,2) have been described as components of switch circuit 1. In switch circuit 1, diodes formed by PN junctions may be used instead of such transistors Tr. The same applies to the other diode-connected transistors described in this specification. When simply referring to a "diode" in this specification, it is intended that either a diode-connected transistor or a diode formed by a PN junction may be used as the diode. In either case, the electrodes of the diode are referred to as the anode and cathode in this specification.

Figure 3 is a diagram illustrating the structure of transistor M2 of switch circuit 1 according to the first embodiment. Figure 3 illustrates a portion of the cross-sectional structure of switch circuit 1. The structure of transistor M2 will be described below as an example, but other transistors M may also have a similar structure to that described below. As an example, a case will be described in which switch circuit 1 is provided on an SOI (Silicon On Insulator) substrate.

An oxide film BOX is provided on the upper surface of the semiconductor substrate SB. A semiconductor layer is provided on the upper surface of the oxide film BOX as a body layer BD. The body layer BD is used as a p ⁺ impurity diffusion layer by being doped with, for example, boron (B). A source region SR and a drain region DR are provided on the surface of the body layer BD with a gap therebetween. The source region SR and the drain region DR are each used as an n ⁺ impurity diffusion region by being doped with, for example, phosphorus (P). A gate electrode G is provided on the upper surface of the body layer BD between the source region SR and the drain region DR via a gate insulator GI. The transistor M2 includes the source region SR, the drain region DR, and the gate electrode G.

Connections between the gate of transistor M2 and other components are formed via contact plugs (not shown) provided on the upper surface of gate electrode G. Similarly, connections between the first end of transistor M2 and other components, and connections between the second end of transistor M2 and other components are formed via contact plugs (not shown) provided on the upper surfaces of drain region DR and source region SR, respectively.

For example, if the voltage of the drain region DR is higher than the voltage of the body layer BD, leakage current Ib may flow from the drain region DR to the body layer BD. Similarly, if the voltage of the source region SR is higher than the voltage of the body layer BD, leakage current Ib may flow from the source region SR to the body layer BD.

When such a leakage current Ib occurs, the voltage of the body of transistor M2 may rise. This voltage rise is suppressed by the current flowing through the various transistors Tr associated with transistor M2 as described above.

[Example of operation]
An example of the operation of the switch circuit 1 according to the first embodiment while the switch circuit 1 is in the OFF state will be described below.

(1) Overview of Operation of Switch Circuit 1 Fig. 4 is a diagram for explaining various currents that flow through the switch circuit 1 according to the first embodiment while the switch circuit 1 is in an off state. For simplicity of explanation, Fig. 4 shows the circuit configuration of the switch circuit 1 when n is 3. The following description will be given for the case where n is 3.

When a high-frequency signal is input to terminal IN, the leakage current Ib described with reference to Figure 3 may occur in each of transistors M1, M2, and M3.

Such leakage current Ib can increase the bias potential (hereinafter also referred to as the bias voltage) of the bodies of transistors M1, M2, and M3. More specifically, this is as follows:

This leakage current Ib can affect the current flowing through resistors Rb1, Rb2, and Rb3. Figure 4 shows, as an example, how this leakage current Ib contributes to current flowing from the body of transistor M1 through resistor Rb1, contributes to current flowing from the body of transistor M2 through resistor Rb2, and contributes to current flowing from the body of transistor M3 through resistor Rb3. This changes the amount of voltage drop across the various resistors Rb. The amount of increase in the bias voltage of the bodies of transistors M1, M2, and M3 described above corresponds to the amount of this change.

Furthermore, this leakage current Ib can cause the bias voltages at the second terminal of transistor M1, the first and second terminals of transistor M2, and the first terminal of transistor M3 to drop. More specifically, this is as follows:

This leakage current Ib can contribute to current flowing from terminal IN through resistors Rds(1,1) and Rds(1,2) to the node connecting the second terminal of transistor M1 and the first terminal of transistor M2. This leakage current Ib can contribute to current flowing from terminal OUT through resistors Rds(3,2) and Rds(3,1) to the node connecting the second terminal of transistor M2 and the first terminal of transistor M3. This changes the amount of voltage drop across the various resistors Rds. The amount of bias voltage drop at the second terminal of transistor M1, the first and second terminals of transistor M2, and the first terminal of transistor M3 corresponds to the amount of this change.

The above describes the case where n is 3, but a similar explanation also applies when n is an integer other than 3. That is, the leakage current Ib generated in each transistor M may increase the bias voltage of the body of each transistor M, and may decrease the bias voltage of each first terminal and/or second terminal of each transistor M.

In switch circuit 1, the following currents can also flow through the feedback circuit. The following describes the currents flowing through transistors Tr(2,1), Tr(2,2), Tr(2,3), and Tr(2,4) associated with transistor M2. Similar descriptions apply to each of the other transistors M in relation to the various transistors Tr associated with that transistor M.

When the voltage of the body of transistor M2 is higher than the voltage of the second terminal of transistor Tr(2,2), the following occurs: While transistors Tr(2,1) and Tr(2,2) are in the on state, current flows from the body to the second terminal. This current contributes to current flow from the second terminal through resistor Rds(1,1) to the node connecting resistor Rds(1,1) and the first terminal of transistor M1.

When the voltage of the body of transistor M2 is higher than the voltage of the second terminal of transistor Tr(2,4), the following occurs: While transistors Tr(2,3) and Tr(2,4) are in the on state, current flows from the body to the second terminal. This current contributes to current flow from the second terminal through resistor Rds(3,2) to the node connecting resistor Rds(3,2) and the second terminal of transistor M3.

The above describes the case where n is 3, but a similar explanation also applies when n is an integer other than 3. As a result of current flowing from the body of each transistor M via the feedback circuit as described above, the bias voltage of the body of each transistor M is lowered so as to suppress the above-mentioned increase, and the bias voltage of each of the first terminal and/or second terminal of each transistor M is raised so as to suppress the above-mentioned decrease.

In relation to this operation, the following provides a more detailed explanation of an example of the operation of switch circuit 1 when various high-frequency signals are input to terminal IN. As with the explanation of Figure 4, the following explanation focuses on transistor M2 of the series-connected transistors M1, M2, M3, ..., and Mn.

The following explanation will refer to the various voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12, and VR23 shown in Figure 2. The explanation will also be given assuming that a bias voltage of 0 volts (V) is applied to terminals IN and OUT.

Voltage VM01 is the voltage at the first end of transistor M1. Voltage VM12 is the voltage at the second end of transistor M1 and the voltage at the first end of transistor M2. Voltage VM23 is the voltage at the second end of transistor M2 and the voltage at the first end of transistor M3. Voltage VM34 is the voltage at the second end of transistor M3 and the voltage at the first end of transistor M4. Voltage VG2 is the voltage at the gate of transistor M2. Voltage VB2 is the voltage at the body of transistor M2. Voltage VR12 is the voltage at the node connecting the second end of transistor Tr(2,2) with resistors Rds(1,1) and Rds(1,2). Voltage VR23 is the voltage at the node connecting the second end of transistor Tr(2,4) with resistors Rds(3,1) and Rds(3,2).

(2) First Operation Example of Switch Circuit 1 FIG. 5 is a diagram for explaining the operation of the switch circuit 1 when a first high-frequency signal is input to the switch circuit 1 according to the first embodiment.

Figure 5 shows an example of the waveforms of voltages VM12, VM23, VG2, VB2, VR12, and VR23 when a first high-frequency signal is input to terminal IN. The horizontal axis represents time. The vertical axis represents voltage values. For ease of reference, the voltage values shown are the potential difference values with respect to voltage VM23 at the second end of transistor M2. The various voltage values and signal waveforms mentioned in the following description are thus based on voltage VM23. Furthermore, the voltage values mentioned in the following description are merely examples for the sake of simplicity. The same applies to similar drawings mentioned in the following description.

When a first high-frequency signal is input to terminal IN, as a result of the voltage division due to the connection relationship of resistor Rds described above, in the example of Figure 5, the voltage signal applied between the first and second terminals of each transistor M becomes a high-frequency signal with an amplitude of 2V. At this time, the voltage VM12 signal is a high-frequency signal with an amplitude of 2V. Furthermore, the voltage VR12 signal is a high-frequency signal with an amplitude of 3V, and the voltage VR23 signal is a high-frequency signal with an amplitude of 1V. These are based on the voltage division by resistors Rds(1,1) and Rds(1,2) and the voltage division by resistors Rds(3,1) and Rds(3,2), respectively. The voltage VR12 signal is substantially in phase with the voltage VM12 signal, and the voltage VR23 signal is substantially out of phase with the voltage VM12 signal.

In the example of Figure 5, the L level voltage of signal GB is -3V. Therefore, the voltage VG2 signal is a bias voltage signal of -3V superimposed with a high-frequency signal of 1V amplitude. The voltage VG2 signal is substantially in phase with the voltage VM12 signal. These are due to the parasitic capacitances that occur, for example, between the gate and the first terminal of transistor M2 and between the gate and the second terminal of transistor M2.

In the example of Figure 5, the voltage of signal BB is also -3V. Therefore, the voltage VB2 signal is a bias voltage of -3V superimposed on a high-frequency signal with an amplitude of 1V. The voltage VB2 signal is substantially in phase with the voltage VM12 signal. These are due to, for example, the parasitic capacitances occurring between the body and the first terminal of transistor M2, and between the body and the second terminal of transistor M2.

Whether or not current flows out of the body of transistor M2 via transistors Tr(2,1) and Tr(2,2) associated with transistor M2 depends on, for example, voltages VB2, VR12, and VG2. Whether or not current flows out of the body of transistor M2 via transistors Tr(2,3) and Tr(2,4) associated with transistor M2 depends on, for example, voltages VB2, VR23, and VG2.

We will explain whether such a current flows out of the body at times T00 and T01. Time T00 is the time when the value of voltage VM12 reaches a maximum, and time T01 is the time when the value of voltage VM12 reaches a minimum.

At time T00, voltages VB2 and VG2 are -2 V, voltage VR12 is 3 V, and voltage VR23 is -1 V. At this time, because voltage VB2 is lower than voltage VR23, no current flows out of the body via transistors Tr(2,3) and Tr(2,4). Similarly, no current flows out of the body via transistors Tr(2,1) and Tr(2,2).

At time T01, voltages VB2 and VG2 are -4 V, voltage VR12 is -3 V, and voltage VR23 is 1 V. At this time, because voltage VB2 is lower than voltage VR12, no current flows out of the body via transistors Tr(2,1) and Tr(2,2). Similarly, no current flows out of the body via transistors Tr(2,3) and Tr(2,4).

Thus, in the example of Figure 5, voltage VB2 is lower than voltage VR23 and voltage VR12, and therefore no current flows out of the body.

(3) Second Operation Example of Switch Circuit 1 Fig. 6 is a diagram for explaining the operation of the switch circuit 1 according to the first embodiment when a second high-frequency signal is input to the switch circuit 1. Fig. 6 shows an example of the waveforms of the voltages VM12, VM23, VG2, VB2, VR12, and VR23 when a second high-frequency signal is input to the terminal IN. The horizontal axis represents time. The vertical axis represents the voltage value.

When a second high-frequency signal is input to terminal IN, as a result of voltage division due to the connection relationship of resistor Rds described above, in the example of Figure 6, the voltage signal applied between the first and second terminals of each transistor M becomes a high-frequency signal with an amplitude of 3V. At this time, the voltage VM12 signal is a high-frequency signal with an amplitude of 3V, the voltage VR12 signal is a high-frequency signal with an amplitude of 4.5V, and the voltage VR23 signal is a high-frequency signal with an amplitude of 1.5V. The voltage VR12 signal is substantially in phase with the voltage VM12 signal, and the voltage VR23 signal is substantially out of phase with the voltage VM12 signal.

In the example of Figure 6, the L level voltage of signal GB is -3V. Therefore, the voltage VG2 signal is a bias voltage signal of -3V superimposed with a high-frequency signal of 1.5V amplitude. The voltage VG2 signal is substantially in phase with the voltage VM12 signal.

The amplitude of the second high-frequency signal is greater than the amplitude of the first high-frequency signal, and in the example of FIG. 6, a leakage current Ib occurs in transistor M2. This leakage current Ib increases the bias voltage of the body of transistor M2, as described with reference to FIG. 4. Therefore, while the voltage of signal BB is also -3V, the voltage VB2 signal is a bias voltage signal of -2V increased from -3V, with a high-frequency signal of 1.5V amplitude superimposed on it. The voltage VB2 signal is substantially in phase with the voltage VM12 signal. Note that, for the sake of simplicity, in the example of FIG. 6, it is assumed that there is no voltage drop at the second terminal of transistor M1, the first and second terminals of transistor M2, and the first terminal of transistor M3, as described with reference to FIG. 4.

At times T10 and T11, we will explain whether current flows out of the body of transistor M2 through transistors Tr(2,1) and Tr(2,2) or through transistors Tr(2,3) and Tr(2,4). Time T10 is the time when the value of voltage VM12 reaches a maximum, and time T11 is the time when the value of voltage VM12 reaches a minimum.

At time T10, voltage VB2 is -0.5V, voltage VG2 is -1.5V, voltage VR12 is 4.5V, and voltage VR23 is -1.5V. At this time, voltage VB2 is higher than voltage VR23, but no current flows out of the body via transistors Tr(2,3) and Tr(2,4). This is because voltage VG2 is not high enough to turn on transistor Tr(2,3), so transistor Tr(2,3) is in the off state. Also, as in the example of Figure 5, voltage VB2 is lower than voltage VR12, so no current flows out of the body via transistors Tr(2,1) and Tr(2,2).

At time T11, voltage VB2 is -3.5V, voltage VG2 is -4.5V, voltage VR12 is -4.5V, and voltage VR23 is 1.5V. At this time, voltage VB2 is higher than voltage VR12, but no current flows out of the body via transistors Tr(2,1) and Tr(2,2). This is because voltage VG2 is not high enough to turn on transistor Tr(2,1), so transistor Tr(2,1) is in the off state. Also, as in the example of Figure 5, voltage VB2 is lower than voltage VR23, so no current flows out of the body via transistors Tr(2,3) and Tr(2,4).

As such, in the example of Figure 6, even if voltage VB2 is higher than voltage VR23, transistor Tr(2,3) is in the off state, and even if voltage VB2 is higher than voltage VR12, transistor Tr(2,1) is in the off state. Therefore, no current flows out of the body.

(4) Third Operation Example of Switch Circuit 1 Fig. 7 is a diagram for explaining the operation of the switch circuit 1 according to the first embodiment when a third high-frequency signal is input to the switch circuit 1. Fig. 7 shows an example of the waveforms of the voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12, and VR23 when a third high-frequency signal is input to the terminal IN. The horizontal axis represents time. The vertical axis represents the voltage value.

When a third high-frequency signal is input to terminal IN, as a result of voltage division due to the connection relationship of resistor Rds described above, in the example of Figure 7, the voltage signal applied between the first and second terminals of each transistor M becomes a high-frequency signal with an amplitude of 4V. In this case, the voltage VM01 signal is a high-frequency signal with an amplitude of 8V, the voltage VM12 signal is a high-frequency signal with an amplitude of 4V, the voltage VM34 signal is a high-frequency signal with an amplitude of 4V, the voltage VR12 signal is a high-frequency signal with an amplitude of 6V, and the voltage VR23 signal is a high-frequency signal with an amplitude of 2V. The voltage VM01 signal, voltage VM12 signal, and voltage VR12 signal are substantially in phase. The voltage VM34 signal and voltage VR23 signal are substantially out of phase with the voltage VM12 signal.

In the example of Figure 7, the L level voltage of signal GB is -3V. Therefore, the voltage VG2 signal is a bias voltage signal of -3V superimposed with a high-frequency signal of 2V amplitude. The voltage VG2 signal is substantially in phase with the voltage VM12 signal.

In the example of Figure 7, the voltage of signal BB is also -3V. Therefore, the voltage VB2 signal is a bias voltage of -3V superimposed on a high-frequency signal with an amplitude of 2V. The voltage VB2 signal is substantially in phase with the voltage VM12 signal.

At times T20 and T21, we will explain whether current flows out of the body of transistor M2 through transistors Tr(2,1) and Tr(2,2) or through transistors Tr(2,3) and Tr(2,4). Time T20 is the time when the value of voltage VM12 reaches a maximum, and time T21 is the time when the value of voltage VM12 reaches a minimum.

At time T20, voltages VB2 and VG2 are -1 V, voltage VR12 is 6 V, and voltage VR23 is -2 V. At this time, voltage VB2 is higher than voltage VR23, and voltage VG2 is high enough to turn on transistor Tr(2,3). Therefore, transistors Tr(2,3) and Tr(2,4) are on, and current flows out of the body through transistors Tr(2,3) and Tr(2,4). This current flows from the second terminal of transistor Tr(2,4) to the node connecting the second terminal of transistor M3 and the first terminal of transistor M4. This is because voltage VR23 is higher than voltage VM34. This current flow leads to a decrease in the bias voltage of the body. On the other hand, as in the example of Figure 5, because voltage VB2 is lower than voltage VR12, no current flows out of the body via transistors Tr(2,1) and Tr(2,2).

At time T21, voltages VB2 and VG2 are -5V, voltage VR12 is -6V, and voltage VR23 is 2V. At this time, voltage VB2 is higher than voltage VR12, and voltage VG2 is high enough to turn on transistor Tr(2,1). Therefore, transistors Tr(2,1) and Tr(2,2) are on, and current flows out of the body through transistors Tr(2,1) and Tr(2,2). This current flows from the second terminal of transistor Tr(2,2) to the node connecting the second terminal and the first terminal of transistor M1. This is because voltage VR12 is higher than voltage VM01. This current flow leads to a decrease in the bias voltage of the body. On the other hand, as in the example of Figure 5, because voltage VB2 is lower than voltage VR23, no current flows out of the body via transistors Tr(2,3) and Tr(2,4).

The amplitude of the third high-frequency signal is greater than the amplitude of the second high-frequency signal, and therefore, in the example of Figure 7 as well, a leakage current Ib occurs in transistor M2. This leakage current Ib can cause the bias voltage of the body of transistor M2 to increase. However, as described above, current flows from the body via transistors Tr(2,1) and Tr(2,2), and also flows from the body via transistors Tr(2,3) and Tr(2,4). This current flow suppresses the increase in the bias voltage of the body of transistor M2. Therefore, in the example of Figure 7, unlike the example of Figure 6, no increase in bias voltage is observed in the signal of voltage VB2.

(5) Relationship between High-Frequency Power Associated with Input High-Frequency Signal and Various Bias Voltages FIG. 8 shows an example of a graph illustrating the relationship between the high-frequency power P in associated with a high-frequency signal and the bias voltages at the first end and the body of the transistor M2 when the high-frequency signal is input to the switch circuit 1 according to the first embodiment.

The graph shown in Figure 8(a) shows the relationship between the high-frequency power Pin and the bias voltage VM12bias at the first end of transistor M2. The horizontal axis represents the value of the high-frequency power Pin. The vertical axis represents the value of the bias voltage VM12bias.

As explained with reference to Figures 4, 5, and 6, as the radio frequency power Pin increases, a leakage current Ib occurs in transistor M2, causing the bias voltage VM12bias to decrease. As explained with reference to Figure 7, when the radio frequency power Pin increases further, current flows from the body of transistor M2 to the node connecting the first end of transistor M1 and terminal IN, and current flows from the body to the node connecting the second end of transistor M3 and the first end of transistor M4. Similarly, current also flows through the first and second ends of transistor M2. As current flows in this way from the bodies of each transistor M, the bias voltage VM12bias increases so as to suppress the above-mentioned decrease.

The graph shown in Figure 8(b) shows the relationship between the high-frequency power Pin and the bias voltage VB2bias of the body of transistor M2. The horizontal axis represents the value of the high-frequency power Pin. The vertical axis represents the value of the bias voltage VB2bias.

As explained with reference to Figures 4, 5, and 6, as the radio frequency power Pin increases, a leakage current Ib occurs in transistor M2, causing the bias voltage VB2bias to rise. As explained with reference to Figure 7, when the radio frequency power Pin increases further, current flows out of the body of transistor M2. This causes the bias voltage VB2bias to fall so that the increase is suppressed.

[effect]
The operation of the switch circuit 1 according to the first embodiment will be described while the circuit is in the off state. As the high-frequency power associated with the high-frequency signal input to the terminal IN increases, a leakage current Ib may flow from the drain or source of each transistor M to the body.

For example, when leakage current Ib occurs in transistor M2, as explained with reference to FIG. 4, the bias voltage of the body of transistor M2 may increase, and the bias voltages of the first and second terminals of transistor M2 may decrease. As a result, when the potential difference between the body and drain of transistor M2 decreases, the parasitic bipolar transistor between the drain and source of transistor M2 becomes more likely to turn on. When the parasitic bipolar transistor of a certain transistor M turns on, the voltage applied to each of the other transistors M increases, i.e., the breakdown voltage of switch circuit 1 decreases.

As described with reference to FIG. 2, the switch circuit 1 includes, as components of the feedback circuit, various transistors Tr associated with each transistor M. The various transistors Tr associated with transistor M2 will now be described. Transistors Tr(2,1) and Tr(2,2) are connected in series between the body of transistor M2 and the first terminal of transistor M1. Transistors Tr(2,3) and Tr(2,4) are connected in series between the body of transistor M2 and the second terminal of transistor M3. As described with reference to FIGS. 4 and 7, current can flow from the body of transistors Tr(2,1) and Tr(2,2) to the node connecting the first terminal of transistor M1 and terminal IN, and current can flow from the body of transistors Tr(2,3) and Tr(2,4) to the node connecting the second terminal of transistor M3 and the first terminal of transistor M4. The same applies to the other transistors M.

By allowing current to flow in this manner (hereinafter, this may also be referred to as the feedback circuit operating), even if a leakage current Ib occurs in a certain transistor M, an increase in the bias voltage of the body of that transistor M is suppressed, and a decrease in the bias voltage at the first terminal and/or second terminal of that transistor M is suppressed. Therefore, the switch circuit 1 according to the first embodiment prevents a decrease in the breakdown voltage of the switch circuit 1 due to the leakage current Ib generated in the transistor M.

In the example of Figure 6, at time T10, the body voltage VB2 of transistor M2 is higher than voltage VR23, but transistor Tr(2,3) is in the off state. This is because the gate voltage VG2 of transistor M2, which is connected to the gate of transistor Tr(2,3), is not high enough to turn transistor Tr(2,3) on. Similarly, in the example of Figure 6, at time T11, the body voltage VB2 of transistor M2 is higher than voltage VR12, but transistor Tr(2,1) is in the off state.

In the example of FIG. 6, even if a second high-frequency signal is input to terminal IN and a leakage current Ib occurs, the bias voltage of the body of each transistor M does not increase enough to turn on the parasitic bipolar transistor of that transistor M, and the bias voltages at the first and second terminals of that transistor M do not decrease enough. In the switch circuit 1 according to the first embodiment, the feedback circuit does not operate even if such a high-frequency signal is input to terminal IN.

Consider a case in which, in the switch circuit 1 according to the first embodiment, the gates of transistors Tr(2,1) and Tr(2,3) are each connected to the body of transistor M2 rather than to the gate of transistor M2. That is, consider a case in which diode-connected transistors Tr(2,1) and Tr(2,3) are connected to the body of transistor M2. When various voltages are the same as those at time T10, voltage VB2 is sufficiently higher than voltage VR23, so current flows from the body via transistors Tr(2,3) and Tr(2,4) to the node connecting the second end of transistor M3 and the first end of transistor M4. When various voltages are the same as those at time T11, voltage VB2 is sufficiently higher than voltage VR12, so current flows from the body via transistors Tr(2,1) and Tr(2,2) to the node connecting the first end of transistor M1 and terminal IN. In this way, in a switch circuit in which only a diode is used as a component of the feedback circuit (hereinafter referred to as a switch circuit according to a comparative example), the feedback circuit may operate even when a high-frequency signal of a level that would not cause the feedback circuit to operate is input to terminal IN in switch circuit 1.

Figure 9 shows an example of a graph illustrating the relationship between the high-frequency power Pin associated with a high-frequency signal and the power Phd3 of third-order distortion generated by the influence of the feedback circuit when the high-frequency signal is input to the switch circuit 1 according to the first embodiment. The horizontal axis represents the value of the high-frequency power Pin. The vertical axis represents the value of the power Phd3. In this graph, values expressed in units of decibel milliwatts (dBmW) (hereinafter referred to as dBm) are plotted for both the high-frequency power Pin and the power Phd3. Figure 9 also shows a similar graph for a switch circuit according to a comparative example.

When the feedback circuit operates, current flows out of the body of each transistor M, degrading the linearity of the switch circuit 1. This can increase the third-order distortion power Phd3 generated in the switch circuit 1. As described above, in the switch circuit according to the comparative example, the feedback circuit operates while the amplitude of the high-frequency signal input to terminal IN is small, compared to the switch circuit 1 according to the first embodiment. Therefore, in the switch circuit according to the comparative example, the third-order distortion power Phd3 begins to increase while the high-frequency power Pin is still small, compared to the switch circuit 1 according to the first embodiment, resulting in a larger power Phd3. In the switch circuit 1 according to the first embodiment, the power Phd3 begins to increase only after the high-frequency power Pin becomes large enough to activate the feedback circuit, as in the example of FIG. 7. In FIG. 9, as the power Pin increases further, the power Phd in the first embodiment is shown to be larger than in the comparative example. However, such a power Pin is not actually used because it is large enough to destroy the switch circuit 1, for example.

In this way, in the switch circuit 1 according to the first embodiment, even if a leakage current occurs in each transistor M, the feedback circuit does not operate if the parasitic bipolar transistor of each transistor M does not turn on. As a result, the switch circuit 1 according to the first embodiment can prevent a decrease in the withstand voltage of the switch circuit 1 and suppress degradation of linearity due to the influence of the feedback circuit.

[Modification]
The configuration of the feedback circuit of the switch circuit 1 according to the first embodiment is not limited to that shown in FIG.

Figure 10 is a diagram illustrating another example of the circuit configuration of the switch circuit 1 according to the first embodiment. The following description will focus on transistors Tr(3,3) and Tr(3,4), which are associated with transistor M3, among the various transistors Tr constituting the feedback circuit described with reference to Figure 2. Figure 10 shows three examples in which the switch circuit 1 includes other transistors Tr associated with transistor M3 as components of the feedback circuit. Similar descriptions apply to the other various transistors Tr described with reference to Figure 2.

As shown in FIG. 10(a), the switch circuit 1 may further include a transistor Tr(3,5) associated with transistor M3 as a component of the feedback circuit.

Transistor Tr(3,5) is connected between transistor Tr(3,4) and the node connecting resistors Rds(4,1) and Rds(4,2). More specifically, the second terminal of transistor Tr(3,4) is connected to the first terminal of transistor Tr(3,5) and the gate of transistor Tr(3,5). Thus, diode-connected transistor Tr(3,5) is connected to the second terminal of transistor Tr(3,4). The second terminal of transistor Tr(3,5) is connected to the node connecting resistors Rds(4,1) and Rds(4,2).

As shown in (b) of Figure 10, the switch circuit 1 may further include a transistor Tr(3,6) associated with transistor M3 as a component of the feedback circuit.

Transistor Tr(3,6) is connected between transistor Tr(3,4) and the node connecting resistors Rds(4,1) and Rds(4,2). More specifically, the first terminal of transistor Tr(3,6) is connected to the second terminal of transistor Tr(3,4), and the gate of transistor Tr(3,6) is connected to the gate of transistor Tr(3,4). The second terminal of transistor Tr(3,6) is connected to the node connecting resistors Rds(4,1) and Rds(4,2).

As shown in (c) of Figure 10, the switch circuit 1 may further include a transistor Tr(3,7) associated with transistor M3 as a component of the feedback circuit.

Transistor Tr(3,7) is connected between transistor Tr(3,3) and transistor Tr(3,4). More specifically, the first terminal of transistor Tr(3,7) is connected to the second terminal of transistor Tr(3,3), and the gate of transistor Tr(3,7) is connected to the gate of transistor M3. The second terminal of transistor Tr(3,7) is connected to the first terminal of transistor Tr(3,4) and the gate of transistor Tr(3,4).

The above shows three examples in which three transistors Tr are connected between the body of transistor M3 and the node connecting resistors Rds(4,1) and Rds(4,2). The number of transistors Tr connected between the body and the node is not limited to three and may be, for example, four or more. In this case, the examples shown in Figure 10(a), (b), and (c) may be combined as appropriate.

In this way, the number and connection relationship of the various transistors Tr connected between the body of transistor M3 and the node connecting resistors Rds(4,1) and Rds(4,2) can be changed as appropriate, taking into account the desired voltage difference between the body and the node when current flows from the body to the node, and/or the breakdown voltage of the various transistors Tr.

Second Embodiment
The switch circuit 1a according to the second embodiment will be described below.
The configuration, operation, and effects of the switch circuit 1a according to the second embodiment will be described, focusing on the differences from those described for the switch circuit 1 according to the first embodiment.

The explanation given with reference to Figure 1 in relation to switch circuit 1 also applies to switch circuit 1a. More specifically, the explanation given in Figure 1 applies with switch circuit 1 replaced with switch circuit 1a. The following explanation focuses on switch circuit 1a.

FIG. 11 shows an example of the circuit configuration of a switch circuit 1a according to the second embodiment.
Switch circuit 1a includes, for example, diodes D1, D2, D3, D4, D5, ..., D(n-2), D(n-1), and Dn each formed of a PN junction, in addition to the components included in switch circuit 1. Switch circuit 1a has a circuit configuration in which, in the circuit configuration of switch circuit 1 described with reference to Fig. 2, a diode D is connected between the body and gate of each of transistors M1, M2, M3, ..., and Mn. More specifically, this is as follows.

The anode of diode D1 is connected to the body of transistor M1, and the cathode of diode D1 is connected to the gate of transistor M1. The anode of diode D2 is connected to the body of transistor M2, and the cathode of diode D2 is connected to the gate of transistor M2. The anode of diode D3 is connected to the body of transistor M3, and the cathode of diode D3 is connected to the gate of transistor M3. The same applies to diodes D4, D5, ..., D(n-2), D(n-1), and Dn.

For example, if the voltage of the body of transistor M2 is higher than the voltage of the gate of transistor M2, current can flow from the body to the gate via diode D2. When current flows in this way, the voltage of the body drops. A similar explanation applies to other diodes D. Current flowing through diodes D in this way can also contribute to suppressing an increase in the bias voltage of the body of transistor M. In particular, these diodes D can operate effectively when the voltage of signal BB is equal to or higher than the voltage of signal GB.

In the above, diodes D1, D2, D3, D4, D5, ..., D(n-2), D(n-1), and Dn, each consisting of a PN junction, have been described as components of switch circuit 1a. In switch circuit 1a, diode-connected transistors may be used instead of diodes D.

Third Embodiment
A switch circuit 1b according to the third embodiment will be described below.
The configuration, operation, and effects of the switch circuit 1b according to the third embodiment will be described, focusing on the differences from those described for the switch circuit 1 according to the first embodiment.

The explanation given with reference to Figure 1 in relation to switch circuit 1 also applies to switch circuit 1b. More specifically, the explanation given in Figure 1 applies with switch circuit 1 replaced with switch circuit 1b. The following explanation focuses on switch circuit 1b.

FIG. 12 shows an example of the circuit configuration of a switch circuit 1b according to the third embodiment.
The circuit configuration of the switch circuit 1b is obtained by replacing the resistor connected between the first terminal and the second terminal of each of the transistors M1, M2, M3, ..., and Mn in the circuit configuration of the switch circuit 1 described with reference to Fig. 2 with that of the transistor M as follows: The following explanation is valid for each case where the integer i is 1 to n.

The resistors connected between the first and second terminals of transistor Mi are replaced from resistors Rds(i,1) and Rds(i,2) to resistors Rds(i,1)b, Rds(i,2)b, and Rds(i,3)b. More specifically, one terminal of resistor Rds(i,1)b is connected to the first terminal of transistor Mi, one terminal of resistor Rds(i,2)b is connected to the other terminal of resistor Rds(i,1)b, one terminal of resistor Rds(i,3)b is connected to the other terminal of resistor Rds(i,2)b, and the second terminal of transistor Mi is connected to the other terminal of resistor Rds(i,3)b.

When the integer i is any value from 1 to n, the resistance values of resistors Rds(i,1)b and Rds(i,3)b are substantially the same, R2, for example, and the resistance value of resistor Rds(i,2)b is, for example, twice R2. Below, we will explain the case where the resistance values of resistors Rds(i,1)b and Rds(i,3)b are substantially the same, R2, for example, and the resistance value of resistor Rds(i,2)b is twice R2, for example, when the integer i is any value from 1 to n.

Next, we will explain the differences between the connection relationships of the various transistors Tr, which are components of the feedback circuit and correspond to each transistor M, and those explained for the switch circuit 1 according to the first embodiment.

The second end of transistor Tr(1,4) associated with transistor M1 is connected to the node connecting resistors Rds(2,2)b and Rds(2,3)b.

With respect to the various transistors Tr associated with transistors M2, M3, . . . and M(n-1), the following statements hold for each case where the integer j is 2 to n-1.
A second end of the transistor Tr(j,2) is connected to a node connecting the resistors Rds(j-1,1)b and Rds(j-1,2)b. A second end of the transistor Tr(j,4) is connected to a node connecting the resistors Rds(j+1,2)b and Rds(j+1,3)b.

The second end of transistor Tr(n,2) associated with transistor Mn is connected to the node connecting resistors Rds(n-1,1)b and Rds(n-1,2)b.

The following description will refer to the various voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12b, and VR23b shown in Figure 12.

Voltage VR12b is the voltage at the node connecting the second end of transistor Tr(2,2) with resistors Rds(1,1)b and Rds(1,2)b. Voltage VR23b is the voltage at the node connecting the second end of transistor Tr(2,4) with resistors Rds(3,2)b and Rds(3,3)b.

Figure 13 is a diagram illustrating the operation of switch circuit 1b according to the third embodiment when a third high-frequency signal is input to switch circuit 1b. Figure 13 shows example waveforms of voltages VM01, VM12, VM23, VM34, VG2, VB2, VR12b, and VR23b when a third high-frequency signal is input to terminal IN. The horizontal axis represents time. The vertical axis represents the voltage value.

When a third high-frequency signal is input to terminal IN, the voltage signal applied between the first and second terminals of each transistor M becomes a high-frequency signal with an amplitude of 4V, similar to the example in Figure 7. As in the example in Figure 7, the L-level voltage of signal GB is -3V, and the voltage of signal BB is also -3V. In this case, the waveforms of voltages VM01, VM12, VM23, VM34, VG2, and VB2 are the same as in the example in Figure 7.

The voltage VR12b signal is a high-frequency signal with an amplitude of 7 V. This is based on voltage division by resistors Rds(1,1)b and Rds(1,2)b and Rds(1,3)b. Similarly, the voltage VR23b signal is a high-frequency signal with an amplitude of 3 V. The voltage VR12b signal is substantially in phase with the voltage VM12 signal, and the voltage VR23b signal is substantially out of phase with the voltage VM12 signal.

Times T30 and T31 will be described below. Time T30 is the time when the value of voltage VM12 reaches a maximum. Time T31 is the time when the value of voltage VM12 reaches a minimum.

At time T30, similar to time T20 in the example of Figure 7, voltages VB2 and VG2 are -1 V, but voltage VR23b is -3 V, lower than the -2 V of voltage VR23 at time T20 in the example of Figure 7. At this time, similar to time T20 in the example of Figure 7, current flows out of the body of transistor M2 via transistors Tr(2,3) and Tr(2,4), but the source voltage of transistor Tr(2,4) is lower compared to time T20 in the example of Figure 7.

At time T31, similar to time T21 in the example of Figure 7, voltages VB2 and VG2 are -5V, but voltage VR12b is -7V, lower than the -6V of voltage VR12 at time T21 in the example of Figure 7. At this time, similar to time T21 in the example of Figure 7, current flows out of the body of transistor M2 via transistors Tr(2,1) and Tr(2,2), but the source voltage of transistor Tr(2,2) is lower compared to time T21 in the example of Figure 7.

This lowering of the source voltages of transistors Tr(2,2) and Tr(2,4) means that, in the switch circuit 1c of the example of Figure 12, the feedback circuit can operate even if the amplitude of the high-frequency signal input to terminal IN is smaller than in the switch circuit 1 of the example of Figure 2.

In the above, for example, an example was described in which the resistance between the first terminal of transistor M1 and the second terminal of transistor Tr(2,2) is R2, and the resistance between the second terminal of transistor Tr(2,2) and the second terminal of transistor M1 is three times R2. However, this embodiment is not limited to this. The ratio of the resistance between the first terminal of transistor M1 and the second terminal of transistor Tr(2,2) to the resistance between the second terminal of transistor Tr(2,2) and the second terminal of transistor M1 may be a different value. For example, the resistance between the first terminal of transistor M1 and the second terminal of transistor Tr(2,2) is between 1/3 and 3 times the resistance between the second terminal of transistor Tr(2,2) and the second terminal of transistor M1. The same applies to the other transistors Tr(1,4), Tr(2,4), Tr(3,2), Tr(3,4), ..., Tr(n-1,2), Tr(n-1,4), and Tr(n,2).

In this way, the switch circuit 1c according to the third embodiment makes it possible to adjust the level of high-frequency power associated with the high-frequency signal input to terminal IN at which the feedback circuit begins to operate.

Fourth Embodiment
A switch circuit 1c according to the fourth embodiment will be described below.
The configuration, operation, and effects of the switch circuit 1c according to the fourth embodiment will be described, focusing on the differences from those described for the switch circuit 1 according to the first embodiment.

The explanation given with reference to Figure 1 in relation to switch circuit 1 also applies to switch circuit 1c. More specifically, the explanation given in Figure 1 applies with switch circuit 1 replaced with switch circuit 1c. The following explanation focuses on switch circuit 1c.

FIG. 14 shows an example of the circuit configuration of a switch circuit 1c according to the fourth embodiment.
Switch circuit 1c further includes transistors Tr(1,1), Tr(1,2), Tr(n,3), and Tr(n,4) as components of a feedback circuit in addition to the configuration included in switch circuit 1. Switch circuit 1c has a circuit configuration in which transistors Tr(1,1), Tr(1,2), Tr(n,3), and Tr(n,4) are connected as follows in the circuit configuration of switch circuit 1 described with reference to FIG.

Transistors Tr(1,1) and Tr(1,2) are associated with transistor M1.

The first terminal of transistor Tr(1,1) is connected to the body of transistor M1, and the gate of transistor Tr(1,1) is connected to the gate of transistor M1. The second terminal of transistor Tr(1,1) is connected to the first terminal of transistor Tr(1,2) and the gate of transistor Tr(1,2). Thus, the diode-connected transistor Tr(1,2) is connected to the second terminal of transistor Tr(1,1). The second terminal of transistor Tr(1,2) is connected to the node connecting resistors Rds(2,1) and Rds(2,2).

Transistors Tr(n,3) and Tr(n,4) are associated with transistor Mn.

The first terminal of transistor Tr(n,3) is connected to the body of transistor Mn, and the gate of transistor Tr(n,3) is connected to the gate of transistor Mn. The second terminal of transistor Tr(n,3) is connected to the first terminal of transistor Tr(n,4) and the gate of transistor Tr(n,4). Thus, the diode-connected transistor Tr(n,4) is connected to the second terminal of transistor Tr(n,3). The second terminal of transistor Tr(n,4) is connected to the node connecting resistors Rds(n-1,1) and Rds(n-1,2).

As explained with reference to FIG. 2, current can flow from the body of transistor M1 via transistors Tr(1,1) and Tr(1,2). This current can also contribute to suppressing an increase in the bias voltage of the body of transistor M1 due to leakage current Ib generated in transistor M1. Similarly, current can flow from the body of transistor Mn via transistors Tr(n,3) and Tr(n,4). This current can also contribute to suppressing an increase in the bias voltage of the body of transistor Mn due to leakage current Ib generated in transistor Mn.

Fifth Embodiment
A switch circuit 1d according to the fifth embodiment will be described below.
The configuration, operation, and effects of the switch circuit 1d according to the fifth embodiment will be described, focusing on the differences from those described for the switch circuit 1a according to the second embodiment.

The explanation given with reference to Figure 1 in relation to switch circuit 1 also applies to switch circuit 1d. More specifically, the explanation given in Figure 1 applies with switch circuit 1 replaced with switch circuit 1d. The following explanation focuses on switch circuit 1d.

FIG. 15 shows an example of the circuit configuration of a switch circuit 1d according to the fifth embodiment.
The switch circuit 1d has a circuit configuration in which the resistors Rb1, Rb2, Rb3, Rb4, ..., Rb(n-2), Rb(n-1), and Rbn are omitted from the configuration of the switch circuit 1a. More specifically, this is as follows.

No polysilicon resistor is provided between the body of transistor M1 and the body of transistor M2. No polysilicon resistor is provided between the body of transistor M2 and the body of transistor M3. No polysilicon resistor is provided between the body of transistor M3 and the body of transistor M4. The same applies to the body of transistor M4 and the body of transistor M5, ..., between the body of transistor M(n-2) and the body of transistor M(n-1), and between the body of transistor M(n-1) and the body of transistor Mn. Furthermore, signal BB is not input to switch circuit 1d.

As such, switch circuit 1d does not include any terminals or resistors for applying voltage to the body of the transistor from the outside. This reduces parasitic capacitance and suppresses insertion loss, which occurs when a signal passes through switch circuit 1d in the on state.

Sixth Embodiment
A switch circuit 1e according to the sixth embodiment will be described below.
The configuration, operation, and effects of the switch circuit 1e according to the sixth embodiment will be described, focusing on the differences from those of the switch circuit 1d according to the fifth embodiment.

The explanation given with reference to Figure 1 in relation to switch circuit 1 also applies to switch circuit 1e. More specifically, the explanation given in Figure 1 applies with switch circuit 1 replaced with switch circuit 1e. The following explanation focuses on switch circuit 1e.

FIG. 16 shows an example of the circuit configuration of a switch circuit 1e according to the sixth embodiment.
The switch circuit 1e has a configuration in which a resistor Rcont is further included in the configuration included in the switch circuit 1d, and the connections of the resistors Rg1, Rg2, Rg3, Rg4, Rg5, ..., Rg(n-2), Rg(n-1), and Rgn are changed. More specifically, this is as follows.

One end of resistor Rg1 is connected to the gate of transistor M1. The other end of resistor Rg1 is connected to one end of resistor Rcont. One end of resistor Rg2 is connected to the gate of transistor M2. The other end of resistor Rg2 is connected to one end of resistor Rcont. One end of resistor Rg3 is connected to the gate of transistor M3. The other end of resistor Rg3 is connected to one end of resistor Rcont. The same applies to the connections of resistors Rg4, Rg5, ..., Rg(n-1), and Rgn. The other end of resistor Rcont is connected to a node to which signal GB is input. Figure 16 shows the control terminal to which signal GB is input to switch circuit 1e.

Even if the connections of resistors Rg1, Rg2, Rg3, ..., Rg(n-1), and Rgn are changed in this way, the switch circuit 1e according to the sixth embodiment can suppress insertion loss, just like the switch circuit 1d according to the fifth embodiment.

<Other Embodiments>
In this specification, the term "connection" refers to an electrical connection, and does not exclude the use of another element therebetween. Furthermore, in this specification, the term "resistance" may refer to a resistive element or a parasitic resistance.

In this specification, terms such as identical, coincident, constant, and maintain are intended to include cases where there may be design errors when implementing the technology described in the embodiments. The same applies when the term "substantially" is used in conjunction with these terms, such as "substantially identical." Furthermore, the term "applying or supplying a certain voltage" is intended to include both controlling the application or supply of that voltage and actually applying or supplying that voltage. Furthermore, applying or supplying a certain voltage may include, for example, applying or supplying a voltage of 0 V.

Although several embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in a variety of other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and variations thereof are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims.

1, 1a, 1b, 1c, 1d, 1e, 2, 3, 4...switch circuit, 5, 6...signal processing circuit, 7...control circuit, WD...radio device, ANT...antenna, M, Tr...transistor, Rg, Rb, Rds...resistor, D...diode, SB...semiconductor substrate, BOX...oxide film, BD...body layer, DR...drain region, SR...source region, G...gate electrode, GI...gate insulator.

Claims (14)

A semiconductor device comprising an input terminal, an output terminal, and a plurality of transistors connected in series between the input terminal and the output terminal,
The plurality of transistors include:
a first transistor having a first end and a second end used in the series connection;
a second transistor having a third end and a fourth end, a first gate, and a first body used in the series connection, the third end being connected to the second end;
The semiconductor device further comprises:
a third transistor and a first diode connected in series between the first body and the first end;
the third transistor has a second gate connected to the first gate;
an anode of the first diode is provided on the first body side of the first body and the first end, and a cathode of the first diode is provided on the first end side of the first body and the first end;
Semiconductor device. further comprising a first resistor and a second resistor connected in series between the first end and the second end;
the third transistor and the first diode are connected in series between the first body and a node connecting the first resistor and the second resistor;
The semiconductor device according to claim 1 . a fourth transistor is used as the first diode;
the third transistor has a fifth terminal connected to the first body and a sixth terminal;
the fourth transistor has a seventh terminal connected to the sixth terminal, an eighth terminal connected to a node connecting the first resistor and the second resistor, and a third gate connected to the seventh terminal.
The semiconductor device according to claim 2 . The plurality of transistors further comprises:
a fifth transistor having a ninth terminal and a tenth terminal used in the series connection, the ninth terminal being connected to the fourth terminal;
The semiconductor device further comprises:
a sixth transistor and a second diode connected in series between the first body and the tenth terminal;
the sixth transistor has a fourth gate connected to the first gate;
an anode of the second diode is provided on the first body side of the first body and the tenth end, and a cathode of the second diode is provided on the tenth end side of the first body and the tenth end;
The semiconductor device according to claim 1 . The plurality of transistors further comprises:
a fourth transistor having a fifth terminal and a sixth terminal used in the series connection, the fifth terminal being connected to the fourth terminal;
The semiconductor device further comprises:
a fifth transistor and a second diode connected in series between the first body and the sixth end;
the fifth transistor has a third gate connected to the first gate;
an anode of the second diode is provided on the first body side of the first body and the sixth end, and a cathode of the second diode is provided on the sixth end side of the first body and the sixth end,
The semiconductor device further comprises:
a third resistor and a fourth resistor connected in series between the fifth terminal and the sixth terminal;
the fifth transistor and the second diode are connected in series between the first body and a node connecting the third resistor and the fourth resistor;
one end of the first resistor is connected to the first end, one end of the second resistor is connected to the other end of the first resistor, and the second end is connected to the other end of the second resistor;
one end of the third resistor is connected to the fifth end, one end of the fourth resistor is connected to the other end of the third resistor, and the sixth end is connected to the other end of the fourth resistor;
the first resistor and the fourth resistor have the same resistance value, and the second resistor and the third resistor have the same resistance value;
The semiconductor device according to claim 2 . further comprising a fifth transistor and a second diode connected in series between the first body and the first end;
the fifth transistor and the second diode are connected between the first body and the first end in parallel with the third transistor and the first diode;
the fifth transistor has a fourth gate connected to the first gate;
an anode of the second diode is provided on the first body side of the first body and the first end, and a cathode of the second diode is provided on the first end side of the first body and the first end;
The semiconductor device according to claim 1 . The semiconductor device of claim 1, further comprising one or more diodes connected in series with the third transistor and the first diode between the first body and the first end. The semiconductor device of claim 1, further comprising a third diode having an anode connected to the first body and a cathode connected to the first gate. further comprising a first resistor and a second resistor connected in series between the first end and the second end, a third resistor and a fourth resistor connected in series between the third end and the fourth end, and a fifth resistor and a sixth resistor connected in series between the ninth end and the tenth end;
the third transistor and the first diode are connected in series between the first body and a node connecting the first resistor and the second resistor;
the sixth transistor and the second diode are connected in series between the first body and a node connecting the fifth resistor and the sixth resistor;
The semiconductor device according to claim 4 . the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor have the same resistance value;
The semiconductor device according to claim 9 . the first transistor further has a fifth gate and a second body;
the semiconductor device further includes a seventh transistor and a third diode connected in series between the second body and a node connecting the third resistor and the fourth resistor;
the seventh transistor has a sixth gate connected to the fifth gate;
an anode of the third diode is provided on the second body side of a node connecting the second body to the third resistor and the fourth resistor, and a cathode of the third diode is provided on the node connecting the third resistor and the fourth resistor of a node connecting the second body to the third resistor and the fourth resistor.
The semiconductor device according to claim 9 . the fifth transistor further has a seventh gate and a third body;
the semiconductor device further includes an eighth transistor and a fourth diode connected in series between the third body and a node connecting the third resistor and the fourth resistor;
the eighth transistor has an eighth gate connected to the seventh gate;
an anode of the fourth diode is provided on the third body side of a node connecting the third body to the third resistor and the fourth resistor, and a cathode of the fourth diode is provided on the node connecting the third body to the third resistor and the fourth resistor,
The semiconductor device according to claim 9 . the first transistor has a second body;
11. The semiconductor device according to claim 1, further comprising a seventh resistor made of polysilicon connecting said first body and said second body. the first transistor has a second body;
11. The semiconductor device according to claim 1, wherein a resistor using polysilicon connecting said first body and said second body is not provided.