JP7736147B2 - Semiconductor Devices - Google Patents

Description

The disclosure in this specification relates to semiconductor devices.

Patent Document 1 discloses a semiconductor device that forms an upper and lower arm circuit. The semiconductor device includes a semiconductor element having main electrodes on both sides and a substrate in which metal bodies are disposed on both sides of an insulating base material. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification.

Japanese Patent Application Laid-Open No. 2020-150021

In the semiconductor device described above, surge voltages occur when the semiconductor elements are switched on and off. To reduce surge voltages, it is necessary to reduce the inductance of the main circuit wiring. Further improvements are required in semiconductor devices in the above respects, as well as in other respects not mentioned.

One disclosed objective is to provide a semiconductor device that can reduce inductance.

The semiconductor device disclosed herein comprises:
a plurality of semiconductor elements (40) each having a first main electrode (40D) and a second main electrode (40S) formed on a surface opposite to the first main electrode in a plate thickness direction, the semiconductor elements (40) including a first element (40H) constituting one of the arms of an upper and lower arm circuit (9), and a second element (40L) constituting the other of the arms and arranged alongside the first element in a first direction perpendicular to the plate thickness direction;
a plurality of power supply terminals (91) arranged so that the first element is located between the first and second elements in a first direction, the first power supply terminals (91P) being electrically connected to first main electrodes of the first elements and the second power supply terminals (91N) being electrically connected to second main electrodes of the second elements;
a first substrate (50) having a first insulating base material (51), a first front surface metal body (52) arranged on the surface of the first insulating base material, a first power supply wiring (54) electrically connecting a first power supply terminal and a first main electrode of a first element, and a first relay wiring (55) arranged alongside the first power supply wiring in a first direction and connected to a first main electrode of a second element, and a first back surface metal body (53) arranged on the back surface of the first insulating base material;
a second substrate (60) arranged so as to sandwich a plurality of semiconductor elements between itself and the first substrate in the plate thickness direction, the second substrate having: a second insulating base (61); a second front surface metal body (62) arranged on the surface of the second insulating base, the second power supply wiring (64) electrically connecting a second power supply terminal and a second main electrode of the second element, and a second relay wiring (65) connected to the second main electrode of the first element; and a second rear surface metal body (63) arranged on the rear surface of the second insulating base;
an arm connection portion (80) disposed between the first element and the second element in the first direction and electrically connecting the first relay wiring and the second relay wiring;
a sealing body (30) that seals the plurality of semiconductor elements, the arm connection portion, a portion of each of the plurality of power supply terminals, the first surface metal body, and the second surface metal body;
The second power supply wiring is arranged alongside the second relay wiring in the first direction and has a base (640) on which the second element is arranged, and a pair of extension portions (641) extending from the base in the first direction so as to sandwich the second relay wiring in a second direction perpendicular to the plate thickness direction and the first direction, and each having a second power supply terminal connected thereto.

According to the disclosed semiconductor device, the inductance can be reduced.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference symbols in parentheses in the claims and this section are intended to illustratively indicate the correspondence with the embodiments described below and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

1 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied; FIG. 1 is a perspective view showing a semiconductor device. FIG. 1 is a perspective view showing a semiconductor device. FIG. 1 is a plan view showing a semiconductor device. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is an enlarged view of region IX shown in FIG. 8. FIG. 1 is an exploded perspective view illustrating a semiconductor device. FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. FIG. 2 is a plan view showing a circuit pattern on the substrate on the source electrode side. FIG. 2 is a diagram showing the arrangement of a circuit pattern, a semiconductor element, and terminals on the drain electrode side. 1A and 1B are diagrams showing the arrangement of a circuit pattern, a semiconductor element, and terminals on the source electrode side. FIG. 10 is a plan view showing a current loop of a reference example. FIG. 2 is a plan view showing a current loop. FIG. 1 is a side view showing a current loop. FIG. 10 is a diagram showing current density in a reference example. FIG. 10 is a diagram showing current density for this embodiment. FIG. FIG. FIG. 10 is a plan view showing a circuit pattern on a substrate on the drain electrode side in a modified example. FIG. 10 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 10 is a diagram for explaining the effect of inductance Ls. FIG. 10 is a diagram for explaining the effect of inductance Ls. FIG. 2 is a plan view showing a circuit pattern on the substrate on the source electrode side. FIG. FIG. 4 is a cross-sectional view showing an arm connection portion. FIG. 10 is a plan view showing a modified example of the substrate on the source electrode side. FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. FIG. 10 is a plan view showing a modified example of the substrate on the drain electrode side. FIG. FIG. 10 is a cross-sectional view showing a modified example of the arm connection portion. FIG. 10 is a cross-sectional view showing a modified example of the arm connection portion. FIG. 10 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. FIG. 10 is a cross-sectional view showing warpage at high temperatures. FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 1 is a cross-sectional view showing a semiconductor device at room temperature. FIG. 1 is a cross-sectional view showing a semiconductor device at a high temperature. FIG. 10 is a diagram showing the relationship between the ratio of thicknesses T1 and T2 and the amount of warping. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is an enlarged plan view of the periphery of a signal terminal in a semiconductor device according to a fourth embodiment. A cross-sectional view taken along line XLVII-XLVII in Figure 46. FIG. 1 is a diagram illustrating wire bonding. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. FIG. FIG. 54 is a cross-sectional view taken along the line LV-LV in FIG. 53. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. FIG. 58 is a plan view seen from the LVIII direction shown in FIG. 57. FIG. 58 is an enlarged view of an area LIX shown in FIG. 57. This is a diagram in which the bonding material is omitted from Figure 59. FIG. FIG. 62 is a plan view seen from the direction LXII shown in FIG. 61. FIG. FIG. 10 is a cross-sectional view showing a modified example. FIG. 65 is an enlarged view of area LXV shown in FIG. 64. FIG. 10 is a cross-sectional view showing a modified example. FIG. 67 is an enlarged view of area LXVII shown in FIG. 66. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. FIG. 1 is a diagram showing the relationship between the glass transition point and the linear expansion coefficient for a sealing body and an insulating base material. FIG. 10 is a diagram showing warpage in a reference example. FIG. 10 is a diagram showing warpage at high temperatures. FIG. 13 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. FIG. 74 is an enlarged view of region LXXIV of FIG. 73. 1A to 1C are diagrams illustrating a method for forming a roughened portion. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 13 is a cross-sectional view showing a semiconductor device according to an eighth embodiment. FIG. 80 is an enlarged view of area LXXX in FIG. 79. FIG. 10 is a diagram showing the relationship between the spacing, thickness, and inductance. FIG. 10 is a diagram showing a simulation result when the interval is smaller than the thickness. FIG. 10 is a diagram showing a simulation result when the spacing is greater than the thickness. FIG. 13 is a cross-sectional view showing a semiconductor device according to a ninth embodiment. FIG. FIG. 85 is an enlarged view of area LXXXVI of FIG. 84. FIG. 10 shows dimensions and angles. FIG. FIG. 22 is a cross-sectional view showing a semiconductor device according to a tenth embodiment. FIG. 1 is a plan view showing a semiconductor element. FIG. 89 is an enlarged view of region XCI in FIG. 89. FIG. 3 is a cross-sectional view showing the arrangement of sintered members. 10A to 10C are cross-sectional views showing a joining method. 10 is a diagram showing the relationship between the distance between the inner circumferential surface of the protective film and the sintered member and the strain amplitude of the base electrode. FIG. FIG. 2 is a cross-sectional view showing the arrangement of solder as a bonding material. FIG. 22 is a cross-sectional view showing a semiconductor device according to an eleventh embodiment. This is an enlarged view of area XCVII in Figure 96. FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and an uneven oxide film. FIG. 98 is an enlarged view of area XCIX in FIG. 97. FIG. 10 is a cross-sectional view showing a modified example. FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and an uneven oxide film. FIG. 10 is a cross-sectional view showing a modified example. FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and an uneven oxide film. FIG. 10 is a cross-sectional view showing a modified example. FIG. 22 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment. FIG. 106 is an enlarged view of area CVI in FIG. 105. FIG. 10 is a diagram showing the relationship between the Young's modulus and the yield stress of the base electrode, the sintered layer, and the brittle layer. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 10 is a cross-sectional view showing a modified example. FIG. 23 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a thirteenth embodiment is applied. FIG. 1 is a perspective view showing a semiconductor device. FIG. 1 is a plan view showing a semiconductor device. FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. FIG. 2 is a plan view showing a circuit pattern on the substrate on the source electrode side. A cross-sectional view taken along line CXVII-CXVII in Figure 113. A cross-sectional view taken along line CXVIII-CXVIII in Figure 113. FIG. 114 is a cross-sectional view taken along line CXIX-CXIX in FIG. 113. A cross-sectional view taken along line CXX-CXX in Figure 113. FIG. 121 is an enlarged view of area CXXI of FIG. 120.

Several embodiments will be described below with reference to the drawings. Note that corresponding components in each embodiment will be given the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another previously described embodiment may be applied to the remaining portions of that configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of multiple embodiments may also be partially combined together even if not explicitly stated, provided that there are no particular problems with the combination.

The semiconductor device of this embodiment is applied, for example, to a power conversion device for a mobile object that uses a rotating electric machine as a drive source. Examples of mobile objects include electrically powered vehicles such as electric vehicles (EVs), hybrid vehicles (HVs), and plug-in hybrid vehicles (PHVs), as well as flying objects such as drones, ships, construction machinery, and agricultural machinery. Below, we will explain an example of application to a vehicle.

(First embodiment)
First, a schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

<Vehicle drive system>
As shown in FIG. 1 , a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

<Power conversion device>
Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6, which is a power conversion circuit.

The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power supply line, and the N line 8, which is the low-potential power supply line. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

The inverter 6 is a DC-AC conversion circuit. Under switching control by a control circuit (not shown), the inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage under switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of the P line 7, N line 8, and output line 10 is configured with a conductive member such as a bus bar.

In this embodiment, an n-channel MOSFET 11 is used as the switching element that constitutes each arm. There is no particular limit to the number of switching elements that constitute each arm. It may be one or multiple. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 that make up one arm are connected in parallel. In the upper arm 9H, the drains of the two parallel-connected MOSFETs 11 are connected to the P line 7. In the lower arm 9L, the sources of the two parallel-connected MOSFETs 11 are connected to the N line 8. The sources of the two parallel-connected MOSFETs 11 in the upper arm 9H are connected to the drains of the two parallel-connected MOSFETs 11 in the lower arm 9L. The two parallel-connected MOSFETs 11 are turned on and off at the same time by a common gate drive signal (drive voltage).

A freewheeling diode 12 is connected in anti-parallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20. Details of the semiconductor device 20 will be described later.

The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage boosting and bucking. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

The power conversion device 4 may include a drive circuit for the switching elements that make up the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. By applying the drive voltage, the drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off. The drive circuit is sometimes referred to as a driver.

The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured, for example, with a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

<Semiconductor Device>
Next, the semiconductor device will be described with reference to FIGS. 2 to 13. FIG. 2 is a perspective view of the semiconductor device 20. FIG. 3 is a perspective view of the semiconductor device 20 similar to FIG. 2. FIG. 3 is a see-through view showing the internal structure. FIG. 4 is a plan view of the semiconductor device 20. FIG. 4 is a see-through view showing the internal structure. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is an enlarged view of region IX indicated by a dashed line in FIG. 8.

Figure 10 is an exploded perspective view illustrating the semiconductor device 20. For convenience, a lead frame 94 is shown in Figure 10. Figure 11 is a plan view showing a semiconductor element 40 mounted on a substrate 50. Figure 12 is a plan view showing the circuit pattern of the surface metal body 52 on the substrate 50. Figure 13 is a plan view showing the circuit pattern of the surface metal body 62 on the substrate 60.

In the following, the thickness direction of the semiconductor element (semiconductor substrate) is referred to as the Z direction. The Y direction is perpendicular to the Z direction and indicates the arrangement direction of the semiconductor elements constituting the upper arm 9H and the semiconductor elements constituting the lower arm 9L. The X direction is the direction perpendicular to both the Z and Y directions. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view. Furthermore, the term "arrangement" is not limited to the mounting surface, and may be used to refer to overlapping positions in a planar view.

As shown in Figures 2 to 13, the semiconductor device 20 constitutes one of the upper and lower arm circuits 9 described above, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90.

The encapsulant 30 encapsulates some of the other elements that make up the semiconductor device 20. The remaining parts of the other elements are exposed outside the encapsulant 30. The encapsulant 30 is made of, for example, a resin. One example of a resin is an epoxy-based resin. The encapsulant 30 is molded using, for example, a transfer molding method using a resin material. Such a encapsulant 30 is sometimes referred to as an encapsulating resin body, a molded resin, or a resin molded body. The encapsulant 30 may be formed using, for example, a gel. The gel is filled (placed) in the opposing regions of the pair of substrates 50, 60, for example.

As shown in Figures 2 to 4, the sealing body 30 has a generally rectangular shape in plan view. The sealing body 30 has, as surfaces forming its outer periphery, one surface 30a and a back surface 30b that is the surface opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. The sealing body 30 also has side surfaces that connect the one surface 30a and the back surface 30b. The side surfaces include two side surfaces 30c and 30d from which the external connection terminals 90 protrude. The side surface 30d is the surface opposite to the side surface 30c in the Y direction .

The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si), a wide bandgap semiconductor with a wider bandgap than silicon, or _the like. Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide ( _Ga2O3 ), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

The semiconductor element 40 of this embodiment has the above-mentioned n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that the main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of the switching element on both sides in the thickness direction, i.e., the Z direction. Specifically, the main electrodes include a drain electrode 40D on one side and a source electrode 40S on the back side, which is the surface opposite the first side in the Z direction.

When diode 12 is a parasitic diode, the source electrode 40S also serves as the anode electrode, and the drain electrode 40D also serves as the cathode electrode. Diode 12 may be configured on a chip separate from MOSFET 11. Drain electrode 40D is the main electrode on the high potential side (first main electrode), and source electrode 40S is the main electrode on the low potential side (second main electrode). Below, drain electrode 40D and source electrode 40S may be referred to as main electrodes 40D and 40S.

The semiconductor element 40 has a generally rectangular shape in plan view. As shown in FIG. 11, the semiconductor element 40 has a pad 40P formed on the back surface at a position different from the source electrode 40S. The source electrode 40S and pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed on almost the entire surface. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. In a plan view, the drain electrode 40D has a larger area than the source electrode 40S.

Pad 40P is a signal electrode. Pad 40P is electrically isolated from source electrode 40S. Pad 40P is formed at the end opposite the formation area of source electrode 40S in the Y direction. Pad 40P includes a pad for a gate electrode.

The semiconductor device 20 includes multiple semiconductor elements 40 having the above-described configuration. The configuration of each semiconductor element 40 is common to all of them. The multiple semiconductor elements 40 include a semiconductor element 40H that constitutes the upper arm 9H and a semiconductor element 40L that constitutes the lower arm 9L. The semiconductor element 40H is sometimes referred to as the upper arm element, and the semiconductor element 40L is sometimes referred to as the lower arm element. Each of the semiconductor elements 40H and 40L is an arm element that constitutes one arm. The semiconductor device 20 of this embodiment includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are aligned in the X direction. Similarly, the two semiconductor elements 40L are aligned in the X direction. The semiconductor elements 40H and 40L are aligned in the Y direction. The Y direction is a first direction perpendicular to the Z direction, which is the thickness direction of the semiconductor element 40. The X direction is a second direction perpendicular to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and semiconductor elements 40L arranged along the Y direction.

Each semiconductor element 40 is arranged at approximately the same position relative to one another in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

The substrates 50, 60 are arranged in the Z direction so as to sandwich multiple semiconductor elements 40 therebetween. The substrates 50, 60 are arranged so that at least a portion of each substrate faces each other in the Z direction. The substrates 50, 60 contain all of the multiple semiconductor elements 40 (40H, 40L) when viewed in a plan view.

The substrate 50 is disposed on the drain electrode 40D side of the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side of the semiconductor element 40. As described below, the substrate 50 is electrically connected to the drain electrode 40D and provides wiring functionality. Similarly, the substrate 60 is electrically connected to the source electrode 40S and provides wiring functionality. For this reason, the substrates 50 and 60 are sometimes referred to as wiring substrates. The substrate 50 is sometimes referred to as a drain substrate, and the substrate 60 is sometimes referred to as a source substrate. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 are sometimes referred to as heat dissipation members. Of the pair of substrates 50 and 60 that sandwich the semiconductor element 40 in the Z direction, the substrate 50 is the first substrate, and the substrate 60 is the second substrate.

The substrate 50 has an opposing surface 50a facing the semiconductor element 40 and a back surface 50b opposite the opposing surface 50a. The substrate 50 comprises an insulating substrate 51, a front surface metal body 52, and a back surface metal body 53. The substrate 50 is a substrate in which the insulating substrate 51 and the metal bodies 52 and 53 are laminated. The substrate 60 has an opposing surface 60a facing the semiconductor element 40 and a back surface 60b opposite the opposing surface 60a. The substrate 60 comprises an insulating substrate 61, a front surface metal body 62, and a back surface metal body 63. The substrate 60 is a substrate in which the insulating substrate 61 and the metal bodies 62 and 63 are laminated. In the substrate 50, which is the first substrate, the insulating substrate 51 is the first insulating substrate, the front surface metal body 52 is the first front surface metal body, and the back surface metal body 53 is the first back surface metal body. In the second substrate 60, the insulating substrate 61 is the second insulating substrate, the front surface metal body 62 is the second front surface metal body, and the back surface metal body 63 is the second back surface metal body. Hereinafter, the front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63.

The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. The insulating substrates 51 and 61 are sometimes referred to as insulating layers. The insulating substrates 51 and 61 are made of resin or inorganic ceramic material. Examples of resins that can be used include epoxy resins and polyimide resins. Examples of ceramics _that can be used include _Al2O3 (alumina) and _Si3N4 (silicon nitride). When the insulating substrates 51 and ₆₁ are made of resin, the substrates 50 and 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51 and 61 are made of ceramic, the substrates 50 and 60 are sometimes referred to as metal-ceramic substrates.

In the case of insulating substrates 51 and 61 made of a resin material, an inorganic filler (inorganic filling material) may be contained in the resin to improve heat dissipation, insulation, and the like. The linear expansion coefficient may be adjusted by adding a filler. Examples of fillers that can be used include Al ₂ O ₃ , SiO ₂ (silicon dioxide), AlN (aluminum nitride), and BN (boron nitride). Insulating substrates 51 and 61 may contain only one type of filler or multiple types of fillers.

Considering heat dissipation and insulation properties, in the case of a resin-based insulating substrate, the thickness of each insulating substrate 51, 61, i.e., the length in the Z direction, is preferably approximately 50 μm to 300 μm. In the case of a ceramic-based insulating substrate, the thickness of each insulating substrate 51, 61 is preferably approximately 200 μm to 500 μm. In the Z direction, the front surface of the insulating substrates 51, 61 is the inner surface, i.e., the surface facing the semiconductor element 40, and the back surface, which is the surface opposite the front surface in the Z direction, is the outer surface. The insulating substrates 51, 61 may be made of the same material or may be made of different materials. In this embodiment, resin-based insulating substrates 51, 61 are used, and the material composition is the same. The linear expansion coefficient of the insulating substrates 51, 61 is adjusted to approximately the same value as that of the encapsulant 30 by adding a filler to the resin. By adding filler to the resin, the linear expansion coefficients of the insulating substrates 51, 61 and the sealing body 30 are close to that of the metal (Cu) that makes up the metal bodies 52, 53, 62, and 63.

The metal bodies 52, 53, 62, and 63 are provided, for example, as metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are formed from metals with good electrical and thermal conductivity, such as Cu or Al. The thickness of each of the metal bodies 52, 53, 62, and 63 is, for example, approximately 0.1 mm to 3 mm. The front surface metal body 52 is disposed on the front surface of the insulating substrate 51 in the Z direction. The back surface metal body 53 is disposed on the back surface of the insulating substrate 51. Similarly, the front surface metal body 62 is disposed on the front surface of the insulating substrate 61 in the Z direction. The back surface metal body 63 is disposed on the back surface of the insulating substrate 61. The insulating substrates 51 and 61 are surfaces facing the semiconductor element 40 in the Z direction. As shown in Figures 5 to 9, in this embodiment, the front surface metal body 52 is thicker than the back surface metal body 53. The front surface metal body 62 is thicker than the back surface metal body 63. The front surface metal body 52 on the drain electrode 40D side is thicker than the front surface metal body 62 on the source electrode 40S side. Alternatively, the back surface metal bodies 53, 63 may be thicker than the corresponding front surface metal bodies 52, 62. The front surface metal body 52 and the back surface metal body 53 may be approximately equal in thickness, or the front surface metal body 62 and the back surface metal body 63 may be approximately equal in thickness.

The surface metal bodies 52, 62 are patterned. The surface metal bodies 52, 62 provide wiring, i.e., circuits. For this reason, the surface metal bodies 52, 62 are sometimes referred to as circuit patterns, wiring layers, or circuit conductors. The surface metal bodies 52, 62 may have a plating film of Ni, Au, or the like on the metal surface. Hereinafter, the pattern of the surface metal bodies 52, 62 may be referred to as a circuit pattern. The surface metal body 52 and the area on the surface of the insulating base material 51 where the surface metal body 52 is not placed form the opposing surface 50a of the substrate 50. Similarly, the surface metal body 62 and the area on the surface of the insulating base material 61 where the surface metal body 62 is not placed form the opposing surface 60a of the substrate 60.

For example, the front surface metal bodies 52, 62 may be prepared by patterning them into a predetermined shape using press working or etching, and then adhered to a two-layer laminate of insulating substrates 51, 61 and back surface metal bodies 53, 63 to form the substrates 50, 60. After forming a three-layer laminate of front surface metal bodies 52, 62, insulating substrates 51, 61, and back surface metal bodies 53, 63, the front surface metal bodies 52, 62 may be patterned by cutting or etching.

As shown in Figure 11, the surface metal body 52 has a P wiring 54 and a relay wiring 55. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined gap. This gap is filled with the encapsulant 30.

The P wiring 54 is connected to the P terminal 91P (described later) and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 is sometimes referred to as a positive wiring or a high-potential power supply wiring. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection portion 80, and the output terminal 92. The relay wiring 55 electrically connects the arm connection portion 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode of the semiconductor element 40L to the output terminal 92. In the surface metal body 52 (first surface metal body), the P wiring 54 is the first power supply wiring, and the relay wiring 55 is the first relay wiring.

The P wiring 54 and relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the output terminal 92 side. In other words, the P wiring 54 is arranged close to the side surface 30c of the sealing body 30, and the relay wiring 55 is arranged close to the side surface 30d.

The P wiring 54 has a notch 540. The notch 540 opens on one of the four sides of a generally rectangular planar shape whose longitudinal direction is the X direction. The notch 540 is located approximately in the center in the X direction on the side opposite the side surface 30c. The P wiring 54 has a base 541 and a pair of extensions 542. The base 541 and the pair of extensions 542 define the notch 540. The P wiring 54 has a generally U-shape (concave shape) in planar form.

The base 541 is the portion closer to the relay wiring 55 than the cutout 540 and the extension 542, and has a generally rectangular shape in plan view. The base 541 overlaps the semiconductor element 40H in plan view. In other words, the semiconductor element 40H is disposed on the base 541. The drain electrode 40D of the semiconductor element 40H is connected to the base 541.

The two extension portions 542 extend from the base portion 541 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30. One of the extension portions 542 is connected to the vicinity of one end of the base portion 541 in the X direction, and the other is connected to the vicinity of the other end of the base portion 541. The ends of the U-shape of the P wiring 54, that is, the ends of the two extension portions 542 opposite the base portion 541, are at approximately the same position in the Y direction. The pair of extension portions 542 sandwich the notch 540 in the X direction. The length of the base portion 541 in the Y direction is longer than the depth of the notch 540 and the extension portions 542.

The relay wiring 55 also has a notch 550. The notch 550 is open on one of the four sides of the approximately rectangular planar shape. The notch 550 is provided approximately in the center in the X direction on the side opposite the side surface 30d. In other words, the surface metal body 52 has a notch 540 on one of its ends in the Y direction, and a notch 550 on the other end.

The relay wiring 55 has a base 551 and a pair of extensions 552. The base 551 and the pair of extensions 552 define a notch 550. The relay wiring 55 has a generally U-shape (concave shape) in plan view. The base 551 is the portion closer to the P wiring 54 than the notch 550 and the extensions 552, and has a generally rectangular shape in plan view. The base 551 overlaps the semiconductor element 40L in plan view. In other words, the semiconductor element 40L is disposed on the base 551. The drain electrode 40D of the semiconductor element 40L is connected to the base 551.

The two extension portions 552 extend from the base portion 551 in the same direction, specifically the Y direction, toward the side surface 30d of the sealing body 30. One of the extension portions 552 is connected to the base portion 551 near one end in the X direction, and the other is connected to the base portion 551 near the other end. The ends of the U-shape of the relay wiring 55, i.e., the ends of the two extension portions 552 opposite the base portion 551, are located at approximately the same position in the Y direction. The pair of extension portions 552 sandwich the notch 550 in the X direction. The length of the base portion 551 in the Y direction is longer than the depth of the notch 550 and the extension portions 552.

On the other hand, the surface metal body 62 has an N wiring 64 and a relay wiring 65, as shown in Figures 10 and 13. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined distance (gap). This gap is filled with the sealing body 30.

The N wiring 64 is connected to the N terminal 91N (described later) and the source electrode 40S of the semiconductor element 40L. The N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The N wiring 64 is sometimes referred to as the N wiring. The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connection portion 80. The relay wiring 65 electrically connects the source electrode 40S of the semiconductor element 40H and the arm connection portion 80. In the surface metal body 62 (second surface metal body), the N wiring 64 is the second power supply wiring, and the relay wiring 65 is the second relay wiring.

The N wiring 64 has a base 640 and a pair of extensions 641. The N wiring 64 has a generally U-shape in plan view. The base 640 is arranged alongside the relay wiring 65 in the Y direction. The base 640 is arranged on the side surface 30d in the Y direction. The base 640 has a generally rectangular shape in plan view with the X direction as its longitudinal direction. As shown in FIG. 15 , the base 640 overlaps the semiconductor element 40L in plan view. In other words, the semiconductor element 40L is arranged on the base 640. The source electrode 40S of the semiconductor element 40L is connected to the base 640.

The two extension portions 641 extend from the base 640 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30. One of the extension portions 641 is connected to near one end of the base 640 in the X direction, and the other is connected to near the other end of the base 640. The ends of the U-shape of the N wiring 64, i.e., the ends of the two extension portions 641 opposite the base 640, are at approximately the same position in the Y direction.

The pair of extensions 641 form both ends of the surface metal body 62 in the X direction. The pair of extensions 641 are arranged near the edge of the substrate 60. In a plan view, a portion of each of the pair of extensions 641 overlaps the P wiring 54. The length of the extensions 641 in the Y direction is longer than that of the base 640. The N wiring 64 also has a notch 642. The notch 642 opens on one of the four sides of the approximately rectangular planar shape whose longitudinal direction is the Y direction. The notch 642 is located approximately in the center in the X direction on the side opposite the side surface 30c. The base 640 and the pair of extensions 641 define the notch 642.

As described above, the relay wiring 65 is arranged alongside the N wiring 64, specifically the base 640, in the Y direction. In the Y direction, the relay wiring 65 is arranged close to the side surface 30c of the sealing body 30, and the base 640 is arranged close to the side surface 30d. The relay wiring 65 is arranged between a pair of extension portions 641 in the X direction. The relay wiring 65 is sandwiched between the pair of extension portions 641. The relay wiring 65 is arranged within the cutout 642. The relay wiring 65 is arranged with a predetermined distance (gap) between it and the N wiring 64. In a plan view, part of the relay wiring 65 overlaps the P wiring 54, and another part overlaps the relay wiring 55.

As shown in FIG. 15, the relay wiring 65 overlaps the semiconductor element 40H in a planar view. In other words, the semiconductor element 40H is disposed on the relay wiring 65. The source electrode 40S of the semiconductor element 40H is connected to the relay wiring 65. A more detailed example of the circuit pattern of the surface metal body 62 will be described later.

The back metal bodies 53, 63 are electrically isolated from the circuit including the semiconductor element 40 by the insulating substrates 51, 61. The back metal bodies 53, 63 are sometimes referred to as metal base substrates. Heat generated by the semiconductor element 40 is transferred to the back metal bodies 53, 63 via the front metal bodies 52, 62 and the insulating substrates 51, 61. The back metal bodies 53, 63 provide heat dissipation functionality. In this embodiment, the back metal bodies 53, 63 have a generally rectangular planar shape, and their outer contours nearly match those of the front metal bodies 52, 62. The back metal bodies 53, 63 are so-called solid conductors disposed over almost the entire back surface of the insulating substrates 51, 61. As described above, the linear expansion coefficient of the insulating substrates 51, 61 is adjusted by adding a filler, thereby suppressing warping even when the patterns on the front and back are different. Of course, the back surface metal bodies 53, 63 may be patterned so that they coincide with the front surface metal bodies 52, 62 in a plan view.

In this embodiment, the back surface metal bodies 53, 63 are arranged over almost the entire back surface of the corresponding insulating base material 51, 61. To further enhance the heat dissipation effect, at least one of the back surface metal bodies 53, 63 may be exposed from the sealing body 30. In this embodiment, the back surface metal body 53 is exposed from one surface 30a of the sealing body 30, and the back surface metal body 63 is exposed from the back surface 30b. The exposed surface of the back surface metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back surface metal body 63 is approximately flush with the back surface 30b. The back surface metal bodies 53, 63 form the back surfaces 50b, 60b of the substrates 50, 60.

The conductive spacer 70 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the substrate 60. For example, the conductive spacer 70 ensures the height required to electrically connect the corresponding signal terminal 93 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, providing wiring and heat dissipation functions. The conductive spacer 70 contains a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plated film on its surface. The conductive spacer 70 is a generally rectangular columnar body that is approximately the same size as the source electrode 40S in a plan view.

The conductive spacers 70 are sometimes referred to as terminals, terminal blocks, or metal blocks. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the semiconductor device 20 includes four conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40.

The arm connection portion 80 electrically connects the relay wiring 55, 65. In other words, the arm connection portion 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connection portion 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. The arm connection portion 80 is provided in the overlapping area of the relay wiring 55 and the relay wiring 65 in a plan view. In this embodiment, the arm connection portion 80 is configured with a joint portion 81 and a bonding material 103, which will be described later.

The joint portion 81 is a metal columnar body provided separately from the surface metal bodies 52, 62. Such a joint portion 81 is sometimes referred to as a joint terminal. In the Z direction, a bonding material 103 is interposed between one end of the joint portion 81 and the relay wiring 55, and a bonding material 103 is interposed between the other end and the relay wiring 65.

Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may not include the joint portion 81. In other words, the arm connection portion 80 may include only the bonding material 103.

The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to external equipment. The external connection terminals 90 are formed using a metal material with good conductivity, such as copper. The external connection terminals 90 are, for example, plate material. The external connection terminals 90 are sometimes called leads. The external connection terminals 90 include a power supply terminal 91, an output terminal 92, and a signal terminal 93. The power supply terminal 91 includes a P terminal 91P and an N terminal 91N. The P terminal 91P, the N terminal 91N, and the output terminal 92 are main terminals electrically connected to the main electrodes of the semiconductor element 40. The signal terminals 93 include a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

The power supply terminal 91 is an external connection terminal 90 that is electrically connected to the power supply lines 7 and 8 described above. The P terminal 91P is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 91P is sometimes referred to as the positive terminal or high-potential power supply terminal. The P terminal 91P is connected to the P wiring 54 of the surface metal body 52. In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H.

The P terminal 91P is connected to the P wiring 54 near one end in the Y direction. The P terminal 91P extends in the Y direction from the connection (joint) with the P wiring 54 and protrudes outside the sealing body 30 from near the center of the side surface 30c in the Z direction. The semiconductor device 20 of this embodiment has two P terminals 91P. As shown in FIG. 11 , one P terminal 91P is connected to one of the pair of extension portions 542, and the other is connected to the other of the pair of extension portions 542. The P terminal 91P is located near the notch 540, i.e., toward the inside, in each extension portion 542 so as to be adjacent to the N terminal 91N in plan view. The two P terminals 91P are arranged side by side in the X direction. The two P terminals 91P are located at approximately the same position in the Z direction.

The N terminal 91N is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 91N is sometimes referred to as the negative terminal or low-potential power supply terminal. The N terminal 91N is connected to the N wiring 64 of the surface metal body 62. In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L.

The N terminal 91N is connected to the N wiring 64 near one end in the Y direction. The N terminal 91N extends in the Y direction from the junction with the N wiring 64 and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 has two N terminals 91N. As shown in Figure 15 and other figures, one of the N terminals 91N is connected to one of a pair of extension portions 641, and the other is connected to the other of the pair of extension portions 641. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged at approximately the same position in the Z direction.

The two N terminals 91N are arranged outside the two P terminals 91P in the X direction. In a plan view, one of the N terminals 91N is arranged near one of the P terminals 91P, and the other N terminal 91N is arranged near the other P terminal 91P. The N terminal 91N and P terminal 91P that are adjacent in the X direction have their sides facing each other in a portion that includes the portion protruding from the sealing body 30.

The output terminal 92 is electrically connected to the winding 3a (stator coil) of the corresponding phase of the motor generator 3. The output terminal 92 is sometimes referred to as an O terminal, an AC terminal, etc. As shown in Figures 3 and 7, the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 on the substrate 50. In other words, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

The output terminal 92 is connected to the relay wiring 55 near one end in the Y direction. The output terminal 92 extends in the Y direction from the joint with the relay wiring 55 and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92. One of the output terminals 92 is connected to one of the pair of extension portions 552, and the other is connected to the other of the pair of extension portions 552. The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are arranged at approximately the same position in the Z direction.

The signal terminal 93 is electrically connected to a drive circuit (driver), not shown. The signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H via a connecting member such as a bonding wire 110. The number of signal terminals 93H is not particularly limited. The signal terminals 93H need only include a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The semiconductor device 20 of this embodiment has two signal terminals 93H. One of the signal terminals 93H is a terminal for the gate electrode. The gate electrode pads 40P of the two semiconductor elements 40H are electrically connected to the signal terminal 93H for the gate electrode. The signal terminal 93H is positioned so as to overlap the notch 540 of the P wiring 54 in a plan view. The joint portion of the signal terminal 93H with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. The two signal terminals 93H are arranged side by side in the X direction.

The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110 and protrudes outside the sealing body 30 from near the center of the side surface 30c in the Z direction. At least a portion of the protruding portion of the signal terminal 93H extends in the same direction as the power terminal 91. The signal terminal 93H is arranged between the two P terminals 91P in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30c are arranged in the following order in the X direction: N terminal 91N, P terminal 91P, two signal terminals 93H, P terminal 91P, and N terminal 91N.

The signal terminals 93L are electrically connected to pads 40P of the semiconductor element 40L via connecting members such as bonding wires 110. The number of signal terminals 93L is not particularly limited. The signal terminals 93L need only include a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40L. The semiconductor device 20 of this embodiment has four signal terminals 93L. One of the signal terminals 93L is a terminal for the gate electrode. The gate electrode pads 40P of two semiconductor elements 40L are electrically connected to the signal terminal 93L for the gate electrode. The signal terminal 93L is positioned so as to overlap the notch 550 of the relay wiring 55 in a plan view. The joint portion of the signal terminal 93L with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. The four signal terminals 93L are arranged horizontally in the X direction.

The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110 and protrudes from the sealing body 30 near the center of the side surface 30d in the Z direction. At least a portion of the protruding portion of the signal terminal 93L extends in the same direction as the output terminal 92. The signal terminal 93L is arranged between the two output terminals 92 in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30d are arranged in the following order in the X direction: the output terminal 92, the four signal terminals 93L, and the output terminal 92.

The drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 via a bonding material 100. The source electrode 40S of the semiconductor element 40 is bonded to the conductive spacer 70 via a bonding material 101. The conductive spacer 70 is bonded to the surface metal body 62 via a bonding material 102. The joint portion 81 is bonded to the metal bodies 52, 62 via a bonding material 103. Of the external connection terminals 90, the main terminals, the P terminal 91P, the N terminal 91N, and the output terminal 92, are bonded to the corresponding surface metal bodies 52, 62 via a bonding material 104.

The bonding materials 100-104 are electrically conductive. For example, solder can be used as the bonding materials 100-104. One example of solder is a multi-element lead-free solder containing Cu, Ni, and the like in addition to Sn. Instead of solder, a sintered bonding material such as sintered silver may be used. The P terminal 91P, N terminal 91N, and output terminal 92 may be bonded directly to the corresponding surface metal bodies 52, 62 without using the bonding material 104. The P terminal 91P, N terminal 91N, and output terminal 92 may be bonded directly to the surface metal bodies 52, 62 by, for example, ultrasonic welding, friction stir welding, or laser welding. If the joint portion 81 is provided separately from the substrates 50, 60, the joint portion 81 may be bonded directly to the surface metal bodies 52, 62.

As described above, in the semiconductor device 20, the multiple semiconductor elements 40 that make up one phase of the upper and lower arm circuits 9 are sealed by the sealing body 30. The sealing body 30 integrally seals the multiple semiconductor elements 40, a portion of the substrate 50, a portion of the substrate 60, multiple conductive spacers 70, arm connection portions 80, and portions of the external connection terminals 90. The sealing body 30 seals the insulating substrates 51, 61 and surface metal bodies 52, 62 on the substrates 50, 60.

The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the opposing substrates 50 and 60. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is approximately flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is approximately flush with the back surface 30b of the sealing body 30. Because the back surfaces 50b and 60b are exposed, heat dissipation can be improved.

<Manufacturing method>
Next, an example of a method for manufacturing the semiconductor device 20 will be described with reference to Fig. 10. In Fig. 10, the substrate 50 and the substrate 60 are shown facing each other to make the subsequent assembly easier to understand.

First, the semiconductor element 40, substrates 50 and 60, conductive spacer 70, joint portion 81, and lead frame 94 are prepared. As shown in Figure 10, the lead frame 94 has external connection terminals 90. The lead frame 94 is formed by processing a metal plate, such as by pressing. The external connection terminals 90 are supported by the outer frame 94b via tie bars 94a.

Next, the semiconductor element 40, joint portion 81, and external connection terminal 90 are bonded (connected) to the substrate 50. Additionally, the conductive spacer 70 is bonded to the semiconductor element 40.

At this time, the lead frame 94 and semiconductor element 40 are placed on the substrate 50. A conductive spacer 70 is also placed on the source electrode 40S of the semiconductor element 40. The lead frame 94 is positioned so that a portion of each of the external connection terminals 90 overlaps the substrate 50 in a plan view. Specifically, the P terminal 91P and N terminal 91N are positioned so that they overlap the P wiring 54 of the surface metal body 52, and the output terminal 92 overlaps the relay wiring 55. The signal terminal 93H is positioned so that it overlaps the insulating substrate 51 exposed from the cutout 540, and the signal terminal 93L is positioned so that it overlaps the insulating substrate 51 exposed from the cutout 550.

Then, the drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 using bonding material 100. The source electrode 40S is bonded to the conductive spacer 70 using bonding material 101. The joint portion 81 is bonded to the surface metal body 52 using bonding material 103. The P terminal 91P and the output terminal 92 are bonded to the surface metal body 52 using bonding material 104. For example, in the case of solder, bonding can be performed all at once by reflow. Figure 10 shows this bonded state.

Next, the pad 40P of the semiconductor element 40H and the signal terminal 93H are electrically connected by a bonding wire 110. Similarly, the pad 40P of the semiconductor element 40L and the signal terminal 93L are electrically connected by a bonding wire 110.

Next, the substrate 60 is bonded (connected). The source electrode 40S of the semiconductor element 40 is bonded to the surface metal body 62 via a bonding material 102. The joint portion 81 is bonded to the surface metal body 62 via a bonding material 103. The N terminal 91N is bonded to the surface metal body 62 via a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow.

Next, the encapsulant 30 is molded using the transfer molding method. Although not shown in the figures, in this embodiment, the encapsulant 30 is molded so that it completely covers the substrates 50 and 60, and is then cut after molding. The encapsulant 30 is cut along with a portion of the back surface metal bodies 53 and 63 of the substrates 50 and 60. This exposes the back surfaces 50b and 60b. The back surface 50b is approximately flush with one surface 30a of the encapsulant 30, and the back surface 60b is approximately flush with the back surface 30b. Note that the encapsulant 30 may be molded with the back surfaces 50b and 60b pressed against the cavity wall of the molding die and in close contact. In this case, the back surfaces 50b and 60b are exposed from the encapsulant 30 when the encapsulant 30 is molded. This eliminates the need for cutting after molding.

Next, unnecessary portions of the lead frame 94, such as the tie bars 94a and the outer peripheral frame 94b, are removed. This completes the semiconductor device 20.

<Location>
Next, the positional relationship between the semiconductor element 40, the circuit patterns of the surface metal bodies 52 and 62, the arm connection portion 80, and the external connection terminals 90 connected to the circuit patterns will be described with reference to FIGS. 14 and 15 . FIG. 14 is a diagram showing the arrangement of the circuit pattern of the surface metal body 52, the semiconductor element 40, and the terminals. FIG. 15 is a diagram showing the arrangement of the circuit pattern of the surface metal body 62, the semiconductor element 40, and the terminals. For convenience, FIGS. 14 and 15 only show the external connection terminals 90 connected to the circuit patterns. In FIG. 14 , the placement area of the semiconductor element 40 is indicated by a letter D to clearly show the main electrode (drain electrode 40D) connected to the surface metal body 52. Similarly, in FIG. 15 , the placement area of the semiconductor element 40 is indicated by a letter S to clearly show the main electrode (source electrode 40S) connected to the surface metal body 62.

The imaginary line CL1 shown in Figure 14 is an imaginary line that passes through the midpoints of the two semiconductor elements 40 that make up one arm. The imaginary line CL1 passes through the midpoint (center) of the two semiconductor elements 40 in the arrangement direction, and extends in the Y direction. The imaginary line CL1 is, for example, a line that passes through the midpoint of two semiconductor elements 40H. Instead of semiconductor element 40H, the imaginary line CL1 may also be a line that passes through the midpoint of semiconductor element 40L.

As shown in FIG. 14, the arrangement of the two semiconductor elements 40H is approximately line-symmetrical with respect to the imaginary line CL1. Similarly, the arrangement of the two semiconductor elements 40L is also approximately line-symmetrical with respect to the imaginary line CL1. Here, approximately line-symmetrical allows for errors of the order of manufacturing variations. The circuit pattern of the surface metal body 52 is also approximately line-symmetrical with respect to the imaginary line CL1. In other words, the P wiring 54 and the relay wiring 55 are each approximately line-symmetrical with respect to the imaginary line CL1.

The arrangement of the arm connection portion 80 connected to the relay wiring 55 is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the external connection terminal 90 connected to the surface metal body 52 is also approximately line-symmetrical with respect to the imaginary line CL1. In other words, the arrangement of the two P terminals 91P is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the two output terminals 92 is also approximately line-symmetrical with respect to the imaginary line CL1.

As in Figure 14, the virtual line CL1 is shown in Figure 15. The arrangement of the semiconductor elements 40H, 40L is the same as in Figure 14. As shown in Figure 15, the circuit pattern of the surface metal body 62 is also approximately line-symmetrical with respect to the virtual line CL1. That is, the N wiring 64 and the relay wiring 65 are each approximately line-symmetrical with respect to the virtual line CL1. The arrangement of the arm connection portion 80 connected to the relay wiring 65 is also approximately line-symmetrical with respect to the virtual line CL1, as in Figure 14. The arrangement of the two N terminals 91N, which are external connection terminals 90 connected to the surface metal body 62, is also approximately line-symmetrical with respect to the virtual line CL1.

<Circuit pattern>
Next, the circuit pattern of the surface metal body 62 will be described in more detail with reference to Fig. 15. The dashed dotted lines shown in Fig. 15 indicate the boundaries of the respective regions.

As described above, the surface metal body 62 of the substrate 60 has an N wiring 64 and a relay wiring 65. The N wiring 64 has a base 640 and a pair of extension portions 641. The pair of extension portions 641 extend from the base 640 in the Y direction toward the side surface 30c of the sealing body 30. The N wiring 64 defines the outer contour of the surface metal body 62. The relay wiring 65 is sandwiched between the pair of extension portions 641. The relay wiring 65 is arranged within the notch 642 of the N wiring 64.

15, the relay wiring 65 has an end 650 as one end in the Y direction. The end 650 is the end on the base 640 side in the Y direction. On the other hand, the base 640 of the N wiring 64 has an opposite side 640a to the end 650. The opposite side 640a is the portion of the base 640 between the pair of extension portions 641. The base 640 also has an arrangement region 640b for the semiconductor element 40L. As shown by the two-dot chain line in FIG. 15, the arrangement region 640b is defined by the outline of the semiconductor element 40L. The arrangement region 640b includes an area overlapping the semiconductor element 40L in a planar view, and also includes the area between the elements when multiple semiconductor elements 40L are included. The area between the elements is the area where the semiconductor elements 40L face each other in the arrangement direction of the semiconductor elements 40L.

Here, the lengths L1, L2, and L3 in the X direction are defined as follows: Length L1 is the length of the end 650 of the relay wiring 65 as shown in FIG. 15. Length L2 is the length of the opposing side 640a of the base 640. Length L3 is the length of the placement area 640b on the base 640. In this embodiment, the relationship L1<L2<L3 is satisfied.

The relay wiring 65 of this embodiment has a reduced-width portion 651a. The reduced-width portion 651a includes the end portion 650. The reduced-width portion 651a is a portion within a predetermined range in the Y direction from the end portion 650. The length in the X direction of the reduced-width portion 651a, i.e., the width, is smallest at the end portion 650. In the reduced-width portion 651a, the width W1 at an arbitrary first position is equal to or smaller than the width W2 at a second position that is farther from the end portion 650 than the first position.

The width of the reduced width portion 651a may be reduced in stages, for example, in the Y direction by a predetermined length. In other words, the end of the reduced width portion 651a in the X direction may change in a stepped manner. In this embodiment, the length of the reduced width portion 651a in the X direction becomes shorter the closer it is to the base 640. In other words, the width of the reduced width portion 651a continuously reduces toward the base 640. The arm connection portion 80 is disposed in the reduced width portion 651a.

The relay wiring 65 may have only the reduced width portion 651a including the end portion 650. In this case, the semiconductor element 40H is also disposed in the reduced width portion 651a. In this embodiment, the relay wiring 65 has a constant width portion 651b. The constant width portion 651b is continuous with the reduced width portion 651a and has a constant width over a predetermined range in the Y direction. The semiconductor element 40H is disposed in the constant width portion 651b.

The relay wiring 65 of this embodiment further includes a reduced width portion 651c. The reduced width portion 651c includes an end portion 652 opposite the end portion 650. The reduced width portion 651c is connected to the constant width portion 651b, opposite the reduced width portion 651a. The width of the reduced width portion 651c is smallest at the end portion 652. In the reduced width portion 651c, the width at an arbitrary first position is equal to or smaller than the width at a second position that is farther from the end portion 652 than the first position. In this embodiment, the width of the reduced width portion 651c continuously decreases toward the end portion 652. In the relay wiring 65, the reduced width portions 651a and 651c become narrower the further away they are from the constant width portion 651b.

In this embodiment, the distance between the N wiring 64 and the relay wiring 65 is approximately constant throughout the entire opposing region. The extension portions 641 of the N wiring 64 are patterned so that the distance between them and the relay wiring 65 is approximately constant. Each extension portion 641 has a widened portion 641a, a fixed-width portion 641b, and a widened portion 641c.

The widened portion 641a is connected to the base 640 and extends over a predetermined range in the Y direction from the boundary with the base 640. The length in the X direction of the widened portion 641a, i.e., the width, is greatest at the boundary with the base 640. In the widened portion 641a, the width at any first position is equal to or greater than the width at a second position that is farther from the base 640 than the first position. In this embodiment, the width of the widened portion 641a continuously increases toward the base 640. The constant-width portion 641b is connected to the widened portion 641a and has a constant width over a predetermined range in the Y direction. The constant-width portion 641b faces the constant-width portion 651b of the relay wiring 65.

The widened portion 641c is opposite the widened portion 641a and is connected to the constant width portion 641b. The widened portion 641a extends to a position closer to the side surface 30c than the narrowed portion 651c. The widened portion 641c includes the tip 641d of the extension portion 641. The width of the widened portion 641c is greatest at the tip 641d. In the widened portion 641c, the width at any first position is equal to or greater than the width at a second position that is farther from the tip 641d than the first position. In this embodiment, the width of the widened portion 641c continuously increases toward the tip 641d in the portion facing the narrowed portion 651c. In the widened portion 641c, the portion closer to the tip 641d than the facing portion has a constant width. In the N wiring 64, part of the widened portion 641c and the widened portion 641a become wider the further away from the fixed width portion 641b.

<Current path>
Next, the current paths will be described with reference to FIGS. 16 to 20. FIG. 16 is a diagram showing a PN current loop of a reference example. In the reference example, the reference symbols of each element are those of the related elements of the semiconductor device 20 with an r added to the end. The configuration of the reference example is substantially the same as that of the semiconductor device 20, except for the number of signal terminals 93Lr and the patterns of the N wirings 64r and relay wirings 65r. FIG. 17 is a diagram showing a PN current loop in the semiconductor device 20 of this embodiment. FIG. 18 is a diagram showing a PN current loop in a side view of the semiconductor device 20 as seen from the X direction. The PN current loop refers to the loop shape of the current path from the P terminal 91P to the N terminal 91N.

When examining inductance, the PN current loop of P terminal 91P → P wiring 54 → semiconductor element 40H → relay wiring 65 → arm connection portion 80 → relay wiring 55 → semiconductor element 40L → N wiring 64 → N terminal 91N is taken into consideration. For this reason, to make the PN current loop easier to understand, a continuous solid line is shown from P terminal 91P to N terminal 91N. In reality, semiconductor elements 40H and 40L are controlled so that they are not turned on at the same time. For convenience, only the current path for one semiconductor element 40H and one semiconductor element 40L is shown, but the same applies to the other semiconductor element 40H and the other semiconductor element 40L.

Figures 19 and 20 show the results of electromagnetic field simulations. Figure 19 shows the current density for the reference example shown in Figure 18. Figure 20 shows the current density for the configuration of this embodiment shown in Figure 16. The conditions for the electromagnetic field simulations were the same for both examples, except for the different circuit patterns of the surface metal body 62. In Figures 19 and 20, the lower the current density, the coarser (lighter color) it is, and the higher the current density, the denser (darker color).

As shown in FIG. 16 , in the semiconductor device 20r of the reference example, the relay wiring 65r has a generally rectangular planar shape. The length of the end 650r of the relay wiring 65r is approximately equal to the length of the placement area 640br of the semiconductor element 40Lr at the base 640r. The length of the opposing side 640ar at the base 640r is longer than the placement area 640br. Therefore, as shown by the solid arrows in FIG. 16 , current enters the generally rectangular semiconductor element 40Lr from one side 400r and exits from another side 401r. Side 400r is the side facing the relay wiring 65r. Side 401r is the side opposite the side where the two semiconductor elements 40Lr face each other. As such, the current flows outward in the X direction from the semiconductor element 40Lr, resulting in a large PN current loop. The simulation results shown in Figure 19 also clearly show that current flows from the semiconductor element 40Lr through the base portion 640r outward in the X direction.

In contrast, in the semiconductor device 20 of this embodiment, as described above, the N wiring 64 and relay wiring 65 are patterned and satisfy a predetermined positional relationship with the semiconductor element 40L. Due to this positional relationship, as shown in FIG. 17, the N wiring 64 (extension portion 641) is also present above one side 400 of the semiconductor element 40L in a planar view. Side 400 is the side opposite the relay wiring 65. Therefore, current enters from side 400 of the semiconductor element 40L and exits from the same side 400. Of the current flowing from the semiconductor element 40L toward the N terminal 91N, the Y-direction component increases, particularly near the semiconductor element 40L. The simulation results shown in FIG. 20 also clearly show that the current flows from the semiconductor element 40L with a Y-direction component.

In this way, the current flowing through the N wiring 64 approaches the relay wiring 65, shortening the current path through the N wiring 64, i.e., the current path between the semiconductor element 40L and the N terminal 91N. Therefore, the PN current loop is smaller than in the reference example. As shown in Figure 18, the PN current loop is also small in the Z direction. The P wiring 54 and the N wiring 64 face each other in the Z direction. Furthermore, the relay wiring 55 and the N wiring 64 face each other in the Z direction.

<Summary of First Embodiment>
If the inductance of the main circuit wiring is high, the surge voltage will be large. If the semiconductor element is made thicker to ensure the withstand voltage, steady-state loss will increase. To reduce steady-state loss, the element area must be increased. Surge voltage can also be reduced by reducing the switching speed. In this case, the output to the motor generator will be reduced. In this way, if the inductance is high, the size of the semiconductor element will be large or the output will be small.

When components through which currents flow in opposite directions are placed opposite each other, the magnetic flux generated by the currents cancels out, reducing inductance. When the PN current loop in the main circuit wiring is smaller, components through which currents flow in opposite directions are closer to each other, enhancing the magnetic flux cancellation effect and reducing inductance.

In this embodiment, the semiconductor elements 40H and 40L are arranged side by side in the Y direction, and the arm connection portion 80 is disposed between the semiconductor elements 40H and 40L. Of the main terminals, the power supply terminals 91 (91P, 91N) are drawn out in the same direction. In addition, in the Y direction, the P wiring 54 is disposed on the power supply terminal 91 side, and the relay wiring 55 is disposed on the opposite side. In the Y direction, the relay wiring 65 is disposed on the power supply terminal 91 side, and the base 640 of the N wiring 64 is disposed on the opposite side. The extension portion 641 of the N wiring 64 extends toward the power supply terminal 91 so as to sandwich the relay wiring 65.

This configuration reduces the size of the PN current loop, thereby reducing the inductance of the main circuit wiring. For example, arranging the P terminal 91P and the N terminal 91N side by side reduces inductance. The relay wiring 65 and the N wiring 64 are also arranged (side by side) with a predetermined distance between them, thereby reducing inductance. Furthermore, the extension portion 641 of the N wiring 64 faces the P wiring 54, thereby reducing inductance.

In this embodiment, the surface metal body 52 of the substrate 50 and the surface metal body 62 of the substrate 60 provide wiring functionality for the semiconductor element 40. The surface metal bodies 52, 62 are sealed by the sealing body 30. Because there is no need to ensure a creepage distance as in the past, the N wiring 64 and the relay wiring 65 can be placed close to each other. This enhances the effect of magnetic flux cancellation and further reduces inductance.

Furthermore, as shown in FIG. 15, the length L1 of the end 650 of the relay wiring 65, the length L2 of the opposing side 640a of the base 640, and the length L3 of the placement area 640b of the base 640 for the semiconductor element 40L satisfy the relationship L1 < L2 < L3. By satisfying this dimensional relationship, as described above, current enters from one side 400 of the semiconductor element 40L and exits from the same side 400. Of the current flowing from the semiconductor element 40L to the N terminal 91N, the Y-direction component increases, particularly near the semiconductor element 40L. This shortens the current path through the N wiring 64, i.e., the current path between the semiconductor element 40L and the N terminal 91N, and reduces the size of the PN current loop. This further reduces the inductance of the main circuit wiring.

Furthermore, the higher the current frequency, the more the current concentrates on the opposing side of the extension portion 641 of the N wiring 64 and the relay wiring 65 due to the skin effect. This makes it possible to further reduce the PN current loop, and therefore the inductance.

In this embodiment, as shown in FIG. 15, the relay wiring 65 has a reduced width portion 651a. This allows the width of the portion of the extension portion 641 that faces the reduced width portion 651a to be increased. This makes it possible to suppress heat generation due to current flow without changing the size of the surface metal body 62, or ultimately the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

In particular, in this embodiment, the length of the reduced width portion 651a in the X direction becomes shorter the closer it is to the base 640. In other words, the width of the reduced width portion 651a continuously decreases toward the base 640. The reduced width portion 651a of the relay wiring 65 has a tapered shape. This makes it easier to maintain a constant distance between the relay wiring 65 and the extension portion 641. In other words, the extension portion 641 can be brought closer to the relay wiring 65, making the PN current loop smaller. Furthermore, the width of the extension portion 641 can be increased to suppress heat generation.

In this embodiment, the relay wiring 65 has a constant-width portion 651b. The semiconductor element 40H is disposed in the constant-width portion 651b. The relay wiring 65, which has the reduced-width portion 651a and the constant-width portion 651b, has a shape identical to or similar to a baseball home base in a plan view. This allows the width of the extension portion 641 to be wider than in a configuration in which the semiconductor element 40H is disposed in the reduced-width portion 651a. Therefore, heat generation due to current flow can be suppressed without changing the size of the surface metal body 62, or ultimately the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

In this embodiment, the semiconductor device 20 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged side by side in the X direction. Similarly, the two semiconductor elements 40L are arranged side by side in the X direction. In this way, the semiconductor elements 40 constituting one arm are arranged side by side in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the semiconductor elements 40H and 40L. In the X direction, a pair of extension portions 641 sandwich the relay wiring 65. This makes it possible to suppress current bias.

The semiconductor device 20 may be provided with a single N terminal 91N whose tip is branched into two so as to connect individually to the pair of extension portions 641. In this embodiment, the semiconductor device 20 is provided with two N terminals 91N, which are individually connected to the pair of extension portions 641. This makes it easy to arrange another external connection terminal 90 between the two N terminals 91N. Since there is no need to avoid the external connection terminal 90 arranged between them, the size can be made more compact.

The semiconductor device 20 may include only one P terminal 91P. In this embodiment, the semiconductor device 20 includes two P terminals 91P. The N terminal 91N, P terminal 91P, signal terminal 93H, P terminal 91P, and N terminal 91N are arranged in this order in the X direction. The P terminal 91P and N terminal 91N are arranged side by side at both ends in the X direction. This makes it easier to reduce the size of the PN current loop. Furthermore, because the external connection terminals 90 are arranged with regularity in the X direction, it is easier to ensure linear symmetry for the circuit patterns of the semiconductor element 40, surface metal bodies 52 and 62, and external connection terminals 90, as described above. This makes it possible to suppress current bias.

In this embodiment, the P terminal 91P and N terminal 91N protrude from side surface 30c of the sealing body 30, and the output terminal 92 protrudes from side surface 30d. In this way, the P terminal 91P and N terminal 91N connected to the smoothing capacitor 5 are drawn out in the same direction, and the output terminal 92 is drawn out in the opposite direction. This improves connectivity with the smoothing capacitor 5 and connectivity with the motor generator 3. Furthermore, arranging the P terminal 91P and N terminal 91N in parallel reduces inductance. This terminal arrangement makes it easier to reduce the size of the PN current loop.

<Modification>
Although an example in which two semiconductor elements 40H and 40L are provided has been shown, this is not limiting. Three or more semiconductor elements may be provided. For example, three semiconductor elements 40H may be arranged side by side in the X direction, and three semiconductor elements 40L may be arranged side by side in the X direction. The circuit pattern of the front surface metal body 62 and the arrangement of the semiconductor elements 40 are not limited to the above example. For example, they may be as shown in FIGS. 21 and 22. For convenience, in FIGS. 21 and 22, the sealing body 30 on the back surface 30b side of the insulating base material 51 is omitted. Furthermore, the insulating base material 61 and the back surface metal body 63 of the substrate 60 are omitted. As in FIG. 17, the PN current loop is indicated by a solid arrow. In FIGS. 21 and 22, the semiconductor device 20 includes two signal terminals 93L.

In FIG. 21, the semiconductor device 20 includes two arm connection portions 80. The relay wiring 65 has a generally rectangular shape in plan view. The two arm connection portions 80 are arranged side by side in the X direction near the end portion 650. The distance between the two semiconductor elements 40L is greater than in the example described above (see FIG. 17). The length of the placement region 640b of the semiconductor element 40L is longer than in the example described above. This satisfies the relationship L1 < L2 < L3. Therefore, current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. Even with this configuration, the current path through the N wiring 64 is shorter, and the PN current loop can be reduced. However, the configuration shown in FIG. 17 allows for a wider width for the N wiring 64, particularly the width of the extension portion 641. Furthermore, the configuration shown in FIG. 17 requires only one arm connection portion 80.

In Figure 22, the semiconductor device 20 includes only one semiconductor element 40H, 40L. In this example, the placement area 640b coincides with the outer contour of the semiconductor element 40L. The length in the X direction of each semiconductor element 40H, 40L is longer than in the example described above (see Figure 17). This satisfies the relationship L1 < L2 < L3. Therefore, current enters from side 400 of the semiconductor element 40L and exits from the same side 400. Even with this configuration, the current path through the N wiring 64 is shortened, making it possible to reduce the PN current loop.

The arrangement of the external connection terminals 90 is not limited to the example above. For example, the P terminal 91P may be arranged on the outside in the X direction, and the N terminal 91N on the inside. In this case, the semiconductor element 40 and circuit pattern are also reversed, as shown in Figures 23 and 24. Figure 23 shows a substrate 50. Figure 24 shows a substrate 60.

As shown in FIG. 23, the circuit pattern of the surface metal body 52 of the substrate 50 is the same as the circuit pattern of the surface metal body 62 of the substrate 60 shown in FIG. 15. The P wiring 54 has the same pattern as the N wiring 64 shown in FIG. 15. The semiconductor element 40H is disposed on the N wiring 64. The relay wiring 55 has the same pattern as the relay wiring 65 shown in FIG. 15. The semiconductor element 40L and the arm connection portion 80 are disposed on the relay wiring 55.

As shown in FIG. 24, the circuit pattern of the surface metal body 62 of the substrate 60 is the same as the circuit pattern of the surface metal body 52 of the substrate 50 shown in FIG. 14. The N wiring 64 has the same pattern as the P wiring 54 shown in FIG. 14. The semiconductor element 40L is disposed on the N wiring 64. The relay wiring 65 has the same pattern as the relay wiring 55 shown in FIG. 14. The semiconductor element 40H and the arm connection portion 80 are disposed on the relay wiring 65.

In the configurations shown in Figures 23 and 24, the relationship between the first and second elements described above is reversed. The semiconductor element 40L is the first element, and the semiconductor element 40H is the second element. The source electrode 40S is the first main electrode, and the drain electrode 40D is the second main electrode. The substrate 60 is the first substrate, and the substrate 50 is the second substrate. The insulating substrate 61 is the first insulating substrate, the front surface metal body 62 is the first front surface metal body, and the back surface metal body 63 is the first back surface metal body. The insulating substrate 51 is the second insulating substrate, the front surface metal body 52 is the second front surface metal body, and the back surface metal body 53 is the second back surface metal body.

Second Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress transient current imbalance during switching, as described in this embodiment, the surface metal body to which multiple semiconductor elements are connected in parallel may have a predetermined structure.

<Semiconductor Device>
First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 25 corresponds to Fig. 8.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 15). The semiconductor device 20 constitutes one phase of the upper and lower arm circuits 9. As shown in Figure 25, the semiconductor device 20 includes multiple semiconductor elements 40, including two semiconductor elements 40H that serve as upper arm elements, substrates 50 and 60 that are arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode on the high potential side of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode on the low potential side of the semiconductor element 40. Although not shown, the semiconductor device 20 also includes two semiconductor elements 40L that serve as lower arm elements.

As in the previous embodiment, the surface metal body 62 is substantially symmetrical with respect to the virtual line CL1. As shown in FIG. 25 , in this embodiment, the relay wiring 65 of the surface metal body 62 has a slit 653. As will be described later, the N wiring 64 has a slit 643.

<Suppression effect of transient current imbalance>
Next, the effect of suppressing transient current imbalance during switching will be described with reference to Figures 26 and 27. Figure 26 is an equivalent circuit diagram of two semiconductor elements 40 (MOSFETs 11) that form one arm. Figure 27 is an image diagram (potential diagram) that clearly shows the potentials.

26 and 27, one of the parallel-connected MOSFETs 11 is shown as MOSFET1, and the other is shown as MOSFET2. The inductance of the wiring on the drain electrode side (hereinafter referred to as drain wiring) is shown as Ld, and the inductance of the wiring on the source electrode side (hereinafter referred to as source wiring) is shown as Ls. The gate potential is shown as Vg, the potential of the source electrode of MOSFET1 as Vks1, the potential of the source electrode of MOSFET2 as Vks2, and the common source potential as Vs. The midpoint potential between the potentials Vks1 and Vks2 is shown as Vm. The midpoint potential Vm is constant.
Vm=(Vks1+Vks2)/2.

The gate voltage of MOSFET1 is denoted as Vgs1, and the gate voltage of MOSFET2 is denoted as Vgs2. The current flowing through MOSFET1 when it is turned on is denoted as I1, and the voltage generated across inductance Ls when current I1 flows is denoted as ΔVs1. Similarly, the current flowing through MOSFET2 when it is turned on is denoted as I2, and the voltage generated across inductance Ls when current I2 flows is denoted as ΔVs2.
ΔVs1=Ls×dI1/dt.
ΔVs2=Ls×dI2/dt.

Assuming that a current I2 greater than current I1 (I2 > I1) flows due to variations in the characteristics of MOSFET 11, as shown in Figure 26. At this time, the voltage ΔVs generated across inductance Ls is ΔVs1 < ΔVs2. In other words, as shown in Figure 27, the source electrode potential Vks2 rises relative to the midpoint potential Vm, and potential Vks1 falls. Therefore, gate voltage Vgs1 > gate voltage Vgs2. Reducing gate voltage Vgs2 reduces current I2. In this way, source wiring inductance Ls functions to suppress transient current imbalances during switching caused by variations in the characteristics of semiconductor elements 40 (MOSFETs 11) connected in parallel.

However, if the inductance Ls of the source wiring is small, the function of suppressing the transient current imbalance described above is impaired. This causes bias in switching loss, making it necessary to include a margin in the thermal design.

<Circuit pattern on board>
Next, the circuit pattern of the front surface metal body 62 in the semiconductor device 20 of this embodiment will be described with reference to Fig. 28. Fig. 28 corresponds to Fig. 15. In Fig. 28, as in Fig. 15, the source electrode 40S is indicated as S in order to clarify the main electrode to which it is connected.

The N wiring 64 and relay wiring 65 are source wirings to which the source electrode 40S of the semiconductor element 40 is connected. The N wiring 64 differs from the pattern of the previous embodiment in that it has a slit 643. Similarly, the relay wiring 65 differs from the pattern of the previous embodiment in that it has a slit 653. Apart from the slits 643 and 653, the configuration is the same as that described in the previous embodiment.

The slit 643 penetrates the N wiring 64 in its thickness direction (Z direction). The slit 643 is provided in a position on the base 640 that overlaps the opposing regions of two semiconductor elements 40L. The opposing regions are regions where the semiconductor elements 40L face each other in the arrangement direction of the semiconductor elements 40L. In other words, the slit 643 is provided between the semiconductor elements 40L, which are the lower arm elements, in a plan view in the Z direction. The slit 643 is provided in the base 640 between the electrical connection portions with the semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction, which is the arrangement direction of the semiconductor elements 40H and 40L. The slit 643 opens to the opposing edge 640a of the base 640. The slit 643 is provided in approximately the center of the N wiring 64 in the X direction.

In this way, the slit 643 extends in the Y direction from the source electrode 40S of the semiconductor element 40L toward the side where the N terminal 91N, which is the main terminal, is located, i.e., the side where current flows. The slit 643 does not open to the end 640c of the base 640. The slit 643 is provided up to near the bottom end of the opposing region of the semiconductor element 40L. The slit 643 divides the N wiring 64 into an area where one semiconductor element 40L is connected and an area where another semiconductor element 40L is connected. The slit 643 separates the current path of the source electrode 40S of the semiconductor element 40L, i.e., the source current path.

The slit 653 penetrates the relay wiring 65 in its thickness direction (Z direction). The slit 653 is provided in the relay wiring 65 at a position that overlaps the opposing regions of the two semiconductor elements 40H. That is, the slit 653 is provided between the semiconductor elements 40H in a plan view. The slit 653 is provided in the relay wiring 65 between the electrical connection portions with the semiconductor elements 40H. The slit 653 extends in the Y direction from between the semiconductor elements 40H. The slit 653 opens at the end 652. The slit 653 extends from the end 652 across the space between the semiconductor elements 40H (the opposing region) and to the vicinity of the arm connection portion 80. The slit 653 is provided in approximately the center of the relay wiring 65 in the X direction.

In this way, the slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the arm connection portion 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side where current flows. The slit 653 does not open to the end portion 650. The slit 643 is provided up to just before the arm connection portion 80. The slit 653 divides the relay wiring 65 into an area where one of the semiconductor elements 40H is connected and an area where another is connected. The slit 653 separates the current path of the source electrode 40S of the semiconductor element 40H, i.e., the source current path.

<Summary of the Second Embodiment>
29 shows the source current paths. The solid arrows indicate the source current paths on the semiconductor element 40H side, and the dashed arrows indicate the source current paths on the semiconductor element 40L side. As described above, in this embodiment, the slits 643 and 653 are provided in the front surface metal body 62 to which the source electrode 40S, which is the main electrode on the low potential side, is connected.

The slits 643 are provided between adjacent semiconductor elements 40L in the N wiring 64 to which the semiconductor elements 40L are connected in parallel. The slits 643 divide the N wiring 64 and separate the source current paths of each semiconductor element 40L. This prevents currents (source currents) from flowing from the source electrodes 40S of the semiconductor elements 40L from merging near the source electrodes 40S. In other words, the merging point of the source currents is moved away from the source electrodes 40S in a planar view. Therefore, in a parallel circuit of two semiconductor elements 40L (MOSFETs 11), the inductance Ls of the source wiring can be increased compared to a configuration without the slits 643. Because the inductance Ls is large, transient current imbalances during switching can be suppressed even if there is variation (deviation) in the characteristics of the two semiconductor elements 40L. By providing the slits 643, transient current imbalances can be suppressed while maintaining high integration of the semiconductor elements 40L.

Similarly, the relay wiring 65 has a slit 653. The slit 653 is provided between the two semiconductor elements 40H. The slit 653 divides the relay wiring 65 and separates the source current paths of each semiconductor element 40H. This prevents the currents (source currents) from flowing from the source electrodes 40S of the semiconductor elements 40H from merging near the source electrodes 40S. In other words, the merging point of the source currents is moved away from the source electrodes 40S in a planar view. Therefore, in a parallel circuit of two semiconductor elements 40H, the inductance Ls of the source wiring can be increased compared to a configuration without the slit 653. Because the inductance Ls is large, transient current imbalance during switching can be suppressed even if there is variation (deviation) in the characteristics of the two semiconductor elements 40H. By providing the slit 653, transient current imbalance can be suppressed while maintaining high integration of the semiconductor elements 40H.

In this embodiment, the slit 643 extends from between adjacent semiconductor elements 40L in the Y direction toward the N terminal 91N. The slit 643 extends from the source electrode 40S of the semiconductor element 40L toward the current flow side. This allows the source current paths of each semiconductor element 40L to be separated by a longer distance. Therefore, in a parallel circuit of semiconductor elements 40L, the inductance Ls of the source wiring can be increased. In other words, the effect of suppressing transient current imbalance can be improved.

Similarly, slits 653 extend from between adjacent semiconductor elements 40H in the Y direction toward the arm connection portion 80. The slits 653 extend from the source electrodes 40S of the semiconductor elements 40H toward the current flowing side. This allows the source current paths of each semiconductor element 40L to be separated by a longer distance. Therefore, in a parallel circuit of semiconductor elements 40H, the inductance Ls of the source wiring can be increased. In other words, the effect of suppressing transient current imbalance can be improved.

Figure 30 is a cross-sectional view taken along line XXX-XXX in Figure 29. In this embodiment, the joint portion 81, the bonding material 103 connecting the joint portion 81 to the relay wiring 55, and the bonding material 103 connecting the joint portion 81 to the relay wiring 65 constitute the arm connection portion 80, which electrically connects the relay wirings 55, 65. The joint portion 81 is a separate member from the substrates 50, 60. The arm connection portion 80 electrically connects the relay wiring 65 connected to the source electrode 40S of the semiconductor element 40H and the relay wiring 55 connected to the drain electrode 40D of the semiconductor element 40L.

<Modification>
In the above example, the multiple semiconductor elements 40 include two each of the semiconductor elements 40H and 40L, but this is not limiting. A configuration including two of the semiconductor elements 40H and 40L and one of the other may also be used. In this case, a slit may be provided in one of the two wirings (64, 65) of the front surface metal body 62, which forms one arm by connecting the multiple semiconductor elements 40 in parallel. For example, in a configuration including two semiconductor elements 40H and one semiconductor element 40L, the slit 643 may not be provided in the N wiring 64, but the slit 653 may be provided in the relay wiring 65 to which the semiconductor element 40H is connected. In this way, the multiple semiconductor elements 40 may include two arm elements of at least one of the semiconductor elements 40H and 40L.

The number of semiconductor elements 40 connected in parallel is not limited to two. Three or more semiconductor elements 40 may be connected in parallel to form one arm. For example, in a configuration including three semiconductor elements 40H, slits 653 may be provided between adjacent semiconductor elements 40H in plan view for the three semiconductor elements 40H arranged side by side in the X direction. The multiple semiconductor elements 40 may include multiple arm elements of at least one of the semiconductor elements 40H, 40L. It may also include multiple arm elements of both, that is, multiple semiconductor elements 40H and multiple semiconductor elements 40L.

The arrangement of the N terminal 91N is not limited to the example described above. For example, the P terminal 91P may protrude from the side surface 30c of the sealing body 30, and the N terminal 91N may protrude from the side surface 30d. In this case, the pattern of the N wiring 64 will have a shape similar to that of the P wiring 54 or relay wiring 55. In other words, the extension portion 641 extends from the base portion 640 toward the side surface 30d of the sealing body 30. Even in this configuration, the slit 643 only needs to be provided at least between the semiconductor elements 40L. Furthermore, by configuring the slit 643 to extend from the opposing region of the semiconductor elements 40L to the outside of the opposing region toward the N terminal 91N, the inductance Ls can be further increased.

Although one slit 643, 653 is provided between the semiconductor elements 40, this is not limitative. At least one of the slits 643, 653 may be provided in multiple positions.

While an example has been shown in which the slits 643 and 653 open at one of the ends of the surface metal body 62, this is not limiting. For example, in the example shown in Figures 31 and 32, the slit 643 extends in the Y direction from the opposing edge 640a of the base 640 to the end 640c. The slit 643 divides the base 640, and therefore the N wiring 64, into two. The slit 643 crosses the opposing region of the semiconductor elements 40L. One of the semiconductor elements 40L is disposed in one of the divided N wirings 64, and the other semiconductor element 40L is disposed in the other N wiring 64. Similarly, the slit 653 extends in the Y direction from the end 652 to the end 650 of the relay wiring 65. The slit 653 divides the relay wiring 65 into two. One of the semiconductor elements 40H is disposed in one of the divided relay wirings 65, and the other semiconductor element 40H is disposed in the other relay wiring 65.

Slits 643 and 653 are connected to each other to form a single slit extending in the Y direction. The surface metal body 62 is approximately symmetrical with respect to the imaginary line CL1. Figure 33 shows the source current path. The solid arrow indicates the source current path of semiconductor element 40H, and the dashed arrow indicates the source current path of semiconductor element 40L. As described above, slit 643 divides N wiring 64 into two. This prevents one source current of semiconductor element 40L and the other source current from merging on the substrate 60. Because the point where the source currents meet is further away, the inductance Ls of the source wiring can be further increased.

Similarly, slit 653 divides relay wiring 65 into two. This prevents the source current of semiconductor element 40H and another source current from merging on substrate 60. Because the source current merging point is further away, the inductance Ls of the source wiring can be further increased. As a result, the effect of suppressing transient current imbalance can be improved. Figures 31, 32, and 33 are diagrams showing modified examples. Figure 31 corresponds to Figure 28. Figure 32 corresponds to Figure 11. Figure 33 corresponds to Figure 29.

In the example shown in Figures 31 to 33, the arm connection parts 80 are divided into the same number as the relay wirings 65, in accordance with the division of the relay wirings 65. The arm connection parts 80 are individually connected to the relay wirings 65. This prevents the source currents from merging at the arm connection parts 80, making it possible to further increase the inductance Ls.

In the configuration of the above-described modified example, a slit may be further provided in the surface metal body 52 of the substrate 50. As shown in Figures 34 and 35, the relay wiring 55 of the surface metal body 52 has a slit 553. The slit 553 opens at the end 551a of the relay wiring 55. The end 551a faces the P wiring 54 in the Y direction. The slit 553 extends in the Y direction, crosses the arm connection portion 80, which is divided into two, and reaches the opposing area (between) of the semiconductor element 40L. The slit 553 is provided up to near the bottom end of the opposing area of the semiconductor element 40L.

When such a configuration is adopted, as shown in FIG. 35, a first current path through one pair of semiconductor elements 40H, 40L and a second current path through another pair of semiconductor elements 40H, 40L are almost completely separated within the semiconductor device 20. The current confluence point is located outside the N terminal 91N. This allows the inductance Ls of the source wiring to be further increased. FIGS. 34 and 35 are diagrams showing modified examples. FIG. 34 corresponds to FIG. 32. FIG. 35 corresponds to FIG. 33. The semiconductor device 20 may also include an N bus bar connecting multiple N terminals 91N. In this case, the currents converge at the N bus bar. The N bus bar connecting the N terminals 91N may also be provided on the smoothing capacitor 5 side, for example.

In the example shown, the arm connection portion 80 is configured with a joint portion 81 and bonding material 103 arranged on both ends of the joint portion 81, but this is not limiting. In the example shown in Figure 36, the joint portion 81 is provided integrally with the substrate 60. The joint portion 81 is provided as a protrusion extending in the Z direction from the relay wiring 65. Like the joint portion 81, the conductive spacer 70 is also provided integrally with the surface metal body 62 as a protrusion.

The surface metal body 62 with protrusions may be formed, for example, by patterning a multi-gauge metal plate by press working and attaching it to the insulating substrate 61. The surface metal body 62 with protrusions may also be formed by etching thick copper. It may also be formed by directly bonding a metal body that is a separate member from the substrate 60 to the surface metal body 62. In the configuration shown in Figure 36, the arm connection part 80 is made up of the joint part 81, which is the protrusion of the relay wiring 65, and the bonding material 103 interposed between the tip of the joint part 81 and the relay wiring 55. Figure 36 is a view corresponding to Figure 30.

In the example shown in Figure 37, the joint portion 81 is eliminated. A bonding material 103 electrically connects the relay wirings 55, 65. The bonding material 103 constitutes the arm connection portion 80. In Figure 37, the conductive spacer 70 is also eliminated, and the source electrode 40S of the semiconductor element 40 is connected to the surface metal body 62 via a bonding material 101. Although not shown, the arm connection portion 80 may be configured to include only the joint portion 81, without the bonding material 103. In this case, the joint portion 81 is directly bonded to the relay wirings 55, 65.

The circuit patterns of the substrates 50 and 60 are not limited to the examples described above. The substrate 60 shown in Figure 38 shows an example in which slits 643 and 653 are applied to the circuit pattern shown in Figure 24. In the example shown in Figure 38, the slit 643 is provided between adjacent semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction toward the N terminal 91N, i.e., the side through which the source current flows. The slit 653 is provided between adjacent semiconductor elements 40H. The slit 653 extends from between the semiconductor elements 40H in the Y direction toward the arm connection portion 80.

In this embodiment, the arrangement of the external connection terminals 90 is not limited to the example shown. The P terminal 91P may be connected to the P wiring 54 at both ends in the X direction, for example. The N terminal 91N may be connected to the N wiring 64 at both ends in the X direction, for example. In this case, the N terminal 91N may be connected to the extension portion 641. The extension portion 641 may be removed from the N wiring 64 and connected to the base portion 640. The output terminal 92 may be connected to the relay wiring 55 at both ends in the X direction, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment and its variations.

(Third embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to effectively dissipate heat from the semiconductor element, the thickness above and below the semiconductor element may satisfy a predetermined relationship, as described in this embodiment.

<Warping at high temperatures>
Through careful investigation, it has become clear that even when insulating substrates 51 and 61 made of resin are used and the linear expansion coefficient is made closer to that of metal bodies 52, 53, 62, and 63 by adding filler, warping can occur in semiconductor device 20 as shown in Fig. 39. Fig. 39 shows the state of semiconductor device 20 when semiconductor element 40 is in operation, that is, at high temperatures. The dashed dotted line in the figure is a reference line indicating the direction of warping.

The configuration shown in Figure 39 is similar to that described in the preceding embodiment (see Figure 5). For convenience, the external connection terminals 90 are omitted from Figure 39. In Figure 39, the semiconductor device 20 and the heat exchanger 121 of the cooler 120 are arranged side by side in the Z direction, which is a predetermined direction. The heat exchanger 121 is arranged on both sides of the semiconductor device 20 in the Z direction, sandwiching the semiconductor device. A thermally conductive member 130, such as silicone gel, is arranged between each heat exchanger 121 and the semiconductor device 20. The cooler 120 cools the semiconductor device 20 by circulating a refrigerant through the flow path of the heat exchanger 121. The refrigerant flowing through the flow path can be a phase-change refrigerant such as water or ammonia, or a phase-non-change refrigerant such as an ethylene glycol-based refrigerant. The thermally conductive member 130 is sometimes referred to as a thermal interface material (TIM). The thermally conductive member 130 conforms to the opposing surfaces of the heat exchanger 121 and the semiconductor device 20, filling the gap between the opposing surfaces.

As described above, in the semiconductor element 40, the drain electrode 40D, which is the main electrode on the high potential side, has a larger electrode area than the source electrode 40S, which is the main electrode on the low potential side. Furthermore, a conductive spacer 70 is interposed between the source electrode 40S and the substrate 60, whereas no conductive spacer 70 is interposed between the drain electrode 40D and the substrate 50. In other words, the thermal resistance of the heat transfer path from the semiconductor element 40 to the substrate 50 is smaller than that of the heat transfer path from the semiconductor element 40 to the substrate 60. In a semiconductor device 20 configured in this way, it is necessary to effectively dissipate heat toward the substrate 50.

When warping occurs, with the substrate 50 side concave and the substrate 60 side convex, as shown in Figure 39, the distance between the exposed back surface 50b of the substrate 50 and the heat exchanger 121 increases, and the intervening heat conduction member 130 becomes thicker. This increases the thermal resistance between the substrate 50 and the heat exchanger 121, making heat transfer (heat exchange) between the semiconductor device 20 and the cooler 120 (heat exchanger 121) more difficult. The warping state shown in Figure 39 is not desirable for effectively dissipating heat from the semiconductor element 40, i.e., for efficiently cooling the semiconductor device 20. Figure 39 shows an example of a double-sided cooling structure in which the cooler 120 (heat exchanger 121) is located on both sides of the semiconductor device 20. However, a single-sided cooling structure in which the cooler 120 is located only on the substrate 50 side in the Z direction also has the same issues.

<Structure of semiconductor device>
Through careful investigation, it has become clear that warpage of the semiconductor device 20 can be controlled by controlling the relative thickness of the portion of the semiconductor device 20 closer to the substrate 50 than the semiconductor element 40 and the portion closer to the substrate 60. The semiconductor device 20 of this embodiment has a configuration based on this finding. Figure 40 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Figure 40 shows an ideal state in which the semiconductor device 20 is free of warpage.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). Similar to Figure 39, Figure 40 shows the semiconductor device 20, as well as the heat exchanger 121 of the cooler 120 and the thermally conductive member 130. In other words, Figure 40 shows a semiconductor module 140 comprising the semiconductor device 20, the cooler 120, and the thermally conductive member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged alongside the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

The rear surface metal bodies 53, 63 are exposed from the sealing body 30 as the rear surfaces 50b, 60b of the substrates 50, 60. One of the heat exchanger sections 121 of the cooler 120 is disposed opposite one surface 30a and the rear surface 50b of the sealing body 30, and the other heat exchanger section 121 is disposed opposite the rear surface 30b and the rear surface 60b of the sealing body 30. A thermal conduction member 130 is disposed between the opposing surfaces of the semiconductor device 20 and the heat exchanger section 121. The thermal conduction member 130 is in close contact with the semiconductor device 20 and the heat exchanger section 121.

The semiconductor device 20 is configured so that the thickness T1 on the substrate 50 side of the semiconductor element 40 and the thickness T2 on the substrate 60 side of the semiconductor element 40 satisfy the relationship T1 ≥ T2. The remaining configuration is the same as that described in the previous embodiment (see Figure 5). Thickness T1 is the total thickness of the bonding material 101, conductive spacer 70, bonding material 102, and substrate 60. Thickness T2 is the total thickness of the bonding material 100 and substrate 50. Since the relationship T1 ≥ T2 is satisfied, the substrate 50 is thicker than the substrate 60. The substrate 50 is thicker than the conductive spacer 70. In the substrate 50, the metal bodies 52 and 53 are thicker than the insulating substrate 51. In the substrate 60, the metal bodies 62 and 63 are thicker than the insulating substrate 61. Except for the thickness relationship, the configuration is the same as that described in the first embodiment.

<Simulation results>
Figures 41 to 43 show the results of thermal stress simulations. Figure 41 shows the state of the semiconductor device 20 shown in Figure 40 at room temperature (RT). Figure 42 shows the state of the semiconductor device 20 shown in Figure 40 at a high temperature. At a high temperature, the semiconductor element 40 generates heat due to electrical current, i.e., the semiconductor element 40 is in operation. As shown in Figures 41 and 42, warping occurs in the semiconductor device 20 at high temperatures. In this embodiment, since the relationship T1 ≥ T2 is satisfied as described above, the expansion amount on the substrate 50 side is greater than the expansion amount on the substrate 60 side, as indicated by the dashed arrows in Figure 42. This is because Cu, which constitutes the metal bodies 52, 53, 62, and 63, has the largest linear expansion coefficient and the substrate 50 is thick. As a result, a convex warp occurs on the first substrate (substrate 50) side and a concave warp occurs on the second substrate (substrate 60) side. The dashed-dotted line in Figure 42 is a reference line indicating the direction of warping.

Figure 43 shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warpage at high temperatures. In this simulation, the semiconductor element 40, conductive spacer 70, and bonding materials 100, 101, and 102 were all the same (common), and the thicknesses of the substrates 50 and 60 were adjusted so that the thickness ratio T1:T2 was a predetermined value. The material composition was also all the same (common). The vertical axis in Figure 43 represents the amount of warpage, expressed in arbitrary units (a.u.). A warpage above 0 (zero) indicates a convex warpage toward the substrate 50 and a concave warpage toward the substrate 60, while a warpage below 0 (zero) indicates a concave warpage toward the substrate 50 and a convex warpage toward the substrate 60. T1:T2 was set to four levels: 1:2, 1:1.3, 1:1, and 1.5:1.

As shown in Figure 43, when T1:T2 = 1:2, concave warping occurred on the substrate 50 side and convex warping occurred on the substrate 60 side, with the amount of convex warping on the substrate 60 side being the largest among the four levels. When T1:T2 = 1:1.3, concave warping occurred on the substrate 50 side and convex warping on the substrate 60 side, with the amount of convex warping on the substrate 60 side being smaller than when T1:T2 = 1:2. When T1:T2 = 1:1, the warping changed to convex warping on the substrate 50 side and concave warping on the substrate 60 side. When T1:T2 = 1.5:1, convex warping occurred on the substrate 50 side and concave warping on the substrate 60 side, with the amount of convex warping on the substrate 50 side being the largest among the four levels.

As such, it was found that when T1 < T2, concave warping occurs on the substrate 50 side and convex warping occurs on the substrate 60 side, and when T1 ≥ T2, convex warping occurs on the substrate 50 side and concave warping occurs on the substrate 60 side. In other words, it was found that by satisfying the relationship T1 ≥ T2, it is possible to control warping that occurs at high temperatures to be convex on the substrate 50 side and concave on the substrate 60 side. It was also found that the larger T2 is relative to T1, the greater the amount of convex warping on the substrate 60 side, and the larger T1 is relative to T2, the greater the amount of convex warping on the substrate 50 side.

<Summary of the Third Embodiment>
In this embodiment, the semiconductor device 20 satisfies the above-described relationship of thickness T1 ≥ thickness T2. The thickness T1 on the side where the conductive spacer 70 is not interposed between the semiconductor element 40 and the substrate 50 is equal to or greater than the thickness T2 on the side where the conductive spacer 70 is interposed between the semiconductor element 40 and the substrate 60. As a result, when the semiconductor element 40 is in operation (at high temperatures), the semiconductor device 20 warps convexly toward the substrate 50 and concavely toward the substrate 60. Therefore, the opposing distance between the semiconductor device 20 and the cooler 120 (heat exchange unit 121) on the substrate 50 side, which contributes more to heat dissipation, can be narrowed compared to a configuration where the relationship of thickness T1 < thickness T2 is satisfied. Because the opposing distance is narrower, the thermal resistance between the semiconductor device 20 and the cooler 120 is reduced. This allows heat generated by the semiconductor element 40 to be efficiently dissipated to the outside of the semiconductor device 20. In other words, the cooling efficiency of the semiconductor device 20 can be improved.

Specifically, the thickness of the thermally conductive member 130 interposed between the semiconductor device 20 and the cooler 120 is thinner than in a configuration where the relationship thickness T1 < thickness T2 is satisfied. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120, facilitating heat exchange between the semiconductor device 20 and the cooler 120. Therefore, heat generated by the semiconductor element 40 can be efficiently dissipated to the outside of the semiconductor device 20.

In this embodiment, the rear surface metal body 53 is exposed from the sealing body 30. This allows for improved heat dissipation compared to a configuration in which the rear surface metal body 53 is covered by the sealing body 30. Similarly, the rear surface metal body 63 is exposed from the sealing body 30. This allows for improved heat dissipation compared to a configuration in which the rear surface metal body 63 is covered by the sealing body 30.

<Modification>
Although an example of a double-sided heat dissipation structure has been shown, this is not limiting. It is desirable for the semiconductor device 20 to efficiently dissipate heat primarily from the substrate 50 side. Therefore, the cooler 120 (heat exchange unit 121) may be disposed only on the substrate 50 side in the Z direction relative to the semiconductor device 20. Even in such a single-sided heat dissipation structure, satisfying the relationship T1≧T2 results in a convex warp toward the substrate 50 side at high temperatures. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently dissipated.

Although an example has been shown in which both the back surface metal bodies 53 and 63 are exposed from the sealing body 30, this is not limiting. For example, a configuration in which only the back surface metal body 53 is exposed may also be used.

In the example shown, the semiconductor device 20 includes a semiconductor element 40H that forms the upper arm 9H and a semiconductor element 40 that forms the lower arm 9L, but this is not limiting. It may also include only a semiconductor element 40 that forms one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40. The semiconductor device 20 may include the semiconductor element 40, a pair of substrates 50, 60 arranged to sandwich the semiconductor element 40, and a conductive spacer 70 interposed between the semiconductor element 40 and the substrate 60.

No particular mention was made of the relationship between the thicknesses of the metal bodies 52, 53 in the substrate 50. For example, as shown in Figure 44, the front surface metal body 52 may be thicker than the back surface metal body 53. The drain electrode 40D, which is the first main electrode of the semiconductor element 40, is bonded to the front surface metal body 52. The thermal resistance between the front surface metal body 52 and the semiconductor element 40 is low. By thickening the front surface metal body 52 closer to the semiconductor element 40, the heat generated by the semiconductor element 40 can be effectively diffused. In other words, the heat from the semiconductor element 40 can be efficiently dissipated. Figure 44 is a cross-sectional view showing a modified example. Figure 44 corresponds to Figure 41.

As shown in Figure 44, the front surface metal body 62 may be thicker than the back surface metal body 63. By making the front surface metal body 62 closer to the semiconductor element 40 thicker, heat generated by the semiconductor element 40 can be effectively diffused.

As described above, heat from a semiconductor element 40 having main electrodes on both sides is primarily conducted to the substrate 50, which has a lower thermal resistance. For this reason, as shown in Figure 45, the front surface metal body 62 may be thinner than the back surface metal body 63. This allows the thickness of the substrate 60 to be reduced, thereby making it possible to miniaturize the size of the semiconductor device 20. Since thick metal bodies are no longer necessary, costs can also be reduced. Figure 45 is a cross-sectional view showing a modified example. Figure 45 corresponds to Figure 44. In Figure 45, the front surface metal body 52 is thicker than the back surface metal body 53, and the front surface metal body 62 is thinner than the back surface metal body 63. Therefore, heat from the semiconductor element 40 can be efficiently dissipated while achieving a smaller size and lower costs.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, and modified examples.

(Fourth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. To improve connection reliability, the substrate and the signal terminals may be configured to satisfy a predetermined positional relationship, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 of this embodiment will be described with reference to Figures 46 and 47. Figure 46 shows the periphery of a signal terminal 93 in the semiconductor device 20 of this embodiment. In Figure 46, some elements of the semiconductor device 20 are omitted to show the positional relationship between the substrate 50 and the signal terminal 93. Figure 47 is a cross-sectional view taken along line XLVII-XLVII in Figure 46. In Figures 46 and 47, the signal terminal 93L on the lower arm 9L side will be described as an example.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 46, the semiconductor device 20 includes two semiconductor elements 40L. Each semiconductor element 40L has a drain electrode 40D, which is a first main electrode, on one surface, and a source electrode 40S, which is a second main electrode, and a signal pad 40P on the back surface. The semiconductor device 20 includes four signal terminals 93L. Each signal terminal 93L extends in the Y direction and protrudes externally from the side surface 30d of the sealing body 30. The four signal terminals 93L are arranged side by side in the X direction between the output terminals 92 when viewed in a plan view in the Z direction.

<Shape and arrangement of signal terminals>
Next, the shape and arrangement of the signal terminals 93 will be described with reference to FIGS.

As shown in FIG. 46, each signal terminal 93L has an overlapping portion 930 that overlaps the substrate 50 in a plan view, and a non-overlapping portion 931 that does not overlap the substrate 50. The overlapping portion 930 faces the substrate 50 in the Z direction.

The overlapping portion 930 is a portion of the signal terminal 93L that is within a predetermined range from the end portion on the semiconductor element 40L side. The non-overlapping portion 931 is the portion excluding the overlapping portion 930. The overlapping portion 930 overlaps the insulating base material 51 of the substrate 50 to which the drain electrode 40D is electrically connected. The entire overlapping portion 930 overlaps the insulating base material 51. The overlapping portion 930 overlaps the exposed portion 510 of the insulating base material 51 that is exposed from the surface metal body 52. In this way, the signal terminal 93L extends onto the substrate 50. In other words, the signal terminal 93L is inserted and positioned up to a position where it overlaps the substrate 50 in a plan view.

Of the four signal terminals 93L, the overlapping portion 930 of two signal terminals 93L has a main portion 930a and a protruding portion 930b. The other two signal terminals 93L do not have a protruding portion 930b. The main portion 930a extends in the Y direction, which is the main extension direction of the signal terminal 93L. The protruding portion 930b is connected to the main portion 930a and protrudes from the main portion 930a. The protruding portion 930b extends in a different direction from the main portion 930a. The protruding portion 930b is sometimes referred to as a branch portion. The planar shape of the main portion 930a can be a variety of shapes, such as a generally L-shaped, generally Y-shaped, or generally T-shaped. In the example shown in Figure 46, one signal terminal 93L has a generally L-shaped planar shape, and the other signal terminal 93L has a generally T-shaped planar shape.

As described in the previous embodiment (see FIG. 11 ), the relay wiring 55 of the surface metal body 52 has a notch 550. The overlapping portion 930 of the signal terminal 93L overlaps the portion of the insulating substrate 51 exposed through the notch 550. The four signal terminals 93L are arranged in a line in the X direction between the output terminals 92 in a plan view. Each signal terminal 93L has a tie bar mark 93a. As described in the previous embodiment (see FIG. 10 ), the tie bar mark 93a is a mark left on the side of the signal terminal 93L when the tie bar 94a of the lead frame 94 is cut off. The tie bar mark 93a is sometimes referred to as a cut mark. Each signal terminal 93L has a tie bar mark 93a on both side surfaces in the X direction. The tie bar mark 93a is provided in the non-overlapping portion 931, outside the sealing body 30.

As shown in FIG. 47, each signal terminal 93L has a joint 93b, a tip 93c, a bent portion 93d, and an extension 93e. The joint 93b is the portion to which a bonding wire 110, which serves as a connecting member, is joined. The joint 93b preferably includes a portion that is approximately parallel to the XY plane. The joint 93b is the portion of the signal terminal 93L that is closest to the surface of the insulating substrate 51 (exposed portion 510). In this embodiment, the joint 93b is floating above the surface of the insulating substrate 51. The joint 93b does not contact the insulating substrate 51, and the sealing body 30 fills the gap between the underside of the joint 93b and the surface of the insulating substrate 51. The bonding wire 110 electrically connects the signal terminal 93L to a pad 40P formed on the same surface as the source electrode 40S.

The tip portion 93c is located further forward than the joint portion 93b, i.e., closer to the semiconductor element 40 (40L). The tip portion 93c is located higher than the joint portion 93b, i.e., farther from the surface of the insulating substrate 51 in the Z direction. The tip portion 93c rises upward as it moves away from the joint portion 93b. The tip portion 93c has an R-shape in the ZY cross section. The bent portion 93d is located between the joint portion 93b and the extension portion 93e, which is the portion rearward of the joint portion 93b. The bent portion 93d is bent so that the extension portion 93e is located higher than the joint portion 93b, i.e., farther from the surface of the insulating substrate 51. Due to the bending process, the bent portion 93d has a smaller cross-sectional area than the other portions of the signal terminal 93, specifically the joint portion 93b, the tip portion 93c, and the extension portion 93e. In other words, it is thinner. The extension portion 93e is located rearward of the joint portion 93b. The extension portion 93e extends in the Y direction and is positioned both inside and outside the sealing body 30.

At least a portion of the joint portion 93b, tip portion 93c, and bent portion 93d is included in the overlapping portion 930 described above. At least a portion of the extension portion 93e is included in the non-overlapping portion 931. In this embodiment, the entire extension portion 93e is included in the non-overlapping portion 931. Each signal terminal 93L is formed by press punching. The surface of the signal terminal 93L facing the insulating substrate 51 is a press-rounded surface 93f, and the surface opposite the facing surface is a burr surface 93g where burrs are generated by punching. The rest of the configuration is the same as that described in the first embodiment.

<Bonding wire connection method>
Next, a method of connecting the signal terminal 93 having the above-described structure to the bonding wire 110 will be described with reference to Fig. 48. Fig. 48 is a diagram illustrating wire bonding. Reference numeral 111 in Fig. 48 denotes a jig that holds down the signal terminal 93L. Reference numeral 112 denotes a tool for ultrasonic bonding. The tool 112 is sometimes referred to as an ultrasonic bonding device. The dashed dotted line in Fig. 48 indicates the position of the signal terminal 93L that has been bent by being pressed by the jig 111.

As shown in Figure 48, first, the overlapping portion 930 of the signal terminal 93L is positioned so that it overlaps the insulating substrate 51, and the wire 110a is set in the portion to be joined. Then, pressure is applied in the Z direction using a jig 111 to elastically deform the signal terminal 93L, bringing the overlapping portion 930 into contact with the surface of the insulating substrate 51. The jig 111 presses the overlapping portion 930 of the signal terminal 93L or the vicinity thereof.

Then, with the signal terminal 93L in contact with the insulating substrate 51, ultrasonic bonding is performed using the tool 112. Because the signal terminal 93L is received by the insulating substrate 51, a separate receiving jig is not required. When ultrasonic bonding is completed and the tool 112 and jig 111 are released from the signal terminal 93L, the signal terminal 93L is released from its elastically deformed state and returns to the position it was in before pressure was applied. The signal terminal 93L is part of the lead frame 94. Because the signal terminal 93L is supported by the tie bars 94a on the outer frame 94b, it returns to its original position when pressure is released.

The above description has been given using the signal terminal 93L as an example. However, the above configuration may also be applied to the signal terminal 93H on the upper arm 9H side. Both signal terminals 93H and 93L may have the above configuration. In the configuration described in the previous embodiment (see Figure 11), each of the signal terminals 93H and 93L overlaps the exposed portion of the insulating substrate 51. The P wiring 54 of the surface metal body 52 has a notch 540, and the signal terminal 93H overlaps the surface of the insulating substrate 51 exposed from the notch 540.

<Summary of the Fourth Embodiment>
In this embodiment, the signal terminal 93 (93L) overlaps the exposed portion 510 of the insulating base material 51. However, the signal terminal 93 is not bonded to the exposed portion 510. In other words, the signal terminal 93 is not fixed to the insulating base material 51, or even to the substrate 50. This allows the signal terminal 93 to absorb dimensional variations within the tolerances of the elements constituting the semiconductor device 20, as well as assembly variations when assembling the elements. Therefore, during molding of the sealing body 30, stress concentration at the electrical connection portion (joint) of the signal terminal 93 with the semiconductor element 40 can be suppressed. As a result, a semiconductor device 20 with high connection reliability can be provided.

In this embodiment, the signal terminals 93 are inserted and positioned up to a position where they overlap the substrate 50, that is, onto the substrate 50. By adopting this type of positioning, the signal terminals 93 are closer to the pads 40P of the semiconductor element 40 (40L) in the Y direction. Therefore, the length of the bonding wires 110, which are connecting members, can be shortened compared to a configuration in which the signal terminals 93 are positioned only in positions that do not overlap the substrate 50. Because the length of the bonding wires 110 can be shortened, it is possible to suppress wire sweep, short circuits due to wire sweep, wire breakage, and other problems when molding the encapsulant 30 using a transfer molding method or the like.

In this embodiment, the overlapping portion 930 of the signal terminal 93 is floating above the surface of the exposed portion 510 of the insulating substrate 51. The sealing body 30 is interposed between the underside of the overlapping portion 930 and the surface of the exposed portion 510. The sealing body 30 is also interposed between the joint portion 93b and the exposed portion 510. This makes it possible to absorb large manufacturing variations in the plate thickness direction. Furthermore, because the signal terminal 93 is located above the insulating substrate 51, it is easier to ensure an insulating distance from the back surface metal body 53.

In this embodiment, the surface metal body 52 has a notch 550 (540). The notch 550 opens at the end in the Y direction, which is a direction perpendicular to the Z direction. The overlapping portion 930 of the signal terminal 93 overlaps the surface of the exposed portion 510 exposed through the notch 550. In this way, by providing the notch 550 in the surface metal body 52 of the substrate 50, it is possible to ensure an insulation distance between the surface metal body 52 and the signal terminal 93 while suppressing an increase in the physical size of the substrate 50.

In this embodiment, the non-overlapping portion 931 of the signal terminal 93 has a tie bar mark 93a. As described above, the signal terminal 93L is part of the lead frame 94 and is supported by the tie bar 94a on the outer frame 94b. Therefore, pressure is applied to bend the signal terminal 93 and bring it into contact with the exposed portion 510 of the insulating substrate 51, and in this contact state, the bonding wire 110 can be joined by ultrasonic bonding. Then, after joining is complete, the pressure is released and the signal terminal 93 returns to its original position.

In this embodiment, the signal terminal 93 has a bent portion 93d between the joint portion 93b and the extension portion 93e. The bent portion 93d positions the extension portion 93e farther from the exposed portion 510 (insulating substrate 51) in the Z direction than the joint portion 93b. By having the bent portion 93d in this way, it is possible to ensure an insulating distance between the signal terminal 93 and the back surface metal body 53 while suppressing an increase in size in the Z direction.

In this embodiment, the signal terminal 93 has a tip portion 93c. The tip portion 93c is farther from the exposed portion 510 (insulating substrate 51) in the Z direction than the joint portion 93b. This prevents the tip of the signal terminal 93 from damaging the insulating substrate 51 during the above-mentioned bonding (ultrasonic bonding), etc. In other words, it is possible to prevent a decrease in insulating performance. In particular, in this embodiment, the tip portion 93c is raised further upward as it moves away from the joint portion 93b, making it less likely for the tip portion 93c to come into contact with the insulating substrate 51. Furthermore, because the tip portion 93c has an R-shape in the ZY cross section, even if it does come into contact, it is possible to prevent the insulating substrate 51 from being damaged.

If the opposing surface is a burr surface 93g, the insulating base material 51 may be scratched, resulting in a deterioration in insulating performance. In this embodiment, the signal terminal 93 is configured so that the surface facing the exposed portion 510 is a pressed round surface 93f, and the back side of the opposing surface is a burr surface 93g. This prevents the insulating performance of the insulating base material 51 from being reduced.

<Modification>
The non-bonding configuration between the signal terminal 93 and the exposed portion 510 is not limited to the above example. For example, in FIG. 49 , the overlapping portion 930 of the signal terminal 93 is floating above the insulating substrate 51, with a slight gap between the overlapping portion 930 and the surface of the exposed portion 510 that is small enough to prevent the sealing body from entering. The sealing body 30 has a gap 31 between the underside of the overlapping portion 930 and the surface of the exposed portion 510. The signal terminal 93 is not fixed to the insulating substrate 51 (exposed portion 510). Therefore, the same effect as the configuration shown in FIG. 47 can be achieved. FIG. 49 is a cross-sectional view showing a modified example, corresponding to FIG. 47 .

In Figure 50, the overlapping portion 930 of the signal terminal 93 is in contact with the surface of the exposed portion 510. Although the signal terminal 93 is in contact with the insulating substrate 51 (exposed portion 510), it is not fixed. Therefore, it is possible to achieve the same effect as the configuration shown in Figure 47. Figure 50 is a cross-sectional view showing a modified example and corresponds to Figure 47. Note that it is also possible for part of the underside of the joint portion 93b to be in contact with the insulating substrate 51, while the other part is not in contact.

In the example shown in Figure 47, the substrate 60 is positioned so as not to overlap the signal terminal 93 in a planar view. In other words, the substrate 60 is not positioned above the signal terminal 93. Adopting such an arrangement allows the size of the substrate 60 to be reduced. It also makes it easier to ensure an insulating distance between the surface metal body 62 and the signal terminal 93. However, the positional relationship between the signal terminal 93 and the substrate 60 is not limited to the example shown in Figure 47. For example, as shown in Figure 51, the overlapping portion 930 of the signal terminal 93 also overlaps with the substrate 60. The surface metal body 62 of the substrate 60 overlaps the overlapping portion 930 and the exposed portion 510 of the insulating base material 51 in a planar view. This improves heat dissipation. Figure 51 is a cross-sectional view showing a modified example and corresponds to Figure 47.

In Figure 52, unlike Figure 51, the front surface metal body 62 is patterned so that it does not overlap the overlapping portion 930 of the signal terminal 93. The insulating substrate 61 and back surface metal body 63 are located above the overlapping portion 930. By making the front surface metal body 62 smaller, it becomes easier to ensure an insulating distance between the front surface metal body 62 and the signal terminal 93. Because the back surface metal body 63 is large, heat dissipation can be improved. Figure 52 is a cross-sectional view showing a modified example and corresponds to Figure 47.

This example shows how the length of the bonding wire 110 (connecting member) can be shortened by inserting the signal terminal 93 into the substrate 50. Alternatively, the length of the bonding wire 110 can be shortened by using an interconnection board 150 as shown in Figures 53 to 55. Figure 53 is a plan view showing a modified example and corresponds to Figure 46. In Figure 53, some elements of the semiconductor device 20 are omitted to show the positional relationship between the substrate 50, signal terminal 93, and interconnection board 150. Figure 54 is a cross-sectional view showing the interconnection board. Figure 55 is a cross-sectional view taken along line LV-LV in Figure 53. Here, the interconnection wiring 55 and signal terminal 93L are shown as an example, but a similar configuration can also be used for the P wiring 54 and signal terminal 93H.

The semiconductor device 20 further includes a relay substrate 150. As shown in Figures 53 and 55, the relay substrate 150 is disposed on the surface metal body 52 (relay wiring 55) of the substrate 50. As shown in Figure 54, the relay substrate 150 has an insulating substrate 151 and a conductor portion 152 disposed on the insulating substrate 151. A portion of the conductor portion 152 provides a wiring function. The relay substrate 150 is sometimes referred to as a printed circuit board or a wiring board.

The conductor portion 152 has lands 152a and 152b. The lands 152a and 152b are exposed on one surface of the relay substrate 150. Specifically, they are exposed from the solder resist 153 provided on one surface 151a of the insulating substrate 151. The land 152a is electrically connected to the pad 40P via the bonding wire 110. The signal terminal 93 overlaps with the substrate 50 in a plan view. The signal terminal 93 is connected to the land 152b.

In addition to the lands 152a and 152b, the conductor portion 152 also has wiring 152c and via conductor 152d. At least a portion of the wiring 152c is an inner layer wiring disposed inside the insulating substrate 151. The lands 152a and 152b are electrically connected via the wiring 152c and the via conductor 152d. The multiple lands 152a include two lands 152a that are individually connected to gate electrode pads 40P of two semiconductor elements 40. The two gate electrode lands 152a are electrically connected to one gate electrode land 152b via the wiring 152c and the via conductor 152d.

In this way, using the relay substrate 150 allows the connection target (land 152a) of the bonding wire 110 to be closer to the pad 40P. This allows the length of the bonding wire 110 that electrically connects the pad 40P and the signal terminal 93 to be shortened. Furthermore, the wiring 152c can be routed freely within the relay substrate 150. This prevents the bonding wires 110 from crossing each other in a configuration in which semiconductor elements 40 are connected in parallel. This prevents the wires from coming into contact with each other when the encapsulation body 30 is molded. Furthermore, using fine wiring technology for printed circuit boards, it is possible to achieve a size reduction similar to that of the configuration shown in Figure 47.

The conductor portion 152 further has a fixing land 152e. The fixing land 152e is a land for fixing the relay board 150 to the substrate 50. The fixing land 152e does not provide an electrical connection function, i.e., a wiring function. The fixing land 152e is disposed on the back surface 151b of the insulating base material 151. The fixing land 152e (relay board 150) is bonded to the front surface metal body 52 via a bonding material 154. The bonding material 154 can be, for example, solder.

In this way, the relay substrate 150 is fixed to the surface metal body 52, allowing for stable wire bonding. Solder containing Ni balls may be used as the bonding material 154. In this case, the Ni balls allow for control of the thickness of the bonding material 154. Also, tilting of the relay substrate 150 can be suppressed.

The wiring function provided by the conductor portion 152 is electrically separated from the surface metal body 52 by the insulating substrate 151. For example, the insulating substrate 151 may have, in the Z direction, a non-placement area 151c where the conductor portion 152 is not placed, and a placement area 151d where the conductor portion 152 is placed. In the Z direction, the non-placement area 151c is located in the center of the insulating substrate 151, and the placement area 151d is located on the surface layer of both sides. The non-placement area 151c is sometimes referred to as a core layer. In this way, by having the non-placement area 151c in the insulating substrate 151, the conductor portion 152, which is located on one surface 151a and provides the wiring function, can be electrically separated from the fixing land 152e and ultimately from the surface metal body 52.

The solder resist 153 has low adhesion to the sealing body 30. Furthermore, peeling of the sealing body 30 due to thermal stress begins at the outer periphery of the relay substrate 150 and progresses. For example, the insulating base material 151 may have an exposed portion 151e exposed from the solder resist 153. The exposed portion 151e is provided on the outer periphery of one surface 151a of the insulating base material 151. The insulating base material 151 has higher adhesion to the sealing body 30 than the solder resist 153. At the exposed portion 151e, the sealing body 30 is in close contact with the relay substrate 150. This prevents the sealing body 30 from peeling from the relay substrate 150. Because the sealing body 30 is in close contact at the outer periphery, the conductor portions 152, such as lands 152a and 152b, that are exposed from the solder resist 153 can be protected.

As shown in FIG. 55, the signal terminal 93 (93L) has a first extension portion 93h, a second extension portion 93i, and a bent portion 93j. The first extension portion 93h and the second extension portion 93i extend in the Y direction. The first extension portion 93h is disposed inside the sealing body 30. The second extension portion 93i is disposed both inside and outside the sealing body 30. The bent portion 93j is provided between the first extension portion 93h and the second extension portion 93i. The first extension portion 93h is located closer to the tip end than the bent portion 93j, and the second extension portion 93i is located closer to the rear end than the bent portion 93j.

The signal terminal 93 may have a protrusion 93k. The protrusion 93k is provided near the tip of the signal terminal 93. The protrusion 93k protrudes from the first extension 93h toward the land 152b in the Z direction. The protrusion 93k is joined to the land 152b. In the signal terminal 93, the tip of the first extension 93h and the protrusion 93k overlap with the land 152b in a plan view in the Z direction. The portion where the tip of the first extension 93h and the protrusion 93k join is a thick portion, and the other portions of the signal terminal 93 are thin portions. By providing the protrusion 93k in this manner, the signal terminal 93 (first extension 93h) is spaced away from the surface metal body 52, making it easier to ensure an insulating distance between the surface metal body 52.

Figure 56 shows an example different from Figure 54. Figure 56 corresponds to Figure 54. In Figure 56, the relay board 150 is fixed to the exposed portion 510 of the insulating base material 51. In this case, the thickness of the bonding material 154 and the relay board 150 ensures an insulation distance between the signal terminals 93 and the back surface metal body 53. If the solder containing Ni balls described above is used as the bonding material 154, a predetermined thickness can be ensured, making it easier to ensure an insulation distance. In addition, tilting of the relay board 150 can be suppressed.

The surface metal body 52 (relay wiring 55) has a notch 550, for example, as shown in FIG. 46, to expose the insulating base material 51. For example, the surface metal body 52 may have a chamfered portion 554. The chamfered portion 554 is provided at least on the surface of the end face defining the notch 550 where an imaginary line connecting the semiconductor element 40 and the relay substrate 150 intersects. The chamfered portion 554 is provided at the upper end of the end face. This ensures an insulating distance between the bonding wire 110 and the surface metal body 52.

An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S. In other words, an example of a semiconductor device 20 with a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, this example is not limited to this. It is also possible to apply to a semiconductor device 20 with a single-sided heat dissipation structure that includes only a substrate 50 to which the drain electrode 40D (first main electrode) is connected. Although an example has been shown in which both rear surface metal bodies 53, 63 are exposed from the sealing body 30, this is not limiting.

In the above example, the semiconductor device 20 includes a semiconductor element 40H that configures the upper arm 9H and a semiconductor element 40 that configures the lower arm 9L, but this is not limiting. It may also include only a semiconductor element 40 that configures one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, and third embodiments, and the modified examples.

Fifth Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to ensure insulation reliability while reducing the overall size, the connection between the metal member and the surface metal body via the bonding material may have a predetermined structure, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 57. Fig. 57 corresponds to Fig. 5.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 57, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 52 is connected to the P terminal 91P, which is the main terminal, and the output terminal 92 via a bonding material 104. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The surface metal body 62 is connected to the N terminal 91N, which is the main terminal, (not shown) via a bonding material 104. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, portions of the main terminals, and the bonding material 104.

<Main terminal joint structure>
Next, the joining structure of the main terminal will be described with reference to Figures 57 to 60. Figure 58 is a plan view of the periphery of the output terminal 92 in Figure 57 as seen from the LVIII direction. In Figure 58, some hatching is added for clarity. Figure 59 is an enlarged view of the area LIX indicated by the dashed line in Figure 57. Figure 60 is a view showing the state in which the joining material 104 has been removed from Figure 59. For convenience, the sealing body 30 is omitted from Figures 59 and 60.

As shown in Figure 57, the joining structure of the P terminal 91P, which is a main terminal, and the output terminal 92, with the substrate 50 differs from the configuration described in the preceding embodiment (see Figure 5). Although not shown, the joining structure of the N terminal 91N, which is a main terminal, is also different. The rest of the configuration is the same as the configuration described in the preceding embodiment. The output terminal 92 will be used as an example below. The joining material 104 wets and spreads over the metal surface during joining. As an example, the joining material 104 is solder.

As shown in Figure 57, the substrate 50 has ends 50c and 50d in the Y direction. End 50c is the end on the side surface 30c side of the sealing body 30, and end 50d is the end on the side surface 30d side. The output terminal 92 extends in the Y direction, straddling end 50d of the substrate 50. In a plan view in the Z direction, part of the output terminal 92 overlaps with the surface metal body 52 (relay wiring 55), and another part does not. As shown in Figures 58 to 60, the output terminal 92 has an opposing surface 920 and a housing portion 921.

The facing surface 920 is the portion of the underside of the output terminal 92 that faces the surface metal body 52 (relay wiring 55) of the substrate 50 in the Z direction. Macroscopically, the facing surface 920 is flat, and ideally, its entire surface contacts the upper surface 52a of the surface metal body 52. Microscopically, the facing surface 920 has minute irregularities on its surface, and at least a portion of it contacts the upper surface 52a. The facing surface 920 is sometimes referred to as a metal touch surface. In a plan view, the facing surface 920 is a portion that extends within a predetermined range in the Y direction from a position that overlaps with the end 52b of the surface metal body 52. The end 52b is the end face (side surface) on the side of the side surface 30d of the sealing body 30 in the Y direction, and is continuous with the upper surface 52a. The end 52b forms part of the end 50d. The facing surface 920 is approximately rectangular in plan view.

The accommodation portion 921 is provided adjacent to the opposing surface 920 and provides a storage space for the bonding material 104. For example, the accommodation portion 921 is a recess that is recessed relative to the opposing surface 920 in a direction away from the upper surface 52a. The recessed accommodation portion 921 is a surface that includes a Z-direction component and has a side surface 921a that is continuous with the opposing surface 920 and a bottom surface 921b that is continuous with the side surface 921a. The side surface 921a is, for example, a surface that is approximately parallel to the Z direction. The accommodation portion 921 opens to the tip surface 922, which is the side surface on the leading side of the output terminal 92 in the Y direction. The accommodation portion 921 opens to side surfaces 923 and 924 on both sides of the output terminal 92 in the X direction. The accommodation portion 921 is provided within a predetermined range from the tip surface 922 of the output terminal 92 in the Y direction. The accommodation portion 921 has an approximately rectangular planar shape. The accommodation portion 921 is provided in the Y direction aligned with the X direction.

The output terminal 92 houses the bonding material 104 in the housing 921 with the opposing surface 920 in contact with the surface metal body 52. The bonding material 104 may be disposed only within the housing 921, or, as shown in FIG. 59, a portion of the bonding material 104 may be disposed outside the housing 921. In FIG. 59, the bonding material 104 forms a fillet with respect to the tip surface 922. The output terminal 92 is connected (bonded) to the surface metal body 52 via the bonding material 104 disposed in the housing 921.

<Main terminal joining method>
The bonding structure between the output terminal 92 and the surface metal body 52 is formed, for example, as follows. With the bonding material 104 (solder) placed in the accommodation portion 921, the upper portion of the facing surface 920 of the output terminal 92 is pressed toward the substrate 50 in the Z direction so that the facing surface 920 is in strong contact with the upper surface 52a. Reflow is performed with the facing surface 920 in strong contact with the upper surface 52a. For this reason, during reflow, the bonding material 104 does not wet and spread toward the facing surface 920, or if it does, it only wets and spreads to the extent that it fills in the minute concavities and convexities on the surface of the facing surface 920.

<Summary of Fifth Embodiment>
In this embodiment, the facing surface 920 of the output terminal 92, which is a metal member, comes into contact (metal touch) with the upper surface 52a of the front surface metal body 52. This makes it possible to prevent the bonding material 104 from overflowing from the accommodation portion 921 toward the facing surface 920. This prevents the bonding material 104 from spreading in unintended directions, ensuring insulation reliability. Furthermore, the output terminal 92, which is a single member, has both the accommodation portion 921 and the facing surface 920. As a result, it is possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size.

In a configuration including a substrate 50, when the bonding material 104 spreads over the end 52b (end surface) of the front metal body 52 and, ultimately, the insulating substrate 51, the area at the same potential as the front metal body 52 expands, shortening the distance to the back metal body 53. There is also a risk that the bonding material 104 may come into contact with the back metal body 53. In this embodiment, the opposing surface 920 is located closer to the end 50d of the substrate 50, i.e., the end 52b of the front metal body 52, than the housing portion 921. By positioning the opposing surface 920 closer to the end 52b, the bonding material 104 can be prevented from spreading over the surface of the output terminal 92 and/or the front metal body 52 and reaching the end 52b and, ultimately, the insulating substrate 51. This improves insulation reliability without increasing the overall size.

As described above, the metal member having an opposing surface and a housing portion can also be applied to the other main terminals, the P terminal 91P and N terminal 91N. The P terminal 91P is connected to the surface metal body 52 (P wiring 54) of the substrate 50 via the bonding material 104. By having the opposing surface of the P terminal 91P contact the surface metal body 52, it is possible to prevent the bonding material 104 from overflowing from the housing portion of the P terminal 91P to the opposing surface side. As shown in Figure 57, by providing the opposing surface on the edge 50c side of the substrate 50, it is possible to prevent the bonding material 104 from wetting and spreading onto the edge of the surface metal body 52 and the insulating base material 51.

The N terminal 91N is connected to the surface metal body 62 (N wiring 64) of the substrate 60 via the bonding material 104. Contact between the opposing surface of the N terminal 91N and the surface metal body 62 prevents the bonding material 104 from overflowing from the housing of the N terminal 91N to the opposing surface side. Furthermore, by providing the opposing surface on the edge 60c side of the substrate 60 shown in FIG. 57, the bonding material 104 can be prevented from spreading onto the edge of the surface metal body 62 or the insulating base material 61. The edge 60c is the end face (side surface) on the side of the side surface 30c of the sealing body 30 in the Y direction.

<Modification>
The arrangement of the opposing surface 920 and the accommodating portion 921 is not limited to the example described above. For example, the configurations shown in Figs. 61 and 62 may be adopted. Fig. 61 is a plan view showing a modified example and corresponds to Fig. 58. Fig. 62 is a plan view seen from the direction LXII shown in Fig. 61. In this example, the accommodating portion 921 does not open to the side surfaces 923 and 924, but only to the tip surface 922. The accommodating portion 921 has an opening 921c in the tip surface 922, which is a side surface.

The opposing surface 920 has a first opposing portion 920a and a second opposing portion 920b. The first opposing portion 920a is located on the opposite side of the storage portion 921 from the opening 921c. The first opposing portion 920a is adjacent to the storage portion 921 in the Y direction, which is the extension direction of the output terminal 92. The second opposing portion 920b is adjacent to the storage portion in the X direction. In the example shown in Figures 61 and 62, the opposing surface 920 has a pair of second opposing portions 920b. The pair of second opposing portions 920b sandwich the storage portion 921 in the X direction. The opposing surface 920 has a generally U-shaped planar shape. Because the opposing surfaces 920 are arranged on three sides of the storage portion 921, the overflow direction of the bonding material 104 from the storage portion 921 can be limited to one direction toward the opening 921c. This further improves insulation reliability.

The opposing surface 920 may also be configured to include only one second opposing portion 920b. In this case, the opposing surface 920 has a generally L-shaped planar shape. Because the opposing surface 920 is arranged on two sides relative to the storage portion 921, the direction in which the bonding material 104 overflows from the storage portion 921 can be restricted compared to the arrangement shown in Figure 58. This can improve insulation reliability.

Although an example has been shown in which the accommodating portion 921 opens on the side surface of the output terminal 92, this is not limiting. Furthermore, the planar shape of the accommodating portion 921 is not limited to a substantially rectangular shape. For example, as shown in FIG. 63, a accommodating portion 921 without an opening on the side surface may be provided. FIG. 63 is a plan view showing a modified example and corresponds to FIG. 58. In FIG. 63, the accommodating portion 921 has a substantially circular planar shape. The accommodating portion 921 is a hole that opens on the underside of the output terminal 92. The accommodating portion 921 shown in FIG. 63 is a blind hole. The accommodating portion 921 that is a blind hole has a side surface 921a and a bottom surface 921b that are continuous with the opposing surface 920, similar to the accommodating portion 921 described above. Alternatively, a through hole that opens on the top surface of the output terminal 92 may be used. The accommodating portion 921 that is a through hole does not have a bottom surface 921b, but has a side surface 921a.

Metal members having opposing surfaces and housing portions are not limited to main terminals. For example, as shown in Figures 64 and 65, in a semiconductor device 20 constituting an upper and lower arm circuit 9, an opposing surface and housing portion may be provided in a joint portion 81. Figure 64 is a cross-sectional view showing a modified example and corresponds to Figure 57. Figure 65 is an enlarged view of the area LXV indicated by the dashed line in Figure 64. For convenience, the sealing body 30 is omitted from Figure 65.

As described in the previous embodiment, the semiconductor device 20 includes a semiconductor element 40H, which is a first semiconductor element constituting the upper arm 9H, and a semiconductor element 40L, which is a second semiconductor element constituting the lower arm 9L. The joint portion 81 electrically connects the source electrode 40S of the semiconductor element 40H to the drain electrode 40D of the semiconductor element 40L. The joint portion 81 is a metal pillar extending in the Z direction. The end portion 81a of the joint portion 81 is connected to the relay wiring 55, which is the first wiring of the substrate 50, via a bonding material 103. The end portion 81b opposite the end portion 81a is connected to the relay wiring 65, which is the third wiring of the substrate 60, via a bonding material 103. The surface metal body 52 includes a P wiring 54, which is the second wiring, provided with a predetermined distance from the relay wiring 55. The surface metal body 62 includes an N wiring 64, which is the fourth wiring, provided with a predetermined distance from the relay wiring 65.

In the example shown in Figures 64 and 65, an opposing surface 810 and a storage portion 811 are provided on each of the end portions 81a, 81b of the joint portion 81. The configuration of the opposing surface 810 and the storage portion 811 is similar to that of the opposing surface 920 and the storage portion 921 described above. At the end portion 81a, the opposing surface 810 faces the upper surface 52a of the surface metal body 52 (relay wiring 55). The opposing surface 810 is in contact with the upper surface 52a. The storage portion 811 is a recess that is recessed relative to the opposing surface 810. The storage portion 811 has a side surface 811a that is continuous with the opposing surface 810, and a bottom surface 811b. The storage portion 811 stores the bonding material 103.

The opposing surface 810 and the accommodating portion 811 are arranged side by side in the Y direction. The opposing surface 810 is located on the side of the wiring gap 52G separating the relay wiring 55 and the P wiring 54, that is, close to the P wiring 54, which is a separate wiring from the relay wiring 55 to which the joint portion 81 is connected. The accommodating portion 811 opens to a side surface 812 of the joint portion 81 in the Y direction, but does not open to a side surface 813 opposite the side surface 812. The accommodating portion 811 may open only to the side surface 812, or may open to three side surfaces including the two side surfaces adjacent to the side surface 812.

In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 52. This prevents the bonding material 103 from overflowing from the housing portion 811 to the opposing surface 810. This makes it possible to provide a semiconductor device 20 that achieves both insulation reliability and compact size.

Furthermore, when the bonding material 103 wets and spreads into the inter-wiring gap 52G of the surface metal body 52, the area at the same potential as the relay wiring 55 expands, shortening the distance to the P wiring 54. There is a risk that the bonding material 103 may come into contact with the P wiring 54. In contrast, in the example described above, the opposing surface 810 is positioned closer to the P wiring 54, i.e., the inter-wiring gap 52G, than the accommodating portion 811. This prevents the bonding material 103 from reaching the inter-wiring gap 52G. This improves insulation reliability without increasing the physical size.

The configuration of the end 81b is the same as that of the end 81a. At the end 81b, the opposing surface 810 faces the upper surface 62a of the surface metal body 62 (relay wiring 65). The opposing surface 810 is in contact with the upper surface 52a. The accommodation portion 811 is a recess. The accommodation portion 811 accommodates the bonding material 103. The opposing surface 810 and the accommodation portion 811 are arranged side by side in the Y direction. The opposing surface 810 is located on the wiring gap 62G side separating the relay wiring 65 and the N wiring 64, that is, near the N wiring 64, which is a separate wiring from the relay wiring 65 to which the joint portion 81 is connected. The accommodation portion 811 opens to the side surface 813 of the joint portion 81 in the Y direction, but not to the side surface 812. The accommodation portion 811 may open only to the side surface 813, or may open to three side surfaces, including the two side surfaces adjacent to the side surface 813.

In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 62. This prevents the bonding material 103 from overflowing from the accommodation portion 811 toward the opposing surface 810. This makes it possible to provide a semiconductor device 20 that achieves both high insulation reliability and a compact size. Furthermore, the opposing surface 810 is located closer to the N wiring 64, i.e., the inter-wiring gap 62G, than the accommodation portion 811. This prevents the bonding material 103 from reaching the inter-wiring gap 62G. This allows for improved insulation reliability without increasing the size.

In the above example, overflow of the bonding material was suppressed by contact of the surface metal body with the opposing surfaces of the metal members. The function of suppressing overflow may be enhanced by further adding a rough oxide film formed by laser irradiation to this configuration. An example is shown in Figures 66 and 67. Figure 66 is a cross-sectional view corresponding to Figure 65, and for convenience, the sealing body 30 has been omitted. Figure 67 is an enlarged view of area LXVII indicated by the dashed dotted line in Figure 66, showing only the surface metal body 52.

In the example shown in Figure 66, uneven oxide films 520, 620 are provided on the surface metal bodies 52, 62, respectively, corresponding to the joint portion 81. The uneven oxide film 520 will be described below as an example. As shown in Figure 67, the surface metal body 52 has a base material 521, a metal film 522 provided on the surface of the base material 521, and an uneven oxide film 520. The base material 521 forms the main portion of the surface metal body 52. The base material 521 is formed using, for example, a Cu-based material. The metal film 522 is formed using a material that has higher solder wettability than the base material 521. The metal film 522 is formed over the entire upper surface 52a. In this embodiment, the metal film 522 is formed over the entire surface of the base material 521. The uneven oxide film 520 is formed locally on the upper surface 52a.

The uneven oxide film 520 is locally formed on the metal film 522 on the upper surface 52a by irradiating the metal film 522 with laser light. The metal film 522 has a base film primarily composed of Ni (nickel) and a top film primarily composed of Au (gold). In this embodiment, an electroless Ni plating film containing P (phosphorus) is used as the base film. When the bonding material 103 is solder, the top film (Au) of the metal film 522 exposed from the uneven oxide film 520 in the portion that comes into contact with the bonding material 103 diffuses into the solder during reflow. The top film (Au) of the metal film 522 in the portion where the uneven oxide film 520 is to be formed is removed by irradiation with laser light when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film primarily composed of Ni. For example, the components constituting the uneven oxide film 520 are 80% NI ₂ O ₃ , 10% NiO, and 10% Ni.

The recesses 523 on the surface of the metal film 522 are formed by irradiating it with pulsed laser light. One recess 523 is formed per pulse. The uneven oxide film 520 is formed when the surface portion of the metal film 522 is melted, vaporized, and deposited by irradiating it with laser light. The uneven oxide film 520 is an oxide film derived from the metal film 522. The uneven oxide film 520 is a film of oxide of the metal (Ni), the main component of the metal film 522. The uneven oxide film 520 is formed to resemble the unevenness of the surface of the metal film 522, which has the recesses 523. The surface of the uneven oxide film 520 has recesses and projections formed at a pitch finer than the width of the recesses 523. In other words, very fine recesses and projections (roughened portions) are formed.

Such an uneven oxide film 520 can be formed by the following process. First, a pulsed laser beam is irradiated onto the upper surface 52a of the surface metal body 52, which has a metal film 522 formed on a base material 521, to melt and evaporate the surface of the metal film 522. The pulsed laser beam is adjusted so that the energy density is greater than 0 J/ ^cm² and less than or ^equal to 100 J/cm² and the pulse width is less than or equal to 1 μsec. To satisfy these conditions, a YAG laser, a _YVO₄ laser, a fiber laser, or the like can be used. For example, in the case of a YAG laser, an energy density of 1 J/ ^cm² or more is sufficient. In the case of electroless Ni plating, the metal film 522 can be processed even with an energy density of, for example, about 5 J/ ^cm² .

At this time, the laser light source and the surface metal body 52 are moved relative to each other, and the laser light is scanned and irradiated sequentially at multiple positions. By irradiating the surface of the metal film 522 with laser light and melting and vaporizing it, recesses 523 are formed on the surface of the metal film 522. The average thickness of the portions of the metal film 522 irradiated with laser light is thinner than the average thickness of the portions not irradiated with laser light. Furthermore, the multiple recesses 523 formed corresponding to the laser light spots are connected together, forming, for example, a scale-like shape. A spot is the area irradiated by one pulse. For example, the laser light is scanned so that adjacent laser light spots partially overlap in the X direction and adjacent laser light spots partially overlap in the Y direction.

The molten metal film 522 is then solidified. Specifically, the molten and vaporized metal film 522 is deposited on the area irradiated with the laser light and its surrounding areas. By depositing the molten and vaporized metal film 522 in this manner, a rough oxide film 520 is formed on the surface of the metal film 522.

In FIG. 66, the uneven oxide film 520 is not provided in a first region 524 of the upper surface 52a of the surface metal body 52 that overlaps with the accommodating portion 811 of the joint portion 81 in a planar view. The uneven oxide film 520 is selectively provided in a second region 525 that overlaps with the opposing surface 810. The configurations of the surface metal body 62 and the uneven oxide film 620 are similar to those of the surface metal body 52 and the uneven oxide film 520. The uneven oxide film 620 is not provided in a first region 624 of the upper surface 62a of the surface metal body 62 that overlaps with the accommodating portion 811 of the joint portion 81 in a planar view. The uneven oxide film 620 is selectively provided in the second region 625 that overlaps with the opposing surface 810.

Compared to metal films, oxide films (rough oxide films 520, 620) have lower wettability with the bonding material 103. Because the rough oxide films 520, 620 have fine irregularities on their surfaces, their contact area with the bonding material 103 is reduced, and portions of the bonding material 103 become spherical due to surface tension. In other words, the contact angle is increased. This results in lower wettability with the bonding material 103. Therefore, due to the reduced wettability caused by the rough oxide films 520, 620 and the contact effect with the opposing surface 810, the bonding material 103 is less likely to pass between the opposing surface 810 and the second region 525, 625. This more effectively prevents the bonding material 103 from overflowing. The rough oxide films 520, 620 are formed using laser light, as described above, making patterning easy.

As shown in FIG. 68, the uneven oxide films 520, 620 may be provided in peripheral regions 526, 626. The peripheral region 526 is the region surrounding the second region 525 in a plan view, excluding the first region 524. The peripheral region 626 is the region surrounding the second region 625 in a plan view, excluding the first region 624. Even if the bonding material 103 passes directly below the opposing surface 810 of the joint portion 81, it can be blocked by the uneven oxide films 520, 620. Furthermore, because the surfaces of the uneven oxide films 520, 620 are formed with very fine irregularities, the sealing body 30 becomes entangled, creating an anchor effect. Furthermore, the contact area with the sealing body 30 is increased. This increases the adhesion of the surface metal bodies 52, 62 to the sealing body 30.

The uneven oxide films 520, 620 may be provided in the second regions 525, 625 and the peripheral regions 526, 626. Only one of the uneven oxide films 520, 620 may be provided. The uneven oxide films 520, 620 may also be used at the junctions with the main terminals, which are metal members, i.e., the P terminal 91P, the N terminal 91N, and the output terminal 92.

An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S (second main electrode). In other words, an example of a semiconductor device 20 with a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, this example is not limited to this. It is also applicable to a semiconductor device 20 with a single-sided heat dissipation structure that includes only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a semiconductor device 20 with a pair of substrates 50, 60, the above structure may be applied only to the joint between one of the substrates 50, 60 and the metal member. An example has been shown in which both back surface metal bodies 53, 63 are exposed from the sealing body 30, but this is not limited to this.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, and fourth embodiments, and the modified examples.

Sixth Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to improve the reliability of the semiconductor device, as described in this embodiment, the physical properties of the sealing body and the physical properties of the insulating base material may satisfy a predetermined relationship.

<Semiconductor device and heat dissipation structure>
The semiconductor device 20 of this embodiment and its heat dissipation structure will be described with reference to Fig. 69. Fig. 69 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 69 is an enlarged view of a portion of Fig. 5. For convenience, the external connection terminals 90 are omitted from Fig. 69.

The semiconductor device 20 of this embodiment has a structure similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 69, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The back surface metal bodies 53 and 63 are exposed from the sealing body 30. The insulating base materials 51 and 61 contain resin. The sealing body 30 contains resin. Although not shown, the semiconductor device 20 also includes a semiconductor element 40L.

Figure 69 shows the semiconductor device 20, along with the heat exchanger 121 of the cooler 120 and a thermally conductive member 130 such as heat dissipation gel. In other words, Figure 69 shows a semiconductor module 140 comprising the semiconductor device 20, the cooler 120, and the thermally conductive member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged alongside the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

The rear surface metal bodies 53, 63 are exposed from the sealing body 30 as the rear surfaces 50b, 60b of the substrates 50, 60. One of the heat exchanger sections 121 of the cooler 120 is disposed opposite one surface 30a and the rear surface 50b of the sealing body 30, and the other heat exchanger section 121 is disposed opposite the rear surface 30b and the rear surface 60b of the sealing body 30. A thermal conduction member 130 is disposed between the opposing surfaces of the semiconductor device 20 and the heat exchanger section 121. The thermal conduction member 130 is in close contact with the semiconductor device 20 and the heat exchanger section 121.

<Relationship with glass transition temperature>
Next, the relationship between the glass transition points of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to FIGS.

Figure 70 is a diagram showing an example of the relationship between the glass transition point Tgs and linear expansion coefficient αs of the sealing body 30 and the glass transition point Tgi and linear expansion coefficient αi of the insulating substrates 51 and 61. In Figure 70, the vertical axis represents the linear expansion coefficient α, and the horizontal axis represents temperature. In Figure 70, the solid line represents the linear expansion coefficient αs of the sealing body 30, and the dashed line represents the linear expansion coefficient αi of the insulating substrates 51 and 61. Of the linear expansion coefficients αs, α1s represents the linear expansion coefficient at temperatures lower than the glass transition point Tgs, i.e., the linear expansion coefficient in the α1 region. α2s represents the linear expansion coefficient at temperatures higher than the glass transition point Tgs, i.e., the linear expansion coefficient in the α2 region. The same is true for the linear expansion coefficient αi, where α1i represents the linear expansion coefficient in the α1 region and α2s represents the linear expansion coefficient in the α2 region.

As shown in Figure 69, the encapsulant 30 is in close contact with the semiconductor element 40. The insulating substrates 51, 61 are thermally connected to the semiconductor element 40 via bonding materials 100, 101, 102 and surface metal bodies 52, 62. Therefore, when the semiconductor element 40 is operating (generating heat), the temperature of the peripheral position MP1 of the encapsulant 30 around the semiconductor element 40 is higher than the temperatures of the positions MP2, MP3 of the insulating substrates 51, 61 that overlap with the semiconductor element 40. In this way, the encapsulant 30 has a higher temperature than the insulating substrates 51, 61.

When the temperature of the sealing body 30 exceeds the glass transition point Tgs, the Young's modulus decreases, and the sealing function of the sealing body 30 deteriorates. This deterioration in sealing function can cause thermal stress to concentrate on the drain electrode 40D, the source electrode 40S, and their junctions, potentially causing cracks or other problems. In other words, there is a risk of reduced connection reliability. In contrast, in this embodiment, the relationship Tgs > Tgi is satisfied, as shown in Figure 70.

<Relationship between linear expansion coefficients>
Next, the relationship between the linear expansion coefficients of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to Figures 70 to 72. Figures 71 and 72 are conceptual diagrams showing warping of the semiconductor device 20. Figures 71 and 72 show only the resin elements that make up the semiconductor device 20, that is, only the sealing body 30 and the insulating base materials 51 and 61.

When the semiconductor element 40 is in operation (heat generation), if the linear expansion coefficient αs of the sealing body 30 is greater than the linear expansion coefficient αi of the insulating base materials 51 and 61, the amount of expansion of the sealing body 30 will be greater than the amount of expansion of the insulating base materials 51 and 61, as shown by the dashed arrows in Figure 71. In other words, the amount of expansion will be greater in the center in the Z direction and smaller at both ends. Therefore, both ends in the Z direction will have a concave shape.

In this embodiment, as shown in Figure 70, the αi > αs relationship is satisfied. Specifically, the α1i > α1s relationship is satisfied in the α1 region, and the α2i > α2s relationship is satisfied in the α2 region. As described above, the Tgs > Tgi relationship is satisfied, and therefore the αi > αs relationship is satisfied throughout the entire operating temperature range. Therefore, when the semiconductor element 40 is operating (heat generation), the amount of expansion of the insulating substrates 51, 61 is greater than the amount of expansion of the encapsulant 30, as shown by the dashed arrows in Figure 72. In other words, the amount of expansion is smaller in the center in the Z direction and greater at both ends. Therefore, as shown in Figure 72, the shape of the semiconductor device 20 is convex at both ends in the Z direction.

<Summary of Sixth Embodiment>
According to this embodiment, the glass transition temperature Tgs of the sealing body 30 is higher than the glass transition temperature Tgi of the insulating base materials 51 and 61. This makes it difficult for the temperature of the sealing body 30, which reaches a higher temperature during operation of the semiconductor element 40, to exceed the glass transition temperature Tgs. The temperature of the sealing body 30 does not exceed the glass transition temperature Tgs, or exceeds it only slightly. Therefore, the Young's modulus of the sealing body 30 is reduced, and deterioration of the sealing function can be suppressed. Since deterioration of the sealing function can be suppressed, stress concentration on the drain electrode 40D and source electrode 40S, which are the main electrodes, and their junctions can be suppressed. In other words, connection reliability can be improved.

The glass transition temperature Tgs of the sealing body 30 may be set to be approximately equal to the glass transition temperature Tgi of the insulating base materials 51 and 61. Compared to when Tgs is lower than Tgi, the temperature of the sealing body 30, which becomes higher when heat is generated, is less likely to exceed the glass transition temperature Tgs.

Furthermore, the linear expansion coefficient αi of the insulating substrates 51 and 61 is greater than the linear expansion coefficient αs of the sealing body 30. As a result, when the semiconductor element 40 is in operation, the amount of expansion of the insulating substrates 51 and 61 is greater than the amount of expansion of the sealing body 30. In other words, the amount of expansion is small at the center in the Z direction and large at both ends. This causes the semiconductor device 20 to warp outward in the Z direction. This reduces the opposing distance between the semiconductor device 20 and the cooler 120 (121), reducing the thermal resistance between the semiconductor device 20 and the cooler 120. Specifically, the thickness of the thermal conduction member 130 is reduced, reducing the thermal resistance. Because heat from the semiconductor element 40 can be efficiently dissipated, the semiconductor element 40 can be prevented from overheating. In other words, heat dissipation is improved.

The linear expansion coefficient αi of the insulating substrates 51, 61 may be approximately equal to the linear expansion coefficient αs of the sealing body 30. In this case, the amount of expansion is approximately equal at the center and both ends in the Z direction, preventing both ends in the Z direction from becoming concave. In other words, an increase in thermal resistance between the semiconductor device 20 and the cooler 120 due to a concave shape can be prevented.

In this way, by satisfying the relationships Tgs≧Tgi and αi≧αs, a highly reliable semiconductor device 20 can be provided.

<Modification>
Although the semiconductor device 20 has been described as having a double-sided heat dissipation structure including a pair of substrates 50 and 60, the present invention is not limited to this example and can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, and fifth embodiments, and the modified examples.

Seventh Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress peeling of the sealing body, the surface metal body may have a predetermined structure as described in this embodiment.

<Semiconductor Device>
73 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG. 73 corresponds to FIG.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 73, the semiconductor device 20 includes two semiconductor elements 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40, via a bonding material 100. The front surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40, via a bonding material 102. The sealing body 30 seals the semiconductor elements 40, substrates 50 and 60, and bonding materials 100 and 102. The back surface metal bodies 53 and 63 of the substrates 50 and 60 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L.

As shown in Figure 73, the surface metal bodies 52, 62 have roughened portions 527, 627 and non-roughened portions 528, 628.

<Uneven oxide film>
Next, the uneven oxide film 520 constituting the roughened portion 527 will be described in detail with reference to Figures 74 and 75. Figure 74 is an enlarged view of region LXXIV in Figure 73. Figure 75 is a view showing a method for forming the roughened portion.

The surface metal bodies 52, 62 have uneven oxide films 520, 620, similar to the configuration described in the modified example of the fifth embodiment (see Figures 66 and 67). The uneven oxide films 520, 620 provide roughened portions 527, 627 on the surfaces of the surface metal bodies 52, 62. Portions of the surfaces of the surface metal bodies 52, 62 where the uneven oxide films 520, 620 are not formed provide non-roughened portions 528, 628. The following explanation will be given using the surface metal body 52 as an example.

As shown in FIG. 74, the surface metal body 52 has a base material 521, and a plating film 522p and a rough oxide film 520 provided on the surface of the base material 521. The base material 521 forms the main portion of the surface metal body 52. The base material 521 is formed using, for example, a Cu-based material. The plating film 522p is formed from a material that has higher wettability with a joining material 100 such as solder than the base material 521. The plating film 522p is formed over the entire upper surface 52a and the entire side surface 52c of the surface metal body 52. The side surface 52c is a surface of the surface metal body 52 that connects the upper surface 52a and the lower surface 52d that faces the insulating base material 51.

The uneven oxide film 520 is formed by irradiating the plating film 522p with laser light, as described in the modified example of the fifth embodiment. In this embodiment, the laser light is irradiated onto the upper surface 52a and the side surface 52c of the surface metal body 52. The roughened portion 527 provided by the uneven oxide film 520 is the portion of the upper surface 52a excluding the non-roughened portion 528. As an example, the roughened portion 527 is formed over the entire side surface 52c. At the end of the surface metal body 52, the roughened portion 527 is provided continuously from the side surface 52c to the upper surface 52a. The roughened portion 527 is provided on a portion of the upper surface 52a and on the side surface 52c. The roughened portion 527 may be provided only on the edge of the upper surface 52a. The non-roughened portion 528 is provided on a portion of the upper surface 52a and includes at least the placement area (bonding area) of the bonding material 100. The non-roughened portion 528 may be provided only in the bonding region, or may include regions other than the bonding region. The roughened portion 527 is provided on at least a portion of the side surface 527. The roughened portion 527 may be provided on only a portion of the side surface 527. For example, the roughened portion 527 may be provided on only a portion of the side surface 527 so that the uneven oxide film 520 does not come into contact with the insulating substrate 51.

In this embodiment, the plating film 522p has a base film primarily composed of Ni (nickel) and a top film primarily composed of Au (gold). Specifically, an electroless Ni plating film containing P (phosphorus) is used as the base film. When the bonding material 100 is solder, the top film (Au) of the plating film 522p exposed from the uneven oxide film 520, which comes into contact with the bonding material 100, diffuses into the solder during reflow. The top film (Au) of the plating film 522p in the portion where the uneven oxide film 520 is to be formed is removed by irradiation with laser light when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film primarily composed of Ni. The uneven oxide film 520 is continuously provided from the side surface 52c to the top surface 52a at the end of the surface metal body 52.

As described in the modified example of the fifth embodiment, the uneven oxide film 520 is formed by melting, vaporizing, and depositing the surface portion of the plating film 522p through irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the plating film 522p. The uneven oxide film 520 is a film of oxide of the metal (Ni), which is the main component of the plating film 522p. The surface of the uneven oxide film 520 always has fine irregularities (roughened portions). The uneven oxide film 520 has a continuously uneven surface.

In this embodiment, the surface metal body 52 has a larger area on the lower surface 52d than on the upper surface 52a. Therefore, as shown in Figure 74, the lower surface 52d protrudes from the upper surface 52a. In other words, in a plan view in the Z direction, at least a portion of the side surface 52c is located outside the upper surface 52a. Therefore, as shown in Figure 75, by irradiating laser light in the Z direction, a rough oxide film 520 can be formed on the upper surface 52a and the side surface 52c.

<Summary of Seventh Embodiment>
In a configuration in which the plating film 522p is provided on the top surface 52a and side surface 52c of the surface metal body 52, thermal stress tends to cause the sealing body 30 to peel off from the end of the surface metal body 52, i.e., the side surface 52c. In contrast, in this embodiment, the roughened portion 527 is provided on the top surface 52a and the side surface 52c, excluding the non-roughened portion 528. This increases the adhesion between the sealing body 30 and the side surface 52c of the surface metal body 52, compared to a configuration in which the roughened portion 527 is not provided. Therefore, peeling of the sealing body 30 at the side surface 52c of the surface metal body 52 can be suppressed. By suppressing peeling, thermal stress can be suppressed from concentrating on the bonding portion of the surface metal body 52, such as the bonding material 100. As a result, a highly reliable semiconductor device 20 can be provided.

The surface metal body 62 has a configuration similar to that of the surface metal body 52. The surface metal body 62 has roughened portions 627 on the upper surface 62a (excluding the non-roughened portion 628) and on the side surfaces 62c. This prevents the sealing body 30 from peeling off on the side surfaces 62c of the surface metal body 62.

In this embodiment, the roughened portions 527, 627 are provided continuously across the side surfaces 52c, 62c and the top surfaces 52a, 62a. This prevents the sealing body 30 from peeling off near the ends of the surface metal bodies 52, 62.

Roughening treatments that can be used to form the roughened portions 527, 627 include roughening plating, sandblasting, and chemical treatment. In this embodiment, laser roughening is used. The uneven oxide films 520, 620 are formed by irradiating the plating film with laser light. The surface metal bodies 52, 62 have the uneven oxide films 520, 620 on the roughened portions 527, 627.

The surfaces of the uneven oxide films 520, 620 have continuous irregularities, which allow the sealant 30 to become entangled, creating an anchor effect. Furthermore, the contact area with the sealant 30 is increased. This increases the adhesion strength of the roughened portions 527, 627 to the sealant 30. Furthermore, the uneven oxide films 520, 620 have lower wettability with the bonding materials 100, 102 than the plating film (plating film 522p). Because the uneven oxide films 520, 620 have fine irregularities on their surfaces, the contact area with the bonding materials 100, 102 is reduced, and portions of the bonding materials 100, 102 become spherical due to surface tension. In other words, the contact angle increases. This prevents the bonding materials 100, 102 from overflowing. Thus, the use of the uneven oxide films 520, 620 increases the adhesion strength to the sealant 30 and prevents the bonding materials 100, 102 from overflowing from the bonding portion.

In this embodiment, the area of the surface metal bodies 52, 62 is larger on the lower surfaces 52d, 62d than on the upper surfaces 52a, 62a. The lower surfaces 52d, 62d protrude relative to the upper surfaces 52a, 62a. This makes it easier to physically roughen the side surfaces 52c, 62c in the Z direction. In the case of the laser roughening described above, by irradiating laser light in the Z direction, it is possible to form uneven oxide films 520, 620 not only on the upper surfaces 52a, 62a but also on the side surfaces 52c, 62c.

<Modification>
The side shape of the surface metal bodies 52, 62 is not limited to the above example. When patterning the surface metal bodies 52, 62 by press working, etching, cutting, or the like, the side can be processed into a predetermined shape. Figure 76 is a cross-sectional view showing a modified side shape. In Figure 76, the surface metal body 52 is shown as an example, and for convenience, the plating film 522p is omitted from the illustration. Although not shown, a similar configuration can also be adopted for the surface metal body 62.

In the example shown in Figure 76, the surface metal body 52 has a side surface 52c that is approximately parallel to the Z direction. In other words, the area of the surface metal body 52 is approximately constant in the Z direction. To physically roughen such a surface metal body 52, for example, the top surface 52a and the side surface 52c can be roughened separately. In the case of laser roughening, laser light is irradiated onto the side surface 52c from a direction different from the direction of laser light irradiation onto the top surface 52a, for example, from a direction tilted with respect to the Z direction. This allows a rough oxide film 520 to be formed on the side surface 52c.

Figure 77 is a cross-sectional view showing a modified example of the side shape, and corresponds to Figure 76. In the example shown in Figure 77, the area of the surface metal body 52 perpendicular to the Z direction increases as it approaches the lower surface 52d. The side surface 52c is rounded. In this case, the entire side surface 52c is located outside the upper surface 52a in a plan view. Therefore, it is easier to physically roughen the side surface 52c from the Z direction, for example, by laser roughening, than with the configuration shown in Figure 75.

Figure 78 is a cross-sectional view showing a modified example of the side shape, and corresponds to Figure 76. In the example shown in Figure 78, the area of the surface metal body 52 perpendicular to the Z direction increases as it approaches the lower surface 52d. The surface metal body 52 has a generally trapezoidal shape in the ZY plane, for example. In this case, too, the entire side surface 52c is located outside the upper surface 52a in a planar view, making it easy to physically roughen the side surface 52c from the Z direction.

Although an example of a semiconductor device 20 with a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, this is not limiting. It can also be applied to a semiconductor device 20 with a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, the roughened portion structure including the side surface described above may be applied to only one of the substrates 50, 60.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, and sixth embodiments, and the modified examples.

Eighth Embodiment
This embodiment is a modification of the previous embodiment, and the description of the previous embodiment can be used. To reduce inductance, the thickness of the surface metal body and the spacing between the wirings may satisfy a predetermined relationship, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment, particularly the circuit pattern of the surface metal bodies 52, 62, will be described with reference to Fig. 79. Fig. 79 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 79 illustrates a portion of the configuration described in the preceding embodiment (see Fig. 8).

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 79, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, substrates 50 and 60, and bonding materials 100 and 102. Of the substrates 50 and 60, the back surface metal bodies 53 and 63 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 also includes a semiconductor element 40L that constitutes a lower arm 9L.

<Relationship between wiring spacing and thickness>
Next, the relationship between the wiring spacing and thickness will be described with reference to Figures 79 and 80. Figure 80 is an enlarged view of region LXXX in Figure 79. Figure 80 shows only the substrate 60.

The surface metal bodies 52, 62 have inter-wiring gaps 52G, 62G, similar to the configuration described in the previous embodiment (see Figure 65). As shown in Figures 79 and 80, the inter-wiring gap 62G separates adjacent N wiring 64 and relay wiring 65. The inter-wiring gap 62G is a predetermined gap provided in the surface metal body 62 between wirings with different potentials.

As shown in Figure 80, in this embodiment, the distance L10 between the N wiring 64 and the relay wiring 65 is less than or equal to the thickness T10 of the surface metal body 62 (L10 < T10). The distance L10 is the length of the inter-wiring gap 62G, i.e., the inter-pattern distance between the N wiring 64 and the relay wiring 65. In Figures 79 and 80, the distance L10 and thickness T10 in the surface metal body 62 satisfy the relationship L10 < T10. Although not shown, the substrate 50 including the surface metal body 52 has the same configuration as the substrate 60. In the surface metal body 52, the distance L10 between the P wiring 54 and the relay wiring 55 is less than or equal to the thickness T10 of the surface metal body 52 (L10 < T10).

<Simulation results>
Figures 81 to 83 show the results of electromagnetic field simulations. Figure 81 summarizes the simulation results as a relationship between length (spacing, thickness) and inductance. The circles at the measurement points represent the results for three levels of thickness T10 (0.3 mm, 1.5 mm, and 2.5 mm) when the spacing L10 is fixed at 1.5 mm. The solid line in the figure represents the change in inductance with changes in thickness T10 when the spacing L10 is fixed. The squares at the measurement points represent the results for three levels of spacing L10 (0.5 mm, 1.5 mm, and 2.5 mm) when the thickness T10 is fixed at 1.5 mm. The dashed line in the figure represents the change in inductance with changes in spacing L10 when the thickness T10 is fixed. The length on the horizontal axis in Figure 81 represents the length of thickness T10 when the spacing L10 is fixed, and the length of spacing L10 when the thickness T10 is fixed.

Figure 82 shows the simulation results when L10 > T10. Figure 82 shows the simulation results when the first condition C1 shown in Figure 81 is met, specifically when the distance L10 = 1.5 mm and the thickness T10 = 0.3 mm. Figure 83 shows the simulation results when L10 < T10. Figure 83 shows the simulation results when the second condition C2 shown in Figure 81 is met, specifically when the distance L10 = 1.5 mm and the thickness T10 = 2.5 mm. In the simulations, all conditions are the same except for the distance L10 and the thickness T10.

The results shown in Figure 81 clearly show that inductance can be reduced in the range where the relationship L10≦T10 is satisfied. In particular, it is clear that inductance can be effectively reduced in the range where the relationship L10<T10 is satisfied.

As shown in Figure 82, when L10 > T10, the current is dispersed in the width direction in the extension portion 641 of the N wiring 64, but flows biased toward the end of the surface metal body 62 (substrate 60). As a result, the PN current loop (see Figure 17) described in the previous embodiment is large. Because the current path flowing through the extension portion 421 is far from the relay wiring 65, the effect of canceling out the magnetic flux due to the reverse current component is weakened. Figure 82 shows that the inductance is larger than when the relationship L10 ≤ T10 is satisfied.

As shown in Figure 83, when L10 < T10, the current flows biased toward the end of the extension portion 641 on the relay wiring 65 side in the width direction. As a result, the PN current loop is small. Because the current path through the extension portion 421 is close to the relay wiring 65, the effect of canceling out the magnetic flux due to the reverse current component is strengthened. Figure 83 shows that the inductance is smaller than when the relationship L10 > T10 is satisfied.

<Summary of Eighth Embodiment>
In this embodiment, the surface metal body 52 has a P wiring 54, which is a first wiring, and a relay wiring 55, which is a second wiring having a different potential from the first wiring. The distance L10 between the P wiring 54 and the relay wiring 55 and the thickness T1 of the surface metal body 52 satisfy the relationship L10≦T10. Similarly, the surface metal body 62 has an N wiring 64, which is a first wiring, and a relay wiring 65, which is a second wiring having a different potential from the first wiring. The distance L10 between the N wiring 64 and the relay wiring 65 and the thickness T1 of the surface metal body 62 satisfy the relationship L10≦T10.

When the relationship L10≦T10 is satisfied, the spacing between adjacent wiring is narrow, which enhances the cancellation effect between the magnetic flux caused by the current flowing in the first wiring and the magnetic flux caused by the current flowing in the second wiring, thereby reducing inductance. Furthermore, because the surface metal body is thick, the cross-sectional area of the current path is large, which reduces inductance. As a result, the semiconductor device 20 of this embodiment is able to reduce inductance. In particular, when the relationship L1<T10 is satisfied, the above-mentioned effects are enhanced, and inductance can be reduced more effectively.

<Modification>
While an example of a semiconductor device 20 with a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. It is also applicable to a semiconductor device 20 with a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, only one of the surface metal bodies 52, 62 may satisfy the above-described relationship L10≦T10. That is, it is sufficient that the surface metal body has first and second wirings in at least one substrate electrically connected to the main electrode of the semiconductor element, and that the relationship L10≦T10 is satisfied. Furthermore, while an example has been shown in which the relationship L10≦T10 is satisfied in the entire opposing region between the N wiring 64, which is the first wiring, and the relay wiring 65, which is the second wiring having a different potential from the first wiring, the present invention is not limited to this. It is sufficient that the relationship L10≦T10 is satisfied in at least a portion of the opposing region. The same applies to the opposing region between the P wiring 54, which is the first wiring, and the relay wiring 55, which is the second wiring having a different potential from the first wiring.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, and seventh embodiments, as well as the modified examples.

Ninth Embodiment
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. To improve heat dissipation and reliability, the side surface of the substrate may have a predetermined shape, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 84. Fig. 84 is a cross-sectional view corresponding to Fig. 5. For convenience, the external connection terminals 90 are not shown in Fig. 84.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 84, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102.

<Substrate>
Next, the substrates 50 and 60 will be described with reference to FIGS. 84 to 86. FIG. 85 is a plan view showing the center of the substrate. FIG. 85 corresponds to FIG. 12. FIG. 86 is an enlarged view of the area LXXXVI indicated by the dashed line in FIG. 84. In the following, "inside" and "outside" refer to the relative positional relationship with the centers 50sc and 60sc of the substrates 50 and 60 as the reference positions in a plan view in the Z direction. The side closer to the center is the inside, and the side further from the center is the outside. FIG. 85 shows the center 50sc of the substrate 50 as an example. Although FIG. 84 is a cross-sectional view, the centers 50sc and 60sc are shown for the sake of convenience.

In the substrates 50, 60 of this embodiment, the insulating base material 51, 61 contains resin. The surface metal bodies 52, 62 are disposed on the surfaces 51a, 61a of the insulating base material 51, 61. The surface metal bodies 52, 62 are patterned as described in the previous embodiment. As a result, the insulating base material 51, 61 has exposed portions 510, 610 exposed from the surface metal bodies 52, 62. The exposed portion 510 of the insulating base material 51, which is the first exposed portion, and the exposed portion 610 of the insulating base material 61, which is the second exposed portion, at least partially overlap each other in a planar view in the Z direction. The exposed portions 510, 610 overlap. In other words, at least a portion of the exposed portion 510 faces the exposed portion 610 in the Z direction.

The back surface metal bodies 53, 63 are arranged on the back surfaces 51b, 61b of the insulating substrate 51, 61. The back surface metal bodies 53, 63 are exposed from the sealing body 30. The surfaces of the back surface metal bodies 53, 63 opposite the surfaces 53a, 63a facing the insulating substrate 51 are the exposed surfaces 53b, 63b. The exposed surface 53b is exposed and approximately flush with one surface 30a of the sealing body 30. The exposed surface 63b is exposed and approximately flush with the back surface 30b of the sealing body 30. The exposed surfaces 53b, 63b form the back surfaces 50b, 60b of the substrates 50, 60. The sealing body 30 has a side surface 30e as a second surface that is continuous with the first surface, the one surface 30a, and the back surface 30b. The side surface 30e includes side surfaces 30c, 30d in the Y direction, as well as a side surface in the X direction. The side surface 30e includes all side surfaces. The side surface 30e, which is the second surface, is a tapered surface that is inclined with respect to the Z direction for removal from the mold during molding. The side surface 30e has a draft angle. In the previous embodiment, the draft angle is omitted from the illustration for convenience. The side surface 30e has a bent portion approximately in the center in the Z direction, and the closer to the one surface 30a and the back surface 30b from the bent portion, the closer to the semiconductor element 40 in a plan view in the Z direction. In other words, in a plan view, the bent portion is on the outside, and the one surface 30a and the back surface 30b are on the inside. Hereinafter, the one surface 30a and the back surface 30b of the encapsulant 30 may be referred to as the first surfaces 30a and 30b.

As shown in Figures 84 and 86, the substrates 50, 60 have laminates 500, 600. The laminate 500 is a two-layer laminate made of an insulating substrate 51 and a back surface metal body 53. Similarly, the laminate 600 is a two-layer laminate made of an insulating substrate 61 and a back surface metal body 63. In the laminates 500, 600, the side surfaces connecting the surfaces 51a, 61a of the insulating substrates 51, 61 and the exposed surfaces 53b, 63b of the back surface metal bodies 53, 63 form a so-called V-cut shape. The side surfaces of the laminates 500, 600 have a shape in which the central portion is convex outward relative to the surfaces 51a, 61a at the upper end and the exposed surfaces 53b, 63b at the lower end.

The side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601, second inclined portions 502 and 602, and intermediate portions 503 and 603. First, we will explain the laminate 500.

The first inclined portion 501 is a portion within a predetermined range from the surface 51a. In a plan view, the first inclined portion 501 has a slope such that the distance from the center 50sc is closest at the upper end on the surface 51a side and farther at the lower end than the upper end. In other words, the lower end of the first inclined portion 501 is located outside the upper end. As shown in Figure 85, the first inclined portion 501 is provided on the edge of the substrate 50. The first inclined portion 501 is annular, surrounding the surface metal body 52.

In this embodiment, the first inclined portion 501 has a slope that increases in distance from the center 50sc in a plan view as it moves away from the surface 51a in the Z direction. In other words, the area of the laminate 500 perpendicular to the Z direction at the surface 51a is smallest at the upper portion including the first inclined portion 501, and the area increases as it moves away from the surface 51a. The slope of the first inclined portion 501 can tolerate manufacturing variations. The first inclined portion 501 has the above-mentioned slope from a macroscopic perspective. The first inclined portion 501 is a tapered surface.

The second inclined portion 502 is a portion within a predetermined range from the exposed surface 53b. In a plan view, the second inclined portion 502 is closest to the center 50sc at its lower end on the exposed surface 53b side, and has an inclination such that its upper end is farther from the center 50sc than the lower end. In other words, the upper end of the second inclined portion 502 is located outside the lower end. Like the first inclined portion 501, the second inclined portion 502 is provided on the edge of the substrate 50. The second inclined portion 502 is annular, surrounding the back surface metal body 53.

In this embodiment, the second inclined portion 502 has a slope that increases in distance from the center 50sc in a plan view as it moves away from the exposed surface 53b in the Z direction. In other words, the area of the laminate 500 is smallest at the exposed surface 53b in the lower part including the second inclined portion 502, and increases as it moves away from the exposed surface 53b. The slope of the second inclined portion 502 can tolerate manufacturing variations. The second inclined portion 502 has the above-mentioned slope from a macroscopic perspective. The second inclined portion 502 is a tapered surface. If the first inclined portion 501 is a forward taper, the second inclined portion 502 is a reverse taper.

The intermediate portion 503 is connected to the first inclined portion 501 and the second inclined portion 502. The intermediate portion 503 connects the first inclined portion 501 and the second inclined portion 502 and has a predetermined length in the Z direction. The intermediate portion 503 is the apex of the side of the laminate 500. The side of the laminate 500 is farthest from the center 50sc at the intermediate portion 503. The intermediate portion 503 is the outermost portion of the laminate 500 in a planar view. The area of the laminate 500 perpendicular to the Z direction is largest at the intermediate portion 503. The area of the laminate 500 is approximately constant at the intermediate portion 503. The distance between the first inclined portion 501 and the center 50sc in a planar view decreases the further away from the intermediate portion 503. The distance between the second inclined portion 502 and the center 50sc in a planar view decreases the further away from the intermediate portion 503.

The laminate 600 has the same configuration as the laminate 500. The first inclined portion 601 is a portion within a predetermined range from the surface 61a. In a plan view, the first inclined portion 601 is closest to the center 60sc at its upper end on the surface 61a side, and is inclined so that its lower end is farther from the center 60sc than the upper end. In other words, the lower end of the first inclined portion 601 is located outside the upper end. The first inclined portion 601 is provided on the edge of the substrate 60. The first inclined portion 601 is annular, surrounding the surface metal body 62.

In this embodiment, the first inclined portion 601 has a slope that increases in distance from the center 60sc in a plan view as it moves away from the surface 61a in the Z direction. In other words, the laminate 600 has the smallest area perpendicular to the Z direction at the surface 61a in the upper portion including the first inclined portion 601, and the area increases with increasing distance from the surface 61a. The slope of the first inclined portion 601 can tolerate manufacturing variations. The first inclined portion 601 has the above-mentioned slope from a macroscopic perspective. The first inclined portion 601 is a tapered surface.

The second inclined portion 602 is a portion within a predetermined range from the exposed surface 63b. In a plan view, the second inclined portion 602 has a slope such that the distance from the center 60sc is closest at the lower end on the exposed surface 63b side and farther at the upper end than at the lower end. In other words, the upper end of the second inclined portion 602 is located outside the lower end. Like the first inclined portion 501, the second inclined portion 602 is provided on the edge of the substrate 60. The second inclined portion 602 is annular, surrounding the back surface metal body 63.

In this embodiment, the second inclined portion 602 has a slope that increases in distance from the center 60sc in a plan view as it moves away from the exposed surface 63b in the Z direction. In other words, in the lower portion of the laminate 600 including the second inclined portion 602, the area is smallest at the exposed surface 63b, and the area increases as it moves away from the exposed surface 63b. The slope of the second inclined portion 602 can tolerate manufacturing variations. The second inclined portion 602 has the above-mentioned slope from a macroscopic perspective. The second inclined portion 602 is a tapered surface. If the first inclined portion 601 is a forward taper, the second inclined portion 602 is a reverse taper.

The intermediate portion 603 is connected to the first inclined portion 601 and the second inclined portion 602. The intermediate portion 603 connects the first inclined portion 601 and the second inclined portion 602, and has a predetermined length in the Z direction. The intermediate portion 603 is the apex of the side of the laminate 600. The side of the laminate 600 is farthest from the center 60sc at the intermediate portion 603. The intermediate portion 603 is the outermost portion of the laminate 600 in a planar view. The area of the laminate 600 is largest at the intermediate portion 603. The area of the laminate 600 is approximately constant at the intermediate portion 603. The distance between the first inclined portion 601 and the center 60sc in a planar view decreases the further away from the intermediate portion 603. The distance between the second inclined portion 602 and the center 60sc in a planar view decreases the further away from the intermediate portion 603.

<Dimensions and angles>
Next, the dimensions and angles of the stacked bodies 500 and 600 will be described with reference to Fig. 87. Fig. 87 is a diagram corresponding to Fig. 86, and shows the dimensions and angles. The following description will be given taking the stacked body 500 as an example.

Length L11 shown in FIG. 87 is the length of the first inclined portion 501 in a plan view, i.e., the width of the annular first inclined portion 501. Length L12 is the length of the second inclined portion 502 in a plan view, i.e., the width of the annular second inclined portion 502. Length L21 is the length of the first inclined portion 501 in the Z direction, i.e., the height of the first inclined portion 501. Length L22 is the length of the second inclined portion 502 in the Z direction, i.e., the height of the second inclined portion 502. Length L23 is the length of the intermediate portion 503 in the Z direction, i.e., the height of the intermediate portion 503. Length L24 is the length of the insulating substrate 51 in the Z direction, i.e., the thickness of the insulating substrate 51. Length L25 is the length of the back surface metal body 53 in the Z direction, i.e., the thickness of the back surface metal body 53.

Angle R1 is the inclination angle of the back surface metal body 53 with respect to the Z direction, which is the plate thickness direction of the semiconductor element 40, at the first inclined portion 501. Angle R2 is the inclination angle of the back surface metal body 53 with respect to the Z direction at the second inclined portion 502. Angle R3 is the inclination angle of the insulating substrate 51 with respect to the Z direction at the first inclined portion 501. Angle R4 is the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53. Angle R5 is the inclination angle of the side surface 30e with respect to one surface 30a of the encapsulant 30.

As shown in Figure 87, in this embodiment, the length of the second inclined portion 502 is shorter than the length of the first inclined portion 501. In other words, the relationship L11 > L12 is satisfied. The angle R1 satisfies the relationship 0° < R1 ≦ 45°, and the angle R2 satisfies the relationship 0° < R2 < 45°. The closer the angle R1 is to 45°, the more effectively the heat generated by the semiconductor element 40 can be diffused. The closer the angle R2 is to 45°, the more effectively the thermal resistance can be reduced, as described below.

Furthermore, the first inclined portion 501 is provided from the insulating substrate 51 to the back surface metal body 53, and the second inclined portion 502 is provided on the back surface metal body 53. In other words, the relationships L21 > L24 and L22 < L25 are satisfied. In the configuration including the intermediate portion 503, the intermediate portion 503 is provided on the back surface metal body 53. In other words, the relationship L24 < (L24 + L25 - L23)/2 is satisfied.

Furthermore, in a configuration in which the first inclined portion 501 is provided from the insulating substrate 51 to the back surface metal body 53, the inclination angle of the back surface metal body 53 and the inclination angle of the insulating substrate 51 are approximately equal. In other words, the relationship R1 = R3 is satisfied.

Furthermore, the inclination angle of the second inclined portion 502 relative to the exposed surface 53b of the back surface metal body 53 is smaller than the inclination angle of the side surface 30e (second surface) relative to the surface 30a (first surface) of the sealing body 30. In other words, the relationship R4 < R5 is satisfied. Although explanation will be omitted, the stack 600 has a similar configuration to the stack 500.

<Method of manufacturing laminate>
Next, an example of a method for manufacturing the above-described laminate 500 will be described. First, a motherboard is formed with a two-layer structure of an insulating base material 51 containing resin and a back surface metal body 53. Next, a blade is used to simultaneously cut (V-cut) both the front surface 51a and the exposed surface 53b of the insulating base material 51. This cutting forms a first inclined portion 501 and a second inclined portion 502 without completely separating the motherboard. In the motherboard, adjacent laminates 500 are connected at a middle portion 503. Then, by separating (cutting off) the adjacent laminates 500 at the middle portion 503, a laminate 500 having a V-cut-shaped side surface can be obtained.

Figure 88 is a side view of the laminate 500 obtained by the manufacturing method described above. The first inclined portion 501 has a cutting mark 501a running along the circumferential direction due to cutting (machining) using a blade. Similarly, the second inclined portion 502 has a cutting mark 502a running along the circumferential direction. Adjacent laminates 500 are separated at the intermediate portion 503, and the intermediate portion 503 has an uneven portion 503a. Although further explanation is omitted, the laminate 600 is also formed using a method similar to that of the laminate 500.

<Summary of the ninth embodiment>
In this embodiment, the side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601 and second inclined portions 502 and 602. That is, the side surfaces are curved (generally V-shaped). As a result, even if delamination that occurs in the sealing body 30 starting from the interface with the exposed surface 53b and 63b progresses along the second inclined portions 502 and 602, the curved shape can suppress the progression to the first inclined portions 501 and 601. Therefore, it is possible to suppress the progression of delamination to the surface metal bodies 52 and 62, the semiconductor element 40, and the joints between the surface metal bodies 52 and 62 and the semiconductor element 40. In other words, it is possible to suppress the concentration of thermal stress on the surface metal bodies 52 and 62, the semiconductor element 40, and the like, which would otherwise cause a decrease in connection reliability. This ensures reliability.

The presence of the second inclined portions 502, 602 also helps prevent the rear surface metal bodies 53, 63 from falling off (falling off) from the sealing body 30 when the above-mentioned peeling occurs.

Heat ideally spreads at a 45-degree angle. In this embodiment, the stacked bodies 500, 600 have first inclined portions 501, 601 on the semiconductor element 40 side in the Z direction. This allows heat generated by the semiconductor element 40 to diffuse above the bent portion, i.e., in the portions corresponding to the first inclined portions 501, 601. On the other hand, by having the second inclined portions 502, 602, the heat conduction path in the portions corresponding to the second inclined portions 502, 602 is narrower than the heat conduction path in the portions corresponding to the first inclined portions 501, 601. A narrower heat conduction path increases thermal resistance. In this embodiment, the length L12 of the second inclined portions 502, 602 is made shorter than the length L11 of the first inclined portions 501, 601 (L11 > L12). This allows the Z-direction length L22 of the second inclined portions 502, 602 to be shorter than in a configuration where L11≦L12, thereby reducing the thermal resistance below the bent portion. In other words, heat diffused in the upper portions of the stacks 500, 600 can be efficiently dissipated from the exposed surfaces 53b, 63b. As a result, the semiconductor device 20 of this embodiment can ensure reliability while improving heat dissipation.

The first inclined portions 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portions 502, 602 may be provided on the back surface metal body 53, 63. The first inclined portions 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portions 502, 602 may be provided across the insulating substrate 51, 61 and the back surface metal body 53, 63. In this embodiment, the first inclined portions 501, 601 are provided across the insulating substrate 51, 61 and the back surface metal body 53, 63, and the second inclined portions 502, 602 are provided on the back surface metal body 53, 63. In other words, a bent portion exists within the back surface metal body 53, 63. Therefore, even if delamination that occurs in the sealing body 30 originating from the interface with the exposed surface 53b, 63b progresses along the second inclined portions 502, 602, it is possible to prevent the delamination from progressing to the interface with the insulating substrate 51, 61. This prevents thermal stress from concentrating on the insulating substrates 51 and 61, which would otherwise reduce insulation reliability. In other words, reliability can be further improved.

The first inclined portion 501, 601 and the second inclined portion 502, 602 may be connected. In this embodiment, an intermediate portion 503, 603 is provided between the first inclined portion 501, 601 and the second inclined portion 502, 602. In this configuration, the intermediate portion 503, 603 forms a bent portion. By providing the intermediate portion 503, 603, as described above, contact between the blades can be avoided even when cutting (milling) simultaneously from both the front surface 51a, 61a of the insulating substrate 51, 61 and the exposed surface 53b, 63b of the back surface metal body 53, 63. Furthermore, because the intermediate portion 503, 603 is provided on the back surface metal body 53, 63, it is possible to prevent peeling from progressing to the interface with the insulating substrate 51, 61, as described above.

In a configuration in which the first inclined portions 501, 601 extend from the insulating substrate 51, 61 to the back metal body 53, 63, the inclination angle R1 of the back metal body 53, 63 and the inclination angle R3 of the insulating substrate 51, 61 may be different. For example, if R1 < R3, thermal stress may concentrate at the end of the insulating substrate 51, 61, which contains resin, resulting in a risk of reduced insulation performance. If R1 > R3, thermal stress may concentrate at the interface between the insulating substrate 51, 61 and the back metal body 53, 63, resulting in interfacial delamination. In this embodiment, the inclination angles R1 and R3 are set to approximately equal angles (R1 = R3). In other words, the inclined surfaces of the insulating substrate 51, 61 and the back metal body 53, 63 are connected in a substantially flush manner at the first inclined portions 501, 601. The inclined surfaces of the insulating substrates 51, 61 and the inclined surfaces of the back surface metal bodies 53, 63 are continuous to form a single flat surface. This prevents thermal stress from concentrating at the triple points of the sealing body 30, insulating substrates 51, 61, and back surface metal bodies 53, 63.

The inclination angle R4 of the second inclined portions 502, 602 relative to the exposed surfaces 53b, 63b may be equal to or greater than the inclination angle R5 of the side surface 30e (second surface) relative to the first surfaces 30a, 30b of the sealing body 30. In this embodiment, the inclination angle R4 is smaller than the inclination angle R5 (R4<R5). As described in the previous embodiment (see, for example, FIG. 72 ), warping occurs in the semiconductor device 20 when the semiconductor element 40 generates heat. As described above, if a configuration that results in a warped shape with high heat dissipation properties is adopted, the warp that is convex in the Z direction makes it more likely that peeling will occur at the interface between the back surface metal bodies 53, 63 and the sealing body 30. By achieving a configuration that satisfies the relationship R4<R5, it is possible to prevent the back surface metal bodies 53, 63 from falling off the sealing body 30, even if peeling occurs.

In this embodiment, the exposed portion 510 of the insulating base material 51, which is the first exposed portion, and the exposed portion 610 of the insulating base material 61, which is the second exposed portion, overlap each other in a plan view in the Z direction. This prevents imbalance in the arrangement of the front surface metal body 52 of the substrate 50, which is the first substrate, and the front surface metal body 62 of the substrate 60, which is the second substrate, and ultimately prevents imbalance in warpage of the semiconductor device 20. This prevents interfacial peeling between the back surface metal bodies 53, 63 and the sealing body 30 from occurring on the side with greater deformation due to uneven warpage.

In this embodiment, the first inclined portion 501 and the second inclined portion 502 have cutting marks 501a, 502a along the circumferential direction. The cutting marks 501a, 502a create an anchor effect, increasing adhesion with the sealing body 30. This makes it possible to prevent the sealing body 30 from peeling off from the laminate 500, 600. Note that cutting marks along the circumferential direction may be provided on only one of the first inclined portion 501 and the second inclined portion 502. In this embodiment, the middle portion 503 also has an uneven portion 503a, so peeling can be expected to be prevented by the anchor effect.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. It is also possible to apply the present invention to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, the above-described structure (V-cut shape) may be applied to only one of the substrates 50, 60.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, and eighth embodiments, as well as the modified examples.

Tenth Embodiment
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve connection reliability, the sintered members, which are joining materials, may be arranged in a predetermined manner, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 89. Fig. 89 is a cross-sectional view corresponding to Fig. 5. For convenience, the external connection terminals 90 are not shown in Fig. 89.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 89, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60, which are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50, which is a first wiring member, is connected to the drain electrode 40D, which is a first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60, which is a second wiring member, is connected to the source electrode 40S, which is a second main electrode of the semiconductor element 40, via a conductive spacer 70, which is a second wiring member. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The source electrode 40S and the conductive spacer 70 are bonded together by a sintered member 101A, which is a bonding material 101.

<Semiconductor element>
Next, the semiconductor element 40 will be described with reference to FIGS. 90 and 91. FIG. 90 is a plan view showing the semiconductor element 40 (40H). FIG. 91 is an enlarged view of region XCI in FIG. 89. FIG. 91 is a cross-sectional view corresponding to line XCI-XCI in FIG. 90. Although FIG. 91 illustrates the semiconductor element 40H, the semiconductor element 40L also has a similar configuration, and therefore will be described below as the semiconductor element 40.

As described above, the semiconductor element 40 has a semiconductor substrate 41 on which a switching element is formed. The semiconductor substrate 41 has a generally rectangular shape in plan view. The drain electrode is provided on one surface of the semiconductor substrate 41, and the source electrode 40S and pad 40P are provided on the back surface of the semiconductor substrate 41. The source electrode 40S has a multi-layer structure. The source electrode 40S has a base electrode 42 and a connection electrode 43. The pad 40P has a similar configuration to the source electrode 40S.

The semiconductor element 40 further has a protective film 44. The protective film 44 is an insulating film provided on the back surface of the semiconductor substrate 41 so as to cover the peripheral edge of the source electrode 40S. Materials that can be used for the insulating film include polyimide and silicon nitride. The protective film 44 has an opening 440 that defines the connection area of the source electrode 40S. The opening 440 exposes the source electrode 40S so that it can be bonded. The protective film 44 has an opening 441 that defines the connection area of the pad 40P. Both openings 440 and 441 are through-holes that penetrate the protective film 44 in the Z direction. The portion of the source electrode 40S (connection electrode 43) exposed through the opening 440 of the protective film 44 forms a bond with the sintered member 101A.

In this embodiment, the protective film 44 is made of polyimide. The protective film 44 covers the peripheral edge 420 (described below) of the base electrode 42. The protective film 44 is not provided, for example, in a scribe region within a predetermined range from the outer peripheral edge of the semiconductor substrate 41. The opening shape of the opening 440, i.e., the inner peripheral surface 442 of the protective film 44 that defines the opening 440, is generally rectangular in plan view. The inner peripheral surface 442 is sometimes referred to as the inner peripheral edge or opening edge.

The base electrode 42 is a metal layer formed adjacent to the semiconductor substrate 41 in the multi-layered source electrode 40S. The base electrode 42 is sometimes referred to as a lower electrode, lower layer electrode, wiring electrode, base layer, first metal layer, etc. The base electrode 42 is connected to the back surface of the semiconductor substrate 41. The base electrode 42 is formed, for example, using a material whose main component is Al (aluminum). In this embodiment, the material is an AlSi-based alloy such as AlSi or AlSiCu.

In plan view, the base electrode 42 encompasses the element region (active region) (not shown) of the semiconductor substrate 41 and extends onto the outer peripheral region surrounding the element region. The peripheral portion 420 of the base electrode 42 has a generally rectangular ring shape in plan view. The peripheral portion 420 is covered with a protective film 44.

The connection electrode 43 is layered on the base electrode 42. The connection electrode 43 is also referred to as the top electrode, upper electrode, upper layer electrode, top layer, or second metal layer. The connection electrode 43 contains at least a precious metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101A. The connection electrode 43 may contain a base metal in addition to the precious metal.

The connection electrode 43 in this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 42. The connection electrode 43 contains Ni and a precious metal, such as Au or Ag. The connection electrode 43 is formed in multiple layers, for example, by plating. At least a portion of the precious metal of the connection electrode 43 diffuses into the sintered component 101A during joining.

The connection electrode 43 is laminated on the base electrode 42 in the opening 440 of the protective film 44. The outer peripheral end of the connection electrode 43 is in contact with the inner peripheral surface 442 of the protective film 44 along its entire periphery.

<Joining structure>
Next, the joining structure of the semiconductor element 40 will be described with reference to Figures 90 to 92. In Figure 90, the outer peripheral edge of the sintered member 101A is indicated by a dashed line, and the outer peripheral edge of the conductive spacer 70 is indicated by a two-dot chain line. Figure 92 is a cross-sectional view showing the arrangement of the sintered member 101A. Figure 92 corresponds to Figure 91. In the following, the terms "inside" and "outside" refer to the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side farther from the center is the outside.

In this embodiment, the substrate 60 and the conductive spacer 70 form a wiring member (second wiring member) electrically connected to the source electrode 40S. As shown in Figures 90 and 91, the sintered member 101A is interposed between the source electrode 40S of the semiconductor element 40 and the conductive spacer 70. The sintered member 101A joins the source electrode 40S and the conductive spacer 70.

The sintered component 101A is made of Ag or Cu. It is a sintered body made of Ag particles or Cu particles. The sintered component 101A can be bonded at a lower temperature than solder. As shown in FIG. 92, the sintered component 101A is positioned with a predetermined distance L30 between it and the inner peripheral surface 442 of the protective film 44. As shown in FIGS. 90 to 92, the sintered component 101A is positioned further inward than the inner peripheral surface 442. The sintered component 101A has, for example, a generally rectangular shape in plan view. The outer peripheral edge of the sintered component 101A is not in contact with the protective film 44 along its entire circumference. In other words, the inner peripheral surface 442 of the protective film 44 encompasses the sintered component 101A in a plan view.

The conductive spacer 70 has a metal film (not shown) on the bonding surface with the sintered member 101A. Like the connection electrode 43, the metal film contains at least a precious metal. In this embodiment, the metal film is a plated film containing Ni and a precious metal, such as Au or Ag.

As shown in Figures 90 to 92, the conductive spacer 70 is positioned inside the inner peripheral surface 442. The conductive spacer 70 has, for example, a generally rectangular shape in plan view. The outer peripheral edge of the conductive spacer 70 is positioned outside the outer peripheral edge of the sintered component 101A in plan view, or so that it is roughly aligned with the outer peripheral edge of the sintered component 101A. In other words, the conductive spacer 70 is positioned so that it contains the sintered component 101A in plan view, or so that it is roughly aligned with the sintered component 101A. In this embodiment, the conductive spacer 70 contains the sintered component 101A.

<Joining method>
Next, a method for forming the above-mentioned bonded structure, that is, a bonding method, will be described with reference to Fig. 93. Fig. 93 is a cross-sectional view showing the bonding method. Fig. 93 corresponds to Fig. 91.

In this embodiment, a sintered sheet 105 is used to form the sintered member 101A. The sintered sheet 105 is sometimes referred to as a sintered film. The sintered sheet 105 contains Ag or Cu. As shown in FIG. 93, the sintered sheet 105 is placed on the source electrode 40S (connection electrode 43) of the semiconductor element 40. The sintered sheet 105 has a predetermined size that does not contact the protective film 44 in a plan view.

Next, a conductive spacer 70 is placed on the sintered sheet 105. Then, while heating, pressure is applied from the conductive spacer 70 side using a pressure device (not shown). As a result, the sintered sheet 105 is pressed and spread between the opposing surfaces of the connection electrode 43 and the conductive spacer 70, reducing its thickness, and is sintered into the sintered member 101A. The size of the sintered sheet 105 is determined so that the sintered member 101A has the predetermined positional relationship described above with respect to the inner surface 442 of the protective film 44 and the conductive spacer 70.

<Simulation results>
Fig. 94 shows the results of a thermal stress simulation. In this simulation, the strain amplitude generated in the base electrode 42 was measured in a power cycle test in which room temperature and 150°C were alternately repeated. Fig. 94 shows the relationship between the distance L30 and the strain amplitude. In Fig. 94, when the distance L30 is 0 (zero), it corresponds to the position that coincides with the inner circumferential surface 442 of the protective film 44 in a plan view. Negative values for the distance L30 indicate the distance inward from the inner circumferential surface 442, and positive values indicate the distance outward.

As shown in Figure 94, it has been found that when the distance L30 is 5 μm or greater, the distortion amplitude generated in the base electrode 42 becomes nearly 0 (zero). Based on this finding, in this embodiment, the predetermined distance L30 is set to 5 μm.

<Summary of the Tenth Embodiment>
FIG. 95 shows a connection structure using solder 101B as the bonding material 101. FIG. 95 corresponds to FIG. 93. In the case of solder 101B, the bonding is performed by reflowing the solder 101B. During bonding, the molten solder 101B wets and spreads over the surface of the connection electrode 43. As a result, a triple junction is formed between the sealing body 30, the source electrode 40S (connection electrode 43), and the solder 101B (bonding material 101), as shown by the dashed-dotted line in FIG. 95. Thermal stress due to the difference in linear expansion coefficients is concentrated at the triple junction. The thermal stress is concentrated in the base electrode 42, directly below the outer periphery of the connection electrode 43. This may result in cracks in the base electrode 42 and ultimately damage to the semiconductor substrate 41.

In this embodiment, a sintered member 101A is used instead of solder 101B. The sintered member 101A is formed by heating at a temperature lower than the melting point. Unlike solder 101B, the sintered member 101A does not become molten during bonding. Compared to solder 101B, the sintered member 101A has lower wettability with respect to the connection electrode 43 and the conductive spacer 70. Therefore, unlike solder 101B, the sintered member 101A does not wet and spread over the surface of the connection electrode 43 or the surface of the conductive spacer 70 during bonding.

The sintered member 101A can be easily held in place, and can be positioned with a predetermined distance L30 between it and the inner surface 442 of the protective film 44. This prevents a triple point between the sealing body 30, the source electrode 40S (connection electrode 43), and the sintered member 101A (joint material 101). This prevents the concentration of thermal stress and provides a semiconductor device 20 with high connection reliability. Furthermore, the sintered member 101A has a higher thermal conductivity than the solder 101B. This also improves heat dissipation.

The distance L30 is not particularly limited. The sintered member 101A only needs to be spaced apart from the inner peripheral surface 442. In this embodiment, the distance L30 between the sintered member 101A and the inner peripheral surface 442 of the protective film 44 is set to 5 μm or more. This effectively reduces the distortion amplitude of the base electrode 42 due to thermal stress. In other words, connection reliability can be further improved.

In plan view, the positional relationship between the conductive spacer 70 and the sintered member 101A is not particularly limited. For example, in plan view, the sintered member 101A may protrude from the conductive spacer 70. As described above, the sintered member 101A is formed by sintering Ag particles or Cu particles through heating and pressure. Because the portion protruding from the conductive spacer 70 is not pressurized, it remains unsintered and may fall off as conductive foreign matter. This could result in a short circuit or other problem.

In this embodiment, in a plan view, the inner surface 442 of the protective film 44 contains the conductive spacer 70, which is flush with or contains the sintered component 101A. This allows pressure to be applied to the entire area of the sintered component 101A (sintered sheet 105) before sintering via the conductive spacer 70. This prevents contact between the sintered component 101A and the protective film 44 and suppresses the occurrence of unsintered portions.

<Modification>
While the sintered sheet 105 is used to form the sintered component 101A, this is not limiting. For example, a sintering paste containing Ag particles or Cu particles dispersed in a solvent may be used. The sintered sheet 105 is more likely to be held in place than the sintering paste.

In the example shown, the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, but this is not limiting. Instead of the conductive spacer 70, a convex portion may be provided on the surface metal body 62. In other words, the second wiring member may be configured to include only the substrate 60, without the conductive spacer 70. In this case, the sintered member 101A is interposed between the tip surface of the convex portion of the surface metal body 62 and the source electrode 40S (connection electrode 43).

Although a substrate 50 has been shown as an example of the first wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 50. Although a substrate 60 has been shown as an example of the second wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and conductive spacers 70, or a metal plate may have a protrusion instead of the conductive spacers 70.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth embodiments, as well as the modified examples.

Eleventh Embodiment
This embodiment is a modification of the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation, a sintered member may be used at the joint between the main electrode and the wiring member, as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 96. Fig. 96 is a cross-sectional view corresponding to Fig. 5. For convenience, the external connection terminals 90 are not shown in Fig. 96.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 96, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60, which are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, via a conductive spacer 70. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The drain electrode 40D and the surface metal body 52 of the substrate 50 are bonded together by a sintered member 100A, which is a bonding material 100.

<Arrangement of sintered member and uneven oxide film>
Next, the arrangement of the sintered member 100A and the uneven oxide film 520 relative to the semiconductor element 40 will be described with reference to Figures 97 to 99. Figure 97 is an enlarged view of region XCVII in Figure 96. Figure 98 is a plan view showing the positional relationship between the semiconductor element 40, the sintered member 100A, and the uneven oxide film 520. Figure 99 is an enlarged view of region XCVIX in Figure 97.

As shown in Figures 97 and 98, the top surface 52a of the surface metal body 52 has a mounting portion 529a, an outer peripheral portion 529b, and an intermediate portion 529c. The uneven oxide film 520 is not provided on the mounting portion 529a, but is provided on the outer peripheral portion 529b and the intermediate portion 529c.

The mounting portion 529a includes a portion that overlaps with the semiconductor element 40 (drain electrode 40D) in a planar view in the Z direction, and is the portion to which the drain electrode 40D is joined via the sintered member 100A. The outer peripheral portion 529b includes a portion that is outer than the outer peripheral edge 402 of the semiconductor element 40 in a planar view, and is the portion that surrounds the semiconductor element 40. The intermediate portion 529c is the portion between the mounting portion 529a and the outer peripheral portion 529b, and surrounds the mounting portion 529a. In this embodiment, the mounting portion 529a approximately coincides with the semiconductor element 40 (drain electrode 40D) in a planar view. The intermediate portion 529c has a generally rectangular ring shape in plan, and the inner peripheral edge of the intermediate portion 529c approximately coincides with the outer peripheral edge 402 of the semiconductor element 40. The entire intermediate portion 529c is located outside the semiconductor element 40 in a planar view.

As shown in Figures 97 to 99, the surface metal body 52 of the substrate 50 has an uneven oxide film 520, similar to the configuration described in the previous embodiment (see Figures 67 and 74). As shown in Figure 99, the surface metal body 52 has a base material 521, a metal film 522 provided on the surface of the base material 521, and an uneven oxide film 520.

The metal film 522 of this embodiment has a base film primarily composed of Ni and an upper film primarily composed of a precious metal, such as Au or Ag, that can be bonded to the sintered component 100A. Specifically, a P-containing Ni-plated film and an Au-plated film are used as the base film. Multiple recesses 523 are formed in the outer peripheral portion 529b of the upper surface 52a of the metal film 522. No recesses 523 are formed in the mounting portion 529a or the intermediate portion 529c. In the portions where no recesses 523 are formed, the film thickness of the metal film 522 is, for example, approximately 10 μm. In other words, the film thickness before laser light irradiation is approximately 10 μm. The recesses 523 are formed by irradiation with pulsed laser light. One recess 523 is formed for each pulse. In the outer peripheral portion 529b, the surface of the metal film 522 is scale-like due to the multiple recesses 523. The outer periphery 529b is the area irradiated with laser light, while the mounting portion 529a and the middle portion 529c are non-irradiated areas.

The uneven oxide film 520 is formed on the metal film 522. The uneven oxide film 520 is not formed on the mounting portion 529a, but is formed on the outer peripheral portion 529b and intermediate portion 529c, which are the portions surrounding the mounting portion 529a. As described in the previous embodiment, the uneven oxide film 520 is formed by irradiating the metal film 522 with laser light. The uneven oxide film 520 is a laser-irradiated film formed by irradiating with laser light. The main component of the uneven oxide film 520 is an oxide of the main component metal of the metal film 522.

In the outer peripheral portion 529b, i.e., the area irradiated with the laser light, the average film thickness of the uneven oxide film 520 is 10 nm to several hundred nm. The uneven oxide film 520 is formed to resemble the unevenness of the surface of the metal film 522, which has recesses 523. Furthermore, the surface of the uneven oxide film 520 has recesses and protrusions formed at a pitch finer than the width of the recesses 523. In other words, extremely fine recesses and protrusions (roughened portions) are formed. In other words, multiple protrusions 520a (columnar bodies) are formed at a fine pitch. For example, the average width of the protrusions 520a is 1 nm to 300 nm, and the average spacing between the protrusions 520a is 1 nm to 300 nm. Furthermore, the average height of the protrusions 520a is 10 nm to several hundred nm.

The uneven oxide film 520 is formed by irradiating the metal film 522 with laser light and melting and depositing the surface layer of the metal film 522. Therefore, it is formed not only in the outer peripheral portion 529b, which is the area irradiated with the laser light, but also in the periphery (vicinity) of the outer peripheral portion 529b. In this embodiment, of the areas not irradiated with laser light, the uneven oxide film 520 is formed over the entire intermediate portion 529c, and not over the mounting portion 529a. The width of the intermediate portion 529c, which has the uneven oxide film 520 over its entire area, is, for example, 0.2 mm to 0.3 mm.

The average thickness of the uneven oxide film 520 in the intermediate portion 529c is thinner than the average thickness of the uneven oxide film 520 in the peripheral portion 529b, because the laser light is not directly irradiated thereto, and is thicker than the native oxide film. Specifically, it is 0.1 nm to 10 nm. Furthermore, the height of the convex portions 520a on the surface of the uneven oxide film 520 is also lower than that of the peripheral portion 529b. Specifically, it is 0.1 nm to 10 nm. The average width and average spacing of the convex portions 520a are similar to those of the peripheral portion 529b.

As such, the uneven oxide film 520 has a thick film portion 520X and a thin film portion 520Y. The thick film portion 520X is the portion of the uneven oxide film 520 that is provided in the area irradiated with laser light, i.e., the outer peripheral portion 529b. The thin film portion 520Y is the portion of the uneven oxide film 520 that is provided in the area not irradiated with laser light, i.e., the intermediate portion 529c. The thin film portion 520Y has a thinner film thickness and a lower height of the convex portion 520a than the thick film portion 520X. The thick film portion 520X is provided in the outer peripheral portion 529b. The thin film portion 520Y is provided in the intermediate portion 529c.

The thick film portion 520X has a higher protrusion 520a than the thin film portion 520Y, so the plug 30 becomes entangled, creating an anchor effect. This also increases the contact area with the plug 30, allowing the plug 30 to adhere tightly to the outer periphery 529b. The thick film portion 520X is sometimes referred to as a roughened portion or an adhesive portion.

Sintered member 100A is made of Ag or Cu, similar to sintered member 101A described in the previous embodiment. Sintered member 100A is a sintered body made of Ag particles or Cu particles. Sintered member 100A can be bonded at lower temperatures than solder. Sintered member 100A is formed by heating and pressurizing a sintered sheet or sintering paste. In a plan view, sintered member 100A extends beyond the outer peripheral edge 402 of semiconductor element 40. Sintered member 100A is positioned so as to overlap mounting portion 529a and intermediate portion 529c in a plan view. In this embodiment, the outer peripheral edge of sintered member 100A substantially coincides with the outer peripheral edge of intermediate portion 529c. In a plan view, sintered member 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c.

<Summary of Eleventh Embodiment>
As described above, the intermediate portion 529c has the thin film portion 520Y of the uneven oxide film 520. Due to the presence of the thin film portion 520Y, the intermediate portion 529c has lower wettability with solder than the mounting portion 529a. As a result, the solder is less likely to wet and spread from the mounting portion 529a toward the intermediate portion 529c.

In this embodiment, a sintered member 100A is used instead of solder. The sintered member 100A is formed by heating at a temperature lower than the melting point. Unlike solder, the sintered member 100A does not melt during joining. Unlike solder, the sintered member 100A does not wet and spread over the surface of the surface metal body 52 during joining.

During pressure sintering, the sintered member 100A is spread between the opposing surfaces of the drain electrode 40D and the surface metal body 52. By spreading, the sintered member 100A is positioned not only on the mounting portion 529a but also on the intermediate portion 529c. The sintered member 100A does not wet and spread, but is spread by pressure and comes into contact with the thin film portion 520Y. This allows not only the joint between the sintered member 100A and the mounting portion 529a, but also the contact portion between the sintered member 100A and the intermediate portion 529c to function as a heat dissipation path. As a result, a semiconductor device 20 with high heat dissipation properties can be provided. Furthermore, the sintered member 100A has a higher thermal conductivity than solder, which also enhances heat dissipation.

The height of the convex portion 520a of the thin film portion 520Y is lower than that of the thick film portion 520X. This means that the adhesion of the intermediate portion 529c to the sealing body 30 is lower than that of the outer peripheral portion 529b. This makes it difficult for the sealing body 30 to adhere to the intermediate portion 529c. In this embodiment, the sintered member 100A is in contact with the intermediate portion 529c. The sintered member 100A covers the portion of the upper surface 52a where adhesion is weak. This prevents the sealing body 30 from peeling off from the upper surface 52a around (near) the semiconductor element 40. This prevents thermal stress from concentrating on the joint portion of the sintered member 100A and the drain electrode 40D, thereby improving connection reliability.

In this embodiment, the entire intermediate portion 529c is located outside the semiconductor element 40. This allows for a larger joint between the sintered member 100A and the mounting portion 529a. Furthermore, the contact portion between the sintered member 100A, located outside the semiconductor element 40, and the intermediate portion 529c also functions as a heat dissipation path. This further enhances heat dissipation.

<Modification>
Although an example in which the sintered member 100A overlaps the entire intermediate portion 529c has been shown, this is not limiting. The sintered member 100A only needs to overlap at least a portion of the intermediate portion 529c. In other words, the sintered member 100A only needs to be in contact with at least a portion of the thin film portion 520Y of the uneven oxide film 520. This expands the heat dissipation path and improves heat dissipation.

The arrangement of the intermediate portion 529c is not limited to the example described above. Only a portion of the intermediate portion 529c in the width direction may be located outside the semiconductor element 40. By locating at least a portion of the intermediate portion 529c in the width direction outside the semiconductor element 40, the joint area can be enlarged and the heat dissipation path can be expanded, thereby improving heat dissipation.

Furthermore, at least a portion of the intermediate portion 529c in the width direction may be located inside the outer peripheral edge 402 of the semiconductor element 40. In this way, the sintered member 100A comes into contact with the thin film portion 520Y (intermediate portion 529c), thereby improving heat dissipation, and the position of the outer peripheral portion 529b can be brought closer to the semiconductor element 40. In other words, peeling of the sealing body 30 around the semiconductor element 40 can be suppressed.

In the example shown in Figures 100 and 101, the intermediate portion 529c straddles the outer peripheral edge 402 of the semiconductor element 40 in a planar view. In other words, part of the width of the intermediate portion 529c is located outside the outer peripheral edge 402, and another part is located inside the outer peripheral edge 402. The sintered component 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c in a planar view. This improves heat dissipation as described above, while preventing peeling of the sealing body 30 around the semiconductor element 40. Figures 100 and 101 are diagrams showing modified examples. Figure 100 corresponds to Figure 97, and Figure 101 corresponds to Figure 98.

In the example shown in Figures 102 and 103, the outer peripheral edge of the intermediate portion 529c substantially coincides with the outer peripheral edge 402 of the semiconductor element 40 in a planar view. The outer peripheral edge of the sintered member 100A also substantially coincides with the outer peripheral edge 402 of the semiconductor element 40 in a planar view. This positions the outer peripheral portion 529b (thick film portion 520X) adjacent to the semiconductor element 40 in a planar view. Therefore, contact of the sintered member 100A with the intermediate portion 529c improves heat dissipation, while more effectively preventing peeling of the sealing body 30 around the semiconductor element 40. Figures 102 and 103 are diagrams showing modified examples. Figure 102 corresponds to Figure 97, and Figure 103 corresponds to Figure 98.

In the example shown in Figure 104, a portion of the outer peripheral portion 529b overlaps the semiconductor element 40 in a planar view. The intermediate portion 529c is located more inward than the outer peripheral edge 402 of the semiconductor element 40. Figure 104 is a diagram showing a modified example. Figure 104 corresponds to Figure 98. In this case, the sintered member 100A may contact only the thin film portion 520Y. The sintered member 100A may also contact both the thin film portion 520Y and the portion of the thick film portion 520X directly below the semiconductor element 40.

While the example shown shows the uneven oxide film 520 being provided only on the surface metal body 52 to which the drain electrode 40D is connected, this is not limiting. In addition to the surface metal body 52, the uneven oxide film 520 may also be provided on the side of the conductive spacer 70 to which the source electrode 40S is connected, and/or on the surface metal body 62 of the substrate 60. As described above, the thick film portion 520X of the uneven oxide film 520 provides the function of increasing adhesion with the sealing body 30 and the function of suppressing the spreading of the solder, which is the bonding material. The uneven oxide film 520 is preferably provided in locations where it is desired to suppress solder overflow or where it is desired to increase adhesion with the sealing body 30.

Although a substrate 50 has been shown as an example of a wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 50. Also, a metal plate (lead frame) may be used instead of the substrate 60. Instead of the conductive spacer 70, a protrusion may be provided on the metal plate on the source electrode 40S side.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth embodiments, as well as the modified examples.

Twelfth Embodiment
This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress cracks from occurring in the main electrode, the sintered member serving as the bonding material may have a multi-layer structure as described in this embodiment.

<Semiconductor Device>
First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 105. Fig. 105 is a cross-sectional view corresponding to (a part of) Fig. 7. For convenience, the external connection terminals 90 and the bonding wires 110 are not shown in Fig. 105.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figures 2 to 13). As shown in Figure 105, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 that are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The semiconductor element 40 has a drain electrode 40D, which is a first main electrode, on one surface of the semiconductor substrate 41, and a source electrode 40S, which is a second main electrode, on the back surface. The drain electrode 40D is a main electrode on the high potential side, and the source electrode 40S is a main electrode on the low potential side. The source electrode 40S is provided on the same surface as the pad 40P.

The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D. The substrate 60 and conductive spacer 70, which are the second wiring members, are connected to the source electrode 40S. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. Although not shown, the semiconductor device 20 also includes a semiconductor element 40L.

The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A, which is a bonding material 100, as in the configuration described in the previous embodiment (see Figure 97). The source electrode 40S and the conductive spacer 70 are joined by a multilayer bonding material 101C, which is a bonding material 101.

<Multi-layered bonding material and its surrounding structure>
Next, the multilayer bonding material 101C and its surrounding structure will be described with reference to Figures 106 and 107. Figure 106 is an enlarged view of region CVI in Figure 105. For convenience, pads are omitted from Figure 106. Figure 107 is a diagram showing the relationship between the Young's modulus and yield stress of the base electrode 42, sintered layer 106, and fragile layer 107. In the strain-stress diagram shown in Figure 107, the solid line indicates the fragile layer 107, the dashed line indicates the sintered layer 106, and the dashed-dotted line indicates the base electrode 42.

Similar to the configuration described in the preceding embodiment (see FIG. 91), the source electrode 40S has a base electrode 42 formed on a semiconductor substrate 41 and a connection electrode 43 formed on the base electrode 42. The base electrode 42 is made of an AlSi-based alloy such as AlSi or AlSiCu. The connection electrode 43 contains at least a noble metal for bonding with the multilayer bonding material 101C. The connection electrode 43 is, for example, a plated film containing Au or Ag and Ni.

The conductive spacer 70 includes a base material 71 containing a metal such as Cu and forming the main portion of the conductive spacer 70, and a metal film 72 formed on the surface of the base material 71. The metal film 72 contains at least a precious metal for bonding with the multilayer bonding material 101C. The metal film 72 is, for example, a plated film containing Au or Ag and Ni. The metal film 72 is provided on the bonding surface, including the surface facing the semiconductor element 40, for example.

The multilayer bonding material 101C has a sintered layer 106 and a fragile layer 107. The sintered layer 106 has a structure similar to that of the sintered member 101A described in the previous embodiment. The sintered layer 106 is a pressure-sintered body of Ag particles or Cu particles. The fragile layer 107 is intentionally designed to have low strength so that cracks will occur before the source electrode 40S, particularly the base electrode 42, when thermal stress is applied.

As shown in Figure 107, the Young's modulus YM2 of the sintered layer 106 is slightly smaller than the Young's modulus YM1 of the base electrode 42. However, the yield stress YS2 of the sintered layer 106 is significantly larger than the yield stress YS1 of the base electrode 42. The yield strain of the sintered layer 106 is larger than the yield strain of the base electrode 42. On the other hand, the Young's modulus YM3 of the fragile layer 107 is smaller than the Young's modulus YM1 of the base electrode 42. Furthermore, the yield stress YS3 of the fragile layer 107 is smaller than the yield stress YS1 of the base electrode 42. The Young's modulus YM3 of the fragile layer 107 is smaller than the Young's modulus YM2 of the sintered layer 106. The yield stress YS3 of the fragile layer 107 is smaller than the yield stress YS2 of the sintered layer 106.

In this embodiment, the fragile layer 107 is a sintered body made of the same type of particles (e.g., Ag particles) as the sintered layer 106. The fragile layer 107 is a low-pressure sintered body sintered at a lower pressure than the sintered layer 106. The fragile layer 107 is a pressureless sintered body sintered without pressure, for example. Due to sintering at a low pressure, the fragile layer 107 has larger voids between the particles than the sintered layer 106. The fragile layer 107 is sparser than the sintered layer 106.

The fragile layer 107 is a sintered body made of Ag particles or Cu particles. The thermal conductivity of the fragile layer 107 is 200 W/m·K or higher. The thermal conductivity of the sintered layer 106, which is denser than the fragile layer 107, is greater than that of the fragile layer 107.

As shown in Figure 106, the multilayer bonding material 101C has a three-layer structure in the Z direction, which is the thickness direction of the semiconductor element 40, with sintered layers 106 at both ends and a fragile layer 107 between the sintered layers 106. The fragile layer 107 is stacked on the sintered layer 106, and another sintered layer 106 is stacked on the fragile layer 107. One of the sintered layers 106 is bonded to the connection electrode 43 of the source electrode 40S, and the other sintered layer 106 is bonded to the metal film 72 of the conductive spacer 70. The fragile layer 107 is sandwiched between the sintered layers 106 in the Z direction. Because the fragile layer 107 is a low-pressure sintered body as described above, the thickness of the fragile layer 107 is thicker than the thickness of each of the sintered layers 106, for example.

<Summary of the twelfth embodiment>
As described in the preceding embodiment, thermal stress tends to concentrate on the source electrode 40S, particularly on the base electrode 42. Furthermore, in a bonding structure using the bonding material 101, if only a sintered member is used as the bonding material 101, the sintered member is less likely to reach its yield stress than the source electrode 40S, and therefore thermal stress tends to concentrate on the source electrode 40S (base electrode 42).

In this embodiment, the bonding material 101 that bonds the source electrode 40S and the conductive spacer 70 is a multilayer bonding material 101C. The multilayer bonding material 101C has a sintered layer 106 and a fragile layer 107. The fragile layer 107 has a smaller Young's modulus and/or yield stress than the source electrode 40S (base electrode 42). This causes thermal stress to concentrate in the fragile layer 107. For example, cracks will occur in the fragile layer 107 before cracks occur in the source electrode 40S. Therefore, damage to the element can be suppressed.

In this embodiment, as shown in Figure 107, the Young's modulus and yield stress of the fragile layer 107 are both smaller than those of the source electrode 40S (base electrode 42). This effectively prevents damage to the element.

In addition, the multilayer bonding material 101C (bonding material 101) includes a sintered body. The thermal conductivity of a sintered body is significantly higher than that of solder. Therefore, heat dissipation can be improved.

In this embodiment, the fragile layer 107 is a sintered body made of the same type of particles as the sintered layer 106. The fragile layer 107 has larger voids between the particles than the sintered layer 106. The fragile layer 107 is a sintered body formed with a lower pressure than the sintered layer 106. By changing the pressure, the sintered layer 106 and the fragile layer 107 can be formed. This simplifies the configuration.

In this embodiment, the multilayer bonding material 101C has a three-layer structure. The multilayer bonding material 101C has sintered layers 106 on both ends and a fragile layer 107 between the sintered layers 106. One of the sintered layers 106 forms a bond with the source electrode 40S, and the other sintered layer 106 forms a bond with the conductive spacer 70, which is the second wiring member. This ensures bonding between the source electrode 40S and the conductive spacer 70 while suppressing damage to the element.

<Modification>
Although the fragile layer 107 is sintered at a lower pressure than the sintered layer 106, the present invention is not limited to this. Instead of the sintered fragile layer 107, a non-sintered fragile layer 108 may be used, as shown in FIG. 108 . The fragile layer 108 contains, for example, Al. The Al-containing fragile layer 108 has a Young's modulus and/or yield stress lower than that of the source electrode 40S (base electrode 42). Therefore, similar to the fragile layer 107, element damage can be suppressed. The Al-containing fragile layer 108 also has a thermal conductivity of 200 W/m·K or higher. FIG. 108 is a cross-sectional view showing a modified example, corresponding to FIG. 106 .

While the multilayer bonding material 101C has been shown as having a three-layer structure, this is not limiting. For example, it may have a four or more layer structure. Alternatively, as shown in Figure 109, it may have a two-layer structure. The multilayer bonding material 101C has a sintered layer 106 on the conductive spacer 70 side and a fragile layer 107 on the source electrode 40S side. In this way, the fragile layer 107 is positioned close to the semiconductor element 40. This enhances the effect of suppressing element damage. Figure 109 is a cross-sectional view showing a modified example, and corresponds to Figure 106.

In the example shown in Figure 110, the multilayer bonding material 101C has a sintered layer 106 on the source electrode 40S side and a fragile layer 107 on the conductive spacer 70 side. The sintered layer 106, which is a pressure-sintered body and has better heat dissipation properties than the fragile layer 107, is positioned closer to the semiconductor element 40. This improves heat dissipation. Figure 110 is a cross-sectional view showing a modified example and corresponds to Figure 106.

In the example shown, the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, but this is not limiting. Instead of the conductive spacer 70, a convex portion may be provided on the surface metal body 62. In other words, the second wiring member may be configured to include only the substrate 60, without the conductive spacer 70. In this case, the multilayer bonding material 101C is interposed between the tip surface of the convex portion of the surface metal body 62 and the source electrode 40S (connection electrode 43).

Although a substrate 50 has been shown as an example of the first wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 50. Although a substrate 60 has been shown as an example of the second wiring member, this is not limiting. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and conductive spacers 70, or a metal plate may have a protrusion instead of the conductive spacers 70.

Although an example has been shown in which the semiconductor device 20 includes semiconductor elements 40H and 40L, this is not limiting. The semiconductor device 20 may include only a semiconductor element 40 that constitutes one of the arms. For example, the semiconductor device 20 may include only one semiconductor element 40.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh embodiments, as well as the modified examples.

Thirteenth Embodiment
This embodiment is a modification of the preceding embodiment as a basic configuration, and the description of the preceding embodiment can be used. As described in this embodiment, each arm may be formed of a single semiconductor element 40.

<Power conversion device>
First, the circuit configuration of the power conversion device 4 to which the semiconductor device 20 is applied will be described with reference to Fig. 111. Fig. 111 is a diagram showing an equivalent circuit of the power conversion device 4.

The power conversion device 4 shown in Figure 111 is also used in a vehicle drive system 1. The configuration of the power conversion device 4 is substantially the same as the configuration described in the previous embodiment (see Figure 1). The difference is that each arm has only one MOSFET 11. The upper and lower arm circuits 9 for one phase are composed of two MOSFETs 11. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20.

<Semiconductor Device>
Next, the semiconductor device will be described with reference to FIGS. 112 to 121. FIG. 112 is a perspective view of the semiconductor device 20. FIG. 113 is a plan view showing the semiconductor device 20. FIG. 113 is a see-through view showing the internal structure. FIG. 114 is a plan view showing a state in which a semiconductor element 40 is mounted on a substrate 50. In FIG. 10, the lead frame 94 is shown for convenience in FIG. 114. FIG. 115 is a plan view showing the circuit pattern of the substrate 50. FIG. 115 shows a state in which the semiconductor element 40 and the joint portion 81 are mounted on the substrate 50. In FIG. 115, the P terminal 91P, the output terminal 92, and the guide frame 94c joined to the surface metal body 52 are also shown by dashed lines.

Figure 116 is a plan view showing the circuit pattern of the substrate 60. In Figure 116, the semiconductor element 40, joint portion 81, and N terminal 91N bonded to the surface metal body 62 are also shown by dashed lines. Figure 117 is a cross-sectional view taken along line CXVII-CXVII in Figure 113. Figure 118 is a cross-sectional view taken along line CXVIII-CXVIII in Figure 113. Figure 119 is a cross-sectional view taken along line CXIX-CXIX in Figure 113. Figure 120 is a cross-sectional view taken along line CXX-CXX in Figure 113. Figure 121 is an enlarged view of area CXXI indicated by the dashed line in Figure 120.

In this embodiment, as in the previous embodiment, the thickness direction of the semiconductor element 40 (semiconductor substrate) is defined as the Z direction, and the arrangement direction of the semiconductor elements 40H, 40L is defined as the Y direction. The direction perpendicular to both the Z direction and the Y direction is defined as the X direction. Unless otherwise specified, the shape when viewed from above in the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction, is defined as the planar shape. Hereinafter, "inside" and "outside" refer to the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side farther from the center is the outside.

Similar to the previous embodiment, the semiconductor device 20 of this embodiment constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 20 comprises elements similar to those in the configuration described in the previous embodiment (see Figures 2 to 13). As shown in Figures 112 to 121, the semiconductor device 20 comprises a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90. The following mainly describes the parts that differ from the configuration described in the previous embodiment.

As in the previous embodiment, the encapsulant 30 encapsulates some of the other elements that make up the semiconductor device 20. As shown in Figures 112 and 113, the encapsulant 30 has a generally rectangular shape in plan view. The encapsulant 30 has one surface 30a and a back surface 30b in the Z direction. The side surface connecting the one surface 30a and the back surface 30b includes two side surfaces 30f and 30g from which the external connection terminals 90 protrude. Side surface 30g is the surface opposite side surface 30f in the X direction.

The semiconductor element 40 has a switching element formed on a semiconductor substrate. Similar to the previous embodiment, the semiconductor element 40 of this embodiment has an n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The semiconductor element 40 has a drain electrode 40D on one side as main electrodes, and a source electrode 40S on the back side. The semiconductor element 40 has a pad 40P on the back side.

The semiconductor elements 40 include one semiconductor element 40H that constitutes the upper arm 9H and one semiconductor element 40L that constitutes the lower arm 9L. The semiconductor elements 40H, 40L have a common configuration. As shown in Figures 113 and 114, the semiconductor elements 40H, 40L are aligned in the Y direction. The semiconductor elements 40 are arranged at approximately the same position as each other in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

The substrates 50, 60 are arranged in the Z direction so as to sandwich multiple semiconductor elements 40 therebetween. The substrates 50, 60 are arranged so that at least a portion of each substrate faces each other in the Z direction. The substrates 50, 60 contain all of the multiple semiconductor elements 40 (40H, 40L) when viewed in a plan view.

Substrate 50 is disposed on the drain electrode 40D side. Substrate 60 is disposed on the source electrode 40S side. Substrate 50 is electrically connected to drain electrode 40D and provides wiring functionality. Substrate 60 is electrically connected to source electrode 40S and provides wiring functionality. Substrates 50 and 60 provide a heat dissipation function to dissipate heat generated by semiconductor element 40.

Substrate 50 comprises an insulating substrate 51, a front metal body 52, and a back metal body 53. Substrate 60 comprises an insulating substrate 61, a front metal body 62, and a back metal body 63. Substrate 60 is a substrate in which insulating substrate 61 and metal bodies 62, 63 are stacked. Hereinafter, front metal bodies 52, 62 and back metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63.

The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. In this embodiment, resin-based insulating substrates 51 and 61 are used, and the material composition is the same.

Metal bodies 52, 53, 62, 63 are provided, for example, as metal plates or metal foils. Surface metal bodies 52, 62 are patterned. Surface metal bodies 52, 62 may have a plating film of Ni-based or Au, etc., on the metal surface. Hereinafter, the pattern of surface metal bodies 52, 62 may be referred to as a circuit pattern. As in the previous embodiment, surface metal body 52 has P wiring 54 and relay wiring 55. P wiring 54 and relay wiring 55 are electrically separated by a predetermined gap. This gap is filled with sealing body 30.

The P wiring 54 is connected to the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 has a generally rectangular shape in plan view with its longitudinal direction in the X direction. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection portion 80, and the output terminal 92. The relay wiring 55 has a generally rectangular shape in plan view.

The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. The semiconductor element 40L is mounted on the relay wiring 55, biased toward one end in the Y direction, specifically the side farther from the P wiring 54. The joint portion 81 that constitutes the arm connection portion 80 is mounted on the relay wiring 55, biased toward the other end in the Y direction, specifically the side closer to the P wiring 54. The P terminal 91P is connected to the P wiring 54 near one end in the X direction. The output terminal 92 is connected to the relay wiring 55 near one end in the X direction. The P terminal 91P and the output terminal 92 are arranged on the same side in the X direction relative to the semiconductor element 40.

As in the previous embodiment, the surface metal body 62 has an N wiring 64 and a relay wiring 65. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined gap. This gap is filled with the sealing body 30. The N wiring 64 is connected to the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connection portion 80.

The N wiring 64 has a base 644 and an extension 645. The N wiring 64 is generally L-shaped in plan view. The base 644 is generally rectangular in plan view. The base 644 contains the semiconductor element 40L in plan view. The extension 645 is connected to one side of the generally rectangular base 644 in plan view. The extension 645 extends from the side of the base 644 facing the relay wiring 65 toward the base 654 in the Y direction.

The relay wiring 65 has a base 654 and an extension portion 655. The relay wiring 65 is generally L-shaped in plan view. The base 654 is generally rectangular in plan view. The base 654 contains the semiconductor element 40H in plan view. The extension portion 655 is connected to one side of the generally rectangular base 654 in plan view. The extension portion 655 extends from the side of the base 654 facing the N wiring 64 toward the base 644 in the Y direction. At least a portion of the extension portion 655 overlaps with the relay wiring 55 in plan view.

The N wiring 64 and relay wiring 65 are arranged side by side in the Y direction. The bases 644, 654 are aligned in the Y direction. The source electrode 40S of the semiconductor element 40L is electrically connected to the base 644. The source electrode 40S of the semiconductor element 40H is electrically connected to the base 654. The extensions 645, 655 are aligned in the X direction. The N terminal 91N is connected to the extension 645. The joint 81 is connected to the extension 655.

The back surface metal bodies 53, 63 are electrically isolated from the front surface metal bodies 52, 62 by the insulating substrates 51, 61. In this embodiment, the back surface metal bodies 53, 63 are so-called solid conductors arranged over almost the entire back surface of the insulating substrates 51, 61. The back surface metal body 53 is exposed from one surface 30a of the encapsulant 30, and the back surface metal body 63 is exposed from the back surface 30b. The exposed surface of the back surface metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back surface metal body 63 is approximately flush with the back surface 30b.

The conductive spacers 70 are interposed between the source electrodes 40S of the semiconductor elements 40 and the substrate 60. The conductive spacers 70 are individually connected to the source electrodes 40S of the semiconductor elements 40. The semiconductor device 20 includes two conductive spacers 70. One of the conductive spacers 70 electrically connects the source electrode 40S of the semiconductor element 40H to the relay wiring 65. The other conductive spacer 70 electrically connects the source electrode 40S of the semiconductor element 40L to the N wiring 64.

The arm connection portion 80 electrically connects the relay wirings 55 and 65. The arm connection portion 80 is provided between the semiconductor elements 40H and 40L in the Y direction. The arm connection portion 80 is provided in the overlapping region of the relay wirings 55 and 65 (extension portion 655) in a plan view. As in the previous embodiment, the arm connection portion 80 of this embodiment is configured with a joint portion 81 and a bonding material 103. The joint portion 81 is a metal column. In the Z direction, the bonding material 103 is interposed between one end of the joint portion 81 and the relay wiring 55, and between the other end and the relay wiring 65.

Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may not include the joint portion 81. In other words, the arm connection portion 80 may include only the bonding material 103.

The external connection terminals 90 include a power supply terminal 91, an output terminal 92, and a signal terminal 93. The power supply terminal 91 includes a P terminal 91P and an N terminal 91N. Hereinafter, the P terminal 91P, N terminal 91N, and output terminal 92 may be referred to as main terminals 91P, 91N, and 92. The signal terminals 93 include a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

The P terminal 91P is connected to the P wiring 54 near one end in the X direction. The P terminal 91P extends outward in the X direction from the connection portion 91a with the P wiring 54. A portion of the P terminal 91P, including the connection portion 91a, is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The P terminal 91P protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The N terminal 91N is connected to the N wiring 64 near one end in the X direction. The N terminal 91N extends outward in the X direction from the connection portion 91b with the N wiring 64. A portion of the N terminal 91N, including the connection portion 91b, is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The N terminal 91N protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The output terminal 92 is connected to the relay wiring 55 near one end in the X direction. The output terminal 92 extends outward in the X direction from the connection portion 92a with the relay wiring 55. A portion of the output terminal 92, including the connection portion 92a, is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The output terminal 92 protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The three main terminals 91P, 91N, and 92 are arranged side by side in the Y direction. The main terminals 91P, 91N, and 92 are arranged in the Y direction in the order of P terminal 91P, N terminal 91N, and output terminal 92. The P terminal 91P and N terminal 91N, which are power supply terminals 91, have their sides facing each other in a portion that includes the portion protruding from the sealing body 30.

Signal terminal 93 is electrically connected to the pad 40P of the corresponding semiconductor element 40 via a connecting member such as a bonding wire 110. Signal terminal 93H is connected to the pad 40P of semiconductor element 40H via a bonding wire 110. Signal terminal 93L is connected to the pad 40P of semiconductor element 40L via a bonding wire 110. Signal terminal 93 extends outward in the X direction and protrudes outside the sealing body 30 from near the center of side surface 30g in the Z direction. Signal terminal 93 extends on the opposite side of main terminals 91P, 91N, and 92 in the X direction.

The lead frame 94, like the configuration described in the previous embodiment, includes external connection terminals 90, tie bars 94a, and an outer peripheral frame 94b. In this embodiment, the lead frame 94 further includes a guide frame 94c. As described in the previous embodiment, the tie bars 94a and outer peripheral frame 94b are removed as unnecessary parts during the manufacturing process of the semiconductor device 20. Meanwhile, the guide frame 94c remains as an element of the semiconductor device 20, along with the external connection terminals 90.

As shown in Figure 114, the lead frame 94 has two guide frames 94c. One of the guide frames 94c is connected to the P terminal 91P. Before unnecessary portions are removed, the guide frame 94c connects the P terminal 91P and the outer frame 94b. The other guide frame 94c is connected to the output terminal 92. Before unnecessary portions are removed, the guide frame 94c connects the output terminal 92 and the outer frame 94b.

As shown in Figures 114 and 119 to 121, the guide frame 94c has a connection portion 940, a first linking portion 941, and a second linking portion 942. The connection portion 940 is the portion of the guide frame 94c that connects to the surface metal body 52. The guide frame 94c that is connected to the P terminal 91P is connected to the P wiring 54. Specifically, the connection portion 940 is the end of the P wiring 54 opposite the connection portion of the P terminal 91P, and is connected near the end opposite the relay wiring 55 in the Y direction. The connection portion 940 is connected to one of the four corners of the P wiring 54, which has a substantially rectangular shape in plan view.

The first connecting portion 941 connects the P terminal 91P and the connecting portion 940. The first connecting portion 941 extends from the connecting portion 91a of the P terminal 91P in the X direction toward the side surface 30g. The first connecting portion 941 does not overlap the P wiring 54 (surface metal body 52) in a plan view. The first connecting portion 941 extends outside the surface metal body 52, along the outer peripheral edge of the surface metal body 52. The second connecting portion 942 connects the connecting portion 940 and the outer peripheral frame 94b. The second connecting portion 942 extends outward from the connecting portion 940 in the X direction.

The guide frame 94c connected to the output terminal 92 is connected to the relay wiring 55. Specifically, the connection portion 940 is connected to the end of the relay wiring 55 opposite the connection portion of the output terminal 92, near the end opposite the P wiring 54 in the Y direction. The connection portion 940 is connected to one of the four corners of the relay wiring 55, which has a generally rectangular shape when viewed from above.

The first connecting portion 941 connects the output terminal 92 and the connection portion 940. The first connecting portion 941 extends from the connection portion 92a of the output terminal 92 in the X direction toward the side surface 30g. The first connecting portion 941 does not overlap the relay wiring 55 (surface metal body 52) in a plan view. The first connecting portion 941 extends outside the surface metal body 52, along the outer periphery of the surface metal body 52. The second connecting portion 942 connects the connection portion 940 and the outer periphery frame 94b. The second connecting portion 942 extends outward from the connection portion 940 in the X direction.

The guide frame 94c can have a connection structure (joint structure) similar to that of the main terminals 91P, 91N, and 92. The guide frame 94c is connected to the surface metal body 52, for example, via a joining material 104. As described in the previous embodiment, the joining material 104 can be solder or a sintered material. The guide frame 94c may also be joined directly to the surface metal body 52 without the joining material 104. For example, the guide frame 94c may be joined directly to the surface metal body 52 by ultrasonic welding, friction stir welding, laser welding, or the like.

As described above, in the semiconductor device 20 of this embodiment, the multiple semiconductor elements 40 that make up one phase of the upper and lower arm circuits 9 are sealed by the sealing body 30. The sealing body 30 integrally seals the multiple semiconductor elements 40, a portion of the substrate 50, a portion of the substrate 60, the multiple conductive spacers 70, the arm connection portion 80, and a portion of each of the external connection terminals 90. The sealing body 30 seals the insulating substrates 51, 61 and the surface metal bodies 52, 62 on the substrates 50, 60.

The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the opposing substrates 50 and 60. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is approximately flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is approximately flush with the back surface 30b of the sealing body 30. Because the back surfaces 50b and 60b are exposed, heat dissipation can be improved.

<Summary of the thirteenth embodiment>
The configuration described in this embodiment can be combined with some of the various configurations described in the preceding embodiments. The aforementioned some configurations include a configuration in which a power terminal is connected to each of a pair of extension portions of a surface metal body (see FIGS. 15 and 23 ) and a configuration in which a slit is provided in the surface metal body to separate multiple semiconductor elements connected in parallel (see FIG. 28 , etc.). In other words, the configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, the eighth embodiment, the ninth embodiment, the tenth embodiment, the eleventh embodiment, the twelfth embodiment, and the modified examples.

Although an example in which the semiconductor device 20 includes a conductive spacer 70 has been shown, this is not limiting. Instead of the conductive spacer 70, a protrusion may be provided on the surface metal body 62.

Although a substrate 50 has been shown as an example of the wiring member connected to the drain electrode 40D, this is not limiting. In configurations that are not limited to a substrate 50, a metal plate (lead frame) may be used instead of the substrate 50. Although a substrate 60 has been shown as an example of the wiring member connected to the source electrode 40S, this is not limiting. In configurations that are not limited to a substrate 60, a metal plate (lead frame) may be used instead of the substrate 60.

(Other embodiments)
The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and/or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and/or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and/or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas set forth in the claims, and extends to technical ideas that are more diverse and extensive than the technical ideas set forth in the claims. Therefore, a variety of technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, there are no intervening elements or layers. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and/or" includes any and all combinations of one or more associated listed items.

Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of the relationship of one element or feature to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may also be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

The vehicle drive system 1 is not limited to the above configuration. For example, while an example has been shown in which one motor-generator 3 is provided, this is not limiting. Multiple motor-generators may be provided. While an example has been shown in which the power conversion device 4 includes an inverter 6 as a power conversion circuit, this is not limiting. For example, the system may be configured to include multiple inverters. The system may be configured to include at least one inverter and a converter. The system may also be configured to include only a converter.

Although the semiconductor element 40 has an example in which the MOSFET 11 is used as a switching element, the present invention is not limited to this. For example, an IGBT (Insulated Gate Bipolar Transistor) may also be used.
The technical ideas that can be understood from the embodiments and modifications described above will be described below as supplementary notes.
<Appendix 1>
A semiconductor device constituting an upper and lower arm circuit (9),
a semiconductor element (40) having main electrodes (40D, 40S) on both sides;
a substrate (50, 60) having an insulating substrate (51, 61), a front surface metal body (52, 62) disposed on the front surface of the insulating substrate and electrically connected to the main electrode, and a back surface metal body (53, 63) disposed on the back surface of the insulating substrate,
The surface metal body has a first wiring (64) extending in a predetermined direction, and a second wiring (65) having a different potential from the first wiring and extending in the predetermined direction with a predetermined gap between it and the first wiring,
the first wiring and the second wiring have currents flowing in opposite directions along the predetermined direction;
a distance between the first wiring and the second wiring that is equal to or less than a thickness of the surface metal body;

1...Drive system, 2...DC power supply, 3...Motor generator, 4...Power conversion device, 5...Smoothing capacitor, 6...Inverter, 7...P line, 8...N line, 9...Upper and lower arm circuits, 9H...Upper arm, 9L...Lower arm, 10...Output line, 11...MOSFET, 12...Diode, 20...Semiconductor device, 30...Sealing body, 30a...One surface, 30b...Reverse surface, 30c, 30d, 30e, 30f, 30g...Side surface, 31...Air gap, 40, 40H, 40L...Semiconductor element, 40D...Drain electrode, 40S...Source electrode, 40P...Pad, 400, 401...Side, 402...Outer Peripheral edge, 41...semiconductor substrate, 41a...one surface, 41b...rear surface, 42...base electrode, 420...periphery, 43...connection electrode, 44...protective film, 440, 441...opening, 442...inner peripheral surface, 50...substrate, 50a...opposing surface, 50b...rear surface, 50c, 50d...edge, 50sc...center, 500...laminated body, 501...first inclined portion, 501a...cutting marks, 502...second inclined portion, 502a...cutting marks, 503...intermediate portion, 503a...uneven portion, 51...insulating base material, 51a...surface, 51b...rear surface, 510...exposed portion, 52...surface metal body, 52a...upper surface, 52b...edge, 52c...side surface, 52d ...underside, 52G...gap between wirings, 520...uneven oxide film, 520a...protruding portion, 520X...thick film portion, 520Y...thin film portion, 521...base material, 522...metal film, 522p...plated film, 523...recess, 524...first region, 525...second region, 526...peripheral region, 527...roughened portion, 528...non-roughened portion, 529a...mounting portion, 529b...peripheral portion, 529c...intermediate portion, 53...back metal body, 53a...opposing surface, 53b...exposed surface, 54...P wiring, 540...notch, 541...base portion, 542...extension portion, 55...relay wiring, 550...notch, 551...base portion, 551a...opposing side , 552...extension portion, 553...slit, 554...chamfered portion, 56...laminated body, 60...substrate, 60a...opposing surface, 60b...rear surface, 60c...edge, 60sc...center, 600...laminated body, 601...first inclined portion, 602...second inclined portion, 603...intermediate portion, 61...insulating base material, 61a...surface, 61b...rear surface, 610...exposed portion, 62...surface metal body, 62a...upper surface, 62c...side surface, 62d...lower surface, 62G...inter-wiring gap, 620...uneven oxide film, 624...first region, 625...second region, 626...peripheral region, 627...roughened portion, 628...non-roughened portion, 63...rear surface metal body, 63 a...opposing surface, 63b...exposed surface, 64...N wiring, 640, 644...base, 640a...opposing side, 640b...placement area, 640c...end, 641, 645...extending portion, 641a...widened portion, 641b...fixed width portion, 641c...widened portion, 641d...tip portion, 642...notch, 643...slit, 65...relay wiring, 650, 652...end, 651a...reduced width portion, 651b...fixed width portion, 651c...reduced width portion, 653...slit, 654...base, 655...extending portion, 70...conductive spacer, 700...uneven oxide film, 71...base material, 72...metal film, 80...arm connecting portion, 81...joint portion, 81a, 81b...end portion, 81c, 81d...side surface, 810...opposing surface, 811...accommodating portion, 811a...side surface, 811b...bottom surface, 90...external connection terminal, 91...power supply terminal, 91a, 91b...connecting portion, 91N...N terminal, 91P...P terminal, 92...output terminal, 92a...connecting portion, 920...opposing surface, 920a...first opposing portion, 920b...second opposing portion, 921...accommodating portion, 921a...side surface, 921b...bottom surface, 921c...opening, 922...tip surface, 923, 924...side surface, 93, 93H, 93L...signal terminal, 93a...tie bar mark, 93b...joint portion, 93c...tip portion, 93 d...bent portion, 93e...extension portion, 93f...pressed R surface, 93g...burr surface, 93h...first extension portion, 93i...second extension portion, 93j...bent portion, 93k...projection portion, 930...overlapping portion, 930a...main portion, 930b...projection portion, 931...non-overlapping portion, 94...lead frame, 94a...tie bar, 94b...peripheral frame, 94c...guide frame, 940...connection portion, 941...first linking portion, 941a...first extension portion, 941b...second extension portion, 942...second linking portion, 100, 101, 102, 103, 104...joint material, 101A...sintered member, 101B...solder, 101 C...multilayer bonding material, 105...sintered sheet, 106...sintered layer, 107, 108...weak layer, 110...bonding wire, 111...jig, 112...tool, 120...cooler, 121...heat exchanger, 130...thermal conductive member, 140...semiconductor module, 150...intermediate board, 151...insulating substrate, 151a...front surface, 151b...rear surface, 151c...non-placement area, 151d...placement area, 151e...exposed portion, 152...conductor portion, 152a, 152b...land, 152c...wiring, 152d...via conductor, 152e...fixing land, 153...solder resist, 154...bonding material

Claims (15)

a plurality of semiconductor elements (40) each having a first main electrode (40D) and a second main electrode (40S) formed on a surface opposite to the first main electrode in a plate thickness direction, the semiconductor elements (40) including a first element (40H) constituting one of the arms of an upper and lower arm circuit (9), and a second element (40L) constituting the other of the arms and arranged alongside the first element in a first direction perpendicular to the plate thickness direction;
a plurality of power supply terminals (91) arranged so that the first element is located between the first and second elements in the first direction, the first power supply terminals (91P) being electrically connected to the first main electrodes of the first elements and the second power supply terminals (91N) being electrically connected to the second main electrodes of the second elements;
a first substrate (50) having a first insulating base material (51); a first front surface metal body (52) that is arranged on a surface of the first insulating base material and includes first power supply wiring (54) that electrically connects the first power supply terminal and the first main electrode of the first element, and first relay wiring (55) that is arranged alongside the first power supply wiring in the first direction and connected to the first main electrode of the second element; and a first back surface metal body (53) that is arranged on a back surface of the first insulating base material;
a second substrate (60) arranged so as to sandwich the plurality of semiconductor elements between itself and the first substrate in the plate thickness direction, the second substrate having: a second insulating base (61); a second front surface metal body (62) arranged on a surface of the second insulating base, the second power supply wiring (64) electrically connecting the second power supply terminal and the second main electrode of the second element, and a second relay wiring (65) connected to the second main electrode of the first element; and a second back surface metal body (63) arranged on a back surface of the second insulating base;
an arm connection portion (80) disposed between the first element and the second element in the first direction and electrically connecting the first relay wiring and the second relay wiring;
a sealing body (30) that seals the plurality of semiconductor elements, the arm connection portion, a portion of each of the plurality of power supply terminals, the first surface metal body, and the second surface metal body,
The second power supply wiring is arranged alongside the second relay wiring in the first direction, and has a base (640) on which the second element is arranged, and a pair of extension portions (641) extending from the base in the first direction so as to sandwich the second relay wiring in a second direction perpendicular to the plate thickness direction and the first direction, and each of which is connected to the second power supply terminal . 2. The semiconductor device according to claim 1, wherein the distance between said second power supply wiring and said second relay wiring is equal to or less than the thickness of said second surface metal body. 3. The semiconductor device according to claim 1, wherein the distance between said first power supply wiring and said first relay wiring is equal to or less than the thickness of said first surface metal body. the pair of extension portions of the second power supply wiring and the pair of second relay wirings have currents flowing in opposite directions along the first direction;
2. The semiconductor device according to claim 1, wherein the distance between said second power supply wiring and said second relay wiring is equal to or less than the thickness of said second surface metal body. 2. The semiconductor device according to claim 1, wherein a shortest distance between said first power supply wiring and said second power supply wiring is longer than a shortest distance between said first power supply wiring and said first relay wiring and a shortest distance between said second power supply wiring and said second relay wiring. 6. The semiconductor device according to claim 1, wherein a portion of each of said pair of extension portions faces said first power supply wiring in said thickness direction. the plurality of semiconductor elements include a plurality of the first elements and a plurality of the second elements,
The plurality of first elements are arranged side by side in the second direction,
7. The semiconductor device according to claim 1, wherein the second elements are arranged side by side in the second direction. two second power supply terminals;
8. The semiconductor device according to claim 1, wherein one of the second power supply terminals is connected to one of the pair of extension portions, and the other of the second power supply terminals is connected to the other of the pair of extension portions. two of the first power supply terminals;
the two first power supply terminals are respectively connected to the first power supply wiring;
The semiconductor device according to claim 8 , wherein the first power supply terminals are arranged between the second power supply terminals in the second direction. 10. The semiconductor device according to claim 1, wherein the first power supply terminal and the second power supply terminal protrude from a first surface (30c) of the sealing body. further comprising an output terminal (92) electrically connected to the first relay wiring,
11. The semiconductor device according to claim 10, wherein the output terminal protrudes from a second surface (30d) of the sealing body, the second surface being opposite to the first surface in the first direction. Further provided is a first signal terminal (93H) connected to the first element and a second signal terminal (93L) connected to the second element,
12. The semiconductor device according to claim 1, wherein the first signal terminal protrudes from a surface of the sealing body opposite to a surface from which the second signal terminal protrudes. 13. The semiconductor device according to claim 12, wherein said first signal terminal protrudes from the same surface of said sealing body as said first power supply terminal and said second power supply terminal. an output terminal (92) electrically connected to the first relay wiring;
14. The semiconductor device according to claim 12, wherein the second signal terminal protrudes from the same surface of the sealing body as the output terminal. Further provided is a first signal terminal (93H) connected to the first element;
10. The semiconductor device according to claim 9, wherein the second power supply terminal, the first power supply terminal, the first signal terminal, the first power supply terminal, and the second power supply terminal are arranged in this order in the second direction.