JP7739730B2 - Imaging unit and imaging device - Google Patents

Description

The present invention relates to an imaging unit and an imaging device.

2. Description of the Related Art Imaging devices are known that include an imaging element and a package that the imaging element is mounted in. There has been a demand for smaller and thinner imaging devices.
[Prior art documents]
[Patent Documents]
[Patent Document 1] JP 2010-103456 A

A first aspect of the present invention provides an imaging unit comprising: an imaging chip that captures an image of a subject; and a mounting board having a first main surface and a second main surface, the imaging chip mounted on the first main surface, and a first connector and a second connector mounted on the second main surface for connection to an external device.

Note that the above summary of the invention does not list all of the necessary features of the present invention. Subcombinations of these features may also constitute inventions.

1 is a schematic cross-sectional view of a camera 10, which is an example of an imaging device, according to an embodiment. FIG. 2 is a top view schematically illustrating an imaging unit 40 according to one embodiment. FIG. 3 is a cross-sectional view schematically showing the AA cross section of FIG. 2. FIG. 2 is a schematic bottom view of an imaging unit 40 according to one embodiment. 10 is a bottom view schematically illustrating a state in which an imaging unit 40 is connected to an ASIC 52 and a power supply unit 53 via a first flexible substrate 250 and a second flexible substrate 260 according to an embodiment. FIG. FIG. 6 is a schematic enlarged view of region (A) shown in FIG. 5. 10 is a bottom view schematically illustrating a state in which an imaging unit 41 is connected to an ASIC 52 and a power supply unit 53 via a first flexible substrate 250 and a second flexible substrate 260 according to an embodiment. FIG. FIG. 10 is a bottom view schematically illustrating a state in which an imaging unit 42 is connected to an ASIC 52 and a power supply unit 53 via a first flexible substrate 257 and a second flexible substrate 267 according to an embodiment. FIG. 2 is a side view schematically illustrating a portion of a first flexible substrate 270 according to one embodiment.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

Figure 1 is a schematic cross-sectional view of a camera 10, which is an example of an imaging device, according to one embodiment. Camera 10 is, for example, a digital compact camera. Camera 10 includes a lens unit 20 and a camera body 30.

Lens unit 20 has an optical system within its barrel, and this optical system defines an optical axis 22. Lens unit 20 is attached to camera body 30. Lens unit 20 may be housed within camera body 30 and extend outward when in use, as shown in the figure.

The lens unit 20 guides the incident subject light beam into the housing 31 of the camera body 30. Note that the lens unit 20 shown in Figure 1 includes two lenses and an aperture simply for clarity of explanation, but is not limited to this configuration.

The camera body 30 has an imaging unit 40, a board unit 60, and a display unit 88. The camera body 30 also has a first flexible board 250 and a second flexible board 260 that connect the imaging unit 40 and the board unit 60.

A subject light beam incident on the lens unit 20 is guided by the lens unit 20 to the imaging unit 40. The imaging unit 40 includes an imaging chip 100 that captures an image of the subject, and a mounting substrate 120 having a first main surface 111 and a second main surface 112. In this embodiment, the imaging unit 40 further includes a frame 140 and a cover glass 160. Note that the imaging unit 40 does not necessarily have to include the frame 140 and the cover glass 160.

The imaging chip 100 is, for example, a CMOS image sensor or a CCD image sensor, and has a rectangular main plane shape. The imaging chip 100 is mounted on the first main surface 111 of the mounting substrate 120.

In this embodiment, the direction along the optical axis 22 is defined as the z-axis direction. That is, the direction in which the subject light beam is incident on the imaging surface of the imaging chip 100 is defined as the z-axis direction. Specifically, the direction in which the subject light beam is incident is defined as the negative z-axis direction, and the opposite direction is defined as the positive z-axis direction. The longitudinal direction of the imaging chip 100 is defined as the x-axis direction. The lateral direction of the imaging chip 100 is defined as the y-axis direction. Specifically, the x-axis and y-axis directions are defined as the directions shown in Figure 1. The x-axis, y-axis, and z-axis are in a right-handed Cartesian coordinate system.

When defined in this way, the imaging unit 40, board unit 60, and display unit 88 in this embodiment are arranged in this order in the negative z-axis direction. For ease of explanation, the positive z-axis direction may be referred to as the front, front side, etc. The negative z-axis direction may be referred to as the rear, back side, etc. The side in the negative z-axis direction may be referred to as the back side, etc.

If an imaging unit has only one connector mounted on the backside of its mounting board, that connector must be capable of multiple applications, including power supply, control, and image transmission, to drive and/or control the imaging chip and read images from it. Flexible boards connected to connectors with multiple applications must also be capable of multiple applications. For this reason, flexible boards specialized for applications involving high current flow or high-speed image signal transmission cannot be used. However, as imaging chips become more pixelated and their readout speeds increase, their power consumption tends to increase. Furthermore, when stacked imaging chips incorporating large-scale circuits such as memory are mounted, the power consumption of the imaging chip increases even further. Furthermore, when multiple flexible boards corresponding to multiple applications are connected to a single connector with multiple applications, due to the layout of the image processing circuitry, power supply, and other components within the camera body, each flexible board must be arranged so that it extends in different directions from the connector, necessitating the use of at least one of the flexible boards as a relatively large size. A relatively large space must be provided within the camera body for such flexible boards, resulting in a relatively large and thick overall device.

In contrast, according to this embodiment, a first connector 181 and a second connector 183 are mounted on the second main surface 112 of the mounting substrate 120. The first connector 181 and the second connector 183 are used to connect to devices external to the imaging unit 40. In this way, by mounting the first connector 181 and the second connector 183 on the mounting substrate 120, the imaging unit 40 of this embodiment can contribute to making the camera 10 smaller and thinner.

The first connector 181 mounted on the mounting board 120 is connected to the first flexible substrate 250. As an example, the first connector 181 may be used to transmit image signals to an external image processing device via the first flexible substrate 250. In other words, the first connector 181 and the first flexible substrate 250 may be specialized for transmitting image signals.

The second connector 183 mounted on the mounting substrate 120 is connected to the second flexible substrate 260. As an example, the second connector 183 may be connected to an external power supply device via the second flexible substrate 260 and used to supply current to the imaging chip 100. In other words, the second connector 183 and the second flexible substrate 260 may be specialized for the purpose of supplying current to the imaging chip 100.

The imaging unit 40 may include three or more connectors. In other words, three or more connectors may be mounted on the second main surface 112 of the mounting substrate 120. Each of the three or more connectors may be connected to a separate flexible substrate. Each pair of connector and flexible substrate may be specialized for a specific application. The applications of multiple such pairs may be partially or entirely common to each other.

The board unit 60 is disposed in the negative z-axis direction of the imaging unit 40. The board unit 60 includes a board 62, and an MPU 51, an ASIC 52, and a power supply unit 53 mounted on the board 62. Note that other electronic circuits may also be mounted on the board 62, either in addition or as an alternative.

The MPU 51 is responsible for overall control of the camera 10. The ASIC 52 processes the image signal output from the imaging chip 100. In this embodiment, the ASIC 52 receives the image signal from the imaging chip 100 via the mounting board 120, the first connector 181, and the first flexible board 250.

The power supply unit 53 includes a battery attached to the camera 10 and a power supply circuit that supplies power stored in the battery to each part of the camera 10. In this embodiment, the power supply unit 53 supplies current to the imaging chip 100 via the second flexible substrate 260, the second connector 183, and the mounting substrate 120. Note that the power supply unit 53 may also be an example of an external device.

The ASIC 52 generates image data for display based on the image signal from the imaging chip 100. The ASIC 52 generates image data for display by performing, for example, image processing and compression processing on the image signal from the imaging chip.

The image data for display generated by the ASIC 52 is output to the display unit 88. The image data may be recorded on a recording medium attached to the camera body 30. The recording medium may be configured to be detachable from the camera body 30. The ASIC 52 may be an example of an external image processing device.

The display unit 88 is located in the negative z-axis direction of the board unit 60. The display unit 88 can be, for example, a liquid crystal panel. The display surface of the display unit 88 appears on the back of the camera body 30. The display unit 88 displays images based on display image data generated by the ASIC 52.

Figure 2 is a top view schematically illustrating an imaging unit 40 according to one embodiment. Figure 3 is a cross-sectional view schematically illustrating the A-A cross section of Figure 2. However, in Figure 3, in addition to the imaging unit 40 shown in solid lines, the bracket 150, first flexible substrate 250, and second flexible substrate 260 are shown in dashed lines.

The imaging chip 100 includes an imaging region 101 and a peripheral region 102. As shown in Figure 2, both the imaging region 101 and the peripheral region 102 are rectangular in plan view.

The imaging region 101 is formed in the central portion of the imaging chip 100. In the imaging region 101, multiple photoelectric conversion elements that photoelectrically convert subject light are arranged two-dimensionally, thereby forming the imaging surface of the imaging chip 100. Each pixel is composed of one or more photoelectric conversion elements.

The peripheral region 102 is located around the imaging region 101. The peripheral region 102 includes a processing circuit 104 that reads out and processes image signals obtained by photoelectric conversion in the photoelectric conversion elements. The processing circuit 104 includes an AD conversion circuit that converts the output image signals into digital signals. The processing circuit 104 also includes a transmission circuit 105 for transmitting the image signals.

The imaging chip 100 is mounted on the mounting substrate 120 using a COB (chip on board) method. The imaging chip 100 is fixed to the mounting substrate 120 by an adhesive 210. The adhesive 210 is, for example, a thermosetting adhesive. The other adhesives described below are also, for example, thermosetting adhesives.

The imaging chip 100 is electrically connected to the mounting substrate 120 via bonding wires 110. Image signals converted into digital signals by the AD conversion circuit of the imaging chip 100 are output to the mounting substrate 120 via the bonding wires 110. The imaging chip 100 may also be flip-chip mounted on the mounting substrate 120.

The mounting substrate 120 includes a first layer 121, a core layer 207, and a second layer 122. The first layer 121 includes a solder resist layer 201, a wiring layer 202, an insulating layer 203, a wiring layer 204, and an insulating layer 205. The second layer 122 includes an insulating layer 215, a wiring layer 214, an insulating layer 213, a wiring layer 212, and a solder resist layer 211. The mounting substrate 120 is a multilayer core substrate having a core layer 207 as a core layer.

On the mounting substrate 120, the following layers are arranged in the negative z-axis direction: solder resist layer 201, wiring layer 202, insulating layer 203, wiring layer 204, insulating layer 205, core layer 207, insulating layer 215, wiring layer 214, insulating layer 213, wiring layer 212, and solder resist layer 211.

Insulating layers 203, 205, 215, and 213 are, for example, resin layers. The thickness of each of insulating layers 203, etc. in the z-axis direction is, for example, 20 μm to 50 μm.

The wiring layers 202, 204, 214, and 212 include wiring patterns. Materials that can be used for the wiring layers 202 and the like include nickel-iron alloys (e.g., 42 alloy, 56 alloy), copper, aluminum, and the like. The thickness of each of the wiring patterns in the wiring layers 202 and the like is, for example, 10 μm to 50 μm.

The core layer 207 is formed from a metal. When the core layer 207 is formed from a metal, the material of the core layer 207 may be, for example, a nickel-iron alloy (e.g., 42 alloy, 56 alloy), copper, aluminum, etc. The thickness of the core layer 207 is thicker than the thickness of any of the wiring layers 202, etc. The thickness of the core layer 207 is thicker than the thickness of any of the insulating layers 203, etc. Specifically, the thickness of the core layer 207 is, for example, 0.1 mm to 0.8 mm.

The rigidity of the core layer 207 is higher than the rigidity of any of the wiring layers 202, etc. The rigidity of the core layer 207 may be higher than the rigidity of the first layer 121. The rigidity of the core layer 207 may be higher than the rigidity of the second layer 122.

The core layer 207 may be formed from resin. When the core layer 207 is formed from resin, it may be formed using, for example, FR4 or a material with a higher elastic modulus than FR4. When the core layer 207 is formed from resin, it is sandwiched between wiring layers in the z-axis direction. For example, when the core layer 207 is formed from resin, the solder resist layer 201, wiring layer 202, insulating layer 203, wiring layer 204, core layer 207, wiring layer 214, insulating layer 213, wiring layer 212, and solder resist layer 211 may be arranged in this order in the negative z-axis direction. When two additional wiring layers are arranged, an additional insulating layer in contact with wiring layer 204 and an additional wiring layer in contact with core layer 207 are arranged in this order in the negative z-axis direction between wiring layer 204 and core layer 207, and an additional wiring layer in contact with core layer 207 and an additional insulating layer in contact with wiring layer 214 are arranged in this order in the negative z-axis direction between core layer 207 and wiring layer 214.

As such, the mounting substrate 120 is a multilayer core substrate having a metal core or a resin core. The thickness of the mounting substrate 120 may be, for example, 0.3 mm to 1.0 mm.

At least a portion of the wiring layer 202 is used for a wiring pattern that receives image signals output from the imaging chip 100 via bonding wires 110. The wiring layer 202 includes bonding pads 240 to which the bonding wires 110 are connected.

The wiring patterns included in wiring layer 204 and wiring layer 214 can be used, for example, as ground lines, power lines, etc.

The imaging chip 100 is placed on the solder resist layer 201 and electrically connected to the bonding pad 240 by a bonding wire 110. The bonding pad 240 and the wiring layer 212 are electrically connected by a via 131 that penetrates the first layer 121 and the core layer 207. The via 131 is covered by an insulator 132. The image signal output from the imaging chip 100 is transmitted to the wiring layer 212 via the wiring layer 202 and the via 131.

Electronic components such as the first connector 181, the second connector 183, the bypass capacitor group 185, and the circuit group 187 are mounted on the solder resist layer 211. In other words, these electronic components are mounted on the second main surface 112 of the mounting substrate 120, which is opposite to the first main surface 111 on which the imaging chip 100 is mounted. Other electronic components, such as resistors, regulators, and transistors, may also be included on the solder resist layer 211.

These electronic components are electrically connected to the wiring layer 212 by lead members. The lead members are fixed to the wiring layer 212 with solder or the like. A portion of the wiring layer 212 is exposed to the outside through an opening formed in the solder resist layer 211, providing an electrode such as a land.

In particular, the first connector 181 in this embodiment is connected to the wiring layer 212, and image signals are transmitted from the transmission circuit 105 via the wiring layer 212. The first connector 181 in this embodiment is also connected to the first flexible substrate 250, and transmits the image signals to the ASIC 52 via the first flexible substrate 250.

The image signal transmitted to the first connector 181 may include an image signal transmitted at 1 GHz or higher. The first connector 181 is disposed on the second main surface 112 in a position opposite the transmission circuit 105 on the first main surface 111. In this way, the first connector 181 is disposed in a position that minimizes the linear distance between it and the transmission circuit 105, thereby minimizing the path of the image signal transmitted from the transmission circuit 105 and preventing the signal level of the image signal output at high speed from deteriorating within the mounting board 120.

In addition, the second connector 183 in this embodiment is connected to the wiring layer 212 and supplies current to the imaging chip 100 via the wiring layer 212. In addition, the second connector 183 in this embodiment is connected to the second flexible substrate 260 and receives current from the power supply unit 53 via the second flexible substrate 260. Note that no image signals are transmitted from the transmission circuit 105 to the second connector 183 in this embodiment.

The frame 140 is made of resin. The frame 140 is adhered to the solder resist layer 201 of the mounting substrate 120 by adhesive parts 220. In other words, the mounting substrate 120 is fixed to the frame 140.

The frame 140 may be constructed by inserting a metal body into resin. The metal body may be made of a nickel-iron alloy (e.g., 42 alloy, 56 alloy), copper, or aluminum. Using a lightweight material such as aluminum as the metal body material can reduce the weight of the frame 140. Using a material with a relatively high thermal conductivity such as copper as the metal body material can improve the heat dissipation characteristics of the frame 140.

The frame 140 has a first surface 141, a second surface 142, a third surface 143, a fourth surface 144, a fifth surface 145, and a sixth surface 146. The sixth surface 146 forms an opening 138. The sixth surface 146 forms the inner wall surface of the frame 140. The opening 138 is formed, for example, in the center of the xy plane. The imaging chip 100 mounted on the first main surface 111 of the mounting substrate 120 is located within the opening 138.

The first surface 141 is a surface that is bonded to the cover glass 160 by the adhesive portion 230. The first surface 141 is a surface that contacts the end of the sixth surface 146. The first surface 141 is formed along the outer edge of the sixth surface 146. The first surface 141 is a surface that is approximately parallel to the xy plane.

The second surface 142 is a surface that contacts the end of the first surface 141. The second surface 142 is a surface that is formed along the outer edge of the first surface 141. The second surface 142 has a surface that is approximately parallel to the yz plane and a surface that is approximately parallel to the xz plane.

The third surface 143 is a surface that contacts the end of the second surface 142. The third surface 143 is a surface that is approximately parallel to the xy plane and is also approximately parallel to the first surface 141.

The fourth surface 144 is a surface that contacts the end of the third surface 143. The fourth surface 144 is a surface that is formed along the outer edge of the third surface 143. The fourth surface 144 has a surface that is approximately parallel to the yz plane and a surface that is approximately parallel to the xz plane.

The fifth surface 145 is a surface that contacts the end of the fourth surface 144. The fifth surface 145 is a surface that is formed along the outer edge of the fourth surface 144. The fifth surface 145 is a surface that is approximately parallel to the xy plane. The fifth surface 145 is a surface that is approximately parallel to the first surface 141 and the third surface 143. The fifth surface 145 is a surface that is bonded to the solder resist layer 201 of the mounting board 120 by the adhesive portion 220. The fifth surface 145 faces the adhesive portion 220. The fifth surface 145 is a surface that contacts the end of the sixth surface 146. The fifth surface 145 is formed along the outer edge of the sixth surface 146.

The frame 140 has a stepped portion formed by a first surface 141, a second surface 142, and a third surface 143. The frame 140 has mounting holes 148 as mounting portions. The frame 140 has, for example, three mounting holes 148. All three mounting holes 148 are holes that penetrate from the third surface 143 to the fifth surface 145. All three mounting holes 148 are used to mount the imaging unit 40 to another structure, such as the housing 31 of the camera body 30.

The frame 140 is fixed to the bracket 150, for example, by fastening it with screws 149 through three mounting holes 148. The bracket 150 is fixed to the housing 31 of the camera body 30, for example, by fastening it with screws. Thus, the imaging unit 40 is fixed to the housing 31 of the camera body 30.

If the frame 140 and bracket 150 are fastened to each other using the mounting holes 148 with, for example, metal screws 149, a heat transfer path can be formed to dissipate heat generated when the imaging chip 100 is operating via the screws 149 toward the housing 31.

The frame 140 has positioning holes 147. The frame 140 has, for example, two positioning holes 147. Both of the positioning holes 147 are holes that penetrate from the third surface 143 to the fifth surface 145. Of the two positioning holes 147, one is formed as a fitting hole, and the other is formed as an elongated hole.

The frame 140 is positioned relative to the bracket 150 using two positioning holes 147. For example, two positioning pins provided on the bracket 150 are inserted into the two positioning holes 147, thereby positioning the frame 140 and bracket 150. The frame 140 is fixed in a position relative to the bracket 150. Therefore, the imaging unit 40 is fixed in a position relative to the housing 31. Note that the frame 140 and bracket 150 may be fixed to a structure other than the housing 31.

The imaging unit 40 may be fixed to the housing 31 without using the bracket 150. The imaging unit 40 may be fixed to the housing 31 by, for example, fastening it with screws through the three mounting holes 148.

The cover glass 160 is made of, for example, borosilicate glass, quartz glass, alkali-free glass, heat-resistant glass, or quartz. The cover glass 160 is translucent. The thickness of the cover glass 160 is, for example, 0.5 mm to 0.8 mm.

The cover glass 160 is used to seal the imaging chip 100 housed within the opening 138 of the frame 140. More specifically, the cover glass 160 is fixed to the frame 140 so as to cover the opening 138 of the frame 140. The cover glass 160 is fixed to the frame 140 after the imaging chip 100, bonding wires 110, and frame 140 have been mounted on the mounting substrate 120. The cover glass 160 is adhered to the frame 140 by an adhesive 230. Because the cover glass 160 is translucent, the adhesive 230 may be a photo-curable adhesive.

The cover glass 160, together with the frame 140 and mounting substrate 120, seals the space within the opening 138. Therefore, the imaging chip 100 located within the opening 138 is disposed in a space sealed by the mounting substrate 120, frame 140, and cover glass 160. This makes the imaging chip 100 less susceptible to the effects of the external environment. For example, the imaging chip 100 is less susceptible to the effects of moisture present outside the space. This makes it possible to prevent deterioration of the imaging chip 100.

Figure 4 is a bottom view schematically illustrating the imaging unit 40 according to one embodiment. Figure 5 is a bottom view schematically illustrating the imaging unit 40 connected to the ASIC 52 and power supply unit 53 via the first flexible substrate 250 and the second flexible substrate 260 according to one embodiment.

In Figures 4 and 5, the configuration on the second main surface 112 side of the mounting substrate 120 is shown with solid lines, and on the first main surface 111 side, the imaging chip 100, the processing circuit 104 in the peripheral region 102 of the imaging chip 100, and the transmission circuit 105 included in the processing circuit 104 are each shown with dashed lines. The bypass capacitor group 185 and circuit group 187 are also shown simplified and are each indicated by hatched areas. The path and flow direction of current from the (+) pole within the mounting substrate 120 are indicated with solid black arrows, and the path and flow direction of the image signal are indicated with hollow arrows. This also applies to Figures 7 and 8, which will be described below, and redundant explanations will be omitted.

When mounting one connector on the back surface of a mounting board, it is preferable to position the connector approximately in the center of the back surface, taking into consideration that when multiple harnesses such as flexible boards are connected, the tension applied to each harness is uniform. Furthermore, when mounting an electrical circuit on the back surface of the mounting board, it is preferable that the wiring layer connected to the imaging chip via electrode pads and vias is exposed on the outer periphery of the back surface of the mounting board, and that the electrical circuit is located near this wiring layer. In such cases, the connector needs to be positioned in the center of the back surface of the mounting board, where there is space available for mounting, rather than on the outer periphery where there is little space remaining.

When a single connector is placed in the center of the back surface of the mounting board, the image signal output from the transmission circuit built into the imaging chip is transmitted through the wiring pattern within the board in the surface direction of the board and reaches the connector. In such a case, the resistance loss and dielectric loss of the image signal in the wiring pattern increase, causing a deterioration in the signal level of the image signal. Furthermore, when a single connector is placed in the center of the back surface of the mounting board, the distance between the connector and the external image processing device is longer than when the connector is placed at the edge of the back surface. In other words, the harness, such as a flexible board, connecting the connector to the external image processing device becomes relatively long. As a result, the resistance loss and dielectric loss of the image signal flowing through the harness increase, causing a deterioration in the signal level of the image signal.

In the imaging unit 40 of this embodiment, as described above, the first connector 181 and the second connector 183 are mounted on the second main surface 112 of the mounting substrate 120. Here, the bypass capacitor group 185 described above is used to power the imaging chip 100, and in order to enhance the functionality of the bypass capacitor group 185, it is preferable to shorten the distance between the bypass capacitor group 185 and the imaging chip 100. In this embodiment, the bypass capacitor group 185 is disposed near the wiring layer 212 that is exposed to the outside through an opening formed in the solder resist layer 211.

In addition, in this embodiment, the bypass capacitor group 185 is arranged on the outer periphery of the second main surface 112 of the mounting substrate 120. More specifically, the bypass capacitor group 185 is mounted in a ring shape on the outer periphery of the second main surface 112 of the mounting substrate 120. Note that in this embodiment, the outline of the region of the bypass capacitor group 185 shown with diagonal lines in FIG. 4 is rectangular in plan view, following the shapes of the mounting substrate 120 and the imaging chip 100, which are rectangular in plan view.

In this embodiment, the first connector 181 is arranged inside the annular bypass capacitor group 185. The second connector 183 is also arranged inside the annular bypass capacitor group 185. This arrangement allows the size of the mounting board 120 to be smaller than when each connector is arranged outside the annular bypass capacitor group 185. It can also be said that the first connector 181 and the second connector 183 are arranged inside the four sides of the rectangular area of the bypass capacitor group 185 in a plan view.

As mentioned above, in this embodiment, the image signal transmitted to the first connector 181 may include an image signal transmitted at 1 GHz or higher. This signal is, for example, a differential signal called SLVS or LVDS. The image signal output at high speed from the transmission circuit 105 of the imaging chip 100 flows through a differential signal pattern wired on the wiring layer 212 of the mounting substrate 120, passes through the first connector 181 and the first flexible substrate 250, and is transmitted to the ASIC 52.

As described above, in this embodiment, the first connector 181 is disposed on the second principal surface 112 at a position opposite the transmission circuit 105 on the first principal surface 111. In Figure 4 and other figures, the first connector 181 (solid line) is shown overlapping the transmission circuit 105 (dashed line). With this arrangement, both the image signal path within the differential signal pattern (shown by the hollow arrows in Figure 4) and the image signal path within the first flexible substrate 250 (shown by the hollow arrows in Figure 5) can be shortened compared to when a single connector is disposed in the center of the back surface of the mounting substrate. Therefore, by mounting each of the first connector 181 and second connector 183 on the mounting substrate 120, the imaging unit 40 of this embodiment can contribute to making the camera 10 smaller and thinner.

The resistive loss and dielectric loss of image signals transmitted at 1 GHz or higher increase at a significantly greater rate depending on the length of the transmission path than image signals transmitted at lower frequencies. In other words, image signals transmitted at 1 GHz or higher experience a significantly greater attenuation rate within the transmission path.

With the imaging unit 40 of this embodiment, the arrangement shown in Figure 4 and other figures can prevent image signals transmitted at frequencies above 1 GHz from being attenuated within the transmission path, compared to when a single connector is located in the center of the back surface of the mounting board.

Furthermore, if one connector is placed in the center of the back surface of the mounting board, the differential signal pattern within the mounting board will be relatively long, which necessitates the use of a substrate made of a material suitable for transmitting image signals at high speed, and this substrate is relatively expensive. In contrast, with the imaging unit 40 of this embodiment, the differential signal pattern within the mounting board 120 can be made relatively short, which allows the use of a relatively inexpensive substrate for the mounting board 120, thereby reducing manufacturing costs.

Image sensors tend to consume more power as the pixel count increases and image readout speeds increase, and this increases even more in the case of stacked types that incorporate large-scale circuits such as memory. When a single connector is used for multiple purposes, such as power supply, control, and image transmission, the connector's multiple pins are used for each purpose, which limits the amount of current that can be supplied to the image sensor via that connector. Furthermore, when a connector and harness suitable for transmitting image signals at high speeds are used, the efficiency of supplying large currents to the image sensor may be lower than when a general-purpose connector and harness are used.

In contrast, with an imaging unit 40 equipped with two connectors, one connector can be specialized for one purpose and the other for another, allowing each connector to be used according to its purpose. For example, the imaging unit 40 can use a first connector 181 suitable for transmitting image signals to the ASIC 52 at high speed, and a second connector 183 suitable for supplying a large current supplied from the power supply unit 53 to the imaging chip 100. In this case, the imaging unit 40 can apply a first flexible substrate 250 suitable for transmitting image signals at high speed to the first connector 181, and a second flexible substrate 260 suitable for supplying a large current to the second connector 183.

In addition, an imaging unit 40 with two connectors may assign multiple uses to one connector, while specializing the other connector for a specific use. For example, the imaging unit 40 may assign the first connector 181 two uses, transmitting image signals and supplying current, and use the second connector 183 exclusively for supplying current. In this case, the second connector 183 may be suitable for supplying large currents. In addition, an imaging unit 40 with two connectors may assign multiple uses to each connector. For example, the imaging unit 40 may assign both the first connector 181 and the second connector 183 two uses, transmitting image signals and supplying current.

In addition, in this embodiment, the first connector 181 is arranged at one end of the second main surface 112 of the mounting board 120, and the second connector 183 is arranged on the opposite side of the one end on the second main surface 112 of the mounting board 120. More specifically, the first connector 181 and the second connector 183 are arranged on opposite sides of the circuit group 187. In this case, it can also be said that the second connector 183 is arranged in a position point-symmetrical to the first connector 181 with respect to the center of the mounting board 120.

With this arrangement, when the ASIC 52 and power supply unit 53 are located on opposite sides of the imaging unit 40 in a plan view, it is possible to shorten both the distance from the first connector 181 to the ASIC 52 and the distance from the second connector 183 to the power supply unit 53. As a result, the second flexible substrate 260 connecting the power supply unit 53 and the second connector 183 can be made shorter than when one connector is located in the center of the back surface of the mounting board, preventing voltage drops on the second flexible substrate 260 and stabilizing the voltage supplied to the imaging chip 100.

Furthermore, with this arrangement, the first connector 181 and the second connector 183 are arranged point-symmetrically with respect to the center of the mounting board 120, so that even when the first flexible board 250 and the second flexible board 260 are connected to the first connector 181 and the second connector 183, respectively, the tension applied to the imaging unit 40 can be made uniform. This allows for stable operation when the imaging unit 40 is operated for functions such as image stabilization, for example, and is particularly effective when the camera 10 is used as a VR camera or the like.

Figure 6 is a schematic enlarged view of region (A) shown in Figure 5. In this embodiment, the first flexible substrate 250 may be a microstrip wiring. The first flexible substrate 250 in this embodiment is formed by a signal line 251, a ground line 253, and a dielectric layer 255 located between the signal line 251 and the ground line 253. Note that in Figure 6, the signal line 251 is indicated by a shaded area, and the ground line 253 is indicated by a dotted area.

As shown in Figure 6, the first flexible substrate 250 of microstrip wiring may have a mesh-structured ground line 253 to increase the width of the signal line 251 while maintaining a matched characteristic impedance and thereby suppress signal loss. This allows the first flexible substrate 250 to suppress degradation of the signal level of the transmitted image signal, which is particularly effective when transmitting image signals at high speeds. Furthermore, it has been experimentally found that this effect is particularly pronounced when the mesh-structured ground line 253 is arranged to occupy 20% of the total area of one surface of the dielectric layer 255. One example of the material for the ground line 253 is copper.

Furthermore, by making the ground wire 253 of the first flexible substrate 250 a mesh structure, the first flexible substrate 250 can be made soft, which is particularly effective when the camera 10 is used as a VR camera or the like. The characteristic impedance may be, for example, 100 Ω. The camera 10 can achieve the same effect even if a thin coaxial cable is used instead of the first flexible substrate 250.

Furthermore, as shown in FIG. 6, the first flexible substrate 250 of the microstrip wiring may have ground lines 253 arranged diagonally relative to the signal lines 251 extending parallel to the extension direction of the first flexible substrate 250. For example, the ground lines 253 may extend at an angle of approximately 45 degrees relative to the extension direction of the signal lines 251. This configuration makes it possible to average the area ratio of the ground lines 253 facing each of the multiple signal lines 251 across the dielectric layer 255. Furthermore, although not shown, the above effect can also be achieved by using a strip wiring structure in which the signal lines 251 are sandwiched between the above-mentioned mesh-structured ground lines 253 and upper and lower layers.

Figure 7 is a bottom view schematically illustrating the state in which the imaging unit 41 is connected to the ASIC 52 and power supply unit 53 via the first flexible substrate 250 and the second flexible substrate 260 according to one embodiment. In this embodiment, the same components as those in the embodiment described using Figures 1 to 6 are assigned the same reference numerals, and duplicated descriptions will be omitted. The same applies to the descriptions of subsequent embodiments.

In this embodiment, as in the embodiment described using Figures 1 to 6, a first connector 181 and a second connector 183 are mounted on the second main surface 112 of the mounting substrate 120, and both connectors are positioned inside the annular group of bypass capacitors 185. Also, as in the embodiment described using Figures 1 to 6, the first connector 181 is positioned at one end of the second main surface 112 of the mounting substrate 120, and the second connector 184 is positioned point-symmetrically to the first connector 181 with respect to the center of the mounting substrate 120.

This embodiment differs from the embodiment described using Figures 1 to 6 in that the first connector 181 and the second connector 184 are not located on opposing sides of the circuit group 187. The second connector 184 is located adjacent to the circuit group 187 in the negative y-axis direction. The imaging unit 41 according to this embodiment also has the same effects as the embodiment described using Figures 1 to 6.

Figure 8 is a bottom view schematically illustrating the state in which the imaging unit 42 is connected to the ASIC 52 and power supply unit 53 via the first flexible substrate 257 and the second flexible substrate 267 according to one embodiment. In this embodiment, as in the embodiment described using Figures 1 to 6, the first connector 182 and the second connector 186 are mounted on the second main surface 112 of the mounting substrate 120, and both connectors are positioned inside the annular bypass capacitor group 185. Also, as in the embodiment described using Figures 1 to 6, the first connector 182 is positioned on one end side of the second main surface 112 of the mounting substrate 120.

This embodiment differs from the embodiment described using Figures 1 to 6 in that the first connector 182 and the second connector 186 are not arranged on opposing sides of the circuit group 187. The second connector 186 is arranged adjacent to the first connector 182 in the negative x-axis direction of the circuit group 187. Furthermore, in this embodiment, the number of pins in each of the first connector 182 and the second connector 186 is smaller than in the embodiment described using Figures 1 to 6. The imaging unit 42 according to this embodiment also has the same effects as the embodiment described using Figures 1 to 6.

Figure 9 is a side view schematically illustrating a portion of a first flexible substrate 270 according to one embodiment. Unlike the first flexible substrate 250 according to the embodiment described using Figures 1 to 6, the first flexible substrate 270 according to this embodiment is a coplanar wiring. The first flexible substrate 270 according to this embodiment is formed by a signal line 271, a ground line 273, and a dielectric layer 275 adjacent to each of the signal line 271 and the ground line 273. The imaging unit 42 according to this embodiment also has the same effects as the embodiment described using Figures 1 to 6.

In the above embodiments, the camera 10 including the lens unit 20 and camera body 30 has been described as an example of an imaging device. However, an imaging device does not have to include the lens unit 20. For example, the camera body 30 is an example of an imaging device. Furthermore, the concept of an imaging device includes not only imaging devices with interchangeable lenses such as single-lens reflex cameras, but also imaging devices with non-interchangeable lenses.

Note that the ASIC 52, power supply unit 53, etc. may also be referred to as the imaging unit 40. Additionally or alternatively, the first flexible substrate 250, second flexible substrate 260, etc. may also be referred to as the imaging unit 40.

The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," or the like, and it should be noted that processes can be performed in any order, unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that it is necessary to perform the processes in that order.

10 Camera, 20 Lens unit, 22 Optical axis, 30 Camera body, 31 Housing, 40, 41, 42 Imaging unit, 100 Imaging chip, 101 Imaging area, 102 Peripheral area, 104 Processing circuit, 105 Transmission circuit, 110 Bonding wire, 120 Mounting substrate, 111 First main surface, 112 Second main surface, 121 First layer, 122 Second layer, 131 Via, 132 Insulator, 138 Opening, 181, 182 First connector, 183, 184, 186 Second connector, 185 Bypass capacitor group, 187 Circuit group, 201, 211 Solder resist layer, 202, 204, 212, 214 Wiring layer, 203, 205, 213, 215 Insulating layer, 207 Core layer, 210, 220, 230 Adhesive portion, 240 Bonding pad, 140 Frame, 141 First surface, 142 Second surface, 143 Third surface, 144 Fourth surface, 145 Fifth surface, 146 Sixth surface, 147 Positioning hole, 148 Mounting hole, 149 Screw, 150 Bracket, 160 Cover glass, 250, 257, 270 First flexible board, 251, 271 Signal line, 253, 273 Ground line, 255, 275 Dielectric layer, 260, 267 Second flexible board, 60 Board unit, 62 Board, 51 MPU, 52 ASIC, 53 Power supply unit, 88 Display unit

Claims (29)

an imaging chip that is a rectangular semiconductor chip and captures an image of a subject;
an imaging unit comprising: a mounting substrate having a first surface on which the imaging chip is mounted; a surface opposite to the first surface, the first connector having a shape that extends in the short direction of the imaging chip more than in the long direction of the imaging chip and for outputting an image signal of a subject imaged by the imaging chip; a second connector having a shape that extends in the short direction of the imaging chip more than in the long direction of the imaging chip and for supplying current to the imaging chip; and a second surface on which electronic components are mounted that are arranged between the first connector and the second connector in the long direction of the imaging chip. 2. The imaging unit according to claim 1,
the imaging chip has an imaging region in which a plurality of photoelectric conversion elements that convert light into electric charges are arranged, and a peripheral region that is arranged outside the imaging region and includes a transmission circuit for transmitting the image signal;
the first connector is disposed on the second surface at a position facing the transmission circuit on the first surface ;
Imaging unit. 3. The imaging unit according to claim 1,
a first bypass capacitor for a power supply of the imaging chip is mounted on the second surface of the mounting board;
the first connector is disposed between the electronic component and the first bypass capacitor in the longitudinal direction of the imaging chip ;
Imaging unit. 4. The imaging unit according to claim 3,
a second bypass capacitor for a power supply of the imaging chip is mounted on the second surface of the mounting board;
the second connector is disposed between the electronic component and the second bypass capacitor in the longitudinal direction of the imaging chip.
Imaging unit. 3. The imaging unit according to claim 1,
a group of bypass capacitors electrically connected to the imaging chip are mounted on the mounting board on the second surface,
the bypass capacitor group is arranged to surround the first connector;
Imaging unit. 6. The imaging unit according to claim 5,
the group of bypass capacitors is arranged to surround the second connector;
Imaging unit. an imaging chip that is a rectangular semiconductor chip and captures an image of a subject;
a mounting substrate having a first surface on which the imaging chip is mounted, and a second surface on the opposite side to the first surface, on which a first connector, having a shape extending in a lateral direction of the imaging chip rather than in a longitudinal direction of the imaging chip, for outputting an image signal of a subject imaged by the imaging chip, a second connector, having a shape extending in a lateral direction of the imaging chip rather than in a longitudinal direction of the imaging chip, for supplying a current to the imaging chip, and a group of bypass capacitors electrically connected to the imaging chip and arranged so as to surround the first connector and the second connector, are mounted;
An imaging unit comprising: The imaging unit according to any one of claims 1 to 7,
the first connector is disposed on one end side of the second surface of the mounting board,
the second connector is disposed on the second surface of the mounting board, on the opposite side to the one end;
Imaging unit. The imaging unit according to any one of claims 1 to 8,
the second connector is disposed at a position point-symmetrical to the first connector with respect to the center of the mounting board;
Imaging unit. The imaging unit according to any one of claims 1 to 9,
a first flexible substrate is connected to the first connector to transmit an image signal to an external image processing device;
Imaging unit. The imaging unit according to claim 10,
the first flexible substrate is a microstrip wiring or a strip wiring, and the ground line has a mesh structure in order to increase the width of the signal line while maintaining a matched characteristic impedance and suppress signal loss;
Imaging unit. The imaging unit according to claim 11,
The first flexible substrate is a coplanar wiring .
Imaging unit. The imaging unit according to any one of claims 1 to 12,
The image signal transmitted to the first connector includes an image signal transmitted at 1 GHz or higher.
Imaging unit. 3. The imaging unit according to claim 2,
a second flexible substrate is connected to the second connector to supply current to the imaging chip;
Imaging unit. 15. The imaging unit according to claim 14,
No image signal is transmitted from the transmission circuit to the second connector.
Imaging unit. The imaging unit according to any one of claims 1 to 15,
The imaging unit includes a frame disposed on the mounting substrate so as to surround the imaging chip. 17. The imaging unit according to claim 16,
The frame has a mounting portion for mounting another structure.
Imaging unit. 18. The imaging unit according to claim 16 or 17,
The frame is formed from a resin.
Imaging unit. 18. The imaging unit according to claim 16 or 17,
The frame is made of metal.
Imaging unit. 18. The imaging unit according to claim 16 or 17,
The frame is formed of resin and metal.
Imaging unit. The imaging unit according to any one of claims 16 to 20,
a light-transmitting substrate fixed to the frame;
the imaging chip is disposed in a space formed by the mounting substrate, the frame, and the light-transmitting substrate;
Imaging unit. 22. The imaging unit according to claim 1,
the imaging chip is fixed to the mounting substrate by an adhesive;
Imaging unit. 23. The imaging unit according to claim 22,
The adhesive is a thermosetting adhesive.
Imaging unit. The imaging unit according to any one of claims 1 to 23,
The mounting substrate is a multilayer core substrate having a core layer formed of a metal.
Imaging unit. The imaging unit according to any one of claims 1 to 23,
The mounting substrate is a multilayer core substrate having a core layer formed of a resin.
Imaging unit. The imaging unit according to any one of claims 1 to 6,
the electronic component includes at least one of a resistor, a regulator, and a transistor;
Imaging unit. An imaging device comprising the imaging unit according to any one of claims 1 to 26 . 28. The imaging device according to claim 27,
The imaging chip receives light emitted from a lens unit having an optical system.
Imaging device. 29. The imaging device according to claim 28,
An imaging device comprising the lens unit.