JP7740323B2 - gaming machines - Google Patents

Description

The present invention relates to an amusement machine.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls given to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section (see, for example, Patent Document 1).

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Japanese Patent Application Laid-Open No. 2009-261415

Here, in gaming machines such as those exemplified above, it is necessary to appropriately manage the gaming machines, and there is still room for improvement in this regard.

The present invention has been made in consideration of the circumstances exemplified above, and has as its object to provide a gaming machine that allows for suitable management of the gaming machine .

In order to solve the above problem, the invention of claim 1 comprises a history storage execution means for storing game history information corresponding to a predetermined event that occurs when a game is executed, in a history storage means;
information deriving means for deriving behavior information corresponding to a game result by utilizing the history information stored in the history storage means;
a behavior information storage means for storing the behavior information derived by the information derivation means;
a mode information display control means for controlling the display of the mode information stored in the mode information storage means on the information display means;
a predetermined correspondence display control means for controlling the information display means to display a predetermined correspondence display before a new display corresponding to the aspect information is started, based on the occurrence of a predetermined display trigger;
a setting means for setting a set value corresponding to the advantage of a player;
a situation generating means for generating a setting possible situation in which the setting means can set the setting value;
Equipped with
the aspect information storage means includes a plurality of specific storage areas so as to be able to store each of the plurality of aspect information,
the aspect information display control means controls the information display means to sequentially execute displays corresponding to the plurality of aspect information stored in the plurality of specific storage areas in accordance with a predetermined display order, and when the information display means is caused to execute displays corresponding to the aspect information after the predetermined corresponding displays have been executed by the information display means, the information display means starts with a display corresponding to the aspect information corresponding to the first order in the predetermined display order,
When the setting possible state is reached, control can be executed to enable confirmation of the behavior information derived using the history information at that time,
The gaming machine is equipped with a control means for executing various processes,
The control means
an area processing execution means for executing an area processing which is a process using a program stored in a storage area within a predetermined address range in the program storage means;
an out-of-area processing execution means for executing out-of-area processing, which is processing using a program stored in a storage area in an address range outside the predetermined address range in the program storage means;
Equipped with
This gaming machine is
an intra-area corresponding storage area into which information can be written and read when the intra-area process is executed, and into which information can be read but not written when the extra-area process is executed;
an outside-area corresponding storage area into which information can be written and read when the outside-area processing is executed, and into which information can be read but not written when the inside-area processing is executed;
Equipped with
a configuration in which, in a situation where a display corresponding to the mode information is being performed on the information display means, a process for making the setting value set as an object to be used visible can be executed;
The in-area processing execution means is characterized by having a means that can execute processing to make the setting value set as the target for use visually confirmable as in-area processing when the processing at the start of the supply of operating power has been completed and game play can begin.

According to the present invention, it is possible to appropriately manage gaming machines .

1 is a perspective view showing a pachinko machine according to a first embodiment. FIG. 1 is an exploded perspective view showing the main components of a pachinko machine. FIG. 2 is a front view showing the configuration of the game board. FIG. 10 is an explanatory diagram for explaining the configuration for discharging game balls that have flowed down the game area. FIG. 2 is a front view of the main control device. FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. This is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. FIG. 4 is an explanatory diagram for explaining various tables stored in the main ROM. 10 is a flowchart showing main processing executed by a main CPU. 10 is a flowchart showing a setting value update process executed by the main CPU. 10 is a flowchart showing a timer interrupt process executed by a main CPU. 10 is a flowchart showing a special chart special power control process executed by the main CPU. This is a flowchart showing the special chart change start processing executed by the main CPU. This is an explanatory diagram to explain the configuration in which the detection results of the ball entry detection sensor are input to the main CPU. This is a flowchart showing the ball entry detection process executed by the main CPU. A block diagram for explaining the electrical configuration of a dispensing control device and various devices that communicate with the dispensing control device. 10 is a flowchart showing a timer interrupt process executed by the dispensing CPU. FIG. 2 is a block diagram illustrating an electrical configuration of a management IC. FIG. 10 is an explanatory diagram illustrating the configuration of an input port of a management side I/F. FIG. 2 is an explanatory diagram for explaining the configuration of a correspondence relationship memory; FIG. 2 is an explanatory diagram illustrating the configuration of a history memory. 10 is a flowchart showing a recognition process executed by a main CPU. 10 is a flowchart showing a management process executed by a management-side CPU. 10A to 10D are time charts showing how information on the correspondence between the first to fifteenth buffers and the signal types is stored in the correspondence memory. 10 is a flowchart showing a management output process executed by the main CPU. 10 is a flowchart showing a history setting process executed by a management-side CPU. 10A to 10E are time charts showing how history information is stored in a history memory. 10 is a flowchart showing a process of outputting a set value update signal executed by a main CPU. 10 is a flowchart showing a setting update recognition process executed by a management CPU. 10 is a flowchart showing a display output process executed by a management-side CPU. 10 is a flowchart showing a display process executed by a management-side CPU. 10A is a flowchart showing a data output process executed by a main CPU, and FIG. 10B is a flowchart showing an external output process executed by a control CPU. FIG. 10 is an explanatory diagram for explaining various tables stored in a main ROM in the second embodiment. FIG. 11 is an explanatory diagram for explaining the configuration of a separate storage memory in the third embodiment. 10 is a flowchart showing a setting update recognition process executed by a management CPU. 10 is a flowchart showing a process of monitoring a repeated change executed by a management CPU; 13 is a flowchart showing a repeated change monitoring process executed by a main CPU in the fourth embodiment. 13 is a flowchart showing a setting update recognition process executed by a management-side CPU in the fifth embodiment. FIG. 20 is an explanatory diagram for explaining the configuration of a history memory in the sixth embodiment. 10 is a flowchart showing a history setting process executed by a management-side CPU. 10 is a flowchart showing a setting update recognition process executed by a management CPU. FIG. 20 is an explanatory diagram illustrating the configuration of a history memory in the seventh embodiment. 10 is a flowchart showing a setting update recognition process executed by a management CPU. FIG. 20 is an explanatory diagram for explaining the configuration of a history memory in the eighth embodiment. 10 is a flowchart showing a setting update recognition process executed by a management CPU. 10 is a flowchart showing a history setting process executed by a management-side CPU. 10 is a flowchart showing a display output process executed by a management-side CPU. FIG. 23 is an explanatory diagram illustrating the configuration of an input port of a management side I/F in the ninth embodiment. 10 is a flowchart showing a recognition process executed by a main CPU. 10 is a flowchart showing a management process executed by a management-side CPU. 10A to 10H are time charts showing how information on the correspondence between the first to twelfth buffers and the signal types is stored in the correspondence memory. A block diagram to explain the configuration of the signal path that transmits the detection results of each ball entry detection sensor to the main CPU and management IC in the 10th embodiment. A front view of the main control device in the eleventh embodiment. FIG. 10 is a block diagram for explaining the electrical configuration for performing various displays in the first to fourth notification display devices based on the control of the MPU. 10 is a flowchart showing a display process executed by a management-side CPU. 10 is a flowchart showing a setting value update process executed by the main CPU. (a) An explanatory diagram for explaining the display mode of the first to fourth notification display devices when the results of game history management are displayed, and (b) an explanatory diagram for explaining the display mode of the first to fourth notification display devices when the setting state of the pachinko machine is changed. 10A to 10H are time charts showing how the first to fourth notification display devices are set to display states. (a) An explanatory diagram for explaining the configuration of the first alarm display device in the twelfth embodiment, and (b) an explanatory diagram for explaining the configuration of the second alarm display device. This is an explanatory diagram for explaining the display contents of the first alarm display device and the second alarm display device when the first to fourth alarm display devices display the results of game history management and when they display that the setting state of the pachinko machine is in a changeable state where it is possible to change it. 10 is a flowchart showing a setting value update process executed by the main CPU. FIG. 23 is an explanatory diagram for explaining the configuration of an abnormality display area in the thirteenth embodiment. 10 is a flowchart showing an abnormality setting process executed by the main CPU. 10 is a flowchart showing an abnormality display process executed by the main CPU. 20 is a flowchart showing the management output process executed by the main CPU in the fourteenth embodiment. 10 is a flowchart showing main processing executed by a main CPU in another embodiment. FIG. 22 is an explanatory diagram for explaining the setting mode of programs and data in the main ROM in the fifteenth embodiment. FIG. 10 is an explanatory diagram for explaining the setting manner of each area in the main RAM. 10 is a flowchart showing a timer interrupt process executed by a main CPU. 10 is a flowchart showing a management process executed by a main CPU. 10 is a flowchart showing a management execution process executed by a main CPU. FIG. 10 is an explanatory diagram illustrating various areas of a work area for non-specific control used to manage game history. 10 is a flowchart showing a check process executed by a main CPU. This is a flowchart showing the normal goal entry management processing executed by the main CPU. 10 is a flowchart showing a result calculation process executed by the main CPU. 10 is a flowchart showing a display process executed by the main CPU. 20 is a flowchart showing a management process executed by a main CPU in the sixteenth embodiment. 20 is a flowchart showing a management execution process executed by a main CPU in the seventeenth embodiment. 20 is a flowchart showing the management execution process executed by the main CPU in the eighteenth embodiment. 20 is a flowchart showing a management execution process executed by a main CPU in the nineteenth embodiment. 13 is a flowchart showing the management process executed by the main CPU in the twentieth embodiment. 10 is a flowchart showing a management execution process executed by a main CPU. FIG. 21 is an explanatory diagram for explaining the electrical configuration in the twenty-first embodiment. 22 is a flowchart showing a main process executed by a main CPU in the 22nd embodiment. 10 is a flowchart showing a setting value update process executed by the main CPU. 10 is a flowchart showing a timer interrupt process executed by a main CPU. 10 is a flowchart showing a setting confirmation process executed by the main CPU. 10 is a flowchart showing a RAM monitoring process executed by the main CPU. 10 is a flowchart showing main processing executed by a main CPU in another embodiment. 10 is a flowchart showing a setting value update process executed by the main CPU in another embodiment. 23 is a flowchart showing a main process executed by a main CPU in the 23rd embodiment. 24 is a flowchart showing a RAM monitoring process executed by the main CPU in the 24th embodiment. 25 is a flowchart showing a RAM monitoring process executed by the main CPU in the 25th embodiment. 10 is a flowchart showing a management execution process executed by a main CPU. 10 is a flowchart showing another monitoring process executed by the main CPU. 26 is a flowchart showing the management process executed by the main CPU in the 26th embodiment. 27 is a flowchart showing the management process executed by the main CPU in the 27th embodiment. 28 is a flowchart showing the management process executed by the main CPU in the 28th embodiment. 29 is a flowchart showing the management process executed by the main CPU in the 29th embodiment. 13 is a flowchart showing a main process executed by the main CPU in the 30th embodiment. 10 is a flowchart showing a power outage information storage process executed by a main CPU. 1A is a block diagram for explaining the configuration of an MPU, and FIG. 1B is a time chart showing how a reset signal is output by a reset signal output unit. 10 is a flowchart showing a timer interrupt process executed by a main CPU. 10 is a flowchart showing a setting monitoring process executed by a main CPU. 10 is a flowchart showing a management process executed by a main CPU. 10 is a flowchart showing a management execution process executed by a main CPU. 10 is a flowchart showing another monitoring process executed by the main CPU. 31 is a flowchart showing a main process executed by a main CPU in the thirty-first embodiment. 10 is a flowchart showing a clearing process executed by the main CPU in the event of an abnormality. 10 is a flowchart showing a clearing process for non-specific control executed by the main CPU. 32 is a flowchart showing a power outage information storage process executed by the main CPU in the 32nd embodiment. 10 is a flowchart showing a checksum monitoring process executed by the main CPU. 10 is a flowchart showing a clearing process for non-specific control executed by the main CPU. 33 is a flowchart showing a main process executed by the main CPU in the thirty-third embodiment. 10 is a flowchart showing a setting confirmation process executed by the main CPU. 10 is a flowchart showing a setting value update process executed by the main CPU. 10 is a flowchart showing a first timer interrupt process executed by the main CPU. 10 is a flowchart showing a setting monitoring process executed by a main CPU. FIG. 10 is a block diagram for explaining a configuration for controlling the display of various display circuits by a main CPU. FIG. 10A is an explanatory diagram for explaining various buffers provided in a work area for specific control, and FIG. 10B is an explanatory diagram for explaining various memory areas provided in a work area for non-specific control. FIG. 2 is an explanatory diagram for explaining the electrical configuration of a display IC. (a) to (g) are time charts showing how type data and display data are sent from the main CPU to the display IC and how the display data sent from the display IC is received by the first display circuit or the second display circuit. 10 is a flowchart showing a second timer interrupt process executed by the main CPU. (a) An explanatory diagram for explaining the display contents of the first to fourth notification display devices when the setting value is updated, and (b) an explanatory diagram for explaining the display contents of the first to fourth notification display devices when the setting value is confirmed. 34 is a flowchart showing a setting value update process executed by the main CPU in the thirty-fourth embodiment. FIG. 23 is an explanatory diagram for explaining the electrical configuration of a calculation result storage area in the thirty-fifth embodiment. 10A to 10D are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. 10A to 10C are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. 10A to 10E are time charts showing how the base values of various areas are notified by the first to fourth notification display devices. 10 is a flowchart showing a result calculation process executed by the main CPU. 10 is a flowchart showing a display process executed by the main CPU. 10 is a flowchart showing main processing executed by a main CPU. 10 is a flowchart showing a first timer interrupt process executed by the main CPU. 10 is a flowchart showing a second timer interrupt process executed by the main CPU. 10 is a flowchart showing a setting process executed by the main CPU during normal operation. 10 is a flowchart showing a setting confirmation process executed by the main CPU. 10 is a flowchart showing a setting value update process executed by the main CPU. (a) to (f) are time charts for explaining the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. 36 is a flowchart showing a main process executed by the main CPU in the thirty-sixth embodiment. 37 is a flowchart showing a main process executed by the main CPU in the thirty-seventh embodiment. A flowchart showing the normal setting process executed by the main CPU in the 38th embodiment. 39(a) to 39(d) are explanatory diagrams for explaining setting correspondence storage areas provided in the main ROM in the thirty-ninth embodiment. This is a flowchart showing the process of reading the win/lose table executed by the main CPU. 10 is a flowchart showing a setting process to the fifth display data buffer during setting update executed by the main CPU. 10A to 10C are explanatory diagrams for explaining a setting correspondence storage area provided in the main ROM in the fortieth embodiment. (a) An explanatory diagram for explaining the various display units provided in an area visible from the front of the pachinko machine through the window panel in the 41st embodiment, and (b) an explanatory diagram for explaining the display content of the round display unit. A flowchart showing the main processing executed by the main CPU in the 42nd embodiment. 10 is a flowchart showing a first timer interrupt process executed by the main CPU. A flowchart showing the result calculation process executed by the main CPU in the 43rd embodiment. 10 is a flowchart showing a display process executed by the main CPU. 10A to 10G are time charts showing how the base values of various areas are notified by the first to fourth notification display devices. 44(a) to 44(g) are time charts showing how the base values of various areas are notified by the first to fourth notification display devices in the 44th embodiment. A flowchart showing the main processing executed by the main CPU in the 45th embodiment. 10 is an explanatory diagram for explaining the contents of a storage area related to setting values provided in a work area for specific control. FIG. 10 is a flowchart showing a setting confirmation process executed by the main CPU. 10 is a flowchart showing a setting process to the fifth display data buffer during setting confirmation executed by the main CPU. 10 is a flowchart showing a setting value update process executed by the main CPU. 10 is a flowchart showing a setting process to the fifth display data buffer during setting update executed by the main CPU. FIG. 10 is an explanatory diagram for explaining the content of the processing executed in the main processing when the supply of operating power is subsequently resumed if a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. 10A to 10E are time charts showing the end timing of the setting value update process and the setting confirmation process in relation to the operation state of the setting key insertion section. A flowchart showing the main processing executed by the main CPU in the 46th embodiment. FIG. 10 is an explanatory diagram for explaining the content of the processing executed in the main processing when the supply of operating power is subsequently resumed if a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. This is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed in a situation where a setting value update processing or setting confirmation processing is being executed in the 47th embodiment. This is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed in a situation where a setting value update processing or setting confirmation processing in the 48th embodiment is being executed. A flowchart showing the main processing executed by the main CPU in the 49th embodiment. 10 is a flowchart showing a setting confirmation process executed by the main CPU. 10 is a flowchart showing a setting value update process executed by the main CPU. 10A to 10H are time charts showing how first timer interrupt processing and second timer interrupt processing are permitted when processing is being executed at the start of supply of operating power. 10A to 10G are time charts showing the progress of processing when an abnormality occurs in the power outage flag, checksum, or set value. (a) to (g) are time charts showing the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. FIG. 10 is an explanatory diagram for explaining the content of the processing executed in the main processing when the supply of operating power is subsequently resumed if a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. FIG. 2 is an explanatory diagram for explaining the electrical configuration of the audio and light emission control device. 10 is a flowchart showing a performance control process executed by the sound and light side CPU. 10 is an explanatory diagram for explaining the action corresponding to the content of the processing executed in the processing at the start of supply of operating power in the main CPU. FIG. A flowchart showing the performance control processing executed by the sound and light side CPU in the 50th embodiment. 10 is an explanatory diagram for explaining the action corresponding to the content of the processing executed in the processing at the start of supply of operating power in the main CPU. FIG. A flowchart showing the main processing executed by the main CPU in the 51st embodiment. A flowchart showing the main processing executed by the main CPU in the 52nd embodiment. A flowchart showing the main processing executed by the main CPU in the 53rd embodiment. 10A to 10G are time charts showing the subsequent processing when the supply of operating power to the main CPU is stopped while the setting value update processing is being executed. 10 is a flowchart showing a setting value update process executed by the main CPU. FIG. 10 is an explanatory diagram for explaining the contents of a storage area provided in a work area for specific control. 10A to 10F are time charts showing how setting values to be updated are updated. A flowchart showing the main processing executed by the main CPU in the 54th embodiment.

First Embodiment
A first embodiment of a pachinko gaming machine (hereinafter referred to as a "pachinko machine"), which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a perspective view of a pachinko machine 10, and Fig. 2 is an exploded perspective view showing the main components of the pachinko machine 10. For convenience, Fig. 2 omits the components within the play area PA of the pachinko machine 10.

As shown in Figure 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so that it can rotate forward. The outer frame 11 is made up of wooden boards connected at all four sides, forming a rectangular frame. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not a required component of the pachinko machine 10, and the outer frame 11 may also be attached to the island equipment of the amusement hall.

As shown in Figure 2, the gaming machine main body 12 comprises an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a rear pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. In detail, when viewed from the front, the inner frame 13 can be rotated forward with the left side as the base end and the right side as the tip end.

A front door frame 14 is rotatably supported on the inner frame 13, and can be rotated forward with the left side as the base end and the right side as the tip end when viewed from the front. A rear pack unit 15 is also rotatably supported on the inner frame 13, and can be rotated rearward with the left side as the base end and the right side as the tip end when viewed from the front.

The gaming machine main body 12 is equipped with a locking device at its pivot tip, which functions to lock the gaming machine main body 12 so that it cannot be opened relative to the outer frame 11, and also functions to lock the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states can be released by using an unlocking key to unlock the cylinder lock 17, which is exposed on the front of the pachinko machine 10.

Next, we will explain the configuration of the front side of the gaming machine main body 12.

The inner frame 13 is primarily composed of a resin base 21 whose outer shape is approximately the same as that of the outer frame 11. A roughly oval window hole 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a play area PA formed on the front of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 in the resin base 21.

Here, the configuration of the game board 24 will be explained based on Figure 3. Figure 3 is a front view of the game board 24.

An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to define part of the outer edge of the play area PA, and these inner rail portion 25 and outer rail portion 26 form a guide rail that serves as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the top of the play area PA by the guide rail.

The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeding device 27b that supplies game balls stored in the upper tray 55a (described below) onto the launching rail 27a, and a solenoid 27c, which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by rotating the launch operating device (or operating handle) 28 provided on the front door frame 14, and the game balls are launched.

The game board 24 has multiple large and small openings that penetrate in the front-to-rear direction. Each opening is equipped with a general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a general symbol unit 38. There are a total of four general winning openings 31, and one of each of the others.

Even if a ball enters the through gate 35, no game balls will be paid out. On the other hand, when balls enter the general prize opening 31, the special electric prize opening 32, the first actuation opening 33, and the second actuation opening 34, a predetermined number of game balls will be paid out. Specifically, when one game ball enters the first actuation opening 33 or when one game ball enters the second actuation opening 34, one prize ball will be paid out; when one game ball enters the general prize opening 31, ten prize balls will be paid out; and when one game ball enters the special electric prize opening 32, fifteen prize balls will be paid out.

The number of prize balls is optional; for example, the second actuation port 34 may be configured to have fewer prize balls than the first actuation port 33, or the second actuation port 34 may be configured to have more prize balls than the first actuation port 33.

In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes are discharged from the game area PA through the outlet 24a. The game board 24 is also equipped with numerous nails 24b to appropriately distribute and adjust the direction in which the game balls fall, and various components such as windmills are also arranged.

Here, "entering" refers to a game ball passing through a specified opening, and includes not only the case where the game ball is discharged from the game area PA after passing through the opening, but also the case where the game ball continues to flow down the game area PA without being discharged after passing through the opening. However, in the following explanation, to clearly distinguish from game balls entering the outlet 24a, game balls entering the general winning opening 31, special electric winning device 32, first operating opening 33, second operating opening 34, and through gate 35 will also be referred to as "winning."

The first actuation port 33 and the second actuation port 34 are united as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 open upward. Furthermore, both actuation ports 33, 34 are aligned vertically, with the first actuation port 33 facing upward. The second actuation port 34 is provided with a normal power device 34a, which serves as a guide piece consisting of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

A through gate 35 is provided upstream of the second actuation port 34 in the direction in which the game ball flows down. The through gate 35 has a through hole (not shown) that runs vertically through it, and game balls that enter the through gate 35 flow down the game area PA after winning. This allows game balls that enter the through gate 35 to enter the second actuation port 34.

Based on a win at the through gate 35, the normal power feature 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is conducted when a win is made at the through gate 35, and a changing image is displayed on the normal map display section 38a of the normal map unit 38, which is located in the lower right corner of the play area PA, an area through which game balls do not pass. If the result of the internal lottery is a win to open the normal power feature, the stop result corresponding to that result is displayed, and the changing display on the normal map display section 38a ends, the system transitions to the normal power open state. In the normal power open state, the normal power feature 34a is opened in a predetermined manner.

The map display unit 38a is configured as a segment display in which multiple LED display segments are arranged in a predetermined pattern, but is not limited to this and may be configured as other types of display devices such as a liquid crystal display, an organic EL display, a CRT, or a dot matrix display. Possible patterns displayed on the map display unit 38a include a configuration in which multiple types of letters are displayed in a variable manner, a configuration in which multiple types of symbols are displayed in a variable manner, a configuration in which multiple types of characters are displayed in a variable manner, or a configuration in which multiple types of colors are displayed in an alternating manner.

In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. Up to four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

A winning lottery is triggered by a winning entry into the first actuation port 33 or the second actuation port 34. The results of the lottery are then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

Regarding the special symbol unit 37 in more detail, the special symbol unit 37 is provided with a special symbol display section 37a. The display area of the special symbol display section 37a is smaller than the display surface 41a of the symbol display device 41. In the special symbol display section 37a, a winning lottery is held when a winning bid is made through the first operating port 33 or the second operating port 34, triggering a winning lottery, which displays a varying or predetermined pattern. The result corresponding to the lottery result is then displayed. Note that the special symbol display section 37a is configured as a segment display in which multiple LED display segments are arranged in a predetermined pattern, but is not limited to this and may be configured as other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display. Possible patterns displayed on the special symbol display section 37a include a configuration in which multiple types of letters are displayed, a configuration in which multiple types of symbols are displayed, a configuration in which multiple types of characters are displayed, or a configuration in which multiple types of colors are displayed.

In the special symbol unit 37, a special symbol reserve display unit 37b is provided adjacent to the special symbol display unit 37a. Up to four game balls that enter the first operating port 33 or the second operating port 34 are reserved, and the number of reserved balls is displayed by lighting up the special symbol reserve display unit 37b.

In more detail, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described below. Note that the pattern display device 41 is not limited to a liquid crystal display device, and may be another display device with a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

In the symbol display device 41, when a symbol variable display or a predetermined display is performed in the special symbol display unit 37a based on a winning entry into the first actuation port 33 or a winning entry into the second actuation port 34, a symbol variable display or a predetermined display is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows (top, middle, and bottom) set as multiple display areas, and in each symbol row, main symbols numbered "1" through "9" are scrolled and displayed in ascending or descending order. This scrolling display first starts scrolling all symbol rows, then switches from scrolling display to standby display in the order of top symbol row → bottom symbol row → middle symbol row, and finally ends with a predetermined symbol being statically displayed in each symbol row. Then, in a game where the game result is a jackpot, a predetermined symbol combination is displayed frozen on a pre-set pay line on the display surface 41a of the symbol display device 41. Specifically, in the case of the most favorable jackpot result described below, the same odd symbol combination will be displayed, in the case of a low probability jackpot result described below, the same even symbol combination will be displayed, and in the case of a low prize high probability jackpot result described below, a symbol combination that is not the same but would not be displayed in the case of a low prize high probability jackpot result will be displayed.

The pattern display device 41 not only produces display effects triggered by a win in the first actuation port 33 or the second actuation port 34, but also produces display effects during the open/close execution mode to which it enters after a win is achieved. Furthermore, display on the special symbol display unit 37a and the pattern display device 41 begins based on a win in either actuation port 33, 34, and one game session is played until the specified result is displayed and the game ends. Furthermore, the manner in which the pattern display device 41 displays the changing patterns is not limited to the above and is arbitrary, and the number of pattern rows, the direction of the changing display of the patterns in the pattern rows, the number of patterns in each pattern row, etc. can be changed as appropriate. Furthermore, the patterns displayed by the pattern display device 41 are not limited to those described above; for example, a configuration in which only numbers are displayed as changing patterns may be used.

If a jackpot is won in a lottery based on a win through the first operating port 33 or the second operating port 34, the system transitions to an open/close execution mode, which allows a win in the special electric winning device 32. The special electric winning device 32 has a large prize opening (not shown) that leads to the back side of the game board 24, as well as an open/close door 32a that opens and closes the large prize opening. The open/close door 32a is positioned in either a closed or open state. Specifically, the open/close door 32a is normally in a closed state, which prevents game balls from winning, but if an internal lottery is successful in transitioning to the open/close execution mode, it switches to an open state, which allows game balls to win. The open/close execution mode is the mode to which the system transitions when a win occurs. Note that while a win is not impossible in the closed state, it may be configured to make it more difficult for a win to occur than in the open state.

Figure 4 is an explanatory diagram illustrating the configuration for discharging game balls that have flowed down the game area PA.

As already explained, a game ball that enters any of the general winning opening 31, special electric winning device 32, first operating opening 33, second operating opening 34, and outlet 24a is discharged from the game area PA. In other words, a game ball that is launched from the game ball launching mechanism 27 and enters the game area PA is discharged from the game area PA by entering any of the general winning opening 31, special electric winning device 32, first operating opening 33, second operating opening 34, and outlet 24a. A game ball that enters any of the general winning opening 31, special electric winning device 32, first operating opening 33, second operating opening 34, and outlet 24a is guided to the back side of the game board 24.

On the back of the gaming board 24, discharge passages 42-48 are formed corresponding to the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, respectively. Gaming balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, leading to the lower end of the gaming board 24 on the back side of the gaming board 24 and being collected by a discharge ball collection section (not shown). The gaming balls collected by the discharge ball collection section are then discharged to a ball circulation device in the island equipment where the pachinko machine 10 is installed in the gaming hall.

Each discharge passage section 42-48 is provided with various detection sensors 42a-48a for detecting game balls. These discharge passage sections 42-48 and detection sensors 42a-48a are described below. As already explained, there are four general winning openings 31, and therefore there is a discharge passage section 42-44 corresponding to each of the four. In this case, one detection sensor 42a is provided for the first discharge passage section 42 corresponding to the leftmost general winning opening 31, and one detection sensor 43a is provided for the second discharge passage section 43 corresponding to the general winning opening 31 adjacent to it to the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located midway along the first discharge passage section 42, and the second winning opening detection sensor 43a is provided so that its detection range is located midway along the second discharge passage section 43. A gaming ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a as it passes through the first discharge passage 42, and a gaming ball that enters the general winning opening 31 adjacent to it on the right is detected by the second winning opening detection sensor 43a as it passes through the second discharge passage 43. A third discharge passage 44 is provided for the two right-side general winning openings 31, and is formed to merge midway. The third discharge passage 44 has entrance-side regions corresponding to each of the two general winning openings 31, and these entrance-side regions merge midway to form a single exit-side region. A third winning opening detection sensor 44a is provided so that a detection range is located midway in the exit-side region of the third discharge passage 44. A gaming ball that enters either of the two right-side general winning openings 31 is detected by the third winning opening detection sensor 44a as it passes through the third discharge passage 44.

A fourth discharge passage section 45 exists in correspondence with the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists midway through the fourth discharge passage section 45, and a game ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a as it passes through the fourth discharge passage section 45. A fifth discharge passage section 46 exists in correspondence with the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists midway through the fifth discharge passage section 46, and a game ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a as it passes through the fifth discharge passage section 46. A sixth discharge passage section 47 exists in correspondence with the second operating port 34. A second actuation port detection sensor 47a is provided so that its detection range is located midway along the sixth discharge passage 47, and a gaming ball that enters the second actuation port 34 is detected by the second actuation port detection sensor 47a as it passes through the sixth discharge passage 47. A seventh discharge passage 48 exists in correspondence with the outlet 24a. An outlet detection sensor 48a is provided so that its detection range is located midway along the seventh discharge passage 48, and a gaming ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage 48.

A gaming ball that is detected by one of the various detection sensors 42a-48a will not be detected by the other detection sensors 42a-48a. A gate detection sensor 49a is also provided for the through gate 35, and gaming balls that pass through the through gate 35 on their way down the play area PA are detected by the gate detection sensor 49a.

The various detection sensors 42a-49a are all electromagnetic induction proximity sensors, but any sensor can be used as long as it can detect game balls individually. The various detection sensors 42a-49a are electrically connected to the main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a game ball, and output a HI level signal when they are detecting a game ball. However, this is not limited to this, and the HI and LOW relationship may be reversed.

As shown in FIG. 2, a front door frame 14 is provided to cover the entire front side of the inner frame 13, which is formed by attaching the game board 24 configured as described above to the resin base 21. As shown in FIG. 1, the front door frame 14 has a window portion 51 formed therein, which allows almost the entire game area PA to be viewed from the front. The window portion 51 is approximately elliptical in shape and has a window panel 52 fitted into it. The window panel 52 is made of colorless and transparent glass, but is not limited to this and may be made of colorless and transparent synthetic resin, or may be made of colored and transparent as long as the game area PA can be viewed through the window panel 52 from the front of the pachinko machine 10.

A display light-emitting unit 53 is provided above the window 51. A pair of left and right speakers 54 are also provided, which output sound effects according to the game status. An upper bulge 55 and a lower bulge 56, which bulge toward the front, are arranged side by side below the window 51. An upper tray 55a with an upward opening is provided inside the upper bulge 55, and a lower tray 56a with a similar upward opening is provided inside the lower bulge 56. The upper tray 55a temporarily stores game balls dispensed from the dispensing device (described below) and guides them in a row toward the game ball launching mechanism 27. The lower tray 56a also stores surplus game balls in the upper tray 55a.

Next, we will explain the configuration on the back side of the gaming machine main body 12.

As shown in Figure 2, a main control device 60, which is responsible for the main control of the game, is mounted on the back of the inner frame 13 (specifically, the game board 24). Figure 5 is a front view of the main control device 60.

As shown in Figure 5, the main control device 60 comprises a main control board 61 housed in a board box 60a. An MPU 62 is mounted on one of the surfaces of the main control board 61, which is the device mounting surface. The board box 60a is transparent so that the MPU 62 housed within the board box 60a can be seen from outside the board box 60a. Note that while the board box 60a is colorless and transparent, it may also be colored and transparent as long as the MPU 62 housed within the board box 60a can be seen from outside the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 so that the opposing wall portion 60b of the board box 60a that faces the device mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine main body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the base box 60a, and also to visually observe the MPU 62 through said opposing wall portion 60b.

The board box 60a is formed by combining multiple case bodies 60c one behind the other. These multiple case bodies 60c are provided with connecting portions 60e that prevent the case bodies 60c from separating and leave a trace of the separation. Multiple connecting portions 60e are arranged side by side along one side of the roughly rectangular board box 60a. This makes it possible to prevent the separation of the case bodies 60c again by subsequently connecting another connecting portion 60e, even if some connecting portions 60e are used to prevent the separation of the case bodies 60c and the case bodies 60c are separated by destroying those connecting portions 60e. Furthermore, because the connecting portions 60e are destroyed when the case bodies 60c are separated, leaving a trace, it is possible to visually check the connecting portions 60e to determine whether the case bodies 60c have been separated improperly. Additionally, a sealing sticker 60f is affixed to the side of the board box 60a opposite the side on which the connecting portions 60e are arranged, spanning the boundary between the case bodies 60c. When the sealing sticker 60f is peeled off, the adhesive layer remains on the case body 60c. This makes it possible to leave a trace if the sealing sticker 60f is peeled off when the case bodies 60c are separated.

In the main control device 60 configured as described above, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the gaming hall manager is inserted and turned ON to trigger an opportunity to change the setting state of the pachinko machine 10 within the range of "Setting 1" to "Setting 6," an update button 68b that is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned ON, a reset button 68c that is operated to clear data in the main RAM 65 (described below) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c that notify the results of game history management. The MPU 62 mounted on the main control board 61 is also provided with a read terminal 68d for connecting to an external device so that the external device can read the game history management results or the information (programs and data) stored in the main ROM 64. Note that the setting status of the pachinko machine 10 is not limited to six levels from "Setting 1" to "Setting 6" and can be any number of levels.

The setting key insertion section 68a, update button 68b, reset button 68c, reading terminal 68d (i.e., MPU 62), and first to third alarm display devices 69a-69c are all provided on the device mounting surface of the main control board 61. As already explained, the device mounting surface of the main control board 61 faces the opposing wall 60b of the circuit board box 60a. However, the opposing wall 60b does not cover the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d. In other words, the opposing wall 60b has separate openings in the areas facing the setting key insertion section 68a, update button 68b, reset button 68c, and reading terminal 68d. This allows the setting key to be inserted into the setting key insertion section 68a, the update button 68b to be pressed, the reset button 68c to be pressed, and the reading terminal 68d to be connected to a connection terminal for an external device, without having to open the circuit board box 60a.

By inserting a setting key into the setting key insertion portion 68a and rotating it in a predetermined direction, the setting key insertion portion 68a is turned ON. In this state, starting the supply of operating power to the pachinko machine 10 (i.e., starting the supply of operating power to the MPU 62 of the main control device 60) puts the pachinko machine 10 into a changeable state, allowing the setting state to be changed. In this state, each time the update button 68b is pressed, the setting state of the pachinko machine 10 changes by one step in ascending order from "Setting 1" to "Setting 6." Note that if the update button 68b is operated while the pachinko machine is in "Setting 6," the setting state is updated to "Setting 1." Furthermore, by rotating the setting key inserted into the setting key insertion portion 68a from the ON position in the opposite direction to the predetermined direction and returning it to its initial position, the setting key insertion portion 68a is turned OFF. When the setting key insertion portion 68a is turned OFF, the changeable state ends, and gameplay is resumed with the setting values at that time. In other words, even if you operate the update button 68b after the changeable state has ended, the setting value cannot be changed.

The ON operation of the setting key insertion section 68a is only valid when the supply of operating power to the pachinko machine 10 begins (i.e., when the supply of operating power to the MPU 62 of the main control unit 60 begins). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control unit 60 has finished, the setting value cannot be changed.

The setting state of the pachinko machine 10 determines the degree of advantage per unit time for that pachinko machine 10, with the larger the value of "setting n" (n is an integer between "1" and "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in more detail below, the win/lose lottery mode that determines the probability of winning a jackpot outcome is a low probability mode with a relatively low probability of winning, and a high probability mode with a relatively high probability of winning, and the higher the setting value, the higher the probability of winning a jackpot outcome in low probability mode. On the other hand, the probability of winning a jackpot outcome in high probability mode remains constant regardless of the setting value.

As described above, the reset button 68c is operated to clear the data in the main RAM 65, but in order to clear this data, the supply of operating power to the pachinko machine 10 must be started while the reset button 68c is pressed (i.e., the supply of operating power to the MPU 62 of the main control device 60 must be started). The ON operation of the reset button 68c is only valid when the supply of operating power to the pachinko machine 10 begins (i.e., when the supply of operating power to the MPU 62 of the main control device 60 begins). Therefore, even if the reset button 68c is pressed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the data in the main RAM 65 cannot be cleared.

As already explained, the read terminal 68d is connected to the connection terminal of an external device so that the external device can read the game history management results or the information (programs and data) stored in the main ROM 64. However, in order to output data to the external device, the supply of operating power to the pachinko machine 10 must be started while the connection terminal of the external device is connected to the read terminal 68d (i.e., the supply of operating power to the MPU 62 of the main control unit 60 must be started). Connection of an external device to the read terminal 68d is only valid when the supply of operating power to the pachinko machine 10 begins (i.e., when the supply of operating power to the MPU 62 of the main control unit 60 begins). Therefore, even if an external device is connected to the read terminal 68d after the MPU 62 of the main control unit 60 has completed processing to start the supply of operating power, no external output will be made to the external device.

The first through third alarm display devices 69a through 69c are all segment displays with an arrangement of seven LED display segments, but are not limited to this and may be a single light-emitting element of a multi-color type, a liquid crystal display, or an organic electroluminescence (EL) display. The first through third alarm display devices 69a through 69c are all installed so that their display surfaces face the direction of the element mounting surface of the main control board 61, and are covered by the opposing wall 60b of the board box 60a. In this case, because the board box 60a is made transparent, the display surfaces of the first through third alarm display devices 69a through 69c housed within the board box 60a can be viewed from outside the board box 60a. Furthermore, as already explained, the main control device 60 is mounted on the back surface of the resin base 21 so that the opposing wall portion 60b, which faces the element mounting surface of the main control board 61 in the board box 60a, faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the back surface of the resin base 21 is exposed toward the front of the pachinko machine 10, the display surfaces of the first to third notification display devices 69a to 69c can be seen through the opposing wall portion 60b.

The display surface of the first notification display device 69a displays not only the numbers "0" through "9" but also various characters, including alphabetic characters. Meanwhile, the second notification display device 69b and the third notification display device 69c display the numbers "0" through "9." The results of game history management are reported using the first through third notification display devices 69a through 69c; the details of these reports will be explained in detail later. Furthermore, when the setting state of the pachinko machine 10 is in a changeable state, where it is possible to change the setting state, a value corresponding to the current setting value is displayed on the third notification display device 69c. Note that the value corresponding to the setting value may be displayed on either the first notification display device 69a or the second notification display device 69b. Alternatively, the setting value before the changeable state may be displayed on one of the first through third notification display devices 69a through 69c, and the current setting value may be displayed on another of the first through third notification display devices 69a through 69c.

As shown in Figure 2, the rear pack unit 15 is installed to cover the rear side of the inner frame 13, including the main control unit 60. The rear pack unit 15 includes a rear pack 72 made of transparent synthetic resin, to which a dispensing mechanism 73 and a control unit assembly unit 74 are attached.

The payout mechanism 73 includes a tank 75 to which game balls are successively replenished from the island equipment in the gaming hall, and a payout device 76 for paying out the game balls stored in the tank 75. Game balls paid out from the payout device 76 are discharged onto the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power on and off.

The control device aggregate unit 74 is equipped with a payout control device 77 that has the function of controlling the payout device 76, and a power supply/launch control device 78 that generates and outputs the predetermined power required by various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and power supply/launch control device 78 are stacked one behind the other, with the payout control device 77 at the rear of the pachinko machine 10.

<Electrical configuration of pachinko machine 10>
FIG. 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

The main control device 60 comprises a main control board 61, which is responsible for the main control of the game, and a power outage monitoring board 67, which monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 contains a main CPU 63, which is a processing device including a control unit and an arithmetic unit, as well as a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also contains an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits such as a random number generator, and more.

The main ROM 64 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

The main RAM 65 is a type of memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM or DRAM, and is used for both reading and writing. The main RAM 65 is randomly accessible and has a faster read time than the main ROM 64 when compared for the same data capacity. The main RAM 65 temporarily stores various data for the execution of the control programs stored in the main ROM 64.

The management IC 66 is a management device that manages game history based on information supplied from the main CPU 63. Details will be described later, but the management IC 66 keeps track of the ball entry history into the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, and also keeps track of the ball entry frequency into the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 based on the ball entry history. The management IC 66 also keeps track of the frequency of the opening/closing execution mode and the high frequency support mode, which will be described later.

The MPU 62 has an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply/launch control device 78, which has the function of supplying operating power, and operating power is supplied to the MPU 62 via the power outage monitoring board 67.

Various sensors, such as the ball entry detection sensors 42a-49a, are connected to the input side of the MPU 62. As already explained, the ball entry detection sensors 42a-49a include the first entry port detection sensor 42a, the second entry port detection sensor 43a, the third entry port detection sensor 44a, the special electric current detection sensor 45a, the first operating port detection sensor 46a, the second operating port detection sensor 47a, the exit port detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a-49a, the main CPU 63 determines whether a ball has entered each entry port. The main CPU 63 also conducts various lotteries based on whether a ball has entered the first operating port 33, and various lotteries based on whether a ball has entered the second operating port 34.

The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is positioned for the ON operation or the OFF operation. The main CPU 63 then determines whether the setting key insertion section 68a is positioned for the ON operation or the OFF operation based on the detection results from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b has been pressed. The main CPU 63 then determines whether the update button 68b has been pressed based on the detection results from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c has been pressed. The main CPU 63 then determines whether the reset button 68c has been pressed based on the detection results from the sensor.

The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio/light emitting control device 81. A prize ball command is output to the payout control device 77, for example, when a game ball enters a prize ball entry section among the entry sections, where the occurrence of the ball entry corresponds to the payout of the game ball. Various commands, such as a variation command, a type command, and an opening command, are output to the audio/light emitting control device 81.

Connected to the output side of the MPU 62 are the special power drive unit 32b, which opens and closes the opening/closing door 32a of the special power winning device 32, the normal power drive unit 34b, which opens and closes the normal power device 34a of the second operating port 34, the special chart unit 37, and the normal chart unit 38. Incidentally, the special chart unit 37 is provided with a special chart display unit 37a and a special chart reserved display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal chart unit 38 is provided with a normal chart display unit 38a and a normal chart reserved display unit 38b, all of which are connected to the output side of the MPU 62. The main control board 61 is provided with various driver circuits, and the MPU 62 controls the drive of the various drive units and displays through these driver circuits.

In other words, in the opening/closing execution mode, the main CPU 63 controls the drive of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Furthermore, if the open state of the normal power device 34a is selected, the main CPU 63 controls the drive of the normal power drive unit 34b so that the normal power device 34a is opened and closed. Furthermore, during each game round, the main CPU 63 controls the display of the special chart display unit 37a. Furthermore, when the result of the lottery as to whether or not the normal power device 34a is to be opened is to be displayed, the main CPU 63 controls the display of the normal chart display unit 38a. In addition, when a win occurs in the first operating port 33 or the second operating port 34, or when a change display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart reserve display unit 37b, and when a win occurs in the through gate 35, or when a change display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart reserve display unit 38b.

The first to third alert display devices 69a to 69c are connected to the output side of the MPU 62. The results of game history management by the management IC 66 are reported through displays on the first to third alert display devices 69a to 69c. When the settings of the pachinko machine 10 are changed, the current setting value is displayed on the third alert display device 69c. In this case, the display of the first alert display device 69a and the second alert display device 69b is controlled by the management IC 66 and not by the main CPU 63, whereas the display of the third alert display device 69c is controlled by both the main CPU 63 and the management IC 66. Display control by the main CPU 63 takes priority over display control by the management IC 66 for the display of the third alert display device 69c.

However, this is not limited to this, and the third alert display device 69c may also be configured so that its display is controlled by the management IC 66 and not by the main CPU 63. In this case, when the setting state of the pachinko machine 10 is changed and the current setting value is to be displayed on the third alert display device 69c, the main CPU 63 may instruct the management IC 66 to display the setting value.

The MPU 62 is provided with a read terminal 68d. A sensor (not shown) is provided on the read terminal 68d, and this sensor detects whether or not an external device connection terminal is connected to the read terminal 68d. The main CPU 63 then determines whether or not an external device connection terminal is connected to the read terminal 68d based on the detection results from the sensor. Furthermore, if an external device is connected to the read terminal 68d, the results of game history management in the management IC 66 or information (programs and data) stored in the main ROM 64 are output to the external device.

The power outage monitoring board 67 relays between the main control board 61 and the power supply/launch control device 78, and monitors the maximum voltage output from the power supply/launch control device 78, which is a stable DC voltage of 24 volts. The payout control device 77 controls the payout of prize balls and loan balls using the payout device 76 based on the prize ball command received from the main control device 60.

The power supply and launch control device 78 is connected to a commercial power source (external power source) in, for example, an amusement hall. It generates the necessary operating power for the main control board 61, payout control device 77, etc. based on the external power supplied from the commercial power source, and supplies the generated operating power. Incidentally, the power supply and launch control device 78 is provided with a power supply unit for power outages, such as a backup capacitor. Even when the power to the pachinko machine 10 is turned off, this power supply unit supplies power for memory retention to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply and launch control device 78 also controls the launch of the game ball launching mechanism 27, which is activated when predetermined launch conditions are met. As already explained, the payout mechanism 73 is also provided with a power switch. Turning the power switch ON starts the supply of operating power to the pachinko machine 10, and turning the power switch OFF stops the supply of operating power to the pachinko machine 10.

The audio and light control device 81 drives and controls the display light-emitting unit 53 and speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 controls the display of the pattern display device 41 based on commands received from the audio and light-emitting control device 81.

<Electrical configuration for performing various lotteries by the main CPU 63>
Next, the electrical configuration for performing various lotteries in the main CPU 63 will be described with reference to FIG.

During play, the main CPU 63 uses various counter information to perform the jackpot lottery, set the display in the special symbol display unit 37a, set the symbol display on the symbol display device 41, and set the display in the normal symbol display unit 38a. Specifically, as shown in FIG. 7, the main CPU 63 uses a hit random number counter C1 used to determine the hit lottery, a jackpot type counter C2 used to determine the type of jackpot, a reach random number counter C3 used to determine the reach lottery when the symbol display device 41 changes due to a miss, a random number initial value counter CINI used to set the initial value of the hit random number counter C1, and a change type counter CS that determines the display duration on the special symbol display unit 37a and the symbol display device 41. Furthermore, the main CPU 63 uses a normal power feature release counter C4 used to determine whether the normal power feature 34a of the second operating port 34 is set to the normal power release state. The above counters C1-C3, CINI, CS, and C4 are provided in the various counter area 65b of the main RAM 65.

Each counter C1-C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

The reserve storage area 65a comprises a reserve area RE and an execution area AE. The reserve area RE comprises a first reserve area RE1, a second reserve area RE2, a third reserve area RE3, and a fourth reserve area RE4. Combinations of numerical information from the win random number counter C1, jackpot type counter C2, and reach random number counter C3 are stored as reserve information in one of the reserve areas RE1 to RE4, according to the winning history of the first actuation port 33 or the second actuation port 34.

In this case, if multiple consecutive wins occur in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first hold area RE1 to the fourth hold area RE4 in chronological order: first hold area RE1 → second hold area RE2 → third hold area RE3 → fourth hold area RE4. By providing four hold areas RE1 to RE4 in this way, up to four winning ball entries in the first actuation port 33 or the second actuation port 34 can be reserved and stored.

The number of items that can be stored on hold is not limited to four and can be any number, such as two, three, five or more, or even a single number.

The execution area AE is an area for moving the numerical information stored in the first reserve area RE1 of the reserve area RE when the variable display of the special chart display section 37a begins, and at the start of one game, a win/loss determination is made based on the various numerical information stored in the execution area AE.

We will explain each of the above counters in detail below.

First, we will explain the normal power feature release counter C4. The normal power feature release counter C4 is configured to increment by one in sequence within a range of, for example, 0 to 250, and return to "0" after reaching its maximum value. The normal power feature release counter C4 is updated periodically, and is stored in the normal power reserve area 65c of the main RAM 65 when a gaming ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the normal power feature 34a to an open state based on the value of the stored normal power feature release counter C4.

This pachinko machine 10 has multiple support modes that differ from one another in the manner of support provided by the normal power device 34a. In detail, the support modes are set to a high-frequency support mode and a low-frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 opens per unit time is relatively high or low when compared to a situation in which game balls are continuously being released in the same manner into the play area PA.

In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power release state in the normal power release lottery using the normal power device release counter C4 is the same (for example, 4/5 in both), but in the high-frequency support mode, the number of times the normal power device 34a will be in the open state when the normal power release state is won is set to be more than in the low-frequency support mode, and the opening time for each opening is set to be longer. In this case, if the normal power release state is won in the high-frequency support mode and the normal power device 34a is in the open state multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each opening. Furthermore, in the high-frequency support mode, the minimum time ensured between one normal power release lottery and the next normal power release lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

As described above, in the high-frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into the first actuation port 33 is higher than in the second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the first actuation port 33. Furthermore, when a winning entry into the second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

The configuration for increasing the frequency of normal power release state per unit time in the high-frequency support mode compared to the low-frequency support mode is not limited to the above, and may be configured to increase the probability of winning the normal power release state in the normal power release lottery, for example. Furthermore, in a configuration in which multiple types of reserved time are available between one normal power release lottery and the next (for example, the time of the variable display executed by the normal power display unit 38a based on winning through gate 35), the high-frequency support mode may be configured so that a shorter reserved time is more likely to be selected or the average reserved time is shorter than in the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of the following conditions: increasing the number of releases, lengthening the open time, shortening the reserved time between one normal power release lottery and the next, shortening the average reserved time, and increasing the probability of winning.

As previously explained, the pachinko machine 10 has setting states "Setting 1" through "Setting 6." The opening frequency and opening mode of the normal power device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and opening mode of the normal power device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not limited to this, and at least one of the opening frequency and opening mode of the normal power device 34a for at least one of the low-frequency support mode and the high-frequency support mode may be configured to vary depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the opening frequency of the normal power device 34a in the low-frequency support mode. Alternatively, the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the low-frequency support mode may be increased. Furthermore, the higher the set value, the more frequently the normal power device 34a opens in the high frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a opens once in the high frequency support mode.

Next, we will explain the winning random number counter C1. The winning random number counter C1 is configured to increment by one within a range of, for example, 0 to 599, and return to "0" after reaching its maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically and stored in the reserved storage area 65a of the main RAM 65 when a gaming ball enters the first actuation port 33 or the second actuation port 34.

The random number value that results in a jackpot is stored in the main ROM 64 as a hit/miss table. Figure 8 is an explanatory diagram illustrating the various tables stored in the main ROM 64. The hit/miss tables stored include low-probability hit/miss tables 64a-64f for the low-probability mode and high-probability hit/miss table 64g for the high-probability mode.

The low-probability hit/miss tables 64a-64f are provided in a one-to-one correspondence with the setting states of "Setting 1" to "Setting 6." That is, there is a setting 1 low-probability hit/miss table 64a that is referenced when the setting state of the pachinko machine 10 is "Setting 1," a setting 2 low-probability hit/miss table 64b that is referenced when the setting state of the pachinko machine 10 is "Setting 2," a setting 3 low-probability hit/miss table 64c that is referenced when the setting state of the pachinko machine 10 is "Setting 3," a setting 4 low-probability hit/miss table 64d that is referenced when the setting state of the pachinko machine 10 is "Setting 4," a setting 5 low-probability hit/miss table 64e that is referenced when the setting state of the pachinko machine 10 is "Setting 5," and a setting 6 low-probability hit/miss table 64f that is referenced when the setting state of the pachinko machine 10 is "Setting 6."

These low-probability tables 64a-64f are set so that the higher the setting value, the higher the probability of winning a jackpot. Specifically, when the low-probability table 64a for setting 1 is referenced, the jackpot result occurs at approximately 1 in 320, when the low-probability table 64b for setting 2 is referenced, the jackpot result occurs at approximately 1 in 310, when the low-probability table 64c for setting 3 is referenced, the jackpot result occurs at approximately 1 in 300, when the low-probability table 64d for setting 4 is referenced, the jackpot result occurs at approximately 1 in 290, when the low-probability table 64e for setting 5 is referenced, the jackpot result occurs at approximately 1 in 280, and when the low-probability table 64f for setting 6 is referenced, the jackpot result occurs at approximately 1 in 270. As a result, when the setting state of the pachinko machine 10 is set at a higher value, the jackpot result is more likely to occur in low probability mode, which is advantageous for players.

On the other hand, only one type of high-probability win/loss table 64g is provided so that it is common to all settings, from "Setting 1" to "Setting 6." The high-probability win/loss table 64g is set to have a higher probability of winning a jackpot than the low-probability win/loss tables 64a to 64f, regardless of the setting, from "Setting 1" to "Setting 6." Specifically, when the high-probability win/loss table 64g is referenced, the jackpot result occurs at approximately 1/30. This makes it possible to make the high-probability mode more advantageous than the low-probability mode, regardless of the setting of the pachinko machine 10. Furthermore, by entering the high-probability mode even in the lowest setting, "Setting 1," it is possible to increase the probability of winning a jackpot compared to the low-probability mode of the highest setting, "Setting 6." Furthermore, it is possible to prevent advantages or disadvantages arising from the setting of the pachinko machine 10 for the high-probability mode, and it is also possible to reduce the storage capacity required to pre-store the high-probability win/loss table 64g in the main ROM 64.

The jackpot type counter C2 is configured to increment by one within the range of 0 to 29, and return to "0" after reaching its maximum value. The jackpot type counter C2 is updated periodically, and is stored in the reserved storage area 65a when a gaming ball enters the first actuation port 33 or the second actuation port 34.

This pachinko machine 10 has multiple jackpot results set. These multiple jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special electric prize winning device 32 in the opening and closing execution mode, (2) the lottery mode of the winning/losing lottery means after the opening and closing execution mode ends, and (3) the support mode of the regular electric device 34a of the second operating port 34 after the opening and closing execution mode ends.

In the opening and closing execution mode, the opening and closing control of the special electric winning device 32 is set to a high-frequency winning mode and a low-frequency winning mode so that the frequency of winning in the special electric winning device 32 is relatively high and low from the start to the end of the opening and closing execution mode. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, a predetermined number of rounds of play are played up to the upper limit.

A round of play is a game that continues until one of the following conditions is met: a predetermined maximum duration has elapsed, or a predetermined maximum number of game balls have entered the special electric winning device 32. Furthermore, the number of rounds of play in the open/close execution mode triggered by a jackpot result is the same fixed number of rounds, regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the jackpot result, the maximum number of rounds of play is set to 15.

In addition, in this pachinko machine 10, multiple types of opening modes of the special electric winning device 32 are set, with different opening durations from when the special electric winning device 32 is opened until when it is closed. In detail, there is a long-time mode in which the opening duration is set to a long time of 29 seconds, and a short-time mode in which the opening duration is set to a short time of 0.06 seconds, which is shorter than the long-time mode.

In this pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is controlled to launch one game ball toward the play area PA every 0.6 seconds. The upper limit for the number of balls required to complete a round is set to nine. In this case, the long-time mode, one of the above-mentioned release modes, sets the release duration to a time longer than the product of the game ball launch cycle and one round of play. On the other hand, the short-time mode sets the release duration to a time shorter than the product of the game ball launch cycle and one round of play, or more specifically, shorter than the game ball launch cycle. Therefore, when a single release is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of prizes in one round of play. When a single release is performed in the short-time mode, it is expected that the special electric winning device 32 will not win any prizes, or that, if any, only one prize will be won.

In the high-frequency winning mode, the special electric winning device 32 is opened once in a long-term mode during each round of play. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is opened once in a short-term mode during each round of play.

In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of rounds of play in one round of play in the high frequency winning mode and low frequency winning mode are not limited to the above values and are arbitrary, as long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

As shown in Figure 8, the allocation destinations of jackpot results for jackpot type counter C2 are stored in main ROM 64 as allocation table 64h. In addition, allocation table 64h sets the allocation destinations of jackpot results in the event of a jackpot result as a low-probability jackpot result, a low-prize high-probability jackpot result, and a most favorable jackpot result.

A low-probability jackpot result is one in which the opening/closing execution mode becomes high-frequency winning mode, and after the opening/closing execution mode ends, the win/lose lottery mode becomes low-probability mode, and the support mode becomes high-frequency support mode. However, this high-frequency support mode will transition to low-frequency support mode if the number of plays reaches the termination threshold number (specifically, 100 plays) after the transition.

A low-prize, high-probability jackpot result is one in which the open/close execution mode becomes low-frequency win mode, and after the open/close execution mode ends, the win/lose lottery mode becomes high-probability mode and the support mode becomes high-frequency support mode. These high-probability mode and high-frequency support mode will continue until the lottery result in a win in the win/lose lottery and the game transitions to the jackpot state.

The most favorable jackpot result is one in which the open/close execution mode becomes high-frequency winning mode, and after the open/close execution mode ends, the win/lose lottery mode becomes high-probability mode and the support mode becomes high-frequency support mode. These high-probability mode and high-frequency support mode will continue until the lottery result in a win in the win/lose state and the game transitions to the jackpot state.

In relation to the above game states, the normal game state refers to a state in which the win/lose lottery mode is a low probability mode and the support mode is a low frequency support mode, rather than the open/close execution mode. Also, a low prize-winning, high probability jackpot result may not be set as a game result. Furthermore, in the open/close execution mode with a low prize-winning, high probability jackpot result, the number of rounds of play may be fewer than in the case of a low probability jackpot result and a most favorable jackpot result.

In allocation table 64h, of the jackpot type counter C2 values "0-29," "0-9" corresponds to a low-probability jackpot result, "10-14" corresponds to a low-prize, high-probability jackpot result, and "15-29" corresponds to the most favorable jackpot result.

Only one type of allocation table 64h is provided so that it is common to all settings, from "Setting 1" to "Setting 6." This makes it possible to prevent advantages or disadvantages in the allocation pattern of jackpot results from arising depending on the setting of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to pre-store the allocation table 64h in the main ROM 64.

The allocation of jackpot results may be different depending on the settings of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result, or the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result or a low-prize, high-probability jackpot result. In this case, the higher the setting value, the higher the probability of entering a high-probability mode after a jackpot result. Also, the higher the setting value, the lower the probability of being allocated to a low-prize, high-probability jackpot result, or a high setting value may not allocate to a low-prize, high-probability jackpot result, while a low setting value may allocate to a low-prize, high-probability jackpot result. In this case, the higher the setting value, the higher the probability of the high-frequency winning mode opening/closing execution mode occurring.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to increment by one within a range of, for example, 0 to 238, and return to "0" after reaching a maximum value. This pachinko machine 10 has an expectation effect set as one type of display effect on the symbol display device 41. In a gaming machine equipped with a symbol display device 41 capable of displaying varying symbols, where the final stop result in a game round resulting in a predetermined jackpot result is a prize-related result, the expectation effect refers to a display state that makes the player believe that the variable display state is likely to result in the prize-related result between the start of the display of varying symbols on the symbol display device 41 and the stage at which the stop result is derived and displayed. Specifically, the prize-related result is the display of a combination of symbols with the same number on one of the pay lines.

There are two types of expected effects: a reach display and a warning display that is set before a reach display occurs, to anticipate the occurrence of a reach display or a corresponding result.

The reach display includes a display state in which a reach pattern combination is displayed by freezing the patterns in some of the multiple pattern rows displayed on the display surface 41a of the pattern display device 41, and in this state, the remaining pattern rows are displayed with varying patterns. It also includes a reach display in which, while a reach pattern combination is displayed as described above, the remaining pattern rows are displayed with varying patterns, and a predetermined character or the like is displayed as a moving image in the background screen, creating a reach effect; and a reach display in which the reach pattern combination is displayed in a reduced size or is not displayed, and a predetermined character or the like is displayed as a moving image across substantially the entire display surface 41a, creating a reach effect.

Pre-announcement displays include a mode in which a character is displayed separately from the symbols on the symbol columns when symbols are displayed in a changing manner in all symbol columns or when symbols are displayed in a changing manner in some symbol columns after the display of changing symbols on the display surface 41a of the symbol display device 41 has begun. They also include a mode in which the background screen is displayed in a predetermined mode different from its previous mode, or a mode in which the symbols on the symbol columns are displayed in a predetermined mode different from their previous mode. Such pre-announcement displays can occur in both gameplays when a reach display is made and when a reach display is not made, but are set to occur with a higher probability when a reach display is made than when a reach display is not made.

The reach display is executed regardless of the value of the reach random number counter C3 in a game in which the same symbol combination is ultimately displayed. Furthermore, in a game in which a jackpot result occurs in which the same symbol combination is not displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Furthermore, in a game in which a miss result occurs, the reach display is executed when the reach random number counter C3 obtained at a predetermined timing by referencing the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

On the other hand, the decision on whether to display a preview is not made by the main control device 60, but by the audio and light control device 81. In this case, the audio and light control device 81 executes a lottery process for preview displays so that a game turn corresponding to a jackpot result is more likely to produce a preview display, and/or a preview display with a low occurrence rate is more likely to occur, compared to a game turn corresponding to a loss result. Incidentally, the result of this lottery is reflected when the effect for the game turn is executed by the symbol display device 41.

Here, the probability of a reach display occurring in a game that results in a losing outcome is the same regardless of the setting state, "Setting 1" to "Setting 6." This makes it possible to ensure that the setting state of the pachinko machine 10 does not create an advantage or disadvantage in terms of the probability of a reach display occurring in a game that results in a losing outcome. However, this is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of a reach display occurring in a game that results in a losing outcome.

Next, the variation type counter CS will be explained. The variation type counter CS is configured to increment by one within a range of, for example, 0 to 198, and return to "0" after reaching its maximum value. The variation type counter CS is used by the main CPU 63 to determine the display duration in the special chart display unit 37a and the display duration of the pattern in the pattern display device 41. The variation type counter CS is updated once each time the timer interrupt process described below is executed, and is also updated repeatedly during the remaining time until the next timer interrupt process is executed. The buffer value of the variation type counter CS is then obtained when determining the variation pattern at the start of the variation display in the special chart display unit 37a and when the pattern display device 41 begins to vary the pattern.

<Regarding the processing configuration of the main CPU 63>
Next, we will explain the various processes executed to progress the game by the main CPU 63. The processes of the main CPU 63 are roughly divided into main processes that are started when the power is turned on, and timer interrupt processes that are started periodically (every 4 millisecond period in this embodiment).

<Main processing>
First, the main processing will be described with reference to the flowchart of FIG.

First, a power-on wait process is executed (step S101). During this power-on wait process, the system waits for a predetermined wait time (specifically, one second) after the main process is started, without proceeding to the next process. During this power-on wait process, the pattern display device 41 starts operating and is initialized. After that, access to the main RAM 65 is permitted (step S102).

Then, it is determined whether the setting key insertion unit 68a has been turned ON (Step S103). If the setting key insertion unit 68a has not been turned ON (Step S103: NO), it is determined whether the reset button 68c has been pressed (Step S104). If the reset button 68c has been pressed (Step S104: YES), all areas of the main RAM 65 are cleared to "0" except for the areas in which setting value information indicating the setting state of the pachinko machine 10 is set, and the areas cleared to "0" are initialized (Step S105). In other words, if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning ON the setting key insertion unit 68a, the main RAM 65 is cleared while the setting value information remains in the state it was in before the supply of operating power to the pachinko machine 10 was stopped, and the memory area where the clearing was performed is initialized. This makes it possible to initialize other areas of the main RAM 65 without changing the setting values. In step S105, various registers in the main CPU 63 are also cleared to "0" and then initialized.

If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is stored in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and the predetermined power outage processing is executed normally, the power outage flag is set to "1." If the power outage flag is set to "1," it is determined whether the checksum calculation result matches the checksum saved at the time of power outage, i.e., the validity of the stored data (step S107). If the processing of step S105 is executed or if a positive determination is made in step S107, it is determined whether the setting values of the pachinko machine 10 are normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

If a negative judgment is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or other person that an error has occurred (step S109), and then an infinite loop is entered. The operation prohibition process is released by executing the all clear process (step S117), which will be described later.

If a positive determination is made in all of steps S106 to S108, a power-on setting process is executed (step S110). In the power-on setting process, predetermined areas of the main RAM 65 are set to initial values, such as initializing the power outage flag, and a command corresponding to the current game status is sent to the sound and light emission control device 81. Furthermore, after executing the process of step S110, a recognition process (step S111) is executed to have the management IC 66 recognize various information, and a data output process is executed to output various data to an external device connected to the read terminal 68d of the MPU 62 (step S112). Details of these recognition processes and data output processes will be explained later.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited when main processing begins. This state in which timer interrupt processing is prohibited is released when step S112 is completed and before step S113 is executed, and timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 begins, the data output processing of step S112 ends and timer interrupt processing is not executed until before step S113 is started. Therefore, processing to progress the game will not be initiated by the main CPU 63 until this situation occurs.

Then, the remaining processing of steps S113 to S116 proceeds. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there will be a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time will be used to repeatedly execute the remaining processing of steps S113 to S116. In this respect, the remaining processing of steps S113 to S116 can be said to be non-periodic processing that is executed non-periodically.

In the remaining processing, first, in step S113, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing. In the following step S114, a random number initial value update process is executed to update the random number initial value counter CINI, and in step S115, a fluctuation counter update process is executed to update the fluctuation type counter CS. These update processes read the current numerical information from the corresponding counter in the main RAM 65, add 1 to the read numerical information, and then overwrite the counter from which it was read. In this case, when the counter value exceeds the maximum value, it is cleared to "0". Then, in step S116, interrupt permission is set to switch from a state in which timer interrupt processing is prohibited to a state in which it is permitted. After executing step S116, the process returns to step S113, and steps S113 to S116 are repeated.

On the other hand, if the setting key insertion section 68a is turned ON (step S103: YES), all areas in the main RAM 65, including the areas in the main RAM 65 where setting value information indicating the setting state of the pachinko machine 10 is set, are cleared to "0," and the areas cleared to "0" are initialized (step S117). In other words, when an operation to change the setting state of the pachinko machine 10 is performed, all areas in the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the memory areas where the clearing process was performed are initialized. In addition, in step S117, various registers in the main CPU 63 are also cleared to "0" and then initialized. However, this is not limited to this. Even when an operation to change the setting state of the pachinko machine 10 is performed, if the reset button 68c is not pressed, the all-clear process of the main RAM 65 is not executed. However, the all-clear process may be executed when an operation to change the setting state of the pachinko machine 10 is performed and the reset button 68c is pressed.

Then, in step S118, the setting value update process is executed, and in step S119, the setting value update signal output process is executed, after which the process proceeds to step S110. The setting value update process is described below. The setting value update signal output process will be described in detail later. Figure 10 is a flowchart showing the setting value update process.

First, the setting value counter provided in the main RAM 65 is set to "1" (step S201). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value will become "Setting 1" regardless of the previous setting value.

Then, the setting value display start process is executed (step S202). In the setting value display start process, the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the gaming hall manager can understand the current setting status of the pachinko machine 10 by checking the third notification display device 69c.

Subsequently, on the condition that the setting key insertion unit 68a has not been turned OFF (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from LOW level to HIGH level. If a negative determination is made in step S204, the process returns to step S203, where it is determined whether the setting key insertion unit 68a has been turned OFF.

If the update button 68b has been pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). Furthermore, if the value of the setting value counter after incrementing by 1 exceeds "6" (step S206: YES), the setting value counter is set to "1" (step S207). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed; if the update button 68b is pressed once when the setting is "6," the setting will return to "1."

If a negative judgment is made in step S206, or if the processing of step S207 is executed, a display update process for the setting value is executed (step S208). In the display update process for the setting value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter in the main RAM 65 is displayed. By checking the third notification display device 69c, the manager of the gaming hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b.

After executing the processing of step S208, the process returns to step S203, where it is determined whether the setting key insertion unit 68a has been turned OFF. If it has not been turned OFF (step S203: NO), the processing from step S204 onwards is executed again. If it has been turned OFF (step S203: YES), the process of ending the display of the setting value is executed (step S209). In the process of ending the display of the setting value on the third alarm display device 69c, the display of the setting value is ended.

<Timer interrupt processing>
Next, the timer interrupt process will be described with reference to the flowchart of Fig. 11. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

First, the power outage information storage process is executed (step S301). In the power outage information storage process, it monitors whether a power outage signal corresponding to a power outage has been received from the power outage monitoring board 67, and if a power outage is identified, the power outage process is executed and then an infinite loop is entered. In the power outage process, the power outage flag in the main RAM 65 is set to "1", a checksum is calculated, and the calculated checksum is saved.

Then, a lottery random number update process is executed (step S302). In the lottery random number update process, the winning random number counter C1, jackpot type counter C2, reach random number counter C3, and normal power feature release counter C4 are updated. Specifically, the current numerical information is sequentially read from the winning random number counter C1, jackpot type counter C2, reach random number counter C3, and normal power feature release counter C4, and the read numerical information is incremented by 1, after which the read numerical information is overwritten onto the original counter. In this case, when the counter value exceeds the maximum value, it is cleared to "0." Then, in step S303, the random number initial value update process is executed as in step S114, and in step S304, the variable counter update process is executed as in step S115.

Then, a fraud detection process is executed to monitor whether a specific event set as a target for fraud monitoring has occurred (step S305). This fraud detection process monitors the occurrence of multiple types of events, and if a specific event has occurred, a game stop flag stored in the main RAM 65 is set to "1". In the following step S306, it is determined whether the game has stopped by determining whether the game stop flag has been set to "1". If a negative determination is made in step S306, the process from step S307 onwards is executed.

In step S307, port output processing is executed. In port output processing, if output information was set in the previous timer interrupt processing, processing is executed to provide output corresponding to that output information to the various drive units 32b, 34b. For example, if information is set to switch the special power winning device 32 to an open state, output of a drive signal to the special power drive unit 32b is initiated, and if information is set to switch to a closed state, output of the drive signal is stopped. Also, if information is set to switch the normal power device 34a of the second operating port 34 to an open state, output of a drive signal to the normal power drive unit 34b is initiated, and if information is set to switch to a closed state, output of the drive signal is stopped.

Then, a reading process is executed (step S308). In the reading process, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in future processing.

Then, the ball entry detection process is executed (step S309). In this ball entry detection process, the signals received from each ball entry detection sensor 42a-49a are read, and based on the read results, it is determined whether or not a ball has entered the outlet 24a, general entry port 31, special electric entry device 32, first operating port 33, second operating port 34, and through gate 35. Details of the ball entry detection process will be explained later.

Then, a timer update process is executed to collectively update the numerical information of multiple types of timer counters stored in the main RAM 65 (step S310). In this case, the timer counters whose stored numerical information is updated by subtraction are handled collectively, but it is also possible to configure the system to collectively update both subtractive timer counters and additive timer counters.

Then, a launch control process is executed to control the launch of gaming balls (step S311). While the launch operation to the launch operation device 28 continues, one gaming ball is launched every 0.6 seconds, which is the predetermined launch cycle. In the following step S312, an input status monitoring process is performed, which checks for disconnections in each of the ball entry detection sensors 42a-49a and whether the gaming machine main body 12 and front door frame 14 are open, based on the information read in the reading process of step S308.

Then, a special symbol special power control process is executed to control the execution of the game round and the open/close execution mode (step S313). The special symbol special power control process will be explained in detail later.

Then, normal map normal power control processing is executed (step S314). In the normal map normal power control processing, if a win has occurred in the through gate 35, processing is executed to obtain the reserved information on the normal map side, and if reserved information on the normal map side is stored, an opening judgment is made for that reserved information, and processing is executed to perform the normal map performance in response to that opening judgment. Also, based on the result of the opening judgment, processing is executed to open and close the normal power device 34a of the second operating port 34. In this case, if the support mode is low-frequency support mode, corresponding processing is executed, and if the support mode is high-frequency support mode, corresponding processing is executed. Also, if the opening/closing execution mode is selected, the support mode immediately before will be low-frequency support mode even if it was high-frequency support mode.

In the following step S315, based on the processing results of the immediately preceding steps S313 and S314, output information is set to reflect the increase or decrease in the number of reserved information items related to the special map display unit 37a in the special map reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information items related to the regular map display unit 38a in the regular map reserved display unit 38b. Also, in step S315, based on the processing results of the immediately preceding steps S313 and S314, output information is set to update the display content of the special map display unit 37a, and output information is set to update the display content of the regular map display unit 38a.

Then, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation results (step S316). A payout output process is also executed to set the prize ball command as the output target (step S317). An external information setting process is also executed to control the start and end of the output of external signals according to the results of the various processes executed in this timer interrupt process (step S318). A management output process is then executed to output information corresponding to the result of the game ball entering the game area PA to the management IC 66 (step S319). Details of the management output process will be explained later.

Next, the special image special power control process of step S313 will be explained with reference to the flowchart in Figure 12.

First, the system executes a pending information acquisition process (step S401). This process determines whether a win has occurred in the first actuation port 33 or the second actuation port 34. If a win has occurred, the system determines whether the number of pending balls in the pending ball storage area 65a is less than the upper limit ("4" in this embodiment). If the number of pending balls is less than the upper limit, the system increments the number of pending balls by one, and stores the numerical information of the hit random number counter C1, jackpot type counter C2, and reach random number counter C3 updated in the previous step S302 in the first of the available pending areas RE1-RE4 in the pending ball area RE. If a win occurs simultaneously in both the first actuation port 33 and the second actuation port 34, the system executes the process to acquire the pending information multiple times within the scope of one execution of the pending information acquisition process. Furthermore, if new pending balls are acquired, a corresponding acquisition command is sent to the audio/light-emitting control device 81. When the audio and light control device 81 receives this command, it updates the image displayed on the pattern display device 41, indicating the number of pending information items, to display content corresponding to the increase in pending information items.

Then, the information of the special pattern special power counter stored in the main RAM 65 is read (step S402), and the special pattern special power address table stored in the main ROM 64 is read (step S403). The start address corresponding to the information of the special pattern special power counter is obtained from the special pattern special power address table (step S404), and the process jumps to the process indicated by the obtained start address among the processes of steps S406 to S412 (step S405). The special pattern special power counter is a counter that allows the main CPU 63 to determine which of the various processes of steps S406 to S412 should be executed, and the special pattern special power address table is set with the start address of the program for executing the processes of steps S406 to S412 corresponding to the numerical information of the special pattern special power counter.

In step S406, the special chart change start process is executed. Figure 13 is a flowchart showing the special chart change start process.

In the special chart change start process, if the number of reserved information items stored in the reserved area RE is one or more (step S501: YES), the data setting process is executed (step S502). In the data setting process, the number of reserved items is first decremented by one, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. Then, the data stored in each of the reserved areas RE1-RE4 of the reserved area RE is shifted. This data shift process shifts the data stored in the first reserved area RE1-RE4 sequentially to the lower-level areas. Specifically, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, the third reserved area RE3 to the second reserved area RE2, and the fourth reserved area RE4 to the third reserved area RE3, and then the fourth reserved area RE4 is cleared to "0." At this time, a shift command is sent to the audio and light control device 81 to acknowledge that the reserved area data has been shifted. When the audio and light control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to display content corresponding to the reduction in pending information items.

After executing the data setting process, the win/loss table is read from the main ROM 64 (step S503). Specifically, the current win/loss lottery mode is determined by first reading information indicating the win/loss lottery mode from the main RAM 65. If it is the high probability mode, the high probability win/loss table 64g is read from the main ROM 64. On the other hand, if it is the low probability mode, the setting state of the pachinko machine 10 is determined by reading the value of the setting value counter in the main RAM 65. Then, the low probability win/loss tables 64a to 64f corresponding to the determined setting value are read from the main ROM 64.

Then, the system executes a win/loss determination process by referencing the win/loss tables 64a-64g read in step S503 (step S504). In the win/loss determination process, it determines whether the information stored in the execution area AE for determining win/loss, i.e., the numerical information related to the win random number counter C1, matches the jackpot numerical information set in the win/loss tables 64a-64g read in step S503.

If the result of the win/loss determination process is a jackpot win (step S505: YES), the allocation determination process is executed (step S506). In the allocation determination process, the allocation determination information stored in the execution area AE, i.e., the numerical information related to the jackpot type counter C2, is read. Then, by referencing the allocation table 64h provided in the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out corresponds to. Specifically, it is determined which jackpot result it corresponds to: a low-probability jackpot result, a low-prize high-probability jackpot result, or a most favorable jackpot result.

Then, the stop result setting process for the jackpot result is executed (step S507). Specifically, information on the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for the jackpot result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the pattern to be stopped and displayed on the special symbol display unit 37a is set differently for each type of jackpot result.

Then, a flag setting process corresponding to the allocation determination result is executed (step S508). Specifically, flags corresponding to each type of jackpot result are provided in the main RAM 65, and in step S508, the flag corresponding to the result of the allocation determination process in step S506 is set to "1".

On the other hand, if it is determined in step S505 that the result is not a jackpot, the stop result setting process for a losing result is executed (step S509). Specifically, information on the pattern type to be finally displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for losing results that is pre-stored in the main ROM 64, and the identified information is written to the main RAM 65. The information on the pattern type selected in this case is different from the information on the pattern type selected in the case of a jackpot result.

After executing either step S508 or step S509, a process for determining the duration of the game round is executed (step S510). In this process, the numerical information of the fluctuation type counter CS is obtained. In addition, it is determined whether a reach display will occur on the pattern display device 41 in the current game round. Specifically, if the game round related to the start of the current fluctuation results in a low-probability jackpot result or a most favorable jackpot result, it is determined that a reach display will occur. In addition, if neither of these jackpot results are obtained, and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

If it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of play times corresponding to the current numerical information of the variable type counter CS. On the other hand, if it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of play times corresponding to the current numerical information of the variable type counter CS. Incidentally, the duration of play times that can be obtained by reference to the reach non-occurrence duration table differs from the duration of play times that can be obtained by reference to the reach occurrence duration table.

The duration of play times when a reach does not occur is set so that the greater the number of reserved information stored in the reserved area RE, the shorter the duration of play times. Furthermore, the non-reach duration table is set so that a shorter duration of play times is selected when the support mode is high-frequency support mode than when it is low-frequency support mode, when the number of reserved information is the same. However, this is not limited to this, and the duration of play times may not change depending on the number of reserved information or support mode, or the above relationship may be reversed. Furthermore, the above configuration may be applied to the duration of play times when a reach occurs. Separate duration tables may also be set for various jackpot results, miss reach results, and miss results without a reach. In this case, the duration of play times will be allocated according to each play result.

Then, the information on the duration of the game round obtained in step S510 is set in the special symbol special power timer counter provided in the main RAM 65 (step S511). The numerical information set in the special symbol special power timer counter is updated in the timer update process (step S310). Incidentally, as a performance for a game round, the special symbol display unit 37a displays changing patterns, and the pattern display device 41 displays changing patterns. When each of these changing displays ends, the stop result of that game round is displayed (the pattern display device 41 displays a state in which a specified pattern combination is waiting on the active line) and the final stop is displayed for the final stop period (e.g., 0.5 seconds). In this case, the duration of the game round obtained in step S510 is the total time for one game round.

Then, the variation command and type command are sent to the audio and light emitting control device 81 (step S512). The variation command includes information on the duration of the game round. Here, as described above, the duration of the game round obtained by referencing the non-reach duration table is different from the duration of the game round obtained by referencing the reach duration table. Therefore, even if the variation command does not include information on whether or not a reach has occurred, the audio and light emitting control device 81 can determine whether or not a reach has occurred from the information on the duration of the game round. In this regard, it can be said that the variation command includes information indicating whether or not a reach has occurred. Note that the variation command may also include information directly indicating whether or not a reach has occurred. Furthermore, the type command includes information on the game result.

When the sound and light-emitting control device 81 receives a variation command and a type command from the main CPU 63, it causes the display light-emitting unit 53, speaker unit 54, and pattern display device 41 to execute a game-round performance. In this case, the performance for that game round is executed in a manner corresponding to the content of the variation command and type command. In addition, the pattern display device 41 displays a variation of the patterns as a game-round performance, and when the performance for that game round ends, a combination of patterns corresponding to the results of the win/loss determination process and the allocation determination process is displayed frozen.

Then, the display of the changing image on the special symbol display unit 37a begins (step S513). Then, the special symbol special power counter is incremented by 1 (step S514). In this case, the numerical information of the special symbol special power counter is "0" when the special symbol change start process is executed, so the numerical information of the special symbol special power counter becomes "1". Then, the 11th output flag provided in the main RAM 65 is set to "1" (step S515). The 11th output flag is a flag that specifies to the main CPU 63 that information indicating that a game round has started should be output to the management IC 66.

Returning to the explanation of the special symbol special power control process (Figure 52), in step S407, special symbol change processing is executed. In special symbol change processing, it is determined whether the timing is within the duration of a game round and before the final stop display, and if it is before the final stop display, processing is executed to regularly change the display mode of the image on the special symbol display unit 37a. When it is time to display the final stop, the numerical information of the special symbol special power counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special symbol change processing to that corresponding to the special symbol confirmation processing. Note that in this embodiment, a final stop command is not sent from the main CPU 63 to the audio and light emission control device 81.

In step S408, special chart determination processing is executed. In special chart determination processing, the display mode of the image on the special chart display unit 37a is changed to a display mode corresponding to the lottery result of the current game round. In addition, in special chart determination processing, it is determined whether the final stop period has elapsed, and if that period has elapsed, it is determined whether a transition to opening and closing execution mode will occur. If a transition to opening and closing execution mode does not occur, the numerical information of the special chart special power counter is cleared to "0". If a transition to opening and closing execution mode occurs, the numerical information of the special chart special power counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart determination processing to that corresponding to the special power start processing.

In step S409, special power start processing is executed. During the special power start processing, if the processing to start the opening period in the current open/close execution mode has not yet been executed, the processing to set the opening period is executed. An opening command is also sent to the audio and light emitting control device 81. Upon receiving the opening command, the audio and light emitting control device 81 causes the display light emitting unit 53, speaker unit 54, and symbol display device 41 to execute an opening effect. If the opening period has elapsed, start processing is executed to start the first round of play. In this start processing, the special power winning device 32 is set to an open state and the end conditions for the round of play are set. When setting this end condition, the upper limit of the duration for which the special power winning device 32 is to remain open during this first round of play is set, and the upper limit of the number of game balls that can win the special power winning device 32 during this first round of play is set in the winning number counter provided in the main RAM 65.

In step S410, special line open processing is executed. In special line open processing, it is determined whether the conditions for ending the round of play have been met. If the conditions for ending have been met, the special line winning device 32 is closed. If the round of play that has just ended is not the last round of play executed, the numerical information of the special line special line counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line closed processing. If the round of play that has just ended is the last round of play executed, the numerical information of the special line special line counter is incremented by 2, thereby updating the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line end processing.

In step S411, special line closed processing is executed. In special line closed processing, it is determined whether the interval period between rounds of play has elapsed. The interval period is set when the previous round of play ends. If the interval period has elapsed, the special line winning device 32 is set to an open state and the end conditions for the round of play are set. Then, the numerical information of the special chart special line counter is subtracted by 1, thereby updating the numerical information of the counter from that corresponding to the special line closed processing to that corresponding to the special line open processing.

In step S412, the special call termination process is executed. In the special call termination process, if the process to start the ending period for this opening/closing execution mode has not yet been executed, the ending period (for example, 5 seconds) is set and an ending command is sent to the audio and light emitting control device 81. Upon receiving the ending command, the audio and light emitting control device 81 causes the display light emitting unit 53, speaker unit 54, and pattern display device 41 to execute an ending performance. When the ending period has elapsed, the win/lose lottery mode and support mode after the end of the opening/closing execution mode are set to the modes corresponding to the jackpot result that triggered the start of this opening/closing execution mode.

Next, we will explain the configuration used by the main CPU 63 to determine whether or not a game ball has entered the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, second operating port 34, and through gate 35 based on the detection results of each ball entry detection sensor 42a-49a. Figure 14 is an explanatory diagram illustrating the configuration used to input the detection results of the ball entry detection sensors 42a-49a to the main CPU 63.

The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so that it can handle eight types of signals simultaneously. An area where information of "0" or "1" is stored depending on the voltage of each signal is provided in one-to-one correspondence with each terminal. In other words, this area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals can be input to the input port 63a, in order to limit the number of signals that can be input simultaneously to eight, the group of signals that are input to the input port 63a is switched through switching control by a driver IC.

During the ball entry detection process (step S309) of the timer interrupt process (Figure 11), the signals to be input to input port 63a are set to the signals from each ball entry detection sensor 42a-49a. When this setting is made, bit 0 D0 stores information corresponding to the detection signal from the first prize entry detection sensor 42a, bit 1 D1 stores information corresponding to the detection signal from the second prize entry detection sensor 43a, bit 2 D2 stores information corresponding to the detection signal from the third prize entry detection sensor 44a, bit 3 D3 stores information corresponding to the detection signal from the special electric current detection sensor 45a, bit 4 D4 stores information corresponding to the detection signal from the first operation port detection sensor 46a, bit 5 D5 stores information corresponding to the detection signal from the second operation port detection sensor 47a, bit 6 D6 stores information corresponding to the detection signal from the outlet detection sensor 48a, and bit 7 D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

Each of the ball entry detection sensors 42a-49a outputs a LOW level signal indicating that it is not currently detecting a passing game ball as a detection signal when it has not detected the passing of a game ball, and outputs a HIGH level signal indicating that it is currently detecting a passing game ball as a detection signal when it has detected the passing of a game ball. Input port 63a stores a "0" in the corresponding bit when it receives a LOW level signal, and stores a "1" in the corresponding bit when it receives a HIGH level signal. In other words, when the ball entry detection sensors 42a-49a have not detected the passing of a game ball, a "0" corresponding to the information indicating that it is not currently detecting is stored in the corresponding bit, and when it has detected the passing of a game ball, a "1" corresponding to the information indicating that it is currently detecting is stored in the corresponding bit.

Figure 15 is a flowchart showing the ball entry detection process executed in step S309 of the timer interrupt process (Figure 11).

If it is confirmed that the 0th bit D0 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first prize opening detection sensor 42a (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by one (step S603). The first output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the first prize opening detection sensor 42a should be output to the management IC 66. The 10-prize ball counter is a counter that specifies to the main CPU 63 the number of times that 10 game balls should be paid out. If the value of the 10 prize ball counter is 1 or greater, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Figure 11), and the value of the 10 prize ball counter is decremented by 1 each time the 10 prize ball command is output. When the payout control device 77 receives a 10 prize ball command, it controls the drive of the payout device 76 so that 10 game balls are paid out.

If it is confirmed that the first bit D1 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second winning opening detection sensor 43a (step S604: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S605), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S606). The second output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the second winning opening detection sensor 43a should be output to the management IC 66.

If it is confirmed that the second bit D2 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the third winning opening detection sensor 44a (step S607: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S608), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S609). The third output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the third winning opening detection sensor 44a should be output to the management IC 66.

If it is confirmed that the third bit D3 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the special electric detection sensor 45a (step S610: YES). In this case, the special electric winning flag in the main RAM 65 is set to "1" (step S611), the fourth output flag in the main RAM 65 is set to "1" (step S612), and the value of the 15-ball counter in the main RAM 65 is incremented by 1 (step S613). The special electric winning flag is a flag that the main CPU 63 uses to identify that one game ball has entered the special electric winning device 32 during round play in the open/close execution mode. The special power control process (step S313) of the timer interrupt process (FIG. 11) determines that one game ball has entered the special power winning device 32 by confirming that the special power winning flag is set to "1," and subtracts one from the remaining number of balls that can enter the special power winning device 32 during a round of play. When this process of subtracting one from the number of balls that can enter is executed, the special power winning flag is cleared to "0." The fourth output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the special power detection sensor 45a should be output to the management IC 66. The 15-ball counter is a counter that specifies to the main CPU 63 the number of times that 15 game balls should be paid out. If the value of the 15 prize ball counter is 1 or greater, a 15 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Figure 11), and the value of the 15 prize ball counter is decremented by 1 each time the 15 prize ball command is output. When the payout control device 77 receives a 15 prize ball command, it controls the drive of the payout device 76 so that 15 game balls are paid out.

If it is confirmed that the fourth bit D4 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first actuation port detection sensor 46a (step S614: YES). In this case, the first actuation winning flag stored in the main RAM 65 is set to "1" (step S615), the fifth output flag stored in the main RAM 65 is set to "1" (step S616), and the value of the one-prize ball counter stored in the main RAM 65 is incremented by one (step S617). The first actuation winning flag is a flag used by the main CPU 63 to identify that one game ball has entered the first actuation port 33. The special power control process (step S313) of the timer interrupt process (Figure 11) confirms that the first activation winning flag is set to "1." This process executes a process to store new reserved information, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. The special power control process (step S313) confirms that the first activation winning flag is set to "1." If the process corresponding to this confirmation is executed, the first activation winning flag is cleared to "0." The fifth output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the first activation port detection sensor 46a should be output to the management IC 66. The single prize ball counter is a counter that specifies to the main CPU 63 the number of times one game ball should be paid out. If the value of the 1 prize ball counter is 1 or greater, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Figure 11), and the value of the 1 prize ball counter is decremented by 1 each time the 1 prize ball command is output. When the payout control device 77 receives a 1 prize ball command, it controls the operation of the payout device 76 so that one game ball is paid out.

If it is confirmed that the fifth bit D5 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second actuation port detection sensor 47a (step S618: YES). In this case, the second actuation winning flag provided in the main RAM 65 is set to "1" (step S619), the sixth output flag provided in the main RAM 65 is set to "1" (step S620), and the value of the one prize ball counter provided in the main RAM 65 is incremented by 1 (step S621). The second actuation winning flag is a flag used by the main CPU 63 to identify that one game ball has entered the second actuation port 34. The special power control process (step S313) of the timer interrupt process (Figure 11) confirms that the second activation winning flag is set to "1" and executes a process to store new reserved information, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. The special power control process (step S313) confirms that the second activation winning flag is set to "1" and clears the second activation winning flag to "0" when the process corresponding to that confirmation is executed. The sixth output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the second activation port detection sensor 47a should be output to the management IC 66.

If it is confirmed that the sixth bit D6 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the outlet detection sensor 48a (step S622: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S623). The seventh output flag is a flag that specifies to the main CPU 63 that information indicating that one gaming ball has been detected by the outlet detection sensor 48a should be output to the management IC 66.

If it is confirmed that the seventh bit D7 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, the gate winning flag stored in the main RAM 65 is set to "1" (step S625). The gate winning flag is a flag used by the main CPU 63 to identify that one game ball has entered the through gate 35. In the normal play control process (step S314) of the timer interrupt process (Figure 11), by confirming that the gate winning flag is set to "1," the process is executed to store the current numerical information of the normal play device release counter C4 as normal play device pending information in the normal play device pending area 65c, provided that the number of normal play device pending information stored in the normal play device pending area 65c is less than the upper limit of four. The normal map and normal power control process (step S314) confirms that the gate winning flag is set to "1", and if processing corresponding to that confirmation is executed, the gate winning flag is cleared to "0".

As already explained, the timer interrupt process (Figure 11) is initiated at a 4 millisecond cycle. Therefore, when one of the ball entry detection sensors 42a-49a begins detecting a single game ball, the main CPU 63 determines that one game ball has been detected by that ball entry detection sensor 42a-49a while that sensor continues to detect that single game ball. Therefore, it is sufficient to provide one each of the first through seventh output flags.

Next, we will explain the processing executed by the dispensing control device 77. First, we will explain the electrical configuration of the dispensing control device 77 and the various devices that communicate with the dispensing control device 77, with reference to the block diagram in Figure 16.

The dispensing control device 77 is equipped with an MPU 91. In addition to a dispensing side CPU 92, which is a processing device including a control unit and a calculation unit, the MPU 91 also contains a dispensing side ROM 93, a dispensing side RAM 94, an interrupt circuit, a timer circuit, a data input/output circuit, etc.

The payout-side ROM 93 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The payout-side ROM 93 stores various control programs and fixed value data executed by the payout-side CPU 92.

The dispensing-side RAM 94 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM or DRAM, and is used for both reading and writing. The dispensing-side RAM 94 is randomly accessible and takes less time to read data than the dispensing-side ROM 93 when compared for the same data capacity. The dispensing-side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing-side ROM 93.

The payout CPU 92 is capable of bidirectional communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout CPU 92 controls the payout device 76 to pay out the number of game balls corresponding to the prize ball command. The payout CPU 92 also monitors whether the payout of game balls can be performed normally, and if it determines that the payout of game balls cannot be performed normally, it stops the payout device 76 even if information on the number of unpaid prize balls is stored in the payout RAM 94. The payout CPU 92 also transmits a payout limit command to the main CPU 63 indicating that the payout of game balls cannot be performed normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the audio/light-emitting control device 81 so that the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54 issue a notification indicating that the payout of game balls cannot be performed normally. The states in which game balls cannot be paid out normally include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been replenished with game balls, an abnormal payout state in which the payout device 76 is not operating normally, a main body open state in which the gaming machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

A full tank detection sensor (not shown) is provided midway along the game ball passageway leading from the payout device 76 to the lower tray 56a, and the detection results of this full tank detection sensor are input to the payout CPU 92. The payout CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

A no-ball detection sensor (not shown) is provided midway along the game ball passageway leading from the tank 75 to the payout device 76, and the detection results of the no-ball detection sensor are input to the payout CPU 92. The payout CPU 92 determines that a no-ball state exists when the no-ball detection sensor continues to not detect game balls, and determines that the no-ball state has been lifted when the state in which the no-ball detection sensor continues to not detect game balls is lifted.

The payout device 76 is provided with a payout detection sensor (not shown) for detecting game balls paid out from the payout device 76, and the detection results of the payout detection sensor are input to the payout side CPU 92. The payout side CPU 92 determines that one game ball has been paid out from the payout device 76 when a game ball is detected by the payout detection sensor. Furthermore, the payout side CPU 92 determines that an abnormal payout state exists when the payout detection sensor continues to not detect a game ball even though the payout device 76 is being driven and controlled so that a game ball is paid out, and determines that the abnormal payout state has been released when the state in which the payout detection sensor continues to not detect a game ball is released.

A front door open sensor 95 is provided on the front portion of the inner frame 13 (see FIG. 2 ), and the detection result of the front door open sensor 95 is input to the dispensing-side CPU 92. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing-side CPU 92, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that the front door frame 14 is closed when it receives a closed detection signal from the front door open sensor 95, and determines that the front door frame 14 is open when it receives an open detection signal from the front door open sensor 95. In addition, the dispensing-side CPU 92 transmits a front door open command to the main-side CPU 63 when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main-side CPU 63 when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in the open state when it receives a front door open command, and determines that the front door frame 14 is in the closed state when it receives a front door close command.

A main body open sensor 96 is provided on the front of the back pack unit 15 (see FIG. 2 ), and the detection result of the main body open sensor 96 is input to the payout CPU 92. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the payout CPU 92, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the payout CPU 92. The payout CPU 92 determines that the gaming machine main body 12 is in a closed state when it receives a closed detection signal from the main body open sensor 96, and determines that the gaming machine main body 12 is in an open state when it receives an open detection signal from the main body open sensor 96. In addition, the payout CPU 92 transmits a main body open command to the main CPU 63 when it determines that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body close command to the main CPU 63 when it determines that the gaming machine main body 12 has changed from an open state to a closed state. The main CPU 63 determines that the gaming machine main body 12 is in the open state when it receives a main body open command, and determines that the gaming machine main body 12 is in the closed state when it receives a main body close command.

Referring to the flowchart in Figure 17, we will explain the timer interrupt processing executed by the dispensing CPU 92. The timer interrupt processing is repeatedly activated at a predetermined interval (e.g., every 2 milliseconds).

First, full tank processing is executed (step S701). As already explained, full tank processing determines whether the tank is full based on the detection results of the full tank detection sensor, and if the tank is full, it executes processing to stop the payout of game balls and sends a command to the main CPU 63 indicating that the tank is full. Furthermore, if the full tank state is released, it executes processing to enable the payout of game balls and sends a command to the main CPU 63 indicating that the full tank state has been released.

Then, no-ball processing is executed (step S702). As already explained, the no-ball processing determines whether or not the state is a no-ball state based on the detection results of the no-ball detection sensor, and if the state is a no-ball state, it executes processing to stop the payout of game balls and sends a command to the main CPU 63 indicating that the no-ball state is in effect. Furthermore, if the no-ball state is released, it executes processing to enable the payout of game balls and sends a command to the main CPU 63 indicating that the no-ball state has been released.

Then, a payout abnormality monitoring process is executed (step S703). As already explained, the payout abnormality monitoring process determines whether or not a payout abnormality state exists based on the detection results of the payout detection sensor, and if a payout abnormality state exists, a process is executed to stop the payout of game balls and a command indicating that a payout abnormality state exists is sent to the main CPU 63. Furthermore, if the payout abnormality state is resolved, a process is executed to enable the payout of game balls and a command indicating that the payout abnormality state has been resolved is sent to the main CPU 63.

Then, a front door open monitoring process is executed (step S704). As already explained, the front door open monitoring process determines whether the front door frame 14 is open or not based on the detection results of the front door open sensor 95. If the front door frame 14 is open, a process is executed to stop the payout of game balls, and a front door open command is sent to the main CPU 63. Furthermore, if the front door frame 14 is closed, a process is executed to enable the payout of game balls, and a front door close command is sent to the main CPU 63.

Then, the main body open monitoring process is executed (step S705). As already explained, the main body open monitoring process determines whether the gaming machine main body 12 is in the open state based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is in the open state, it executes a process to stop the payout of game balls and sends a main body open command to the main CPU 63. Furthermore, if the gaming machine main body 12 is closed, it executes a process to enable the payout of game balls and sends a main body close command to the main CPU 63.

Then, a command reading process is executed (step S706). In this command reading process, a process is executed to read the prize ball command sent by the main CPU 63 and store the prize ball command in the payout RAM 94. Then, a prize ball setting process is executed to add the number corresponding to the received prize ball command to the unpaid prize ball count information in the payout RAM 94 (step S707), and then a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S708). In the payout control process, if the unpaid prize ball count information stored in the payout RAM 94 is a value of 1 or greater, the payout device 76 is driven and controlled, and if the payout detection sensor detects one game ball, the value of the prize ball count information is decremented by 1. Then, if the value of the prize ball count information becomes "0," the drive control of the payout device 76 is stopped. After that, an external information setting process is executed to control the start and end of external signal output according to the results of the various processes executed during this timer interrupt process (step S709).

Next, we will explain the configuration for externally outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall.

As shown in FIG. 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with a large number of external terminals, some of which are electrically connected to the main CPU 63, and some of which are electrically connected to the payout CPU 92. Because the main CPU 63 and the payout CPU 92 are each electrically connected to the external terminal board 97 in this way, the main CPU 63 and the payout CPU 92 can externally output information to the hall computer HC, as shown in FIG. 16.

One external terminal on the external terminal board 97 is electrically connected to the front door open sensor 95, and another external terminal on the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the detailed configuration of this electrical connection, a signal relay board 98 is provided midway along the signal path from the front door open sensor 95 to the dispensing side CPU 92. The signal relay board 98 has a branch path SL2 that branches off from the signal path SL1 from the front door open sensor 95 to the dispensing side CPU 92. The branch path SL2 is then connected to the front door open external terminal on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the dispensing side CPU 92, but also to the front door open external terminal on the external terminal board 97. This allows a signal indicating whether the front door frame 14 is open to be output to the hall computer HC without control by the dispensing side CPU 92.

Regarding the main body open sensor 96 in more detail, the signal relay board 98 has a branch path SL4 that branches off from the signal path SL3 that runs from the main body open sensor 96 to the payout side CPU 92. This branch path SL4 is then connected to an external terminal for main body open on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the main body open sensor 96 is not only input to the payout side CPU 92, but also to the external terminal for main body open on the external terminal board 97. This makes it possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through control by the payout side CPU 92.

Next, we will explain the content of the information externally output from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, we will explain the content of the information externally output from the main CPU 63 to the hall computer HC.

During the external information setting process (step S318) in the timer interrupt process (Figure 11), the main CPU 63 sets information output to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the opening/closing execution mode is in progress, information indicating that the support mode is in high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (e.g., 100) of game balls have been discharged from the game area PA through the outlet 24a, general winning port 31, special electric winning device 32, first actuation port 33, or second actuation port 34, information indicating that a game ball has entered the first actuation port 33, and information indicating that a game ball has entered the second actuation port 34.

In the external information setting process (step S709) of the timer interrupt process (FIG. 17), the payout CPU 92 sets the output of information to each external terminal assigned to the payout CPU 92 on the external terminal board 97. The information output from the payout CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

The hall computer HC can grasp the manner in which game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example,
The payout rate, which is the ratio of the number of payout balls generated until 100 game balls are discharged from the game area PA of the pachinko machine 10. The payout rate in a normal game state other than the open/close execution mode and the high frequency support mode (hereinafter, this payout rate will be referred to as "B")
・Ball payout rate in the open/close execution mode ・Ball payout rate in the high frequency support mode ・Number of games played until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this rate will be referred to as "S")
B-S x "number of winning balls for winning the first actuation port 33 and the second actuation port 34"
The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1")
The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2")
B - (S1 x "number of winning balls for winning through the first actuation port 33" + S2 x "number of winning balls for winning through the second actuation port 34")
The probability of the opening/closing execution mode occurring per unit play, the probability of the high frequency support mode occurring per unit play, etc. are calculated. This allows the hall computer HC to manage the ball entry patterns of game balls in the play area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls paid out when one game ball enters the corresponding ball entry section.

<Configuration for managing winning status of gaming balls>
Next, we will explain the configuration for managing game history using the management IC 66. First, we will explain the electrical configuration of the management IC 66 with reference to the block diagram of FIG.

As already explained, the MPU 62 of the main control unit 60 is equipped with a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 is also equipped with an I/F 101, as well as the read terminal 68d already explained.

I/F 101 is an interface for sending and receiving signals between the MPU 62 and devices external to it. I/F 101 is electrically connected to the main CPU 63 via the internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a-49a and commands from the payout CPU 92 are input to the MPU 62 through the input port of I/F 101, and the main CPU 63 executes various processes based on the input detection results and command content, as previously explained. Furthermore, if a signal is output to a device such as the special power driver 32b as a result of various processes executed by the main CPU 63, the signal is output through the output port of I/F 101. Furthermore, if a command is output to the payout CPU 92 and the audio/light-emitting control device 81 as a result of various processes executed by the main CPU 63, the command is output through the output port of I/F 101.

The management IC 66 includes a management I/F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, a history memory 117, and a calculation result memory 131. These devices are connected to each other via an internal bus 66a provided in the management IC 66, allowing bidirectional communication.

The management side I/F 111 is an interface that receives various signals from the main CPU 63 via a group of one-way communication signal paths 118 built into the MPU 62, and transmits various signals to the reading terminal 68d via a group of one-way communication signal paths 119 built into the MPU 62. Various signals from the main CPU 63 are input to the input port of the management side I/F 111, and various signals to the reading terminal 68d are output from the output port of the management side I/F 111. The main CPU 63 is electrically connected to the reading terminal 68d via a group of two-way communication signal paths 120 built into the MPU 62.

The management CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management ROM 113 is a memory such as a NOR flash memory or a NAND flash memory that does not require an external power supply to retain its data (i.e., a non-volatile storage means) and is used as read-only. The management ROM 113 stores various control programs executed by the management CPU 112 and fixed value data. The management RAM 114 is a memory such as an SRAM or DRAM that requires an external power supply to retain its data (i.e., a volatile storage means) and is used as both read and write. The management RAM 114 is randomly accessible and has a faster read time than the management ROM 113 when compared for the same data capacity. The management RAM 114 temporarily stores various data and the like in response to the execution of the control programs stored in the management ROM 113.

The RTC 115 is a real-time clock that constantly measures date and time information and is capable of outputting the measured date and time information (hereinafter also referred to as date and time information) in accordance with instructions from the management CPU 112. The RTC 115 is also equipped with a backup power supply, making it possible to measure date and time information even when the power to the pachinko machine 10 is cut off.

The correspondence memory 116 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM or DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a-122p provided in the input port 121 of the management side I/F 111 and the types of signals input to those buffers 122a-122p. The contents of the correspondence memory 116 will be explained in detail later.

The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information related to the game history received from the main CPU 63 via the management I/F 111. Details of the contents of the history memory 117 will be explained later.

The calculation result memory 131 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or NAND flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c, and are also output to an external device connected to the read terminal 68d.

Next, we will explain the configuration of the input port 121 provided in the management side I/F 111. Figure 19 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I/F 111.

The input port 121 is provided with multiple buffers 122a-122p. Specifically, first through sixteenth buffers 122a-122p are provided. Each of the first through sixteenth buffers 122a-122p can input one type of signal via signal paths 118a-118p, and each of the first through sixteenth buffers 122a-122p stores "0" as first data when the input signal is at a LOW level, and stores "1" as second data when the input signal is at a HIGH level. Note that the relationship between LOW and HIGH and the first and second data may be reversed.

A first signal corresponding to the detection result of the first winning opening detection sensor 42a is input to the first buffer 122a. In this case, the main CPU 63 outputs a LOW level first signal when no new gaming balls are detected by the first winning opening detection sensor 42a, and outputs a HI level first signal for a specific period of time when one gaming ball is detected by the first winning opening detection sensor 42a. This specific period is long enough for the management CPU 112 to determine that a HI level first signal has been input to the first buffer 122a.

A second signal corresponding to the detection result of the second winning opening detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a LOW level second signal when no new game balls are detected by the second winning opening detection sensor 43a, and outputs a HI level second signal for a specific period of time when one game ball is detected by the second winning opening detection sensor 43a. This specific period is long enough for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

A third signal corresponding to the detection result of the third winning opening detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a LOW level third signal when no new gaming balls are detected by the third winning opening detection sensor 44a, and outputs a HI level third signal for a specific period of time when one gaming ball is detected by the third winning opening detection sensor 44a. This specific period is long enough for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

A fourth signal corresponding to the detection result of the special electric detection sensor 45a is input to the fourth buffer 122d. In this case, the main CPU 63 outputs a LOW level fourth signal when no new gaming balls are detected by the special electric detection sensor 45a, and outputs a HI level fourth signal for a specific period of time when one gaming ball is detected by the special electric detection sensor 45a. This specific period is long enough for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

A fifth signal corresponding to the detection result of the first actuation port detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a LOW level fifth signal when no new game balls are detected by the first actuation port detection sensor 46a, and outputs a HI level fifth signal for a specific period of time when one game ball is detected by the first actuation port detection sensor 46a. This specific period is long enough for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW level sixth signal when no new game balls are detected by the second actuation port detection sensor 47a, and outputs a HI level sixth signal for a specific period of time when one game ball is detected by the second actuation port detection sensor 47a. This specific period is long enough for the management CPU 112 to determine that a HI level sixth signal has been input to the sixth buffer 122f.

A seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g. In this case, the main CPU 63 outputs a LOW level seventh signal when no new gaming balls are detected by the outlet detection sensor 48a, and outputs a HI level seventh signal for a specific period of time when one gaming ball is detected by the outlet detection sensor 48a. This specific period is long enough for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

An eighth signal corresponding to whether or not the open/close execution mode is in progress is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs a low-level eighth signal when the open/close execution mode is not in progress, and continuously outputs a high-level eighth signal when the open/close execution mode is in progress.

A ninth signal corresponding to whether or not the high-frequency support mode is in effect is input to the ninth buffer 122i. In this case, the main CPU 63 continuously outputs a LOW-level ninth signal when the high-frequency support mode is not in effect, and continuously outputs a HI-level ninth signal when the high-frequency support mode is in effect.

A tenth signal corresponding to whether or not the front door frame 14 is open is input to the tenth buffer 122j. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

An 11th signal corresponding to whether or not a game turn has started is input to the 11th buffer 122k. In this case, the main CPU 63 continues to output a LOW level 11th signal until a game turn starts, and once a game turn has started, outputs a HI level 11th signal for a specific period of time. This specific period is long enough for the management CPU 112 to determine that a HI level 11th signal has been input to the 11th buffer 122k.

A setting value update signal is input to the 15th buffer 122o to make the management CPU 112 aware that the main CPU 63 has newly set the setting state of the pachinko machine 10. In this case, the main CPU 63 outputs a LOW level setting value update signal when no new setting state has been set for the pachinko machine 10, and when a new setting state has been set for the pachinko machine 10, it outputs a HI level setting value update signal, a pulse signal that is maintained for a specific period of time, for the number of times corresponding to the newly set value. This specific period is long enough for the management CPU 112 to identify that a HI level setting value update signal has been input to the 15th buffer 122o.

An output instruction signal is input to the 16th buffer 122p to cause the management CPU 112 to recognize the opportunity to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output history information, and outputs a HIGH level output instruction signal for a specific period when there is a need to output history information. This specific period is long enough for the management CPU 112 to determine that a HIGH level output instruction signal has been input to the 16th buffer 122p.

Although the twelfth buffer 122l, thirteenth buffer 122m, and fourteenth buffer 122n can receive signals from the main CPU 63, they are blank and do not receive normal signals in this pachinko machine 10. In this way, by providing a greater number of buffers 122a-122p as input ports 121 of the management I/F 111 in this pachinko machine 10 than the number of signals output from the main CPU 63 to the management IC 66, it is possible to use the management IC 66 in models other than this pachinko machine 10. This increases the versatility of the management IC 66. Incidentally, signal paths 118a-118p are formed between the primary CPU 63 and the first through sixteenth buffers 122a-122p, respectively, in a one-to-one correspondence with the first through sixteenth buffers 122a-122p, but this is not limited to this, and the signal paths 118l-118n may not be formed between the primary CPU 63 and the buffers 122l-122n to be blanked.

The fact that a set value update signal is input to the 15th buffer 122o and that an output instruction signal is input to the 16th buffer 122p was determined during the design stage of the management IC 66, and the management CPU 112 can determine that a set value update signal is input to the 15th buffer 122o and that an output instruction signal is input to the 16th buffer 122p without receiving instructions from the main CPU 63. On the other hand, the type of signals input to the first through fourteenth buffers 122a through 122n was not determined during the design stage of the management IC 66, and the types of these signals are identified by the management CPU 112 upon receiving instructions from the main CPU 63. The management CPU 112 identifies the types of these signals when a type identification command is sent from the main CPU 63 to the management CPU 112 when control is initiated in the main CPU 63 and management CPU 112 following the start of supply of operating power to the MPU 62, as will be described in detail below. In this case, the information on the types of signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of signals while operating power is being supplied, it references the information stored in the correspondence memory 116.

Figure 20 is an explanatory diagram illustrating the configuration of the correspondence memory 116. The correspondence memory 116 has first to fourteenth correspondence areas 123a to 123n that correspond one-to-one to the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I/F 111.

The first correspondence area 123a stores information indicating that the signal input to the first buffer 122a is a general winning opening 31, which is used by the management CPU 112 to identify the type of signal input to the first buffer 122a. The first correspondence area 123a also stores information indicating that the signal input to the first buffer 122a is a general winning opening 31, along with information indicating the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The second correspondence area 123b stores information indicating that the signal input to the second buffer 122b is a general winning opening 31, which is used by the management CPU 112 to identify the type of signal input to the second buffer 122b. The second correspondence area 123b also stores information indicating that the signal input to the second buffer 122b is a general winning opening 31, along with information indicating the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The third correspondence area 123c stores information indicating that the signal input to the third buffer 122c is from the general winning opening 31, which is used by the management CPU 112 to identify the type of signal input to the third buffer 122c. In addition to the information indicating that the signal is from the general winning opening 31, the third correspondence area 123c also stores information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31.

The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is a special electric winning device 32, which is used by the management CPU 112 to identify the type of signal. The fourth correspondence area 123d also stores information indicating that the signal is a special electric winning device 32, as well as information on the number of game balls (15) that will be paid out when one game ball enters the special electric winning device 32. The fifth correspondence area 123e stores information indicating that the signal is a first actuation port 33, which is used by the management CPU 112 to identify the type of signal input to the fifth buffer 122e. The fifth correspondence area 123e also stores information indicating that the signal is a first actuation port 33, as well as information on the number of game balls (1) that will be paid out when one game ball enters the first actuation port 33. The sixth correspondence area 123f stores information indicating that the signal input to the sixth buffer 122f is from the second actuation port 34, which is information used by the management CPU 112 to identify the type of signal. The sixth correspondence area 123f also stores information indicating that the signal is from the second actuation port 34, as well as information on the number of game balls (1) that will be paid out when one game ball enters the second actuation port 34. The seventh correspondence area 123g stores information indicating that the signal is from the outlet 24a, which is information used by the management CPU 112 to identify the type of signal input to the seventh buffer 122g.

The eighth correspondence area 123h stores information indicating the open/close execution mode, which is used by the management CPU 112 to identify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating the high frequency support mode, which is used by the management CPU 112 to identify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating the front door frame 14, which is used by the management CPU 112 to identify the type of signal input to the tenth buffer 122j. The eleventh correspondence area 123k stores information indicating the start of a game round, which is used by the management CPU 112 to identify the type of signal input to the eleventh buffer 122k.

The twelfth correspondence area 123l stores information indicating that it is blank and does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the twelfth buffer 122l. The thirteenth correspondence area 123m stores information indicating that it is blank and does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the thirteenth buffer 122m. The fourteenth correspondence area 123n stores information indicating that it is blank and does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the fourteenth buffer 122n.

As described above, the type of signal to be input to the first through fourteenth buffers 122a through 122n is determined by the management CPU 112 upon receiving instructions from the main CPU 63. This allows the management IC 66 to be used in models other than this pachinko machine 10. This increases the versatility of the management IC 66.

Furthermore, rather than outputting information for recognizing the type of signal each time a signal corresponding to the storage of history information is output to the first through fourteenth buffers 122a through 122n, information for recognizing the type of signal is output in advance, and information for identifying the type of signal to be input to the first through fourteenth buffers 122a through 122n based on the output information is stored in the correspondence memory 116. This makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration in which information for recognizing the type of signal is output each time a signal corresponding to the storage of history information is output to the first through fourteenth buffers 122a through 122n.

In addition, information used by the management CPU 112 to identify the types of signals input to the first through fourteenth buffers 122a through 122n is output when the supply of operating power begins. This allows the management CPU 112 to identify the types of signals input to the first through fourteenth buffers 122a through 122n when play begins on this pachinko machine 10.

In addition, the information that a setting value update signal is input to the 15th buffer 122o and the information that an output instruction signal is input to the 16th buffer 122p are set during the design stage of the management IC 66. This makes it possible to omit processing to identify the type of signal input to the 15th buffer 122o and the 16th buffer 122p for setting value update signals and output instruction signals that are reliably used not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load of processing to identify the type of such signals.

Next, we will explain the history memory 117 of the management IC 66. Figure 21 is an explanatory diagram illustrating the configuration of the history memory 117.

The history memory 117 has a history area 124 for sequentially storing history information. The history area 124 contains multiple pointer information items, each numbered consecutively. A history information storage area 125 is also provided in a one-to-one correspondence with each pointer information item. The history information storage area 125 can store combinations of RTC information and correspondence information. Each history information storage area 125 has a data capacity of 2 bytes, with 1 byte allocated as an area for storing RTC information and 1 byte allocated as an area for storing correspondence information. When correspondence information needs to be stored based on signals input to the first through fourteenth buffers 122a through 122n (actually the first through eleventh buffers 122a through 122k in the case of this pachinko machine 10), the date and time information currently measured by the RTC 115 is first stored in the area for storing RTC information in the history information storage area 125 corresponding to the pointer information currently being written. The correspondence information corresponding to the buffers 122a-122n that triggered the current information storage is then read from the correspondence areas 123a-123n in the correspondence memory 116 that correspond to those buffers 122a-122n, and the read correspondence information is stored in an area in the history information storage area 125 that stores correspondence information corresponding to the pointer information currently being written.

Specifically, with regard to the correspondence information stored in the history information storage area 125, as already explained, the first through seventh buffers 122a through 122g receive signals corresponding to the detection results of the ball entry detection sensors 42a through 48a, and therefore the first through seventh correspondence areas 123a through 123g in the correspondence memory 116 store information corresponding to the type of ball entry sensor 42a through 48a. More specifically, information corresponding to the type of ball entry section corresponding to each of the ball entry detection sensors 42a through 48a is stored in the first through seventh correspondence areas 123a through 123g. As already explained, in this pachinko machine 10, the first through third prize entry detection sensors 42a through 44a all detect game balls that have entered the general prize entry port 31, and therefore the first through third correspondence areas 123a through 123c corresponding to these first through third prize entry detection sensors 42a through 44a all store information indicating that the general prize entry port 31 is present. Additionally, the fourth correspondence area 123d stores information indicating that it is the special electric winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the outlet 24a. If the buffer 122a-122n that triggered the current information storage is one of the first through seventh buffers 122a-122g, information on the type of ball entry point corresponding to that buffer 122a-122g is read from one of the first through seventh correspondence areas 123a-123g, and the read information on the type of ball entry point is stored directly in the area for storing correspondence information in the history information storage area 125.

Meanwhile, the eighth buffer 122h receives a signal indicating whether the opening/closing execution mode is in progress, the ninth buffer 122i receives a signal indicating whether the high-frequency support mode is in progress, the tenth buffer 122j receives a signal indicating whether the front door frame 14 is open, and the eleventh buffer 122k receives a signal indicating whether a game has started. Therefore, the eighth correspondence area 123h stores information indicating the opening/closing execution mode, the ninth correspondence area 123i stores information indicating the high-frequency support mode, the tenth correspondence area 123j stores information indicating the front door frame 14, and the eleventh correspondence area 123k stores information indicating a game has started.

As explained above, the main CPU 63 continuously outputs a LOW-level 8 signal when the open/close execution mode is not active and a HIGH-level 8 signal when the open/close execution mode is active. Therefore, the management CPU 112 determines that the open/close execution mode has started when the 8th signal changes from LOW to HIGH, and determines that the open/close execution mode has ended when the 8th signal changes from HIGH to LOW. Furthermore, when the 8th signal changes from LOW to HIGH, or from HIGH to LOW, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the 8th signal changes from LOW to HIGH, not only the information indicating the open/close execution mode read from the 8th correspondence area 123h but also the start information are stored in the area for storing correspondence information in the history information storage area 125. Furthermore, when the eighth signal changes from HI to LOW, not only the information indicating the opening/closing execution mode read from the eighth correspondence area 123h but also the end information are stored in the area for storing correspondence information in the history information storage area 125.

As explained above, the main CPU 63 continuously outputs a LOW-level ninth signal when not in high-frequency support mode and a HIGH-level ninth signal when in high-frequency support mode. Therefore, the management CPU 112 can determine that high-frequency support mode has begun when the ninth signal changes from LOW to HIGH, and that high-frequency support mode has ended when the ninth signal changes from HIGH to LOW. Furthermore, when the ninth signal changes from LOW to HIGH, or from HIGH to LOW, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from LOW to HIGH, not only the information indicating high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing correspondence information in the history information storage area 125. Furthermore, when the ninth signal changes from HI to LOW, not only the information indicating the high frequency support mode read from the ninth correspondence area 123i but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

As already explained, the main CPU 63 continuously outputs a LOW level 10th signal when the front door frame 14 is closed, and continuously outputs a HIGH level 10th signal when the front door frame 14 is open. This allows the management CPU 112 to determine that the front door frame 14 is open when the 10th signal changes from LOW to HIGH, and to determine that the front door frame 14 is closed when the 10th signal changes from HI to LOW. Furthermore, when the 10th signal changes from LOW to HI, or from HI to LOW, the management CPU 112 determines that an opportunity has occurred to store correspondence information in the history information storage area 125. In other words, when the 10th signal changes from a LOW level to a HIGH level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening start information are stored in the area for storing correspondence information in the history information storage area 125. Also, when the 10th signal changes from a HIGH level to a LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening end information are stored in the area for storing correspondence information in the history information storage area 125.

As already explained, the main CPU 63 continues to output a LOW level 11th signal until the start of a game round, and when the start of a game round arrives, it outputs a HIGH level 11th signal for a specific period of time. Therefore, the management CPU 112 determines that a game round has started when the 11th signal changes from a LOW level to a HIGH level. In other words, when the 11th signal changes from a LOW level to a HIGH level, the information indicating that this is a game round read from the 11th correspondence area 123k is stored in the area for storing correspondence information in the history information storage area 125.

The history information storage area 125 is provided for a sufficient number of times to store all history information generated during a 10-day consecutive business day, during which game balls are continuously fired from opening to closing. For example, if history information is generated 60,000 times per day, more than 600,000 history information storage areas 125 are provided. This makes it possible to store and retain all history information in the history memory 117 for at least 10 days.

The history memory 117 is provided with a pointer area 126 separate from the history area 124. The pointer area 126 stores information that allows the management CPU 112 to identify the pointer information currently being written to in the history memory 117. Specifically, when the pachinko machine 10 is shipped, the pointer area 126 is set with information specifying pointer information of "0" as the write target. Each time a new piece of history information is stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information in the order is to be written and history information is stored in the history information storage area 125 corresponding to that last pointer information, the information in the pointer area 126 is updated so that pointer information of "0" is the write target. As a result, if a trigger occurs to store history information that exceeds the number of pieces of history information that can be stored, the oldest history information will be overwritten with the newest history information, starting with the oldest history information stored in the history information storage area 125.

In addition, when an external device attempts to read history information from history memory 117, the history information storage area 125 is cleared to all "0"s, and the information in pointer area 126 is updated so that pointer information of "0" becomes the write target. This makes it possible to prevent history information that has already been read from becoming the target for reading again.

Next, we will explain the specific processing configuration for managing game history using the management IC 66. First, we will explain the processing configuration for storing information on the correspondence between the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I/F 111 and the signal type in the correspondence memory 116. Figure 22 is a flowchart showing the recognition processing executed by the main side CPU 63. Note that the recognition processing is executed in step S111 in the main processing (Figure 9).

First, the recognition output counter provided in the main RAM 65 is set to "14" (step S801). The recognition output counter is a counter used by the main CPU 63 to determine the remaining number of times information must be output in order to have the management CPU 112 recognize which type of signal the first to fourteenth buffers 122a to 122n of the input port 121 in the management I/F 111 correspond to. As already explained, the first to fourteenth buffers 122a to 122n are the 14 buffers that are the targets for signal type recognition, so the recognition output counter is set to "14".

Then, the primary CPU 63 executes the output process of an identification start command (step S802). The primary CPU 63 outputs various commands to the management CPU 112 to have the management CPU 112 recognize which types of signals the first through fourteenth buffers 122a through 122n correspond to. The first through eighth signals input to the first through eighth buffers 122a through 122h are used to output these commands. In other words, the first through eighth signals (i.e., the first through eighth signal paths 118a through 118h) used to instruct the management CPU 112 to store history information are used to output commands to have the management CPU 112 recognize which types of signals the first through fourteenth buffers 122a through 122n correspond to. This allows for a reduction in the number of signal paths and simplifies the configuration compared to a configuration in which the signal paths for outputting the commands are provided separately from the signal paths 118a through 118p for outputting signals to the first through sixteenth buffers 122a through 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first through eighth buffers 122a through 122h as the first through eighth signals, respectively. Furthermore, in the process of outputting the identification start command, the output state of the ninth signal is switched to HIGH level at the timing when the output of the identification start command begins, so that the management CPU 112 recognizes that a new command has been sent. Furthermore, the output period of the identification start command and the period during which the output state of the ninth signal is maintained at HIGH level are set long enough for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the first through fourteenth buffers 122a through 122n and signal types in the correspondence memory 116.

Then, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and then the n+1th buffer is set as the signal type, and so on. Signal type recognition settings are performed for the first through fourteenth buffers 122a through 122n. Therefore, if the recognition output counter is "14" through "12," a type identification command indicating the general winning slot 31 and the number of prize balls is read; if the recognition output counter is "11," a type identification command indicating the special winning slot 32 and the number of prize balls is read; if the recognition output counter is "10," a type identification command indicating the first operating slot 33 and the number of prize balls is read; if the recognition output counter is "9," a type identification command indicating the second operating slot 34 and the number of prize balls is read; if the recognition output counter is "8," a type identification command indicating the outlet 31 is read; If the recognition output counter is "7", it reads a type identification command indicating that it is in open/close execution mode; if the recognition output counter is "6", it reads a type identification command indicating that it is in high frequency support mode; if the recognition output counter is "5", it reads a type identification command indicating that it is the front door frame 14; if the recognition output counter is "4", it reads a type identification command indicating that it is a play count; if the recognition output counter is "3" to "1", it reads a type identification command indicating that it is blank.

Then, the CPU 112 executes output processing for the read type identification command (step S804). Like the identification start command, the type identification command has an 8-bit data capacity, and each bit of data is input to the first through eighth buffers 122a through 122h as signals 1 through 8, respectively. During output processing for the identification type command, the output state of signal 9 is switched to HIGH level when output of the identification type command begins, allowing the management CPU 112 to recognize that a new command has been sent. The output period for the identification type command and the period for which the output state of signal 9 is maintained at HIGH are set long enough for the management CPU 112 to recognize the output states of the identification type command and signal 9. Upon receiving the identification type command, the management CPU 112 stores information corresponding to the identification type command in the correspondence area 123a through 123n corresponding to the buffer currently being set among the first through fourteenth buffers 122a through 122n.

Then, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after decrement is "0" (step S806). If the value of the recognition output counter is 1 or greater (step S806: NO), processing is executed to output a type identification command corresponding to the value of the recognition output counter after decrement (steps S803 and S804).

On the other hand, if the value of the recognition output counter is "0" (step S806: YES), the system executes the output process of the recognition end command (step S807). The recognition end command has a data capacity of 8 bits, and each bit of data is input to the first through eighth buffers 122a through 122h as the first through eighth signals, respectively. Furthermore, in the recognition end command output process, the output state of the ninth signal is switched to HIGH level when the recognition end command output begins, so that the management CPU 112 recognizes that a new command has been sent. Furthermore, the output period of the recognition end command and the period during which the output state of the ninth signal is maintained at HIGH are set long enough for the management CPU 112 to recognize the recognition of the recognition end command and the output state of the ninth signal. By receiving the recognition end command, the management CPU 112 determines that the process of storing the information on the correspondence between the first through fourteenth buffers 122a through 122n and signal types in the correspondence memory 116 has been completed.

Next, the management processing executed by the management CPU 112 will be described with reference to the flowchart in Figure 23. The management processing is initiated when the supply of operating power to the management CPU 112 is initiated. The processing speed of the management CPU 112 is configured to be faster than the processing speed of the main CPU 63, and the combination of processing from step S908 onwards in the management processing is executed 16 or more times between the start of one timer interrupt processing (Figure 11) in the main CPU 63 and the start of the next timer interrupt processing (Figure 11).

First, it is determined whether an identification start command has been received from the main CPU 63 (step S901). If an identification start command has not been received (step S901: NO), the process executes a setting update recognition process (step S902) and then returns to step S901. In the setting update recognition process, details of which will be described later, if the main CPU 63 performs a new setting on the setting status of the pachinko machine 10, the process corresponding to that setting is executed.

When an identification start command is received from the main CPU 63 (step S901: YES), the value of the setting target counter provided in the management RAM 114 is cleared to "0" (step S903). The setting target counter is a counter used by the management CPU 112 to identify the type of buffer 122a to 122n for which the signal type is to be set. The first buffer 122a is the first to be set as the signal type, followed by the nth buffer and then the (n+1)th buffer.

After that, on the condition that a type identification command has been received from the main CPU 63 (step S904: YES), a correspondence setting process is executed (step S905). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter in the management RAM 114, among the first to fourteenth correspondence areas 123a to 123n of the correspondence memory 116. Then, the value of the setting target counter in the management RAM 114 is incremented by 1 (step S906).

If a negative judgment is made in step S904, or if the processing of step S906 is executed, it is determined whether an identification end command has been received from the main CPU 63 (step S907). If an identification end command has not been received (step S907: NO), the processing returns to step S904, and the processing of steps S905 and S906 is executed again, provided that a new type identification command has been received from the main CPU 63 (step S904: YES).

If an identification end command has been received from the main CPU 63 (step S907: YES), steps S908 to S910 are repeatedly executed. In step S908, a history setting process is executed to store history information corresponding to the type of signal received from the main CPU 63 in the history memory 117, as will be described in detail later. In step S909, a display output process is executed to calculate various parameters using the history information stored in the history memory 117 and to notify the first to third notification display devices 69a to 69c of the calculation results, as will be described in detail later. In step S910, an external output process is executed to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d, as will be described in detail later.

Figure 24 is a time chart showing how information on the correspondence between the first through fourteenth buffers 122a through 122n and the types of signals input to these buffers 122a through 122n is stored in the correspondence memory 116. Figure 24(a) shows the period during which commands are output from the main CPU 63 to the management CPU 112 using the first through eighth signals (i.e., the first through eighth signal paths 118a through 118h), Figure 24(b) shows the period during which the output state of the ninth signal is at HI level, Figure 24(c) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first through fourteenth buffers 122a through 122n and the types of signals input to these buffers 122a through 122n, and Figure 24(d) shows the timing when the correspondence setting process (step S905) is executed by the management CPU 112.

When the supply of operating power to the main CPU 63 and the management CPU 112 begins, output of the identification start command using signals 1 through 8 begins at time t1, as shown in Figure 24(a). Also at time t1, the output state of signal 9 changes from LOW to HIGH, as shown in Figure 24(b). Then, at time t2, while the output of the identification start command continues, the output state of signal 9 changes from HI to LOW, as shown in Figure 24(b). The management CPU 112 determines that a command has been sent from the main CPU 63 by confirming that the output state of signal 9 has changed from HI to LOW, and then determines the content of the command received from the main CPU 63 by checking the information in buffers 122a through 122h. In this case, because the identification start command has been received, the management CPU 112 enters the identification state by making a positive determination in step S901 of the management process (Figure 23). After that, at timing t3, output of the identification start command is stopped, as shown in Figure 24(a).

Then, at timing t4, output of the first type identification command using signals 1 through 8 begins, as shown in Figure 24(a). Also at timing t4, the output state of signal 9 changes from LOW to HIGH, as shown in Figure 24(b). Then, at timing t5, while the type identification command continues to be output, the output state of signal 9 changes from HI to LOW, as shown in Figure 24(b). The control CPU 112 determines that a command has been sent from the primary CPU 63 by confirming that the output state of signal 9 has changed from HI to LOW, and determines the content of the command received from the primary CPU 63 by checking the information in buffers 122a through 122h. In this case, since the first type identification command has been received, the control CPU 112 executes the correspondence setting process at timing t5, as shown in Figure 24(d). In this correspondence setting process, information indicating that the general winning slot 31 is selected and information on the number of winning balls is stored in the first correspondence area 123a of the correspondence memory 116. After that, at timing t6, the output of the type identification command is stopped as shown in Figure 24(a).

After that, from t7 to t9, from t10 to t12, from t13 to t15, and from t16 to t18, the management CPU 112 executes the correspondence setting process corresponding to the type identification command output from the main CPU 63, just as it did from t4 to t6. In this case, the correspondence setting process corresponding to the 14th type identification command is completed from t16 to t18.

Then, at timing t19, output of the identification end command using signals 1 to 8 begins, as shown in Figure 24(a). Also at timing t19, the output state of signal 9 changes from LOW to HIGH, as shown in Figure 24(b). Then, at timing t20, while the output of the identification end command is continuing, the output state of signal 9 changes from HI to LOW, as shown in Figure 24(b). The control CPU 112 determines that a command has been sent from the primary CPU 63 by confirming that the output state of signal 9 has changed from HI to LOW, and determines the content of the command received from the primary CPU 63 by checking the information in buffers 122a to 122h. In this case, because the identification end command has been received, the control CPU 112 ends its identification state at timing t20, as shown in Figure 24(c). Then, at timing t21, output of the identification end command is stopped, as shown in Figure 24(a).

As described above, by configuring the management CPU 112 to recognize whether a command is being output using the 9th signal, it is possible to have the management CPU 112 clearly recognize that a command is being output, even in a configuration in which commands are output using the 1st to 8th signals (i.e., the 1st to 8th signal paths) that are used to instruct the management CPU 112 when to store history information.

Next, we will explain the processing configuration for storing history information in the history memory 117. Figure 25 is a flowchart showing the management output processing executed by the main CPU 63. Note that the management output processing is executed in step S319 of the timer interrupt processing (Figure 11).

First, the managed object counter stored in the main RAM 65 is set to "11" (step S1001). The managed object counter is a counter that allows the main CPU 63 to determine whether there are any managed objects that have not yet been identified as whether the signal output status to the management CPU 112 should be changed in this management output process, and to identify which managed objects the signal output status to the management CPU 112 should be changed for. In one management output process, the main CPU 63 identifies 11 managed objects as whether the signal output status to the management CPU 112 should be changed: the seven ball entry detection sensors 42a-48a, whether the open/close execution mode is active, whether the high-frequency support mode is active, whether the front door frame 14 is open/closed, and whether a game round has started. Therefore, the managed object counter is initially set to "11".

Then, it is determined whether the signal output state to the management CPU 112 for the managed object corresponding to the current value of the managed object counter is at HI level (step S1002). If it is not at HI level (step S1002: NO), it is determined whether the value of the managed object counter is 5 or greater, thereby identifying which of the seven ball entry detection sensors 42a to 48a is the managed object corresponding to the value of the managed object counter (step S1003).

If a positive judgment is made in step S1003, it is determined whether the output flag in the main RAM 65 corresponding to the value of the managed counter is set to "1" (step S1004). Specifically, if the value of the managed counter is "11" and corresponds to the first winning slot detection sensor 42a, it is determined whether the first output flag is set to "1". If the value of the managed counter is "10" and corresponds to the second winning slot detection sensor 43a, it is determined whether the second output flag is set to "1". If the value of the managed counter is "9" and corresponds to the third winning slot detection sensor 44a, it is determined whether the third output flag is set to "1". If the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1". If the value of the managed counter is "7" and corresponds to first actuation port detection sensor 46a, it determines whether the fourth output flag is set to "1." If the value of the managed counter is "6" and corresponds to second actuation port detection sensor 47a, it determines whether the sixth output flag is set to "1." If the value of the managed counter is "5" and corresponds to outlet 24a, it determines whether the seventh output flag is set to "1." As already explained, these first through seventh output flags are set to "1" during the ball entry detection process (Figure 15).

If the output flag corresponding to the value of the managed counter is set to "1" (step S1004: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HIGH (step S1005). Then, the output flag corresponding to the value of the managed counter is cleared to "0" (step S1006).

If a negative determination is made in step S1003, a determination is made as to whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed counter to a high level (step S1007). Specifically, if the value of the managed counter is "4," a determination is made as to whether a transition to the open/close execution mode has occurred; if the value of the managed counter is "3," a determination is made as to whether a transition to the high-frequency support mode has occurred; if the value of the managed counter is "2," a determination is made as to whether the front door frame 14 has entered an open state; and if the value of the managed counter is "1," a determination is made as to whether a game turn has started by determining whether the 11th output flag is set to "1." If a positive determination is made in step S1007, the output state of the signal corresponding to the value of the managed counter is set to a high level (step S1008). Note that if the processing of step S1008 is executed when the value of the managed counter is "1," the 11th output flag is cleared to "0."

If a positive judgment is made in step S1002, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed counter to a LOW level (step S1009). Specifically, if the value of the managed counter is 5 or greater or "1" and the current managed object is one of the ball entry detection sensors 42a-48a or the start of a game, it is determined whether a HI output duration (specifically, 10 milliseconds) has elapsed since the output state of the signal corresponding to the value of the managed counter, among signals 1 through 7 and signal 11, was switched from a LOW level to a HI level. This HI output duration is set by the management CPU 112 to a period longer than the longest processing interval of the history setting process (step S908) of the management process (Figure 23), and is a period that allows the management CPU 112 to reliably identify the output state of the signal that switched from a LOW level to a HI level. Furthermore, if the value of the management target counter is "4" and the current management target is in open/close execution mode, it determines whether the open/close execution mode has ended; if the value of the management target counter is "3" and the current management target is in high-frequency support mode, it determines whether the high-frequency support mode has ended; and if the value of the management target counter is "2" and the current management target is the front door frame 14, it determines whether the front door frame 14 is in a closed state. If an opportunity has arisen to switch the output state of the signal corresponding to the value of the management target counter to a LOW level (step S1009: YES), the output state of the signal corresponding to the value of the management target counter is set to a LOW level (step S1010).

If a negative judgment is made in step S1004, if the processing of step S1006 is executed, if a negative judgment is made in step S1007, if the processing of step S1008 is executed, if a negative judgment is made in step S1009, or if the processing of step S1010 is executed, the value of the managed object counter in the main RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the managed object counter after the decrement is "0" (step S1012). If the value of the managed object counter is 1 or greater (step S1012: NO), the processing from step S1002 onwards is executed for the managed object corresponding to the new managed object counter value.

Next, the history setting process executed by the management CPU 112 will be described with reference to the flowchart in Figure 26. The history setting process is executed in step S908 of the management process (Figure 23).

First, the number of buffers to be checked by the management CPU 112, out of the first through fourteenth buffers 122a through 122n, is set in a confirmation target counter provided in the management RAM 114 (step S1101). Specifically, the number of correspondence areas in the correspondence memory 116, out of the first through fourteenth correspondence areas 123a through 123n, that store information other than information indicating that they are blank is identified, and the information for this identified number is set in the confirmation target counter. As already explained, in this pachinko machine 10, information other than information indicating that they are blank is stored in the first through eleventh correspondence areas 123a through 123k, and therefore the confirmation target counter is set to "11" in step S1101.

Then, by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked, among the first through fourteenth buffers 122a through 122n, has changed from "0" to "1," it is determined whether the output state of the input signal from the main CPU 63 to that buffer has switched from LOW to HIGH (step S1102). Note that if the value of the counter to be checked is "n," the nth buffers 122a through 122n are the target for checking the numerical information. For example, if the value of the counter to be checked is "11," the eleventh buffer 122k is the target for checking the numerical information, and if the value of the counter to be checked is "5," the fifth buffer 122e is the target for checking the numerical information.

If a positive judgment is made in step S1102, RTC information, which is date and time information, is read from the RTC 115 (step S1103). Then, a write process to the history memory 117 is executed (step S1104). In this write process, the pointer information in the history area 124 that is the current write target is identified by referencing the pointer area 126 of the history memory 117, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is the write target. In addition, correspondence information is read from the correspondence area 123a to 123n that corresponds to the current value of the counter to be confirmed, and the correspondence information is written to the history information storage area 125 that corresponds to the pointer information that is the write target. Furthermore, if the correspondence information is any of information indicating the opening/closing execution mode, information indicating the high-frequency support mode, and information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information being written. Note that if the value of the counter to be checked is "n", the nth correspondence area 123a-123n is the target for reading the correspondence information. For example, if the value of the counter to be checked is "11", the eleventh correspondence area 123k is the target for reading the correspondence information, and if the value of the counter to be checked is "5", the fifth correspondence area 123e is the target for reading the correspondence information.

By executing the write process as described above, if the value of the counter to be checked is either the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, second operating opening 34, or number of plays, the history information storage area 125 corresponding to the pointer information being written stores a combination of RTC information and correspondence information indicating either the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, second operating opening 34, or number of plays as history information. Also, if the value of the counter to be checked is either the open/close execution mode, high-frequency support mode, or front door frame 14, the history information storage area 125 corresponding to the pointer information being written stores a combination of RTC information, correspondence information indicating either the open/close execution mode, high-frequency support mode, or front door frame 14, and start information as history information.

Then, the target pointer is updated (step S1105). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. A determination is made as to whether the pointer information after incrementing by one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

If a negative judgment is made in step S1102, or if the processing of step S1105 is executed, it is determined whether the correspondence information for which it is to be confirmed whether the signal output has been switched to a LOW level is stored in the correspondence area 123a-123n corresponding to the current value of the counter to be confirmed (step S1106). Specifically, if the current value of the counter to be confirmed is between "8" and "10", the corresponding correspondence area 123h-123j stores any of the following information: opening/closing execution mode, high frequency support mode, or front door frame 14, and therefore a positive judgment is made in step S1106.

If a positive determination is made in step S1106, the system checks whether the numerical information stored in the buffer corresponding to the current counter value among the first through fourteenth buffers 122a through 122n has changed from "1" to "0," thereby determining whether the output state of the input signal from the master CPU 63 to that buffer has switched from HI to LOW (step S1107). If a positive determination is made in step S1107, the system reads the RTC information (step S1108), as in step S1103, and then executes a write process to the history memory 117 (step S1109). In this write process, the RTC information read in step S1108 is written to the history information storage area 125 in the history area 124 corresponding to the pointer information being written. Furthermore, the system reads the correspondence information from the correspondence area 123a through 123n corresponding to the current counter value being checked, and writes the correspondence information to the history information storage area 125 corresponding to the pointer information being written. In addition, not only the correspondence information but also the termination information is written to the history information storage area 125 corresponding to the pointer information being written. By executing the writing process in this manner, if the value of the counter being checked is either the open/close execution mode, the high frequency support mode, or the front door frame 14, a combination of RTC information, correspondence information indicating either the open/close execution mode, the high frequency support mode, or the front door frame 14, and the termination information is stored as history information in the history information storage area 125 corresponding to the pointer information being written. Thereafter, the target pointer update process is executed in the same manner as in step S1105 (step S1110).

If a negative judgment is made in step S1106, if a negative judgment is made in step S1107, or if the processing of step S1110 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the confirmation target counter after the decrement is "0" (step S1112). If the value of the confirmation target counter is 1 or greater (step S1112: NO), the processing from step S1102 onwards is executed for the confirmation target corresponding to the new value of the confirmation target counter.

Next, the manner in which history information is stored in history memory 117 will be described with reference to the timing chart in Figure 27. Figure 27(a) shows the period when a HIGH level signal is input to any of the first to seventh and eleventh buffers 122a to 122g and 122k, Figure 27(b) shows the period when a HIGH level signal is input to the eighth buffer 122h, Figure 27(c) shows the period when a HIGH level signal is input to the ninth buffer 122i, Figure 27(d) shows the period when a HIGH level signal is input to the tenth buffer 122j, and Figure 27(e) shows the timing for writing history information to history memory 117.

At time t1, as shown in Figure 27(a), the output state of the signal input to one of the first through seventh and eleventh buffers 122a through 122g, and 122k is switched from low to high. Therefore, at time t1, history information is written to history memory 117 as shown in Figure 27(e). Then, at time t2, the signal that was switched to high at time t1 as shown in Figure 27(a) is switched to low. However, since this signal is input to one of the first through seventh and eleventh buffers 122a through 122g, and the low level switch is not a target for storing history information, no history information is written at time t2 as shown in Figure 27(e).

After that, at times t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to any of the first through seventh and eleventh buffers 122a through 122g, 122k is switched from LOW to HIGH, as shown in Figure 27(a). Therefore, at each of these times, history information is written, as shown in Figure 27(e).

As shown in Figure 27(b), the output state of the signal input to the eighth buffer 122h is HIGH from time t4 to time t7. This eighth buffer 122h corresponds to whether or not the open/close execution mode is active. Therefore, as shown in Figure 27(e), history information is written at time t4, when the output state of the signal input to the eighth buffer 122h switches to HIGH, and at time t7, when the output state of that signal switches to LOW. In this case, the history information written at time t4 includes start information, and the history information written at time t7 includes end information. This makes it possible to determine the execution period of the open/close execution mode by checking the history information in the history memory 117.

In addition, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is from the opening/closing execution mode. Furthermore, because the history information includes RTC information, it is also possible to distinguish by comparing this RTC information whether history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is from the opening/closing execution mode.

As shown in Figure 27(c), the output state of the signal input to the ninth buffer 122i is HIGH from time t8 to time t11. This ninth buffer 122i corresponds to whether or not the high frequency support mode is active. Therefore, as shown in Figure 27(e), history information is written at time t8, when the output state of the signal input to the ninth buffer 122i switches to HIGH, and at time t11, when the output state of that signal switches to LOW. In this case, the history information written at time t8 includes start information, and the history information written at time t11 includes end information. This makes it possible to determine the execution period of the high frequency support mode by checking the history information in the history memory 117.

In addition, history information is written to history memory 117 in chronological order. Therefore, it is possible to distinguish whether history information indicating that a ball has entered any of outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is from high-frequency support mode. Furthermore, because the history information includes RTC information, it is also possible to distinguish by comparing this RTC information whether history information indicating that a ball has entered any of outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is from high-frequency support mode.

As shown in Figure 27(d), the output state of the signal input to the tenth buffer 122j is HIGH from time t12 to time t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in Figure 27(e), history information is written at time t12, when the output state of the signal input to the tenth buffer 122j switches to HIGH, and at time t15, when the output state of that signal switches to LOW. In this case, the history information written at time t12 contains start information, and the history information written at time t15 contains end information. This makes it possible to determine the period during which the front door frame 14 is open by checking the history information in the history memory 117.

In addition, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open. Furthermore, because the history information includes RTC information, it is also possible to distinguish by comparing this RTC information whether history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open.

Next, we will explain the setting value update signal output process that is executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Figure 28 is a flowchart showing the setting value update signal output process executed by the main CPU 63. Note that the setting value update signal output process is executed in step S119 in the main processing (Figure 9).

A value corresponding to the currently set value of the pachinko machine 10 is set in the pulse count counter provided in the main RAM 65 (step S1201). Specifically, the value of the setting value counter in the main RAM 65 is set in the pulse count counter. Then, it is determined whether the setting value update signal directed to the management CPU 112 is at a HI level (step S1202). As already explained, the setting value update signal is input to the 15th buffer 122o of the input port 121 in the management IC 66. Here, the output process of the setting value update signal is executed at a timing prior to the recognition process, which is a process for having the management CPU 112 identify the types of signals input to the 1st to 14th buffers 122a to 122n of the input port 121 during the main process (Figure 9). In contrast, the input of a setting value update signal to the 15th buffer 122o is set in the management IC 66 during the design stage of the pachinko machine 10, so even if the output process for the setting value update signal is executed before the recognition process, the management CPU 112 can identify that the signal input to the 15th buffer 122o is a setting value update signal.

If the determination in step S1202 is negative, the value of the LOW level counter provided in the main RAM 65 is decremented by 1 (step S1203), and it is determined whether the value of the LOW level counter after decrementing by 1 is "0" (step S1204). The LOW level counter is a counter used by the main CPU 63 to determine whether the set value update signal has been maintained at a LOW level for a predetermined period while multiple pulses at a HIGH level are output. If the value of the LOW level counter is "0" (step S1204: YES), this means that it is time to set the set value update signal to a HIGH level, and therefore the set value update signal is set to a HIGH level (step S1205).

Then, the HI level counter provided in the main RAM 65 is set to "20" (step S1206). The HI level counter is a counter used by the main CPU 63 to determine the period during which the set value update signal is maintained at a HI level. The value set in the HI level counter is decremented by 1 approximately every 10 microseconds, so that the set value update signal is maintained at a HI level for 200 microseconds when one pulse is output. This period during which the HI level is maintained is sufficient for the management CPU 112 to determine that the set value update signal has changed from a LOW level to a HI level.

If the set value update signal is at a high level (step S1202: YES), the value of the high level counter in the main RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the high level counter after decrementing by 1 is "0" (step S1208). If the value of the high level counter is "0" (step S1208: YES), this means that it is time to set the set value update signal to a low level, so the set value update signal is set to a low level (step S1209).

Then, the value of the pulse number counter in the main RAM 65 is decremented by 1 (step S1210), and it is determined whether the value of the pulse number counter after decrementing by 1 is "0" (step S1211). If the value of the pulse number counter is not "0" (step S1211: NO), this means that the output of pulse signals in response to the setting value update signal for the number of pulses corresponding to the currently set setting value of the pachinko machine 10 has not been completed, and the LOW level counter in the main RAM 65 is set to "20" (step S1212). The value set in the LOW level counter is decremented by 1 approximately every 10 microseconds, so it is maintained at a LOW level for 200 microseconds between multiple pulse outputs in response to the setting value update signal. This LOW level maintenance period is sufficient for the management CPU 112 to determine that the setting value update signal has changed from a HIGH level to a LOW level.

If the value of the pulse number counter is "0" (step S1211: YES), this means that the output of pulse signals due to the setting value update signal corresponding to the currently set setting value of the pachinko machine 10 has been completed, and the output process of the setting value identification end command is executed (step S1213). The setting value identification end command is a command that causes the management CPU 112 to recognize that the output of the setting value update signal that causes the management CPU 112 to recognize the currently set setting value of the pachinko machine 10 has been completed. When outputting the setting value identification end command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used, just like the identification start command, type identification command, and identification end command. However, the signal pattern of the setting value identification end command is different from that of the identification start command, type identification command, and identification end command.

As described above, the setting value update signal output process outputs to the management IC 66 a number of pulse signals from the setting value update signal corresponding to the setting value of the pachinko machine 10 that was set when the current supply of operating power began. The management CPU 112 executes the setting update recognition process to determine the number of pulse signals from the setting value update signal, and based on this, determines the setting value of the pachinko machine 10 that was set this time.

Figure 29 is a flowchart showing the setting update recognition process executed by the management CPU 112. Note that the setting update recognition process is executed in step S902 of the management process (Figure 23).

It is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from a LOW level to a HIGH level (step S1301). If a positive determination is made in step S1301, the value of the setting value grasp counter provided in the management RAM 114 is set to "1" (step S1302). The setting value grasp counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10; for example, a setting value grasp counter value of "1" indicates "setting 1," and a setting value grasp counter value of "6" indicates "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S1303). If a positive determination is made in step S1303, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S1304). As a result, the setting value of the pachinko machine 10 identified by the management CPU 112 is increased by one level.

If a negative determination is made in step S1303, or if the processing of step S1304 is executed, it is determined whether a set value identification end command has been received from the main CPU 63 based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, processing returns to step S1303.

If a positive determination is made in step S1305, RTC information, which is date and time information, is read from the RTC 115 (step S1306). Then, a write process to the history memory 117 is executed (step S1307). In this write process, the pointer information in the history area 124 that is currently being written to is identified by referencing the pointer area 126 of the history memory 117, and the RTC information read in step S1306 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is being written to. In addition, both information identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 that corresponds to the pointer information that is being written to. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

Then, the target pointer is updated (step S1308). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. A determination is made as to whether the pointer information after incrementing by one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

When the setting update recognition process is executed as described above, when the setting status of the pachinko machine 10 is newly set, the fact that the setting was made, the date and time the setting was made, and the combination of setting values when the setting was made are stored as history information in the history area 124. As a result, by reading and analyzing the information stored in the history memory 117 using an external device connected to the reading terminal 68d, it is possible to determine the date and time the setting status of the pachinko machine 10 was newly set and the contents of the setting values when the setting was made.

Here, even if the setting state of the pachinko machine 10 is newly set, the information stored in the history memory 117 remains unchanged. This prevents the history information in the history memory 117 from being erased even when the setting state of the pachinko machine 10 is newly set, and the various parameters described below are calculated using history information that exists both before and after the timing of the change in the setting state of the pachinko machine 10. In this case, since the date and time when the setting state of the pachinko machine 10 was newly set as described above is stored in the history memory 117, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate the various parameters for the period after the setting state of the pachinko machine 10 was newly set and while that setting state was maintained.

Next, the display output process executed by the management CPU 112 will be described with reference to the flowchart in Figure 30. Note that the display output process is executed in step S909 of the management process (Figure 23).

First, it is determined whether it is time for calculation (step S1401). If 51 seconds have passed since the supply of operating power to the management CPU 112 began, or if 51 seconds have passed since the previous affirmative determination in step S1401, a positive determination is made in step S1401. If a positive determination is made in step S1401, the number of balls that enter during normal times is calculated (step S1402). Specifically, the number of balls that enter the outlet 24a is calculated by first counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the ball is the outlet 24a. In addition, the number of balls that enter the general winning slot 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the ball is the general winning slot 31. In addition, the number of balls that have entered the special power winning device 32 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the device is the special power winning device 32. In addition, the number of balls that have entered the first operating port 33 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the device is the first operating port 33. In addition, the number of balls that have entered the second operating port 34 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the device is the second operating port 34.

Then, by referencing the history information storage areas 125 in the history area 124 of the history memory 117 that exist in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating that it is the front door frame 14 and the history information storage area 125 storing the correspondence relationship information and end information indicating that it is the front door frame 14, the number of balls that entered each of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 while the front door frame 14 was in the open state is calculated (step S1403). The period between the history information storage area 125 in the history area 124 of the history memory 117 storing the correspondence relationship information and start information indicating that it is the front door frame 14 and the history information storage area 125 storing the correspondence relationship information and end information indicating that it is the front door frame 14 is calculated from the RTC information stored in these history information storage areas 125. In addition, if there are multiple sections within the entire consecutive pointer information that have a history information storage area 125 storing correspondence information and start information indicating the front door frame 14 and a history information storage area 125 storing correspondence information and end information indicating the front door frame 14, the total number of balls scored for each section is calculated. In addition, if there is a history information storage area 125 storing correspondence information and start information indicating the front door frame 14, but the history information storage area 125 storing RTC information corresponding to a time later than the history information storage area 125 storing correspondence information and start information indicating the front door frame 14 does not store correspondence information and end information indicating the front door frame 14, all history information in the history information storage area 125 storing RTC information corresponding to a time later than the history information storage area 125 storing correspondence information and start information indicating the front door frame 14 is treated as if the front door frame 14 is in an open state.

Thereafter, various parameters are calculated using the calculation results of steps S1402 and S1403 (step S1404). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1403, is subtracted from the number of balls that entered the outlet 24a calculated in step S1402. Then, the following first to eighth parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1402 and the number of balls that entered the outlet 24a calculated in step S1403 is set as the number of balls that entered the outlet 24a, the difference between the number of balls that entered the general winning port 31 calculated in step S1402 and the number of balls that entered the general winning port 31 calculated in step S1403 is set as the number of balls that entered the outlet 24a, and the difference between the number of balls that entered the general winning port 31 calculated in step S1402 and the number of balls that entered the special winning device 32 calculated in step S1402 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1403 is designated as the number of balls that enter the device 32, the difference in the number of balls that enter the device 32 calculated in step S1403 from the number of balls that enter the device 32 calculated in step S1402 is designated as the number of balls that enter the device 32, the difference in the number of balls that enter the device 32 calculated in step S1403 from the number of balls that enter the device 32 calculated in step S1402 is designated as the number of balls that enter the device 32, and ....
First parameter: Total number of game balls paid out (K2 x "number of prize balls for winning at the general winning port 31" + K3 x "number of prize balls for winning at the special electric winning device 32" + K4 x "number of prize balls for winning at the first operating port 33" + K5 x "number of prize balls for winning at the second operating port 34") / ratio of total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D1").
Second parameter: Ratio of total number of game balls entering the general winning port 31 (K2) / total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) Third parameter: Ratio of total number of game balls entering the special winning device 32 (K3) / total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) Fourth parameter: Ratio of total number of game balls entering the first operating port 33 (K4) / total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D2")
Fifth parameter: the ratio of the total number of game balls entering the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D3")
Sixth parameter: D1 - (D2 x "number of winning balls for winning through the first actuation port 33" + D3 x "number of winning balls for winning through the second actuation port 34")
Seventh parameter: (K3 x "number of prize balls for winning the special electric winning device 32" + K5 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special electric winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") the ratio of "number of prize balls for winning at the special electric winning device 32" to "total number of game balls paid out"); eighth parameter: K3 x "number of prize balls for winning at the special electric winning device 32" / total number of game balls paid out (K2 x "number of prize balls for winning at the general winning port 31" + K3 x "number of prize balls for winning at the special electric winning device 32" + K4 x "number of prize balls for winning at the first operating port 33" + K5 x "number of prize balls for winning at the second operating port 34") In step S1404, the first to eighth parameters, which are the calculation results, are stored in a normal time memory area in the calculation result memory 131. The first to eighth parameters stored in the normal time memory area are retained until the next time step S1404 is executed. In other words, when step S1404 is executed next time and the first to eighth parameters are calculated, the newly calculated first to eighth parameters are stored in the normal time memory area, overwriting the previous calculation results of the first to eighth parameters that had been stored in the normal time memory area.

Then, by referencing the history information storage areas 125 in the history area 124 of the history memory 117 that exist in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the open/close execution mode and the history information storage area 125 storing the correspondence relationship information and end information indicating the open/close execution mode, the number of balls that entered each of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 in the open/close execution mode is calculated (step S1405). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the open/close execution mode and the history information storage area 125 storing the correspondence relationship information and end information indicating the open/close execution mode in the history area 124 of the history memory 117 is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections within the entire set of consecutive pointer information between history information storage areas 125 storing correspondence information and start information indicating the opening and closing execution mode and history information storage areas 125 storing correspondence information and end information indicating the opening and closing execution mode, the total number of balls entered for each section is calculated. Furthermore, if there is a history information storage area 125 storing correspondence information and start information indicating the opening and closing execution mode, but the history information storage area 125 storing RTC information corresponding to a time later than the history information storage area 125 storing correspondence information and start information indicating the opening and closing execution mode does not store correspondence information and end information indicating the opening and closing execution mode, all history information in the history information storage area 125 storing RTC information corresponding to a time later than the history information storage area 125 storing correspondence information and start information indicating the opening and closing execution mode is treated as being in the opening and closing execution mode.

Then, during the period of the opening/closing execution mode identified in step S1405, the number of balls that entered each of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 while the front door frame 14 was in the open state is calculated (step S1406). The method for calculating these numbers of balls is the same as in step S1403, except that it is based on the period of the opening/closing execution mode identified in step S1405.

Thereafter, various parameters are calculated using the calculation results of steps S1405 and S1406 (step S1407). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1406, is subtracted from the number of balls that entered the outlet 24a calculated in step S1405. Then, the following 11th to 18th parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1405 and the number of balls that entered the outlet 24a calculated in step S1406 is set as the number of balls that entered the outlet 24a, the difference between the number of balls that entered the general winning port 31 calculated in step S1405 and the number of balls that entered the general winning port 31 calculated in step S1406 is set as the number of balls that entered the outlet 24a, and the difference between the number of balls that entered the general winning port 31 calculated in step S1405 and the number of balls that entered the special winning device 32 calculated in step S1405 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1406 is designated as the number of balls that enter K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1405 from the number of balls that enter the first operating port 33 calculated in step S1406 is designated as the number of balls that enter K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1405 from the number of balls that enter the second operating port 34 calculated in step S1406 is designated as the number of balls that enter K15.
11th parameter: Total number of game balls paid out (K12 x "number of prize balls for winning at the general winning port 31" + K13 x "number of prize balls for winning at the special electric winning device 32" + K14 x "number of prize balls for winning at the first operating port 33" + K15 x "number of prize balls for winning at the second operating port 34") / ratio of total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D11")
12th parameter: Ratio of total number of game balls entering the general winning port 31 K12/total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 13th parameter: Ratio of total number of game balls entering the special winning device 32 K13/total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 14th parameter: Ratio of total number of game balls entering the first operating port 33 K14/total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) (hereinafter, this ratio will be referred to as "D12")
・15th parameter: The ratio of the total number of game balls entering the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13")
16th parameter: D11 - (D12 x "number of winning balls for winning into the first actuation port 33" + D13 x "number of winning balls for winning into the second actuation port 34")
17th parameter: (K13 x "number of prize balls for winning the special electric winning device 32" + K15 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K12 x "number of prize balls for winning the general winning port 31" + K13 x "number of prize balls for winning the special electric winning device 32" + K14 x "number of prize balls for winning the first operating port 33" + K15 x "number of prize balls for winning the second operating port 34") 18th parameter: K13 x "number of prize balls for winning at the special electric winning device 32" / total number of game balls paid out (K12 x "number of prize balls for winning at the general winning port 31" + K13 x "number of prize balls for winning at the special electric winning device 32" + K14 x "number of prize balls for winning at the first operating port 33" + K15 x "number of prize balls for winning at the second operating port 34") ratio In step S1407, the 11th to 18th parameters, which are the calculation results, are stored in a memory area for the opening and closing execution mode in the calculation result memory 131. The 11th to 18th parameters stored in the memory area for the opening and closing execution mode are retained until the next time step S1407 is executed. In other words, when step S1407 is executed next time and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the memory area for the opening/closing execution mode, overwriting the previous calculation results of the 11th to 18th parameters that had been stored in the memory area for the opening/closing execution mode.

Then, by referencing the history information storage areas 125 in the history area 124 of the history memory 117 that exist in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high-frequency support mode and the history information storage area 125 storing the correspondence relationship information and end information indicating the high-frequency support mode, the number of balls that entered each of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 during the high-frequency support mode situation is calculated (step S1408). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high-frequency support mode and the history information storage area 125 storing the correspondence relationship information and end information indicating the high-frequency support mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections within the entire set of consecutive pointer information between history information storage areas 125 storing correspondence information and start information indicating high frequency support mode and history information storage areas 125 storing correspondence information and end information indicating high frequency support mode, the total number of balls scored for each section is calculated. Also, if there is a history information storage area 125 storing correspondence information and start information indicating high frequency support mode, but the history information storage area 125 storing RTC information corresponding to a time later than that history information storage area 125 does not store correspondence information and end information indicating high frequency support mode, any history information in history information storage areas 125 storing RTC information corresponding to a time later than that history information storage area 125 storing correspondence information and start information indicating high frequency support mode is treated as being in high frequency support mode.

Then, during the period of the high-frequency support mode identified in step S1408, the number of balls that entered each of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 while the front door frame 14 was in the open state is calculated (step S1409). The method for calculating these numbers of balls is the same as in step S1403, except that it is based on the period of the high-frequency support mode identified in step S1408.

Thereafter, various parameters are calculated using the calculation results of steps S1408 and S1409 (step S1410). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1409, is subtracted from the number of balls that entered the outlet 24a calculated in step S1408. Then, the following 21st to 26th parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1408 and the number of balls that entered the outlet 24a calculated in step S1409 is set as the number of balls that entered the outlet 24a, the difference between the number of balls that entered the general winning port 31 calculated in step S1408 and the number of balls that entered the general winning port 31 calculated in step S1409 is set as the number of balls that entered the outlet 24a, and the difference between the number of balls that entered the general winning port 31 calculated in step S1408 and the number of balls that entered the special winning device 32 calculated in step S1408 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1409 is designated as the number of balls that enter K23, the difference in the number of balls that enter the first operating port 33 calculated in step S1409 from the number of balls that enter the first operating port 33 calculated in step S1408 is designated as the number of balls that enter K24, and the difference in the number of balls that enter the second operating port 34 calculated in step S1408 from the number of balls that enter the second operating port 34 calculated in step S1409 is designated as the number of balls that enter K25.
21st parameter: Total number of game balls paid out (K22 x "number of prize balls for winning at the general winning port 31" + K23 x "number of prize balls for winning at the special winning device 32" + K24 x "number of prize balls for winning at the first operating port 33" + K25 x "number of prize balls for winning at the second operating port 34") / ratio of total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D11")
22nd parameter: Ratio of total number of game balls entering the general winning port 31 K22 / total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) 23rd parameter: Ratio of total number of game balls entering the special winning device 32 K23 / total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) 24th parameter: Ratio of total number of game balls entering the first operating port 33 K24 / total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D22")
25th parameter: The ratio of the total number of game balls entering the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D23")
26th parameter: D21 - (D22 x "number of winning balls for winning through the first actuation port 33" + D23 x "number of winning balls for winning through the second actuation port 34")
In step S1410, the 21st to 26th parameters, which are the calculation results, are stored in a high frequency support mode storage area in the calculation result memory 131. The 21st to 26th parameters stored in the high frequency support mode storage area are held until the next execution of step S1410. In other words, when the next execution of step S1410 is performed and the 21st to 26th parameters are calculated, the newly calculated 21st to 26th parameters are stored in the high frequency support mode storage area, overwriting the previous calculation results of the 21st to 26th parameters that had been stored in the high frequency support mode storage area.

Thereafter, the frequency of occurrence of the opening/closing execution mode is calculated and stored (step S1411). Specifically, the number of occurrences of the opening/closing execution mode is calculated by counting the number of history information storage areas 125 in which correspondence relationship information and start information indicating the opening/closing execution mode are stored in the history area 124 of the history memory 117. The number of occurrences of game rounds is also calculated by counting the number of history information storage areas 125 in which correspondence relationship information indicating the start of a game round is stored in the history area 124 of the history memory 117. Then, the number of occurrences of the opening/closing execution mode per unit game round is calculated. The number of occurrences of the opening/closing execution mode is referred to as the occurrence number K31, and the number of occurrences of game rounds is referred to as the occurrence number K32.
・31st parameter: K31/K32
In step S1411, the 31st parameter, which is the calculation result, is stored in the opening/closing execution mode frequency storage area in the calculation result memory 131. The 31st parameter stored in the opening/closing execution mode frequency storage area is held until the next execution of step S1411. In other words, when the next step S1411 is executed and the 31st parameter is calculated, the newly calculated 31st parameter is stored in the opening/closing execution mode frequency storage area, overwriting the previous calculation result of the 31st parameter that had been stored in the opening/closing execution mode frequency storage area.

Thereafter, the occurrence frequency of the high-frequency support mode is calculated and stored (step S1412). Specifically, the number of occurrences of the high-frequency support mode is calculated by counting the number of history information storage areas 125 in which correspondence relationship information and start information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117. The number of game occurrences is calculated by counting the number of history information storage areas 125 in which correspondence relationship information indicating the start of a game is stored in the history area 124 of the history memory 117. Then, the number of occurrences of the high-frequency support mode per unit game and the ratio of the number of occurrences of the high-frequency support mode to the number of occurrences of the open/close execution mode are calculated. The number of occurrences of the high-frequency support mode is referred to as the occurrence number K41, the number of game occurrences is referred to as the occurrence number K42, and the number of occurrences of the open/close execution mode calculated in step S1411 is referred to as the occurrence number K43.
41st parameter: K41/K42
・42nd parameter: K41/K43
In step S1412, the 41st to 42nd parameters, which are the calculation results, are stored in a high-frequency support mode frequency storage area in the calculation result memory 131. The 41st to 42nd parameters stored in the high-frequency support mode frequency storage area are held until the next execution of step S1412. In other words, when the next execution of step S1412 is performed and the 41st to 42nd parameters are calculated, the newly calculated 41st to 42nd parameters are stored in the high-frequency support mode frequency storage area, thereby overwriting the previous calculation results of the 41st to 42nd parameters that had been stored in the high-frequency support mode frequency storage area.

If a negative determination is made in step S1401, or if the processing of step S1412 is executed, display processing is executed (step S1413). Figure 31 is a flowchart showing the display processing.

First, the value of the update timing counter stored in the management RAM 114 is decremented by 1 (step S1501). The update timing counter is a counter used by the management CPU 112 to determine when it is time to update the display contents of the game history management results displayed on the first through third notification display devices 69a through 69c. The management CPU 112 controls the display of the first through third notification display devices 69a through 69c to notify the calculation results of the first through eighth parameters, the eleventh through eighteenth parameters, the twenty-first through twenty-sixth parameters, the thirty-first parameter, and the forty-first through forty-second parameters. In this case, the first notification display device 69a displays information corresponding to the type of parameter being notified. Furthermore, the second notification display device 69b displays the digit corresponding to the tens digit of the value obtained by multiplying the parameter being notified by 100, and the third notification display device 69c displays the digit corresponding to the ones digit. The first to third notification display devices 69a to 69c sequentially switch between displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters in a predetermined order, and after the calculation result of the forty-second parameter, which is the last parameter to be displayed, is displayed, the calculation result of the first parameter, which is the first parameter to be displayed, is displayed. In this case, the calculation result of one parameter is continuously displayed for two seconds.

The calculation cycle for the various parameters in the management CPU 112 is 51 seconds. There are 25 parameters, and the calculation results for one parameter are continuously displayed for 2 seconds. Therefore, each parameter calculated by the management CPU 112 is displayed at least once on the first to third notification display devices 69a to 69c.

When the processing of step S1501 is executed, it is determined whether the value of the update timing counter after decrementing by 1 is "0" by determining whether it is time to update the display content of the first to third alarm display devices 69a to 69c (step S1502). If a positive determination is made in step S1502, the value of the display target counter stored in the management RAM 114 is incremented by 1 (step S1503). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "24" (step S1504: YES), the value of the display target counter is cleared to "0" (step S1505).

The display object counter is a counter that allows the management CPU 112 to identify the type of parameter to be displayed on the first to third alarm display devices 69a to 69c. There is a one-to-one correspondence between the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters and the possible values of the display object counter, "0" to "24." For example, when the value of the display object counter is "0," the first parameter, which is the first display object, is displayed on the first to third alarm display devices 69a to 69c; and when the value of the display object counter is "24," the forty-second parameter, which is the last display object, is displayed on the first to third alarm display devices 69a to 69c.

If a negative judgment is made in step S1504, or if the processing of step S1505 is executed, the display of the first alarm display device 69a is controlled so that information corresponding to the type of parameter corresponding to the value of the counter to be displayed is displayed (step S1506). Furthermore, the parameter corresponding to the value of the counter to be displayed is read from the calculation result memory 131, and the read parameter is multiplied by 100 so that the number corresponding to the tens digit is displayed on the second alarm display device 69b and the number corresponding to the ones digit is displayed on the third alarm display device 69c (step S1507). The contents displayed on the first to third alarm display devices 69a to 69c in steps S1506 and S1507 continue until the next update timing occurs or until the supply of operating power to the management CPU 112 is stopped. Thereafter, a value corresponding to 2 seconds is set in the update timing counter in the management RAM 114 as the value corresponding to the next update timing (step S1508).

By executing the display processing as described above, when the supply of operating power to the management CPU 112 has begun, the game history management results are displayed on the first to third notification display devices 69a to 69c. The game history management results are displayed regardless of whether play is continuing or not, and regardless of whether the gaming machine main body 12 has been opened relative to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By allowing the display control of the first to third notification display devices 69a to 69c to be executed in this way regardless of the game situation or the state of the pachinko machine 10, it is possible to simplify the processing configuration for display control of the first to third notification display devices 69a to 69c.

Display of the gaming history management results on the first to third notification display devices 69a to 69c begins after the supply of operating power to the management CPU 112 has begun and after an identification end command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131, like the information stored in the history memory 117, is stored and retained even when the supply of operating power to the pachinko machine 10 is stopped. Therefore, when the supply of operating power to the management CPU 112 begins, the gaming history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

When the setting status of the pachinko machine 10 is changed after the supply of operating power to the main CPU 63 begins, information corresponding to the setting value being changed will be displayed on the third notification display device 69c. However, the display of the information corresponding to the setting value is performed before the main CPU 63 sends an identification end command, whereas the display of the game history management results on the first to third notification display devices 69a to 69c begins after the main CPU 63 sends an identification end command. This makes it possible to prevent the display periods of these displays from overlapping, even when the third notification display device 69c is configured to serve both as a display device for displaying information corresponding to the setting value and as a display device for displaying the game history management results.

Furthermore, when information corresponding to the set value is displayed, the first notification display device 69a and the second notification display device 69b are hidden. In contrast, when the gaming history management results are displayed, the first notification display device 69a and the second notification display device 69b are not hidden. This makes it possible to distinguish whether the third notification display device 69c is displaying information corresponding to the set value or the gaming history management results.

Next, we will explain the processing configuration for outputting the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to an external device electrically connected to the read terminal 68d of the MPU 62. Figure 32(a) is a flowchart showing the data output processing executed by the main CPU 63. Note that the data output processing is executed in step S112 of the main processing (Figure 9).

The data output process first determines whether a connection signal indicating that an external device is electrically connected to the read terminal 68d has been received from the read terminal 68d (step S1601). If a negative determination is made in step S1601, the data output process is terminated. In this case, the supply of operating power to the main CPU 63 must be restarted in order for the data output process to be executed. Therefore, in order to externally output history information and various parameters, the supply of operating power to the main CPU 63 must be started with the external device electrically connected to the read terminal 68d. The power switch for stopping and starting the supply of operating power to the main CPU 63 is located on the payout mechanism 73 mounted on the back of the back pack unit 15. Therefore, in order to perform these stopping and starting operations, the gaming machine main body 12 must be opened relative to the outer frame 11 to expose the back of the back pack unit 15. In these circumstances, in order to enable the external output of history information and various parameters, the configuration requires that an external device be electrically connected to the reading terminal 68d before the supply of operating power to the main CPU 63 is started, making it difficult for anyone other than the amusement hall manager to read history information and various parameters.

If a positive determination is made in step S1601, a determination is made as to whether a control information confirmation signal has been received from the read terminal 68d, thereby determining whether the current connection of the external device to the read terminal 68d corresponds to confirmation of the control information (programs and data) of the main ROM 64 (step S1602). The external device is configured to be able to both confirm control information and check history information and various parameters. If confirmation of control information is selected by manual operation of the external device, a control information confirmation signal is transmitted from the external device. If confirmation of history information and various parameters is selected by manual operation of the external device, a history confirmation signal is transmitted from the external device. Note that this is not limited to this, and the external device for control information confirmation and the external device for history confirmation may be separate. In this case, if an external device for control information confirmation is electrically connected to the read terminal 68d, a control information confirmation signal is transmitted from the external device. If an external device for history confirmation is electrically connected to the read terminal 68d, a history confirmation signal is transmitted from the external device.

If a positive determination is made in step S1602, an output process for confirming control information is executed (step S1603). In this output process, programs and data are read from the main ROM 64 as control information, and the read control information is output to the read terminal 68d. This makes it possible for an external device electrically connected to the read terminal 68d to read the control information, making it possible to confirm whether the control information is authentic and normal.

If a negative judgment is made in step S1602, an output instruction signal is sent to the management CPU 112 (step S1604). Specifically, the output state of the output instruction signal is switched from LOW level to HIGH level. This HIGH level output state continues for a specific period of time. This specific period is long enough for the management CPU 112 to determine that a HIGH level output instruction signal has been input to the 16th buffer 122p. By switching the output state of the output instruction signal to HIGH level, the management CPU 112 executes processing to output history information.

Specifically, as shown in the flowchart of FIG. 32(b), when the output state of the output instruction signal input to the 16th buffer 122p of the input port 121 switches from LOW to HIGH (step S1701: YES), the management CPU 112 reads the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131, and outputs the read history information and various parameters to the read terminal 68d (step S1702). This allows the history information and various parameters to be read by an external device electrically connected to the read terminal 68d, making it possible to analyze the information on the game history management results. Furthermore, when the management CPU 112 outputs the history information to the read terminal 68d, it clears the history memory 117 to "0" (step S1703). The history information in the history memory 117 is erased only when the history information is read by an external device.

Returning to the explanation of the data output process (Figure 32(a)), when the process of step S1603 or step S1604 is executed, it is determined whether the electrical connection of the external device to the read terminal 68d continues (step S1605). If it continues (step S1605: YES), the process waits in step S1605. This makes it possible to prevent processes set in the execution order after the data output process from being executed until the external device is disconnected from the read terminal 68d. If the external device is disconnected from the read terminal 68d (step S1605: NO), the data output process is terminated.

The present embodiment described above provides the following excellent effects:

When a gaming ball enters any of the general winning slot 31, special electric winning device 32, first operating slot 33, and second operating slot 34, the gaming ball is paid out. Therefore, players play in the hope that a gaming ball will enter one of these slots. In this configuration, when a gaming ball enters any of the outlet slot 24a, general winning slot 31, special electric winning device 32, first operating slot 33, and second operating slot 34 (hereinafter referred to as the history-targeted ball entry slots), the corresponding history information is stored in the history memory 117 of the management IC 66. This allows the pachinko machine 10 to store and retain information for managing the number and frequency of gaming balls entering each history-targeted ball entry slot. Using this managed information, it is possible to appropriately manage the status of gaming balls entering each history-targeted ball entry slot. Furthermore, since the history information is stored and retained within the pachinko machine 10 itself, unauthorized access to or alteration of the history information can be prevented.

All ball entry areas that eject game balls from the game area PA are subject to the execution of the history information storage process and are also subject to management using the history information. This makes it possible to manage the frequency of balls entering any history-target ball entry area using the history information. It also makes it possible to manage the ratio of the number of game balls that enter each history-target ball entry area to the number of game balls ejected from the game area PA using the history information.

The history information includes RTC information, which corresponds to the timing at which the game ball entered the history target ball entry area that triggered the storage of that history information. This makes it possible to use the history information to obtain a detailed understanding of the game ball entry history at the history target ball entry area.

The history memory 117 stores not only history information corresponding to game balls entering the history target ball entry section, but also history information indicating whether the opening/closing execution mode is active, history information indicating whether the high-frequency support mode is active, and history information indicating whether the front door frame 14 is open. This makes it possible to distinguish between these situations and manage the manner in which game balls enter the history target ball entry section.

The history information stored in the history memory 117 can be output to an external device external to the pachinko machine 10. This makes it possible to read the history information using the external device and use the read history information to analyze the manner in which game balls enter the history target entry area.

The MPU 62 is provided with a read terminal 68d, which allows an external device electrically connected to the read terminal 68d to read the program from the main ROM 64. This makes it possible to check whether the program is correct. In this configuration, the read terminal 68d, which is used to output the program externally, is used to output the history information stored in the history memory 117 externally. This makes it possible to output the history information externally without complicating the configuration.

It is determined whether the information to be output from the read terminal 68d is a program or history information, and the information corresponding to this determination result is output externally via the read terminal 68d. As a result, in a configuration in which the read terminal 68d used to externally output a program is used to externally output history information, the pachinko machine 10 determines whether the information to be externally output is a program or history information, and then outputs the determined information externally. Therefore, even in a configuration in which the read terminal 68d is used for both purposes, it is possible to read out only the necessary information.

Based on information received from an external device electrically connected to the read terminal 68d, it is determined whether the information to be output from the read terminal 68d is program information or history information. This makes it possible to avoid complicating the configuration for selecting the information to be output externally.

The MPU 62, which has a main ROM 64 that stores programs in advance, has a management IC 66 and a read terminal 68d. This makes it possible to consolidate the signal path to the read terminal 68d within the MPU 62. This makes it difficult to gain unauthorized access to the signal path to the read terminal 68d, while achieving the excellent effects already described.

A management CPU 112 is provided in addition to the main CPU 63, which executes processing to ensure that game balls are paid out based on their entry into either the general winning port 31, the special electric winning device 32, the first operating port 33, or the second operating port 34. The management CPU 112 executes processing to store history information in the history memory 117. This makes it possible to manage the entry patterns of game balls into each history-targeted entry port without excessively increasing the processing load on the main CPU 63.

The main CPU 63 and management CPU 112 are provided on the same chip as the MPU 62. This makes it possible to prevent unauthorized access to the communication path between the main CPU 63 and management CPU 112.

The main CPU 63 transmits information corresponding to the detection results of each ball entry detection sensor 42a-48a to each buffer 122a-122g of the input port 121 of the management IC 66 using the signal path corresponding to each ball entry detection sensor 42a-48a. This ensures that the type of information transmitted from the main CPU 63 corresponds to each buffer 122a-122g (i.e., each signal path), simplifying the configuration for distinguishing between types of information in the management CPU 112.

The main CPU 63 sends information corresponding to whether the machine is in open/close execution mode, whether the machine is in high-frequency support mode, whether the front door frame 14 is open, and whether a game has started to each buffer 122h-122k of the input port 121 of the management IC 66 using the signal paths corresponding to each of these situations. This allows the type of information corresponding to each of these situations to correspond to each buffer 122h-122k (i.e., each signal path), simplifying the configuration for distinguishing between each type of information in the management CPU 112.

The main CPU 63 transmits correspondence information to the management CPU 112, indicating which type of information each buffer 122a-122k (i.e., each signal path 118a-118k) corresponds to. This eliminates the need to store this correspondence information in advance in the management IC 66. This makes it possible to increase the versatility of the management IC 66.

When the supply of operating power to the main CPU 63 begins, the main CPU 63 transmits correspondence information to the management IC 66. This makes it possible for the management IC 66 to identify the correspondence between the information transmitted from the main CPU 63 and the history target ball entry area in situations where a game ball may enter the history target ball entry area.

The correspondence information is sent from the main CPU 63 to the management IC 66 using signal paths 118a-118g, which are used to transmit information indicating whether or not a game ball has entered the history target entry area. This simplifies the communication configuration compared to a configuration that requires a dedicated signal path for transmitting correspondence information.

The management IC 66 is provided with a correspondence memory 116, and the correspondence information sent from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. This eliminates the need to provide information that enables the management IC 66 to identify the historical target goal location corresponding to the information to be sent each time the main CPU 63 sends information on the detection results of each goal detection sensor 42a-48a. This makes it possible to reduce the amount of information on the detection results of each goal detection sensor 42a-48a sent from the main CPU 63.

When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from LOW to HIGH, information is output from the management IC 66 to the read terminal 68d. In this case, the management CPU 112 can determine that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal without receiving correspondence information from the main CPU 63. This makes it possible to prevent the configuration for transmitting correspondence information from becoming extremely complicated.

The management IC 66 is provided with buffers 122a-122p capable of receiving information from the main CPU 63, a number greater than the number of types of information that need to be sent from the main CPU 63 to the management IC 66. This makes it possible to accommodate changes in the number of types of information depending on the model of pachinko machine 10 without changing the configuration of the buffers 122a-122p. This makes it possible to increase the versatility of the management IC 66.

When history information is sent from the management IC 66 to the read terminal 68d, the history information contains correspondence information indicating the type of history target ball entry area that corresponds to that history information. This makes it possible to use the read history information to identify the manner in which the game ball entered each history target ball entry area.

By using the history information stored in the history memory 117, the management IC 66 calculates various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameters 31, and parameters 41 to 42) corresponding to the manner in which game balls enter the play area PA over a specified period of time. These calculated parameters are then displayed sequentially on the first to third notification display devices 69a to 69c. This makes it possible for the pachinko machine 10 to notify the various parameters calculated using the history information.

Various parameters are calculated with historical information corresponding to the situation when the front door frame 14 is open excluded. This makes it possible to derive various parameters for the normal situation when the front door frame 14 is closed. In addition, various parameters corresponding to the situation in the open/close execution mode and the situation in the high-frequency support mode are calculated. This allows the manager of the amusement hall to understand the ball entry patterns corresponding to each situation.

When history information in history memory 117 is output to an external device, a process to clear history memory 117 is executed, thereby initializing history memory 117. This makes it less likely that history information that exceeds the storage capacity of history memory 117 will be stored in history memory 117, resulting in the history information that should have been stored being erased by overwriting.

In a configuration in which an external output corresponding to a game ball entering the first actuation port 33 or the second actuation port 34 is sent via the external terminal board 97, history information is stored in the history memory 117. This makes it possible to easily determine the number and frequency of game balls entering the first actuation port 33 or the second actuation port 34 by using the information output via the external terminal board 97, while accurately determining the number and frequency of game balls entering the history target ball entry areas by using the history information stored in the history memory 117.

The probability of a jackpot result in low probability mode varies depending on the setting of the pachinko machine 10, from "Setting 1" to "Setting 6." This makes it possible to create situations in which the probability of a jackpot result in low probability mode is favorable or unfavorable, even with a single pachinko machine 10. This makes it possible to increase the enjoyment of the game.

While the probability of achieving a jackpot in low probability mode varies depending on the setting of the pachinko machine 10, from "Setting 1" to "Setting 6," the probability of achieving a jackpot in high probability mode does not vary depending on the setting of the pachinko machine 10. This makes it possible to limit the impact of the setting of the pachinko machine 10 on the probability of achieving a jackpot to the situation in low probability mode. Furthermore, because the high probability hit/miss table 64g referenced in high probability mode can be made common regardless of the setting of the pachinko machine 10, it is possible to prevent an increase in the storage capacity required to pre-store the hit/miss tables 64a to 64g in the main ROM 64.

While the probability of a jackpot result in low probability mode varies depending on the setting of the pachinko machine 10, from "Setting 1" to "Setting 6," the allocation pattern for the types of jackpot results does not vary depending on the setting of the pachinko machine 10. This makes it possible to limit the impact of the setting of the pachinko machine 10 to the situation in low probability mode. Furthermore, because the allocation table 64h referenced when allocating the types of jackpot results can be made common regardless of the setting of the pachinko machine 10, it is possible to prevent an increase in the storage capacity required to pre-store the allocation table 64h in the main ROM 64.

Even if a new setting is made to the pachinko machine 10, the history information stored in the history memory 117 is not erased but is retained. This makes it possible to continue storing the previous history information in the history memory 117 even if a new setting is made to the pachinko machine 10, and makes it possible to determine the results of game history management using the history information accumulated in the history memory 117 over a long period of time.

In a configuration in which the history information stored in the history memory 117 is not erased but retained even when a new setting is made to the setting state of the pachinko machine 10, when a new setting is made to the setting state of the pachinko machine 10, the corresponding history information is stored in the history memory 117. This makes it possible to distinguish between the history information before the new setting of the setting state of the pachinko machine 10 is made and the history information after the new setting is made.

When a new setting is made to the setting status of the pachinko machine 10 and the corresponding history information is stored in the history memory 117, information corresponding to that setting value is included in that history information. This makes it possible to identify the contents of previously set setting values by referencing the history information.

When the setting value update process (Figure 10) is initiated, the setting value is changed from a predetermined start-related setting value. This makes it possible to change the setting value from a fixed start-related setting value in the setting value update process (Figure 10), regardless of the setting value to be used before the setting value update process (Figure 10) was initiated. This makes it easy for the operator to understand the details of the setting value change operation.

The above starting setting value is specifically "Setting 1," which has the lowest level of advantage. Therefore, when the setting value update process (Figure 10) is initiated, the setting value is changed from "Setting 1," which has the lowest level of advantage. This means that even if the amusement hall manager unintentionally ends the setting value update process (Figure 10) immediately after it has started, the setting value will still have the lowest level of advantage, preventing unintended disadvantages to the amusement hall in such situations.

When calculating various parameters at the calculation timing, the history memory 117 may be configured to use history information corresponding to a new setting of the pachinko machine 10's setting status as a reference, and to calculate various parameters using history information stored later. In this case, it is possible to derive various parameters from the results of managing the game history at the timing after a new setting of the pachinko machine 10's setting status is made.

Furthermore, when various parameters are calculated at the calculation timing, the history information stored in the history memory 117 corresponding to a new setting of the setting state of the pachinko machine 10, which corresponds to a change in setting value, may be used as a reference, and the various parameters may be calculated using history information stored later. In this case, it is possible to derive the results of game history management at the timing after the setting state of the pachinko machine 10 is changed as various parameters.

In addition, while the main control device 60 has been configured with an opening in the circuit board box 60a to expose the reading terminal 68d, it may also be configured without such an opening and with the reading terminal 69d covered by the opposing wall portion 60b. In this case, it will be necessary to open the circuit board box 60a in order to connect an external device to the reading terminal 68d.

Second Embodiment
In this embodiment, the contents of the win/loss table corresponding to the setting state of the pachinko machine 10 are different from those of the first embodiment. Below, the configurations that are different from the first embodiment will be explained. Note that the explanation of the same configurations as the first embodiment will basically be omitted.

Figure 33 is an explanatory diagram illustrating the various tables stored in the main ROM 64 in this embodiment.

As shown in Figure 33, the main ROM 64 has an area 161 for setting 1, an area 162 for setting 2, an area 163 for setting 3, an area 164 for setting 4, an area 165 for setting 5, and an area 166 for setting 6. The area 161 for setting 1 stores a low probability win/lose table 161a for setting 1 that is referenced when the setting state of the pachinko machine 10 is "setting 1" and the win/lose lottery mode is the low probability mode, and a high probability win/lose table 161b for setting 1 that is referenced when the setting state of the pachinko machine 10 is "setting 1" and the win/lose lottery mode is the high probability mode. The setting 2 area 162 stores a setting 2 low-probability win/loss table 162a that is referenced when the setting state of the pachinko machine 10 is "setting 2" and the win/loss lottery mode is the low-probability mode, and a setting 2 high-probability win/loss table 162b that is referenced when the setting state of the pachinko machine 10 is "setting 2" and the win/loss lottery mode is the high-probability mode. The setting 3 area 163 stores a setting 3 low-probability win/loss table 163a that is referenced when the setting state of the pachinko machine 10 is "setting 3" and the win/loss lottery mode is the low-probability mode, and a setting 3 high-probability win/loss table 163b that is referenced when the setting state of the pachinko machine 10 is "setting 3" and the win/loss lottery mode is the high-probability mode.

The area for setting 4 164 stores a low-probability win/loss table 164a for setting 4 that is referenced when the setting state of the pachinko machine 10 is "setting 4" and the win/loss lottery mode is low-probability mode, and a high-probability win/loss table 164b for setting 4 that is referenced when the setting state of the pachinko machine 10 is "setting 4" and the win/loss lottery mode is high-probability mode. The area for setting 5 165 stores a low-probability win/loss table 165a for setting 5 that is referenced when the setting state of the pachinko machine 10 is "setting 5" and the win/loss lottery mode is low-probability mode, and a high-probability win/loss table 165b for setting 5 that is referenced when the setting state of the pachinko machine 10 is "setting 5" and the win/loss lottery mode is high-probability mode. The setting 6 area 166 stores a low probability win/lose table 166a for setting 6 that is referenced when the setting state of the pachinko machine 10 is "setting 6" and the win/lose lottery mode is the low probability mode, and a high probability win/lose table 166b for setting 6 that is referenced when the setting state of the pachinko machine 10 is "setting 6" and the win/lose lottery mode is the high probability mode.

The probability of winning a jackpot set for each of the low-probability tables 161a-166a is different. Specifically, when the low-probability table 161a for setting 1 is referenced, the probability of a jackpot result is approximately 1/320; when the low-probability table 162a for setting 2 is referenced, the probability of a jackpot result is approximately 1/310; when the low-probability table 163a for setting 3 is referenced, the probability of a jackpot result is approximately 1/300; when the low-probability table 164a for setting 4 is referenced, the probability of a jackpot result is approximately 1/290; when the low-probability table 165a for setting 5 is referenced, the probability of a jackpot result is approximately 1/280; and when the low-probability table 166a for setting 6 is referenced, the probability of a jackpot result is approximately 1/270. As a result, when the setting state of the pachinko machine 10 is set to a higher value, a jackpot result is more likely to occur in low probability mode, providing an advantage to the player.

The probability of winning a jackpot set for each of the high-probability tables 161b-166b is different. Specifically, when the high-probability table 161b for setting 1 is referenced, the probability of a jackpot result is approximately 1/45; when the high-probability table 162b for setting 2 is referenced, the probability of a jackpot result is approximately 1/40; when the high-probability table 163b for setting 3 is referenced, the probability of a jackpot result is approximately 1/35; when the high-probability table 164b for setting 4 is referenced, the probability of a jackpot result is approximately 1/30; when the high-probability table 165b for setting 5 is referenced, the probability of a jackpot result is approximately 1/25; and when the high-probability table 166b for setting 6 is referenced, the probability of a jackpot result is approximately 1/20. As a result, when the setting state of the pachinko machine 10 is set to a higher value, a jackpot result is more likely to occur in high-probability mode, which is advantageous for players.

In other words, in the first embodiment described above, the probability of winning a jackpot in low probability mode increases the higher the setting value of the pachinko machine 10, while the probability of winning a jackpot in high probability mode is the same regardless of the setting value from "Setting 1" to "Setting 6." However, in this embodiment, the probability of winning a jackpot in low probability mode and the probability of winning a jackpot in high probability mode both increase the higher the setting value of the pachinko machine 10. This makes it possible to increase the player's advantage by setting a high setting value.

In addition, even the probability of winning a jackpot in low probability mode when the pachinko machine 10 is set to the highest setting, "Setting 6," is set lower than the probability of winning a jackpot in high probability mode when the pachinko machine 10 is set to the lowest setting, "Setting 1." This makes it possible to prevent the player's advantage from becoming extremely low when the pachinko machine 10 is set to "Setting 1," and to prevent the player's advantage from becoming extremely high when the pachinko machine 10 is set to "Setting 6."

On the other hand, just like in the first embodiment, only one type of allocation table 64h is provided so that it is common to all settings from "Setting 1" to "Setting 6." This makes it possible to prevent advantages or disadvantages in the allocation pattern of jackpot results from arising depending on the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to pre-store the allocation table 64h in the main ROM 64.

The configuration may also be such that the probability of winning a jackpot in low probability mode increases as the setting value of the pachinko machine 10 increases, while the probability of winning a jackpot in high probability mode decreases as the setting value of the pachinko machine 10 increases. In this case, it is possible to make it so that the higher the setting value of the pachinko machine 10 in low probability mode, the more advantageous it is for the player, and the lower the setting value of the pachinko machine 10 in high probability mode, the more advantageous it is for the player.

Furthermore, the probability of winning a jackpot in high probability mode increases as the setting value of the pachinko machine 10 increases, while the probability of winning a jackpot in low probability mode may be configured to remain constant across settings of "Setting 1" to "Setting 6." In this case, the higher the setting value of the pachinko machine 10 in high probability mode, the more advantageous it is for the player, and in low probability mode, it is possible to prevent any advantage or disadvantage arising from the setting value of the pachinko machine 10.

Third Embodiment
In this embodiment, the handling of the game history management results when the setting state of the pachinko machine 10 is newly set is different from the first embodiment. Below, the configurations that are different from the first embodiment will be explained. Note that the explanation of the same configurations as the first embodiment will basically be omitted.

In addition to the memories in the first embodiment described above, the management IC 66 is also provided with a separate storage memory 171 for storing information. Figure 34 is an explanatory diagram for explaining the separate storage memory 171. The separate storage memory 171 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or NAND flash memory, and is used for both reading and writing.

The separate storage memory 171 is provided with a first separate storage area 172, a second separate storage area 173, a third separate storage area 174, a fourth separate storage area 175, and a fifth separate storage area 176. These first through fifth separate storage areas 172-176 sequentially store information on the game history management results calculated when the setting state of the pachinko machine 10 is newly set, more specifically, the various parameters described in the first embodiment above (the first through eighth parameters, the eleventh through eighteenth parameters, the twenty-first through twenty-sixth parameters, the thirty-first parameter, and the forty-first and forty-second parameters). In this case, when the setting state of the pachinko machine 10 is newly set, the various parameters are first stored in the first separate storage area 172. Thereafter, each time the setting state of the pachinko machine 10 is newly set, the storage area is switched from the nth separate storage area 172-176 to the n+1th separate storage area 172-176. Then, if the settings of the pachinko machine 10 are newly set after the various parameters have been stored in the fifth separate storage area 176, the various parameters are stored again in the first separate storage area 172. At this time, the various parameters already stored in the first separate storage area 172 are erased. As a result, the various parameters up to the fiveth time that a new setting of the settings of the pachinko machine 10 has been executed are stored in the separate storage memory 171, and for parameters exceeding five times, the oldest various parameters are erased and stored.

The various parameters stored in the first through fifth separate storage areas 172-176 can be read by an external device by connecting the external device to the reading terminal 68d. This makes it possible to understand the results of game history management before new settings are made in the pachinko machine 10.

Next, the setting update recognition process executed by the management CPU 112 in this embodiment will be explained with reference to the flowchart in Figure 35.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a LOW level to a HIGH level (step S1801: YES), the value of the setting value grasp counter in the management RAM 114 is set to "1" (step S1802). The setting value grasp counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10; for example, a setting value grasp counter value of "1" indicates "setting 1," and a setting value grasp counter value of "6" indicates "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S1803). If a positive determination is made in step S1803, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S1804). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S1803, or if the processing of step S1804 is executed, it is determined whether a set value identification end command has been received from the primary CPU 63 based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1805). If a negative determination is made in step S1805, processing returns to step S1803.

If a positive judgment is made in step S1805, a process for monitoring repeated changes is executed (step S1806). The process for monitoring repeated changes, which will be described in detail later, executes a process for notifying the user when new settings of the pachinko machine 10 are repeatedly made in a short period of time. In a configuration in which various parameters are stored in the separate storage memory 171 each time a new setting is made to the pachinko machine 10, it is expected that new settings of the pachinko machine 10 will be repeatedly made in a short period of time in order to intentionally erase the management results of the game history when play has been performed over a predetermined period of time. In response to this, the process for monitoring repeated changes is executed, and a corresponding notification will be issued if such an action is taken.

After that, various calculation processes are executed (step S1807). In the various calculation processes, steps S1402 to S1412 of the display output process (FIG. 30) in the first embodiment are executed. As a result, various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameters 31, and parameters 41 to 42) are calculated using the history information stored in the history memory 117 at that time.

Then, the various parameters calculated in step S1807 are stored in the current storage target area among the first to fifth separate storage areas 172-176 in the separate storage memory 171 (step S1808). A pointer information area is set in the separate storage memory 171 to enable the management CPU 112 to identify the storage target area among the first to fifth separate storage areas 172-176. The information in this pointer information area is updated so that when various parameters are stored in the storage target area among the first to fifth separate storage areas 172-176, the storage target is changed to the next sequential area. By executing the processing of step S1808, the various parameters at that time for the new setting of the current setting status of the pachinko machine 10 are stored in the separate storage memory 171.

Then, the history memory 117 is cleared to "0" (step S1809). In other words, in this embodiment, the history information in the history memory 117 is erased not only when the history information is read by an external device connected to the reading terminal 68d, but also when a new setting is made to the pachinko machine 10.

Then, RTC information, which is date and time information, is read from the RTC 115 (step S1810). Then, a write process to the history memory 117 is executed (step S1811). In this write process, the pointer information in the history area 124 that is currently being written to is identified by referencing the pointer area 126 of the history memory 117, and the RTC information read in step S1810 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is being written to. In addition, both information identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 that corresponds to the pointer information that is being written to. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

Then, the target pointer is updated (step S1812). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. A determination is made as to whether the pointer information after incrementing by 1 has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by 1 is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

Next, the repeated change monitoring process executed in step S1806 will be explained with reference to the flowchart in Figure 36.

First, it is determined whether the number of times a game has been played since the setting state of the pachinko machine 10 was last set is within a reference number (specifically, 100 times) (step S1901). Specifically, the number of times a game has been played since the setting state of the pachinko machine 10 was last set is determined by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence information indicating the start of a game is stored, and it is then determined whether the determined number of times a game has been played is within a reference number (specifically, 100 times).

If a positive judgment is made in step S1901, the value of the repeat change counter provided in the separate storage memory 171 is incremented by 1 (step S1902). As already explained, the separate storage memory 171 is a memory that does not require an external power supply to retain its memory, and therefore does not require an external power supply to retain the value of the repeat change counter.

Then, it is determined whether the value of the repeat change counter after adding 1 exceeds the notification reference value of "5" (step S1903). The notification reference value corresponds to the number of the first through fifth separate storage areas 172-176 provided in the separate storage memory 171. Therefore, in step S1903, it is determined whether the number of times the new setting of the setting state of the pachinko machine 10 has been repeated without the execution of more than the reference number of games exceeds the number of the first through fifth separate storage areas 172-176.

If a positive judgment is made in step S1903, a repeat change display process is executed (step S1904). In the repeat change display process, the display content of the first through third notification display devices 69a through 69c is changed to a repeat change display content corresponding to the fact that a new setting of the pachinko machine 10 has been repeated a number of times exceeding the notification reference value in a short period of time. The repeat change display content is a display content that displays "E" on all first through third notification display devices 69a through 69c, and this display content does not appear under other circumstances. Furthermore, the state in which the repeat change display content is displayed on the first through third notification display devices 69a through 69c continues until the repeat change flag stored in the separate storage memory 171 is cleared to "0." The repeat change flag is a flag that the management CPU 112 uses to identify a situation in which the repeat change display content should be displayed on the first through third notification display devices 69a through 69c. Furthermore, if the repeat change flag is set to "1" and the repeat change display content is being displayed on the first to third notification display devices 69a to 69c, the display process in the first embodiment (Figure 31) is not executed. After that, the repeat change flag in the separate storage memory 171 is set to "1" (step S1905).

If the determination in step S1901 is negative, the value of the repeat change counter in the separate storage memory 171 is cleared to "0" (step S1906). Then, provided that the repeat change flag in the separate storage memory 171 is set to "1" (step S1907: YES), the display of the repeat change display content on the first to third notification display devices 69a to 69c is terminated (step S1908), and the repeat change flag is cleared to "0" (step S1909).

The present embodiment described above provides the following excellent effects:

When a new setting is made to the pachinko machine 10, the history information stored in the history memory 117 is erased. This makes it possible to leave in the history memory 117 the history information from games played after a new setting is made to the pachinko machine 10.

When a new setting is made to the pachinko machine 10, various parameters are calculated as the results of game history management using the history information in the history memory 117 at that time. This makes it possible to understand the game history management results in the situation before the new setting is made to the pachinko machine 10. Furthermore, even if the history information in the history memory 117 is erased when a new setting is made to the pachinko machine 10, it is possible to understand the game history management results based on the history information to be erased.

When a new setting is made in the pachinko machine 10, various parameters are calculated using the history information in the history memory 117 at that time, and these calculated parameters are stored in the separate storage memory 171. This makes it possible to grasp the gaming history management results from the situation before the new setting was made at any time thereafter, even if a new setting is made in the pachinko machine 10.

By providing multiple separate storage areas 172-176 in the separate storage memory 171, it is possible to store various parameters corresponding to the timing of multiple setting states. This makes it possible to understand the results of game history management over multiple periods, based on the timing at which new setting states were established. Furthermore, even if new setting states are repeatedly established for the pachinko machine 10 when no game is being played, it is possible to increase the likelihood that various parameters calculated using history information from situations in which game play is actually being played will remain in the separate storage memory 171.

The various parameters stored in the first through fifth separate storage areas 172-176 can be read by an external device by connecting the external device to the reading terminal 68d. This makes it possible to understand the results of game history management before new settings are made in the pachinko machine 10.

In a configuration in which various parameters are stored in the separate storage memory 171 each time a new setting is made to the pachinko machine 10, it is anticipated that new settings will be made repeatedly over a short period of time to intentionally erase the management results of the game history when play has been performed over a predetermined period of time. In response to this, by executing a process to monitor repeated changes, a corresponding notification will be issued if such an action is taken. This makes it possible to notify an administrator or the like that new settings have been made repeatedly over a short period of time to the pachinko machine 10.

The first to third notification display devices 69a to 69c notify the user that new settings have been repeatedly made to the pachinko machine 10 within a short period of time. This makes it possible to use the first to third notification display devices 69a to 69c, which are used to notify the user of the results of game history management, to notify the user that new settings have been repeatedly made to the pachinko machine 10 within a short period of time.

In situations where it is necessary to notify that new settings have been repeatedly made to the pachinko machine 10 in a short period of time, the first to third notification display devices 69a to 69c continue to display the repeated changes, and the first to third notification display devices 69a to 69c do not notify the results of management of the normal game history. This makes it possible to emphasize the notification that new settings have been repeatedly made to the pachinko machine 10 in a short period of time.

In the above configuration, a corresponding alert is issued when the number of times a new setting is made exceeds an alert reference value and the number of times the new setting is made is within a reference number. However, this is not limited to this configuration, and a corresponding alert may be issued when the total number of game balls discharged from the play area PA after a new setting is made is within a reference number and the number of times the new setting is made exceeds an alert reference value and the number of times the new setting is made is within a reference number. Also, a corresponding alert may be issued when the total number of game balls discharged into a predetermined ball entry section (e.g., the outlet port 24a, the general winning port 31, the first actuation port 33, or the second actuation port 34, or a predetermined combination thereof) after a new setting is made is within a reference number and the number of times the new setting is made exceeds an alert reference value and the number of times the new setting is made is within a reference number. Alternatively, if the total number of pieces of history information newly stored in the history memory 117 after a new setting of the setting status of the pachinko machine 10 is made is within a reference number, and the number of consecutive events for which the new setting is made exceeds the notification reference value, a corresponding notification may be issued.

Also, if a new setting of the pachinko machine 10 exceeds the notification reference value within a monitoring reference period (e.g., 600 seconds), a corresponding notification may be issued.

In addition, the configuration is such that a corresponding notification is issued if the number of times a game has been played since a new setting was made to the pachinko machine 10 is within a reference number of times and the number of consecutive times that the new setting is made exceeds the notification reference value.However, the configuration may also be such that a corresponding notification is issued if the number of consecutive times that a setting value is changed exceeds the notification reference value and the number of consecutive times that the number of consecutive times that the game has been played since a new setting was made to the pachinko machine 10 is within the reference number.

In addition, the configuration is such that a corresponding notification is issued when the number of games played since the setting of the pachinko machine 10 was newly set is within a reference number and the number of consecutive games in which the new setting is performed exceeds a notification reference value.However, the configuration may also be such that a corresponding notification is issued when the number of games played since the setting of the pachinko machine 10 was newly set is within a reference number and the number of consecutive games in which various parameters are calculated as a result of the new setting exceeds a notification reference value.

Furthermore, if the number of times a game has been played since a new setting was made to the pachinko machine 10 is within a reference number of times, and the number of consecutive events in which the new setting is made exceeds the notification reference value, a corresponding notification is issued. However, in addition to or instead of this, the progress of play may be limited for a predetermined period of time (for example, one hour).

<Fourth embodiment>
This embodiment differs from the third embodiment in that the repeated change monitoring process is executed by the main CPU 63. The following describes the configuration that differs from the third embodiment. Note that the description of the same configuration as the third embodiment will basically be omitted.

Figure 37 is a flowchart showing the repeat change monitoring process executed by the main CPU 63. Note that the repeat change monitoring process is executed when the setting value update process (step S118) is executed in the main process ( Figure 9 ). In other words, the repeat change monitoring process is executed when a new setting state of the pachinko machine 10 is set. However, this is not limited to this, and the repeat change monitoring process may be configured to be executed when the setting value is changed.

First, it is determined whether the number of times a game has been played since the setting state of the pachinko machine 10 was last set is within a reference number (specifically, 100 times) (step S2001). The main RAM 65 is provided with a game count counter for measuring the number of times a game has been played since the setting state of the pachinko machine 10 was newly set, and the main CPU 63 increments the value of the game count counter by 1 each time a new game is played. This game count counter is excluded from being cleared to "0" even when the main RAM 65 clearing process (steps S105, S117) is executed.

If a positive judgment is made in step S2001, the value of the repeat change counter stored in the main RAM 65 is incremented by 1 (step S2002). This repeat change counter is excluded from being cleared to "0" even when the main RAM 65 clearing process (steps S105 and S117) is executed.

Then, it is determined whether the value of the repeat change counter after incrementing by 1 exceeds the notification reference value of "5" (step S2003). The notification reference value corresponds to the number of first through fifth separate storage areas 172-176 provided in the separate storage memory 171. Therefore, in step S2003, it is determined whether the number of times the new setting of the pachinko machine 10 has been repeated without an intervening game play exceeding the reference number of times exceeds the number of first through fifth separate storage areas 172-176.

If a positive judgment is made in step S2003, the repeat change flag stored in the main RAM 65 is set to "1" (step S2004). The repeat change flag is a flag used by the main CPU 63 to identify situations in which a repeat change notification should be issued. The repeat change flag is excluded from being cleared to "0" even when the main RAM 65 clearing process (steps S105 and S117) is executed.

If the determination in step S2001 is negative, the value of the repeat change counter in the main RAM 65 is cleared to "0" (step S2005). Then, if the repeat change flag in the main RAM 65 is set to "1" (step S2006: YES), the repeat change flag is cleared to "0" (step S2007).

In the repeat change monitoring process, if the repeat change flag in the main RAM 65 is set to "1" (step S2008: YES), a repeat change notification command is sent to the audio and light-emitting control device 81 (step S2009). When the audio and light-emitting control device 81 receives the repeat change notification command, it causes the pattern display device 41, display light-emitting unit 53, and speaker unit 54 to notify the repeat change. The repeat change notification continues until the supply of operating power to the audio and light-emitting control device 81 is stopped.

With the above configuration, it is possible to notify the administrator that new settings have been repeatedly made to the pachinko machine 10 in a short period of time, based on control by the main CPU 63. Furthermore, because this notification is made by the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54, it is possible to make the administrator aware that new settings have been repeatedly made to the pachinko machine 10 in a short period of time, without having to open the gaming machine main body 12 forward relative to the outer frame 11.

In addition to or instead of a configuration in which a notification command for repeated changes to the setting status of the pachinko machine 10 is sent from the main CPU 63 to the audio and light control device 81 when new settings are made repeatedly within a short period of time, a corresponding external output may be generated.

Alternatively, the main CPU 63 may be configured to execute the repeated change monitoring process of this embodiment, while the management CPU 112 may be configured to execute the repeated change monitoring process of the third embodiment. This makes it possible to closely monitor whether new settings for the pachinko machine 10 are repeatedly made within a short period of time.

Fifth Embodiment
In this embodiment, the processing configuration of the setting update recognition process in the management CPU 112 differs from that of the third embodiment. The configuration that differs from the third embodiment will be described below. Note that the description of the same configuration as the third embodiment will basically be omitted.

Figure 38 is a flowchart showing the setting update recognition process in this embodiment, executed by the management CPU 112.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from LOW level to HIGH level (step S2101: YES), the value of the setting value grasp counter in the management RAM 114 is set to "1" (step S2102). The setting value grasp counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10; for example, a setting value grasp counter value of "1" indicates "setting 1," and a setting value grasp counter value of "6" indicates "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2103). If a positive determination is made in step S2103, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S2104). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2103, or if the processing of step S2104 is executed, it is determined whether a set value identification end command has been received from the main CPU 63 based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2105). If a negative determination is made in step S2105, processing returns to step S2103.

If a positive determination is made in step S2105, it is determined whether or not a predetermined number of pieces of predetermined history information exist in the history memory 117 (step S2106). Specifically, the number of history information storage areas 125 in which correspondence information indicating the start of a game is stored in the history area 124 of the history memory 117 is counted to determine the number of games that have been played since the setting state of the pachinko machine 10 was last set, and it is then determined whether or not the determined number of games has exceeded a reference number (specifically, 100). However, this is not limited to this, and step S2106 may be configured to determine whether or not the number of history information storage areas 125 in which correspondence information indicating that game balls have been ejected from the play area PA is stored exceeds a reference number (specifically, 1,000). Alternatively, step S2106 may be configured to determine whether the number of history information storage areas 125 storing correspondence relationship information indicating that game balls have entered a predetermined ball entry section (for example, any one of the outlet 24a, general entry port 31, first actuation port 33, and second actuation port 34, or a predetermined combination thereof) exceeds a reference number (specifically, 1,000). Alternatively, step S2106 may be configured to determine whether the total number of pieces of history information stored in the history memory 117 exceeds a reference number (specifically, 1,000).

In the above configuration, a corresponding alert is issued when the number of times a new setting is made exceeds an alert reference value and the number of times the new setting is made is within a reference number. However, this is not limited to this configuration, and a corresponding alert may be issued when the total number of game balls discharged from the play area PA after a new setting is made is within a reference number and the number of times the new setting is made exceeds an alert reference value and the number of times the new setting is made is within a reference number. Also, a corresponding alert may be issued when the total number of game balls discharged into a predetermined ball entry section (e.g., the outlet port 24a, the general winning port 31, the first actuation port 33, or the second actuation port 34, or a predetermined combination thereof) after a new setting is made is within a reference number and the number of times the new setting is made exceeds an alert reference value and the number of times the new setting is made is within a reference number. Alternatively, if the total number of pieces of history information newly stored in the history memory 117 after a new setting of the setting status of the pachinko machine 10 is made is within a reference number, and the number of consecutive events for which the new setting is made exceeds the notification reference value, a corresponding notification may be issued.

If a positive determination is made in step S2106, various calculation processes are executed (step S2107). These calculation processes include steps S1402 to S1412 of the display output process (FIG. 30) in the first embodiment described above. As a result, various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameters 31, and parameters 41 to 42) are calculated using the history information stored in history memory 117 at that time.

Then, the various parameters calculated in step S2107 are stored in the current storage target area among the first to fifth separate storage areas 172-176 in the separate storage memory 171 (step S2108). A pointer information area is set in the separate storage memory 171 to enable the management CPU 112 to identify the storage target area among the first to fifth separate storage areas 172-176. The information in this pointer information area is updated so that when various parameters are stored in the storage target area among the first to fifth separate storage areas 172-176, the storage target is changed to the next sequential area. By executing the processing of step S2108, the various parameters at that time for the new setting of the current setting status of the pachinko machine 10 are stored in the separate storage memory 171.

If a negative judgment is made in step S2106, or if the processing of step S2108 is executed, the history memory 117 is cleared to "0" (step S2109). In other words, in this embodiment, the history information in the history memory 117 is erased not only when the history information is read by an external device connected to the reading terminal 68d, but also when a new setting state is set for the pachinko machine 10.

Then, RTC information, which is date and time information, is read from the RTC 115 (step S2110). Then, a write process to the history memory 117 is executed (step S2111). In this write process, the pointer information in the history area 124 that is currently being written to is identified by referencing the pointer area 126 of the history memory 117, and the RTC information read in step S2110 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is being written to. In addition, both information identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 that corresponds to the pointer information that is being written to. This results in a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made being stored as history information.

Then, the target pointer is updated (step S2112). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. A determination is made as to whether the pointer information after incrementing by 1 has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by 1 is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

With the above configuration, when the setting state of the pachinko machine 10 is newly set, various parameters are calculated using the history information stored in the history memory 117, and these various parameters are stored in the separate storage memory 171, provided that a predetermined number of pieces of history information are stored in the history memory 117. This makes it possible to store information on the management results of the game history as a result of actual game play, even if new settings of the pachinko machine 10 are repeatedly made in a short period of time, in the separate storage memory 171.

The processing of step S2109 may be configured to be executed on the condition that the processing of steps S2107 and S2108 has been executed. In other words, the history information stored in the history memory 117 is erased on the condition that a predetermined number of pieces of history information or more are stored in the history memory 117. This makes it possible to prevent the history information in the history memory 117 from being erased even if new settings for the setting state of the pachinko machine 10 are repeatedly made in a short period of time.

Sixth Embodiment
In this embodiment, the configuration of the history memory 117 is different from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 39 is an explanatory diagram illustrating the configuration of the history memory 117 in this embodiment.

The history memory 117 has a total area 141, a first state area 142, a second state area 143, and a third state area 144. Each of these areas 141-144 has first to fourteenth counters 141a-141n, 142a-142n, 143a-143n, and 144a-144n. The first counters 141a-144a in each of areas 141-144 store information on the number of times the output state of the first signal input to the first buffer 122a has changed from a low level to a high level. The second counters 141b-144b in each of areas 141-144 store information on the number of times the output state of the second signal input to the second buffer 122b has changed from a low level to a high level. The third counters 141c to 144c in each of the areas 141 to 144 store information on the number of times the output state of the third signal input to the third buffer 122c has changed from a low level to a high level. The fourth counters 141d to 144d in each of the areas 141 to 144 store information on the number of times the output state of the fourth signal input to the fourth buffer 122d has changed from a low level to a high level. The fifth counters 141e to 144e in each of the areas 141 to 144 store information on the number of times the output state of the fifth signal input to the fifth buffer 122e has changed from a low level to a high level. The sixth counters 141f to 144f in each of the areas 141 to 144 store information on the number of times the output state of the sixth signal input to the sixth buffer 122f has changed from a low level to a high level. The seventh counters 141g to 144g in each of the areas 141 to 144 store information on the number of times the output state of the seventh signal input to the seventh buffer 122g has changed from a low level to a high level. The eighth counters 141h to 144h in each of the areas 141 to 144 store information on the number of times the output state of the eighth signal input to the eighth buffer 122h has changed from a low level to a high level. The ninth counters 141i to 144i in each of the areas 141 to 144 store information on the number of times the output state of the ninth signal input to the ninth buffer 122i has changed from a low level to a high level. The tenth counters 141j to 144j in each of the areas 141 to 144 store information on the number of times the output state of the tenth signal input to the tenth buffer 122j has changed from a low level to a high level. The eleventh counters 141k to 144k in each of areas 141 to 144 store information on the number of times the output state of the eleventh signal input to the eleventh buffer 122k has changed from low to high. The twelfth counters 141l to 144l in each of areas 141 to 144 store information on the number of times the output state of the twelfth signal input to the twelfth buffer 122l has changed from low to high. The thirteenth counters 141m to 144m in each of areas 141 to 144 store information on the number of times the output state of the thirteenth signal input to the thirteenth buffer 122m has changed from low to high. The fourteenth counters 141n to 144n in each of areas 141 to 144 store information on the number of times the output state of the fourteenth signal input to the fourteenth buffer 122n has changed from low to high.

Figure 40 is a flowchart showing the history setting process in this embodiment, which is executed by the management CPU 112.

First, the number of buffers to be checked by the management CPU 112, among the first through fourteenth buffers 122a through 122n, is set in the confirmation target counter in the management RAM 114 (step S2201). Specifically, the number of correspondence areas in the correspondence memory 116, among the first through fourteenth correspondence areas 123a through 123n, that store information other than information indicating that they are blank is identified, and the information for this identified number is set in the confirmation target counter. In this pachinko machine 10, information other than information indicating that they are blank is stored in the first through eleventh correspondence areas 123a through 123k, so in step S2201, the confirmation target counter is set to "11."

Then, it is determined whether the buffer 122a-122n corresponding to the current counter to be checked is a buffer to which a status information signal is input (step S2202). Specifically, it is determined whether any of the following correspondence information is stored in the correspondence area 123a-123n corresponding to the current counter value to be checked: information indicating open/close execution mode, information indicating high-frequency support mode, or information indicating the front door frame 14.

If a positive judgment is made in step S2202, a state information setting process is executed (step S2203). In this setting process, if the output state of an eighth signal indicating whether the device is in the opening/closing execution mode switches from a low level to a high level, first state information indicating that the device is in the opening/closing execution mode is stored in the management RAM 114. If the output state of the eighth signal switches from a high level to a low level, the first state information is erased from the management RAM 114. Furthermore, if the output state of a ninth signal indicating whether the device is in the high frequency support mode switches from a low level to a high level, second state information indicating that the device is in the high frequency support mode is stored in the management RAM 114. If the output state of the ninth signal switches from a high level to a low level, the second state information is erased from the management RAM 114. Furthermore, when the output state of the tenth signal, which indicates whether the front door frame 14 is open or not, switches from a low level to a high level, third state information indicating that the front door frame 14 is open is stored in the management RAM 114, and when the output state of the tenth signal switches from a high level to a low level, the third state information is erased from the management RAM 114.

If a negative judgment is made in step S2202, or if the processing of step S2203 is executed, it is determined whether the numerical information stored in the buffer corresponding to the current counter value to be checked among the first to fourteenth buffers 122a to 122n has changed from "0" to "1," thereby determining whether the output state of the input signal from the main CPU 63 to that buffer has been switched from a low level to a high level (step S2204). Note that if the numerical information stored in the eighth buffer 122h has changed from "0" to "1" when the current counter value to be checked corresponds to the value of the eighth buffer 122h, the first state information is stored in the management RAM 114 in step S2203, and a positive judgment is made in step S2204. Furthermore, if the current value of the counter to be checked is a value corresponding to the ninth buffer 122i and the numerical information stored in the ninth buffer 122i is changed from "0" to "1", second state information is stored in the management RAM 114 in step S2203, and a positive determination is made in step S2204. Furthermore, if the current value of the counter to be checked is a value corresponding to the tenth buffer 122j and the numerical information stored in the tenth buffer 122j is changed from "0" to "1", third state information is stored in the management RAM 114 in step S2203, and a positive determination is made in step S2204.

If a positive judgment is made in step S2204, an increment process is performed on the corresponding total counter (step S2205). In this increment process, one is added to the value of the counter corresponding to the current value of the counter to be checked, among the first to fourteenth total counters 141a to 141n in the total area 141 of the history memory 117. For example, if the value of the counter to be checked is "11," the eleventh total counter 141k is added; if the value of the counter to be checked is "5," the fifth total counter 141e is added; and if the value of the counter to be checked is "1," the first total counter 141a is added.

Then, by referencing the status information in the management RAM 114, it is determined whether the device is in the first state, i.e., whether it is in the open/close execution mode (step S2206). If the device is in the first state (step S2206: YES), an increment process is performed on the corresponding counter for the first state (step S2207). In this increment process, one is added to the value of the counter corresponding to the current value of the counter to be checked, among the first through fourteenth counters 142a through 142n for the first state in the first state area 142 of the history memory 117. For example, if the value of the counter to be checked is "11," the eleventh counter 142k for the first state is added; if the value of the counter to be checked is "5," the fifth counter 142e for the first state is added; and if the value of the counter to be checked is "1," the first counter 142a for the first state is added.

Then, by referencing the status information in the management RAM 114, it is determined whether the device is in the second state, i.e., whether it is in high-frequency support mode (step S2208). If the device is in the second state (step S2208: YES), an increment process is performed on the corresponding counter for the second state (step S2209). In this increment process, one is added to the value of the counter corresponding to the current value of the counter to be checked, among the first to fourteenth counters 143a to 143n for the second state in the second state area 143 of the history memory 117. For example, if the value of the counter to be checked is "11," the eleventh counter 143k for the second state is added; if the value of the counter to be checked is "5," the fifth counter 143e for the second state is added; and if the value of the counter to be checked is "1," the first counter 143a for the second state is added.

Then, by referencing the status information in the management RAM 114, it is determined whether the state is the third state, i.e., whether the front door frame 14 is open (step S2210). If the state is the third state (step S2210: YES), an increment process is performed on the corresponding counter for the third state (step S2211). In this increment process, one is added to the value of the counter corresponding to the current value of the counter to be checked, among the first through fourteenth counters 144a to 144n for the third state in the third state area 144 of the history memory 117. For example, if the value of the counter to be checked is "11," the eleventh counter 144k for the third state is added; if the value of the counter to be checked is "5," the fifth counter 144e for the third state is added; and if the value of the counter to be checked is "1," the first counter 144a for the third state is added.

If a negative judgment is made in step S2204, if a negative judgment is made in step S2210, or if the processing of step S2211 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S2212). Then, it is determined whether the value of the confirmation target counter after the decrement is "0" (step S2213). If the value of the confirmation target counter is 1 or greater (step S2213: NO), the processing from step S2202 onwards is executed for the confirmation target corresponding to the new value of the confirmation target counter.

By executing the history setting process as described above, the number of times game balls enter the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34, the number of times the open/close execution mode occurs, the number of times the high-frequency support mode occurs, and the number of times a game has occurred are stored as count information rather than as history information as in the first embodiment above. This makes it possible to reduce the storage capacity required in the history memory 117 compared to a configuration in which each piece of history information is stored individually.

By storing the number of times information rather than history information in this way, there is no need to perform a process to derive the number of times information from the history information when calculating various parameters. This makes it possible to reduce the processing load required to calculate various parameters.

Next, the setting update recognition process executed by the management CPU 112 in this embodiment will be explained with reference to the flowchart in Figure 41.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from LOW to HIGH (step S2301: YES), the value of the setting value grasp counter in the management RAM 114 is set to "1" (step S2302). The setting value grasp counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10; for example, a setting value grasp counter value of "1" indicates "setting 1," and a setting value grasp counter value of "6" indicates "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2303). If a positive determination is made in step S2303, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S2304). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2303, or if the processing of step S2304 is executed, it is determined whether a set value identification end command has been received from the primary CPU 63 based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2305). If a negative determination is made in step S2305, processing returns to step S2303.

If a positive judgment is made in step S2305, the following counters are cleared to "0": the eleventh total counter 141k, which counts the number of times a game has been played in the total area 141 in the history memory 117; the eighth total counter 141h, which counts the number of times the open/close execution mode has occurred in the total area 141 in the history memory 117; and the ninth total counter 141i, which counts the number of times the high frequency support mode has occurred in the total area 141 in the history memory 117 (steps S2306 to S2308). As a result, the count information for the number of times a game has been played, the number of times the open/close execution mode has occurred, and the number of times the high frequency support mode has occurred are cleared to "0" in response to the new setting of the pachinko machine 10. Therefore, the calculation results of the 31st parameter, which indicates the number of times the open/close execution mode occurs per unit play, the 41st parameter, which indicates the number of times the high-frequency support mode occurs per unit play, and the 42nd parameter, which indicates the ratio of the number of times the high-frequency support mode occurs to the number of times the open/close execution mode occurs, correspond to the game content after the new setting of the pachinko machine 10. In a configuration in which the probability of winning a jackpot changes when the setting value of the pachinko machine 10 is changed, by making the calculation results of the 31st parameter, 41st parameter, and 42nd parameter correspond to the game content after the new setting of the pachinko machine 10, as described above, it becomes possible to determine whether the calculation results of the 31st parameter, 41st parameter, and 42nd parameter are appropriate based on the current setting value.

On the other hand, even if a new setting is made to the setting state of the pachinko machine 10, counters other than the eighth total counter 141h, the ninth total counter 141i, and the eleventh total counter 141k in the history memory 117 are not cleared to "0." This makes it possible to manage the number or frequency of game balls entering each history target ball entry section based on long-term game history, without being affected by the new setting of the setting state of the pachinko machine 10.

With the above configuration, the number of times game balls enter the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34, the number of times the open/close execution mode occurs, the number of times the high-frequency support mode occurs, and the number of times a game has occurred are stored as count information rather than as history information as in the first embodiment. This makes it possible to reduce the storage capacity required in the history memory 117 compared to a configuration in which each piece of history information is stored individually.

Furthermore, by storing the information as count information rather than history information in this way, there is no need to perform a process to derive count information from history information when calculating various parameters. This makes it possible to reduce the processing load required to calculate various parameters.

The count information for the number of game plays, the number of times the open/close execution mode occurred, and the number of times the high-frequency support mode occurred is cleared to "0" when a new setting is made to the pachinko machine 10. Therefore, the calculation results of parameter 31, which indicates the number of times the open/close execution mode occurred per game play, parameter 41, which indicates the number of times the high-frequency support mode occurred per game play, and parameter 42, which indicates the ratio of the number of times the high-frequency support mode occurred to the number of times the open/close execution mode occurred, correspond to the game content after the new setting is made to the pachinko machine 10. In a configuration in which the probability of winning a jackpot changes when the setting value of the pachinko machine 10 is changed, by making the calculation results of parameter 31, parameter 41, and parameter 42 correspond to the game content after the new setting is made to the pachinko machine 10, as described above, it becomes possible to determine whether the calculation results of parameter 31, parameter 41, and parameter 42 are appropriate based on the current setting value.

On the other hand, even if a new setting is made to the setting state of the pachinko machine 10, counters other than the eighth total counter 141h, the ninth total counter 141i, and the eleventh total counter 141k in the history memory 117 are not cleared to "0." This makes it possible to manage the number or frequency of game balls entering each history target ball entry section based on long-term game history, without being affected by the new setting of the setting state of the pachinko machine 10.

The configuration of the history memory 117 as in this embodiment may be applied to the first to fifth embodiments described above and the embodiments described after this embodiment. For example, when applied to the first embodiment, the information in the history memory 117 is maintained as is even if a new setting is made to the setting state of the pachinko machine 10. Furthermore, when applied to the third embodiment, the entire history memory 117 is cleared to "0" when a new setting is made to the setting state of the pachinko machine 10.

Furthermore, the processing of steps S2306 to S2308 may be executed in the setting update recognition process (FIG. 41) when the setting value of the pachinko machine 10 is changed. This means that even if a new setting is made to the pachinko machine 10, if the setting value is not changed before and after the change, the information on the number of game plays executed, the number of times the open/close execution mode has occurred, and the number of times the high-frequency support mode has occurred will not be cleared to "0." It is possible to clear the information on the number of game plays executed, the number of times the open/close execution mode has occurred, and the number of times the high-frequency support mode has occurred to "0" when the setting value of the pachinko machine 10 is changed.

Also, before the processing of steps S2306 to S2308 is executed in the setting update recognition processing (Figure 41), various parameters may be calculated using the counters 141 to 144 in the history memory 117, and the calculated parameters may be stored in the calculation result memory 131.

Seventh Embodiment
In this embodiment, the configuration of the history memory 117 is different from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 42 is an explanatory diagram illustrating the configuration of the history memory 117 in this embodiment.

The history memory 117 includes history memories 181-186 corresponding to the setting states of the pachinko machine 10, "Setting 1" through "Setting 6." Specifically, a history memory 181 for setting 1 is provided corresponding to "Setting 1," a history memory 182 for setting 2 is provided corresponding to "Setting 2," a history memory 183 for setting 3 is provided corresponding to "Setting 3," a history memory 184 for setting 4 is provided corresponding to "Setting 4," a history memory 185 for setting 5 is provided corresponding to "Setting 5," and a history memory 186 for setting 6 is provided corresponding to "Setting 6."

Each of the history memories 181-186 for settings 1-6 is provided with a combination of the history area 124 and pointer area 126 of the history memory 117 in the first embodiment. This makes it possible to store history information corresponding to each of the pachinko machine 10's setting states, "Setting 1" to "Setting 6." In this case, when a new setting is made to the pachinko machine 10, the history memories 181-186 corresponding to the newly set setting value are used to store the history information. This makes it possible to store history information separately for each setting value without erasing the history information when a new setting is made to the pachinko machine 10. Furthermore, because various parameters are calculated using history information corresponding to the currently set setting state of the pachinko machine 10, it is possible to appropriately derive various parameters corresponding to each setting value.

In addition, each of the history memories 181-186 for settings 1-6 may be configured to contain a combination of the total area 141, first state area 142, second state area 143, and third state area 144 in the sixth embodiment.

Next, the setting update recognition process executed by the management CPU 112 in this embodiment will be explained with reference to the flowchart in Figure 43.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a low level to a high level (step S2401: YES), the value of the setting value grasp counter provided in the calculation result memory 131 is set to "1" (step S2402). The setting value grasp counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10. For example, a setting value grasp counter value of "1" indicates "setting 1," and a setting value grasp counter value of "6" indicates "setting 6." In addition, in this embodiment, the setting value grasp counter is provided in the calculation result memory 131, which is a memory that does not require an external power supply for memory retention. Therefore, the value stored in the setting value grasp counter is retained even if the supply of operating power to the management IC 66 is stopped.

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2403). If a positive determination is made in step S2403, the value of the setting value grasp counter in the calculation result memory 131 is incremented by 1 (step S2404). As a result, the setting value of the pachinko machine 10 identified by the management CPU 112 is increased by one level.

If a negative determination is made in step S2403, or if the processing of step S2404 is executed, it is determined whether a set value identification end command has been received from the main CPU 63 based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2405). If a negative determination is made in step S2405, processing returns to step S2403.

If a positive judgment is made in step S2405, the history memories 181-186 corresponding to the value of the setting value grasp counter in the calculation result memory 131 are set as the storage target for history information and the reference target when calculating various parameters (step S2406). Specifically, if the value of the setting value grasp counter is "1," this means that "Setting 1" has been set, so the history memory 181 for Setting 1 is set as the storage target for history information and the reference target when calculating various parameters. Furthermore, if the value of the setting value grasp counter is "2," this means that "Setting 2" has been set, so the history memory 182 for Setting 2 is set as the storage target for history information and the reference target when calculating various parameters. Furthermore, if the value of the setting value grasp counter is "3," this means that "Setting 3" has been set, so the history memory 183 for Setting 3 is set as the storage target for history information and the reference target when calculating various parameters. Furthermore, if the value of the setting value grasp counter is "4," this means that "setting 4" has been set, so history memory 184 for setting 4 is set as the storage target for history information and the reference target when calculating various parameters. If the value of the setting value grasp counter is "5," this means that "setting 5" has been set, so history memory 185 for setting 5 is set as the storage target for history information and the reference target when calculating various parameters. If the value of the setting value grasp counter is "6," this means that "setting 6" has been set, so history memory 186 for setting 6 is set as the storage target for history information and the reference target when calculating various parameters.

Then, RTC information, which includes date and time information, is read from the RTC 115 (step S2407). Then, a write process to the history memory 117 is executed (step S2408). In this write process, the history memory 181-186 designated in step S2406 as the storage target for history information is selected from the history memories 181-186 for settings 1-6. Then, by referencing the pointer area 126 in the designated history memory 181-186, the pointer information in the history area 124 currently being written is identified. The RTC information read in step S2407 is written to the history information storage area 125 in the history area 124 corresponding to the pointer information being written. Furthermore, information identifying the setting value is written to the history information storage area 125 corresponding to the pointer information being written. This results in a combination of information indicating that the setting status of the pachinko machine 10 has been newly set and the RTC information corresponding to the date and time when the setting was made being stored as history information.

Then, the target pointer is updated (step S2409). In this update process, the history memory 181-186 set as the target for storing history information in step S2406 is selected from the history memories 181-186 for settings 1-6, and the numerical information stored in the pointer area 126 of that history memory 181-186 is read and incremented by 1. A determination is made as to whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If the maximum value is not exceeded, the pointer information after the increment of 1 is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value is exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

With the above configuration, the history memory 117 is provided with history memories 181-186 for Settings 1-6, corresponding to "Setting 1"-"Setting 6," respectively. This makes it possible to store game history corresponding to each of the pachinko machine 10's setting states, "Setting 1"-"Setting 6." In this case, when a new setting is made to the pachinko machine 10, the history memories 181-186 corresponding to the newly set setting value are used to store the history information. This makes it possible to store history information separately for each setting value without erasing the history information when a new setting is made to the pachinko machine 10. Furthermore, because various parameters are calculated using history information corresponding to the currently set setting state of the pachinko machine 10, it is possible to appropriately derive various parameters corresponding to each setting value.

Note that the history memory 117 is not limited to a configuration in which six memories, 181-186, for settings 1-6, are provided. A single memory may have an area corresponding to the history memory 181 for setting 1, an area corresponding to the history memory 182 for setting 2, an area corresponding to the history memory 183 for setting 3, an area corresponding to the history memory 184 for setting 4, an area corresponding to the history memory 185 for setting 5, and an area corresponding to the history memory 186 for setting 6.

Eighth Embodiment
In this embodiment, the configuration of the history memory 117 is different from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 44 is an explanatory diagram illustrating the configuration of the history memory 117 in this embodiment.

The history memory 117 includes a first history memory 191 and a second history memory 192. Each of the first history memory 191 and the second history memory 192 is provided with a combination of the history area 124 and pointer area 126 of the history memory 117 in the first embodiment. In this case, if a new setting is made to the setting state of the pachinko machine 10 while history information is being stored using one of the first history memory 191 and the second history memory 192, the history information in one of the history memories 191 and 192 can be retained without being erased until a predetermined number of pieces of history information is stored in the other history memory 191 and 192. Furthermore, new history information can be stored in both history memories 191 and 192 until a predetermined number of pieces of history information is stored in the other history memory 191 and 192.

Next, the setting update recognition process in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 45.

When the setting value update signal input to the 15th buffer 122o of the input port 121 switches from a LOW level to a HIGH level (step S2501: YES), the value of the setting value grasp counter provided in the management RAM 114 is set to "1" (step S2502). The setting value grasp counter is a counter used by the management CPU 112 to identify the setting value of the pachinko machine 10; for example, a setting value grasp counter value of "1" indicates "setting 1," and a setting value grasp counter value of "6" indicates "setting 6."

Then, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HIGH level again (step S2503). If a positive determination is made in step S2503, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S2504). This causes the setting value of the pachinko machine 10 identified by the management CPU 112 to increase by one level.

If a negative determination is made in step S2503, or if the processing of step S2504 is executed, it is determined whether a set value identification end command has been received from the primary CPU 63 based on the input status of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S2505). If a negative determination is made in step S2505, processing returns to step S2503.

If a positive determination is made in step S2505, the setting change occurrence flag provided in the calculation result memory 131 is set to "1" (step S2506). The setting change occurrence flag is a flag used by the management CPU 112 to determine whether, after a new setting has been made to the setting state of the pachinko machine 10, not only the first history memory 191 or the second history memory 192, which had previously been set as the history information storage target, but also the other history memory 191, 192, is now set as the history information storage target. Furthermore, because the setting change occurrence flag is provided in the calculation result memory 131, which does not require an external power supply to retain its memory, the value stored in the setting change occurrence flag is retained even if the supply of operating power to the management IC 66 is stopped.

Then, RTC information, which is date and time information, is read from the RTC 115 (step S2507). Then, a write process to each history memory 191, 192 is executed (step S2508). In this write process, the pointer information in the history area 124 currently being written to is identified by referencing the pointer area 126 of the first history memory 191. The RTC information read in step S2507 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. Additionally, both information identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 corresponding to the pointer information being written to. As a result, a combination of information indicating that the setting status of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information in the first history memory 191. Furthermore, during this write process, the pointer information in the history area 124 that is currently the target of writing is identified by referencing the pointer area 126 of the second history memory 192, and the RTC information read in step S2507 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is the target of writing. Additionally, both information identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 that corresponds to the pointer information that is the target of writing. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information in the second history memory 192.

Then, an update process for each target pointer is executed (step S2509). In this update process, first, the numerical information stored in the pointer area 126 of the first history memory 191 is read and incremented by 1. A determination is made as to whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If the maximum value is not exceeded, the pointer information after the increment of 1 is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value is exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information. Also, in this update process, the numerical information stored in the pointer area 126 of the second history memory 192 is read and incremented by 1. A determination is made as to whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If the maximum value is not exceeded, the pointer information after the increment of 1 is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value is exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

Next, the history setting process in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 46.

If the setting change occurrence flag for the calculation result memory 131 is not set to "1" (step S2601: NO), this means that history information should only be stored in the target memory, either the first history memory 191 or the second history memory 192. In this case, the current target memory, either the first history memory 191 or the second history memory 192, is identified (step S2602). The calculation result memory 131 is provided with a target memory flag; if the target memory flag's value is "0," the first history memory 191 is the target memory; if the target memory flag's value is "1," the second history memory 192 is the target memory. Note that the target memory flag is provided in the calculation result memory 131, which does not require external power supply to retain its data. Therefore, the value of the target memory flag is retained even if the supply of operating power to the management IC 66 is stopped.

Then, a history setting execution process is executed for the history memory 191, 192 to be stored (step S2603). Specifically, steps S1101 to S1112 of the history setting process (Figure 26) in the first embodiment are executed for one of the history memories 191, 192 to be stored. As a result, history information is stored in one of the history memories 191, 192 to be stored.

On the other hand, if the setting change occurrence flag in the calculation result memory 131 is set to "1" (step S2601: YES), this means that history information should be stored not only in the first history memory 191 or the second history memory 192, whichever is currently being used for storage, but also in the other. In this case, history setting execution processing is executed for both history memories 191, 192 (step S2604). Specifically, steps S1101 to S1112 of the history setting processing in the first embodiment (Figure 26) are first executed for the first history memory 191. This causes history information to be stored in the first history memory 191. Then, steps S1101 to S1112 of the history setting processing in the first embodiment (Figure 26) are executed for the second history memory 192. This causes history information to be stored in the second history memory 192.

When the processing of step S2603 is executed or when the processing of step S2604 is executed, it is determined whether the setting change occurrence flag in the calculation result memory 131 is set to "1" (step S2605). If a positive determination is made in step S2605, it is determined whether a predetermined number or more of ball discharge history records exist in the non-storage target history memories 191, 192 (step S2606). Specifically, when the storage target flag in the calculation result memory 131 has a value of "0", the first history memory 191 is the storage target, so it is determined whether a predetermined number (specifically, "1000") or more of history information indicating that game balls have been discharged from the game area PA is stored in the second history memory 192. Furthermore, when the value of the storage target flag in the calculation result memory 131 is "1", the second history memory 192 is the storage target, and therefore a determination is made as to whether or not a predetermined number (specifically, "1000") or more of history information indicating that game balls have been ejected from the game area PA is stored in the first history memory 191. Note that, instead of determining whether or not a predetermined number (specifically, "1000") or more of history information indicating that game balls have been ejected from the game area PA is stored, a configuration may be adopted in which a determination is made as to whether or not a predetermined number (specifically, "100") or more of history information indicating that a game round has been played is stored.

If a positive judgment is made in step S2606, a process for changing the storage target is executed (step S2607). In the process for changing the storage target, the value of the storage target flag in the calculation result memory 131 is set to a value between two values that is different from the current value, thereby changing the storage target between the first history memory 191 and the second history memory 192. Specifically, if the value of the storage target flag is "0," the storage target is changed from the first history memory 191 to the second history memory 192 by setting the storage target flag to "1." Furthermore, if the value of the storage target flag is "1," the storage target is changed from the second history memory 192 to the first history memory 191 by clearing the storage target flag to "0." As a result, the history memories 191 and 192, which store only the history information from games played after the new setting of the pachinko machine 10 is made, are set as the storage targets. Various parameters are then calculated using the history information in the newly stored history memories 191, 192, making it possible to derive various parameters based on games played after the new settings for the pachinko machine 10 have been made.

Then, a clearing process is performed on either the first history memory 191 or the second history memory 192, whichever had been the storage target up until that point (step S2608). Specifically, if the storage target flag value is "0", the second history memory 192 is cleared to "0", and if the storage target flag value is "1", the first history memory 191 is cleared to "0". Then, the setting change occurrence flag in the calculation result memory 131 is cleared to "0" (step S2609).

Next, the display output processing in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in Figure 47.

If it is the calculation timing (step S2701: YES), the first history memory 191 or the second history memory 192 is identified as the storage target (step S2702). Specifically, if the storage target flag of the calculation result memory 131 is "0," the first history memory 191 is identified as the storage target; if the storage target flag is "1," the second history memory 192 is identified as the storage target. Subsequently, steps S1402 to S1412 of the display output process (FIG. 30) in the first embodiment are executed using the history information stored in the history memories 191 and 192 identified in step S2702 to calculate various parameters (parameters 1 to 8, parameters 11 to 18, parameters 21 to 26, parameters 31, and parameters 41 to 42), and the calculated parameters are stored in the calculation result memory 131 (step S2703). In this case, even if the setting change occurrence flag in the calculation result memory 131 is set to "1" and history information is stored in both the first history memory 191 and the second history memory 192, various parameters are calculated using one of the history memories 191, 192 that is the storage target.

If a negative determination is made in step S2701, or if the processing of step S2703 is executed, display processing is executed (step S2704). The processing content of the display processing is the same as the display processing in the first embodiment described above (Figure 31).

According to the above configuration, the history memory 117 is provided with a first history memory 191 and a second history memory 192. When a new setting is made to the pachinko machine 10, the history memories 191, 192 that had been the storage targets remain the storage targets, while history information is also stored in the history memories 191, 192 that are not the storage targets. When a predetermined number or more of history information corresponding to game balls being ejected from the play area PA is stored in the history memories 191, 192 that are not the storage targets, the history memories 191, 192 that are not the storage targets remain the storage targets, and the history memories 191, 192 that were the storage targets are cleared to "0." As a result, when a new setting is made to the pachinko machine 10, various parameters can be calculated using only the history information of games played with the newly set settings.

On the other hand, with the above configuration, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time to prevent the appropriate calculation of various parameters, the history memories 191, 192 to be stored are maintained without change. This makes it possible to properly derive the management results of the game history up to that point, even if the settings of the pachinko machine 10 are repeatedly changed in a short period of time.

Note that the history memory 117 is not limited to a configuration in which two memories, a first history memory 191 and a second history memory 192, are provided, and a configuration in which a first history area corresponding to the first history memory 191 and a second history area corresponding to the second history memory 192 are set in one memory may also be used.

Alternatively, a configuration may be provided in which only one history memory 117 is provided. In this case, if the total number of game balls discharged from the game area PA after a new setting of the pachinko machine 10 is made becomes equal to or exceeds a predetermined number, history information before the time when the new setting of the pachinko machine 10 is made is erased, and history information after the time when the new setting is made is stored and retained without being erased. This makes it possible to erase history information before the time when a predetermined number of history information items have been accumulated since a new setting of the pachinko machine 10 is made. Furthermore, by storing history information corresponding to a new setting of the pachinko machine 10 in the history memory 117 when the new setting is made, it becomes possible to distinguish between history information before and after the new setting in the history memory 117.

Furthermore, the timing for erasing the history information is not limited to when the total number of game balls discharged from the game area PA reaches a predetermined number or more after the setting state of the pachinko machine 10 is newly set, but may also be when the number of games played since the setting state of the pachinko machine 10 is newly set reaches a predetermined number or more.

Furthermore, even if a new setting is made to the setting state of the pachinko machine 10, if the setting values have not changed before and after the setting, the history memories 191, 192 to be stored as described above will not be changed and the history information will not be erased. However, if a new setting is made to the setting state of the pachinko machine 10 but the setting values have changed before and after the setting, the history memories 191, 192 to be stored as described above will be changed and the history information will be erased.

Ninth Embodiment
In this embodiment, the type of buffers for which the type of input signal is determined at the design stage of the management IC 66 among the first to sixteenth buffers 122a to 122p of the input port 121 in the management I/F 111 differs from that of the first embodiment. Also, the processing configuration executed by the main CPU 63 to cause the management CPU 112 to identify the type of input signal differs from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that a description of the same configuration as the first embodiment will generally be omitted.

Figure 48 is an explanatory diagram illustrating the configuration of the input port 121 of the management side I/F 111 in this embodiment.

The first to seventh buffers 122a to 122g and the sixteenth buffer 122p receive the same types of signals as in the first embodiment above. In detail, a first signal corresponding to the detection result of the first winning opening detection sensor 42a is input to the first buffer 122a, a second signal corresponding to the detection result of the second winning opening detection sensor 43a is input to the second buffer 122b, a third signal corresponding to the detection result of the third winning opening detection sensor 44a is input to the third buffer 122c, a fourth signal corresponding to the detection result of the special electric current detection sensor 45a is input to the fourth buffer 122d, a fifth signal corresponding to the detection result of the first operating opening detection sensor 46a is input to the fifth buffer 122e, a sixth signal corresponding to the detection result of the second operating opening detection sensor 47a is input to the sixth buffer 122f, a seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g, and an output instruction signal is input to the sixteenth buffer 122p.

On the other hand, in the first embodiment described above, a signal corresponding to the opening/closing execution mode is input as the eighth signal to the eighth buffer 122h, a signal corresponding to the high frequency support mode is input as the ninth signal to the ninth buffer 122i, a signal corresponding to the front door frame 14 is input as the tenth signal to the tenth buffer 122j, a signal corresponding to the start of a game round is input as the eleventh signal to the eleventh buffer 122k, and a setting value update signal is input to the fifteenth buffer 122o, but in this embodiment, the buffers to which these signals are input are different. Specifically, a signal corresponding to the start of a game round is input to the 11th buffer 122k as a game round signal, a setting value update signal is input to the 12th buffer 122l, a signal corresponding to the opening/closing execution mode is input to the 13th buffer 122m as an opening/closing execution mode in progress signal, a signal corresponding to the high frequency support mode is input to the 14th buffer 122n as a high frequency support mode in progress signal, and a signal corresponding to the front door frame 14 is input to the 15th buffer 122o as a door open signal.

The input of a game signal to the 11th buffer 122k, the input of a setting value update signal to the 12th buffer 122l, the input of an open/close execution mode signal to the 13th buffer 122m, the input of a high-frequency support mode signal to the 14th buffer 122n, the input of a door open signal to the 15th buffer 122o, and the input of an output instruction signal to the 16th buffer 122p were determined during the design stage of the management IC 66, and the management CPU 112 can determine that each of the above signals corresponding to the 11th to 16th buffers 122k to 122p will be input without receiving instructions from the main CPU 63. On the other hand, the types of signals input to the 1st to 10th buffers 122a to 122j were not determined during the design stage of the management IC 66, and the types of these signals are determined by the management CPU 112 upon receiving instructions from the main CPU 63. As with the first embodiment, the process for identifying the type of signal is executed when the supply of operating power to the main CPU 63 and management CPU 112 begins.

Figure 49 is a flowchart showing the recognition processing of this embodiment executed by the main CPU 63. Note that the recognition processing is executed in step S111 of the main processing (Figure 9), as in the first embodiment.

First, the recognition output counter in the main RAM 65 is set to "10," which represents the number of buffers 122a-122j to be recognized for signal type recognition (step S2801). Then, the output process for the identification start signal is executed (step S2802). In this output process, the output states of the first signal input to the first buffer 122a, the open/close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to a HIGH level, thereby starting the output of the identification start signal. The period for which these signals are maintained at a HIGH level is set long enough for the management CPU 112 to recognize the output states of these signals.

Then, the output count information corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64, and the read output count information is set in the output count counter provided in the main RAM 65 (step S2803). The output count counter is a counter used by the main CPU 63 to determine the number of times the type identification signal has been output.

In this embodiment, when the management CPU 112 is made to recognize the type of signal input to the first buffer 122a through the tenth buffer 122j, a type identification signal is output the same number of times as the number of prize balls set for the ball entry section corresponding to that signal type. The management CPU 112 stores information corresponding to the number of times the type identification signal has been received for each of the first buffer 122a through the tenth buffer 122j in the first through tenth correspondence areas 123a through 123j of the correspondence memory 116. In other words, the type of signal input to the first buffer 122a through the tenth buffer 122j is understood to be the number of prize balls set for the ball entry section corresponding to that signal type.

In step S2803, if the value of the recognition output counter is "10," "9," or "8," the output count counter is set to "10," which corresponds to the number of prize balls in the general winning port 31. If the value of the recognition output counter is "7," the output count counter is set to "15," which corresponds to the number of prize balls in the special winning device 32. If the value of the recognition output counter is "6," the output count counter is set to "1," which corresponds to the number of prize balls in the first operating port 33. If the value of the recognition output counter is "5," the output count counter is set to "1," which corresponds to the number of prize balls in the second operating port 34. If the value of the recognition output counter is "4," although it corresponds to the outlet 24a, the payout of the game balls will not be executed even if a game ball enters the outlet 24a, so the output count counter is set to "0." Also, if the value of the recognition output counter is between "3" and "1," there is no corresponding ball entry area and it is blank, so the output count counter is set to "0."

Then, the output process of the start trigger signal is executed (step S2804). In this output process, the output state of the first signal input to the first buffer 122a is set to a HIGH level, thereby starting the output of the start trigger signal. The period during which the first signal is maintained at a HIGH level is set to a period sufficient for the management CPU 112 to recognize the output state of the first signal.

Then, on the condition that the value of the output count counter in the main RAM 65 is not "0" (step S2805: YES), that is, on the condition that a value of 1 or greater was set in the output count counter in step S2803, the process proceeds to step S2806. In step S2806, output processing of a type identification signal is executed. In this output processing, the output state of the second signal input to the second buffer 122b is set to a HI level, thereby starting output of the type identification signal. The period for which the second signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the second signal.

Then, the value of the output count counter in the main RAM 65 is decremented by 1 (step S2807), and it is determined whether the value of the output count counter after decrementing by 1 is "0" (step S2808). If the value of the output count counter is 1 or greater (step S2808: NO), the process returns to step S2806.

If a positive judgment is made in step S2805 or if a positive judgment is made in step S2808, output processing of the termination trigger signal is executed (step S2809). In this output processing, the output state of the third signal input to the third buffer 122c is set to a HIGH level, thereby starting output of the termination trigger signal. The period for which the third signal is maintained at a HIGH level is set to a period sufficient for the management CPU 112 to recognize the output state of the third signal.

Then, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S2810), and it is determined whether the value of the recognition output counter after decrement is "0" (step S2811). If the value of the recognition output counter is 1 or greater (step S2811: NO), the process returns to step S2803, and processing is performed to recognize the type of signal corresponding to the value of the recognition output counter after decrement.

On the other hand, if the value of the recognition output counter is "0" (step S2811: YES), an identification end signal output process is executed (step S2812). In this output process, the output states of the third signal input to the third buffer 122c, the open/close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to a HI level, thereby starting output of the identification end signal. The period for which these signals are maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

Next, the management process executed by the management CPU 112 in this embodiment will be described with reference to the flowchart in Figure 50. The management process begins when the supply of operating power to the management CPU 112 begins, as in the first embodiment described above.

First, it is determined whether reception of the identification start signal from the main CPU 63 has ended (step S2901). If the identification start signal has not been received, the setting update recognition process is executed in step S2902, and then the process of step S2901 is executed again. The processing content of the setting update recognition process is the same as in the first embodiment described above.

When reception of the identification start signal from the main CPU 63 has ended (step S2901: YES), the value of the setting target counter in the management RAM 114 is cleared to "0" (step S2903). Then, on the condition that a start trigger signal has been received from the main CPU 63 (step S2904: YES), the process proceeds to step S2905. In step S2905, it is determined whether a type identification signal has been received from the main CPU 63. If a type identification signal has been received (step S2905: YES), the value of the reception count counter provided in the management RAM 114 is incremented by 1 (step S2906). The reception count counter is a counter used by the management CPU 112 to determine the number of times a type identification signal has been received from the main CPU 63. Note that the value of the reception count counter is cleared to "0" if a positive determination is made in step S2904.

If a negative judgment is made in step S2905, or if the processing of step S2906 is executed, it is determined whether a termination trigger signal has been received from the main CPU 63 (step S2907). If a termination trigger signal has not been received (step S2907: NO), the process returns to step S2905. If a termination trigger signal has been received (step S2907: YES), the correspondence setting process is executed (step S2908). In the correspondence setting process, the value set in the reception count counter is stored in the correspondence area corresponding to the current value of the setting target counter in the management RAM 114, among the first to tenth correspondence areas 123a to 123j of the correspondence memory 116. In this case, the first correspondence area 123a, the second correspondence area 123b, and the third correspondence area 123c are set to "10," which corresponds to the number of prize balls in the general winning port 31; the fourth correspondence area 123d is set to "15," which corresponds to the number of prize balls in the special winning device 32; the fifth correspondence area 123e is set to "1," which corresponds to the number of prize balls in the first operating port 33; and the sixth correspondence area 123f is set to "1," which corresponds to the number of prize balls in the second operating port 34. Additionally, the seventh to twelfth correspondence areas 123g to 123l are set to "0." Then, the value of the setting target counter in the management RAM 114 is incremented by 1 (step S2909).

If a negative judgment is made in step S2904, or if the processing of step S2909 is executed, it is determined whether reception of the identification end signal from the main CPU 63 has ended (step S2910). If reception of the identification end signal has not ended (step S2910: NO), the process returns to step S2904, and, on the condition that a start trigger signal is received from the main CPU 63 (step S2904: YES), processing from step S2905 onwards is executed. If reception of the identification end signal from the main CPU 63 has ended (step S2910: YES), the history setting processing of step S2911, the display output processing of step S2912, and the external output processing of step S2913 are repeatedly executed.

Figure 51 is a time chart showing how information on the correspondence between the first to tenth buffers 122a to 122j and the types of signals input to these buffers 122a to 122j is stored in the correspondence memory 116. FIG. 51(a) shows the period when the output state of the first signal is HIGH, FIG. 51(b) shows the period when the output state of the second signal is HIGH, FIG. 51(c) shows the period when the output state of the third signal is HIGH, FIG. 51(d) shows the period when the output state of the open/close execution mode signal is HIGH, FIG. 51(e) shows the period when the output state of the high frequency support mode signal is HIGH, FIG. 51(f) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first to tenth buffers 122a to 122j and the types of signals input to these buffers 122a to 122j, FIG. 51(g) shows the timing when the value of the reception count counter in the management RAM 114 is incremented by 1, and FIG. 51(h) shows the timing when the correspondence setting processing (step S2908) is performed by the management CPU 112.

When the supply of operating power to the main CPU 63 and the control CPU 112 begins, at timing t1, the output states of the first signal, the switching execution mode signal, and the high-frequency support mode signal are changed from LOW to HIGH, as shown in Figures 51(a), 51(d), and 51(e). This causes output of an identification start signal from the main CPU 63 to the control CPU 112 to begin. Thereafter, at timing t2, the output states of the first signal, the switching execution mode signal, and the high-frequency support mode signal are changed from HI to LOW. This causes output of the identification start signal from the main CPU 63 to the control CPU 112 to stop. At timing t2, the control CPU 112 makes a positive determination in step S2901 of the control process (Figure 50), and enters the identification state as shown in Figure 51(f).

After that, the output state of the first signal is maintained at a HI level from time t3 to time t4, as shown in Figure 51(a). This results in a state in which a start trigger signal is output to the management CPU 112. Then, the output state of the second signal is maintained at a HI level from time t5 to time t7, as shown in Figure 51(b). This results in a state in which a type identification signal has been output once to the management CPU 112. In this case, at time t6, the value of the reception count counter in the management RAM 114 is incremented by 1, as shown in Figure 51(g).

After that, the output state of the third signal is maintained at HI level from time t8 to time t10, as shown in Figure 51 (c). This causes a termination trigger signal to be output to the management CPU 112. In this case, at time t9, the management CPU 112 executes the correspondence setting process, as shown in Figure 51 (h). Because the value of the reception count counter is "1" when this correspondence setting process is executed, the correspondence information of "1" is stored in the correspondence areas 123a to 123j of the correspondence memory 116 that are currently being set.

After that, the output state of the first signal is maintained at a HIGH level from timing t11 to timing t12, as shown in Figure 51(a). This results in a state in which a start trigger signal is output to the management CPU 112. Then, the output state of the second signal is maintained at a HIGH level from timing t13 to timing t15, timing t16 to timing t18, timing t19 to timing t21, and timing t22 to timing t24, as shown in Figure 51(b). This results in a state in which a type identification signal has been output once to the management CPU 112. In this case, the value of the reception count counter in the management RAM 114 is incremented by 1 at timings t14, t17, t20, and t23, as shown in Figure 51(g).

After that, the output state of the third signal is maintained at HI level from time t25 to time t27, as shown in Figure 51 (c). This causes a termination trigger signal to be output to the management CPU 112. In this case, at time t26, the management CPU 112 executes the correspondence setting process, as shown in Figure 51 (h). Because the value of the reception count counter is "10" when this correspondence setting process is executed, the information "10" is stored as the correspondence information in the correspondence areas 123a to 123j currently being set in the correspondence memory 116.

After that, at timing t28, as shown in Figures 51(c), 51(d), and 51(e), the output states of the third signal, the opening/closing execution mode signal, and the high-frequency support mode signal are changed from LOW to HI. This causes output of an identification end signal from the main CPU 63 to the control CPU 112 to begin. After that, at timing t29, the output states of the third signal, the opening/closing execution mode signal, and the high-frequency support mode signal are changed from HI to LOW. This causes output of the identification end signal from the main CPU 63 to the control CPU 112 to stop. At timing t29, the control CPU 112 makes a positive determination in step S2910 of the control process (Figure 50), and the identification state is released as shown in Figure 51(f).

In this embodiment, since information on the number of prize balls is stored as correspondence information, the history information stored in the history memory 117 also includes, as correspondence information, information on the number of prize balls corresponding to the entry point that triggered the storage of that history information. In this configuration, if there are multiple entry points with the same number of prize balls, these entry points cannot be distinguished in the history information. Specifically, since the first actuation port 33 and the second actuation port 34 both have a single prize ball, the first actuation port 33 and the second actuation port 34 cannot be distinguished in the history information. In such circumstances, the number of prize balls for the first actuation port 33 and the second actuation port 34 may be made different. This makes it possible to distinguish between the first actuation port 33 and the second actuation port 34 in the history information, even in a configuration in which history information is stored as in this embodiment.

According to the present embodiment described above, the management CPU 112 can identify the signal paths corresponding to not only the setting value update signal and output instruction signal, but also information corresponding to whether a game has started, whether the opening/closing execution mode is active, whether the high-frequency support mode is active, and whether the front door frame 14 is open, without receiving correspondence information from the main CPU 63. In this case, only the information corresponding to the detection results of each ball entry detection sensor 42a-48a is the information that the main CPU 63 needs to have the management CPU 112 recognize the correspondence between each piece of information and each signal path 118a-118j. When the management CPU 112 is made to recognize the correspondence information, a number of pulse signals equal to the number of winning balls corresponding to each ball entry detection sensor 42a-48a is output from the main CPU 63 to the management CPU 112 using the second signal. This simplifies the configuration for transmitting correspondence information.

Tenth Embodiment
In this embodiment, the configuration for providing the information on each goal score result to the management IC 66 differs from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will be omitted.

Figure 52 is an explanatory diagram illustrating the configuration of the signal path for inputting the detection results of each ball entry detection sensor 42a-48a to the main CPU 63 and management IC 66.

The detection result of the first winning opening detection sensor 42a is input to the main CPU 63 via the first signal path SL11. The detection result of the second winning opening detection sensor 43a is input to the main CPU 63 via the second signal path SL12. The detection result of the third winning opening detection sensor 44a is input to the main CPU 63 via the third signal path SL13. The detection result of the special current detection sensor 45a is input to the main CPU 63 via the fourth signal path SL14. The detection result of the first operating opening detection sensor 46a is input to the main CPU 63 via the fifth signal path SL15. The detection result of the second operating opening detection sensor 47a is input to the main CPU 63 via the sixth signal path SL16. The detection result of the outlet detection sensor 48a is input to the main CPU 63 via the seventh signal path SL17.

A first branch path SL21 is formed by branching off from the first signal path SL11 at a midpoint, and this first branch path SL21 is electrically connected to the management IC 66. A second branch path SL22 is formed by branching off from the second signal path SL12 at a midpoint, and this second branch path SL22 is electrically connected to the management IC 66. A third branch path SL23 is formed by branching off from the third signal path SL13 at a midpoint, and this third branch path SL23 is electrically connected to the management IC 66. A fourth branch path SL24 is formed by branching off from the fourth signal path SL14 at a midpoint, and this fourth branch path SL24 is electrically connected to the management IC 66. A fifth branch path SL25 is formed by branching off from the fifth signal path SL15 at a midpoint, and this fifth branch path SL25 is electrically connected to the management IC 66. In addition, a sixth branch path SL26 is formed by branching off from a midpoint of the sixth signal path SL16, and this sixth branch path SL26 is electrically connected to the management IC 66. In addition, a seventh branch path SL27 is formed by branching off from a midpoint of the seventh signal path SL17, and this seventh branch path SL27 is electrically connected to the management IC 66.

With the above configuration, the detection results of each ball entry detection sensor 42a-48a are input to the management IC 66 without processing by the main CPU 63. This eliminates the need for the main CPU 63 to execute processing to have the management CPU 112 recognize the ball entry results of each of the outlet 24a, general entry port 31, special electric entry device 32, first operating port 33, and second operating port 34, thereby reducing the processing load on the main CPU 63.

In addition, the branch points of the branch paths SL21 to SL27 from the signal paths SL11 to SL17 are located within the MPU 62. This makes it difficult to access these branch points and the branch paths SL21 to SL27 from the outside, preventing fraudulent activity such as inputting abnormal ball-scoring results only to the management IC 66.

Eleventh Embodiment
In this embodiment, the configuration of the display device for displaying the results of game history management differs from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will be basically omitted.

Figure 53 is a front view of the main control unit 60 in this embodiment.

In the first embodiment described above, the main control device 60 was provided with a first alert display device 69a, a second alert display device 69b, and a third alert display device 69c, but in this embodiment, a first alert display device 201, a second alert display device 202, a third alert display device 203, and a fourth alert display device 204 are provided. These first to fourth alert display devices 201 to 204 are arranged side by side on the element mounting surface of the main control board 61.

The first through fourth alarm display devices 201-204 are all segment displays with an arrangement of seven LED display segments, but are not limited to this and may be a single light-emitting element of a multi-color type, a liquid crystal display device, or an organic EL display. The first through fourth alarm display devices 201-204 are all installed so that their display surfaces face the direction of the element mounting surface of the main control board 61, and are covered by the opposing wall portion 60b of the board box 60a. In this case, because the board box 60a is formed to be transparent, the display surfaces of the first through fourth alarm display devices 201-204 housed within the board box 60a can be seen from outside the board box 60a. Furthermore, the main control device 60 is mounted on the back surface of the resin base 21 so that the opposing wall portion 60b, which faces the element mounting surface of the main control board 61 in the board box 60a, faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the rear surface of the resin base 21 is exposed toward the front of the pachinko machine 10, the display surfaces of the first to fourth alarm display devices 201 to 204 can be seen through the opposing wall portion 60b.

The display surface of the first notification display device 201 displays alphabets such as "A," "E," "H," "L," and "O." Meanwhile, the second notification display device 202, third notification display device 203, and fourth notification display device 204 display numbers ranging from "0" to "9." The first through fourth notification display devices 201 through 204 are used to notify the results of game history management. In this case, the first notification display device 201 and second notification display device 202 display information corresponding to the type of game history management result being notified (parameters 1 through 8, parameters 11 through 18, parameters 21 through 26, parameters 31, and parameters 41 through 42 in the first embodiment), while the third notification display device 203 and fourth notification display device 204 display information corresponding to the content of the game history management result for the type being notified.

More specifically, in the first embodiment, the types of game history management results include parameters 1 through 8, parameters 11 through 18, parameters 21 through 26, parameters 31, and parameters 41 through 42. The first notification display device 201 displays a display corresponding to the type of parameter group that is the subject of notification. Specifically, if any of parameters 1 through 8 is the subject of notification, the first notification display device 201 displays "A." If any of parameters 11 through 18 is the subject of notification, the first notification display device 201 displays "E." If any of parameters 21 through 26 are the subject of notification, the first notification display device 201 displays "H." If any of parameters 31 is the subject of notification, the first notification display device 201 displays "L." If parameters 41 through 42 are the subject of notification, the first notification display device 201 displays "O."

The second notification display device 202 displays the order of the game history management results for the parameter group being notified, in an order that corresponds to the type of game history management result being notified. Taking the parameter group of parameters 1 to 8 as an example, if the first parameter is the target of notification, "1" is displayed on the second notification display device 202, if the second parameter is the target of notification, "2" is displayed on the second notification display device 202, if the third parameter is the target of notification, "3" is displayed on the second notification display device 202, if the fourth parameter is the target of notification, "4" is displayed on the second notification display device 202, if the fifth parameter is the target of notification, "5" is displayed on the second notification display device 202, if the sixth parameter is the target of notification, "6" is displayed on the second notification display device 202, if the seventh parameter is the target of notification, "7" is displayed on the second notification display device 202, and if the eighth parameter is the target of notification, "8" is displayed on the second notification display device 202. Taking the parameter group of parameters 21 to 26 as an example, if parameter 21 is the subject of notification, then "1" is displayed on the second alert display device 202; if parameter 22 is the subject of notification, then "2" is displayed on the second alert display device 202; if parameter 23 is the subject of notification, then "3" is displayed on the second alert display device 202; if parameter 24 is the subject of notification, then "4" is displayed on the second alert display device 202; if parameter 25 is the subject of notification, then "5" is displayed on the second alert display device 202; and if parameter 26 is the subject of notification, then "6" is displayed on the second alert display device 202.

Regarding the display contents of the third alarm display device 203 and the fourth alarm display device 204 in detail, the parameter to be notified is multiplied by 100, and the number corresponding to the tens digit of the value is displayed on the third alarm display device 203, while the number corresponding to the ones digit is displayed on the fourth alarm display device 204.

In the first to fourth alarm display devices 201-204, the displays corresponding to the calculation results of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters are switched sequentially in a predetermined order. After the calculation result of the forty-second parameter, which is the last parameter to be displayed, is displayed, the calculation result of the first parameter, which is the first parameter to be displayed, is displayed. In this case, the calculation result of one parameter is continuously displayed for two seconds. In contrast, the calculation cycle of the various parameters in the management CPU 112 is 51 seconds, and the number of various parameters is 25. Therefore, each parameter calculated by the management CPU 112 becomes the target of notification on the first to fourth alarm display devices 201-202 at least once.

The first to fourth notification display devices 201-204 not only notify the results of game history management, as in the first embodiment described above, but also display values corresponding to the current setting values when the setting state of the pachinko machine 10 is in a changeable state, in which it is possible to change the setting state of the pachinko machine 10. Specifically, when in this changeable state, the first to third notification display devices 201-203 are turned off, while the fourth notification display device 204, which is located at the right end of the first to fourth notification display devices 204 arranged horizontally, displays a value corresponding to the current setting value. In other words, if "Setting 1" is selected in the changeable state, "1" is displayed on the fourth alert display device 204; if "Setting 2" is selected in the changeable state, "2" is displayed on the fourth alert display device 204; if "Setting 3" is selected in the changeable state, "3" is displayed on the fourth alert display device 204; if "Setting 4" is selected in the changeable state, "4" is displayed on the fourth alert display device 204; if "Setting 5" is selected in the changeable state, "5" is displayed on the fourth alert display device 204; and if "Setting 6" is selected in the changeable state, "6" is displayed on the fourth alert display device 204.

Next, we will explain the electrical configuration for displaying various information on the first to fourth alarm display devices 201 to 204 based on the control of the MPU 62. Figure 54 is a block diagram illustrating the electrical configuration for displaying various information on the first to fourth alarm display devices 201 to 204 based on the control of the MPU 62.

As already explained, the main control board 61 is provided with an MPU 62 and first to fourth notification display devices 201 to 204. The main control board 61 also is provided with a first display IC 205, a second display IC 206, a third display IC 207, and a fourth display IC 208.

The first display IC 205 is provided corresponding to the first alarm display device 201 and is electrically connected to the MPU 62 via signal path SL31 and to the first alarm display device 201 via signal path SL32. The first display IC 205 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the first alarm display device 201, i.e., controls the illumination of each display segment, in accordance with the display data stored in the storage buffer. When operating power is supplied, the first display IC 205 can store and retain the display data stored in the storage buffer, and causes the first alarm display device 201 to continuously display the display content corresponding to the stored display data. When the display data is changed by the MPU 62, the display of the first alarm display device 201 is changed to the display content corresponding to the changed display data. Furthermore, after the supply of operating power to the first display IC 205 has started and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the first alarm display device 201 will be in a non-display state, i.e., off state.

However, this configuration is not limited to this, and the first display IC 205 may be configured to store and retain display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the first display IC 205. In this case, when the supply of operating power to the pachinko machine 10 begins, the display that was being displayed on the first alert display device 201 immediately before the supply of operating power to the pachinko machine 10 was stopped will begin on the first alert display device 201.

The second display IC 206 is provided corresponding to the second alert display device 202 and is electrically connected to the MPU 62 via signal path SL33 and to the second alert display device 202 via signal path SL34. The second display IC 206 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the second alert display device 202, i.e., controls the illumination of each display segment, in accordance with the display data stored in the storage buffer. When operating power is supplied, the second display IC 206 can store and retain the display data stored in the storage buffer, and causes the second alert display device 202 to continuously display the display content corresponding to the stored display data. When the display data is changed by the MPU 62, the display of the second alert display device 202 is changed to the display content corresponding to the changed display data. Furthermore, after the supply of operating power to the second display IC 206 has begun and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the second alarm display device 202 will be in a non-display state, i.e., off state.

However, this configuration is not limited to this, and the second display IC 206 may be configured to store and retain display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the second display IC 206. In this case, when the supply of operating power to the pachinko machine 10 begins, the display that was being displayed on the second alert display device 202 immediately before the supply of operating power to the pachinko machine 10 was stopped will begin on the second alert display device 202.

The third display IC 207 is provided corresponding to the third alert display device 203 and is electrically connected to the MPU 62 via signal path SL35 and to the third alert display device 203 via signal path SL36. The third display IC 207 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the third alert display device 203, i.e., controls the illumination of each display segment, in accordance with the display data stored in the storage buffer. When operating power is supplied, the third display IC 207 can store and retain the display data stored in the storage buffer, and causes the third alert display device 203 to continuously display the display content corresponding to the stored display data. When the display data is changed by the MPU 62, the display of the third alert display device 203 is changed to the display content corresponding to the changed display data. Furthermore, after the supply of operating power to the third display IC 207 has started and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the third alarm display device 203 will be in a non-display state, i.e., off state.

However, this configuration is not limited to this, and the third display IC 207 may be configured to store and retain display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the third display IC 207. In this case, when the supply of operating power to the pachinko machine 10 begins, the display that was being displayed on the third alert display device 203 immediately before the supply of operating power to the pachinko machine 10 was stopped will begin on the third alert display device 203.

The fourth display IC 208 is provided corresponding to the fourth alert display device 204 and is electrically connected to the MPU 62 via signal path SL37 and to the fourth alert display device 204 via signal path SL38. The fourth display IC 208 is provided with a storage buffer for storing display data received from the MPU 62, and controls the display of the fourth alert display device 204, i.e., controls the illumination of each display segment, in accordance with the display data stored in the storage buffer. When operating power is supplied, the fourth display IC 208 can store and retain the display data stored in the storage buffer, and causes the fourth alert display device 204 to continuously display the display content corresponding to the stored display data. When the display data is changed by the MPU 62, the display of the fourth alert display device 204 is changed to the display content corresponding to the changed display data. Furthermore, after the supply of operating power to the fourth display IC 208 has begun and the display data has not yet been set by the MPU 62, the display data will be all "0" data, in which case the fourth alarm display device 204 will be in a non-display state, i.e., off state.

However, this configuration is not limited to this, and the fourth display IC 208 may be configured to store and retain display data even when the supply of operating power to the pachinko machine 10 is stopped by supplying backup power to the fourth display IC 208. In this case, when the supply of operating power to the pachinko machine 10 begins, the display that was being displayed on the fourth alert display device 204 immediately before the supply of operating power to the pachinko machine 10 was stopped will begin on the fourth alert display device 204.

Display data is output to the first through fourth display ICs 205-208 by the MPU 62, but the main CPU 63 and the control CPU 112 configure the display data output, respectively. That is, the main CPU 63 controls the display of the first through fourth alarm display devices 201-204, while the control CPU 112 controls the display of the first through fourth alarm display devices 201-204. In this case, the periods during which the main CPU 63 and the control CPU 112 configure the display data output are adjusted so that the display data output settings are not configured simultaneously. Specifically, after the supply of operating power to the MPU 62 begins, in a changeable state in which the settings of the pachinko machine 10 can be changed, the main CPU 63 configures the display data output, but the control CPU 112 does not configure the display data output. On the other hand, in a state in which the settings are not changeable, the control CPU 112 configures the display data output, but the main CPU 63 does not configure the display data output.

Note that if the display data output settings by the main CPU 63 and the control CPU 112 are performed synchronously, the display data output settings by the main CPU 63 will take priority. However, this is not limited to this, and the display data output settings by the control CPU 112 may also take priority.

Next, the display processing in this embodiment executed by the management CPU 112 will be explained with reference to the flowchart in Figure 55.

First, the value of the update timing counter in the management RAM 114 is decremented by 1 (step S3001). The update timing counter is a counter that the management CPU 112 uses to determine whether it is time to update the display content of the game history management results on the first to fourth notification display devices 201 to 204. Then, by determining whether the value of the update timing counter after decrementing by 1 is "0," it is determined whether it is time to update the display content of the first to fourth notification display devices 201 to 204 (step S3002).

If a positive judgment is made in step S3002, the value of the display target counter in the management RAM 114 is incremented by 1 (step S3003). If the value of the display target counter after incrementing by 1 exceeds the maximum value of "24" (step S3004: YES), the value of the display target counter is cleared to "0" (step S3005). The display target counter is a counter used by the management CPU 112 to identify the type of parameter to be displayed on the first to fourth alarm display devices 201 to 204. There is a one-to-one correspondence between the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters and the possible values of the display target counter, which are "0" to "24." For example, if the value of the display object counter is "0", the first parameter, which is the first display object, will be displayed on the first to fourth alarm display devices 201-204; if the value of the display object counter is "24", the 42nd parameter, which is the last display object, will be displayed on the first to fourth alarm display devices 201-204.

If a negative judgment is made in step S3004, or if the processing of step S3005 is executed, display data corresponding to the type of parameter corresponding to the value of the display target counter is read from the management side ROM 113 (step S3006). Then, a setting process for display data corresponding to the first alarm display device 201 is executed (step S3007), and a setting process for display data corresponding to the second alarm display device 202 is executed (step S3008). For example, if the value of the display target counter is "0" and the first parameter is the display target, display data for displaying "A" on the first alarm display device 201 is output to the first display IC 205, and display data for displaying "1" on the second alarm display device 202 is output to the second display IC 206. Furthermore, for example, if the value of the display target counter is "24" and the 42nd parameter is the display target, display data for displaying "O" on the first alert display device 201 is output to the first display IC 205, and display data for displaying "2" on the second alert display device 202 is output to the second display IC 206.

Then, a parameter corresponding to the value of the counter to be displayed is read from the calculation result memory 131, and the display data corresponding to the tens digit and the ones digit of the result obtained by multiplying the read parameter by 100 are read from the management ROM 113 (step S3009). Then, the display of the third alert display device 203 is controlled so that the digit corresponding to the tens digit of the result is displayed (step S3010), and the display of the fourth alert display device 204 is controlled so that the digit corresponding to the ones digit is displayed (step S3011). For example, if the result of multiplying by 100 is "53," display data for displaying "5" on the third alert display device 203 is output to the third display IC 207, and display data for displaying "3" on the fourth alert display device 204 is output to the fourth display IC 208.

Then, the update timing counter in the management RAM 114 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S3012).

By executing the display processing as described above, the game history management results are displayed on the first to fourth notification display devices 201-204. The game history management results are displayed regardless of whether play is continuing or not, and regardless of whether the gaming machine main body 12 is opened relative to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By executing display control of the first to fourth notification display devices 201-204 in this way regardless of the game situation or the state of the pachinko machine 10, it is possible to simplify the processing configuration for display control of the first to fourth notification display devices 201-204.

Display of the gaming history management results on the first to fourth notification display devices 201-204 begins after the supply of operating power to the management CPU 112 has begun and after an identification end command has been received from the main CPU 63. In this case, the information stored in the calculation result memory 131, like the information stored in the history memory 117, is stored and retained even when the supply of operating power to the pachinko machine 10 is stopped. Therefore, when the supply of operating power to the management CPU 112 begins, the gaming history management results calculated before the supply of operating power to the management CPU 112 was stopped are displayed.

While operating power is being supplied, the first through fourth display ICs 205-208 store and retain the display data output from the MPU 62, and control the display of the corresponding first through fourth notification display devices 201-204 in accordance with that display data. Therefore, after the display of the gaming history management results begins, the first through fourth notification display devices 201-204 never go into an off state (i.e., a non-display state), but remain in an on state (i.e., a display state) corresponding to some kind of display.

Next, the setting value update process in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 56.

First, the first through third alert display devices 201-203 are turned off (step S3101). Specifically, all "0" display data is output to the first through third display ICs 205-207. As a result, all display segments of the first through third alert display devices 201-203 are turned off, and the first through third alert display devices 201-203 are turned off. Note that immediately after the supply of operating power to the pachinko machine 10 begins, all display segments of the first through fourth alert display devices 201-204 are turned off, and the first through fourth alert display devices 201-204 are turned off. Therefore, step S3101 is a process that maintains the first through third alert display devices 201-203 in a turned-off state, and also a process that switches any of the first through third alert display devices 201-203 that are turned on due to some influence to a turned-on state.

Then, the setting value counter in the main RAM 65 is set to "1" (step S3102). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value will become "Setting 1" regardless of the previous setting value.

Then, the fourth display notification device 204 executes a process to start displaying the set value (step S3103). In the process to start displaying the set value, display data for displaying "1" is output to the fourth display IC 208. As a result, the number "1" corresponding to "Setting 1" is displayed on the fourth notification display device 204.

Subsequently, on the condition that the setting key insertion unit 68a has not been turned OFF (step S3104: NO), it is determined whether the update button 68b has been pressed once (step S3105). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from LOW level to HIGH level. If a negative determination is made in step S3105, the process returns to step S3104, where it is determined whether the setting key insertion unit 68a has been turned OFF.

If the update button 68b has been pressed once (step S3105: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S3106). Furthermore, if the value of the setting value counter after incrementing by 1 exceeds "6" (step S3107: YES), the setting value counter is set to "1" (step S3108). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed; if the update button 68b is pressed once when the setting is "6," the setting will return to "1."

If a negative judgment is made in step S3107, or if the processing of step S3108 is executed, a display update process for the setting value on the fourth alert display device 204 is executed (step S3109). In the display update process for the setting value, display data for displaying a number corresponding to the value of the setting value counter in the main RAM 65 is output to the fourth display IC 208. As a result, a number corresponding to the current setting value is displayed on the fourth alert display device 204. By checking the fourth alert display device 204, the manager of the gaming hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b.

After executing step S3109, the process returns to step S3104, where it is determined whether the setting key insertion unit 68a has been turned OFF. If it has not been turned OFF (step S3104: NO), the process from step S3105 onwards is executed again. If it has been turned OFF (step S3104: YES), the process of starting display of the management results on the first to fourth alarm display devices 201 to 204 is executed (step S3110).

In this display start processing, a command to start displaying the management results is sent from the main CPU 63 to the management CPU 112. Upon receiving this command to start displaying the management results, the management CPU 112 executes processing to display the first parameter from among the various parameters stored in the calculation result memory 131. The processing content in this case is the same as steps S3006 to S3012 in the display processing (Figure 55). As a result, a display corresponding to the first parameter calculated immediately before the operating power of the pachinko machine 10 was last shut off is displayed on the first to fourth notification display devices 201 to 204.

Next, we will explain the display modes of the first to fourth notification display devices 201-204 when the results of game history management are displayed and when the settings of the pachinko machine 10 are updated. Figure 57(a) is an explanatory diagram for explaining the display modes of the first to fourth notification display devices 201-204 when the results of game history management are displayed, and Figure 57(b) is an explanatory diagram for explaining the display modes of the first to fourth notification display devices 201-204 when the settings of the pachinko machine 10 are changed.

When the gaming history management results are displayed, at least one display segment is illuminated on each of the first through fourth notification display devices 201-204, as shown in FIG. 57(a). In other words, each of the first through fourth notification display devices 201-204 is in a display state. This is the same regardless of whether the notification target is parameters 1-8, 11-18, 21-26, 31, or 41-42. This allows the gaming hall manager to visually confirm that all of the first through fourth notification display devices 201-204 are in a display state and understand that the gaming history management results are being displayed on the first through fourth notification display devices 201-204.

On the other hand, when the setting state of the pachinko machine 10 is changed, all display segments are turned off in each of the first to third alert display devices 201-203, as shown in Figure 57(b). In other words, each of the first to third alert display devices 201-203 goes into a non-display state. Additionally, the fourth alert display device 204 displays one of the numbers "1" to "6." In this way, by displaying one of the numbers "1" to "6" in the fourth alert display device 204 and each of the first to third alert display devices 201-203 going into a non-display state, the amusement hall manager can see that the first to fourth alert display devices 201-204 are displaying values corresponding to the setting values, and can clearly understand the current setting values.

Next, we will explain how the first to fourth alarm display devices 201 to 204 change their display state, referring to the time charts in Figures 58(a) to 58(h). FIG. 58(a) shows the period during which the setting state of the pachinko machine 10 is changeable, FIG. 58(b) shows the update timing of the setting display on the first to fourth display devices 201-204, FIG. 58(c) shows the period during which the game history management results are displayed on the first to fourth display devices 201-204, FIG. 58(d) shows the update timing of the display corresponding to the game history management results on the first to fourth display devices 201-204, FIG. 58(e) shows the period during which the first display device 201 is in a display state, FIG. 58(f) shows the period during which the second display device 202 is in a display state, FIG. 58(g) shows the period during which the third display device 203 is in a display state, and FIG. 58(h) shows the period during which the fourth display device 204 is in a display state.

When the setting key insertion section 68a is turned ON and the supply of operating power to the pachinko machine 10 begins, the pachinko machine 10 enters a changeable state at timing t1, allowing the setting status of the pachinko machine 10 to be changed, as shown in Figure 58(a). At timing t1, the setting display is updated as shown in Figure 58(b), and the fourth alert display device 204 enters a display state as shown in Figure 58(h), and this display state continues. In this case, because "Setting 1" has been selected, "1" is displayed on the fourth alert display device 204. Meanwhile, at timing t1, the first to third alert display devices 201-203 are in a non-display state, i.e., all display segments remain unlit, as shown in Figures 58(e) to 58(g).

Subsequently, at times t2, t3, t4, and t5, the update button 68b is operated to change the setting value, resulting in an update timing for the setting value display at each of these times, as shown in Figure 58(b). In this case, as shown in Figure 58(h), the display content on the fourth alert display device 204 will change to the number corresponding to the changed setting value at each of these times, but the fourth alert display device 204 will remain in a display state, including at each time this display content changes. Meanwhile, as shown in Figures 58(e) to 58(g), the first to third alert display devices 201-203 will remain in a non-display state, i.e., all display segments will remain unlit, even at each of these update timings for the setting value display.

Then, at timing t6, the setting key insertion section 68a is turned OFF, ending the changeable state as shown in Figure 58(a). In this case, at timing t6, the display period for the gaming history management results begins as shown in Figure 58(c). Specifically, the display of the first parameter stored in the calculation result memory 131 begins. Therefore, at timing t6, the first to third notification display devices 201-203 are switched from a non-display state to a display state as shown in Figures 58(e) to 58(g), and the fourth notification display device 204 remains in a display state although the display content is changed.

After that, at times t7, t8, t9, t10, t11, and t12, the display of the gaming history management results is updated, as shown in Figure 58(d). In this case, as shown in Figures 58(e) to 58(h), the first to fourth notification display devices 201-204 will switch to display content corresponding to the updated gaming history management results at each of these times, but all of the first to fourth notification display devices 201-204 will maintain their display state, including at each time the display content is switched.

The present embodiment described above provides the following excellent effects:

In a configuration in which the results of game history management are displayed on the first to fourth notification display devices 201-204, when the setting state of the pachinko machine 10 is in a changeable state in which it is possible to change the setting state, a corresponding display is made on the first to fourth notification display devices 201-204. This makes it possible to use the first to fourth notification display devices 201-204 not only to display the results of game history management, but also as display devices for making a corresponding display in the changeable state.

The period during which the first to fourth notification display devices 201-204 display the results of game history management is distinguished from the period during which the first to fourth notification display devices 201-204 display information corresponding to the setting value being changeable. This makes it possible to identify which display is being displayed on the first to fourth notification display devices 201-204 by understanding the status of the display on the first to fourth notification display devices 201-204.

When a display corresponding to a changeable setting value is made, the first through fourth notification display devices 201-204 are controlled to display in a different manner than when the gaming history management results are displayed. This makes it possible to identify which display is being made on the first through fourth notification display devices 201-204 by understanding the display manner of the first through fourth notification display devices 201-204.

Multiple notification display devices 201-204 are provided. This allows for a wide variety of displays to be displayed corresponding to the results of game history management. Furthermore, the presence of multiple notification display devices 201-204 makes it possible to significantly differ the display format when displaying the results of game history management and when displaying a display corresponding to the changeable state of setting values.

When a display corresponding to the changeable state of the setting value is made, the first to third notification display devices 201-203, which are not in a hidden state when displaying the game history management results, are made in a hidden state. As a result, simply by checking whether the first to third notification display devices 201-203 are in a hidden state, it is possible to clearly identify which of the first to fourth notification display devices 201-204 is displaying the game history management results or the display corresponding to the changeable state of the setting value.

When a display corresponding to a changeable setting value state is made, the fourth alert display device 204 is in a display state, and the display content is the display content that can be displayed on the fourth alert display device 204 when displaying the gaming history management results. By allowing the display content on the fourth alert display device 204 to overlap in this way, it is possible to avoid restricting the display content when displaying the gaming history management results and when a display corresponding to a changeable setting value is made. Furthermore, even when the display content on the fourth alert display device 204 is configured to overlap in this way, the first through third alert display devices 201-203 are in a non-display state when a display corresponding to a changeable setting value is made, making it possible to identify which display is being made on the first through fourth alert display devices 201-204.

When the gaming history management results are displayed, the first through fourth notification display devices 201-204 are each in a display state. This makes it possible to clearly differentiate the display modes of the first through fourth notification display devices 201-204 when the gaming history management results are displayed and when a display corresponding to the changeable state of the setting value is performed.

When the gaming history management results are displayed, the first to fourth notification display devices 201-204 are not kept in a hidden state, even if the type of gaming history management result to be displayed is changed. This makes it possible to identify the gaming history management results regardless of when the first to fourth notification display devices 201-204 are checked while the gaming history management results are being displayed. Furthermore, regardless of when the first to fourth notification display devices 201-204 are checked, it is possible to identify whether the first to fourth notification display devices 201-204 are displaying the gaming history management results or a display corresponding to the changeable state of the setting values.

When a display corresponding to a changeable state of the setting value is being displayed, only one of the fourth notification display devices 204 is in a display state. This makes it easier to understand whether a display corresponding to a changeable state of the setting value is being displayed.

In a configuration in which the first to fourth notification display devices 201-204 are arranged horizontally, only the fourth notification display device 204, located at the far right, is used to display the setting value changeable state. This makes it easier to understand whether a display corresponding to the setting value changeable state is being displayed.

When the gaming history management results are displayed, the first alert display device 201 and the second alert display device 202 are used to display a result corresponding to the type of gaming history management result to be displayed, and the third alert display device 203 and the fourth alert display device 204 are used to display a result corresponding to the content of the gaming history management result. This makes it easier to understand the gaming history management results. In this case, when the setting value is changeable, the first alert display device 201 and the second alert display device 202, which display the type of gaming history management result, are both hidden. This means that the hidden state of the first and second alert display devices 201, 202, which display the type, corresponds to the setting value being changeable, making it easier to understand that a display corresponding to the setting value being changeable is being displayed.

In addition, when a display corresponding to a changeable state of the setting value is made, not only the first notification display device 201 and the second notification display device 202, which display the type of gaming history management result, but also the third notification display device 203, which displays the content of the gaming history management result, will be hidden. This makes it easier to understand that a display corresponding to a changeable state of the setting value is being made.

Display data is output from the MPU 62 to the first through fourth display ICs 205-208, which then cause the first through fourth alert display devices 201-204 to display a specific message in accordance with the display data. The display data is stored and held in the first through fourth display ICs 205-208. This makes it possible to maintain the display of the game history management results on the first through fourth alert display devices 201-204, even if the main CPU 63 stops executing processing for game progress due to, for example, a radio wave detection anomaly or vibration detection anomaly (when a positive determination is made in step S306).

Incidentally, among the first to fourth alert display devices 201-204, the devices that are in a non-display state (all lights off state) when the setting state of the pachinko machine 10 can be changed are not limited to the first to third alert display devices 201-203, but may also be the first and second alert display devices 201 and 202. In this case, the third alert display device 203 may be configured to display a predetermined display that is different from the current setting value (for example, displaying "5"), while the fourth alert display device 204 may display a number corresponding to the current setting value, or the fourth alert display device 204 may be configured to display a predetermined display that is different from the current setting value (for example, displaying "5"), while the third alert display device 203 displays a number corresponding to the current setting value. Alternatively, the first alert display device 201 and the third alert display device 203 may be configured to be in a non-display state (fully off state) and the second alert display device 202 and the fourth alert display device 204 may be configured to be in a display state; the first alert display device 201 and the fourth alert display device 204 may be configured to be in a non-display state (fully off state) and the second alert display device 202 and the third alert display device 203 may be configured to be in a display state; or the second alert display device 202 and the fourth alert display device 204 may be configured to be in a non-display state (fully off state) and the first alert display device 201 and the third alert display device 203 may be configured to be in a display state.

Furthermore, in a changeable state in which the setting state of the pachinko machine 10 can be changed, only the first alert display device 201 may be configured to be in a non-display state (all lights off state), only the second alert display device 202 may be configured to be in a non-display state (all lights off state), only the third alert display device 203 may be configured to be in a non-display state (all lights off state), or only the fourth alert display device 204 may be configured to be in a non-display state (all lights off state).

Furthermore, in a changeable state in which the setting state of the pachinko machine 10 can be changed, only the first alert display device 201 may be configured to be in a display state, only the second alert display device 202 may be configured to be in a display state, or only the third alert display device 203 may be configured to be in a display state.

Twelfth Embodiment
In this embodiment, the display contents of the first notification display device 201 and the second notification display device 202 when the setting value is changeable are different from those of the eleventh embodiment. The following describes the configurations that are different from the eleventh embodiment. Note that the description of the same configurations as the eleventh embodiment will basically be omitted.

Figure 59(a) is an explanatory diagram illustrating the configuration of the first alarm display device 201, and Figure 59(b) is an explanatory diagram illustrating the configuration of the second alarm display device 202.

As shown in Figure 59(a), the first alarm display device 201 has seven display segments, numbered 1 to 7, 201a to 201g. Each of the first to seventh display segments 201a to 201g is formed in a rod shape and has an LED or other light emitter inside. These seven display segments, numbered 1 to 7, 201a to 201g, are arranged so that the first alarm display device 201 is a so-called 7-segment display.

As shown in Figure 59(b), the second alarm display device 202 has seven display segments, numbered 1 to 7, 202a to 202g. Each of the first to seventh display segments 202a to 202g is formed in a rod shape and has an LED or other light emitter inside. These seven display segments, numbered 1 to 7, 202a to 202g, are arranged so that the second alarm display device 202 is a so-called 7-segment display.

Figure 60 is an explanatory diagram illustrating the display contents of the first notification display device 201 and the second notification display device 202 when the first to fourth notification display devices 201 to 204 display the results of game history management and when they display that the settings of the pachinko machine 10 are in a changeable state where they can be changed.

When displaying the results of game history management, the display contents of the first notification display device 201 and the second notification display device 202 are the same as those in the eleventh embodiment. Therefore, the first notification display device 201 displays either "A," "E," "H," "L," or "O," and the second notification display device 202 displays either "1" to "8."

In this case, each of the first to seventh display segments 201a to 201g of the first alarm display device 201 is subject to illumination when at least one of the following displays is displayed on the first alarm display device 201: "A," "E," "H," "L," or "O." In other words, there are no display segments 201a to 201g that are not subject to illumination when the first alarm display device 201 displays "A," "E," "H," "L," or "O."

Similarly, for the second alert display device 202, each of the first through seventh display segments 202a through 202g of the second alert display device 202 is subject to illumination when at least one of the numbers "1" through "8" is displayed on the second alert display device 202. In other words, there are no display segments 202a through 202g that are not subject to illumination when any of the numbers "1" through "8" is displayed on the second alert display device 202.

When the pachinko machine 10 is in a changeable state, in which the settings can be changed, the second display segment 201b and the fifth display segment 201e are illuminated on the first alert display device 201. As already explained, these second display segment 201b and fifth display segment 201e can be illuminated when the first alert display device 201 displays the results of game history management. Furthermore, the second display segment 201b and the fifth display segment 201e are illuminated in all cases in which the first alert display device 201 displays the results of game history management. On the other hand, when the results of game history management are displayed on the first alert display device 201, the display content of the first alert display device 201, in which only the second display segment 201b and the fifth display segment 201e are illuminated among the first to seventh display segments 201a to 201g, is not present. This makes it possible to display a display mode on the first alert display device 201 that is not displayed when displaying the gaming history management results while utilizing display segments 201b and 201e, which can be illuminated when displaying the gaming history management results, when the setting value is changeable. Therefore, it is possible to display a display corresponding to the setting value changeable state on the first alert display device 201 while also using display segments 201a to 201g that are used when displaying the gaming history management results.

When the setting value is changeable, the third display segment 202c of the second alert display device 202 is illuminated. As already explained, the third display segment 202c can be illuminated when the second alert display device 202 displays the gaming history management results. On the other hand, the display content of the second alert display device 202, in which only the third display segment 202c of the first through seventh display segments 202a through 202g is illuminated, is not present when the gaming history management results are displayed. This makes it possible to display a display mode on the second alert display device 202 that is not displayed when the gaming history management results are displayed, while utilizing the display segment 202c that can be illuminated when the gaming history management results are displayed, in the setting value changeable state. Therefore, it is possible to cause the second alert display device 202 to display a display corresponding to the setting value changeable state, while also using the display segments 202a through 202g that are used when displaying the gaming history management results.

Next, the setting value update process in this embodiment, which is executed by the main CPU 63, will be explained with reference to the flowchart in Figure 61.

First, processing is performed to start displaying setting values on the first and second alert display devices 201 and 202 (step S3201). Specifically, for the first alert display device 201, display data is output to the first display IC 205 so that the second display segment 201b and the fifth display segment 201e are illuminated and the other display segments 201a, 201c, 201d, 201f, and 201g are extinguished. For the second alert display device 202, display data is output to the second display IC 206 so that the third display segment 202c is illuminated and the other display segments 202a, 202b, 202d-202g are extinguished. This initiates a display on the first alert display device 201 and the second alert display device 202 to notify users that the setting state of the pachinko machine 10 is in a changeable state, allowing it to be changed.

Then, the third alarm display device 203 is turned off (step S3202). Specifically, display data that is all "0" is output to the third display IC 207. As a result, all display segments of the third alarm display device 203 are turned off, and the third alarm display device 203 enters a non-display state.

Then, the setting value counter in the main RAM 65 is set to "1" (step S3203). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value will become "Setting 1" regardless of the previous setting value.

Then, the fourth alarm display device 204 executes a process to start displaying the setting value (step S3204). In the process to start displaying the setting value, display data for displaying "1" is output to the fourth display IC 208. As a result, the number "1" corresponding to "Setting 1" is displayed on the fourth alarm display device 204.

Subsequently, on the condition that the setting key insertion unit 68a has not been turned OFF (step S3205: NO), it is determined whether the update button 68b has been pressed once (step S3206). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from LOW level to HIGH level. If a negative determination is made in step S3206, the process returns to step S3205, where it is determined whether the setting key insertion unit 68a has been turned OFF.

If the update button 68b has been pressed once (step S3206: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S3207). Furthermore, if the value of the setting value counter after incrementing by 1 exceeds "6" (step S3208: YES), the setting value counter is set to "1" (step S3209). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed; if the update button 68b is pressed once when the setting is "6," the setting will return to "1."

If a negative judgment is made in step S3208, or if the processing of step S3209 is executed, a display update process for the setting value on the fourth alert display device 204 is executed (step S3210). In the display update process for the setting value, display data for displaying a number corresponding to the value of the setting value counter in the main RAM 65 is output to the fourth display IC 208. As a result, a number corresponding to the current setting value is displayed on the fourth alert display device 204. By checking the fourth alert display device 204, the manager of the gaming hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b.

After executing step S3210, the process returns to step S3205, where it is determined whether the setting key insertion unit 68a has been turned OFF. If it has not been turned OFF (step S3205: NO), the process from step S3206 onwards is executed again. If it has been turned OFF (step S3205: YES), the process starts displaying the management results on the first to fourth alarm display devices 201 to 204 (step S3211).

In this display start processing, a command to start displaying the management results is sent from the main CPU 63 to the management CPU 112. Upon receiving this command to start displaying the management results, the management CPU 112 executes processing to display the first parameter from among the various parameters stored in the calculation result memory 131. The processing content in this case is the same as steps S3006 to S3012 in the display processing (Figure 55). As a result, a display corresponding to the first parameter calculated immediately before the operating power of the pachinko machine 10 was last shut off is displayed on the first to fourth notification display devices 201 to 204.

The present embodiment described above provides the following excellent effects:

By lighting up the display segments 201a-201g and 202a-202g of the first and second notification display devices 201 and 202 that can be illuminated when the gaming history management results are displayed, a display corresponding to the setting value changeable state is displayed. This makes it possible to diversify the display of gaming history management results while minimizing restrictions on the content of the display corresponding to the gaming history management results. On the other hand, for each of the first notification display device 201 and the second notification display device 202, the combinations of display segments 201a-201g and 202a-202g that are illuminated when a display corresponding to the setting value changeable state is displayed are combinations that do not exist when the gaming history management results are displayed. As a result, by determining the combinations of display segments 201a-201g and 202a-202g that are illuminated for each of the first notification display device 201 and the second notification display device 202, it is possible to determine whether the display of the gaming history management results or the display corresponding to the setting value changeable state is being displayed.

For each of the first notification display device 201 and the second notification display device 202, there are no display segments 201a-201g, 202a-202g that do not illuminate even when all patterns of game history management results are displayed. This makes it possible to minimize restrictions on the display content of game history management results while diversifying the display corresponding to the game history management results.

When a display corresponding to the changeable state of the setting value is made, the third notification display device 203, which is not made invisible when displaying the gaming history management results, is made invisible. As a result, by checking not only the display contents of the first notification display device 201 and the second notification display device 202 but also whether the third notification display device 203 is in the invisible state, it is possible to clearly identify which of the display of the gaming history management results and the display corresponding to the changeable state of the setting value is being made on the first to fourth notification display devices 201 to 204.

The first and second notification display devices 201, 202 are not limited to a configuration in which only one type of display content is set corresponding to the changeable states in which the setting state of the pachinko machine 10 can be changed; multiple types may be set. In this case, the display order of the multiple types of display content may be predetermined, and the display content to be displayed may be changed according to that display order each time a new changeable state is executed. Even when there are multiple types of display content corresponding to the changeable states of the setting value, these display contents are displayed using the display segments 201a-201g, 202a-202g that are illuminated when displaying the results of game history management, and are not displayed when displaying the results of game history management.

Furthermore, when displaying the gaming history management results or when displaying a display corresponding to a changeable state in which the settings of the pachinko machine 10 can be changed, the first and second alert display devices 201, 202 may be configured to flash in one direction, while remaining lit in the other direction. In this case, the amusement hall manager can identify whether the display corresponds to the gaming history management results or the changeable state depending on whether the display is flashing or lit. Therefore, the combination of display segments 201a-201g, 202a-202g that are illuminated in the display corresponding to the changeable state may be a combination used when displaying the gaming history management results, or a combination not used when displaying the gaming history management results. Furthermore, the lighting periods and off periods in the flashing display may be configured to match, be completely offset, or only partially overlap between the first alert display device 201 and the second alert display device 202.

Thirteenth Embodiment
This embodiment differs from the eleventh embodiment in that when an abnormal state occurs in the pachinko machine 10, a corresponding display is made using the first to fourth alarm display devices 201 to 204. The following describes the configuration that differs from the eleventh embodiment. Note that a description of the same configuration as the eleventh embodiment will basically be omitted.

Figure 62 is an explanatory diagram illustrating the configuration of the abnormality display area 211 provided in the main RAM 65.

The abnormality display area 211 is an area for storing information about abnormal conditions to be displayed on the first to fourth alarm display devices 201 to 204. The abnormality display area 211 has multiple unit areas 211a to 211d. Specifically, it has a first unit area 211a, a second unit area 211b, a third unit area 211c, and a fourth unit area 211d. Each of these first to fourth unit areas 211a to 211d can store one piece of information about an abnormal condition of the pachinko machine 10. In other words, the abnormality display area 211 can store and hold up to four pieces of information about an abnormal condition of the pachinko machine 10.

In this embodiment, all information about abnormal conditions that occur in the pachinko machine 10 is identified by the main CPU 63. For example, if an abnormality occurs related to the payout of game balls (e.g., the lower tray 56a is full, there are no balls in the tank 75, or a payout abnormality by the payout device 76), a command corresponding to the abnormality is sent from the payout CPU 92 to the main CPU 63. The pachinko machine 10 is also equipped with a radio wave detection sensor and a vibration detection sensor (not shown). If the radio wave detection sensor detects unauthorized radio waves, a corresponding abnormality signal is sent to the main CPU 63, and if the vibration detection sensor detects abnormal vibrations, a corresponding abnormality signal is sent to the main CPU 63. Furthermore, by identifying that each of the ball entry detection sensors 42a to 49a no longer transmits normal signals, the occurrence of a wire break abnormality in these ball entry detection sensors 42a to 49a is identified.

The number of types of abnormal conditions identified by the main CPU 63 is greater than the maximum number of abnormal condition information items that can be stored in the abnormality display area 211. As a result, if multiple abnormal conditions occur simultaneously, it is expected that new abnormal condition information will occur even though the maximum number of abnormal condition information items has already been stored in the abnormality display area 211. In response to this, storage priorities are set for abnormal condition information during the configuration stage of the pachinko machine 10, and if a new abnormal condition occurs when the maximum number of abnormal condition information items have already been stored in the abnormality display area 211, the abnormal condition information with the highest storage priority will remain in the abnormality display area 211. This makes it possible to prioritize the notification of abnormal conditions with the highest storage priority.

Next, the abnormality setting process executed by the main CPU 63 will be described with reference to the flowchart in Figure 63. Note that the abnormality setting process is executed as the first process of the timer interrupt process (Figure 11).

First, it is determined whether an abnormality has occurred (step S3301). The types of abnormalities that can be displayed include a full lower tray 56a, no balls in the tank 75, a dispensing error by the dispensing device 76, an abnormal radio wave detection error, an abnormal vibration detection error, and a disconnection error in each ball entry detection sensor 42a-49a. The number of types of abnormalities that can be displayed is greater than the number of first to fourth unit areas 211a-211d provided in the abnormality display area 211.

If a positive judgment is made in step S3301, it is determined whether information about the abnormal condition corresponding to the currently occurring abnormal display object has already been stored in any of the first to fourth unit areas 211a to 211d of the abnormality display area 211 (step S3302). If information about the abnormal condition corresponding to the currently occurring abnormal display object has already been stored, it is not stored in the abnormality display area 211. This makes it possible to prevent information about the same type of abnormal condition from being stored twice in the abnormality display area 211.

If a negative determination is made in step S3302, the main CPU 63 determines whether the value of the abnormality target counter stored in the main RAM 65 is at its maximum value (specifically, "4") (step S3303). The abnormality target counter is a counter used by the main CPU 63 to determine the number of areas among the first to fourth unit areas 211a to 211d in the abnormality display area 211 that store information about abnormal conditions.

If the value of the abnormality object counter is at its maximum value (step S3303: YES), a priority comparison process is executed (step S3304). The priority comparison process first identifies the abnormality information with the lowest storage priority among the abnormality information stored in the first to fourth unit areas 211a to 211d of the abnormality display area 211. The storage priority is predetermined during the design stage of the pachinko machine 10, and specifically, the storage priority increases in the following order: full lower tray 56a → no balls in tank 75 → vibration detection abnormality → payout abnormality by payout device 76 → disconnection abnormality in ball entry detection sensors 42a to 49a → radio wave detection abnormality. The priority comparison process compares the abnormality information with the lowest storage priority stored in the first to fourth unit areas 211a to 211d with the currently occurring abnormality display object to determine which has a higher storage priority.

If the storage priority of the currently occurring abnormality display object is low (step S3305: NO), information about the abnormal condition corresponding to the currently occurring abnormality display object is not stored in the abnormality display area 211. This makes it possible to leave information about abnormal conditions with a high storage priority in the abnormality display area 211 in a configuration where the number of types of abnormality display objects is greater than the number of first to fourth unit areas 211a to 211d provided in the abnormality display area 211.

If the storage priority of the currently occurring abnormality display target is higher (step S3305: YES), the setting process for the abnormality display area 211 is executed (step S3306). In the setting process for the abnormality display area 211, which is executed when a positive determination is made in step S3305, the information on the abnormality state corresponding to the currently occurring abnormality display target is overwritten in the unit area 211a-211d identified as storing information on the abnormality state with the lowest storage priority.

On the other hand, if the value of the abnormality object counter in the main RAM 65 has not reached its maximum value (step S3303: NO), the value of the abnormality object counter is incremented by 1 (step S3307), and then the setting process for the abnormality display area 211 is executed (step S3306). In this setting process, one area is selected from the unit areas 211a to 211d in which no abnormality state information is stored in the abnormality display area 211, and the abnormality state information corresponding to the currently occurring abnormality display object is stored in the selected area.

In step S3306, if there is only one abnormality information stored in the abnormality display area 211, that abnormality information is stored in the first unit area 211a.If there are multiple abnormality information stored in the abnormality display area 211, the abnormality information is stored in the nth unit areas 211a to 211b in order from the area with the smallest value of "n."

The abnormality setting process determines whether an event that would cause the abnormality display to be canceled has occurred (step S3308). For example, it determines whether a command indicating that the full state of the lower tray 56a has been canceled, the absence of balls in the tank 75 has been canceled, or a dispensing abnormality caused by the dispensing device 76 has been canceled has been received from the dispensing side CPU 92. It also determines whether an abnormality cancellation operation has been performed in response to the occurrence of a radio wave detection abnormality, whether an abnormality cancellation operation has been performed in response to the occurrence of a vibration detection abnormality, or whether an abnormality cancellation operation has been performed in response to the occurrence of a disconnection abnormality.

If a positive determination is made in step S3308, the abnormality display area 211 is cleared (step S3309). This clearing process determines whether abnormal condition information corresponding to the abnormality display target that has been cleared is stored in any of the first to fourth unit areas 211a to 211d of the abnormality display area 211. If stored, the area in which the abnormal condition information is stored is cleared to "0" to erase the abnormal condition information. In this case, if there is only one abnormal condition information stored in the abnormality display area 211 after the clearing, the abnormal condition information is stored in the first unit area 211a. If there are multiple abnormal condition information stored in the abnormality display area 211 after the clearing, the abnormal condition information is stored in the nth unit areas 211a to 211b in order from the area with the smallest "n" value. The value of the abnormality target counter in the main RAM 65 is also decremented by 1 (step S3310).

The abnormality setting process determines whether an operation to start an abnormality display has occurred (step S3311). The operation to start an abnormality display is performed by pressing the update button 68b with the gaming machine body 12 open forward relative to the outer frame 11 in a situation where the setting state of the pachinko machine 10 is not in a changeable state in which it is possible to change the setting state.

If a positive judgment is made in step S3311, it is determined whether information on one or more abnormal conditions is stored in the abnormality display area 211 (step S3312). If no information on an abnormal condition is stored, abnormality display is not initiated on the first to fourth alarm display devices 201 to 204. This makes it possible to prevent abnormality display from being initiated even when there is no information on an abnormal condition to be notified.

If a positive determination is made in step S3312, the abnormality display flag stored in the main RAM 65 is set to "1" (step S3313). The abnormality display flag is a flag used by the main CPU 63 to identify a situation in which the display corresponding to the gaming history management results should be stopped and a display corresponding to the abnormal state information stored in the abnormality display area 211 should be displayed on the first to fourth alarm display devices 201-204. Note that even if an operation to start an abnormality display is performed when the abnormality display flag has already been set to "1," a negative determination is made in step S3311.

Then, a process to set the display of management results to halt is executed (step S3314). In this halt setting process, a display halt command is sent to the management CPU 112, temporarily halting the update of the display of the gaming history management results on the first to fourth notification display devices 201 to 204. Upon receiving this display halt command, the management CPU 112 halts execution of the display process (Figure 55). However, even if the management CPU 112 receives the display halt command, it does not set display data to all "0" data in the first to fourth display ICs 205 to 208. Therefore, the display of the gaming history management results at that time will continue on the first to fourth notification display devices 201 to 204 until display data is sent from the main CPU 63 to the first to fourth display ICs 205 to 208.

In the abnormality setting process, it is determined whether an operation to end the abnormality display has occurred (step S3315). The operation to end the abnormality display is performed by pressing the reset button 68c with the gaming machine body 12 open forward relative to the outer frame 11 in a situation where the setting state of the pachinko machine 10 is not in a changeable state where it is possible to change it. If a positive determination is made in step S3315, the abnormality display flag in the main RAM 65 is cleared to "0" (step S3316). Note that even if an operation to end the abnormality display is performed in a situation where the value of the abnormality display flag is already "0", a negative determination is made in step S3315.

Then, the system executes a process to cancel the suspension of the display of the management results (step S3317). In this process, a suspension command is sent to the management CPU 112, thereby canceling the suspension of the display updates of the gaming history management results on the first through fourth notification display devices 201-204. Upon receiving the suspension command, the management CPU 112 resumes the display process (Figure 55). However, even after receiving the suspension command, the management CPU 112 does not set display data to all "0" data in the first through fourth display ICs 205-208. Therefore, the current abnormality display continues on the first through fourth notification display devices 201-204 until display data is sent from the management CPU 112 to the first through fourth display ICs 205-208. Furthermore, even when the update of the display updates of the gaming history management results is suspended, the management CPU 112 continues to store history information and calculate various parameters, and the results of calculating the various parameters are stored in the calculation result memory 131. Therefore, when the state in which updates to the gaming history management results display were suspended is lifted, the display of the most recent gaming history management results will immediately resume on the first through fourth notification display devices 201 through 204.

During the abnormality setting process, if the abnormality display flag in the main RAM 65 is set to "1" (step S3318: YES), the abnormality display process is executed (step S3319). Figure 64 is a flowchart showing the abnormality display process.

First, the first and second alarm display devices 201, 202 are turned off (step S3401). Specifically, display data that is all "0" is output to the first and second display ICs 205, 206. As a result, all display segments of both the first and second alarm display devices 201, 202 are turned off, and the first and second alarm display devices 201, 202 are turned off.

Then, the value of the update timing counter stored in the main RAM 65 is decremented by 1 (step S3402). The update timing counter is a counter that the main CPU 63 uses to determine whether it is time to update the display contents of the abnormality display on the first to fourth alarm display devices 201 to 204. If the value of the update timing counter is already "0," this state is maintained. Then, by determining whether the value of the update timing counter is "0," it is determined whether it is time to update the display contents of the first to fourth alarm display devices 201 to 204 (step S3403).

If a positive judgment is made in step S3403, an update process for the display target counter provided in the main RAM 65 is executed (step S3404). In this update process, if this is the first time the abnormality display process has been performed since the abnormality display flag in the main RAM 65 was set to "1", the display target counter is set to "0". The values of the display target counter correspond to the first to fourth unit areas 211a to 211d of the abnormality display area 211. Specifically, a value of "0" in the display target counter corresponds to the first unit area 211a, a value of "1" in the display target counter corresponds to the second unit area 211b, a value of "2" in the display target counter corresponds to the third unit area 211c, and a value of "3" in the display target counter corresponds to the fourth unit area 211d. In the update process, if this is not the first time the abnormality display process has been performed since the abnormality display flag in the main RAM 65 was set to "1", the value of the display target counter is incremented by 1.

Then, it is determined whether abnormal state information is stored in the area among the first to fourth unit areas 211a to 211d that corresponds to the current value of the counter to be displayed (step S3405). As already explained, if only one abnormal state information item is stored, that abnormal state information item is stored in the first unit area 211a. If multiple abnormal state information items are stored, the abnormal state information items are stored in the nth unit areas 211a to 211b, starting with the area with the smallest "n" value. Therefore, if no abnormal state information is stored in the area corresponding to the current value of the counter to be displayed, then no abnormal state information is stored in the area corresponding to a value greater than the value of the counter to be displayed. Furthermore, if the value of the counter to be displayed after adding 1 exceeds the maximum value of "3," then there is no corresponding area, and so it is treated as if no abnormal state information is stored.

If a positive judgment is made in step S3405, the value of the display target counter in the main RAM 65 is cleared to "0" (step S3406). Here, it is assumed that all abnormal conditions that are the subject of abnormality display while an abnormality display is being performed will be canceled. In this case, even when the abnormality display process is being executed, no abnormality condition information is stored in the abnormality display area 211. In such a situation, the third and fourth alarm display devices 203, 204 will display an indication that no abnormality condition information is stored.

If a negative judgment is made in step S3405, or if the processing of step S3406 is executed, display data for the display target corresponding to the value of the display target counter in the main RAM 65 is read from the main ROM 64 (step S3407). Specifically, information stored in the area corresponding to the value of the display target counter in the main RAM 65 among the first to fourth unit areas 211a to 211d of the abnormality display area 211 is read. Then, display data corresponding to that information is read from the main ROM 64. The display data is set in one-to-one correspondence with the abnormality status information, and the display content of the third and fourth alarm display devices 203, 204 based on that display data differs depending on the type of abnormality status information. In addition, display data corresponding to the absence of abnormality status information also exists, and this display data differs from the display data corresponding to abnormality status information. Therefore, when abnormality status information does not exist, the display content of the third and fourth alarm display devices 203, 204 will be different from the display content when abnormality status information is present.

On the other hand, the display contents of the displays corresponding to abnormal state information and the display contents corresponding to the absence of abnormal state information on the third and fourth alert display devices 203, 204 overlap with the display contents when displaying the gaming history management results on the third and fourth alert display devices 203, 204 and the display contents of the setting values on the fourth alert display device 204. In contrast, when displaying the gaming history management results, all of the first through fourth alert display devices 201-204 are in a display state; when the pachinko machine 10's setting state is in a changeable state where it is possible to change it, the first through third alert display devices 201-203 are in a hidden state and the fourth alert display device 204 is in a displayed state; and when an abnormality is displayed, the first and second alert display devices 201, 202 are in a hidden state and the third and fourth alert display devices 203, 204 are in a displayed state. Therefore, even if the display contents overlap as described above, the amusement hall manager can determine which situation the display corresponds to.

Then, the display of the third alarm display device 203 is controlled in accordance with the display data read in step S3407 (step S3408), and the display of the fourth alarm display device 204 is controlled (step S3409). In this case, whether a display corresponding to information about an abnormal state is being displayed or a display corresponding to the absence of information about an abnormal state is being displayed, neither the third alarm display device 203 nor the fourth alarm display device 204 will be in a non-display state (i.e., will not be in a completely off state), but will remain in some display state.

Then, the update timing counter in the main RAM 65 is set to a value corresponding to 2 seconds as the value corresponding to the next update timing (step S3410).

The present embodiment described above provides the following excellent effects:

In a configuration in which the results of game history management are displayed on the first to fourth notification display devices 201-204, displays corresponding to abnormal conditions in the pachinko machine 10 are also displayed on the first to fourth notification display devices 201-204. This makes it possible to use the first to fourth notification display devices 201-204 not only to display the results of game history management, but also as display devices for displaying information corresponding to abnormal conditions.

When the first to fourth alert display devices 201-204 are made to display an indication corresponding to an abnormal state when no abnormal state has occurred in the pachinko machine 10, the first to fourth alert display devices 201-204 will display an indication corresponding to the absence of an abnormal state. This makes it possible to clearly determine whether or not an abnormal state has occurred in the pachinko machine 10 by checking the first to fourth alert display devices 201-204.

The period during which the first to fourth alert display devices 201-204 display the results of game history management is distinguished from the period during which the first to fourth alert display devices 201-204 display information corresponding to abnormal conditions in the pachinko machine 10. This makes it possible to identify which display is being displayed on the first to fourth alert display devices 201-204 by understanding the status of the display on the first to fourth alert display devices 201-204.

When a display corresponding to an abnormal state of the pachinko machine 10 is made, the first to fourth alert display devices 201-204 are controlled to display a different style from the style used when displaying the gaming history management results. This makes it possible to identify which display is being made on the first to fourth alert display devices 201-204 by understanding the display style of the first to fourth alert display devices 201-204.

Multiple notification display devices 201-204 are provided. This makes it possible to display a wide variety of information corresponding to the results of game history management. Furthermore, the presence of multiple notification display devices 201-204 makes it possible to significantly differ the display format when displaying the results of game history management and when displaying information corresponding to an abnormal state of the pachinko machine 10.

When a display corresponding to an abnormal state of the pachinko machine 10 is made, the first and second alert display devices 201, 202, which are not made invisible when displaying the game history management results, are made invisible. As a result, simply by checking whether the first and second alert display devices 201, 202 are made invisible, it becomes possible to clearly identify which of the game history management results and the abnormal state of the pachinko machine 10 displays are being made on the first to fourth alert display devices 201-204.

When a display corresponding to an abnormal state of the pachinko machine 10 is made, the third and fourth alert display devices 203, 204 are turned on, and the display content is the same as that which can be displayed on the third and fourth alert display devices 203, 204 when displaying the game history management results. By allowing the display content on the third and fourth alert display devices 203, 204 to overlap in this way, it is possible to avoid restrictions on the display content when displaying the game history management results and when a display corresponding to an abnormal state of the pachinko machine 10 is made. Furthermore, even when the display content on the third and fourth alert display devices 203, 204 is configured to overlap in this way, the first and second alert display devices 201, 202 are turned off when a display corresponding to an abnormal state of the pachinko machine 10 is made, making it possible to identify which display is being made on the first through fourth alert display devices 201-204.

In addition, if an operation to start the abnormality display is performed when no abnormality information is stored in the abnormality display area 211, the first to fourth alarm display devices 201 to 204 may be configured to display a message indicating that no abnormality information is stored at that time.

<Fourteenth embodiment>
In this embodiment, the processing configuration of the management output process executed by the main CPU 63 is different from that of the first embodiment. The configuration that differs from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 65 is a flowchart showing the management output processing in this embodiment executed by the main CPU 63.

First, it is determined whether the management start flag stored in the main RAM 65 is set to "1" (step S3501). The management start flag is a flag used by the main CPU 63 to determine whether history information should be stored in the history memory 117. In this embodiment, after the supply of operating power to the pachinko machine 10 begins (i.e., after the supply of operating power to the MPU 62 begins), history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA reaches or exceeds the number corresponding to the management start reference value. When the total number of game balls discharged from the play area PA reaches or exceeds the number corresponding to the management start reference value, the history information begins to be stored in the history memory 117. During the shipping stage of the pachinko machine 10, an operation check of the pachinko machine 10 may be performed prior to shipping. At that time, game balls are placed in each ball entry section and the subsequent operation is checked. In response to this, by not storing history information in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, it is possible to prevent ball entry results and the like during the operation check described above from being stored as history information.

If a negative judgment is made in step S3501, the start management counter provided in the main RAM 65 is set to "7" (step S3502). The start management counter is a counter that allows the main CPU 63 to determine which of the seven ball entry detection sensors 42a to 48a is currently in a situation where the game ball detection state needs to be determined when the management start flag is not set to "1."

Then, it is determined whether the output flag in the main RAM 65 corresponding to the value of the start-up management counter is set to "1" (step S3503). Specifically, if the value of the start-up management counter is "7" and corresponds to the first winning slot detection sensor 42a, it is determined whether the first output flag is set to "1." If the value of the start-up management counter is "6" and corresponds to the second winning slot detection sensor 43a, it is determined whether the second output flag is set to "1." If the value of the start-up management counter is "5" and corresponds to the third winning slot detection sensor 44a, it is determined whether the third output flag is set to "1." If the value of the start-up management counter is "4" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1." If the value of the start management counter is "3" and corresponds to the first actuation port detection sensor 46a, it determines whether the fourth output flag is set to "1." If the value of the start management counter is "2" and corresponds to the second actuation port detection sensor 47a, it determines whether the sixth output flag is set to "1." If the value of the start management counter is "1" and corresponds to the outlet 24a, it determines whether the seventh output flag is set to "1." As already explained, these first through seventh output flags are set to "1" during the ball entry detection process (Figure 15).

If a positive judgment is made in step S3503, the output flag corresponding to the value of the start management counter is cleared to "0" (step S3504). Then, the value of the discharged ball number counter provided in the main RAM 65 is incremented by 1 (step S3505). The discharged ball number counter is a counter used by the main CPU 63 to determine the total number of game balls discharged from the game area PA when the management start flag in the main RAM 65 is not set to "1".

Then, it is determined whether the value of the discharged number counter is equal to or greater than the management start reference value (step S3506). The management start reference value is set to "300," but is not limited to this and may be a number less than "300" or greater than "300."

If a negative judgment is made in step S3503, or if a negative judgment is made in step S3506, the value of the start-up management counter in the main RAM 65 is decremented by 1 (step S3507). Then, it is determined whether the value of the start-up management counter after the decrement is "0" (step S3508). If a negative judgment is made in step S3508, the process returns to step S3503; if a positive judgment is made in step S3508, the management output process is terminated.

On the other hand, if the value of the discharged item counter in the main RAM 65 is equal to or greater than the management start reference value (step S3506: YES), the management start flag in the main RAM 65 is set to "1" (step S3509). Then, management processing is executed (step S3510). Furthermore, if the management start flag is set to "1" and a positive determination is made in step S3501, management processing is also executed (step S3510). The processing content of the management processing is the same as steps S1001 to S1012 of the management output processing (Figure 25) in the first embodiment described above.

With the above configuration, after the supply of operating power to the pachinko machine 10 has begun (i.e., after the supply of operating power to the MPU 62 has begun), history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA reaches or exceeds the management start reference value. When the total number of game balls discharged from the play area PA reaches or exceeds the management start reference value, history information storage in the history memory 117 begins. When the pachinko machine 10 is shipped, an operation check of the pachinko machine 10 may be performed before shipping, during which time game balls are placed in each ball entry section and the subsequent operation is checked. By not storing history information in the history memory 117 until the total number of game balls discharged from the play area PA reaches or exceeds the management start reference value after the supply of operating power to the pachinko machine 10 has begun, it is possible to prevent ball entry results and the like from being stored as history information during the operation check described above.

Here, in a configuration in which history information is not stored in history memory 117 until the total number of game balls discharged from play area PA after the supply of operating power to pachinko machine 10 begins and reaches or exceeds the number corresponding to the management start reference value, as described above, it is not possible to calculate the game history management results for that period. Therefore, in such a situation, the first through fourth alert display devices 201-204 may be configured to display a message corresponding to the situation. For example, all display segments on each of the first through fourth alert display devices 201-204 may be configured to be illuminated. This display content is not displayed whether the game history management results are displayed or when indicating that the settings of the pachinko machine 10 are changeable. Therefore, by checking the first through fourth alert display devices 201-204, it is possible to determine whether the situation in which history information is not stored is as described above.

In addition, the setting of the information in the management start flag in the main RAM 65 may be different depending on whether the setting state of the pachinko machine 10 has entered a changeable state in which it is possible to change the setting state after the supply of operating power to the pachinko machine 10 has started. Figure 66 is a flowchart showing main processing in this alternative embodiment executed by the main CPU 63. Steps S3601 to S3609 execute the same processing as steps S101 to S109 in the main processing (Figure 9) in the first embodiment described above, and steps S3611 to S3620 execute the same processing as steps S110 to S119 in the main processing (Figure 9) in the first embodiment described above. On the other hand, in this alternative embodiment, if a positive judgment is made in step S3608, the management start flag in the main RAM 65 is cleared to "0" (step S3610), and after executing the processing of step S3620, the management start flag in the main RAM 65 is set to "1" (step S3621). With this configuration, if the process for setting a new setting for the pachinko machine 10 is not executed, history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, and if the process for setting a new setting for the pachinko machine 10 is executed, history information is stored in the history memory 117 regardless of the number of game balls discharged after the supply of operating power to the pachinko machine 10 begins. This makes it possible to manage the game history immediately after the supply of operating power to the pachinko machine 10 begins in situations where there is a high possibility that the operation check performed at the time of shipment of the pachinko machine 10 will not be applicable.

In addition, instead of a configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, a configuration may be adopted in which an area separate from the history memory 117 is provided for storing history information until the total number of game balls reaches or exceeds the management start reference value. This makes it possible to identify the management results of the game history in that situation.

In addition, a condition for preventing history information from being stored in history memory 117 from the time the supply of operating power to pachinko machine 10 begins until the total number of game balls discharged from play area PA reaches or exceeds the management start reference value may be added, namely, when the supply of operating power to pachinko machine 10 begins when no history information is stored in history memory 117. In this case, if the supply of operating power to pachinko machine 10 begins when history information is already stored in history memory 117, history information will be stored in history memory 117 from the beginning, regardless of whether the total number of game balls discharged from play area PA reaches or exceeds the management start reference value.

In addition to or instead of a configuration in which history information is not stored in history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to pachinko machine 10 begins reaches or exceeds the management start reference value, if an abnormal condition such as a radio wave detection abnormality or vibration detection abnormality occurs, history information may not be stored in history memory 117 until the abnormal condition is resolved. This makes it possible to prevent history information from being stored for events that occur in an abnormal condition.

In addition to or instead of a configuration in which history information is not stored in the history memory 117 until the total number of game balls discharged from the play area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, history information may not be stored in the history memory 117 when the gaming machine main body 12 or front door frame 14 is open. This makes it possible to prevent history information from being stored for events that occur when the gaming machine main body 12 or front door frame 14 is open.

<Fifteenth embodiment>
In this embodiment, the entity that executes the process for managing the game history differs from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will be basically omitted.

In the first embodiment described above, the MPU 62 is provided with a management IC 66, but in this embodiment, the MPU 62 is not provided with a management IC 66. Instead of providing a management IC 66, in this embodiment, the main CPU 63 executes processing for managing game history. Furthermore, in this embodiment, the main CPU 63 executes various controls by distinguishing between specific control and non-specific control. Specifically, control related to the management of game history is considered non-specific control, and control other than non-specific control, including control for progressing the game based on the player's game operations, is considered specific control.

Specific control specifically includes all of the control performed by the main processing (Figure 9) when the supply of operating power to the main CPU 63 begins. Note that in this embodiment, the recognition processing (step S111), data output processing (step S112), and setting value update signal output processing (step S119) of the main processing (Figure 9) in the first embodiment are not executed. Also, in this embodiment, timer interrupt processing is periodically executed by interrupting the processing of steps S113 to S116 in the main processing (Figure 9), and all of the various processes in this timer interrupt processing, except for the management processing described below, are included in specific control. Furthermore, some of the management processing is also included in specific control.

Figure 67 is an explanatory diagram illustrating how programs and data are set in the main ROM 64. In accordance with the distinction between specific control and non-specific control in the control executed by the main CPU 63, as shown in Figure 67, the addresses of the areas in the main ROM 64 where programs and data for specific control are stored are clearly distinguished from those where programs and data for non-specific control are stored.

Specific control programs are collectively stored in the area of consecutive addresses within the range of addresses X(1) to X(k+2). Addresses X(k+3) to X(k+5), which are consecutive to addresses X(1) to X(k+2), are unused addresses where no data is stored, and specific control data are collectively stored in the area of consecutive addresses within the range of addresses X(k+6) to X(m+2). Addresses X(m+3) to X(m+5), which are consecutive to addresses X(k+6) to X(m+2), are unused addresses where no data is stored, and non-specific control programs are collectively stored in the area of consecutive addresses within the range of addresses X(m+6) to X(n+2). Additionally, addresses X(n+3) to X(n+5), which are consecutive to addresses X(m+6) to X(n+2), are unused area addresses where no data is stored, and non-specific control data is collectively stored in each consecutive address area within the range of addresses X(n+6) to X(p+2). Note that the relationship between the above programs and data and addresses is set both in physical addresses in the primary ROM 64 and in logical addresses on the memory map recognized by the primary CPU 63.

As described above, programs and data for specific control and programs and data for non-specific control are stored in different address ranges, regardless of the execution order of the processes for executing the corresponding controls. Therefore, for example, when checking only programs and data for specific control, it is sufficient to check only the address range area where these programs and data for specific control are stored. Similarly, when checking only programs and data for non-specific control, it is sufficient to check only the address range area where these programs and data for non-specific control are stored. This makes it possible to efficiently check programs and data for specific and non-specific control separately. This also makes it possible to efficiently modify programs and data for specific and non-specific control separately.

By setting an address range for an unused area where no data is stored between the address range of the area where specific control programs and specific control data are stored and the address range of the area where non-specific control programs and non-specific control data are stored, it becomes easier to grasp the boundary between the address range for specific control and the address range for non-specific control when checking.

In the address ranges for specific control and the address ranges for non-specific control, programs and data are stored in different address ranges, regardless of the execution order of the processes for executing the corresponding controls. This allows for efficient work when checking programs and data separately. Furthermore, an address range for an unused area where no data is stored is set between the address range of the area where programs are stored and the address range of the area where data is stored, making it easier to grasp the boundary between the address range of the program and the address range of the data when checking.

Figure 68 is an explanatory diagram illustrating the setting of each area in the main RAM 65. In accordance with the distinction between specific control and non-specific control executed by the main CPU 63, as shown in Figure 68, the address ranges of the work area 221 for specific control and the stack area 222 for specific control are clearly distinguished from the address ranges of the work area 223 for non-specific control and the stack area 224 for non-specific control in the main RAM 65.

Specifically, the area of consecutive addresses within the range of addresses Y(1) to Y(r+2) is set as the specific control work area 221. Furthermore, addresses Y(r+3) to Y(r+5), which are consecutive to addresses Y(1) to Y(r+2), are unused addresses, and the area of consecutive addresses within the range of addresses Y(r+6) to Y(s+2) are set as the specific control stack area 222. Furthermore, addresses Y(s+3) to Y(s+5), which are consecutive to addresses Y(r+6) to Y(s+2), are unused addresses, and the area of consecutive addresses within the range of addresses Y(s+6) to Y(t+2) are set as the non-specific control work area 223. Additionally, addresses Y(t+3) to Y(t+5), which are consecutive to addresses Y(s+6) to Y(t+2), are unused area addresses, and the areas of consecutive addresses within the range of addresses Y(t+6) to Y(u+2) are set as the non-specific control stack area 224. The relationship between each area and address as described above is set both as a physical address in the primary RAM 65 and as a logical address on the memory map recognized by the primary CPU 63.

As described above, by separately setting the work area 221 for specific control and the work area 223 for non-specific control, different areas of the main RAM 65 are used when performing various calculations, etc., when the main CPU 63 executes specific control and when it executes non-specific control. This makes it less likely that information in the main RAM 65 required for specific control or non-specific control will be erased when the other is executed. Incidentally, the main CPU 63 issues a load command when writing information to each work area 221, 223 and reading information from each work area 221, 223.

By separately setting the stack area 222 for specific control and the stack area 224 for non-specific control, different areas of the main RAM 65 are used when saving information stored in the main CPU 63's registers and when storing program return address information, depending on whether the main CPU 63 is executing specific control or non-specific control. This makes it less likely that information used in the other control will be erased when saving information stored in the main CPU 63's registers or storing program return address information while one of the specific and non-specific controls is being executed. Incidentally, when writing information to each stack area 222, 224, the main CPU 63 issues a push command, and when reading information from each stack area 222, 224, the main CPU 63 issues a pop command. Furthermore, when reading information from each stack area 222, 224, the order in which information is written to the stack area 222, 224 is such that the last information is read first.

Here, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can write information to the specific control work area 221 and the specific control stack area 222, and can read information from the specific control work area 221 and the specific control stack area 222. On the other hand, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can read information from the non-specific control work area 223 and the non-specific control stack area 224, but cannot write information to the non-specific control work area 223 and the non-specific control stack area 224. This makes it possible to prevent information used in processing corresponding to non-specific control from being accidentally erased when processing corresponding to specific control is being executed.

Furthermore, when the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can write information to the non-specific control work area 223 and the non-specific control stack area 224, and can read information from the non-specific control work area 223 and the non-specific control stack area 224. On the other hand, when the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can read information from the specific control work area 221 and the specific control stack area 222, but cannot write information to the specific control work area 221 and the specific control stack area 222. This makes it possible to prevent information used in processing corresponding to specific control from being accidentally erased when processing corresponding to non-specific control is being executed.

Note that backup power will continue to be supplied to the main RAM 65 even after the power to the pachinko machine 10 is shut off, and this backup power will be supplied to all of the specific control work area 221, the specific control stack area 222, the non-specific control work area 223, and the non-specific control stack area 224. As a result, the information stored in the specific control work area 221, the specific control stack area 222, the non-specific control work area 223, and the non-specific control stack area 224 will be retained as long as backup power is being supplied, even after the power to the pachinko machine 10 is shut off.

Next, the timer interrupt processing in this embodiment, which is executed by the main CPU 63, will be described with reference to the flowchart in Figure 69. As in the first embodiment, the timer interrupt processing is executed periodically (for example, every 4 milliseconds) while the processing of steps S113 to S116 is being executed in the main processing (Figure 9). Note that the program corresponding to the timer interrupt processing is set in the program for specific control.

Steps S3701 to S3718 execute the same processing as steps S301 to S318 of the timer interrupt processing (Figure 11) in the first embodiment described above. These processes are executed by the main CPU 63 using a specific control program and specific control data. In step S3719 of the timer interrupt processing, management processing is executed. When management processing is executed, a subroutine program corresponding to the management processing set in the specific control program is executed. When this subroutine program is executed, information for specifying the return address of the timer interrupt processing after execution of the management processing is written to the specific control stack area 222 by a push command. Then, when the management processing is completed, information for specifying the return address is read by a pop command, and processing returns to the timer interrupt processing program indicated by the return address.

Figure 70 is a flowchart showing the management processing. Note that steps S3801 to S3805 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 69) (step S3801). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, a push command is issued as "PUSH PSW" to save the information in the flag register of the main CPU 63 to the specific control stack area 222 (step S3802). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process is started, it is possible to save the flag register information in the specific control stack area 222 in its state before it changes after the subroutine is called or started. The size of the flag register information is 1 byte.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S3803). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

When the management execution process is completed and the program for management processing is returned to, the flag register information saved in the stack area 222 for specific control in step S3802 is restored to the flag register of the primary CPU 63 by a pop command as "POP PSW" (step S3804). This restores the information in the flag register of the primary CPU 63 to the information at the time step S3802 was executed. In other words, the information in the flag register of the primary CPU 63 is restored to the information required to execute specific control.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S3805). This allows new execution of timer interrupt processing.

Figure 71 is a flowchart showing the management execution process. Note that steps S3901 to S3915 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, a load command is issued to set "LD SP, Y(u+2)" to the stack pointer of the primary CPU 63 as a fixed address at the start of non-specific control, Y(u+2) (step S3901). The stack pointer is an area where address information is set, allowing the primary CPU 63 to identify the storage area in the stack areas 222 and 224 to which information is to be written in response to a push command. Each time a push command is issued, the stack pointer information is updated to the address information of the storage area to be written next. Each time a pop command is issued, the stack pointer information is updated to the address information of the storage area to be written previously. Furthermore, when the stack area 224 for non-specific control is used, information to be stored is stored starting from the storage area with the last address in the stack area 224 for non-specific control. Each time information to be stored is added, the storage area to be stored is changed toward the first address in the stack area 224 for non-specific control. Therefore, in step S3901, the stack pointer is set to the last address information in the stack area 224 for non-specific control. This same process of storing information from the memory area with the last address to the memory area with the first address also applies to the specific control stack area 222.

Incidentally, for both the specific control stack area 222 and the non-specific control stack area 224, if an additional push command is executed even though information has been set in all storage areas, all areas of the main RAM 65 are cleared to "0" as an abnormality has occurred in the storage process. This makes it possible to prevent the game from continuing even though an abnormality has occurred in the storage process.

Thereafter, the information in the WA register of the main CPU 63 is saved to the WA buffer set in the work area 223 for non-specific control by a load command as "LD (_WABUF), WA" (step S3902). Also, the information in the BC register of the main CPU 63 is saved to the BC buffer set in the work area 223 for non-specific control by a load command as "LD (_BCBUF), BC" (step S3903). Also,
The load command "LD (_DEBUF), DE" is used to save the information in the DE register of the primary CPU 63 to the DE buffer set in the work area 223 for non-specific control (step S3904). The load command "LD (_HLBUF), HL" is used to save the information in the HL register of the primary CPU 63 to the HL buffer set in the work area 223 for non-specific control (step S3905). The load command "LD (_IXBUF), IX" is used to save the information in the IX register of the primary CPU 63 to the IX buffer set in the work area 223 for non-specific control (step S3906). The load command "LD (_IYBUF), IY" is used to save the information in the IY register of the primary CPU 63 to the IY buffer set in the work area 223 for non-specific control (step S3907).

In addition to the flag register already described, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S3902 to S3907, the information in some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the corresponding buffer in the non-specific control work area 223. Note that the information capacity of the WA register, BC register, DE register, HL register, IX register, and IY register is each 2 bytes.

The WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the check process (step S3908), which is a process corresponding to non-specific control. By saving the information set in these registers to the work area 223 for non-specific control prior to executing the check process (step S3908), it is possible to save the information in these registers used during specific control before non-specific control is started. Therefore, even if these registers are overwritten during non-specific control, by restoring the information saved in the work area 223 for non-specific control to these registers when non-specific control is terminated, it is possible to restore the state of these registers to the state corresponding to specific control before non-specific control was executed.

In addition, rather than saving all information from the various general-purpose registers, auxiliary registers, and index registers to the work area 223 for non-specific control, information from the WA register, BC register, DE register, HL register, IX register, and IY register to be used in the check process, which is a process corresponding to non-specific control, is selectively saved to the work area 223 for non-specific control. This reduces the capacity required to save register information in the work area 223 for non-specific control. This makes it possible to save the above-mentioned register information while ensuring a large capacity for the work area 223 for non-specific control that is available for the check process. Naturally, for the various general-purpose registers, auxiliary registers, and index registers in the main CPU 63 other than the WA register, BC register, DE register, HL register, IX register, and IY register, information set before the process corresponding to non-specific control is started is stored and retained until the process corresponding to non-specific control ends and the process corresponding to specific control resumes.

In addition, by saving register information in the work area 223 for non-specific control rather than in the stack area 224 for non-specific control, it is possible to reduce the capacity of the stack area 224 for non-specific control. Furthermore, when using the stack area 224 for non-specific control, as already explained, the order in which information is written is such that later information is read first. Therefore, if the order in which information is read is shifted due to some kind of noise or other cause, all of the information read after that will be restored to different registers. The probability of this happening increases as the amount of information saved in the stack area 224 for non-specific control increases. In contrast, by saving register information in the work area 223 for non-specific control, it is possible to prevent the above-mentioned happening even when there is a lot of information to save.

After steps S3902 to S3907 are executed, check processing is executed (step S3908). When check processing is executed, a subroutine program corresponding to the check processing set in the non-specific control program is executed, and when this subroutine program is executed, information for specifying the return address of the management execution processing after execution of the check processing is written to the non-specific control stack area 224 by a push command. Then, when the check processing is completed, information for specifying the return address is read by a pop command, and processing returns to the management execution processing program indicated by the return address. Details of the check processing will be explained later.

After the check process is executed, a load command is issued to set Y(r+α) in the stack pointer of the primary CPU 63 as a fixed address for when returning to specific control, as "LD SP, Y(r+α)" (step S3909). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

The amount of information stored in the stack area 222 for specific control immediately before the subroutine for the management execution process is executed in step S3803 of the management process (Figure 70) is always constant, and accordingly, the stack pointer information (i.e., the value of the stack pointer) of the main CPU 63 at that timing is constant. In this case, examples of information stored in the stack area 222 for specific control include the return address information for the management process (Figure 70) after the management execution process (Figure 71) has ended, and the return address information for the timer interrupt process (Figure 69) after the management process (Figure 70) has ended. The fixed information in the stack pointer is Y(r+α). Therefore, when the check process, which is a process corresponding to non-specific control, ends and returns to the process corresponding to specific control, the fixed information Y(r+α) is set in the stack pointer of the main CPU 63, thereby enabling the stack pointer information to be restored to the information immediately before the process corresponding to non-specific control was started. By setting fixed information in the stack pointer in this way, the stack pointer information is restored to the information immediately before processing corresponding to non-specific control is started, eliminating the need to save the stack pointer information of the main CPU 63 corresponding to specific control to the main RAM 65 before starting processing corresponding to non-specific control. This makes it possible to reduce the processing load and eliminates the need to reserve an area in the main RAM 65 for saving the information.

Then, the information saved in the WA buffer of the work area 223 for non-specific control is overwritten in the WA register of the primary CPU 63 by a load command as "LD WA, (_WABUF)" (step S3910). The information saved in the BC buffer of the work area 223 for non-specific control is overwritten in the BC register of the primary CPU 63 by a load command as "LD BC, (_BCBUF)" (step S3911). The information saved in the DE buffer of the work area 223 for non-specific control is overwritten in the DE register of the primary CPU 63 by a load command as "LD DE, (_DEBUF)" (step S3912). The information saved in the HL buffer of the work area 223 for non-specific control is overwritten in the HL register of the primary CPU 63 by a load command as "LD HL, (_HLBUF)" (step S3913). Furthermore, the load command "LD IX, (_IXBUF)" overwrites the IX register of the primary CPU 63 with the information saved in the IX buffer of the work area 223 for non-specific control (step S3914). The load command "LD IY, (_IYBUF)" overwrites the IY register of the primary CPU 63 with the information saved in the IY buffer of the work area 223 for non-specific control (step S3915). By executing the processes of steps S3910 to S3915, it is possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the primary CPU 63 to the information corresponding to specific control that was present immediately before the process corresponding to non-specific control was started.

Here, when processing corresponding to non-specific control is executed, the information stored in the flag register and various registers of the main CPU 63 is not saved to the main RAM 65 when processing corresponding to specific control is resumed. This eliminates the need to reserve memory areas for saving the above information in the work area 221 for specific control and the stack area 222 for specific control.

In addition, the information stored in the flag register and various registers of the main CPU 63 when processing corresponding to non-specific control is executed is information that will not be used when processing corresponding to non-specific control is restarted after returning to processing corresponding to specific control. In other words, the information required for multiple executions of processing corresponding to non-specific control that are executed with processing corresponding to specific control in between is stored in the work area 223 for non-specific control or the stack area 224 for non-specific control, and is not stored in the flag register and various registers of the main CPU 63. Therefore, even if the information stored in the flag register and various registers of the main CPU 63 is not saved to the main RAM 65 when processing corresponding to non-specific control is executed, there will be no problems in executing processing corresponding to non-specific control.

Next, we will explain the check processing that is executed when a subroutine program is called in step S3908. This check processing executes processing for collecting gaming history information, processing for deriving gaming history management results, and processing for notifying those management results. In other words, the processing for collecting gaming history information, processing for deriving gaming history management results, and processing for notifying those management results are executed as processing corresponding to non-specific control.

Before explaining the check process, we will explain the contents of the various areas 231-234 of the non-specific control work area 223 used to manage game history. Figure 72 is an explanatory diagram illustrating the various areas 231-234 of the non-specific control work area 223 used to manage game history.

The non-specific control work area 223 is provided with a normal counter area 231, an open/close execution mode counter area 232, and a high-frequency support mode counter area 233. Each of these areas 231-233 is provided with a general winning counter 231a, 232a, 233a, a special call winning counter 231b, 232b, 233b, a first operation counter 231c, 232c, 233c, a second operation counter 231d, 232d, 233d, and an out counter 231e, 232e, 233e. The general winning counters 231a, 232a, 233a are counters for counting the number of game balls that enter the general winning port 31 from a predetermined measurement start trigger. Special electric winning counters 231b, 232b, 233b are counters for counting the number of game balls that have entered the special electric winning device 32 from a predetermined measurement start trigger. First operation counters 231c, 232c, 233c are counters for counting the number of game balls that have entered the first operation port 33 from a predetermined measurement start trigger. Second operation counters 231d, 232d, 233d are counters for counting the number of game balls that have entered the second operation port 34 from a predetermined measurement start trigger. Out counters 231e, 232e, 233e are counters for counting the number of game balls that have entered the out port 24a from a predetermined measurement start trigger.

The counters 231a-231e in the normal counter area 231 are used to count the number of game balls that have entered the target ball entry areas 24a, 31-34 when the front door frame 14 is closed and the machine is not in either the open/close execution mode or the high-frequency support mode. The counters 232a-232e in the open/close execution mode counter area 232 are used to count the number of game balls that have entered the target ball entry areas 24a, 31-34 when the front door frame 14 is closed and the machine is in the open/close execution mode. The counters 233a-233e in the high-frequency support mode counter area 233 are used to count the number of game balls that have entered the target ball entry areas 24a, 31-34 when the front door frame 14 is closed and the machine is in the high-frequency support mode.

The reason why the situation where the front door frame 14 is in an open state is not included in the measurement is to exclude from the measurement the number of balls that enter the ball entry areas 24a, 31-34 by hand when the front door frame 14 is open. However, this is not limited to this, and the situation where the front door frame 14 is in an open state may also be included in the measurement, just like the situation where the front door frame 14 is in a closed state.

In addition to the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, the non-specific control work area 223 also has a calculation result storage area 234. The calculation result storage area 234 is an area for storing information on the game history management results calculated using the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233. The game history management result information stored in the calculation result storage area 234 is stored and retained until newly calculated game history management result information is overwritten by the newly calculated information.

Figure 73 is a flowchart showing the check processing executed when a subroutine program is called in step S3908. Note that steps S4001 to S4008 of the check processing, including the subroutine processing, are executed by the main CPU 63 using the non-specific control program and non-specific control data. When subroutine processing is executed, the return address information after execution of the subroutine processing is written to the storage area in the non-specific control stack area 224 corresponding to the current stack pointer value of the main CPU 63, and the stack pointer value is updated to the address information of the storage area to be stored in the next order. When subroutine processing is completed, the return address information is read from the storage area corresponding to the previous value of the current stack pointer of the main CPU 63, and the program corresponding to the return address information is returned to, and the stack pointer value is updated to the address information of the storage area from which the return address information was read.

In the check process, if the front door frame 14 is in the open state (step S4001: YES), the normal ball entry management process (step S4004), the ball entry management process in the open/close execution mode (step S4005), and the ball entry management process in the high-frequency support mode (step S4006) are not executed, and the result calculation process (step S4007) and display process (step S4008) described below are executed. Since the game area PA is formed by the space partitioned front and back by the back surface of the window panel 52 provided in the front door frame 14 and the front surface of the game board 24, when the front door frame 14 is in the open state, the game area PA is opened forward, and even if a game ball is launched toward the game area PA in this situation, the game ball will not be able to flow down the game area PA normally. Furthermore, when game balls enter the ball entry sections 24a, 31-34 while the front door frame 14 is open, this occurs when the front door frame 14 is left open by the amusement hall manager for maintenance or to resolve a malfunction, resulting in game balls entering the hall as a result of care and other such actions. Since such game balls do not enter the hall during legitimate game play, they do not need to be managed. Therefore, in the check process, none of the steps S4004 to S4006 are executed when the front door frame 14 is open, as described above.

If the front door frame 14 is closed and is not in either the opening/closing execution mode or the high-frequency support mode (steps S4001 to S4003: NO), normal goal entry management processing is executed (step S4004). Also, if the front door frame 14 is closed and in the opening/closing execution mode (step S4001: NO, step S4002: YES), goal entry management processing during the opening/closing execution mode is executed (step S4005). Also, if the front door frame 14 is closed and in the high-frequency support mode (step S4001: NO, step S4003: YES), goal entry management processing during the high-frequency support mode is executed (step S4006).

Figure 74 is a flowchart showing the normal goal entry management process in step S4004.

If it is determined that one game ball has been detected by the first prize opening detection sensor 42a (step S4101: YES), i.e., if it is confirmed that the signal received from the first prize opening detection sensor 42a has switched from LOW to HIGH, if it is determined that one game ball has been detected by the second prize opening detection sensor 43a (step S4103: YES), i.e., if it is confirmed that the signal received from the second prize opening detection sensor 43a has switched from LOW to HIGH, or if it is determined that one game ball has been detected by the third prize opening detection sensor 44a (step S4105: YES), i.e., if it is confirmed that the signal received from the third prize opening detection sensor 44a has switched from LOW to HIGH, the value of the normal general prize winning counter 231a is incremented by 1 (steps S4102, S4104, S4106).

If the ball entry management process is in the open/close execution mode, the value of the general winning counter 232a for the open/close execution mode is incremented by 1 as the process corresponding to steps S4102, S4104, and S4106. If the ball entry management process is in the high frequency support mode, the value of the general winning counter 233a for the high frequency support mode is incremented by 1 as the process corresponding to steps S4102, S4104, and S4106. Also, in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69), which is executed as a process corresponding to specific control, the detection results of the first to third winning slot detection sensors 42a to 44a are monitored, and if it is determined that one game ball has been detected by any of the first to third winning slot detection sensors 42a to 44a, a process is executed to pay out the number of game balls corresponding to the general winning slot 31.

If it is determined that one game ball has been detected by the special electric detection sensor 45a (step S4107: YES), that is, if it is confirmed that the signal received from the special electric detection sensor 45a has switched from LOW level to HIGH level, the value of the normal special electric winning counter 231b is incremented by 1 (step S4108).

If the ball entry management process is during the open/close execution mode, the value of the special electric winning counter 232b for the open/close execution mode is incremented by 1 as the process corresponding to step S4108, and if the ball entry management process is during the high frequency support mode, the value of the special electric winning counter 233b for the high frequency support mode is incremented by 1 as the process corresponding to step S4108. The detection results of the special electric detection sensor 45a are also monitored in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69), which is executed as a process corresponding to specific control, and if it is determined that one game ball has been detected by the special electric detection sensor 45a, a process is executed to pay out the number of game balls corresponding to the special electric winning device 32, and a process is executed to identify the trigger for ending the round of play.

If it is determined that one game ball has been detected by the first actuation port detection sensor 46a (step S4109: YES), that is, if it is confirmed that the signal received from the first actuation port detection sensor 46a has switched from LOW level to HIGH level, the value of the normal first actuation counter 231c is incremented by 1 (step S4110).

If the ball entry management process is during the open/close execution mode, the value of the first operation counter 232c for the open/close execution mode is incremented by 1 as the process corresponding to step S4110, and if the ball entry management process is during the high frequency support mode, the value of the first operation counter 233c for the high frequency support mode is incremented by 1 as the process corresponding to step S4110. The detection result of the first operation port detection sensor 46a is also monitored in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69), which is executed as the process corresponding to specific control. If it is determined that one game ball has been detected by the first operation port detection sensor 46a, a process is executed to pay out the number of game balls corresponding to the first operation port 33, and a process is executed to identify the trigger for obtaining reserved information for the special design.

If it is determined that one game ball has been detected by the second actuation port detection sensor 47a (step S4111: YES), that is, if it is confirmed that the signal received from the second actuation port detection sensor 47a has switched from LOW level to HIGH level, the value of the normal second actuation counter 231d is incremented by 1 (step S4112).

If the ball entry management process is during the open/close execution mode, the value of the second operation counter 232d for the open/close execution mode is incremented by 1 as the process corresponding to step S4112, and if the ball entry management process is during the high frequency support mode, the value of the second operation counter 233d for the high frequency support mode is incremented by 1 as the process corresponding to step S4112. The detection result of the second operation port detection sensor 47a is also monitored in the ball entry detection process (step S3709) of the timer interrupt process (FIG. 69), which is executed as the process corresponding to specific control. If it is determined that one game ball has been detected by the second operation port detection sensor 47a, a process is executed to pay out the number of game balls corresponding to the second operation port 34, and a process is executed to identify the trigger for obtaining reserved information for the special design.

If it is determined that one game ball has been detected by the outlet detection sensor 48a (step S4113: YES), that is, if it is confirmed that the signal received from the outlet detection sensor 48a has switched from LOW level to HIGH level, the value of the normal out counter 231e is incremented by 1 (step S4114).

If the goal entry management process is in the open/close execution mode, the value of the out counter 232e for the open/close execution mode is incremented by 1 as a process corresponding to step S4114, and if the goal entry management process is in the high frequency support mode, the value of the out counter 233e for the high frequency support mode is incremented by 1 as a process corresponding to step S4114. Furthermore, the detection results of the out port detection sensor 48a are not monitored in the goal entry detection process (step S3709) of the timer interrupt process (Figure 69), which is executed as a process corresponding to specific control.

By executing the processing of steps S4004 to S4006 as described above, the number of game balls entering the general winning port 31 is counted using the general winning counters 231a, 232a, and 233a, the number of game balls entering the special winning device 32 is counted using the special winning counters 231b, 232b, and 233b, the number of game balls entering the first operating port 33 is counted using the first operating counters 231c, 232c, and 233c, the number of game balls entering the second operating port 34 is counted using the second operating counters 231d, 232d, and 233d, and the number of game balls entering the outlet 24a is counted using the outlet counters 231e, 232e, and 233e. This enables the main CPU 63 to grasp the ball entry history for each ball entry section 24a, 31-34. Furthermore, by separately setting up the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, the main CPU 63 can grasp the history of balls entering each of the ball entry sections 24a, 31-34, distinguishing between situations where the mode is neither open/close execution mode nor high-frequency support mode, situations where the mode is open/close execution mode, and situations where the mode is high-frequency support mode.

Returning to the explanation of the check process (Figure 73), if a positive judgment is made in step S4001, if the processing of step S4004 is executed, if the processing of step S4005 is executed, or if the processing of step S4006 is executed, a result calculation process is executed in step S4007, and a display process is executed in step S4008.

Figure 75 is a flowchart showing the result calculation process of step S4007.

First, it is determined whether the management start flag set in the non-specific control work area 223 is set to "1" (step S4201). The management start flag is a flag used by the main CPU 63 to determine whether or not game history collection is required to calculate game history management results. In this embodiment, when the supply of operating power to the pachinko machine 10 is initiated for the first time after the pachinko machine 10 is manufactured (i.e., when the supply of operating power to the MPU 62 is initiated), game history collection for calculating game history management results is not performed until the total number of game balls discharged from the play area PA reaches or exceeds the number corresponding to the management start reference value. When the total number of game balls discharged from the play area PA reaches or exceeds the number corresponding to the management start reference value, game history collection for calculating game history management results is performed. During the shipping stage of the pachinko machine 10, an operation check of the pachinko machine 10 may be performed prior to shipping. During this check, game balls are placed in each ball entry section and the subsequent operation is checked. In response to this, by not collecting game history for calculating game history management results until the total number of game balls discharged from the game area PA after the supply of operating power to the pachinko machine 10 begins reaches or exceeds the management start reference value, it is possible to prevent ball entry results, etc., during the operation check described above from being collected as game history for calculating game history management results.

Here, when the supply of operating power to the pachinko machine 10 begins for the first time after the pachinko machine 10 is manufactured (i.e., when the supply of operating power to the MPU 62 begins), the value of the management start flag is set to "0." In this case, the values of the counters 231a-231e in the normal counter area 231, the values of the counters 232a-232e in the open/close execution mode counter area 232, and the values of the counters 233a-233e in the high-frequency support mode counter area 233 are also set to "0." On the other hand, if the supply of operating power to the pachinko machine 10 is stopped when the value of the management start flag is "1," and then the supply of operating power to the pachinko machine 10 is started while backup power is being supplied to the main RAM 65, the value of the management start flag will remain at "1." In this case, the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high-frequency support mode counter area 233 are maintained in the state they were in before the supply of operating power to the pachinko machine 10 was stopped. With the above configuration, when the value of the management start flag is "0", the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high-frequency support mode counter area 233 also become "0".

Incidentally, when the main RAM 65 is cleared in step S105 or step S117 of the main processing (Figure 9), the work area 221 for specific control and the stack area 222 for specific control are the targets of the clearing process, and the work area 223 for non-specific control and the stack area 224 for non-specific control are excluded from the clearing process. This prevents the amusement hall manager from intentionally clearing the work area 223 for non-specific control and the stack area 224 for non-specific control to "0".

The main CPU 63 may also be configured to check whether an abnormality has occurred in the non-specific control work area 223 and the non-specific control stack area 224 during the timer interrupt processing (Figure 69) described below, and if an abnormality is confirmed, the non-specific control work area 223 and the non-specific control stack area 224 are cleared to "0." This makes it possible to initialize the non-specific control work area 223 and the non-specific control stack area 224 if an abnormality occurs in them. In this configuration, if an abnormality occurs in the non-specific control work area 223, the non-specific control work area 223 may be cleared to "0" without clearing the non-specific control stack area 224 to "0," and if an abnormality occurs in the non-specific control stack area 224, the non-specific control stack area 224 may be cleared to "0" without clearing the non-specific control work area 223 to "0." Furthermore, even if an abnormality occurs in the non-specific control work area 223 and the non-specific control stack area 224, the calculation result storage area 234 may be excluded from being cleared to "0".

If the determination in step S4201 is negative, the total number is calculated by adding up the values of the counters 231a-231e in the normal counter area 231, the values of the counters 232a-232e in the open/close execution mode counter area 232, and the values of the counters 233a-233e in the high-frequency support mode counter area 233 (step S4202). It is then determined whether the calculated total number is greater than the management start reference value of "300" (step S4203).

If a positive judgment is made in step S4203, the management start flag for the non-specific control work area 223 is set to "1" (step S4204). Furthermore, the counters 231a-231e in the normal counter area 231, the counters 232a-232e in the open/close execution mode counter area 232, and the counters 233a-233e in the high-frequency support mode counter area 233 are all cleared to "0" (step S4205). This erases all game history information collected after the supply of operating power to the pachinko machine 10 has started (i.e., after the supply of operating power to the MPU 62 has started) and the total number of game balls discharged from the game area PA reaches or exceeds the management start reference value. This prevents the collection of game history information for calculating the game history management results from being executed until the total number of game balls discharged from the game area PA reaches or exceeds the management start reference value after the supply of operating power to the pachinko machine 10 has started.

If a positive determination is made in step S4201, the total number is calculated in the same manner as in step S4202 (step S4206). That is, the total number is calculated by adding up the values of the counters 231a to 231e in the normal counter area 231, the values of the counters 232a to 232e in the open/close execution mode counter area 232, and the values of the counters 233a to 233e in the high frequency support mode counter area 233. Then, it is determined whether the calculated total number is equal to or greater than the calculation reference number of "6000" (step S4207).

If the determination in step S4207 is affirmative, calculation processing of various parameters is performed (step S4208). Specifically, assuming that the values of the various counters 231a to 231e in the normal counter area 231 are K61 to K65, the values of the various counters 232a to 232e in the open/close execution mode counter area 232 are K71 to K75, and the values of the various counters 233a to 233e in the high frequency support mode counter area 233 are K81 to K85, the following 61st to 68th parameters are calculated.
61st parameter: total number of game balls paid out ("K61 + K71 + K81" x "number of prize balls for winning at the general winning port 31" + "K62 + K72 + K82" x "number of prize balls for winning at the special winning device 32" + "K63 + K73 + K83" x "number of prize balls for winning at the first operating port 33" + "K64 + K74 + K84" x "number of prize balls for winning at the second operating port 34") / total number of game balls discharged from the game area PA (K61 + K62 + K63 + K64 + K65 + K71 + K72 + K73 + K74 + K75 + K81 + K82 + K83 + K84 + K85) ratio; 62nd parameter: total number of game balls paid out during normal times (K61 x "number of prize balls for winning at the general winning port 31" + K62 x "number of prize balls for winning at the special electric winning device 32" + K63 x "number of prize balls for winning at the first operating port 33" + K64 x "number of prize balls for winning at the second operating port 34" ) / The ratio of the total number of game balls discharged from the skill area PA during normal times (K61 + K62 + K63 + K64 + K65) 63rd parameter: The total number of game balls paid out during the opening and closing execution mode (K71 × “Number of prize balls for winning the general winning port 31” + K72 × “Number of prize balls for winning the special winning device 32” + K73 × “Number of prize balls for winning the first operating port 33” + K74 × “Number of prize balls for winning the second operating port 34”) / The ratio of the total number of game balls (K71 + K72 + K73 + K74 + K75) discharged from the skill area PA in the open/close execution mode. The 64th parameter: The total number of game balls paid out in the high frequency support mode (K81 x "number of prize balls for winning the general winning port 31" + K82 x "number of prize balls for winning the special winning device 32" + K83 x "number of prize balls for winning the first operating port 33" + K84 x "number of prize balls for winning the second operating port 34" 65th parameter: the total number of game balls entering the general winning port 31 (K61 + K71 + K81) / the ratio of the total number of game balls ejected from the game area PA (K61 + K62 + K63 + K64 + K65 + K71 + K72 + K73 + K74 + K75 + K81 + K82 + K83 + K84 + K85) 66th parameter: The ratio of the total number of game balls entering the first operating port 33 (K63 + K73 + K83) / the total number of game balls discharged from the game area PA (K61 + K62 + K63 + K64 + K65 + K71 + K72 + K73 + K74 + K75 + K81 + K82 + K83 + K84 + K85) 67th parameter: ("K62 + K72 + K82" x "number of prize balls for winning into the special electric winning device 32" + "K64 + K74 + K84" x "second Ratio of "K61 + K71 + K81" x "number of prize balls for winning at the general prize winning port 31" + "K62 + K72 + K82" x "number of prize balls for winning at the special electric prize winning device 32" + "K63 + K73 + K83" x "number of prize balls for winning at the first prize winning port 33" + "K64 + K74 + K84" x "number of prize balls for winning at the second prize winning port 34"), 68th parameter: "K6 2 + K72 + K82 × "number of prize balls for winning the special electric winning device 32" / total number of game balls paid out ("K61 + K71 + K81" × "number of prize balls for winning the general winning port 31" + "K62 + K72 + K82" × "number of prize balls for winning the special electric winning device 32" + "K63 + K73 + K83" × "number of prize balls for winning the first operating port 33" + "K64 + K74 + K84" × "number of prize balls for winning the second operating port 34") ratio. Then, the 61st to 68th parameters calculated in step S4208 are overwritten in the calculation result storage area 234 (step S4209). In this case, the 61st to 68th parameters of the calculation results from the previous processing that were already stored in the calculation result storage area 234 are erased. Furthermore, even when the supply of operating power to the pachinko machine 10 is stopped, backup power is supplied to the main RAM 65, so if the backup power is being supplied, the calculation result memory area 234 stores information on parameters 61 to 68 calculated before the supply of operating power to the pachinko machine 10 is stopped, even immediately after the supply of operating power to the pachinko machine 10 starts.

Then, all counters 231a-231e in the normal counter area 231, all counters 232a-232e in the open/close execution mode counter area 232, and all counters 233a-233e in the high frequency support mode counter area 233 are cleared to "0" (step S4210). This allows the game history information to be temporarily erased at that point, triggered by the calculation of parameters 61-68.

Incidentally, immediately after the management start flag is set to "1", steps S4208 to S4210 are executed if the total number of game balls discharged from the play area PA is equal to or greater than the calculation reference number minus the management start reference value, and thereafter steps S4208 to S4210 may be executed if the total number of game balls discharged from the play area PA is equal to or greater than the calculation reference number.

Figure 76 is a flowchart showing the display processing of step S4008 in the check processing (Figure 73).

First, the value of the update timing counter provided in the work area 223 for non-specific control is decremented by 1 (step S4301). The update timing counter is a counter used by the main CPU 63 to determine when it is time to update the display contents of the game history management results on the first to third notification display devices 69a to 69c. The main CPU 63 notifies the calculation results of the 61st to 68th parameters by controlling the display of the first to third notification display devices 69a to 69c. In this case, the first notification display device 69a displays information corresponding to the type of parameter being notified. Furthermore, of the value obtained by multiplying the parameter being notified by 100, the digit corresponding to the tens digit is displayed on the second notification display device 69b, and the digit corresponding to the ones digit is displayed on the third notification display device 69c. The first to third notification display devices 69a to 69c sequentially switch displays corresponding to the calculation results of the 61st to 68th parameters in a predetermined order, and after the calculation result of the 68th parameter, which is the last parameter to be displayed, is displayed, the calculation result of the 61st parameter, which is the first parameter to be displayed, is displayed. In this case, the calculation result of one parameter is continuously displayed for 10 seconds.

The main CPU 63 has a minimum calculation cycle of 60 minutes for the above parameters 61 to 68. However, there are eight parameters 61 to 68, and the calculation results for one parameter are continuously displayed for 10 seconds. Therefore, parameters 61 to 68 calculated by the main CPU 63 are displayed at least once on the first to third alarm display devices 69a to 69c.

When the processing of step S4301 is executed, it is determined whether the value of the update timing counter after subtracting 1 is "0" to determine whether it is time to update the display content of the first to third alarm display devices 69a to 69c (step S4302). If a positive determination is made in step S4302, the value of the display target counter provided in the non-specific control work area 223 is incremented by 1 (step S4303). Then, if the value of the display target counter after incrementing 1 exceeds the maximum value of "7" (step S4304: YES), the value of the display target counter is cleared to "0" (step S4305).

The display target counter is a counter that allows the main CPU 63 to identify the type of parameter to be displayed on the first to third alarm display devices 69a to 69c. There is a one-to-one correspondence between the above parameters 61 to 68 and the possible values of the display target counter, "0" to "7." For example, when the value of the display target counter is "0," parameter 61, which is the first display target, is displayed on the first to third alarm display devices 69a to 69c; when the value of the display target counter is "7," parameter 68, which is the last display target, is displayed on the first to third alarm display devices 69a to 69c.

If a negative judgment is made in step S4304, or if the processing of step S4305 is executed, the display of the first alarm display device 69a is controlled so that information corresponding to the type of parameter corresponding to the value of the counter to be displayed is displayed (step S4306). In addition, the parameter corresponding to the value of the counter to be displayed is read from the calculation result storage area 234, and the read parameter is multiplied by 100, so that the number corresponding to the tens digit is displayed on the second alarm display device 69b and the number corresponding to the ones digit is displayed on the third alarm display device 69c (step S4307).

Here, a display IC is provided corresponding to each of the first to third alarm display devices 69a to 69c. In step S4306, the main CPU 63 outputs display data to the display IC corresponding to the first alarm display device 69a, and in step S4307, the main CPU 63 outputs display data to the display IC corresponding to the second alarm display device 69b and the display IC corresponding to the third alarm display device 69c. These display ICs can store and retain display data when operating power is supplied, and cause the corresponding alarm display devices 69a to 69c to continuously display the display content corresponding to the stored display data. Then, when the display data is changed by the main CPU 63, the display of the alarm display devices 69a to 69c is changed to the display content corresponding to the changed display data. As a result, even after the management execution process (Figure 71), which is a process corresponding to non-specific control, ends and returns to the process corresponding to specific control, the first to third notification display devices 69a to 69c continue to display the display data set during the execution status of the process corresponding to non-specific control.

Then, the update timing counter in the non-specific control work area 223 is set to a value corresponding to 10 seconds as the value corresponding to the next update timing (step S4308).

By executing the display processing as described above, when the supply of operating power to the main CPU 63 has begun, the game history management results are displayed on the first to third notification display devices 69a to 69c. The game history management results are displayed regardless of whether play is continuing or not, and regardless of whether the gaming machine main body 12 has been opened relative to the outer frame 11 and the main control device 60 is visible from the front of the pachinko machine 10. By executing display control on the first to third notification display devices 69a to 69c in this way regardless of the game situation or the state of the pachinko machine 10, it is possible to simplify the processing configuration for display control on the first to third notification display devices 69a to 69c.

The present embodiment described above provides the following excellent effects:

The main RAM 65 is provided with a work area 221 and stack area 222 for specific control, and a work area 223 and stack area 224 for non-specific control. The work area 221 and stack area 222 for specific control are capable of storing and reading information when processing corresponding to specific control is executed by the main CPU 63 using a program for specific control and data for specific control, whereas the work area 221 and stack area 222 for specific control are capable of reading information but are unable to store information when processing corresponding to non-specific control is executed by the main CPU 63 using a program for non-specific control and data for non-specific control. The work area 223 and stack area 224 for non-specific control are capable of storing and reading information when processing corresponding to non-specific control is executed by the main CPU 63, whereas the work area 223 and stack area 224 for non-specific control are capable of storing and reading information when processing corresponding to non-specific control is executed by the main CPU 63, whereas the work area 221 and stack area 222 for non-specific control are capable of reading information but are unable to store information when processing corresponding to specific control is executed by the main CPU 63. This allows the work area 221 for specific control and the stack area 222 for specific control to be treated as dedicated storage areas for processing corresponding to specific control, while the work area 223 for non-specific control and the stack area 224 for non-specific control can be treated as dedicated storage areas for processing corresponding to non-specific control. This makes it possible to clearly differentiate the storage destinations of information in the main RAM 65 for processing corresponding to specific control and processing corresponding to non-specific control. This makes it possible to prevent information used in processing corresponding to specific control or processing corresponding to non-specific control from being erased when the other processing is executed.

Processing corresponding to specific control includes processing for controlling the progress of the game, while processing corresponding to non-specific control includes processing for managing the game history. As described above, the work area 221 for specific control and the stack area 222 for specific control are treated as storage areas dedicated to processing corresponding to specific control, while the work area 223 for non-specific control and the stack area 224 for non-specific control are treated as storage areas dedicated to processing corresponding to non-specific control. This makes it possible to prevent information used in processing for managing the game history, such as information stored in the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the calculation result storage area 234, from being overwritten when processing for controlling the progress of the game is executed.

The main RAM 65 is provided with a normal counter area 231, an open/close execution mode counter area 232, a high-frequency support mode counter area 233, and a calculation result storage area 234, which store information for managing game history. This allows the main CPU 63 to complete the processing for managing game history. It also prevents unauthorized access to or modification of game history information and information on various parameters calculated using that game history information.

When the situation changes from one in which processing corresponding to specific control is being executed to one in which processing corresponding to non-specific control is being executed, or when the situation changes to one in which processing corresponding to non-specific control is being executed, the information in the various registers of the main CPU 63 is saved to the main RAM 65. This makes it possible to prevent the information stored in the various registers of the main CPU 63 from being overwritten when processing corresponding to specific control is executed when processing corresponding to non-specific control is executed. Furthermore, when or after processing corresponding to non-specific control is terminated, the information saved in the main RAM 65 is restored to the various registers of the main CPU 63. This makes it possible, when processing corresponding to non-specific control is terminated, to execute processing corresponding to specific control from the state of the various registers of the main CPU 63 before the execution of processing corresponding to the non-specific control.

When the system changes from a situation where processing corresponding to specific control is being executed to a situation where processing corresponding to non-specific control is being executed, or when the system changes to a situation where processing corresponding to non-specific control is being executed, information from some of the various registers in the main CPU 63 is saved to the main RAM 65. This makes it possible to reduce the storage capacity required in the main RAM 65 to save information from the registers of the main CPU 63.

When the situation changes from one in which processing corresponding to specific control is being performed to one in which processing corresponding to non-specific control is being performed, or when the situation changes to one in which processing corresponding to non-specific control is being performed, information from the various registers of the main CPU 63 that are the target of information storage in the processing corresponding to non-specific control is saved to the main RAM 65. This makes it possible to resume processing corresponding to specific control from the state of the main CPU 63 registers before the processing corresponding to non-specific control is completed, while also reducing the storage capacity required in the main RAM 65 to save the information from the main CPU 63 registers.

When processing corresponding to non-specific control is initiated, the information in the flag register of the main CPU 63 is saved to the stack area 222 for specific control during processing corresponding to specific control, and the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the work area 223 for non-specific control during processing corresponding to non-specific control. This makes it possible to save the information at a time that is convenient for the information stored in the various registers of the main CPU 63, and also makes it possible to distribute the processing for saving information between processing corresponding to specific control and processing corresponding to non-specific control.

The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, input/output instructions, etc. In this case, the flag register information is saved to the stack area 222 for specific control during processing corresponding to specific control before processing corresponding to non-specific control begins. This makes it possible to save the flag register information in its state before it changes after calling a subroutine corresponding to non-specific control or starting the subroutine in the stack area 222 for specific control.

By saving the information in the WA register, BC register, DE register, HL register, IX register, and IY register in the non-specific control work area 223 rather than in the non-specific control stack area 224, it is possible to reduce the capacity of the non-specific control stack area 224. Furthermore, when using the non-specific control stack area 224, the order in which information is written is such that later information is read first. Therefore, if the order in which information is read is shifted due to some kind of noise or other cause, all of the information read after that will be restored to different registers. The probability of this happening increases as the amount of information saved in the non-specific control stack area 224 increases. In contrast, by saving register information in the non-specific control work area 223, it is possible to prevent the above-mentioned happening even when there is a lot of information to save.

When the state where processing corresponding to specific control is executed changes to the state where processing corresponding to non-specific control is executed, or when the state where processing corresponding to non-specific control is executed changes, the stack pointer information of the main CPU 63 becomes fixed information, and the stack pointer information is not saved to the main RAM 65 when processing corresponding to non-specific control is started. This eliminates the need to reserve capacity in the main RAM 65 for saving stack pointer information, thereby making it possible to reduce the storage capacity of the main RAM 65. Furthermore, even in this configuration where stack pointer information is not saved, when the state where processing corresponding to specific control is executed changes to the state where processing corresponding to non-specific control is executed, or when the state where processing corresponding to non-specific control is executed changes, the stack pointer information of the main CPU 63 becomes fixed information. Therefore, even without saving the stack pointer information as described above, when processing corresponding to non-specific control is completed, it is possible to restore the stack pointer information to the state before processing corresponding to the non-specific control was started.

In addition, while the configuration is such that the information in the flag register of the main CPU 63 is saved to the main RAM 65 during processing corresponding to specific control when processing corresponding to non-specific control is executed, this is not limited to this, and the information in the flag register may also be saved to the main RAM 65 during processing corresponding to non-specific control. Also, although the configuration is such that the information is restored to the flag register of the main CPU 63 during processing corresponding to specific control after processing corresponding to non-specific control has ended, this is not limited to this, and the information may also be restored to the flag register during processing corresponding to non-specific control.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the main RAM 65 during processing corresponding to non-specific control after processing corresponding to the non-specific control has begun, but this is not limited to this, and the information in these registers may be saved to the main RAM 65 during processing corresponding to specific control. In addition, when processing corresponding to non-specific control ends, the information is restored to each of the above registers during processing corresponding to non-specific control, but this is not limited to this, and the information may be restored to each of the above registers during processing corresponding to specific control after processing corresponding to non-specific control ends.

<16th embodiment>
In this embodiment, the processing configuration of the management process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 77 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S4401 to S4405 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 69) (step S4401). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, using the load command "LD (_PSWBUF), PSW," the flag register information of the main CPU 63 is saved to the PSW buffer set in the specific control work area 221 (step S4402). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the flag register information changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process is started, it is possible to save the flag register information in the specific control work area 221 in its state before it changes after the subroutine is called or started.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S4403). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

When the management execution process is completed and the management process program is resumed, the flag register information saved in the PSW buffer in the specific control work area 221 in step S4402 is restored to the flag register of the primary CPU 63 by a load command using "LD PSW, (_PSWBUF)" (step S4404). This restores the flag register information of the primary CPU 63 to the information at the time step S4402 was last executed. In other words, the flag register information of the primary CPU 63 is restored to the information required to execute specific control.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S4405). This allows new execution of timer interrupt processing.

With the above configuration, the information in the flag register of the main CPU 63 immediately before switching from specific control to non-specific control is saved in the work area 221 for specific control rather than the stack area 222 for specific control. This makes it possible to save the information in the flag register while minimizing the capacity of the stack area 222 for specific control.

Note that while the PSW buffer in the work area 221 for specific control is secured as a dedicated area, it is not limited to this and may be configured as a shared area to which other information can also be written. In other words, since there is no need to save the information in the flag register of the main CPU 63 corresponding to specific control when management processing is not being executed, a shared area that is also used as a PSW buffer when performing predetermined arithmetic processing in processing corresponding to specific control when management processing is not being executed may be configured. In this case, since the shared area will be reliably used to save the information in the flag register when management processing is being executed, it is necessary to configure the shared area so that information other than flag register information that becomes unnecessary before management processing is executed is written to the shared area.

Seventeenth Embodiment
In this embodiment, the processing configuration of the management execution process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the configuration that is the same as the fifteenth embodiment will basically be omitted.

Figure 78 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4501 to S4515 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as in step S3901 of the management execution process (Figure 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the primary CPU 63 (step S4501).

Then, using the push command "PUSH WA," the information in the WA register of the primary CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the primary CPU 63 (step S4502). In this case, the information in the WA register is saved to a memory area corresponding to the fixed address set in the stack pointer of the primary CPU 63 in step S4501. In addition, the information in the stack pointer of the primary CPU 63 is updated to the address information of the memory area to be written to next.

Then, using the push command "PUSH BC," the information in the BC register of the primary CPU 63 is saved to a storage area in the non-specific control stack area 224 corresponding to the current stack pointer information of the primary CPU 63 (step S4503). The stack pointer information of the primary CPU 63 is also updated to the address information of the storage area to be written to next.

Then, using the push command "PUSH DE," the information in the DE register of the primary CPU 63 is saved to a storage area in the non-specific control stack area 224 corresponding to the current stack pointer information of the primary CPU 63 (step S4504). The stack pointer information of the primary CPU 63 is also updated to the address information of the storage area to be written to next.

Then, using the push command "PUSH HL," the information in the HL register of the primary CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the primary CPU 63 (step S4505). The stack pointer information of the primary CPU 63 is also updated to the address information of the memory area to be written to next.

Then, using the push command "PUSH IX," the information in the IX register of the primary CPU 63 is saved to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the primary CPU 63 (step S4506). The stack pointer information of the primary CPU 63 is also updated to the address information of the memory area to be written to next.

Then, using the push command "PUSH IY," the information in the IY register of the primary CPU 63 is saved to a storage area in the non-specific control stack area 224 corresponding to the current stack pointer information of the primary CPU 63 (step S4507). The stack pointer information of the primary CPU 63 is also updated to the address information of the storage area to be written to next.

After steps S4502 to S4507 are executed, a check process is executed (step S4508). When the check process is executed, a subroutine program corresponding to the check process set in the non-specific control program is executed. When the subroutine program is executed, information for specifying the return address of the management execution process after the check process is executed is written by a push command to a memory area in the non-specific control stack area 224 corresponding to the current stack pointer information of the main CPU 63. Then, when the check process is completed, a pop command is used to read the information for specifying the return address, and the program returns to the management execution process indicated by the return address. The content of the check process is the same as in the fifteenth embodiment described above.

Then, as in step S3909 of the management execution process (FIG. 71) in the above-mentioned 15th embodiment, a load command is used to set "LD SP, Y(r+α)" to Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the primary CPU 63 (step S4509). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Then, a pop command "POP IY" is issued to overwrite the IY register of the main CPU 63 with the information saved in the storage area corresponding to the previous information in the non-specific control stack area 224 relative to the current stack pointer information of the main CPU 63 (step S4510). The stack pointer information of the main CPU 63 is also updated to the address information of the storage area to be written to in the previous order.

Then, using the pop command "POP IX," the information saved in the memory area corresponding to the previous information in the non-specific control stack area 224 of the primary CPU 63 is overwritten in the IX register of the primary CPU 63 (step S4511). The stack pointer information of the primary CPU 63 is also updated to the address information of the memory area to which the previous information is to be written.

Then, using the pop command "POP HL," the information saved in the memory area corresponding to the previous information in the non-specific control stack area 224 of the main CPU 63 is overwritten in the HL register of the main CPU 63 (step S4512). The stack pointer information of the main CPU 63 is also updated to the address information of the memory area to which the previous information is to be written.

Then, using the pop command "POP DE," the DE register of the primary CPU 63 is overwritten with the information saved in the storage area corresponding to the previous information in the non-specific control stack area 224, in relation to the current stack pointer information of the primary CPU 63 (step S4513). The stack pointer information of the primary CPU 63 is also updated to the address information of the storage area to be written to in the previous order.

Then, a "POP BC" command is issued to overwrite the BC register of the main CPU 63 with the information saved in the storage area corresponding to the previous information in the non-specific control stack area 224 relative to the current stack pointer information of the main CPU 63 (step S4514). The stack pointer information of the main CPU 63 is also updated to the address information of the storage area to which the previous information is to be written.

Then, a "POP WA" command is issued to overwrite the WA register of the main CPU 63 with the information saved in the storage area corresponding to the previous information in the non-specific control stack area 224, in relation to the current stack pointer information of the main CPU 63 (step S4515). The stack pointer information of the main CPU 63 is also updated to the address information of the storage area to be written to in the previous order.

By executing steps S4510 to S4515, the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 can be restored to the information corresponding to specific control immediately before processing corresponding to non-specific control was started.

In addition to the flag register, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S4502 through S4507, information from some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the non-specific control stack area 224. The WA register, BC register, DE register, HL register, IX register, and IY register are used in the check process (step S4508), which corresponds to non-specific control. By saving the information stored in these registers to the non-specific control stack area 224 prior to the execution of the check process (step S4508), it is possible to save the information in these registers used during specific control before non-specific control begins. Therefore, even if these registers are overwritten during non-specific control, when the non-specific control is terminated, the information saved in the stack area 224 for non-specific control is restored to these registers, making it possible to restore the state of these registers to the state corresponding to the specific control before the non-specific control was executed.

In addition, rather than saving all information from various general-purpose registers, auxiliary registers, and index registers to the non-specific control stack area 224, information from the WA register, BC register, DE register, HL register, IX register, and IY register to be used in the check process, which is a process corresponding to non-specific control, is selectively saved to the non-specific control stack area 224. This makes it possible to reduce the capacity required to save register information in the non-specific control stack area 224. Therefore, it is possible to save the above-mentioned register information while ensuring a large capacity for the non-specific control stack area 224 that is available for use in the check process.

<Eighteenth embodiment>
In this embodiment, the processing configuration of the management execution process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the configuration that is the same as the fifteenth embodiment will basically be omitted.

Figure 79 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4601 to S4605 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as in step S3901 of the management execution process (Figure 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the primary CPU 63 (step S4601).

Then, the load command "LD (_ALLBUF), ALL" is issued to save the information in all registers of the main CPU 63 to the ALL buffer set in the work area 223 for non-specific control (step S4602). As a result, not only the information in the WA register, BC register, DE register, HL register, IX register, and IY register used in the check process, which is a process corresponding to non-specific control, but also information in all registers, including other registers, are saved together in the ALL buffer in the work area 223 for non-specific control. By saving all registers of the main CPU 63 to the work area 223 for non-specific control in this way, there is no need to selectively save the information in the registers of the main CPU 63.

The registers to be saved here also include the flag register. Flag register information is saved to the stack area 222 for specific control in step S3802 of the management process (Figure 70), but in step S4602, the flag register information is saved to the work area 223 for non-specific control. This eliminates the need to selectively save register information in the main CPU 63, including flag register information. Furthermore, even if flag register information is saved in duplicate in this way, after the management execution process is completed, the information is restored from the stack area 222 for specific control to the flag register of the main CPU 63 in step S3804 of the management process (Figure 70). Therefore, when returning to processing corresponding to specific control, it is possible to restore the flag register information of the main CPU 63 to the state it was in immediately before the management execution process was executed.

Then, check processing is executed (step S4603). When check processing is executed, a subroutine program corresponding to the check processing set in the program for non-specific control is executed. When the subroutine program is executed, information for specifying the return address of the management execution processing after execution of the check processing is written by a push command to a memory area in the stack area 224 for non-specific control corresponding to the information of the current stack pointer of the main CPU 63. Then, when check processing is completed, information for specifying the return address is read by a pop command, and processing returns to the program for management execution processing indicated by the return address. The content of the check processing is the same as in the fifteenth embodiment described above.

Then, as in step S3909 of the management execution process (FIG. 71) in the above-mentioned 15th embodiment, a load command is used to set "LD SP, Y(r+α)" to Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the primary CPU 63 (step S4604). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Then, the load command "LD ALL, (_ALLBUF)" is used to overwrite the information saved in the ALL buffer in the work area 223 for non-specific control into the registers corresponding to each of the primary CPUs 63 (step S4605). This makes it possible to restore the information in all registers of the primary CPU 63 to the information corresponding to specific control that was present immediately before processing corresponding to non-specific control was started.

With the above configuration, by saving the register information of the main CPU 63 to the work area 223 for non-specific control rather than to the stack area 224 for non-specific control, it is possible to reduce the capacity of the stack area 224 for non-specific control. Furthermore, when using the stack area 224 for non-specific control, the order in which information is written is such that later information is read first. Therefore, if the order in which information is read is shifted due to some kind of noise or other cause, all of the information read after that will be restored to different registers. The probability of this happening increases as the amount of information saved in the stack area 224 for non-specific control increases. In contrast, by saving register information to the work area 223 for non-specific control, it is possible to prevent the above-mentioned happening even when there is a lot of information to save.

In addition, when the register information of the main CPU 63 is saved to the work area 223 for non-specific control, the information of all registers, including not only the WA register, BC register, DE register, HL register, IX register, and IY register used in the check process, which is a process corresponding to non-specific control, but also other registers, is saved together in the ALL buffer of the work area 223 for non-specific control. By saving all registers of the main CPU 63 to the work area 223 for non-specific control in this way, there is no need to selectively save the register information of the main CPU 63.

In addition, although the information in all registers of the main CPU 63 is saved to the main RAM 65 during processing corresponding to non-specific control after processing corresponding to the non-specific control has begun, this is not limited to this, and the information in all registers may be saved to the main RAM 65 during processing corresponding to specific control. Furthermore, although the information is restored to all registers during processing corresponding to non-specific control when processing corresponding to non-specific control ends, this is not limited to this, and the information may be restored to all registers during processing corresponding to specific control after processing corresponding to non-specific control ends.

<Nineteenth embodiment>
In this embodiment, the processing configuration of the management execution process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the configuration that is the same as the fifteenth embodiment will basically be omitted.

Figure 80 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4701 to S4706 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, the stack pointer information of the primary CPU 63 is saved to the SP buffer set in the work area 223 for non-specific control using the load command "LD (_SPBUF), SP" (step S4701). As a result, the stack pointer information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started is saved to the work area 223 for non-specific control.

Then, as in step S3901 of the management execution process (FIG. 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as the fixed address at the start of non-specific control in the stack pointer of the primary CPU 63 (step S4702).

Then, using the push command "PUSH ALL," the information in all registers of the primary CPU 63 is saved to the storage area in the non-specific control stack area 224 corresponding to the information in the current stack pointer of the primary CPU 63 and to a storage area contiguous to that storage area (step S4703). In this case, since it is not possible to store the information in all registers of the primary CPU 63 in a single storage area in the non-specific control stack area 224, the storage area in the non-specific control stack area 224 corresponding to the information in the current stack pointer of the primary CPU 63 and a storage area contiguous to that storage area are used as the destination for saving the register information, as described above. In addition, the stack pointer information of the primary CPU 63 is updated to the address information of the storage area to be written next in order, in the storage area in which the last information was stored when all register information was saved.

Then, check processing is executed (step S4704). When check processing is executed, a subroutine program corresponding to the check processing set in the program for non-specific control is executed. When the subroutine program is executed, information for specifying the return address of the management execution processing after execution of the check processing is written by a push command to a memory area in the stack area 224 for non-specific control corresponding to the information of the current stack pointer of the main CPU 63. Then, when check processing is completed, a pop command is used to read the information for specifying the return address, and control returns to the program for management execution processing indicated by the return address. The content of the check processing is the same as in the fifteenth embodiment described above.

Then, a pop command "POP ALL" is issued to overwrite the information saved in the memory area corresponding to the current stack pointer information of the primary CPU 63 in the stack area 224 for non-specific control and in the memory area adjacent to that memory area in the registers corresponding to the primary CPU 63 (step S4705). This makes it possible to restore the information in all registers of the primary CPU 63 to the information corresponding to specific control immediately before processing corresponding to non-specific control was started.

Then, the information saved in the SP buffer of the work area 223 for non-specific control is overwritten to the stack pointer of the primary CPU 63 using the load command "LD SP, (_SPBUF)" (step S4706). This restores the information in the stack pointer of the primary CPU 63 to the information corresponding to specific control immediately before processing corresponding to non-specific control was started.

With the above configuration, when the register information of the main CPU 63 is saved to the stack area 224 for non-specific control, not only the WA register, BC register, DE register, HL register, IX register, and IY register used in the check process, which is a process corresponding to non-specific control, but also information from all other registers is saved together in the stack area 224 for non-specific control. By saving all registers of the main CPU 63 to the stack area 224 for non-specific control in this way, there is no need to selectively save information from the registers of the main CPU 63.

The stack pointer information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started is saved in the work area 223 for non-specific control. As a result, even if the configuration allows the stack pointer information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started to change, when the processing corresponding to the non-specific control ends and returns to the processing corresponding to the specific control, the stack pointer information of the main CPU 63 can be restored to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started.

In addition, although the information in all registers of the main CPU 63 is saved to the main RAM 65 during processing corresponding to non-specific control after processing corresponding to the non-specific control has begun, this is not limited to this, and the information in all registers may be saved to the main RAM 65 during processing corresponding to specific control. Furthermore, although the information is restored to all registers during processing corresponding to non-specific control when processing corresponding to non-specific control ends, this is not limited to this, and the information may be restored to all registers during processing corresponding to specific control after processing corresponding to non-specific control ends.

<Twentieth embodiment>
In this embodiment, the processing configuration of the management process and the management execution process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the configuration that is the same as the fifteenth embodiment will basically be omitted.

Figure 81 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S4801 to S4811 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 69) (step S4801). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, a push command is issued as "PUSH PSW" to save the flag register information of the main CPU 63 to the specific control stack area 222 (step S4802). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the flag register information changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program of the subroutine corresponding to the management execution process is started, it is possible to save the flag register information in the specific control stack area 222 in its state before it changes after the subroutine is called or started.

Then, the WA register of the primary CPU 63 is cleared to "0" by a load command as "LD WA, 0" (step S4803). The BC register of the primary CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S4804). The DE register of the primary CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S4805). The HL register of the primary CPU 63 is cleared to "0" by a load command as "LD HL, 0" (step S4806). The IX register of the primary CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S4807). The IY register of the primary CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S4808).

In addition to the flag register, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S4803 to S4808, some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, are cleared to "0." The WA register, BC register, DE register, HL register, IX register, and IY register are used in the check process (step S4902), which corresponds to non-specific control. By clearing these registers to "0" prior to the execution of the management execution process (step S4809), which corresponds to non-specific control, the state of these registers can be restored to the state they were in immediately after the supply of operating power to the main CPU 63 was initiated, before the process corresponding to non-specific control was initiated.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register before processing corresponding to non-specific control begins is unnecessary for processing corresponding to specific control after processing corresponding to that non-specific control has ended. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in processing corresponding to specific control that is restored after processing corresponding to non-specific control has ended.

After steps S4803 to S4808 have been executed, the subroutine program corresponding to the management execution process set in the non-specific control program is read out, thereby starting the management execution process (step S4809). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read out by a pop command, and control returns to the management processing program indicated by the return address.

When the management execution process is completed and the program for management processing is returned to, the flag register information saved in the stack area 222 for specific control in step S4802 is restored to the flag register of the primary CPU 63 by a pop command as "POP PSW" (step S4810). This restores the flag register information of the primary CPU 63 to the information at the time step S4802 was last executed. In other words, the flag register information of the primary CPU 63 is restored to the information for executing specific control.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S4811). This allows new execution of timer interrupt processing.

Figure 82 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S4901 to S4909 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as in step S3901 of the management execution process (Figure 71) in the 15th embodiment, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the primary CPU 63 (step S4901).

Then, check processing is executed (step S4902). When the check processing is executed, a subroutine program corresponding to the check processing set in the non-specific control program is executed, and when the subroutine program is executed, information for specifying the return address of the management execution processing after the check processing is executed is written to the non-specific control stack area 224 by a push command. Then, when the check processing is completed, information for specifying the return address is read by a pop command, and processing returns to the management execution processing program indicated by the return address. The content of the check processing is the same as in the 15th embodiment above.

Then, the WA register of the primary CPU 63 is cleared to "0" by a load command as "LD WA, 0" (step S4903). The BC register of the primary CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S4904). The DE register of the primary CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S4905). The HL register of the primary CPU 63 is cleared to "0" by a load command as "LD HL, 0" (step S4906). The IX register of the primary CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S4907). The IY register of the primary CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S4908).

As already explained, the WA register, BC register, DE register, HL register, IX register, and IY register are registers used in the check process (step S4902), which is a process corresponding to non-specific control. By clearing these registers to "0" prior to returning from the process corresponding to non-specific control to the process corresponding to specific control, the state of these registers can be restored to the state they were in immediately after the supply of operating power to the main CPU 63 began, before returning to the process corresponding to specific control.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register before processing corresponding to specific control begins is unnecessary for processing corresponding to non-specific control after processing corresponding to that specific control has ended. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in processing corresponding to non-specific control that is restored after processing corresponding to specific control has ended.

Then, as in step S3909 of the management execution process (FIG. 71) in the above-mentioned 15th embodiment, a load command is used to set "LD SP, Y(r+α)" to Y(r+α) as a fixed address at the time of return to specific control in the stack pointer of the primary CPU 63 (step S4909). The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

With the above configuration, when processing corresponding to specific control is executed and processing corresponding to non-specific control is initiated, the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 are cleared to "0." This eliminates the need to save the information in these registers to the main RAM 65. Therefore, there is no need to reserve capacity for saving this information.

In addition, when returning to processing corresponding to specific control from a situation where processing corresponding to non-specific control is being executed, the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 are cleared to "0." This makes it possible to restore the state of each of these registers to the state it was in immediately before processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

The state in which each of the above registers is cleared to "0" is the state when the supply of operating power to the main CPU 63 begins. This simplifies the processing configuration for setting each of the above registers to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

When starting processing corresponding to non-specific control and when returning to processing corresponding to specific control, the registers that are cleared to "0" are some of the various registers in the main CPU 63. This makes it possible to reduce the processing load required to set each of the above registers to a specified state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

When starting processing corresponding to non-specific control and when returning to processing corresponding to specific control, the WA register, BC register, DE register, HL register, IX register, and IY register are cleared to "0," but other registers are not cleared to "0." This makes it possible to prevent information necessary for processing corresponding to specific control from being erased when processing corresponding to non-specific control begins.

In addition, information in registers other than the WA register, BC register, DE register, HL register, IX register, and IY register is not saved to the main RAM 65 when processing corresponding to non-specific control begins. This eliminates the need to reserve an area in the main RAM 65 for saving this information.

The information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 before processing corresponding to non-specific control begins is information that is not used in processing corresponding to specific control after processing corresponding to non-specific control ends. This makes it possible to prevent the processing corresponding to specific control after processing corresponding to non-specific control ends from being affected, even if the above registers are configured to be cleared to "0" when processing corresponding to non-specific control begins.

Instead of clearing the WA, BC, DE, HL, IX, and IY registers of the main CPU 63 to "0" in steps S4803 to S4808 of the management process (FIG. 81), these registers may be initialized. In other words, when the supply of operating power to the main CPU 63 begins, each register of the main CPU 63 is cleared to "0" and then the information in each register is set to its initial state. However, steps S4803 to S4808 may be configured to set each register to this initial state. In this case, by configuring steps S4903 to S4908 to also set each register to the above-mentioned initial state, it is possible to restore the state of each register to the state it was in immediately before the process corresponding to non-specific control was started when returning to the process corresponding to specific control.

In addition, instead of clearing the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to "0" in steps S4803 to S4808 in the management processing (Figure 81), all of these registers may be set to "1." In this case, by setting all of the above registers to "1" in steps S4903 to S4908 as well, when returning to processing corresponding to specific control, it is possible to restore the state of each of these registers to the state it was in immediately before processing corresponding to non-specific control was started.

Furthermore, while the configuration is such that when processing corresponding to non-specific control is executed, the information in the flag register of the main CPU 63 is saved to the main RAM 65 during processing corresponding to specific control, this is not limited to this, and the information in the flag register may also be saved to the main RAM 65 during processing corresponding to non-specific control. Furthermore, the configuration is such that after processing corresponding to non-specific control is completed, the information is restored to the flag register of the main CPU 63 during processing corresponding to specific control, but this is not limited to this, and the information may also be restored to the flag register during processing corresponding to non-specific control.

Furthermore, although the process of clearing the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 to "0" is configured to be executed in the process corresponding to specific control before the process corresponding to non-specific control is started, this is not limited to this, and the process of clearing these registers to "0" may be executed in the process corresponding to non-specific control. Furthermore, although the process of clearing each of the above registers to "0" is configured to be executed in the process corresponding to non-specific control when the process corresponding to non-specific control ends, this is not limited to this, and the process of clearing each of the above registers to "0" may be executed in the process corresponding to specific control after the process corresponding to non-specific control ends.

In addition, in the management processing (FIG. 81), the "PUSH PSW" processing in step S4802 is configured to be executed before setting each register to "0" in steps S4803 to S4808. Alternatively, the "PUSH PSW" processing in step S4802 may be configured to be executed after setting each register to "0" in steps S4803 to S4808 and before the subroutine program corresponding to the management execution processing is read in step S4809. This makes it possible to save the information in the flag register after it has been changed by the load instruction in steps S4803 to S4808 to the specific control stack area 222.

<Twenty-first embodiment>
In this embodiment, the configuration for collecting game history information differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will be omitted.

Figure 83 is an explanatory diagram illustrating the electrical configuration of this embodiment.

The MPU 62 is provided with a main CPU 63, main ROM 64, and main RAM 65, similar to the fifteenth embodiment. Also, unlike the fifteenth embodiment, a management RAM 241 is electrically connected to the MPU 62. In other words, the management RAM 241 is provided separately from the main RAM 65 built into the MPU 62, and the management RAM 241 is external to the MPU 62.

The main RAM 65 is provided with a work area 221 for specific control, a stack area 222 for specific control, a work area 223 for non-specific control, and a stack area 224 for non-specific control, as in the fifteenth embodiment described above. Therefore, when the main CPU 63 executes processing corresponding to specific control using the program for specific control and data for specific control in the main ROM 64, it uses the work area 221 for specific control and the stack area 222 for specific control in the main RAM 65, and when the main CPU 63 executes processing corresponding to non-specific control using the program for non-specific control and data for non-specific control in the main ROM 64, it uses the work area 223 for non-specific control and the stack area 224 for non-specific control in the main RAM 65.

The management RAM 241 is provided with a normal counter area 231, an open/close execution mode counter area 232, a high-frequency support mode counter area 233, and a calculation result storage area 234. The contents of these areas 231-234 are the same as those in the fifteenth embodiment. In this embodiment, management execution processing including a check process is executed as processing corresponding to non-specific control in the main CPU 63. Then, as in the fifteenth embodiment, this check process collects game history through updating the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233, and the 61st to 68th parameters calculated using the collected game history are written to the calculation result storage area 234. In other words, the management RAM 241 is used when the main CPU 63 executes processing corresponding to non-specific control, and therefore the management RAM 241 is used as a work area for non-specific control.

In addition, when collecting game history and calculating parameters 61 to 68 using the collected history information, the non-specific control work area 223 and non-specific control stack area 224 in the main RAM 65 are used as appropriate.

With the above configuration, the normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233, and calculation result storage area 234 are provided in the management RAM 241 external to the MPU 62. This makes it possible to store collected game history information and store parameters 61 through 68 calculated using that game history without increasing the storage capacity required in the non-specific control work area 223 in the main RAM 65. It also makes it possible to increase the storage capacity for storing game history information while using a general-purpose MPU 62.

When collecting game history and calculating parameters 61 through 68 using the collected history information, the non-specific control work area 223 and non-specific control stack area 224 in the main RAM 65 are used as appropriate. This makes it possible to prevent an extreme drop in processing speed when processing history information.

In addition to or instead of the configuration in which the management RAM 241 is provided with the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234, a storage area corresponding to the history memory 117 in the first embodiment or the like may be configured. In this case, it is necessary to increase the storage capacity required to store the history information, but because the management RAM 241 external to the MPU 62 is configured to be used as storage means for storing the history information, it is possible to flexibly accommodate increases in storage capacity.

<Twenty-second embodiment>
In this embodiment, the processing configuration executed by the main CPU 63 differs from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 84 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S5001 to S5019 in the main processing are executed by the main CPU 63 using a specific control program and specific control data.

First, power-on wait processing is executed (step S5001). During this power-on wait processing, the system waits for a predetermined wait time (specifically, one second) after the main processing is started, without proceeding to the next processing. During this power-on wait processing, the pattern display device 41 starts operating and is initialized. After that, access to the main RAM 65 is permitted (step S5002).

Then, it is determined whether the reset button 68c has been pressed (step S5003), whether the setting key insertion unit 68a has been turned ON using the setting key (step S5004), whether the front door frame 14 is open relative to the inner frame 13 (step S5005), and whether the gaming machine main body 12 is open relative to the outer frame 11 (step S5006).

In this embodiment, a front door open sensor 95 for detecting whether the front door frame 14 is open relative to the inner frame 13 is electrically connected to the main CPU 63, and the detection result of the front door open sensor 95 is input to the main CPU 63. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 sends a closed detection signal to the main CPU 63, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 sends an open detection signal to the main CPU 63. When the main CPU 63 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is closed, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is open.

In addition, in this embodiment, a main body open sensor 96 for detecting whether the gaming machine main body 12 is in an open state relative to the outer frame 11 is electrically connected to the main CPU 63, and the detection result of the main body open sensor 96 is input to the main CPU 63. In this case, if the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 sends a closed detection signal to the main CPU 63, and if the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 sends an open detection signal to the main CPU 63. If the main CPU 63 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and if it receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state.

If the reset button 68c is pressed (step S5003: YES) and a negative judgment is made in any of steps S5004 through S5006, a clearing process for non-setting updates is executed (step S5007). In the clearing process for non-setting updates, the specific control work area 221 is cleared to "0" except for the area in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set (specifically, the setting value counter), and initial settings are performed for the area cleared to "0." This clears to "0" the area indicating whether the win/loss lottery mode is in high probability mode, so the win/loss lottery mode becomes low probability mode regardless of the win/loss lottery mode in effect immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserved storage area 65a and normal power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so the reserved information for the special map display unit 37a is erased and the reserved information for the normal map display unit 38a is erased. In addition, in the clearing process for non-setting updates, the stack area 222 for specific control is cleared to "0". In addition, in the clearing process for non-setting updates, various registers of the main CPU 63 are also cleared to "0" before initial settings are performed.

The clearing process during non-setting updates does not clear the non-specific control work area 223 and the non-specific control stack area 224 to "0." This prevents the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" even if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed.

If the reset button 68c is not pressed (step S5003: NO), it is determined whether the power outage flag is set to "1" (step S5008). The power outage flag is provided in the specific control work area 221. If the supply of operating power to the main CPU 63 is stopped and the predetermined power outage processing is executed normally, the power outage flag is set to "1." If the power outage flag is set to "1," it is determined whether the checksum calculation result matches the checksum saved at the time of power outage, i.e., the validity of the stored data (step S5009). If the non-setting update clear processing was executed in step S5007, or if a positive determination is made in step S5009, it is determined whether the setting value of the pachinko machine 10 is normal by checking the value of the setting value counter in the specific control work area 221 (step S5010). Specifically, if the setting value set in the setting value counter is any of "Setting 1" through "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

If a negative judgment is made in any of steps S5008 to S5010, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or other person that an error has occurred (step S5011), and then an infinite loop is entered. This operation prohibition process is released by executing the clear process (step S5018) when updating settings, which will be described later.

If a positive judgment is made in all of steps S5008 to S5010, the power-on setting process is executed (step S5012). In the power-on setting process, a predetermined area of the work area 221 for specific control, such as the initialization of the power outage flag, is set to its initial value, and a command corresponding to the current game state is sent to the audio and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited when main processing begins. This state in which timer interrupt processing is prohibited is released when step S5012 is completed and before step S5013 is executed, and timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 begins, the power-on setting process of step S5012 ends and timer interrupt processing is not executed until before step S5013 is started. Therefore, processing to progress the game will not be initiated by the main CPU 63 until this situation is reached.

Then, the process proceeds to the remaining processing of steps S5013 to S5016. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there will be remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time will be used to repeatedly execute the remaining processing of steps S5013 to S5016. In this respect, the remaining processing of steps S5013 to S5016 can be said to be non-periodic processing executed non-periodically. Steps S5013 to S5016 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

On the other hand, if the reset button 68c has been pressed (step S5003: YES) and all of steps S5004 to S5006 return a positive result, processing is executed to update the setting values. Specifically, a setting value copy process is first executed (step S5017). In this copy process, the setting value counter information used to identify the setting values of the pachinko machine 10 in the specific control work area 221 is stored in a copy area provided in the specific control work area 221. As a result, even if the setting value counter information is cleared to "0" in the subsequent setting update clear process (step S5018), it is possible to determine the setting values of the pachinko machine 10 before the setting value clear process was executed (i.e., the setting values of the pachinko machine 10 before the supply of operating power to the pachinko machine 10 was stopped).

Then, a clearing process is executed when the settings are updated (step S5018). In the clearing process when the settings are updated, the work area 221 for specific control is cleared to "0," except for the area in the work area 221 for specific control that indicates whether the win/lose lottery mode is the high probability mode, and the copy area. Initial settings are then made for the areas cleared to "0." This results in a situation where no game rounds are being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying any changes, and the normal power device 34a is in a closed state. Furthermore, the reserve storage area 65a and the normal power reserve area 65c provided in the work area 221 for specific control are also cleared to "0," thereby erasing the reserved information for the special map display unit 37a and the reserved information for the normal map display unit 38a. In the clearing process when the settings are updated, the stack area 222 for specific control is cleared to "0," and initial settings are made for the areas cleared to "0." Additionally, during the clearing process when updating settings, the setting value counter used to identify the setting values of the pachinko machine 10 is cleared to "0." During the clearing process when updating settings, various registers of the main CPU 63 are also cleared to "0" before initial settings are performed.

On the other hand, the clearing process when updating settings does not clear to "0" the area indicating whether the win/lose lottery mode is the high probability mode, so even if the setting value update process (step S5019) is executed, the win/lose lottery mode can be maintained in the mode it was in before the supply of operating power to the pachinko machine 10 was stopped. Furthermore, because the clearing process when updating settings does not clear to "0" the copy area, it is possible to subsequently identify the setting value that was set before the clearing process when updating settings was executed.

The clearing process during setting updates does not clear the non-specific control work area 223 and the non-specific control stack area 224 to "0." This makes it possible to prevent the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" even when a setting value update process that can change the setting values of the pachinko machine 10 is executed.

Then, in step S5019, the setting value update process is executed, and then processing proceeds to step S5012. The setting value update process is described below. Figure 85 is a flowchart showing the setting value update process. Note that steps S5101 to S5114 in the setting value update process are executed by the main CPU 63 using a program and data for specific control.

First, the setting value counter provided in the work area 221 for specific control is set to "1" (step S5101). The setting value counter is a counter that allows the main CPU 63 to determine which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value will become "Setting 1" regardless of the previous setting value.

Then, processing to start displaying the setting value is executed (step S5102). In the processing to start displaying the setting value, the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the gaming hall manager can understand the current setting status of the pachinko machine 10 by checking the third notification display device 69c.

Then, it is determined whether one gaming ball has been detected by the outlet detection sensor 48a (step S5103). Specifically, it is determined whether the signal received from the outlet detection sensor 48a has switched from a LOW level to a HIGH level. If a negative determination is made in step S5103, it is determined whether the update button 68b has been pressed once (step S5104). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HIGH level. If a negative determination is made in step S5104, the process returns to step S5103, and it is determined whether one gaming ball has been detected by the outlet detection sensor 48a.

If the update button 68b has been pressed once (step S5104: YES), the value of the setting value counter in the specific control work area 221 is incremented by 1 (step S5105). Furthermore, if the value of the setting value counter exceeds "6" after incrementing by 1 (step S5106: YES), the setting value counter is set to "1" (step S5107). As a result, the setting value is updated to the next higher level each time the update button 68b is pressed; if the update button 68b is pressed once when the setting is "6," the setting will return to "1."

If a negative judgment is made in step S5106, or if the processing of step S5107 is executed, a display update process for the setting value is executed (step S5108). In the display update process for the setting value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter in the work area 221 for specific control is displayed. By checking the third notification display device 69c, the manager of the gaming hall can understand the setting status of the pachinko machine 10 after pressing the update button 68b.

After executing the processing of step S5108, the process returns to step S5103, where it is determined whether one game ball has been detected by the outlet detection sensor 48a. If the outlet detection sensor 48a has not detected one game ball (step S5103: NO), the processing from step S5104 onwards is executed again. If the outlet detection sensor 48a has detected one game ball (step S5103: YES), it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state (step S5109). In this case, it is not determined whether the setting key insertion unit 68a is in the OFF state, but rather whether a switch from the ON state to the OFF state has occurred, and if it is determined that such a switch has occurred, a positive determination is made in step S5109.

If the setting key has not been switched to the OFF state (step S5109: NO), step S5109 is executed again. This causes the process to wait until the setting key insertion unit 68a is turned OFF. If the setting key insertion unit 68a has been switched to the OFF state (step S5109: YES), the setting value display termination process is executed (step S5110). In this setting value display termination process, the display of the setting value on the third alarm display device 69c is terminated. In this case, the display of information on various parameters stored in the calculation result storage area 234 provided in the non-specific control work area 223 begins on the first to third alarm display devices 69a to 69c.

Then, a setting value comparison process is executed (step S5111). The setting value comparison process determines whether the information in the setting value counter in the work area 221 for specific control matches the information stored in the copy area in the work area 221 for specific control. In other words, it determines whether the setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is the same as the setting value set in this setting value update process.

If the setting value set before the supply of operating power to the pachinko machine 10 was stopped is the same as the setting value set in this setting value update process (step S5112: NO), a notification process for when no change has occurred is executed (step S5113). In the notification process for when no change has occurred, a setting maintenance command indicating that the setting value has not been changed is sent to the audio and light-emitting control device 81. Upon receiving the setting maintenance command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to maintaining the setting, and outputs a voice message saying "Settings are maintained" from the speaker unit 54. In addition, a text image saying "Settings are maintained" is displayed on the pattern display device 41.

These notifications are maintained until the notification execution period (e.g., 10 seconds) has elapsed since the setting maintenance command was sent, and are terminated when the notification execution period has elapsed. However, this is not limited to this, and the notifications may be terminated when the amusement hall manager performs an operation to terminate the notification. The notification termination operation may be, for example, by pressing the update button 68b or the reset button 68c. By confirming the notification, the amusement hall manager can understand that the setting value has been maintained. Note that in the notification process when no change is made, the display content on at least one of the first to third notification display devices 69a to 69c may be changed to display content corresponding to maintaining the setting, thereby notifying that the setting value has been maintained, or an external output may be provided indicating that the setting value has been maintained.

If the setting value set before the supply of operating power to the pachinko machine 10 was stopped is not the same as the setting value set in this setting value update process (step S5112: YES), a change notification process is executed (step S5114). In the change notification process, a setting change command indicating that the setting value has been changed is sent to the audio and light control device 81. Upon receiving the setting change command, the audio and light control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the setting change, and outputs a voice message saying "Settings have been changed" from the speaker unit 54. In addition, a text image saying "Settings have been changed" is displayed on the pattern display device 41.

These notifications are maintained until the notification execution period (e.g., 10 seconds) has elapsed since the setting change command was sent, and are terminated when the notification execution period has elapsed. However, this is not limited to this, and the notifications may also be terminated when an operation to terminate the notification is performed by the amusement hall manager. The notification may be terminated by, for example, pressing the update button 68b or the reset button 68c. By confirming the notification, the amusement hall manager will be able to understand that the setting value has been changed. Note that the notification process upon change may be configured to notify that the setting value has been changed by changing the display content on at least one of the first to third notification display devices 69a to 69c to display content corresponding to the setting change, or may be configured to provide an external output indicating that the setting value has been changed.

As described above, in this embodiment, in order for the setting value update process to be executed, not only must the setting key insertion section 68a be turned ON, but the reset button 68c must also be pressed, the front door frame 14 must be open, and the gaming machine main body 12 must be open. This makes it difficult to fraudulently execute the setting value update process.

Furthermore, in order for the setting value update process to be executed, the front door frame 14 and the gaming machine main body 12 must be in an open state. As a result, even if someone attempts to execute the setting value update process fraudulently, the fraudulent activity will be noticeable because the front door frame 14 and the gaming machine main body 12 are in an open state, making it easier for the gaming hall manager to discover the fraudulent activity.

In particular, in order to execute the setting value update process, not only does it require the opening of the gaming machine main body 12, which is necessary to expose the main control device 60, but it also requires the opening of the front door frame 14, which makes the fraudulent activity more complicated and makes the fraudulent activity more noticeable.

Furthermore, in a configuration where the game does not return to processing for progressing the game if the setting value update processing is not completed, in order to confirm the setting value selected in the setting value update processing and end the setting value update processing, it is necessary to insert a gaming ball into the outlet 24a, have the outlet detection sensor 48a detect the gaming ball, and then turn off the setting key insertion unit 68a. This makes it difficult to subsequently end the setting value update processing and return to processing for progressing the game, even if the setting value update processing is executed fraudulently.

In addition, the setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is compared with the setting value selected in the setting value update process, and a notification is issued corresponding to whether the two setting values are the same. This allows the amusement hall manager to easily understand whether the setting value was successfully changed through the setting value update process.

Figure 86 is a flowchart showing the timer interrupt processing in this embodiment, which is executed by the main CPU 63. The timer interrupt processing is executed periodically (for example, every 4 milliseconds) while steps S5013 to S5016 are being executed in the main processing (Figure 84). The program corresponding to the timer interrupt processing is set in the program for specific control.

Steps S5201 to S5205 execute the same processing as steps S301 to S305 of the timer interrupt processing (Figure 11) in the first embodiment described above. These processes are executed by the main CPU 63 using a specific control program and specific control data.

Then, the setting confirmation process is executed (step S5206). When the setting confirmation process is executed, a subroutine program corresponding to the setting confirmation process set in the specific control program is executed. When the subroutine program is executed, information for specifying the return address of the timer interrupt process after the setting confirmation process is executed is written to the specific control stack area 222 by a push command. Then, when the setting confirmation process is completed, the information for specifying the return address is read by a pop command, and control returns to the timer interrupt process program indicated by the return address.

Figure 87 is a flowchart showing the setting confirmation process. Note that steps S5301 to S5312 in the setting confirmation process are executed by the main CPU 63 using a specific control program and specific control data.

First, it is determined whether the third alarm display device 69c is displaying a setting value corresponding to the information from the setting value counter in the specific control work area 221 (step S5301). If a negative determination is made in step S5301, it is determined whether the mode is neither a game cycle nor an open/close execution mode (step S5302), whether the normal picture display unit 38a is displaying a changing pattern cycle, or whether the normal power device 34a is in a normal power open state in which it can be opened (step S5303), whether the front door frame 14 is in an open state relative to the inner frame 13 (step S5304), whether the gaming machine main body 12 is in an open state relative to the outer frame 11 (step S5305), and whether the setting key insertion unit 68a has been turned ON (step S5306). Whether the front door frame 14 is in the open state is determined based on the detection result of the front door open sensor 95, as in step S5005 in the main processing (Figure 84), and whether the gaming machine main body 12 is in the open state is determined based on the detection result of the main body open sensor 96, as in step S5006 in the main processing (Figure 84).

If a negative judgment is made in any of steps S5302 to S5306, this setting confirmation process is terminated without executing the processes of steps S5307 to S5309. If a positive judgment is made in all of steps S5302 to S5306, the setting value display start process is executed (step S5307). In the setting value display start process, the third alert display device 69c is controlled so that the setting value number corresponding to the setting value counter information in the specific control work area 221 is displayed. When checking the setting value, the gaming hall manager can grasp the current setting status of the pachinko machine 10 by visually checking the third alert display device 69c.

Then, the game stop flag provided in the work area 221 for specific control is set to "1" (step S5308). The game stop flag is a flag used by the main CPU 63 to identify whether or not a situation has occurred in which a positive judgment has been made in step S5207 of the timer interrupt processing (Figure 86) and the processing of steps S5208 to S5221 is not executed, i.e., whether or not the execution of processing to progress the game should be stopped. By setting the game stop flag to "1," a positive judgment has been made in step S5207 of the timer interrupt processing (Figure 86), and the processing of steps S5208 to S5221 is not executed. This allows the setting value to be checked in a situation in which the execution of processing to progress the game has been stopped. However, even if the game stop flag is set to "1", steps S5201 to S5205 of the timer interrupt process (Fig. 86) are executed, so even if the setting value is being checked, power outage monitoring is executed, the win random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is also executed.

Then, a confirmation notification start command is sent to the audio and light-emitting control device 81 (step S5309). Upon receiving the confirmation notification start command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the setting being confirmed, and causes the speaker unit 54 to output the audio message "Settings being confirmed." In addition, the pattern display device 41 is caused to display a text image saying "Settings being confirmed." These notifications continue until a confirmation notification end command is received from the main CPU 63. Note that an external output may also be configured to indicate that the setting values are being confirmed.

As described above, under the condition that the game is not in play mode or open/close execution mode, and that the image on the normal display unit 38a is not showing a changing image, or that the normal power device 34a is not in a normal power open state in which it can be opened, a display for checking the setting value is displayed on the third notification display device 69c, thereby making it possible to prevent the setting value from being checked while the game is being played.

Furthermore, in order for the display for confirming the setting value to be displayed on the third notification display device 69c, not only must the setting key insertion section 68a be turned ON, but the front door frame 14 must also be in the open state, and the gaming machine main body 12 must also be in the open state. This makes it difficult to fraudulently display the display for confirming the setting value.

Furthermore, in order for the display for confirming the set value to be displayed on the third alarm display device 69c, the front door frame 14 and the gaming machine main body 12 must be in an open state. As a result, even if someone attempts to fraudulently display the display for confirming the set value, the fraudulent activity will be noticeable because the front door frame 14 and the gaming machine main body 12 are in an open state, making it easier for the gaming hall manager to discover the fraudulent activity.

In particular, in order to display the setting value on the third alarm display device 69c, it is necessary not only to open the gaming machine main body 12 to expose the main control device 60, but also to open the front door frame 14, which makes the fraudulent activity more complicated and makes the fraudulent activity more noticeable.

If a positive determination is made in step S5301, it is determined whether the setting key insertion section 68a has been turned OFF (step S5310). If it has been turned OFF (step S5310: YES), the game stop flag in the specific control work area 221 is cleared to "0" (step S5311). This results in a situation where a negative determination is made in step S5207 of the timer interrupt process (Figure 86), causing the processing of steps S5208 to S5221 to be executed. This cancels the state in which the execution of processing to progress the game has been stopped.

Then, a confirmation notification end command is sent to the audio and light control device 81 (step S5312). Upon receiving the confirmation notification end command, the audio and light control device 81 ends the notification indicating that the setting values of the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are being confirmed.

Returning to the explanation of the timer interrupt processing (Figure 86), after the setting confirmation processing of step S5206 is completed, it is determined whether or not game play is currently stopped (step S5207). In this case, if the game stop flag in the specific control work area 221 is set to "1" during the setting confirmation processing of step S5206, a positive determination is made in step S5207 and the processing of steps S5208 to S5221 is not executed. Also, if the occurrence of fraud is detected during the fraud detection processing of step S5205, a positive determination is made in step S5207 and the processing of steps S5208 to S5221 is not executed.

Steps S5208 to S5219 execute the same processing as steps S307 to S318 in the timer interrupt processing (Figure 11) in the first embodiment described above. These processes are executed in the main CPU 63 using a program for specific control and data for specific control. Furthermore, step S5221 executes the same processing as step S3719 in the timer interrupt processing (Figure 69) in the fifteenth embodiment described above.

Meanwhile, in step S5220, RAM monitoring processing is executed. When RAM monitoring processing is executed, a subroutine program corresponding to the RAM monitoring processing set in the specific control program is executed, and when this subroutine program is executed, information for specifying the return address of the timer interrupt processing after execution of the RAM monitoring processing is written to the specific control stack area 222 by a push command. Then, when the RAM monitoring processing is completed, information for specifying the return address is read by a pop command, and processing returns to the timer interrupt processing program indicated by that return address.

Figure 88 is a flowchart showing the RAM monitoring process. Note that steps S5401 to S5412 in the RAM monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a monitoring process is executed for the work area 221 for specific control (step S5401). This monitoring process monitors whether an abnormality has occurred in the information stored in the work area 221 for specific control due to noise or other causes. Any monitoring method can be used, but one example is to monitor whether the state of a storage area in the work area 221 for specific control, to which no information is written by various controls in the main CPU 63, differs from its initial state, and determine that an abnormality has occurred if the state differs from the initial state. In this case, if the initial state of the storage area is set to "0," an abnormality is determined to have occurred if a "1" is stored in the storage area. Alternatively, if the initial state of the storage area is set to "1," an abnormality is determined to have occurred if the value of the storage area is set to "0." In addition to the above monitoring method, a configuration may also be used in which an abnormality is determined to have occurred if the value of a specified byte differs from the value that would normally be set in the storage area.

If it is determined in step S5401 that an abnormality exists (step S5402: YES), execute steps S5409 to S5412. If it is not determined in step S5401 that an abnormality exists (step S5402: NO), proceed to step S5403.

In step S5403, a monitoring process is executed for the specific control stack area 222. This monitoring process monitors whether an abnormality has occurred in the information stored in the specific control stack area 222 due to noise or other causes. Any monitoring method can be used, but one example is to monitor whether the state of the specific control stack area 222, to which no information is written by various controls in the main CPU 63, is different from its initial state, and determine that an abnormality has occurred if the state is different from the initial state. In this case, if the initial state of the storage area is set to "0", an abnormality is determined to have occurred if a "1" is stored in the storage area. Alternatively, if the initial state of the storage area is set to "1", an abnormality is determined to have occurred if the value of the storage area is set to "0". In addition to the above monitoring method, a configuration may also be used in which an abnormality is determined to have occurred if the value of a specified byte is different from the value that would be set in a normal state.

If it is determined in step S5403 that an abnormality exists (step S5404: YES), execute steps S5409 to S5412. If it is not determined in step S5403 that an abnormality exists (step S5404: NO), proceed to step S5405.

In step S5405, monitoring processing of the non-specific control work area 223 is performed. This monitoring processing monitors whether an abnormality has occurred in the information stored in the non-specific control work area 223 due to noise or other causes. Any monitoring method can be used, but one example is to monitor whether the state of a storage area in the non-specific control work area 223 to which information is not written by various controls in the main CPU 63 differs from its initial state, and determine that an abnormality has occurred if the state differs from the initial state. In this case, if the initial state of the storage area is set to "0," an abnormality is determined to have occurred if a "1" is stored in the storage area. Alternatively, if the initial state of the storage area is set to "1," an abnormality is determined to have occurred if the value of the storage area is set to "0." In addition to the above monitoring method, a configuration may also be used to determine that an abnormality has occurred if the value of a specified byte differs from the value that would normally be set in the storage area.

If it is determined in step S5405 that an abnormality exists (step S5406: YES), execute steps S5409 to S5412. If it is not determined in step S5405 that an abnormality exists (step S5406: NO), proceed to step S5407.

In step S5407, monitoring processing is performed on the non-specific control stack area 224. This monitoring processing monitors whether an abnormality has occurred in the information stored in the non-specific control stack area 224 due to noise or other causes. Any monitoring method can be used, but one example is to monitor whether the state of the storage area in the non-specific control stack area 224, to which no information is written by various controls in the main CPU 63, is different from its initial state, and determine that an abnormality has occurred if the state is different from the initial state. In this case, if the initial state of the storage area is set to "0," an abnormality is determined to have occurred if a "1" is stored in the storage area. Alternatively, if the initial state of the storage area is set to "1," an abnormality is determined to have occurred if the value of the storage area is set to "0." In addition to the above monitoring method, a configuration may also be used in which an abnormality is determined to have occurred if the value of a specified byte is different from the value that would normally be set in the storage area.

If it is determined in step S5407 that an abnormality has occurred (step S5408: YES), steps S5409 to S5412 are executed. Specifically, a setting value copy process is first executed (step S5409). In this copy process, the setting value counter information used to identify the setting value of the pachinko machine 10 in the specific control work area 221 is stored in a copy area provided in the specific control work area 221. As a result, even if the setting value counter information is cleared to "0" in the subsequent abnormality clear process (step S5410), it is possible to determine the setting value of the pachinko machine 10 before the abnormality clear process was executed.

Then, an abnormality clearing process is executed (step S5410). In the abnormality clearing process, the specific control work area 221 is cleared to "0" except for the copy area, and the specific control stack area 222, non-specific control work area 223, and non-specific control stack area 224 are cleared to "0". After clearing to "0", initialization is performed. In other words, if the RAM monitoring process determines that an abnormality has occurred in any one of the specific control work area 221, specific control stack area 222, non-specific control work area 223, and non-specific control stack area 224, the specific control work area 221 is cleared to "0" except for the copy area, and the specific control stack area 222, non-specific control work area 223, and non-specific control stack area 224 are cleared to "0". This makes it possible to prevent any processing corresponding to specific control or non-specific control from being executed in the current state if there is a possibility that some kind of information abnormality has occurred in the main RAM 65.

When the stack area 222 for specific control is cleared to "0," the return address information after the RAM monitoring process is executed is also erased. Therefore, when the stack area 222 for specific control is cleared to "0," the process of step S5412 is completed, and then a specific program is returned to. Specifically, the process is configured to return to step S5013 in the main process (Figure 22). However, the program to which the specific control is returned to is not limited to step S5013, but may be step S5221 in the timer interrupt process (Figure 86). Furthermore, when the stack area 222 for specific control is cleared to "0," the stack pointer of the main CPU 63 is also set to the address of the first memory area in the storage order in the stack area 222 for specific control.

Then, an abnormal command indicating that an abnormality clear process has occurred is sent to the audio and light-emitting control device 81 (step S5411). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to a forced clear and outputs a voice message saying "Forced clear has been performed" from the speaker unit 54. The symbol display device 41 also displays a text image saying "Forced clear has been performed." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notifications may be terminated when an operation to terminate the notifications is performed by the amusement hall manager. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By confirming the notification, the amusement hall manager can understand that the main RAM 65 has been forced cleared.

Then, the setting value update process is executed (step S5412). In other words, when an abnormality clear process is executed, the setting value counter in the specific control work area 221 is also cleared to "0," and therefore the setting value update process is executed to reset the setting value of the pachinko machine 10. The processing content of the setting value update process is the same as step S5019 of the main processing (Figure 84). Therefore, each time the update button 68b is pressed, the setting value is updated by one level, and the selected setting value is confirmed when the outlet detection sensor 48a detects a game ball. The setting value being updated and the confirmed setting value are displayed on the third notification display device 69c. Thereafter, when the setting key insertion section 68a switches from the ON state to the OFF state, it is determined that the termination condition for the setting value update process has been met.

The termination condition is not determined to be met simply because the setting key insertion unit 68a is in the OFF state; it is determined to be met when the setting key insertion unit 68a switches from the ON state to the OFF state. When the setting value update process is executed during the RAM monitoring process (Figure 88), the setting key insertion unit 68a is in the OFF state when the setting value update process begins. Therefore, in order to achieve the termination condition for the setting value update process, it is necessary to insert the setting key into the setting key insertion unit 68a, turn it ON, and then turn it OFF. This makes it possible to prevent the setting value update process from terminating even when the proper operation by the amusement hall manager has not been performed.

When the setting key insertion section 68a switches from ON to OFF and the termination condition for the setting value update process is met, step S5111 of the setting value update process (FIG. 85) is executed to compare whether the setting value stored in the copy area of the specific control work area 221 is the same as the setting value currently set in the setting value counter in the specific control work area 221. In other words, it is determined whether the setting value set before the abnormality clear process (step S5410) is executed is the same as the setting value set in the current setting value update process. If the two setting values are the same (step S5112: NO), the non-change notification process (step S5113) is executed, thereby issuing the previously described setting maintenance notification. On the other hand, if the two setting values are different (step S5112: YES), the change notification process (step S5114) is executed, thereby issuing the previously described setting change notification.

The present embodiment described above provides the following excellent effects:

In order for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is started, not only must the setting key insertion section 68a be turned ON, but the reset button 68c must also be pressed, the front door frame 14 must be open, and the gaming machine main body 12 must be open. This makes it difficult to fraudulently execute the setting value update process.

In order for the setting value update process to be executed, the front door frame 14 and the gaming machine main body 12 must be in an open state. As a result, even if someone attempts to execute the setting value update process fraudulently, the front door frame 14 and the gaming machine main body 12 will be in an open state, making the fraudulent activity more noticeable and easier for the gaming hall manager to discover.

In particular, in order to execute the setting value update process, not only does it require the opening of the gaming machine main body 12, which is necessary to expose the main control device 60, but it also requires the opening of the front door frame 14, which makes the fraudulent activity more complicated and makes the fraudulent activity more noticeable.

In a configuration where the system does not return to processing for progressing the game if the setting value update processing is not completed, in order to confirm the setting value selected in the setting value update processing and end the setting value update processing, it is necessary to insert a gaming ball into the outlet 24a, have the outlet detection sensor 48a detect the gaming ball, and then turn off the setting key insertion unit 68a. This makes it difficult to subsequently end the setting value update processing and return to processing for progressing the game, even if the setting value update processing is executed fraudulently.

The setting value that was set before the supply of operating power to the pachinko machine 10 was stopped is compared with the setting value selected in the setting value update process, and a notification is issued depending on whether the two setting values are the same. This allows the amusement hall manager to easily determine whether the setting value was successfully changed through the setting value update process.

By displaying a message to check the setting value on the third notification display device 69c, it is possible to prevent the setting value from being checked while a game is in progress, provided that the game is not in play mode or open/close execution mode, and that the image on the normal picture display unit 38a is not showing a changing image, nor is the normal power open state in which the normal power device 34a can be opened.

In order for the display for confirming the setting value to be displayed on the third notification display device 69c, not only must the setting key insertion section 68a be turned ON, but the front door frame 14 must also be open, and the gaming machine main body 12 must also be open. This makes it difficult to fraudulently display the display for confirming the setting value.

In order for the display for confirming the setting value to be displayed on the third alarm display device 69c, the front door frame 14 and the gaming machine main body 12 must be in an open state. As a result, even if someone attempts to fraudulently display the display for confirming the setting value, the fraudulent activity will be noticeable because the front door frame 14 and the gaming machine main body 12 are in an open state, making it easier for the gaming hall manager to discover the fraudulent activity.

In particular, in order to display the setting value on the third alarm display device 69c, it is necessary not only to open the gaming machine main body 12 to expose the main control device 60, but also to open the front door frame 14, which makes the fraudulent activity more complicated and makes the fraudulent activity more noticeable.

If it is determined that an abnormality has occurred in any one of the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control are cleared to "0". This makes it possible to prevent any processing corresponding to specific control or non-specific control from being executed in the current state if there is a possibility that some kind of information abnormality has occurred in the main RAM 65.

In processing corresponding to specific control, not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control and the stack area 224 for non-specific control are monitored for information anomalies. This simplifies the processing configuration compared to a configuration in which information anomalies are monitored separately for processing corresponding to specific control and processing corresponding to non-specific control.

If it is determined that an abnormality has occurred in any one of the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control, not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0" in the processing corresponding to the specific control. This simplifies the processing configuration compared to a configuration in which "0" clearing is performed separately for processing corresponding to specific control and processing corresponding to non-specific control.

If an abnormality occurs and the abnormality clear process is executed, a setting value update process is executed. This makes it possible to prevent gameplay from proceeding even when a setting value has not been set. In this case, if the setting value set before the abnormality clear process is executed and the setting value set in the setting value update process after the abnormality clear process are executed are the same, a setting maintenance notification is issued. As a result, even if the abnormality clear process is executed, the setting value set in the previous situation is reset, and a setting maintenance notification is issued, making it possible to clearly inform the player that the setting value has not changed even if the abnormality clear process is executed. Incidentally, since it is common for gaming halls to record the setting values of each pachinko machine 10 installed, it is possible to execute the setting value update process after the abnormality clear process is executed so that the recorded setting value is used.

The conditions for executing the setting value update process when the supply of operating power to the pachinko machine 10 is started may be different from those in the above embodiment. Figure 89 is a flowchart showing another form of main processing. In this main processing, steps S5501 to S5506 and steps S5508 to S5520 execute the same processing as steps S5001 to S5019 in the main processing (Figure 84) in the above embodiment. Meanwhile, in this main processing, step S5507 determines whether the operating handle of the launch operating device 28, which is operated to launch game balls into the game area PA, has been rotated from the initial rotation position. Then, when the reset button 68c is pressed (step S5503: YES), the setting key insertion unit 68a is turned ON (step S5504: YES), the front door frame 14 is open relative to the inner frame 13 (step S5505: YES), the gaming machine main body 12 is open relative to the outer frame 11 (step S5506: YES), and the operating handle of the firing operation device 28 is rotated from the initial rotation position (step S5507: YES), the setting value update process (step S5520) is executed. As a result, in order for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is started, not only is it necessary to insert the setting key into the setting key insertion unit 68a and turn it ON, but it is also necessary to rotate the operating handle of the firing operation device 28 so that the supply of operating power to the pachinko machine 10 is started. This makes it difficult to attempt to fraudulently change the setting value. Note that, instead of determining whether the operating handle of the firing operation device 28 has been rotated from the initial rotation position in step S5507, it may be configured to determine whether the firing operation device 28 is being touched by the player.

In addition, the conditions for executing the setting value update process when the supply of operating power to the pachinko machine 10 begins are set to both that the front door frame 14 be open relative to the inner frame 13 and that the gaming machine main body 12 be open relative to the outer frame 11, but it is also possible to set only one of these conditions.

In addition, the condition for executing the setting value update process when the supply of operating power to the pachinko machine 10 begins is that the reset button 68c must be pressed, but this condition may not be set.

Furthermore, a configuration may be adopted in which a condition for executing the setting value update process when the supply of operating power to the pachinko machine 10 is initiated is that the supply of operating power to the pachinko machine 10 is initiated while a gaming ball is detected by the gate detection sensor 49a. As a result, in order for the setting value update process to be executed when the supply of operating power to the pachinko machine 10 is initiated, not only does it require inserting the setting key into the setting key insertion portion 68a and turning it ON, but it also requires that the supply of operating power to the pachinko machine 10 be initiated with a gaming ball remaining in the through gate 35. This makes it more difficult to fraudulently change the setting values.

Furthermore, the operation for confirming the setting value in the setting value update process may be different from that of the above embodiment. Figure 90 is a flowchart showing a different form of setting value update process. In this setting value update process, steps S5601 to S5602 and steps S5604 to S5614 execute the same processing as steps S5101 to S5102 and steps S5104 to S5114 of the setting value update process in the above embodiment (Figure 85). Meanwhile, in this setting value update process, step S5603 does not determine whether the outlet detection sensor 48a has detected a gaming ball, but rather determines whether the ON duration during which the gate detection sensor 49a has continuously output an ON signal is equal to or exceeds the termination reference period (specifically, 5 seconds). If a positive determination is made in step S5603, the selected setting value is confirmed, and the process proceeds to step S5609. With this configuration, in order to confirm the selected setting value, it is necessary to intentionally retain a gaming ball in the through gate 35 for a period equal to or longer than the termination reference period. During normal gameplay, a game ball will not remain in the through gate 35 for longer than the termination reference period. This makes it possible to make the conditions for confirming the selected setting value less likely to be met or less likely to be met during normal gameplay. Furthermore, even if the setting value update process is initiated fraudulently, it becomes more difficult to perform the operation to confirm the selected setting value during the setting value update process.

Furthermore, in the setting value update process, the selected setting value may be confirmed when the operating handle of the firing operation device 28 is rotated from the initial rotation position, or the selected setting value may be confirmed when the firing operation device 28 is touched by the player.

In addition, the setting value update process may be configured so that the selected setting value is confirmed when the special electric detection sensor 45a detects that a gaming ball has entered the special electric winning device 32, which is equipped with an opening/closing member, or so that the selected setting value is confirmed when the second operating port detection sensor 47a detects that a gaming ball has entered the second operating port 34, which is equipped with an opening/closing member. In this case, in order to confirm the selected setting value, it is necessary to manually open the target ball entry port and then handle the gaming ball, making it more difficult to fraudulently change the setting value.

Furthermore, the setting value update process may be configured so that the selected setting value is confirmed based on the detection of a game ball entering the first ball entry section and then the detection of a game ball entering the second ball entry section. In this case, since it is necessary to manually place game balls into multiple ball entry sections in a predetermined order to confirm the selected setting value, it becomes difficult to fraudulently change the setting value. In this case, by making both the first and second ball entry sections ball entry sections that do not have opening and closing members, it becomes possible to prevent an extreme reduction in the ease of performing legitimate work.

Furthermore, during the setting value update process, the setting key insertion section 68a may be switched from the ON state to the OFF state, thereby finalizing the selected setting value and establishing the termination condition for the setting value update process.

Furthermore, the operation for updating the setting value by one step in the setting value update process is not limited to pressing the update button 68b, but may also be configured so that the setting value is updated by one step by pressing the reset button 68c.

Furthermore, when the supply of operating power to the pachinko machine 10 is initiated while the reset button 68c is pressed and the setting key insertion section 68a is turned ON by the setting key, and the front door frame 14 is not open relative to the inner frame 13 or the gaming machine main body 12 is not open relative to the outer frame 11, the configuration is not limited to executing the clear process for non-setting updates (step S5007), and the clear process for non-setting updates may also be not executed. This makes it possible to prevent the clear process for non-setting updates from being executed against the wishes of the gaming hall manager.

Furthermore, if the supply of operating power to the pachinko machine 10 is initiated when the reset button 68c is pressed and the setting key insertion section 68a has not been turned ON by the setting key, and the front door frame 14 is not open relative to the inner frame 13 or the gaming machine main body 12 is not open relative to the outer frame 11, the configuration is not limited to executing the clear process when no setting update is performed (step S5007), and the clear process when no setting update is performed may also be configured not to be performed. This makes it difficult to fraudulently execute the clear process when no setting update is performed.

<Twenty-third embodiment>
In this embodiment, the processing configuration of the main processing differs from that of the 22nd embodiment. The following describes the configuration that differs from the 22nd embodiment. Note that the description of the configuration that is the same as the 22nd embodiment will basically be omitted.

Figure 91 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S5701 to S5720 in the main processing are executed by the main CPU 63 using a specific control program and specific control data.

First, power-on wait processing is executed (step S5701). During this power-on wait processing, the system waits for a predetermined wait time (specifically, one second) to elapse after the main processing is started, without proceeding to the next processing. During this power-on wait processing, the pattern display device 41 starts operating and is initialized. After that, access to the main RAM 65 is permitted (step S5702).

Then, based on the detection results of the front door open sensor 95, it is determined whether the front door frame 14 is open relative to the inner frame 13 (step S5703), based on the detection results of the main body open sensor 96, it is determined whether the gaming machine main body 12 is open relative to the outer frame 11 (step S5704), and it is determined whether the reset button 68c has been pressed (step S5705). If a negative determination is made in any of steps S5703 to S5705, the processing of steps S5706 to S5714 is executed. The processing of these steps S5706 to S5714 is the same as steps S5008 to S5016 in the main processing (Figure 84) in the 22nd embodiment described above.

If a positive judgment is made in all of steps S5703 to S5705, a selection process is executed (step S5715). The selection process executes a process to determine, based on a selection operation by the amusement hall manager, whether the situation is one in which the clear process is executed when no settings are updated and the setting value update process is not executed, or one in which the clear process is executed when settings are updated and the setting value update process is executed. Specifically, each time the update button 68b is pressed once, the state in which one of the above situations is selected is switched to a state in which the other situation is selected. Note that this selection operation may be performed by operating the reset button 68c, or by operating another operating unit. Furthermore, if a situation in which the clear process is performed when no settings are updated and the setting value update process is not performed is selected, the first alert display device 69a displays "O" and the second alert display device 69b and the third alert display device 69c are turned off. If a situation in which the clear process is performed when settings are updated and the setting value update process is performed is selected, the second alert display device 69b displays "O" and the first alert display device 69a and the third alert display device 69c are turned off. Furthermore, if the reset button 68c is pressed continuously for more than the confirmation selection period (specifically, 10 seconds), the selected of the above situations is confirmed as the current selection.

In addition, the configuration may be such that when the update button 68b is continuously pressed for a selection period (specifically, 10 seconds) or longer, the selected one of the above situations is confirmed as the current selection target, or when another operating unit is continuously pressed for a selection period (specifically, 10 seconds) or longer, the selected one of the above situations is confirmed as the current selection target. Alternatively, the configuration may be such that when the operating handle of the firing operating device 28 is rotated, the selected one of the above situations is confirmed as the current selection target.

If, in the selection process, it is determined that the current selection will involve executing the clear process when no setting is updated and not executing the setting value update process (step S5716: NO), the clear process when no setting is updated is executed (step S5717). The processing details of the clear process when no setting is updated are the same as those in step S5007 of the main processing (Figure 84) in the 22nd embodiment described above.

If the selection process determines that the current selection will involve both clear processing during a settings update and a setting value update process (step S5716: YES), the setting value copy process is executed (step S5718), clear processing during a settings update is executed (step S5719), and setting value update processing is executed (step S5720). The processing content of steps S5718 to S5720 is the same as steps S5017 to S5019 in the main processing (Figure 84) in the 22nd embodiment.

With the above configuration, even in a configuration that does not have a setting key insertion unit 68a, the amusement hall manager can select whether to execute the clear process when no settings are updated and not the setting value update process, or to execute the clear process and execute the setting value update process when settings are updated.

In addition, not only when executing the setting value update process but also when executing the clear process when no setting update is performed, when the reset button 68c is pressed, not only does the supply of operating power to the pachinko machine 10 need to be started, but the front door frame 14 needs to be open relative to the inner frame 13, and the gaming machine main body 12 needs to be open relative to the outer frame 11. This makes it difficult to fraudulently execute the clear process when no setting update is performed.

In addition, the conditions for executing the selection process when the supply of operating power to the pachinko machine 10 begins are set to both that the front door frame 14 be open relative to the inner frame 13 and that the gaming machine main body 12 be open relative to the outer frame 11, but it is also possible to set only one of these conditions.

Furthermore, the conditions for executing the selection process when the supply of operating power to the pachinko machine 10 begins may be configured to include an additional condition that the launch handle of the launch operation device 28 is being rotated, or that the launch operation device 28 is being touched, or that a gaming ball is being detected by the gate detection sensor 49a.

<Twenty-fourth embodiment>
In this embodiment, the processing configuration of the RAM monitoring process differs from that of the 22nd embodiment. The following describes the configuration that differs from the 22nd embodiment. Note that the description of the same configuration as the 22nd embodiment will basically be omitted.

Figure 92 is a flowchart showing the RAM monitoring process in this embodiment, which is executed by the main CPU 63. Note that steps S5801 to S5814 in the RAM monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a monitoring process is performed on the specific control work area 221 (step S5801). The content of this monitoring process is the same as step S5401 of the RAM monitoring process (Figure 88) in the 22nd embodiment. If an abnormality is determined to exist in step S5801 (step S5802: YES), steps S5805 to S5808 are executed.

If it is determined in step S5801 that no abnormality exists (step S5802: NO), monitoring processing of the specific control stack area 222 is executed (step S5803). The content of this monitoring processing is the same as step S5403 of the RAM monitoring processing (Figure 88) in the 22nd embodiment described above. If it is determined in step S5803 that an abnormality exists (step S5804: YES), processing of steps S5805 to S5808 is executed.

Regarding the processing of steps S5805 to S5808 in more detail, a setting value copy process is first executed (step S5805). In this copy process, the setting value counter information used to identify the setting value of the pachinko machine 10 in the specific control work area 221 is stored in a copy area provided in the specific control work area 221. As a result, even if the setting value counter information is cleared to "0" in the subsequent abnormality clear process (step S5806), it is possible to determine the setting value of the pachinko machine 10 before the abnormality clear process was executed.

Then, a clearing process is performed in the event of an abnormality (step S5806). In the clearing process in the event of an abnormality, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". After clearing to "0", initialization is performed. On the other hand, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". In other words, in the RAM monitoring process of this embodiment, if it is determined that an abnormality has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". This makes it possible to prevent processing corresponding to specific control from being executed in the current state if there is a possibility that an information abnormality has occurred in the work area 221 for specific control or the stack area 222 for specific control. Furthermore, even if an information abnormality occurs in the work area 221 for specific control or the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0", which makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 221 for specific control or the stack area 222 for specific control.

When the stack area 222 for specific control is cleared to "0," the return address information after the RAM monitoring process is executed is also erased. Therefore, when the stack area 222 for specific control is cleared to "0," the process of step S5808 is completed, and then a specific program is returned to. Specifically, the process is configured to return to step S5013 in the main process (Figure 22). However, the program to which the specific control is returned to is not limited to step S5013, but may be step S5221 in the timer interrupt process (Figure 86). Furthermore, when the stack area 222 for specific control is cleared to "0," the stack pointer of the main CPU 63 is also set to the address of the first storage area in the storage order in the stack area 222 for specific control.

Then, an abnormal command indicating that an abnormality clear process has occurred is sent to the audio and light-emitting control device 81 (step S5807). Upon receiving the abnormal command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to a forced clear and outputs a voice message saying "Forced clear has been performed" from the speaker unit 54. The symbol display device 41 also displays a text image saying "Forced clear has been performed." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notification may be terminated when an operation to terminate the notification is performed by the amusement hall manager. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By confirming the notification, the amusement hall manager can understand that the specific control work area 221 and the specific control stack area 222 have been forcibly cleared.

Then, the setting value update process is executed (step S5808). The processing content of the setting value update process is the same as step S5412 in the RAM monitoring process (Figure 88) in the 22nd embodiment described above.

If neither step S5801 nor step S5803 determines that an abnormality exists (step S5802 and step S5804: NO), monitoring processing of the non-specific control work area 223 is executed (step S5809). The content of this monitoring processing is the same as step S5405 of the RAM monitoring processing (FIG. 88) in the 22nd embodiment described above. If step S5809 determines that an abnormality exists (step S5810: YES), the non-specific control work area 223 is cleared to "0" and initialized (step S5811). In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0." This makes it possible to resolve the information abnormality in the non-specific control work area 223.

On the other hand, in step S5811, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0." This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control from being cleared to "0" even if an information abnormality occurs in the work area 223 for non-specific control.

In step S5811, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the calculation result storage area 234 may be cleared to "0" but the management start flag may not be cleared to "0." In step S5811, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the management start flag may be cleared to "0" but the calculation result storage area 234 may not be cleared to "0." In step S5811, the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 may be cleared to "0" but the calculation result storage area 234 and the management start flag may not be cleared to "0."

If a negative determination is made in step S5810 or if the processing of step S5811 is executed, monitoring processing of the stack area 224 for non-specific control is executed (step S5812). The content of this monitoring processing is the same as step S5407 of the RAM monitoring processing (Figure 88) in the 22nd embodiment described above. If an abnormality is determined to exist in step S5812 (step S5813: YES), the stack area 224 for non-specific control is cleared to "0" and initialized (step S5814). This makes it possible to resolve the information abnormality in the stack area 224 for non-specific control.

On the other hand, in step S5814, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0." This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control from being cleared to "0" even if an information abnormality occurs in the stack area 224 for non-specific control.

With the above configuration, if it is determined that an abnormality has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is also cleared to "0." This makes it possible to prevent processing corresponding to specific control from being executed in the current state if there is a possibility that some kind of information abnormality has occurred in the work area 221 for specific control or the stack area 222 for specific control.

Even if an information abnormality occurs in the work area 221 for specific control or the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0." This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 221 for specific control or the stack area 222 for specific control.

Even if an information abnormality occurs in the work area 223 for non-specific control, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control will not be cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 223 for non-specific control.

Even if an information abnormality occurs in the stack area 224 for non-specific control, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control will not be cleared to "0". This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control from being cleared to "0" as a result of an information abnormality in the stack area 224 for non-specific control.

In addition, if an information abnormality occurs in the work area 221 for specific control, the work area 221 for specific control, excluding the copy area, may be cleared to "0", while the stack area 222 for specific control may not be cleared to "0".

Also, if an information anomaly occurs in the stack area 222 for specific control, the stack area 222 for specific control may be cleared to "0," but the work area 221 for specific control may not be cleared to "0." In this case, the processing of steps S5805 to S5808 may not be executed even if the stack area 222 for specific control is cleared to "0."

<Twenty-fifth embodiment>
In this embodiment, the processing configuration for monitoring whether or not an information anomaly has occurred in each of the areas 221 to 224 of the main RAM 65 differs from that of the 22nd embodiment. The configuration that differs from the 22nd embodiment will be described below. Note that a description of the same configuration as the 22nd embodiment will basically be omitted.

Figure 93 is a flowchart showing the RAM monitoring process in this embodiment, which is executed by the main CPU 63. Note that steps S5901 to S5908 in the RAM monitoring process are executed by the main CPU 63 using a specific control program and specific control data.

First, a monitoring process is performed on the specific control work area 221 (step S5901). The content of this monitoring process is the same as step S5401 of the RAM monitoring process (Figure 88) in the 22nd embodiment. If an abnormality is determined to exist in step S5901 (step S5902: YES), steps S5905 to S5908 are executed.

If it is determined in step S5901 that no abnormality exists (step S5902: NO), monitoring processing of the specific control stack area 222 is executed (step S5903). The content of this monitoring processing is the same as step S5403 of the RAM monitoring processing (Figure 88) in the 22nd embodiment described above. If it is determined in step S5903 that an abnormality exists (step S5904: YES), processing of steps S5905 to S5908 is executed.

Regarding the processing of steps S5905 to S5908 in more detail, a setting value copy process is first executed (step S5905). In this copy process, the setting value counter information used to identify the setting value of the pachinko machine 10 in the specific control work area 221 is stored in a copy area provided in the specific control work area 221. As a result, even if the setting value counter information is cleared to "0" in the subsequent abnormality clear process (step S5906), it is possible to determine the setting value of the pachinko machine 10 before the abnormality clear process was executed.

Then, a clearing process is performed in the event of an abnormality (step S5906). In the clearing process in the event of an abnormality, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". After clearing to "0", initialization is performed. On the other hand, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". In other words, in the RAM monitoring process of this embodiment, if it is determined that an abnormality has occurred in either the work area 221 for specific control or the stack area 222 for specific control, the work area 221 for specific control is cleared to "0" except for the copy area, and the stack area 222 for specific control is cleared to "0". This makes it possible to prevent processing corresponding to specific control from being executed in the current state if there is a possibility that an information abnormality has occurred in the work area 221 for specific control or the stack area 222 for specific control. Furthermore, even if an information abnormality occurs in the work area 221 for specific control or the stack area 222 for specific control, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0", which makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" as a result of an information abnormality in the work area 221 for specific control or the stack area 222 for specific control.

Then, an abnormal command indicating that an abnormality clear process has occurred is sent to the audio and light-emitting control device 81 (step S5907). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display and light-emitting unit 53 to emit light in a manner corresponding to the forced clearing of the specific control work area 221 and the specific control stack area 222, and causes the speaker unit 54 to output a voice message stating, "A forced clear has been executed for specific control." The symbol display device 41 also displays a text image stating, "A forced clear has been executed for specific control." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notifications may be terminated when an operation to terminate the notification is performed by the gaming hall manager. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By checking the above notification, the amusement hall manager can understand that the specific control work area 221 and the specific control stack area 222 have been forcibly cleared.

Then, the setting value update process is executed (step S5908). The processing content of the setting value update process is the same as step S5412 in the RAM monitoring process (Figure 88) in the 22nd embodiment described above.

As described above, in the RAM monitoring process executed using the specific control program and specific control data, the specific control work area 221 and the specific control stack area 222 are monitored for information anomalies, but the non-specific control work area 223 and the non-specific control stack area 224 are not monitored for information anomalies. Monitoring of the non-specific control work area 223 and the non-specific control stack area 224 for information anomalies is performed in the process corresponding to the non-specific control, in which the non-specific control program and non-specific control data are used.

Figure 94 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that, as with the 15th embodiment, the management execution process is executed by reading out a subroutine program in the management process (Figure 70). Furthermore, steps S6001 to S6016 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

Steps S6001 to S6008 and steps S6010 to S6016 execute the same processing as steps S3901 to S3915 of the management execution process (Figure 71) in the fifteenth embodiment described above. Furthermore, step S6009 executes a separate monitoring process. When the separate monitoring process is executed, a subroutine program corresponding to the separate monitoring process set in the non-specific control program is executed. When the subroutine program is executed, information for specifying the return address of the management execution process after the separate monitoring process is executed is written to the non-specific control stack area 224 by a push command. When the separate monitoring process is completed, information for specifying the return address is read by a pop command, and processing returns to the management execution process program indicated by the return address.

Figure 95 is a flowchart showing the separate monitoring process. Note that steps S6101 to S6108 in the separate monitoring process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, a monitoring process is performed on the non-specific control work area 223 (step S6101). The content of this monitoring process is the same as step S5405 of the RAM monitoring process (Figure 88) in the 22nd embodiment. If an abnormality is determined to exist in step S6101 (step S6102: YES), the non-specific control work area 223 is cleared to "0" and initialized (step S6103). In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0." This makes it possible to resolve the information abnormality in the non-specific control work area 223.

On the other hand, in step S6103, the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control are not cleared to "0." This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control from being cleared to "0" even if an information abnormality occurs in the work area 223 for non-specific control.

In step S6103, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the calculation result storage area 234 may be cleared to "0" but the management start flag may not be cleared to "0." In step S6103, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, and the management start flag may be cleared to "0" but the calculation result storage area 234 may not be cleared to "0." In step S6103, the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 may be cleared to "0" but the calculation result storage area 234 and the management start flag may not be cleared to "0."

Then, a clear notification process is executed (step S6104). In the clear notification process, a command indicating that the work area 223 for non-specific control has been cleared to "0" is sent to the audio/light-emitting control device 81. Upon receiving this command, the audio/light-emitting control device 81 causes the display/light-emitting unit 53 to emit light in a manner corresponding to the forced clearing of the work area 223 for non-specific control, and causes the speaker unit 54 to output a voice message stating, "The history information has been forcibly cleared." Furthermore, the symbol display device 41 is caused to display a text image stating, "The history information has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notification may be terminated when an operation to terminate the notification is performed by the gaming hall manager. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By checking the above notification, the gaming hall manager will be able to understand that the non-specific control work area 223 has been forcibly cleared.

If a negative determination is made in step S6102 or if the processing of step S6104 is executed, monitoring processing of the stack area 224 for non-specific control is executed (step S6105). The content of this monitoring processing is the same as step S5407 of the RAM monitoring processing (Figure 88) in the 22nd embodiment described above. If an abnormality is determined to exist in step S6105 (step S6106: YES), the stack area 224 for non-specific control is cleared to "0" and initialized (step S6107). This makes it possible to resolve the information abnormality in the stack area 224 for non-specific control.

On the other hand, in step S6107, the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control are not cleared to "0." This makes it possible to prevent the work area 221 for specific control, the stack area 222 for specific control, and the work area 223 for non-specific control from being cleared to "0" even if an information abnormality occurs in the stack area 224 for non-specific control.

Then, a clear notification process is executed (step S6108). In the clear notification process, a command indicating that the non-specific control stack area 224 has been cleared to "0" is sent to the audio and light-emitting control device 81. Upon receiving this command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the forced clearing of the non-specific control stack area 224 and causes the speaker unit 54 to output a voice message stating, "The non-specific control stack has been forcibly cleared." Furthermore, the symbol display device 41 is caused to display a text image stating, "The non-specific control stack has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notification may be terminated when an operation to terminate the notification is performed by the gaming hall manager. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By checking the above notification, the gaming hall manager will be able to understand that the non-specific control stack area 224 has been forcibly cleared.

When the stack area 224 for non-specific control is forcibly cleared, the address of the program in step S6010 in the management execution process (Figure 94) is uniquely set as the return address information after execution of another monitoring process. This makes it possible to return to the program to which the management execution process should originally return, even if the stack area 224 for non-specific control is forcibly cleared. Furthermore, when the stack area 224 for non-specific control is forcibly cleared, the stack pointer of the main CPU 63 is also set to the address of the first storage area in the storage order in the stack area 224 for non-specific control.

With the above configuration, monitoring for information anomalies in the work area 221 for specific control and the stack area 222 for specific control is performed by processing corresponding to specific control in the main CPU 63, and monitoring for information anomalies in the work area 223 for non-specific control and the stack area 224 for non-specific control is performed by processing corresponding to non-specific control in the main CPU 63. This not only clearly distinguishes between the areas 221-224 of the main RAM 65 that are used in processing corresponding to specific control and processing corresponding to non-specific control, but also clearly distinguishes between the areas 221-224 of the main RAM 65 that are monitored.

When the work area 223 for non-specific control is cleared to "0," the information in various registers of the main CPU 63 used in the processing corresponding to specific control and saved in the work area 223 for non-specific control is also cleared to "0." In this case, even if the processing corresponding to non-specific control ends and returns to the processing corresponding to specific control, it may not be possible to return to the state before the processing corresponding to non-specific control began. Therefore, when the work area 223 for non-specific control is cleared to "0," the work area 221 for specific control and the stack area 222 for specific control may also be cleared to "0." In this configuration, since the setting value counter in the work area 221 for specific control is also cleared to "0," the setting value update process may be executed first as the processing corresponding to specific control when returning from the processing corresponding to non-specific control to the processing corresponding to specific control.

<Twenty-sixth embodiment>
In this embodiment, the processing configuration of the management process differs from that of the twentieth embodiment. The following describes the configuration that differs from the twentieth embodiment. Note that the description of the configuration that is the same as that of the twentieth embodiment will basically be omitted.

Figure 96 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S6201 to S6219 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 69) (step S6201). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, the information in the stack pointer of the primary CPU 63 is overwritten in the HL register of the primary CPU 63 by a load command, "LD HL, SP" (step S6202). In this case, since the stack pointer contains 16 bits of information and the H and L registers each contain 8 bits of information, the 8 consecutive bits from the upper side of the stack pointer are overwritten in the H register, and the 8 consecutive bits from the lower side of the stack pointer are overwritten in the L register.

Then, a load command is issued to clear to "0" a 1-byte storage area in the specific control stack area 222 corresponding to the stack pointer information stored in the HL register of the primary CPU 63, as "LD (HL), 0" (step S6203). Note that the HL register of the primary CPU 63 has been overwritten with the stack pointer information of the primary CPU 63 in step S6202, and the stack pointer information of the primary CPU 63 has not been updated by the time the processing of step S6203 is executed. Therefore, in step S6203, the 1-byte storage area in the specific control stack area 222 corresponding to the stack pointer information of the primary CPU 63 is cleared to "0."

Then, using the load command "LD SP, SP-1," the stack pointer information of the primary CPU 63 is updated to the address information of the next storage area to be written in the specific control stack area 222 (step S6204). When the specific control stack area 222 is used, the storage target information is stored starting from the storage area with the last address in the specific control stack area 222. Each time new information to be stored is added, the storage target storage area is changed toward the first address in the specific control stack area 222. Therefore, in step S6204, the stack pointer information of the primary CPU 63 is updated to the address information corresponding to the storage area one address smaller in the specific control stack area 222. By executing the processing of step S6204, the next storage area is set as the storage target for information to be stored in response to the next push command, relative to the storage area cleared to "0" in step S6203, and the storage area cleared to "0" in step S6203 is set as the storage target for information to be read in response to the next pop command.

Then, the WA register of the primary CPU 63 is cleared to "0" by a load command as "LD WA, 0" (step S6205). The BC register of the primary CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S6206). The DE register of the primary CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S6207). The HL register of the primary CPU 63 is cleared to "0" by a load command as "LD HL, 0" (step S6208). The IX register of the primary CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S6209). The IY register of the primary CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S6210).

In addition to the flag register, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S6205 to S6210, some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, are cleared to "0." The WA register, BC register, DE register, HL register, IX register, and IY register are used in the management execution process (step S6212), which corresponds to non-specific control. By clearing these registers to "0" prior to the execution of the management execution process (step S6212), which corresponds to non-specific control, the state of these registers can be restored to the state they were in immediately after the supply of operating power to the main CPU 63 was initiated, before the process corresponding to non-specific control was initiated.

In addition, the information in the WA register, BC register, DE register, HL register, IX register, and IY register before processing corresponding to non-specific control begins is unnecessary for processing corresponding to specific control after processing corresponding to that non-specific control has ended. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in processing corresponding to specific control that is restored after processing corresponding to non-specific control has ended.

Then, using the pop command "POP PSW," information is read from the memory area in the specific control stack area 222 that corresponds to the information of the stack pointer of the primary CPU 63, which is the previous memory area in the write order, and the read information is overwritten in the flag register of the primary CPU 63 (step S6211). The stack pointer information of the primary CPU 63 immediately before the pop command of step S6211 is the information corresponding to the memory area in the specific control stack area 222 that corresponds to the next memory area in the write order, which was cleared to "0" in step S6203. Therefore, the memory area in the specific control stack area 222 that corresponds to the information of the stack pointer of the primary CPU 63, which is the previous memory area in the write order, is the memory area cleared to "0" in step S6203. The information read from this memory area is then overwritten in the flag register of the primary CPU 63, causing the flag register to be cleared to "0." Note that each storage area in the stack area 222 for specific control has an information capacity of 8 bits (1 byte), and the flag register of the main CPU 63 also has an information capacity of 8 bits (1 byte). By clearing the flag register to "0" prior to execution of the management execution process (step S6212), which is a process corresponding to non-specific control, the state of the flag register can be set to the state it was in immediately after the supply of operating power to the main CPU 63 began, before the process corresponding to non-specific control began.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S6212). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

The processing content of the management execution process is the same as that of the management execution process (Figure 82) in the 20th embodiment described above. Therefore, after the check process in the management execution process is completed, the WA register, BC register, DE register, HL register, IX register, and IY register are cleared to "0." This clears these registers to "0" prior to returning from processing corresponding to non-specific control to processing corresponding to specific control, making it possible to restore the state of these registers to the state they were in immediately after the supply of operating power to the main CPU 63 began before returning to processing corresponding to specific control.

When returning to the management processing program after the management execution process has been executed, a process is executed to clear the flag register of the main CPU 63 to "0." Specifically, first, a "PUSH HL" push command is issued to save the information in the HL register of the main CPU 63 to the specific control stack area 222 (step S6213). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the next memory area in the write order relative to the memory area in the specific control stack area 222 where the HL register information was saved.

Then, the information in the stack pointer of the primary CPU 63 is overwritten in the HL register of the primary CPU 63 by a load command, "LD HL, SP" (step S6214). In this case, since the stack pointer contains 16 bits of information and the H and L registers each contain 8 bits of information, the 8 consecutive bits from the upper side of the stack pointer are overwritten in the H register, and the 8 consecutive bits from the lower side of the stack pointer are overwritten in the L register.

Then, a load command is issued to clear to "0" a 1-byte storage area in the specific control stack area 222 corresponding to the stack pointer information stored in the HL register of the primary CPU 63, as "LD (HL), 0" (step S6215). Note that the HL register of the primary CPU 63 was overwritten with the stack pointer information of the primary CPU 63 in step S6214, and the stack pointer information of the primary CPU 63 had not been updated by the time the processing of step S6215 was executed. Therefore, in step S6215, the 1-byte storage area in the specific control stack area 222 corresponding to the stack pointer information of the primary CPU 63 is cleared to "0."

Then, using the load command "LD SP, SP-1," the stack pointer information of the primary CPU 63 is updated to the address information of the next storage area to be written in the specific control stack area 222 (step S6216). When the specific control stack area 222 is used, the storage target information is stored starting from the storage area with the last address in the specific control stack area 222. Each time new information to be stored is added, the storage target storage area is changed toward the first address in the specific control stack area 222. Therefore, in step S6216, the stack pointer information of the primary CPU 63 is updated to the address information corresponding to the storage area one address smaller in the specific control stack area 222. By executing the processing of step S6216, the next storage area is set as the storage target for information to be stored in response to the next push command, relative to the storage area cleared to "0" in step S6215, and the storage area cleared to "0" in step S6215 is set as the storage target for information to be read in response to the next pop command.

Then, using the pop command "POP PSW," information is read from the previous storage area in the specific control stack area 222 corresponding to the information of the stack pointer of the primary CPU 63, and the read information is overwritten in the flag register of the primary CPU 63 (step S6217). The stack pointer information of the primary CPU 63 immediately before the pop command of step S6217 is the information corresponding to the next storage area in the specific control stack area 222 in the write order relative to the storage area in the specific control stack area 222 cleared to "0" in step S6215. Therefore, the previous storage area in the specific control stack area 222 in the write order relative to the storage area corresponding to the information of the stack pointer of the primary CPU 63 in the specific control stack area 222 is the storage area in the specific control stack area 222 cleared to "0" in step S6215. The information read from this storage area is then overwritten in the flag register of the primary CPU 63, causing the flag register to be cleared to "0." Note that each storage area in the stack area 222 for specific control has an information capacity of 8 bits (1 byte), and the flag register of the main CPU 63 also has an information capacity of 8 bits (1 byte). By clearing the flag register to "0" after executing the management execution process (step S6212), which is a process corresponding to non-specific control, the state of the flag register can be set to the state immediately after the supply of operating power to the main CPU 63 begins after the process corresponding to non-specific control has ended. Furthermore, when the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to the information corresponding to the previous storage area in the write order in the stack area 222 for specific control.

Then, the pop command "POP HL" is issued to restore the HL register information saved in the specific control stack area 222 in step S6213 to the HL register of the main CPU 63 (step S6218). Note that the HL register was cleared to "0" immediately before the management execution process (step S6212) ended, so in step S6213, the "0"-cleared information was saved in the specific control stack area 222, and in step S6218, the "0"-cleared information was restored to the HL register of the main CPU 63. Consequently, the HL register of the main CPU 63 is cleared to "0." Furthermore, when the pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S6219). This allows new execution of timer interrupt processing.

The above configuration can achieve the following effects in addition to those described in the 20th embodiment.

This configuration clears the flag register of the main CPU 63 to "0" when processing corresponding to non-specific control is initiated from a situation where processing corresponding to specific control is being executed. This eliminates the need to save the flag register information used in processing corresponding to specific control in the main RAM 65 when processing corresponding to non-specific control is being executed. Therefore, there is no need to reserve capacity for saving this information.

The flag register of the main CPU 63 is also cleared to "0" when returning to processing corresponding to specific control from a situation where processing corresponding to non-specific control is being executed. This makes it possible to restore the state of the flag register to the state it was in immediately before processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

The state in which the flag register is cleared to "0" is the state when the supply of operating power to the main CPU 63 begins. This simplifies the processing configuration for setting the flag register to a predetermined state when starting processing corresponding to non-specific control and when returning to processing corresponding to specific control.

The information in the flag register of the main CPU 63 before processing corresponding to non-specific control begins is information that is not used in processing corresponding to specific control after processing corresponding to non-specific control ends. This makes it possible to prevent the processing corresponding to specific control after processing corresponding to non-specific control ends from being affected, even if the flag register is configured to be cleared to "0" when processing corresponding to non-specific control begins.

This configuration clears a specified memory area in the specific control stack area 222 to "0," and then overwrites the flag register with the information from that memory area using a pop command, thereby clearing the flag register to "0." This makes it possible to clear the flag register to "0" even in a configuration where direct clearing of the flag register to "0" using a load command is restricted.

Instead of clearing the flag register to "0," the flag register may be initialized. That is, when the supply of operating power to the main CPU 63 begins, the flag register of the main CPU 63 is first cleared to "0" and then information is set to its initial state. However, the flag register may be set to this initial state in steps S6202 to S6204 and step S6211. In this case, by configuring the flag register to be set to the initial state in steps S6213 to S6218 as well, it is possible to restore the state of the flag register to the state it was in immediately before the processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

In addition, instead of clearing the flag register of the main CPU 63 to "0" in steps S6202 to S6204 and step S6211, all flag registers may be set to "1." In this case, by also setting all flag registers to "1" in steps S6213 to S6218, when returning to processing corresponding to specific control, it is possible to restore the state of the flag register to the state it was in immediately before processing corresponding to non-specific control was started.

Also, instead of the processing of steps S6202 to S6204 and step S6211, the flag register of the primary CPU 63 may be directly cleared to "0" by a load command using "LD PSW, 0." Also, instead of the processing of steps S6213 to S6218, the flag register of the primary CPU 63 may be directly cleared to "0" by a load command using "LD PSW, 0."

In addition, instead of executing the processing of steps S6213 and S6218, the HL register may be cleared to "0" by a load command such as "LD HL, 0." Even in this case, it is possible to restore the state of the HL register to the state it was in immediately before the management execution process, which is a process corresponding to non-specific control, was executed.

In addition, instead of a configuration in which the process of clearing the flag register to "0" is performed by a process corresponding to specific control, it may be performed by a process corresponding to non-specific control.

<Twenty-seventh embodiment>
In this embodiment, the processing configuration of the management process differs from that of the twentieth embodiment. The following describes the configuration that differs from the twentieth embodiment. Note that the description of the configuration that is the same as that of the twentieth embodiment will basically be omitted.

Figure 97 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S6301 to S6323 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 69) (step S6301). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, using the push command "PUSH AF," the information in the A register and the flag register of the primary CPU 63 are saved to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area that is next in the write order relative to that memory area (step S6302). Because the A register and flag register of the primary CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and the flag register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, the pop command "POP HL" overwrites the A register information and flag register information saved in the specific control stack area 222 in step S6302 into the HL register of the main CPU 63 (step S6303). In this case, the A register information saved in the specific control stack area 222 is overwritten into the H register of the main CPU 63, and the flag register information saved in the specific control stack area 222 is overwritten into the L register of the main CPU 63. The H register and L register of the main CPU 63 each hold 8 bits (1 byte) of information. Note that when the above pop command is executed, the stack pointer information of the main CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, the A register of the master CPU 63 is cleared to "0" by a load command as "LD A,0" (step S6304). Then, the information in the A register of the master CPU 63 is overwritten in the L register of the master CPU 63 by a load command as "LD L,A" (step S6305), and the information in the A register of the master CPU 63 is overwritten in the H register of the master CPU 63 by a load command as "LD H,A" (step S6306). Because the A register was cleared to "0" in step S6304, overwriting the information in the A register into each of the L register and H register clears both the L register and H register to "0".

Then, using the push command "PUSH HL," the information in the HL register (i.e., the H register and L register) of the primary CPU 63 is saved to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area with the next write order relative to that memory area (step S6307). Because the H register and L register of the primary CPU 63 each hold 8 bits (1 byte), the information in the H register and the information in the L register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, the BC register of the primary CPU 63 is cleared to "0" by a load command as "LD BC, 0" (step S6308). The DE register of the primary CPU 63 is cleared to "0" by a load command as "LD DE, 0" (step S6309). The IX register of the primary CPU 63 is cleared to "0" by a load command as "LD IX, 0" (step S6310). The IY register of the primary CPU 63 is cleared to "0" by a load command as "LD IY, 0" (step S6311).

In addition to the flag register, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S6308 to S6311, some of these general-purpose registers, auxiliary registers, and index registers, namely the BC register, DE register, IX register, and IY register, are cleared to "0." Additionally, in steps S6305 and S6306, the HL register is cleared to "0." The BC register, DE register, HL register, IX register, and IY register are used in the management execution process (step S6313), which corresponds to non-specific control. By clearing these registers to "0" prior to the execution of the management execution process (step S6313), which corresponds to non-specific control, the state of these registers can be restored to the state they were in immediately after the supply of operating power to the main CPU 63 was initiated, before the process corresponding to non-specific control was initiated.

In addition, the information in the BC register, DE register, HL register, IX register, and IY register before processing corresponding to non-specific control begins is unnecessary for processing corresponding to specific control after processing corresponding to that non-specific control has ended. Therefore, even if the information in these registers is cleared to "0" without being saved, no problems will arise in processing corresponding to specific control that is restored after processing corresponding to non-specific control has ended.

Then, using the pop command "POP AF," the H register information and L register information saved in the specific control stack area 222 in step S6307 are overwritten onto the A register and flag register of the primary CPU 63 (step S6312). In this case, the H register information saved in the specific control stack area 222 is overwritten onto the A register of the primary CPU 63, and the L register information saved in the specific control stack area 222 is overwritten onto the flag register of the primary CPU 63. Because the H register information and L register information saved in the specific control stack area 222 are all "0," execution of step S6312 clears the A register of the primary CPU 63 to "0" and also clears the flag register of the primary CPU 63 to "0." This allows the flag register to be set to the state it was in immediately after the supply of operating power to the primary CPU 63 was initiated, before processing corresponding to non-specific control was initiated. When the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places earlier in the write order in the specific control stack area 222.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S6313). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

After the check process is completed in the management execution process, the BC register, DE register, HL register, IX register, and IY register are cleared to "0." This clears these registers to "0" prior to returning from processing corresponding to non-specific control to processing corresponding to specific control, making it possible to restore the state of these registers to the state they were in immediately after the supply of operating power to the main CPU 63 began before returning to processing corresponding to specific control.

When returning to the management processing program after the management execution process has been executed, a process is executed to clear the flag register of the main CPU 63 to "0." Specifically, first, a "PUSH HL" push command is issued to save the information in the HL register of the main CPU 63 to the specific control stack area 222 (step S6314). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the next memory area in the write order relative to the memory area in the specific control stack area 222 where the HL register information was saved.

Then, a push command is issued as "PUSH AF" to save the information in the A register and flag register of the primary CPU 63 to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area that is next in the write order relative to that memory area (step S6315). Because the A register and flag register of the primary CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, the pop command "POP HL" overwrites the A register information and flag register information saved in the specific control stack area 222 in step S6315 into the HL register of the primary CPU 63 (step S6316). In this case, the A register information saved in the specific control stack area 222 is overwritten into the H register of the primary CPU 63, and the flag register information saved in the specific control stack area 222 is overwritten into the L register of the primary CPU 63. The H register and L register of the primary CPU 63 each hold 8 bits (1 byte) of information. Note that when the pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, the A register of the master CPU 63 is cleared to "0" by a load command as "LD A,0" (step S6317). Then, the information in the A register of the master CPU 63 is overwritten in the L register of the master CPU 63 by a load command as "LD L,A" (step S6318), and the information in the A register of the master CPU 63 is overwritten in the H register of the master CPU 63 by a load command as "LD H,A" (step S6319). Because the A register was cleared to "0" in step S6317, overwriting the information in the A register into each of the L register and H register clears both the L register and H register to "0".

Then, using the push command "PUSH HL," the information in the HL register (i.e., the H register and L register) of the primary CPU 63 is saved to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area with the next write order relative to that memory area (step S6320). Because the H register and L register of the primary CPU 63 each hold 8 bits (1 byte) of information, the information in the H register and the L register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

After that, the pop command "POP AF" overwrites the A register and flag register of the master CPU 63 with the H register information and L register information saved in the specific control stack area 222 in step S6320 (step S6321). In this case, the H register information saved in the specific control stack area 222 is overwritten in the A register of the master CPU 63, and the L register information saved in the specific control stack area 222 is overwritten in the flag register of the master CPU 63. Because the H register information and L register information saved in the specific control stack area 222 are all "0" information, execution of the processing of step S6321 clears the A register of the master CPU 63 to "0" and also clears the flag register of the master CPU 63 to "0". By clearing the flag register to "0" after the management execution process (step S6313), which is a process corresponding to non-specific control, is executed, the state of the flag register can be set to the state immediately after the supply of operating power to the main CPU 63 begins after the process corresponding to non-specific control is completed. Note that when the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places earlier in the writing order in the stack area 222 for specific control.

Then, the pop command "POP HL" is executed to restore the HL register information saved in the specific control stack area 222 in step S6314 to the HL register of the main CPU 63 (step S6322). Note that the HL register was cleared to "0" immediately before the management execution process (step S6313) ended, so in step S6314, the "0"-cleared information is saved in the specific control stack area 222, and in step S6322, the "0"-cleared information is restored to the HL register of the main CPU 63. As a result, the HL register of the main CPU 63 is cleared to "0." Furthermore, when the pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S6323). This allows new execution of timer interrupt processing.

With the above configuration, it is possible to clear the flag register of the main CPU 63 to "0" without executing the process of clearing a specified memory area in the stack area 222 for specific control to "0" using a load command. This makes it possible to clear the flag register of the main CPU 63 to "0" even in a configuration in which clearing a specified memory area in the stack area 222 for specific control to "0" using a load command is restricted.

Instead of clearing the flag register to "0," the flag register may be initialized. That is, when the supply of operating power to the main CPU 63 begins, the flag register of the main CPU 63 is first cleared to "0" and then information is set to its initial state. However, the flag register may be set to this initial state in steps S6302 to S6307 and step S6312. In this case, by setting the flag register to the initial state in steps S6314 to S6322 as well, it is possible to restore the state of the flag register to the state it was in immediately before the processing corresponding to non-specific control was started when returning to processing corresponding to specific control.

Furthermore, instead of clearing the flag register of the main CPU 63 to "0" in steps S6302 to S6307 and step S6312, all flag registers may be set to "1." In this case, by also setting all flag registers to "1" in steps S6314 to S6322, when returning to processing corresponding to specific control, it is possible to restore the state of the flag register to the state it was in immediately before processing corresponding to non-specific control was started.

Furthermore, the processing of steps S6302 and S6303 may not be performed. In this case, the processing configuration can be simplified.

Furthermore, the processing of steps S6315 and S6316 may not be performed. In this case, the processing configuration can be simplified.

In addition, instead of performing the processing of steps S6302 to S6306, a configuration may be used in which the HL register is cleared to "0" by a load command ("LD HL, 0"), the HL register cleared to "0" is then saved to the specific control stack area 222 by a push command, and the saved information is then restored to the AF register by a pop command, thereby clearing the flag register of the main CPU 63 to "0."

In addition, instead of a configuration in which the process of clearing the flag register to "0" is performed by a process corresponding to specific control, it may be performed by a process corresponding to non-specific control.

<Twenty-eighth embodiment>
In this embodiment, the processing configuration of the management process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 98 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S6401 to S6416 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 69) (step S6401). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, using the push command "PUSH WA," the information in the WA register (i.e., the W register and A register) of the primary CPU 63 is saved to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area with the next write order relative to that memory area (step S6402). Because the W register and A register of the primary CPU 63 each hold 8 bits (1 byte) of information, the information in the W register and A register is saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, the information in the flag register of the primary CPU 63 is overwritten in the A register of the primary CPU 63 by a load command using "LD A, PSW" (step S6403). In this case, the information capacity of both the flag register and the A register is 8 bits (1 byte). Then, the information in the A register of the primary CPU 63 is saved to the FG buffer set in the work area 221 for specific control by a load command using "LD (_FGBUF), A" (step S6404). Because the A register has been overwritten with the information from the flag register in step S6403, execution of step S6404 results in the information in the flag register being saved in the work area 221 for specific control.

Then, a pop command "POP WA" is issued to restore the information in the WA register that was saved in the specific control stack area 222 in step S6402 to the WA register of the main CPU 63 (step S6405). This makes it possible to restore the state of the A register to the state it was in before the save, even if the A register was used to save the flag register information to the specific control work area 221. Note that when the pop command is executed, the information in the stack pointer of the main CPU 63 is updated to the information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S6406). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

The processing content of the management execution process is the same as that of the management execution process (Figure 71) in the fifteenth embodiment described above. Therefore, before the check process in the management execution process is started, the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the non-specific control work area 223, and after the check process in the management execution process is completed, the information saved in the non-specific control work area 223 is restored to the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63. This makes it possible to maintain the same state for the WA register, BC register, DE register, HL register, IX register, and IY register of the main CPU 63 before and after the check process.

However, this is not limited to this, and the processing content of the management execution process may be configured to be the same as the management execution process in the 17th embodiment (Figure 78), the same as the management execution process in the 18th embodiment (Figure 79), or the same as the management execution process in the 19th embodiment (Figure 80).

When returning to the management processing program after the management execution process is executed, processing is executed to restore the information in the flag register of the main CPU 63 to the state it was in before the management execution process was executed. In detail, first, a push command "PUSH HL" is issued to save the information in the HL register of the main CPU 63 to the specific control stack area 222 (step S6407). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the memory area in the specific control stack area 222 that is next in the write order relative to the memory area where the HL register information was saved.

Then, a "PUSH WA" push command is issued to save the information in the WA register of the primary CPU 63 to the specific control stack area 222 (step S6408). After the push command is executed, the information in the stack pointer of the primary CPU 63 becomes information corresponding to the next memory area in the write order relative to the memory area in the specific control stack area 222 where the WA register information was saved.

Then, the information in the stack pointer of the primary CPU 63 is overwritten in the HL register of the primary CPU 63 by a load command, "LD HL, SP" (step S6409). In this case, since the stack pointer contains 16 bits of information and the H and L registers each contain 8 bits of information, the 8 consecutive bits from the upper side of the stack pointer are overwritten in the H register, and the 8 consecutive bits from the lower side of the stack pointer are overwritten in the L register.

Then, the flag register information saved in the FG buffer in the work area 221 for specific control in step S6406 is overwritten in the A register of the primary CPU 63 by a load command as "LD A, (_FGBUF)" (step S6410). Then, the information in the A register of the primary CPU 63 is stored in a 1-byte memory area in the stack area 222 for specific control corresponding to the stack pointer information stored in the HL register of the primary CPU 63 by a load command as "LD (HL), A" (step S6411). As a result, the flag register information saved in the FG buffer in the work area 221 for specific control in step S6404 is saved in the stack area 222 for specific control.

Then, using the load command "LD SP, SP-1," the stack pointer information of the primary CPU 63 is updated to the address information of the next storage area to be written in the specific control stack area 222 (step S6412). When the specific control stack area 222 is used, the storage target information is stored starting from the storage area with the last address in the specific control stack area 222. Each time new information to be stored is added, the storage target storage area is changed toward the first address in the specific control stack area 222. Therefore, in step S6412, the stack pointer information of the primary CPU 63 is updated to the address information corresponding to the storage area one address smaller in the specific control stack area 222. By executing the processing of step S6412, the next storage area to which information from the A register was saved in step S6411 is set as the storage target for information to be stored in response to the next push command, and the storage area to which information from the A register was saved in step S6411 is set as the storage target for information to be read in response to the next pop command.

Then, using the pop command "POP PSW," information is read from the previous storage area in the specific control stack area 222 corresponding to the information of the primary CPU 63's stack pointer, and the read information is overwritten in the flag register of the primary CPU 63 (step S6413). The information of the primary CPU 63's stack pointer immediately before the pop command of step S6413 is the information corresponding to the next storage area in the write order relative to the storage area to which the A register information was saved in step S6411. Therefore, the previous storage area in the specific control stack area 222 corresponding to the information of the primary CPU 63's stack pointer is the storage area to which the A register information was saved in step S6411. The information read from this storage area is then overwritten in the flag register of the primary CPU 63, and the flag register information saved in the FG buffer in the specific control work area 221 in step S6404 is restored to the flag register of the primary CPU 63. When the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the previous memory area in the specific control stack area 222 in the write order.

Then, a pop command "POP WA" is executed to restore the information in the WA register saved in the specific control stack area 222 in step S6408 to the WA register of the primary CPU 63 (step S6414). When the pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222. Furthermore, a pop command "POP HL" is executed to restore the information in the HL register saved in the specific control stack area 222 in step S6407 to the HL register of the primary CPU 63 (step S6415). When the pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S6416). This allows new execution of timer interrupt processing.

With the above configuration, when processing corresponding to specific control is initiated from a state in which processing corresponding to specific control is being executed to a state in which processing corresponding to non-specific control is executed, it is possible to save the information in the flag register of the main CPU 63 to the work area 221 for specific control rather than the stack area 222 for specific control. Then, when processing corresponding to specific control is resumed from a state in which processing corresponding to non-specific control is being executed, the information in the flag register saved in the work area 221 for specific control is restored to the flag register of the main CPU 63. This allows information to be restored to the flag register of the main CPU 63 from the storage area of the work area 221 for specific control specified in the program without referencing the stack pointer information of the main CPU 63. Therefore, even if the information in the stack pointer of the main CPU 63 is rewritten due to noise or other reasons, it is possible to restore information to the flag register of the main CPU 63.

In addition, instead of being configured to execute the process of saving flag register information to the main RAM 65 in a process corresponding to specific control, it may be configured to execute the process in a process corresponding to non-specific control. In addition, instead of being configured to execute the process of restoring flag register information saved in the main RAM 65 to the flag register of the main CPU 63 in a process corresponding to specific control, it may be configured to execute the process in a process corresponding to non-specific control.

<Twenty-ninth embodiment>
In this embodiment, the processing configuration of the management process differs from that of the fifteenth embodiment. The following describes the configuration that differs from the fifteenth embodiment. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 99 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S6501 to S6519 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, to prohibit the occurrence of timer interrupt processing (Figure 69), an interrupt prohibition setting is performed (step S6501). This makes it possible to prevent the timer interrupt processing (Figure 69), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, using the push command "PUSH HL," the information in the HL register (i.e., the H register and L register) of the primary CPU 63 is saved to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area with the next write order relative to that memory area (step S6502). Because the H register and L register of the primary CPU 63 each hold 8 bits (1 byte) of information, the information in the H register and L register is saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, a push command "PUSH AF" is used to save the information in the A register and flag register of the primary CPU 63 to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area that is next in the write order relative to that memory area (step S6503). Because the A register and flag register of the primary CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, the pop command "POP HL" overwrites the A register information and flag register information saved in the specific control stack area 222 in step S6503 into the HL register of the primary CPU 63 (step S6504). In this case, the A register information saved in the specific control stack area 222 is overwritten into the H register of the primary CPU 63, and the flag register information saved in the specific control stack area 222 is overwritten into the L register of the primary CPU 63. Note that when the above pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, the information in the L register of the master CPU 63 is overwritten in the A register of the master CPU 63 by a load command set to "LD A, L" (step S6505). Because the information in the flag register of the master CPU 63 was overwritten in the L register in step S6504, overwriting the information in the L register in the A register results in the flag register information being overwritten in the A register. Then, the information in the A register of the master CPU 63 is saved in the FG buffer set in the work area 221 for specific control by a load command set to "LD (_FGBUF), A" (step S6506). Because the information in the A register was overwritten with the flag register information in step S6505, execution of step S6506 results in the flag register information being saved in the work area 221 for specific control.

Then, using the push command "PUSH HL," the information in the HL register (i.e., the H register and L register) of the primary CPU 63 is saved to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area that is next in the write order relative to that memory area (step S6507). In this case, since the A register information and flag register information were overwritten in the HL register in step S6504, in step S6507 the A register information and flag register information are saved to the specific control stack area 222. Note that when the above push command is executed, the stack pointer information of the primary CPU 63 is updated to the information corresponding to the memory area two places later in the write order in the specific control stack area 222.

Then, using the pop command "POP AF," the H register information and L register information saved in the specific control stack area 222 in step S6507 are overwritten onto the A register and flag register of the master CPU 63 (step S6508). In this case, the H register information saved in the specific control stack area 222 is overwritten onto the A register of the master CPU 63, and the L register information saved in the specific control stack area 222 is overwritten onto the flag register of the master CPU 63. The H register information saved in the specific control stack area 222 is the A register information at the time of step S6503, and the L register information saved in the specific control stack area 222 is the flag register information at the time of step S6503. Therefore, by executing the processing of step S6508, the states of the A register and flag register of the master CPU 63 are restored to the states at the time of step S6503. When the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places earlier in the write order in the specific control stack area 222.

Then, the pop command "POP HL" is used to restore the HL register information saved in the specific control stack area 222 in step S6502 to the HL register of the primary CPU 63 (step S6509). This restores the state of the HL register of the primary CPU 63 to the state it was in at the time of step S6502. When the pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S6510). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

In addition, in the management execution process, before the check process begins, the information in the BC register, DE register, HL register, IX register, and IY register of the main CPU 63 is saved to the non-specific control work area 223, and after the check process in the management execution process is completed, the information saved in the non-specific control work area 223 is restored to the BC register, DE register, HL register, IX register, and IY register of the main CPU 63. This makes it possible to maintain the same state in the BC register, DE register, HL register, IX register, and IY register of the main CPU 63 before and after the check process.

However, this is not limited to this, and the processing content of the management execution process may be configured to be the same as the management execution process in the 17th embodiment (Figure 78), the same as the management execution process in the 18th embodiment (Figure 79), or the same as the management execution process in the 19th embodiment (Figure 80).

When returning to the management processing program after the management execution process is executed, processing is executed to restore the information in the flag register of the main CPU 63 to the state it was in before the management execution process was executed. In detail, first, a push command "PUSH HL" is issued to save the information in the HL register of the main CPU 63 to the specific control stack area 222 (step S6511). After the push command is executed, the information in the stack pointer of the main CPU 63 becomes information corresponding to the memory area in the specific control stack area 222 that is next in the write order relative to the memory area where the HL register information was saved.

Then, a push command "PUSH AF" is used to save the information in the A register and flag register of the primary CPU 63 to the memory area in the specific control stack area 222 corresponding to the current stack pointer information of the primary CPU 63 and to the memory area that is next in the write order relative to that memory area (step S6512). Because the A register and flag register of the primary CPU 63 each contain 8 bits (1 byte) of information, the information in the A register and flag register are saved separately to two memory areas with consecutive addresses. Note that when the above push command is executed, the information in the stack pointer of the primary CPU 63 is updated to the information corresponding to the memory area two addresses later in the write order in the specific control stack area 222.

Then, the pop command "POP HL" overwrites the A register information and flag register information saved in the specific control stack area 222 in step S6512 into the HL register of the primary CPU 63 (step S6513). In this case, the A register information saved in the specific control stack area 222 is overwritten into the H register of the primary CPU 63, and the flag register information saved in the specific control stack area 222 is overwritten into the L register of the primary CPU 63. Note that when the above pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the write order in the specific control stack area 222.

After that, the flag register information at the time of step S6503, which was saved to the FG buffer in the specific control work area 221 in step S6506, is overwritten in the A register of the master CPU 63 by a load command as "LD A, (_FGBUF)" (step S6514). Then, the L register of the master CPU 63 is overwritten with the A register information of the master CPU 63 by a load command as "LD L, A" (step S6515). Since the flag register information of the master CPU 63 at the time of step S6503 has been restored to the A register in step S6514, overwriting the L register with the A register information results in the L register being overwritten with the flag register information at the time of step S6503.

Then, using the push command "PUSH HL," the information in the HL register (i.e., the H register and L register) of the primary CPU 63 is saved to the storage area in the specific control stack area 222 corresponding to the information in the primary CPU 63's current stack pointer and to the storage area in the next write order relative to that storage area (step S6516). In this case, since the H register was overwritten in step S6513 with the information in the A register at the time of step S6512, the information in that A register is saved in the specific control stack area 222 in step S6516. Also, since the L register was overwritten in step S6515 with the information in the flag register at the time of step S6503, the information in that flag register is saved in the specific control stack area 222 in step S6516.

Then, a pop command "POP AF" is issued to overwrite the A register and flag register of the master CPU 63 with the H register information and L register information saved in the specific control stack area 222 in step S6516 (step S6517). In this case, the H register information saved in the specific control stack area 222 is overwritten in the A register of the master CPU 63, and the L register information saved in the specific control stack area 222 is overwritten in the flag register of the master CPU 63. The H register information saved in the specific control stack area 222 is the A register information at the time of step S6512, and the L register information saved in the specific control stack area 222 is the flag register information at the time of step S6503. Therefore, by executing the processing of step S6517, the state of the A register of the master CPU 63 is restored to the state of step S6512, and the flag register state is restored to the state at the time of step S6503.

Incidentally, the A register of the main CPU 63 is not used in the management execution process. Therefore, the state of the A register at the time of step S6512 is the state of the A register at the time of step S6508, and the state of the A register at the time of step S6508 is the state of the A register at the time of step S6503. Therefore, by executing the processing of step S6517, the states of the A register and flag register of the main CPU 63 are restored to the states at the time of step S6503. Note that when the above pop command is executed, the information in the stack pointer of the main CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the specific control stack area 222.

Then, the pop command "POP HL" is used to restore the HL register information saved in the specific control stack area 222 in step S6511 to the HL register of the primary CPU 63 (step S6518). This restores the state of the HL register of the primary CPU 63 to the state it was in at the time of step S6511. When the pop command is executed, the stack pointer information of the primary CPU 63 is updated to information corresponding to the memory area two places back in the writing order in the specific control stack area 222.

Then, interrupt permission is set to switch from a state in which timer interrupt processing (Figure 69) is prohibited to a state in which it is permitted (step S6519). This allows new execution of timer interrupt processing.

With the above configuration, the load command makes it possible to save the information in the flag register of the main CPU 63 to the work area 221 for specific control without executing a process that directly overwrites the information in the flag register of the main CPU 63 to another register of the main CPU 63.

Instead of executing steps S6505 to S6508, the process of step S6504 may be executed, and then the information in the L register, which has been overwritten with the information in the flag register by a load command as "LD (_FGBUF), L," may be saved to the FG buffer, thereby saving the information in the flag register to the specific control work area 221.

Alternatively, instead of executing steps S6514 and S6515, the process may be configured to execute step S6513, and then overwrite the L register with the flag register information saved in the specific control work area 221 using a load command such as "LD L, (_FGBUF)."

In addition, instead of being configured to execute the process of saving flag register information to the main RAM 65 in a process corresponding to specific control, it may be configured to execute the process in a process corresponding to non-specific control. In addition, instead of being configured to execute the process of restoring flag register information saved in the main RAM 65 to the flag register of the main CPU 63 in a process corresponding to specific control, it may be configured to execute the process in a process corresponding to non-specific control.

Thirtieth Embodiment
In this embodiment, the processing configuration executed by the main CPU 63 differs from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 100 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S6601 to S6621 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, power-on wait processing is executed (step S6601). During this power-on wait processing, the system waits for a predetermined wait time (specifically, one second) to elapse after the main processing is started, without proceeding to the next processing. During this power-on wait processing, the pattern display device 41 starts operating and is initialized. After that, access to the main RAM 65 is permitted (step S6602).

Then, it is determined whether the power outage flag provided in the specific control work area 221 in the main RAM 65 is set to "1" (step S6603). If the power outage flag is set to "1" (step S6603: YES), a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step S6604).

The checksum can be calculated using any method, but one example is to add up all the numerical values in the storage area that is the target of the checksum calculation. This checksum calculation method is the same as the checksum calculation method used in the power outage processing described below. The checksum calculated in the power outage processing described below is stored in the work area 221 for specific control, but the storage area of the work area 221 for specific control in which this checksum is stored is excluded from the storage areas that are the target of the calculation when the checksum is calculated.

In other words, when calculating the checksum, some storage areas in the specific control work area 221 and the specific control stack area 222 are subject to the calculation. These storage areas subject to the calculation are generally not rewritten with information if the supply of power, such as backup power, to the specific control work area 221 and the specific control stack area 222 continues from the time the checksum is calculated during power outage processing when the supply of operating power to MPU 62 is stopped until the supply of operating power to MPU 62 is resumed and the processing of step S6604 is executed. Therefore, if the information in the specific control work area 221 and the specific control stack area 222 has not been changed between the time the supply of operating power to MPU 62 is stopped and the time the supply of operating power to MPU 62 is resumed, the checksums for the specific control work area 221 and the specific control stack area 222 will be the same as they were immediately before the supply of operating power to MPU 62 was stopped. The storage area that is the subject of calculation when calculating this checksum includes an area (specifically, a setting value counter) in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set.

Then, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and saved in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the MPU 62 was stopped, are read from the specific control work area 221, and the read checksums are compared with the checksum calculated in step S6604 (step S6605). It is then determined whether the checksums match (step S6606).

Here, the power outage information storage process executed by the main CPU 63 will be described with reference to the flowchart in Figure 101. Note that the power outage information storage process is executed in step S6801 of the timer interrupt process (Figure 103), which will be described later.

The power outage information storage process first sets the repetition count information for the power outage signal, "10," to the repetition counter provided in the specific control work area 221 (step S6701), and then clears the power outage detection counter provided in the specific control work area 221 to "0" (step S6702).

Then, the MPU 62 executes a process to read information about the power outage signal received at its input port (step S6703). In this case, if a power outage signal corresponding to no power outage (a LOW level power outage signal) is received, the input port stores "0" as non-power outage information; if a power outage signal corresponding to a power outage (a HI level power outage signal) is received, the input port stores "1" as power outage information. In step S6703, the main CPU 63 executes a process to read the power outage signal information into its register.

If the power outage signal information read in step S6703 corresponds to the occurrence of a power outage (power interruption) (step S6704: YES), the numerical information of the power outage detection counter is incremented by 1 (step S6705). If a negative determination is made in step S6704 or if the processing of step S6705 is executed, the numerical information of the repeat counter is decremented by 1 (step S6706). Then, it is determined whether the numerical information of the repeat counter after the decrement is "0" (step S6707). If a negative determination is made in step S6707, the process returns to step S6703 and the processing of steps S6703 to S6706 is repeated. On the other hand, if a positive determination is made in step S6707, the process proceeds to step S6708.

In step S6708, it is determined whether the current numerical information of the power outage detection counter is equal to or greater than the trigger reference count corresponding to the occurrence of a power outage. If it is less than the trigger reference count, the power outage information storage process is terminated. On the other hand, if it is equal to or greater than the trigger reference count, the power outage processing of steps S6709 to S6712 is executed.

Specifically, first, the power outage flag provided in the specific control work area 221 is set to "1" (step S6709). As a result, if power outage processing is executed normally and information is stored and maintained normally in the main RAM 65, the power outage flag in the specific control work area 221 will be set to "1" when the supply of operating power to the main CPU 63 is resumed again.

Then, a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step S6710). In this case, the storage areas in the specific control work area 221 and the specific control stack area 222 that are the objects of calculation when calculating the checksum are the same as the storage areas in the specific control work area 221 and the specific control stack area 222 that are the objects of calculation of the checksum in step S6604 of the main processing (FIG. 100). Furthermore, the storage areas that are the objects of calculation when calculating this checksum include an area in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set (specifically, a setting value counter). The calculated checksum is then stored in a storage area in the specific control work area 221 that is used to store the checksum but is excluded from the objects of calculation of the checksum.

Then, all output port information in the register of the primary CPU 63 is set to "0" (step S6711), and access to the primary RAM 65 is prohibited (step S6712). The infinite loop continues until the power is completely cut off and processing can no longer be executed.

Furthermore, by executing the power outage information storage process as the first process in the timer interrupt process, there is no need to restart the timer interrupt process partway through after power is restored. This eliminates the need to store the address of the process that was being executed when the power outage occurred as stack information in the main RAM 65, making it possible to reduce the processing load when a power outage occurs.

Returning to the explanation of the main processing (FIG. 100), if a negative judgment is made in step S6603 or step S6606, a clearing process for non-setting update is executed (step S6607). In the clearing process for non-setting update, the specific control work area 221 is cleared to "0" and an initial setting is executed, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter). As a result, the area indicating whether the win/loss lottery mode is the high probability mode is cleared to "0," so the win/loss lottery mode becomes the low probability mode regardless of the win/loss lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being executed, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserved storage area 65a and normal power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so the reserved information for the special map display unit 37a is erased and the reserved information for the normal map display unit 38a is erased. In addition, in the clearing process for non-setting updates, the stack area 222 for specific control is cleared to "0" and initial settings are performed. In addition, in the clearing process for non-setting updates, various registers of the main CPU 63 are also cleared to "0" and then initial settings are performed.

On the other hand, the clearing process during non-setting updates does not clear the work area 223 for non-specific control and the stack area 224 for non-specific control to "0". This makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if the power outage processing was not executed normally and the power outage flag was not set to "1". Also, it makes it possible to prevent the work area 223 for non-specific control and the stack area 224 for non-specific control from being cleared to "0" even if an abnormality occurs in the checksum for the work area 221 for specific control and the stack area 222 for specific control.

If a negative determination is made in step S6603 or step S6606 and the non-setting update clear process is executed in step S6607, the value of the setting value counter in the specific control work area 221 is checked to determine whether the setting value of the pachinko machine 10 is normal (step S6608). Specifically, if the setting value set in the setting value counter is any of "Setting 1" through "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal. If the setting value is abnormal (step S6608: NO), processing to set a new setting value (steps S6619 through S6621), described below, is executed. This makes it possible to monitor whether the setting value is normal even when a negative determination is made in step S6603 or step S6606 and the non-setting update clear process (step S6607) is executed, and to reset the setting value if it is abnormal.

If the setting value is normal (step S6608: YES), the power-on setting process is executed (step S6609). During the power-on setting process, a predetermined area in the work area 221 for specific control, such as the initialization of the power outage flag, is set to its initial value, and a command corresponding to the current game status is sent to the audio and light emission control device 81.

The main CPU 63 is configured to periodically execute timer interrupt processing, but timer interrupt processing is prohibited when main processing begins. This state in which timer interrupt processing is prohibited is released when step S6609 is completed and before step S6610 is executed, and timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 begins, the power-on setting process of step S6609 ends and timer interrupt processing is not executed until before step S6610 is started. Therefore, processing to progress the game will not be initiated by the main CPU 63 until this situation is reached.

Then, the process proceeds to the remaining processing of steps S6610 to S6613. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there will be remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time will be used to repeatedly execute the remaining processing of steps S6610 to S6613. In this respect, the remaining processing of steps S6610 to S6613 can be said to be non-periodic processing executed non-periodically. Steps S6610 to S6613 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

As described above, in this embodiment, when the supply of operating power to the main CPU 63 begins, if the power outage flag in the specific control work area 221 is not set to "1" or the checksums do not match, the system executes the clear process for non-setting updates, and if the setting values are normal (step S6608: YES), it proceeds to processing for progressing the game. As a result, even if the power outage flag is not set to "1" because the power outage process was not executed normally, there is no need to turn the power on and off again after the supply of operating power to the main CPU 63 begins. Furthermore, even if an abnormality occurs in the checksums for the specific control work area 221 and the specific control stack area 222, there is no need to turn the power on and off again after the supply of operating power to the main CPU 63 begins.

If a positive determination is made in both step S6603 and step S6606, the value of the setting value counter in the specific control work area 221 is checked to determine whether the setting value of the pachinko machine 10 is normal (step S6614). Specifically, if the setting value set in the setting value counter is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal. If the setting value is abnormal (step S6614: NO), the process (steps S6619 to S6621) for setting a new setting value, described below, is executed.

If the setting value is normal (step S6614: YES), it is determined whether the reset button 68c has been pressed (step S6615), whether the setting key insertion unit 68a has been turned ON using the setting key (step S6616), whether the front door frame 14 is open relative to the inner frame 13 (step S6617), and whether the gaming machine main body 12 is open relative to the outer frame 11 (step S6618).

In this embodiment, a front door open sensor 95 for detecting whether the front door frame 14 is open relative to the inner frame 13 is electrically connected to the main CPU 63, and the detection result of the front door open sensor 95 is input to the main CPU 63. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 sends a closed detection signal to the main CPU 63, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 sends an open detection signal to the main CPU 63. When the main CPU 63 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is closed, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is open.

In addition, in this embodiment, a main body open sensor 96 for detecting whether the gaming machine main body 12 is in an open state relative to the outer frame 11 is electrically connected to the main CPU 63, and the detection result of the main body open sensor 96 is input to the main CPU 63. In this case, if the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 sends a closed detection signal to the main CPU 63, and if the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 sends an open detection signal to the main CPU 63. If the main CPU 63 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and if it receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state.

If the reset button 68c has not been pressed (step S6615: NO), the power-on setting process is executed in step S6609, and the remaining processes of steps S6610 to S6613 are then repeated. In other words, if the reset button 68c has not been pressed, the process proceeds to the process for controlling the progress of the game without executing the process for clearing the specific control work area 221 and the specific control stack area 222.

If the reset button 68c is pressed (step S6615: YES) and a negative judgment is made in any of steps S6616 to S6618, the system executes the clear process when no setting is updated (step S6607), and then, provided that the setting values are normal (step S6608: YES), proceeds to the process for controlling the progress of the game from step S6609 onwards. The details of the clear process when no setting is updated have already been explained.

If the reset button 68c is pressed (step S6615: YES) and all of steps S6616 to S6618 return a positive result, processing is performed to update the setting value. Furthermore, if it is determined in step S6608 or step S6614 that the setting value is abnormal, processing is also performed to update the setting value.

Specifically, first, a setting value copy process is executed (step S6619). In this copy process, the setting value counter information used to identify the setting value of the pachinko machine 10 in the specific control work area 221 is stored in a copy area provided in the specific control work area 221. As a result, even if the setting value counter information is cleared to "0" in the subsequent setting update clear process (step S6620), it is possible to determine the setting value of the pachinko machine 10 before the setting value update clear process was executed (i.e., the setting value of the pachinko machine 10 before the supply of operating power to the pachinko machine 10 was stopped).

Then, a clearing process is executed when the settings are updated (step S6620). During the clearing process when the settings are updated, the specific control work area 221 is cleared to "0" and initial settings are executed, except for the area in the specific control work area 221 indicating whether the win/lose lottery mode is the high probability mode and the copy area. This results in a situation where no game rounds are being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying any changes, and the normal power device 34a is in a closed state. Furthermore, the reserve storage area 65a and the normal power reserve area 65c provided in the specific control work area 221 are also cleared to "0," thereby erasing the reserved information for the special map display unit 37a and the reserved information for the normal map display unit 38a. During the clearing process when the settings are updated, the specific control stack area 222 is cleared to "0" and initial settings are executed. During the clearing process when the settings are updated, the setting value counter used to identify the setting value of the pachinko machine 10 is cleared to "0." Additionally, during the clearing process when updating settings, various registers in the main CPU 63 are cleared to "0" before initial settings are performed.

On the other hand, the clearing process when the settings are updated does not clear to "0" the area indicating whether the win/lose lottery mode is the high probability mode, so even if the setting value update process (step S6621) is executed, the win/lose lottery mode can be maintained in the mode it was in before the supply of operating power to the pachinko machine 10 was stopped. Furthermore, the clearing process when the settings are updated does not clear the copy area to "0," so it is possible to subsequently identify the setting value that was set before the clearing process when the settings were updated. Note that this is not limited to the above configuration, and the clearing process when the settings are updated may be configured not to clear to "0" the setting value counter used to identify the setting value of the pachinko machine 10, or the clearing process when the settings are updated may be configured to clear to "0" the area indicating whether the win/lose lottery mode is the high probability mode.

The clearing process during setting updates does not clear the non-specific control work area 223 and the non-specific control stack area 224 to "0." This makes it possible to prevent the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" even when a setting value update process that can change the setting values of the pachinko machine 10 is executed.

Then, in step S6621, the setting value update process is executed. The processing content of the setting value update process is the same as the setting value update process in the 22nd embodiment (Figure 85). After the setting value update process is executed, the process proceeds to step S6609 and subsequent steps for controlling the progress of the game.

With the above configuration, if the setting value is abnormal, the setting value update process is initiated without any special operation by the amusement hall manager. Then, when the setting value update process is completed, the process moves on to control the progress of the game. This makes it possible to play under conditions where the setting value has been set to the correct value. On the other hand, because completing the setting value update process requires turning the setting key off on the setting key insertion section 68a, it is possible to prevent the occurrence of an incident in which the setting value is arbitrarily set by someone other than the amusement hall manager and game play is started.

Next, we will explain the configuration for forcibly stopping game progress when the main CPU 63 is unable to perform various processes normally. Figure 102(a) is a block diagram illustrating the configuration of the MPU 62.

As shown in FIG. 102(a), the MPU 62 is provided with a main CPU 63, a main ROM 64, and a main RAM 65, as well as a reset signal output unit 251 and a program monitoring unit 252. The reset signal output unit 251 has the function of outputting a reset signal to the main CPU 63. Specifically, the reset signal output unit 251 outputs a reset signal to the main CPU 63 as a HI level signal when operating power is being supplied from the power supply/launch control device 78 and the output disable condition is not met, and does not output a reset signal to the main CPU 63 when operating power is not being supplied from the power supply/launch control device 78 or when operating power is being supplied but the output disable condition is met. The main CPU 63 executes various processes when operating power is being supplied from the power supply/launch control device 78 and a reset signal is being received from the reset signal output unit 251, and does not execute various processes when operating power is being supplied from the power supply/launch control device 78 but a reset signal is not being received from the reset signal output unit 251. Additionally, when operating power is being supplied from the power supply and launch control device 78, the main CPU 63 starts the main processing (Figure 100) when the state changes from not receiving a reset signal from the reset signal output unit 251 to receiving a reset signal.

The program monitoring unit 252 has the function of monitoring whether the main CPU 63 is in a state where various processes can be performed normally. Specifically, the program monitoring unit 252 monitors whether the value of a program counter provided in the main CPU 63 is an abnormal value. The program counter is used to store the address where an instruction to be executed by the main CPU 63 is stored. The program counter has a set of possible values, and the program monitoring unit 252 monitors whether the value of the program counter is a value other than the possible values. In addition, when writing information to the specific control work area 221 in response to a load command, the program monitoring unit 252 monitors whether the address specified as the write destination area is an abnormal address. Note that the program monitoring unit 252 may also be configured to monitor whether the address specified as the read target area when reading information from the specific control work area 221 in response to a load command is an abnormal address.

If the program monitoring unit 252 determines that the program counter value is abnormal, or that the address specified when writing information by a load command is abnormal, it outputs a monitoring abnormality signal to the reset signal output unit 251. When the reset signal output unit 251 receives a monitoring abnormality signal from the program monitoring unit 252, it temporarily suspends the output of the reset signal even if operating power is being supplied from the power supply/launch control device 78, suspends the output of the reset signal for a duration of suspension, and then resumes the output of the reset signal. The duration of suspension is long enough for the main CPU 63 to identify that the output of the reset signal has been suspended. As a result, if the program counter value becomes abnormal, or if the address specified when writing information by a load command is abnormal, the main processing will be executed by the main CPU 63 by turning the reset signal OFF and ON.

Figure 102(b) is a time chart showing the output of a reset signal by the reset signal output unit 251. Figure 102(b1) shows the period during which operating power is supplied from the power supply and launch control device 78, Figure 102(b2) shows the period during which a reset signal is output from the reset signal output unit 251, and Figure 102(b3) shows the timing at which a monitoring abnormality signal is output from the program monitoring unit 252.

First, let us explain the case where no monitoring abnormality signal is output from the program monitoring unit 252. At timing t1, as shown in FIG. 102(b1), the supply of operating power from the power supply and launch control device 78 to the MPU 62 begins, and at timing t2, as shown in FIG. 102(b), the output of a reset signal from the reset signal output unit 251 begins. Then, at timing t3, as shown in FIG. 102(b1), the supply of operating power from the power supply and launch control device 78 to the MPU 62 is stopped, and at timing t4, as shown in FIG. 102(b2), the output of the reset signal from the reset signal output unit 251 is stopped.

Next, we will explain the case where a monitoring abnormality signal is output from the program monitoring unit 252. At timing t5, as shown in Figure 102 (b1), the power supply and launch control device 78 begins supplying operating power to the MPU 62, and at timing t6, as shown in Figure 102 (b), the reset signal output unit 251 begins outputting a reset signal. Thereafter, at timing t7, the program counter value becomes abnormal, or the address specified when writing information with a load command becomes abnormal, and a monitoring abnormality signal is output from the program monitoring unit 252 to the reset signal output unit 251, as shown in Figure 102 (b3). As a result, the output of the reset signal from the reset signal output unit 251 is temporarily stopped at timing t7, as shown in Figure 102 (b2), and then resumed at timing t8.

In this case, the main CPU 63 stops execution of various processes at timing t7 and starts the main processing (Figure 100) at timing t8, when the rising edge of the reset signal is confirmed. However, because power outage processing was not being executed when the main CPU 63 stopped execution of various processes, the main processing (Figure 100) is started in a situation where the power outage flag in the specific control work area 221 is not set to "1," and the main processing (Figure 100) is started without saving the checksums for the specific control work area 221 and the specific control stack area 222. Therefore, a negative judgment is made in step S6603 or step S6606 in the main processing (Figure 100), and the clear processing for non-setting update (step S6607) is executed. As a result, if a monitoring abnormality signal is output from the program monitoring unit 252 because the program counter value becomes abnormal or the address specified when writing information using a load command becomes abnormal, a non-setting update clear process can be executed in which a specified storage area in the specific control work area 221 and specific control stack area 222 is cleared to "0."

However, the clearing process during non-setting updates does not clear the non-specific control work area 223 and the non-specific control stack area 224 to "0." This prevents the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" even if a monitoring abnormality signal is output from the program monitoring unit 252 because the program counter value becomes abnormal or the address specified when writing information with a load command becomes abnormal.

Returning to the explanation of Figure 102(b), thereafter, at timing t9, the supply of operating power from the power supply/launch control device 78 to the MPU 62 is stopped as shown in Figure 102(b1), and at timing t10, the output of the reset signal from the reset signal output unit 251 is stopped as shown in Figure 102(b2).

Next, the timer interrupt processing in this embodiment executed by the main CPU 63 will be described with reference to the flowchart in Figure 103. The timer interrupt processing is executed periodically (for example, every 4 milliseconds) while the processing of steps S6610 to S6613 is being executed in the main processing (Figure 100). Note that the program corresponding to the timer interrupt processing is set in the program for specific control.

Steps S6801 to S6819 are identical to steps S5201 to S5219 of the timer interrupt processing (Figure 86) in the 22nd embodiment. These processes are executed by the main CPU 63 using a program for specific control and data for specific control. Then, setting monitoring processing is executed (step S6820). Figure 104 is a flowchart showing the setting monitoring processing.

The value of the setting value counter in the specific control work area 221 is checked to determine whether the setting value of the pachinko machine 10 is normal (step S6901). Specifically, if the setting value set in the setting value counter is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

If the setting value is abnormal (step S6901: NO), a setting value copy process is first executed (step S6902). In this copy process, the setting value counter information used to identify the setting value of the pachinko machine 10 in the specific control work area 221 is stored in a copy area provided in the specific control work area 221. This makes it possible to determine the setting value of this pachinko machine 10 before the setting value update process, which is executed subsequently, is executed.

Then, an abnormality command indicating that a setting value abnormality has occurred is sent to the audio and light-emitting control device 81 (step S6903). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the setting value abnormality and outputs a voice message stating, "A setting value abnormality has been detected," from the speaker unit 54. The symbol display device 41 also displays a text image stating, "A setting value abnormality has been detected." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notifications may be terminated when an operation to terminate the notification is performed by the amusement hall manager. The notification termination operation may be, for example, by pressing the update button 68b or the reset button 68c. By confirming the notification, the amusement hall manager can understand that a setting value abnormality has occurred.

Then, the setting value update process is executed (step S6904). That is, each time the timer interrupt process (FIG. 103) is executed, the setting value is monitored for abnormalities, and if an abnormality in the setting value is detected, the setting value update process is executed to reset the setting value of the pachinko machine 10. The content of the setting value update process is the same as the setting value update process (FIG. 85) in the 22nd embodiment. Therefore, each time the update button 68b is pressed, the setting value is updated by one step, and the currently selected setting value is confirmed when the outlet detection sensor 48a detects a game ball. The setting value being updated and the confirmed setting value are displayed on the third notification display device 69c. Thereafter, if the setting key insertion section 68a switches from the ON state to the OFF state, it is determined that the termination condition for the setting value update process has been met. After the setting value update process is executed, the process returns to the timer interrupt process (FIG. 103).

In the setting value update process, the termination condition is not determined to be met simply because the setting key insertion unit 68a is in the OFF state; rather, the termination condition is determined to be met when the setting key insertion unit 68a switches from the ON state to the OFF state. When the setting value update process is executed during the setting monitoring process, the setting key insertion unit 68a is in the OFF state when the setting value update process begins. Therefore, in order to fulfill the termination condition for the setting value update process, it is necessary to insert a setting key into the setting key insertion unit 68a, turn it ON, and then turn it OFF. This makes it possible to prevent the setting value update process from terminating even when the proper operation by the amusement hall manager has not been performed.

When the setting key insertion section 68a switches from the ON state to the OFF state and the termination condition for the setting value update process is met, step S5111 of the setting value update process (FIG. 85) is executed to compare whether the setting value stored in the copy area of the specific control work area 221 is the same as the setting value currently set in the setting value counter in the specific control work area 221. In other words, it is determined whether the setting value set before the setting value update process (step S6904) is executed is the same as the setting value set in the current setting value update process. If the two setting values are the same (step S5112: NO), the non-change notification process (step S5113) is executed, thereby issuing the previously described setting maintenance notification. On the other hand, if the two setting values are different (step S5112: YES), the change notification process (step S5114) is executed, thereby issuing the previously described setting change notification.

In a configuration in which a setting value update process is executed when a setting value abnormality occurs, a setting maintenance notification is issued if the setting value set before the setting value update process is executed is the same as the setting value set in the setting value update process. As a result, even if a setting value update process is executed due to a setting value abnormality, the setting maintenance notification is issued by resetting the setting value set in the previous situation, making it possible to clearly inform players that the setting value has not changed even if a setting value update process is executed due to a setting value abnormality. Incidentally, since it is common for gaming halls to record the setting values of each pachinko machine 10 installed, it is possible to execute a setting value update process due to a setting value abnormality so that the recorded setting value is used.

Returning to the explanation of the timer interrupt processing (Figure 103), after the setting monitoring processing is executed in step S6820, the management processing is executed in step S6821. When the management processing is executed, a subroutine program corresponding to the management processing set in the specific control program is executed, and when the subroutine program is executed, information for specifying the return address of the timer interrupt processing after execution of the management processing is written to the specific control stack area 222 by a push command. Then, when the management processing is completed, the information for specifying the return address is read by a pop command, and the program returns to the timer interrupt processing program indicated by the return address.

Figure 105 is a flowchart showing the management processing in this embodiment, which is executed by the main CPU 63. Note that steps S7001 to S7005 in the management processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (Figure 103) (step S7001). This makes it possible to prevent the timer interrupt processing (Figure 103), which is processing corresponding to specific control, from interrupting and being started in the middle of the management execution processing (described below), which is processing corresponding to non-specific control.

Then, using the load command "LD (_PSWBUF), PSW," the information in the flag register of the main CPU 63 is saved to the PSW buffer set in the work area 221 for specific control (step S7002). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the information in the flag register changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program for the subroutine corresponding to the management execution process is started, it is possible to save the flag register information in the state it was in before it changed after the subroutine was called or started in the work area 221 for specific control.

Then, the management execution process is started by reading the subroutine program corresponding to the management execution process set in the non-specific control program (step S7003). In this case, information for specifying the return address of the management process after the management execution process is executed is written to the specific control stack area 222 by a push command. Then, when the management execution process is completed, information for specifying the return address is read by a pop command, and the process returns to the management processing program indicated by the return address.

When the management execution process is completed and the management process program is restored, the flag register information saved in the PSW buffer in the specific control work area 221 in step S7002 is restored to the flag register of the primary CPU 63 by a load command as "LD PSW, (_PSWBUF)" (step S7004). This restores the flag register information of the primary CPU 63 to the information at the time step S7002 was last executed. In other words, the flag register information of the primary CPU 63 is restored to the information required to execute specific control.

Then, interrupt permission is set (step S7005) to switch from a state in which timer interrupt processing (Figure 103) is prohibited to a state in which it is permitted. This allows new execution of timer interrupt processing.

Figure 106 is a flowchart showing the management execution process in this embodiment, which is executed by the main CPU 63. Note that steps S7101 to S7116 in the management execution process are executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

Steps S7101 to S7108 and steps S7110 to S7116 execute the same processing as steps S4501 to S4515 of the management execution process (Figure 78) in the seventeenth embodiment described above. Furthermore, step S7109 executes a separate monitoring process. When the separate monitoring process is executed, a subroutine program corresponding to the separate monitoring process set in the non-specific control program is executed. When the subroutine program is executed, information for specifying the return address of the management execution process after the separate monitoring process is executed is written to the non-specific control stack area 224 by a push command. When the separate monitoring process is completed, information for specifying the return address is read by a pop command, and the program returns to the management execution process indicated by the return address.

Figure 107 is a flowchart showing the separate monitoring process. Note that steps S7201 to S7206 in the separate monitoring process are executed by the main CPU 63 using a program and data for non-specific control.

In the separate monitoring process, it is determined whether the value of the pointer indicating the processing position of the process being executed in the non-specific control program is outside the normal numerical range (step S7201). It is also determined whether the information stored in the normal counter area 231, the open/close execution mode counter area 232, and the high-frequency support mode counter area 233 provided in the non-specific control work area 223 is clearly abnormal (step S7202). For example, if the value of the normal out counter 231e in the normal counter area 231 is "0" but the value of the normal general winning counter 231a is 1000 or greater, it is determined to be abnormal. It is also determined whether the information stored in the calculation result storage area 234 provided in the non-specific control work area 223 is clearly abnormal (step S7203). For example, if the 61st parameter is "0" but any of the 62nd to 64th parameters is not "0," it is determined to be abnormal.

If a positive judgment is made in any of steps S7201 to S7203, it is determined that an information abnormality has occurred in the work area 223 for non-specific control, and a partial clear process for the work area 223 for non-specific control is executed (step S7204). In this partial clear process, all storage areas in the work area 223 for non-specific control other than the management start flag are cleared to "0". In this case, the normal counter area 231, the counter area 232 for opening/closing execution mode, the counter area 233 for high-frequency support mode, and the calculation result storage area 234 are all cleared to "0". This makes it possible to resolve the information abnormality in the work area 223 for non-specific control.

Furthermore, by not clearing the management start flag to "0," it is possible to maintain the state in which the management start flag is already set to "1," and it is possible to prevent restrictions on the collection of history information at the shipping stage of the pachinko machine 10 from occurring even if the pachinko machine 10 is already being used continuously at the gaming hall. However, this is not limited to this, and in step S7204, the entire work area 223 for non-specific control, including the management start flag, may be configured to be cleared to "0."

In addition, in step S7204, the stack area 224 for non-specific control is not cleared to "0." The stack area 224 for non-specific control stores information from various registers used in the processing corresponding to the specific control in steps S7102 to S7107 of the management execution process (Figure 106). In this case, by not clearing the stack area 224 for non-specific control to "0," it is possible to prevent the information from being erased that is stored in the stack area 224 for non-specific control and that is used in the processing corresponding to this specific control. In addition, the stack area 224 for non-specific control stores information about the return address of the management execution process (Figure 106) after the separate monitoring process has ended, and by not clearing the stack area 224 for non-specific control to "0," it is possible to prevent this return address information from being erased.

After that, the initial setting process is executed (step S7205). In the initial setting process, initial settings are made to the storage areas in the non-specific control work area 223 that were cleared to "0" in step S7204.

Then, a clear notification process is executed (step S7206). In the clear notification process, a command indicating that the work area 223 for non-specific control has been cleared to "0" is sent to the audio/light-emitting control device 81. Upon receiving this command, the audio/light-emitting control device 81 causes the display/light-emitting unit 53 to emit light in a manner corresponding to the forced clearing of the work area 223 for non-specific control, and causes the speaker unit 54 to output a voice message stating, "The history information has been forcibly cleared." Furthermore, the symbol display device 41 is caused to display a text image stating, "The history information has been forcibly cleared." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, this is not limited to this, and the notification may be terminated when an operation to terminate the notification is performed by the gaming hall manager. The notification termination operation may be, for example, pressing the update button 68b or the reset button 68c. By checking the above notification, the gaming hall manager will be able to understand that the non-specific control work area 223 has been forcibly cleared.

If a negative judgment is made in all of steps S7201 to S7203, or if the processing of step S7206 is executed, the separate monitoring processing ends and the processing returns to the monitoring execution processing (Figure 106).

The present embodiment described above provides the following excellent effects:

If the program monitoring unit 252 determines that the address specified when writing information via a load command is abnormal, the reset signal output unit 251 turns the reset signal from OFF to ON, causing the main CPU 63 to execute the main processing (Fig. 100) in the same manner as when the supply of operating power is newly started. When the reset signal is turned from OFF to ON, the power outage flag in the specific control work area 221 is not set to "1" and the checksum at the time of the power outage is not stored in the specific control work area 221, so the non-setting update clear processing (step S6607) is forcibly executed. In the non-setting update clear processing, all memory areas in the specific control work area 221 other than the memory area in which the setting values of the pachinko machine 10 are stored are cleared to "0," and the specific control stack area 222 is cleared to "0," and the initial setting processing of these areas is then executed. As a result, if there is a possibility that an information anomaly has occurred in the specific control work area 221 or the specific control stack area 222, the information anomaly can be resolved by performing a "0" clear process and an initial setting process on the specific control work area 221 and the specific control stack area 222.

If the program monitoring unit 252 determines that the program counter value of the main CPU 63 is abnormal, the reset signal output unit 251 turns the reset signal from OFF to ON, causing the main CPU 63 to execute the main processing (Figure 100) in the same way as when the supply of operating power is newly started. When the reset signal is turned from OFF to ON, the power outage flag in the specific control work area 221 is not set to "1" and the checksum at the time of the power outage is not stored in the specific control work area 221, so a clear process for non-setting update (step S6607) is forcibly executed. In the clear process for non-setting update, the internal storage area of the main CPU 63, including various registers, is cleared to "0" and an initial setting process is executed. As a result, if there is a possibility that an information anomaly has occurred in the internal storage area of the main CPU 63, the information anomaly can be resolved by clearing the internal storage area of the main CPU 63 to "0" and executing the initial setting process.

On the other hand, the clearing process during non-setting updates does not clear the non-specific control work area 223 and the non-specific control stack area 224 to "0." This makes it possible to prevent game history information from being erased, and also makes it possible to prevent information on the game history management results from being erased, even when an information anomaly is identified by the program monitoring unit 252 as described above and the internal memory area of the main CPU 63, the specific control work area 221, and the specific control stack area 222 are cleared to "0" and initial setting processing is performed.

In a configuration in which the clear process for non-setting updates (step S6607) is executed if the power outage flag is not set to "1" or the checksum does not match during main processing (Figure 100) when the supply of operating power to the main CPU 63 begins, and if the program monitoring unit 252 identifies the occurrence of an information anomaly, the reset signal is turned from OFF to ON so that the main processing (Figure 100) is executed in a state in which the power outage flag is not set to "1" and no checksum is stored. This makes it possible to resolve the information anomaly identified by the program monitoring unit 252 by utilizing the configuration for resolving the information anomaly when the supply of operating power begins.

In a configuration in which the checksum is monitored for normality during main processing (Figure 100) when the supply of operating power to the main CPU 63 begins, the checksum calculation targets include the work area 221 for specific control and the stack area 222 for specific control, but do not include the work area 223 for non-specific control and the stack area 224 for non-specific control. This makes it possible to determine whether an information anomaly has occurred in only the storage area corresponding to specific control in the main RAM 65.

If an abnormality in the checksum is identified during main processing (Figure 100) when the supply of operating power to the main CPU 63 is initiated, a non-setting update clear process (step S6607) is executed. However, during this non-setting update clear process, the specific control work area 221 and the specific control stack area 222 are cleared to "0" and an initial setting process is executed, whereas the non-specific control work area 223 and the non-specific control stack area 224 are not cleared to "0". This prevents the process corresponding to specific control from continuing to be executed in the current state despite an information abnormality occurring in the specific control work area 221 and the specific control stack area 222, and also prevents the storage area corresponding to non-specific control in the main RAM 65 from being cleared to "0" as a result of an information abnormality in the specific control work area 221 and the specific control stack area 222.

During the power outage processing (steps S6709 to S6712) of the power outage information storage process (Figure 101), checksums are calculated for the work area 221 for specific control and the stack area 222 for specific control, but checksums are not calculated for the storage areas corresponding to non-specific control in the main RAM 65. This makes it possible to prevent the processing time required to complete power outage processing from becoming excessively long.

If a separate monitoring process (Figure 107) executed in the process corresponding to non-specific control identifies an abnormality in the information stored in the work area 223 for non-specific control, the separate monitoring process (Figure 107) corresponding to non-specific control clears the work area 223 for non-specific control to "0" and executes an initial setting process. This makes it possible to prevent the process corresponding to non-specific control from being executed while the information in the work area 223 for non-specific control is retained as is, even if some abnormality has occurred in the work area 223 for non-specific control. Furthermore, because the process of clearing the work area 223 for non-specific control to "0" and the process of initial setting are executed in the process corresponding to non-specific control, it is possible to prevent the process corresponding to specific control from intervening in the update of the information in the work area 223 for non-specific control.

In a separate monitoring process (Figure 107) corresponding to non-specific control, monitoring is performed to determine whether an abnormality has occurred in the work area 223 for non-specific control, and if an abnormality has occurred, the work area 223 for non-specific control is cleared to "0" and initialized. This makes it possible to monitor whether an abnormality has occurred in the work area 223 for non-specific control and initialize the work area 223 for non-specific control as a series of processes in the process corresponding to non-specific control.

If the separate monitoring process (Figure 107) executed in the process corresponding to non-specific control identifies an abnormality in the information stored in the work area 223 for non-specific control, the work area 223 for non-specific control is cleared to "0" and initialized, but the stack area 224 for non-specific control is not cleared to "0" or initialized. This makes it possible to resolve the information abnormality in the work area 223 for non-specific control while preventing the information of various registers used in the process corresponding to specific control that was saved in the stack area 224 for non-specific control and the return address information after the separate management process is completed from being erased.

The process of clearing the work area 221 for specific control and the stack area 222 for specific control to "0" and initializing them is executed by the process corresponding to the specific control, and the process of clearing the work area 223 for non-specific control to "0" and initializing them is executed by the process corresponding to the non-specific control. This makes it possible for such initialization processes to be handled such that the work area 221 for specific control and the stack area 222 for specific control are treated as dedicated storage areas for the process corresponding to the specific control, and the work area 223 for non-specific control is treated as a dedicated storage area for the process corresponding to the non-specific control.

In the main processing (Figure 100), steps S6608 and S6614 are configured to monitor whether the set values are normal, but the processing to monitor whether these set values are normal may not be executed. This makes it possible to reduce the processing load of the processing at the start of operating power supply, which is executed when the supply of operating power to the main CPU 63 is started. Also, even if the processing at the start of operating power supply does not monitor whether the set values are normal, the setting monitoring processing (step S6820) of the timer interrupt processing (Figure 103), which is executed after the processing at the start of operating power supply is completed, monitors whether the set values are normal, making it possible to deal with any abnormal set values.

Furthermore, the setting monitoring process (step S6820) is not limited to being executed each time the timer interrupt process (Figure 103) is activated. For example, the setting monitoring process (step S6820) may be executed each time the timer interrupt process (Figure 103) is executed a predetermined number of times (for example, 10,000 times). In this case, it is possible to periodically monitor whether the setting values are normal, while reducing the frequency with which such monitoring is executed.

Alternatively, the setting monitoring process (step S6820) may be configured to be executed during the remaining processing (steps S6610 to S6613) in the main processing (Figure 100). In this case, it is possible to monitor whether the setting values are normal by utilizing the free time when the timer interrupt processing is not being executed.

Also, the setting monitoring process (step S6820) may be executed when a new round of play begins. More specifically, the setting monitoring process (step S6820) may be executed before the hit/miss determination process is executed when a new round of play begins. This makes it possible to prevent the hit/miss determination process from being executed when the setting value is abnormal.

Also, if the setting monitoring process (step S6820) identifies an abnormal setting value, instead of proceeding to the setting value update process (step S6904), a configuration may be adopted in which a game stop flag provided in the specific control work area 221 is set to "1." In this case, a positive judgment is made in step S6807 in the timer interrupt process (Figure 103), preventing the processing of steps S6808 to S6821. Therefore, if the setting value is abnormal, game progress is halted. However, since the processing of steps S6801 to S6806 is executed, power outage monitoring is performed, and the hit random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and further fraud detection is performed. Furthermore, if the game stop flag is set to "1," a notification indicating that the setting value should be updated may be executed to prompt the execution of the setting value update process. In this case, the gaming hall manager who has confirmed the notification can turn the power OFF and then turn the power ON in a manner that executes the setting value update process. This will clear the game stop flag to "0," cancel the state in which game progress has been stopped, and execute the setting value update process, setting the correct setting value.

Also, if the setting monitoring process (step S6820) identifies an abnormal setting value, the main process (Figure 100) may be started with the setting abnormality flag set to "1" in the specific control work area 221, and the game may be stopped with the setting abnormality flag set to "1," with the power required to be turned OFF and ON to release the stopped game. In this case, even if no operation is performed in the main process (Figure 100) to execute the setting value update process, by forcibly executing the setting value update process when the setting abnormality flag is set to "1," it is possible to forcibly set a new setting value using the setting value update process set in the main process (Figure 100).

Also, when the program monitoring unit 252 identifies the occurrence of an information abnormality and forcibly turns the reset signal from OFF to ON, an initialization process is performed on the work area 221 for specific control, and the setting value of the pachinko machine 10 may be set to "Setting 1."Also, when the program monitoring unit 252 identifies the occurrence of an information abnormality and forcibly turns the reset signal from OFF to ON, an initialization process is performed on the work area 221 for specific control, and then a setting value update process may be performed.

Also, if the program monitoring unit 252 identifies the occurrence of an information abnormality, the reset signal may not be forcibly turned from OFF to ON, and a clear process (step S6607) may be executed when no settings are updated, or a clear process (step S6620) and a setting value update process (step S6621) may be executed when settings are updated.

Furthermore, in the clearing process when the setting is not updated (step S6607), the setting value of the pachinko machine 10 can be configured to be "Setting 1" by initializing the storage area that stores setting value information in the work area 221 for specific control, or it can be configured to be a predetermined setting value other than "Setting 1". This makes it possible to set the setting value to a predetermined value when the clearing process when the setting is not updated is executed.

In addition, during the clearing process (step S6607) when updating non-settings, the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0", but they may be cleared to "0".

In addition, in step S7204 of the separate monitoring process (FIG. 107), the management start flag is not cleared to "0," but the management start flag may be cleared to "0." In addition, in step S7204 of the separate monitoring process (FIG. 107), the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may not be cleared to "0," and the calculation result storage area 234 may not be cleared to "0."

Furthermore, in step S7204 of the separate monitoring process (Figure 107), a "0" clear process and an initial setting process may be performed not only on the work area 223 for non-specific control but also on the stack area 224 for non-specific control. In this case, it is preferable not to erase the return address information for the management execution process after the separate monitoring process is completed in the stack area 224 for non-specific control, and the information of various registers used in the process corresponding to the specific control that has been saved in the stack area 224 for non-specific control.

Furthermore, the separate monitoring process (Figure 107) may be configured to monitor whether an abnormality has occurred in the non-specific control stack area 224, and if an abnormality is detected, to clear the non-specific control stack area 224 to "0" and perform an initial setting process. In this case, it is preferable not to erase the return address information for the management execution process in the non-specific control stack area 224 after the separate monitoring process has ended.

Furthermore, the configuration is not limited to one in which both the work area 221 for specific control and the stack area 222 for specific control are subject to checksum calculation; it may be one in which only the work area 221 for specific control is subject to checksum calculation, or one in which only the stack area 222 for specific control is subject to checksum calculation.

Thirty-first embodiment
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 30th embodiment. The configuration that differs from the 30th embodiment will be described below. Note that the description of the configuration that is the same as the 30th embodiment will basically be omitted.

Figure 108 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S7301 to S7322 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, power-on wait processing is executed (step S7301). During this power-on wait processing, the system waits for a predetermined wait time (specifically, one second) to elapse after the main processing is started, without proceeding to the next processing. During this power-on wait processing, the pattern display device 41 starts operating and is initialized. After that, access to the main RAM 65 is permitted (step S7302).

Then, it is determined whether the power outage flag provided in the specific control work area 221 in the main RAM 65 is set to "1" (step S7303). If the power outage flag is set to "1" (step S7303: YES), a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step S7304). The method of calculating the checksum is the same as step S6604 in the main processing (Figure 100) in the 30th embodiment above.

Then, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped, are read from the specific control work area 221, and the read checksums are compared with the checksum calculated in step S7304 (step S7305). It is then determined whether the checksums match (step S7306).

If a positive determination is made in step S7306, steps S7307 to S7320 are executed. In this case, steps S7307 to S7314 are identical to steps S6614 to S6621 in the main processing (Figure 100) of the 30th embodiment, and steps S7316 to S7320 are identical to steps S6609 to S6613 in the main processing (Figure 100) of the 30th embodiment.

Furthermore, if the reset button 68c has been pressed (step S7308: YES) and a negative judgment is made in any of steps S7309 to S7311, a clear process for non-setting update is executed (step S7315). The process content of the clear process for non-setting update is the same as step S6607 in the main process (FIG. 100) in the 30th embodiment. However, in this embodiment, after executing the clear process for non-setting update, the process proceeds to steps S7316 to S7320 without determining whether the setting values are normal. The clear process for non-setting update (step S7315) is executed only if a negative judgment is made in any of steps S7309 to S7311. However, because the determination of whether the setting values are normal is made in step S7307 before the processing of steps S7309 to S7311 is executed, there is no need to determine whether the setting values are normal after executing the clear process for non-setting update.

If a negative judgment is made in step S7303 or step S7306, i.e., if the power outage flag in the specific control work area 221 is not set to "1" or if a checksum abnormality occurs, an abnormality clearing process is executed (step S7321). Figure 109 is a flowchart showing the abnormality clearing process. Note that steps S7401 to S7405 in the abnormality clearing process are executed by the main CPU 63 using the specific control program and specific control data.

First, a clearing process is performed on the specific control work area 221 (step S7401). In this clearing process, the specific control work area 221 is cleared to "0" except for the area in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set (specifically, the setting value counter), and initial settings are performed on the area cleared to "0." This clears to "0" the area indicating whether the win/loss lottery mode is in high probability mode, so the win/loss lottery mode becomes low probability mode regardless of the win/loss lottery mode in effect immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserved storage area 65a and regular power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so the reserved information for the special map display unit 37a and the reserved information for the regular map display unit 38a are erased.

Then, a clear process is executed for the specific control stack area 222 (step S7402). During this clear process, the specific control stack area 222 is cleared to "0" and initialized.

Then, a push command is issued as "PUSH PSW" to save the flag register information of the main CPU 63 to the specific control stack area 222 (step S7403). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the flag register information changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program for the subroutine corresponding to the non-specific control clear process is started, it is possible to save the flag register information in the state before it changes after the subroutine is called or started to the specific control stack area 222. The size of the flag register information is 1 byte.

Then, the clearing process for non-specific control is initiated by reading a subroutine program corresponding to the clearing process for non-specific control set in the program for non-specific control (step S7404). In this case, information for specifying the return address for the clearing process in the event of an abnormality after the clearing process for non-specific control is executed is written to the stack area 222 for specific control by a push command. Then, when the clearing process for non-specific control is completed, information for specifying the return address is read by a pop command, and the program returns to the clearing process in the event of an abnormality indicated by the return address.

When returning to the abnormality clearing program after executing the non-specific control clearing process, the flag register information saved in the specific control stack area 222 in step S7402 is restored to the flag register of the primary CPU 63 by a pop command as "POP PSW" (step S7405). This restores the flag register information of the primary CPU 63 to the information at the time step S7402 was executed. In other words, the flag register information of the primary CPU 63 is restored to the information required to execute specific control.

Figure 110 is a flowchart showing the clearing process for non-specific control. Note that steps S7501 to S7516 in the clearing process for non-specific control are executed by the main CPU 63 using the non-specific control program and non-specific control data.

First, a load command is used to set "LD SP, Y(u+2)" to Y(u+2) as a fixed address at the start of non-specific control in the stack pointer of the primary CPU 63 (step S7501). In this case, the information of the last address in the stack area 224 for non-specific control is set in the stack pointer, similar to step S3901 of the management execution process (Figure 71) in the 15th embodiment described above.

Thereafter, the information in the WA register of the main CPU 63 is saved to the WA buffer set in the work area 223 for non-specific control by a load command as "LD (_WABUF), WA" (step S7502). Also, the information in the BC register of the main CPU 63 is saved to the BC buffer set in the work area 223 for non-specific control by a load command as "LD (_BCBUF), BC" (step S7503). Also,
The load command "LD (_DEBUF), DE" is used to save the information in the DE register of the primary CPU 63 to the DE buffer set in the work area 223 for non-specific control (step S7504). The load command "LD (_HLBUF), HL" is used to save the information in the HL register of the primary CPU 63 to the HL buffer set in the work area 223 for non-specific control (step S7505). The load command "LD (_IXBUF), IX" is used to save the information in the IX register of the primary CPU 63 to the IX buffer set in the work area 223 for non-specific control (step S7506). The load command "LD (_IYBUF), IY" is used to save the information in the IY register of the primary CPU 63 to the IY buffer set in the work area 223 for non-specific control (step S7507).

In addition to the flag register already described, the main CPU 63 also contains various general-purpose registers, auxiliary registers, and index registers. In this case, in steps S7502 to S7507, the information in some of these general-purpose registers, auxiliary registers, and index registers, namely the WA register, BC register, DE register, HL register, IX register, and IY register, is saved to the corresponding buffer in the non-specific control work area 223. Note that the information capacity of the WA register, BC register, DE register, HL register, IX register, and IY register is each 2 bytes.

The WA register, BC register, DE register, HL register, IX register, and IY register are used in the partial clearing process (step S7508) and initial setting process (step S7509) of the work area 223 for non-specific control, which are processes corresponding to non-specific control. By saving the information set in these registers to the work area 223 for non-specific control prior to the partial clearing process (step S7508) and initial setting process (step S7509) of the work area 223 for non-specific control, it is possible to save the information in these registers used during specific control before the non-specific control is started. Therefore, even if these registers are overwritten during non-specific control, by restoring the information saved in the work area 223 for non-specific control to these registers when the non-specific control is terminated, it is possible to restore the state of these registers to the state corresponding to specific control before the non-specific control was executed.

In addition, rather than saving all information from various general-purpose registers, auxiliary registers, and index registers to the non-specific control work area 223, information from the WA register, BC register, DE register, HL register, IX register, and IY register to be used in the partial clearing process (step S7508) and initial setting process (step S7509) of the non-specific control work area 223, which are processes corresponding to non-specific control, is selectively saved to the non-specific control work area 223. This makes it possible to reduce the capacity required to save register information in the non-specific control work area 223. Therefore, it is possible to save the above-mentioned register information while ensuring a large capacity for the non-specific control work area 223 that is available for the partial clearing process (step S7508) and initial setting process (step S7509) of the non-specific control work area 223. Naturally, for the various general-purpose registers, auxiliary registers, and index registers in the main CPU 63, other than the WA register, BC register, DE register, HL register, IX register, and IY register, the information set before the processing corresponding to the non-specific control is started is stored and held until the processing corresponding to the non-specific control is completed and the processing corresponding to the specific control is resumed.

In addition, by saving register information in the work area 223 for non-specific control rather than in the stack area 224 for non-specific control, it is possible to reduce the capacity of the stack area 224 for non-specific control. Furthermore, when using the stack area 224 for non-specific control, as already explained, the order in which information is written is such that later information is read first. Therefore, if the order in which information is read is shifted due to some kind of noise or other cause, all of the information read after that will be restored to different registers. The probability of this happening increases as the amount of information saved in the stack area 224 for non-specific control increases. In contrast, by saving register information in the work area 223 for non-specific control, it is possible to prevent the above-mentioned happening even when there is a lot of information to save.

After steps S7502 to S7507 are executed, a partial clear process is executed for the work area 223 for non-specific control (step S7508). In this partial clear process, all storage areas in the work area 223 for non-specific control are cleared to "0" except for the storage areas in which information from the various registers of the main CPU 63 used in the processing corresponding to specific control is saved. Specifically, the WA buffer, BC buffer, DE buffer, HL buffer, IX buffer, and IY buffer in the work area 223 for non-specific control are not cleared to "0," while all storage areas other than these various buffers are cleared to "0."

In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0." This makes it possible to resolve information abnormalities in the work area 223 for non-specific control. Furthermore, by not clearing to "0" the storage area where information from the various registers of the main CPU 63 used in processing corresponding to specific control is saved, it is possible to restore the information used in processing corresponding to specific control to the various registers of the main CPU 63 when processing corresponding to non-specific control ends and returns to processing corresponding to specific control.

In addition, in step S7508, the stack area 224 for non-specific control is not cleared to "0." The stack area 224 for non-specific control stores return address information for the clearing process (Figure 109) in the event of an abnormality after the clearing process for non-specific control has been completed, but by not clearing the stack area 224 for non-specific control to "0," it is possible to prevent this return address information from being erased.

After that, the initial setting process is executed (step S7509). In the initial setting process, initial settings are made to the storage area in the non-specific control work area 223 that was cleared to "0" in step S7508.

Then, using the load command "LD SP, Y(r+α)", Y(r+α) is set in the stack pointer of the primary CPU 63 as a fixed address upon return to specific control (step S7510), similar to step S3909 of the management execution process (FIG. 71) in the 15th embodiment. The address of Y(r+α) is set as an address between Y(r+8) and Y(s) in the stack area 222 for specific control.

Then, the information saved in the WA buffer of the work area 223 for non-specific control is overwritten in the WA register of the primary CPU 63 by a load command as "LD WA, (_WABUF)" (step S7511). The information saved in the BC buffer of the work area 223 for non-specific control is overwritten in the BC register of the primary CPU 63 by a load command as "LD BC, (_BCBUF)" (step S7512). The information saved in the DE buffer of the work area 223 for non-specific control is overwritten in the DE register of the primary CPU 63 by a load command as "LD DE, (_DEBUF)" (step S7513). The information saved in the HL buffer of the work area 223 for non-specific control is overwritten in the HL register of the primary CPU 63 by a load command as "LD HL, (_HLBUF)" (step S7514). Furthermore, the load command "LD IX, (_IXBUF)" overwrites the IX register of the primary CPU 63 with the information saved in the IX buffer of the work area 223 for non-specific control (step S7515). The load command "LD IY, (_IYBUF)" overwrites the IY register of the primary CPU 63 with the information saved in the IY buffer of the work area 223 for non-specific control (step S7516). By executing the processes of steps S7511 to S7516, it is possible to restore the information in the WA register, BC register, DE register, HL register, IX register, and IY register of the primary CPU 63 to the information corresponding to specific control that was present immediately before the process corresponding to non-specific control was started.

With the above configuration, if the power outage flag is not set to "1" or the checksum is abnormal during the main processing (Figure 108) executed when the supply of operating power to the main CPU 63 begins, an abnormality clearing process (step S7321) is executed, and not only the work area 221 for specific control and the stack area 222 for specific control, but also the work area 223 for non-specific control are cleared to "0" and initialized. If an information abnormality has occurred in the work area 221 for specific control, an information abnormality may also have occurred in the work area 223 for non-specific control. However, by initializing the work area 223 for non-specific control during the abnormality clearing process, it is possible to prevent processing corresponding to non-specific control from being executed in this state despite an information abnormality having occurred in the work area 223 for non-specific control.

Even when the process of clearing the work area 223 for non-specific control to "0" and initializing the work area 223 is executed during the abnormality clearing process (step S7321), the information in the various registers used in the process corresponding to the specific control that was saved in the work area 223 for non-specific control is not cleared to "0." This makes it possible to execute the process of clearing the work area 223 for non-specific control to "0" and initializing the work area 223 for non-specific control without erasing the information used in the process corresponding to the specific control after the process corresponding to the non-specific control has finished.

Even if the process of clearing the non-specific control work area 223 to "0" and initializing it is executed during the abnormality clearing process (step S7321), the process of clearing the non-specific control stack area 224 to "0" and initializing it is not executed. This makes it possible to prevent the return address information from being erased after the non-specific control clearing process (Figure 110) is completed.

The process of clearing the work area 221 for specific control and the stack area 222 for specific control to "0" and the process of initializing the same are executed by the process corresponding to the specific control, and the process of clearing the work area 223 for non-specific control to "0" and the process of initializing the same are executed by the process corresponding to the non-specific control. This makes it possible to treat the work area 221 for specific control and the stack area 222 for specific control as dedicated storage areas for the process corresponding to the specific control, and to treat the work area 223 for non-specific control as a dedicated storage area for the process corresponding to the non-specific control, even with regard to the process of clearing to "0" and the process of initializing the same.

Note that the configuration is not limited to one in which both the work area 221 for specific control and the stack area 222 for specific control are subject to checksum calculation; it may also be one in which only the work area 221 for specific control is subject to checksum calculation, or one in which only the stack area 222 for specific control is subject to checksum calculation.

The work area 223 for non-specific control may also be configured to be the target of checksum calculation. In this case, the work area 221 for specific control and the work area 223 for non-specific control may also be configured to be the target of checksum calculation, or the stack area 222 for specific control and the work area 223 for non-specific control may also be configured to be the target of checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control and the work area 223 for non-specific control may also be configured to be the target of checksum calculation.

The stack area 224 for non-specific control may also be configured to be the target of checksum calculation. In this case, the work area 221 for specific control and the stack area 224 for non-specific control may also be configured to be the target of checksum calculation, or the stack area 222 for specific control and the stack area 224 for non-specific control may also be configured to be the target of checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control, and the stack area 224 for non-specific control may also be configured to be the target of checksum calculation.

The work area 223 for non-specific control and the stack area 224 for non-specific control may also be configured to be the targets of checksum calculation. In this case, the work area 221 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may also be configured to be the targets of checksum calculation, or the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may also be configured to be the targets of checksum calculation, or the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may also be configured to be the targets of checksum calculation.

Furthermore, in steps S7508 and S7509 of the non-specific control clearing process (Figure 110), it is also possible to configure the non-specific control stack area 224 to be cleared to "0" and initialized, as well as the non-specific control work area 223. In this case, it is preferable not to erase the return address information for the clearing process in the event of an abnormality after the non-specific control clearing process has been completed.

In addition, in step S7508 of the clearing process for non-specific control (Figure 110), the management start flag is cleared to "0," but the management start flag may not be cleared to "0." In addition, in step S7508 of the clearing process for non-specific control (Figure 110), the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may not be cleared to "0," and the calculation result storage area 234 may not be cleared to "0."

<Thirty-second embodiment>
In this embodiment, the processing configuration for monitoring information abnormalities in the main RAM 65 using a checksum differs from that of the 30th embodiment. The configuration that differs from the 30th embodiment will be described below. Note that the description of the same configuration as the 30th embodiment will basically be omitted.

Figure 111 is a flowchart showing the power outage information storage process in this embodiment, which is executed by the main CPU 63. The power outage information storage process is executed in step S6801 of the timer interrupt process (Figure 103). Furthermore, steps S7601 to S7613 of the power outage information storage process are executed in the main CPU 63 using a specific control program and specific control data.

Steps S7601 to S7608 in the power outage information storage process are identical to steps S6701 to S6708 in the power outage information storage process (Figure 101) in the 30th embodiment. If a power outage is identified, a positive determination is made in step S7608 and power outage processing in steps S7609 to S7613 is executed.

Specifically, first, the power outage flag in the specific control work area 221 is set to "1" (step S7609). As a result, if power outage processing is executed normally and information is stored and maintained normally in the main RAM 65, the power outage flag in the specific control work area 221 will be set to "1" when the supply of operating power to the main CPU 63 is resumed again.

Then, checksums are calculated for the specific control work area 221 and the specific control stack area 222 (step S7610). In this case, the storage areas in the specific control work area 221 and the specific control stack area 222 that are the objects of calculation when calculating the specific control checksum are the same as the storage areas in the specific control work area 221 and the specific control stack area 222 that are the objects of calculation when calculating the specific control checksum in step S7701 of the checksum monitoring process (FIG. 112) described below. Furthermore, the storage areas that are the objects of calculation when calculating this specific control checksum include an area in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set (specifically, a setting value counter). The calculated specific control checksum is then stored in a storage area in the specific control work area 221 that is used to store the specific control checksum but is excluded from the storage area that is used to calculate the specific control checksum.

Then, checksums are calculated for the non-specific control work area 223 and the non-specific control stack area 224 (step S7611). In this case, the storage areas in the non-specific control work area 223 and the non-specific control stack area 224 that are the objects of calculation when calculating the checksum for non-specific control are the same as the storage areas in the non-specific control work area 223 and the non-specific control stack area 224 that are the objects of calculation of the checksum for non-specific control in step S7706 of the checksum monitoring process (FIG. 112) described below. The calculated checksum for non-specific control is then stored in a storage area in the specific control work area 221 that is used to store the checksum for non-specific control and that is excluded from the calculation of the checksum for specific control.

Then, all output port information in the register of the main CPU 63 is set to "0" (step S7612), and access to the main RAM 65 is prohibited (step S7613). The infinite loop continues until the power is completely cut off and processing can no longer be executed.

Next, the checksum monitoring process executed by the primary CPU 63 will be described with reference to the flowchart in Figure 112. Note that the checksum monitoring process is executed in place of steps S6604 to S6606 in the main processing (Figure 100). Furthermore, the processing of steps S7701 to S7711 in the checksum monitoring process is executed by the primary CPU 63 using a specific control program and specific control data.

First, a specific control checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step S7701). The method for calculating this specific control checksum is the same as step S7610 in the power outage information storage process (Figure 111). Then, the specific control checksum calculated and stored in the specific control work area 221 in step S7610 of the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped is read from the specific control work area 221, and the read specific control checksum is compared with the specific control checksum calculated in step S7701 (step S7702). Then, it is determined whether these specific control checksums match (step S7703).

If the checksums for specific control do not match (step S7703: NO), a clearing process is performed on the work area 221 for specific control (step S7704). This clearing process clears the work area 221 for specific control to "0" and performs initial settings, except for the area in the work area 221 for specific control where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter). This clears the area indicating whether the win/loss lottery mode is in high-probability mode to "0," thereby setting the win/loss lottery mode to low-probability mode regardless of the win/loss lottery mode in effect immediately before the supply of operating power to the pachinko machine 10 was stopped. Furthermore, a game round is not being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserved storage area 65a and normal power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so the reserved information for the special map display unit 37a and the reserved information for the normal map display unit 38a are erased. In addition, during this clearing process, various registers of the main CPU 63 are also cleared to "0" before initial setup is performed. In addition, the stack area 222 for specific control is cleared to "0" and initial setup is performed (step S7705).

If a positive judgment is made in step S7703, or if the processing of step S7705 is executed, a checksum for non-specific control is calculated for the non-specific control work area 223 and the non-specific control stack area 224 (step S7706). The method for calculating the checksum for non-specific control is the same as step S7611 in the power outage information storage processing (FIG. 111). Then, the checksum for non-specific control calculated and stored in the work area 221 for specific control in step S7611 of the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped is read from the work area 221 for specific control, and the read checksum for non-specific control is compared with the checksum for non-specific control calculated in step S7706 (step S7707). It is then determined whether the checksums for non-specific control match (step S7708).

If the checksums for non-specific control do not match (step S7708: NO), a "PUSH PSW" push command is issued to save the flag register information of the primary CPU 63 to the stack area 222 for specific control (step S7709). The flag register includes a carry flag, zero flag, P/V flag, sign flag, and half carry flag, and the flag register information changes depending on the execution results of arithmetic instructions, rotate instructions, and input/output instructions. By saving this flag register information before the program for the subroutine corresponding to the non-specific control clear process is started, it is possible to save the flag register information in the state before it changes after the subroutine is called or started to the stack area 222 for specific control. The size of the flag register information is 1 byte.

Then, the subroutine program corresponding to the non-specific control clear processing set in the non-specific control program is read, thereby starting the non-specific control clear processing (step S7710). In this case, information for specifying the return address of the checksum monitoring processing after the non-specific control clear processing is executed is written to the specific control stack area 222 by a push command. Then, when the non-specific control clear processing is completed, information for specifying the return address is read by a pop command, and processing returns to the checksum monitoring processing program indicated by the return address.

When returning to the abnormality clearing program after executing the non-specific control clearing process, the flag register information saved in the specific control stack area 222 in step S7709 is restored to the flag register of the primary CPU 63 by a pop command as "POP PSW" (step S7711). This restores the flag register information of the primary CPU 63 to the information at the time step S7709 was executed. In other words, the flag register information of the primary CPU 63 is restored to the information required to execute specific control.

Figure 113 is a flowchart showing the clearing process for non-specific control. Note that steps S7801 to S7818 in the clearing process for non-specific control are executed by the main CPU 63 using the program and data for non-specific control.

Steps S7801 to S7807 in the clearing process for non-specific control are identical to steps S7501 to S7507 in the clearing process for non-specific control in the 31st embodiment (Figure 110).

Then, a partial clear process is executed for the work area 223 for non-specific control (step S7808). In this partial clear process, all storage areas in the work area 223 for non-specific control are cleared to "0" except for the storage areas in which information from the various registers of the main CPU 63 used in the process corresponding to the specific control is saved. Specifically, among the storage areas in the work area 223 for non-specific control, the WA buffer, BC buffer, DE buffer, HL buffer, IX buffer, and IY buffer are not cleared to "0", while all storage areas other than these various buffers are cleared to "0".

In this case, the normal counter area 231, the open/close execution mode counter area 232, the high-frequency support mode counter area 233, the calculation result storage area 234, and the management start flag are all cleared to "0." This makes it possible to resolve information abnormalities in the work area 223 for non-specific control. Furthermore, by not clearing to "0" the storage area where information from the various registers of the main CPU 63 used in processing corresponding to specific control is saved, it is possible to restore the information used in processing corresponding to specific control to the various registers of the main CPU 63 when processing corresponding to non-specific control ends and returns to processing corresponding to specific control.

After that, the initial setting process is executed (step S7809). During the initial setting process, initial settings are made to the storage area in the non-specific control work area 223 that was cleared to "0" in step S7808.

Then, a partial clear process is performed on the non-specific control stack area 224 (step S7810). In this partial clear process, all storage areas of the non-specific control stack area 224 are cleared to "0" except for the storage area in which the return address information for the checksum monitoring process (FIG. 112) after the non-specific control clear process is completed is stored. This makes it possible to resolve the information anomaly in the non-specific control stack area 224 while preventing the return address information for the checksum monitoring process (FIG. 112) after the non-specific control clear process is completed from being erased.

After that, the initial setting process is executed (step S7811). During the initial setting process, the memory area in the non-specific control stack area 224 that was cleared to "0" in step S7810 is initialized.

Then, steps S7812 to S7818 are executed. These steps S7812 to S7818 are the same as steps S7510 to S7516 in the clearing process for non-specific control in the 31st embodiment (Figure 110).

With the above configuration, checksums are calculated separately for the work area 221 for specific control and the stack area 222 for specific control, and for the work area 223 for non-specific control and the stack area 224 for non-specific control. This makes it possible to identify information anomalies separately for the storage area in the main RAM 65 corresponding to specific control and the storage area in the main RAM 65 corresponding to non-specific control.

If an abnormality is found in the checksum for specific control, the specific control work area 221 and the specific control stack area 222 are cleared to "0" and initial setting is performed; if an abnormality is found in the checksum for non-specific control, the non-specific control work area 223 and the non-specific control stack area 224 are cleared to "0" and initial setting is performed. This makes it possible to narrow down the areas where the "0" clearing and initial setting are performed to those areas where a checksum abnormality has been identified.

The process of clearing the work area 221 for specific control and the stack area 222 for specific control to "0" and the process of initializing the same are executed by the process corresponding to the specific control, and the process of clearing the work area 223 for non-specific control to "0" and the process of initializing the same are executed by the process corresponding to the non-specific control. This makes it possible to treat the work area 221 for specific control and the stack area 222 for specific control as dedicated storage areas for the process corresponding to the specific control, and to treat the work area 223 for non-specific control as a dedicated storage area for the process corresponding to the non-specific control, even with regard to the process of clearing to "0" and the initial setting process.

In step S7808 of the clearing process for non-specific control (FIG. 113), the management start flag is cleared to "0," but the management start flag may not be cleared to "0." Also, in step S7808 of the clearing process for non-specific control (FIG. 113), the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may not be cleared to "0," and the calculation result storage area 234 may not be cleared to "0."

<Thirty-third embodiment>
In this embodiment, the processing configuration executed by the main CPU 63 differs from that of the fifteenth embodiment. The configuration that differs from the fifteenth embodiment will be described below. Note that the description of the same configuration as the fifteenth embodiment will basically be omitted.

Figure 114 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S7901 to S7924 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, the power-on initialization process is executed (step S7901). During the power-on initialization process, for example, the main process is started and then a predetermined waiting time (specifically, one second) passes before proceeding to the next process. During this predetermined waiting period, the operation of the pattern display device 41 is started and the initial settings are completed. In addition, access to the main RAM 65 is permitted.

Then, the internal function register setting process is executed (step S7902). In the internal function register setting process, the interrupt period of the first timer interrupt process (Fig. 117), which is a process that periodically interrupts the main process and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt process (Fig. 123), which is a process that periodically interrupts the main process and is started, is set to a second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, first timer interrupt processing and second timer interrupt processing exist as timer interrupt processing so that the interrupt periods are relatively long and short. Both the first timer interrupt processing and the second timer interrupt processing are started by interrupting the main processing. Furthermore, the second timer interrupt processing is started by interrupting the first timer interrupt processing. On the other hand, the first timer interrupt processing is not started by interrupting the second timer interrupt processing. Furthermore, if both the first timer interrupt processing and the second timer interrupt processing are not being executed and both the first interrupt period and the second interrupt period have elapsed, the second timer interrupt processing is started first, regardless of the order in which the periods elapse. In this respect, it can be said that the second timer interrupt processing is started with priority over the first timer interrupt processing.

The internal function register setting process sets the first interrupt period of the first timer interrupt process in a specified register of the main CPU 63, and sets the second interrupt period of the second timer interrupt process in a specific register of the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs processes such as setting the numerical ranges of various counters, such as the numerical range of the winning random number counter C1.

Then, the startup processing in progress flag provided in the work area 221 for specific control is set to "1" (step S7903). The startup processing in progress flag is a flag that the main CPU 63 uses to identify a situation in which the first timer interrupt processing should be terminated without executing the various processes set in the first timer interrupt processing, even if the first timer interrupt processing has been activated. By setting the startup processing in progress flag to "1", the first timer interrupt processing will be terminated without executing the various processes set in the first timer interrupt processing, even if the first timer interrupt processing has been activated.

Then, interrupt permission is set (step S7904). As a result, the first timer interrupt process (Fig. 117) is started at the first interrupt cycle, and the second timer interrupt process (Fig. 123) is started at the second interrupt cycle. However, because the startup process in progress flag was set to "1" in step S7903, even if the first timer interrupt process is started, the various processes set in the first timer interrupt process are not executed and the first timer interrupt process ends.

Then, it is determined whether the reset button 68c has been pressed (step S7905). In other words, it is determined whether the power to the pachinko machine 10 has been turned on while the reset button 68c is pressed, and the supply of operating power to the main CPU 63 has begun. In this embodiment, the main control unit 60 is provided with a setting key insertion unit 68a and a reset button 68c, but is not provided with an update button 68b. Furthermore, the main control unit 60 is provided with first to fourth notification display devices 201 to 204, as in the 11th embodiment, rather than first to third notification display devices 69a to 69c.

If the reset button 68c has not been pressed (step S7905: NO), it is determined whether the power outage flag provided in the specific control work area 221 is set to "1" (step S7906). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8202) of the first timer interrupt processing (Figure 117) described below. The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step S7906: YES), a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step S7907). Any method for calculating the checksum can be used, but it is the same calculation method as used when a checksum is calculated during power outage processing in the power outage information storage process (step S8202) of the first timer interrupt process (FIG. 117) described below. The checksum calculated during this power outage processing is stored in the specific control work area 221, but the storage area of the specific control work area 221 where this checksum is stored is excluded from the storage areas that are used for calculation when calculating the checksum.

In other words, when calculating the checksum, the target storage area is a portion of the specific control work area 221 and the specific control stack area 222. This target storage area is generally not rewritten with information if power supply, such as backup power, to the specific control work area 221 and the specific control stack area 222 continues from the time the checksum is calculated during power outage processing when the supply of operating power to MPU 62 is stopped until the supply of operating power to MPU 62 is resumed and the processing of step S7907 is executed. Therefore, if the information in the specific control work area 221 and the specific control stack area 222 has not changed between the time the supply of operating power to MPU 62 is stopped and the time the supply of operating power to MPU 62 is resumed, the checksum for the specific control work area 221 and the specific control stack area 222 will be the same as it was immediately before the supply of operating power to MPU 62 was stopped. Furthermore, the storage areas that are the subject of calculation when calculating this checksum include an area (specifically, a setting value counter) in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set. Note that the non-specific control work area 223 and the non-specific control stack area 224 are not included in the calculation of the checksum.

Then, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped, are read from the specific control work area 221, and the read checksums are compared with the checksum calculated in step S7907 (step S7908). It is then determined whether the checksums match (step S7909).

If a negative judgment is made in step S7906 or step S7909, i.e., if the power outage flag is not set to "1" or the checksums do not match, the game stop flag provided in the specific control work area 221 is set to "1" (step S7910). The game stop flag is a flag used by the main CPU 63 to identify whether a positive judgment is made in step S8207 in the first timer interrupt processing (Figure 117) described below, and the processing of steps S8208 to S8221 is not executed, i.e., whether the execution of processing to progress the game should be stopped. By setting the game stop flag to "1," a positive judgment is made in step S8207 in the first timer interrupt processing (Figure 117) described below, and the processing of steps S8208 to S8221 is not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was shut off, game progress will be stopped, and if the checksums do not match because the state of information stored in at least one of the specific control work area 221 and the specific control stack area 222 has changed since the previous power outage, game progress will be stopped.

In this case, the memory area that is the subject of calculation when calculating the checksum includes an area (specifically, a setting value counter) in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set, as described above. Therefore, if an abnormal setting value has occurred since the previous power outage, the checksum will not match, and game progress will be halted.

On the other hand, even if the game stop flag is set to "1," steps S8202 to S8206 of the first timer interrupt process (Figure 117) are executed. Therefore, even if game progress is stopped, power outage monitoring is executed, the hit random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is also executed.

Then, an abnormality command indicating that an abnormality occurred in the power outage flag or checksum when the supply of operating power began is sent to the audio and light-emitting control device 81 (step S7911). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the information abnormality at the start of the supply of operating power, and causes the speaker unit 54 to output a voice message saying "Please change the settings." In addition, a text image saying "Please change the settings" is displayed on the symbol display device 41. These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notifications may be configured to continue when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (step S7918) is executed.

When the gaming hall manager confirms the above notification while game progress has been halted, he or she will temporarily halt the supply of operating power to the pachinko machine 10, and then perform an operation to ensure that the setting value update process (step S7918) is executed when the supply of operating power to the pachinko machine 10 is resumed. This makes it possible to set new setting values in the setting value update process (step S7918) if an abnormality occurs with the power outage flag or checksum when the supply of operating power begins.

In particular, the memory area that is the target of calculation when calculating the checksum includes an area (specifically, a setting value counter) in the specific control work area 221 where setting value information indicating the setting status of the pachinko machine 10 is set, as described above. Therefore, if an abnormality occurs in the checksum, there is a possibility that an abnormality has occurred in the setting value. In contrast, if an abnormality occurs with the checksum as described above, execution of the setting value update process (step S7918) is prompted, making it possible to prevent play from being played with the abnormal setting value.

If the power outage flag is set to "1" and the checksum is normal (steps S7906 and S7909: YES), it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step S7912), and it is determined whether the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7913). The front door open sensor 95 is used to detect whether the front door frame 14 is open relative to the inner frame 13, as in the 30th embodiment, and the main body open sensor 96 is used to detect whether the gaming machine main body 12 is open relative to the outer frame 11, as in the 30th embodiment. If the setting key insertion unit 68a has been turned on using the setting key (step S7912: YES), and further, the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7913: YES), a setting confirmation process is executed (step S7914). In the setting confirmation process, the first to fourth notification display devices 201-204, which are used to display various parameters that are the results of game history management, execute a process to display a message indicating that the current setting values of the pachinko machine 10 are being confirmed and a message indicating the current setting values of the pachinko machine 10.

Figure 115 is a flowchart showing the setting confirmation process. Note that steps S8001 to S8003 in the setting confirmation process are executed using a specific control program and specific control data in the main CPU 63.

First, the setting confirmation display flag provided in the specific control work area 221 is set to "1" (step S8001). The setting confirmation display flag is a flag that allows the main CPU 63 to identify that the current setting values of the pachinko machine 10 are being confirmed. By setting the setting confirmation display flag to "1", corresponding display control is performed on the first to fourth alert display devices 201-204 in the second timer interrupt process (FIG. 123) described below. As a result, the first to fourth alert display devices 201-204 display an indication that the current setting values of the pachinko machine 10 are being confirmed and an indication of the current setting values of the pachinko machine 10 are displayed.

Then, it is determined whether the setting key insertion unit 68a has been turned off using the setting key (step S8002). In this case, it may be configured to determine whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or whether the setting key insertion unit 68a is in an OFF state. If the setting key insertion unit 68a has not been turned off (step S8002: NO), the process of step S8002 is repeated.

If the setting key insertion section 68a has been turned OFF (step S8002: YES), the setting confirmation display flag in the specific control work area 221 is cleared to "0" (step S8003). This cancels the state in which the first to fourth notification display devices 201-204 display an indication that the current setting values of the pachinko machine 10 are being confirmed and the current setting values of the pachinko machine 10. In this case, the first to fourth notification display devices 201-204 begin displaying the results of game history management.

As described above, in this embodiment, when the power to the pachinko machine 10 is turned on with the setting key insertion section 68a turned on using the setting key without pressing the reset button 68c, the reset button 68c is not pressed and the setting key insertion section 68a is turned on when the supply of operating power to the main CPU 63 begins and the main processing begins. This results in the setting confirmation processing being executed when processing is being executed at the start of the supply of operating power, which is the state before the processing that allows game play to proceed in the main processing is executed. This makes it possible to check the setting values when no game is being played.

Assuming that the setting value is checked while the game is still in progress, for example, if the setting value is checked during the execution of a game, there is a risk that the system will transition to the open/close execution mode while the setting value is being checked. In this case, even though the open/close execution mode has started, it may not be possible to launch the game ball toward the special electric winning device 32. Furthermore, if the setting value is checked during the execution of the open/close execution mode, the open/close execution mode will proceed while the setting value is being checked, and in this case too, it may not be possible to launch the game ball toward the special electric winning device 32.

Considering that game progress is halted when a setting value is checked, if setting value checking is initiated while a game is in progress, the processing required to halt game progress midway may become complicated. For example, if setting value checking is initiated during the execution of a game round and game progress is to be halted midway, processing is required to halt the game round midway. In this case, if the display of the changing patterns on the pattern display device 41 is halted midway when setting value checking is initiated, and the display of the changing patterns on the pattern display device 41 is resumed when setting value checking is completed, this requires correspondingly more complex processing. Furthermore, for example, if setting value checking is initiated during the execution of the open/close execution mode and game progress is to be halted midway, processing is required to halt the open/close execution mode midway. Furthermore, if setting value checking is initiated during the execution of the changing pattern display on the normal pattern display unit 38a and game progress is to be halted midway, processing is required to halt the display of the changing patterns midway. Furthermore, if setting value confirmation is initiated during the opening execution state of the normal power device 34a and the progress of the game is to be stopped midway, processing is required to stop the opening execution state midway. On the other hand, a configuration is also possible in which the setting value confirmation is waited until all games are completed, but in this case, it becomes necessary to wait until a situation occurs in which none of the game rounds, open/close execution mode, changing display of the image on the normal picture display unit 38a, and the opening execution state of the normal power device 34a are being executed, which may result in a long wait time before setting value confirmation can begin.

In contrast, the setting confirmation process is executed when the supply of operating power to the main CPU 63 begins, during the main processing, which is executed before the processing that enables game progress is executed, during the processing that occurs when the supply of operating power begins. Therefore, the setting values are confirmed when game progress has already been stopped. This makes it possible to avoid checking the setting values while game progress is in progress, and there is no need to stop game progress midway to check the setting values, or wait until game progress is stopped to check the setting values. This makes it possible to check the setting values appropriately.

Returning to the explanation of the main processing (FIG. 114), if the reset button 68c is pressed (step S7905: YES), RAM clear processing is executed (step S7915). In the RAM clear processing, the specific control work area 221 is cleared to "0" and initial settings are executed, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting value counter). As a result, the area indicating whether the win/loss lottery mode is the high probability mode is cleared to "0," so the win/loss lottery mode becomes the low probability mode regardless of the win/loss lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being executed, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserved storage area 65a and normal power reserved area 65c provided in the work area 221 for specific control are also cleared to "0", so that the reserved information for the special map display unit 37a and the reserved information for the normal map display unit 38a are erased. In addition, the RAM clear process clears the stack area 222 for specific control to "0" and performs initial settings. In addition, in the RAM clear process, various registers of the main CPU 63 are also cleared to "0" and then initial settings are performed. In this initial setting, the same process as the internal function register setting process (step S7902) in step S7902 is performed.

On the other hand, the RAM clearing process does not clear the non-specific control work area 223 and the non-specific control stack area 224 to "0." This makes it possible to prevent the non-specific control work area 223 and the non-specific control stack area 224 from being cleared to "0" by the clearing operation performed by the amusement hall manager.

Then, it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step S7916), and whether the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7917). The front door open sensor 95 is used to detect whether the front door frame 14 is open relative to the inner frame 13, as in the 30th embodiment, and the main body open sensor 96 is used to detect whether the gaming machine main body 12 is open relative to the outer frame 11, as in the 30th embodiment. If the setting key insertion unit 68a has been turned ON using the setting key (step S7916: YES) and further if the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S7917: YES), the setting value update process is executed (step S7918).

Figure 116 is a flowchart showing the setting value update process. Note that steps S8101 to S8107 in the setting value update process are executed using the specific control program and specific control data in the main CPU 63.

First, the setting update display flag provided in the specific control work area 221 is set to "1" (step S8101). The setting update display flag is a flag that allows the main CPU 63 to identify that the setting values of the pachinko machine 10 are being updated. By setting the setting update display flag to "1", corresponding display control is performed on the first to fourth alert display devices 201-204 in the second timer interrupt process (FIG. 123) described below. As a result, the first to fourth alert display devices 201-204 display an indication that the setting values of the pachinko machine 10 are being updated and an indication of the current setting values of the pachinko machine 10.

Then, it is determined whether the value of the setting value counter provided in the specific control work area 221 is greater than or equal to 1, corresponding to "Setting 1," and less than or equal to 6, corresponding to "Setting 6" (step S8102). If the value of the setting value counter is "0" or greater than or equal to 7, a negative determination is made in step S8102, and the setting value counter is set to "1" (step S8103). As a result, the setting value of the pachinko machine 10 becomes "Setting 1."

If a positive determination is made in step S8102 or if the processing of step S8103 is executed, it is determined whether the setting key insertion unit 68a has been turned off using the setting key (step S8104). In this case, the configuration may be such that it determines whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or whether the setting key insertion unit 68a is in the OFF state.

If the setting key insertion section 68a has not been turned OFF (step S8104: NO), and provided that the reset button 68c has been pressed (step S8105: YES), the value of the setting value counter in the specific control work area 221 is incremented by 1 (step S8106). This causes the setting value to be updated to the next higher level each time the reset button 68c is pressed. Furthermore, if the reset button 68c has not been pressed (step S8105: NO) or the setting value counter has been incremented by 1, processing returns to step S8102. However, if it is determined in step S8102 that the setting value counter value is 7 or greater, the setting value counter is set to "1" in step S8103. This means that pressing the reset button 68c once when the setting is "6" will return the setting to "1."

If the setting key insertion section 68a has been turned OFF (step S8104: YES), the setting update display flag in the specific control work area 221 is cleared to "0" (step S8107). This cancels the first to fourth notification display devices 201 to 204 from displaying an indication that the setting values of the pachinko machine 10 are being updated and the current setting values of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 will begin displaying the results of game history management.

As described above, in this embodiment, when the power to the pachinko machine 10 is turned on while the reset button 68c is pressed, the supply of operating power to the main CPU 63 begins, and the main processing begins. The reset button 68c is then pressed, and the RAM clear process (step S7915) is executed regardless of whether the setting key insertion section 68a is turned on. This means that the operation of turning on the power to the pachinko machine 10 while pressing the reset button 68c is uniquely linked to the execution of the RAM clear process (step S7915), making it possible to make the operation to trigger the RAM clear process (step S7915) easy to understand for the amusement hall manager.

Even if the RAM clear process (step S7915) is executed, the setting value counter in the specific control work area 221 is not cleared to "0" and the information in the setting value counter is not changed. This makes it possible to prevent the setting value from being changed even if the RAM clear process (step S7915) is executed.

In addition to turning on the power to the pachinko machine 10 while pressing the reset button 68c, turning on the power to the pachinko machine 10 while also turning on the setting key insertion section 68a with the setting key will execute not only the RAM clear process (step S7915) but also the setting value update process (step S7918). Furthermore, as already explained, turning on the power to the pachinko machine 10 while turning on the setting key insertion section 68a with the setting key without pressing the reset button 68c will execute the setting confirmation process (step S7914). This makes it possible to standardize the ON operation of the setting key insertion section 68a as the operation for executing processing related to setting values. This makes it possible to make the operation content for triggering processing related to setting values easy to understand for the amusement hall manager.

In addition, when the setting key insertion section 68a is turned on with the setting key while the pachinko machine 10 is powered on, if the reset button 68c is not pressed, a setting confirmation process is executed, but if the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process depending on whether the reset button 68c is pressed. This makes it possible to make the operation details for executing the desired process, either the setting confirmation process or the setting value update process, easier for the amusement hall manager to understand. Furthermore, by having more operation details for executing the setting value update process than the setting confirmation process, it becomes particularly difficult to perform fraudulent acts in the setting value update process.

Returning to the explanation of the main processing (FIG. 114), if the processing of step S7911 is executed, if a negative judgment is made in step S7912 or step S7913, if the processing of step S7914 is executed, if a negative judgment is made in step S7916 or step S7917, or if the processing of step S7918 is executed, the startup processing in progress flag in the specific control work area 221 is cleared to "0" (step S7919). Clearing the startup processing in progress flag to "0" cancels the state in which various processes set in the first timer interrupt processing are not executed even if the first timer interrupt processing is activated. Note that in step S7919, the power outage flag in the specific control work area 221 is also cleared to "0".

A return command is then sent to the audio and light control device 81 (step S7920). The return command includes information indicating the number of pending information for the special symbol display unit 37a, information indicating the current win/lose lottery mode, information indicating the current support mode, information indicating whether the open/close execution mode is currently being executed, and information indicating whether a game round is currently being executed. This information is set based on the information stored in the work area 221 for specific control. Upon receiving the return command, the audio and light control device 81 changes the display content of the symbol display device 41, the light emission content of the display light-emitting unit 53, and the sound output content of the speaker unit 54 to content corresponding to the various information set in the return command.

When checking the setting values of the pachinko machine 10, it is necessary to turn on the power to the pachinko machine 10 while turning on the setting key insertion section 68a with the setting key. For example, if it becomes necessary to check the setting values during a game, the power to the pachinko machine 10 is turned off during the game, and then the power to the pachinko machine 10 is turned on while turning on the setting key insertion section 68a with the setting key. In this case, because backup power is not supplied to the RAM provided in the sound and light-emitting control device 81, the information used to control the presentation of the game is erased from the RAM of the sound and light-emitting control device 81 when the power to the pachinko machine 10 is turned off. In contrast, because backup power is supplied to the main RAM 65 and the main RAM 65 is not cleared when the setting values are confirmed, if the power to the pachinko machine 10 is turned OFF during a game and then the power to the pachinko machine 10 is turned ON while the setting key insertion unit 68a is turned ON with the setting key, the display of changing patterns will resume on the special symbol display unit 37a after the setting confirmation process has been executed. This will result in a situation where, even though the special symbol display unit 37a is displaying changing patterns, the pattern display device 41 is not displaying changing patterns.

In response to this, after the setting confirmation process is completed, a return command is sent to the audio and light control device 81, and this return command includes information indicating whether a game round is currently being played. Then, upon receiving the return command, the audio and light control device 81 causes the pattern display device 41 to begin displaying changing patterns. This makes it possible to prevent a situation in which changing patterns are not displayed on the pattern display device 41 despite the special pattern display unit 37a displaying changing patterns. This changing pattern display is performed at a relatively fast speed so that each changing pattern is indistinguishable or difficult to distinguish for the player. Furthermore, the return command does not include the results of the win/loss determination process and the allocation determination process for the game round to be resumed, nor does it include information indicating the end timing of the game round to be resumed. Therefore, when the sound and light emission control device 81 starts the variable display of patterns on the pattern display device 41 based on a return command, if the game turn to be resumed corresponds to a miss result, and a command indicating the start of the next game turn or a command to start a demo display on the pattern display device 41 is received, the sound and light emission control device 81 ends the variable display of patterns based on the return command and starts a display corresponding to the newly received command; if the game turn to be resumed corresponds to a jackpot result, and an opening command indicating the start of the open/close execution mode is received, the sound and light emission control device 81 ends the variable display of patterns based on the return command and starts an opening performance.

Furthermore, if the return command includes information indicating that the opening and closing execution mode is currently being executed, the audio and light control device 81 will cause the symbol display device 41 to start a display effect indicating that the opening and closing execution mode is in progress. This makes it possible for the player to recognize that the opening and closing execution mode is being executed.

Then, the process proceeds to the remaining processing of steps S7921 to S7924. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 117) and the second timer interrupt processing (Figure 123), but there is remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps S7921 to S7924. In this respect, the remaining processing of steps S7921 to S7924 can be said to be non-periodic processing executed non-periodically. Steps S7921 to S7924 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, the first timer interrupt processing executed by the main CPU 63 will be explained with reference to the flowchart in Figure 117. As already explained, the first timer interrupt processing is periodically started at a 4 millisecond cycle, which is the first interrupt cycle. Furthermore, the program corresponding to the first timer interrupt processing is set in the program for specific control.

First, it is determined whether the startup processing in progress flag in the specific control work area 221 is set to "1" (step S8201). As already explained, the startup processing in progress flag is set to "1" in step S7903 of the main processing (Figure 114). Then, if the startup processing in progress flag is set to "1" (step S8201: YES), the first timer interrupt processing is terminated without executing the various processes of steps S8202 to S8221. This makes it possible to prevent the various processes for controlling game progress in the first timer interrupt processing from being executed until the processing at the start of the supply of operating power is completed and the execution of the processes for controlling game progress is permitted, even if the configuration allows the execution of the first timer interrupt processing and second timer interrupt processing early when the supply of operating power to the pachinko machine 10 is initiated and the main processing (Figure 114) is initiated.

As already explained, the startup processing flag is cleared to "0" in step S7919 when processing at the start of the supply of operating power in the main processing (Figure 114) is completed. In the first timer interrupt processing, if the startup processing flag is not set to "1" (step S8201: NO), processing from step S8202 onwards is executed.

Steps S8202 through S8219 and S8221 execute the same processing as steps S3701 through S3719 of the timer interrupt processing (Figure 69) in the fifteenth embodiment described above. These processes are executed by the main CPU 63 using a program and data for specific control. In this case, as already explained, if the main processing (Figure 114) determines that the power outage flag is not set to "1" (step S7906: NO) or that the checksums do not match (step S7909: NO), the game stop flag in the work area 221 for specific control is set to "1" (step S7910). If the game stop flag is set to "1," the first timer interrupt processing executes steps S8201 through S8206, but does not execute steps S8208 through S8221 due to a positive determination in step S8207. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was shut off, game progress is stopped. Also, if the checksums do not match because the information storage state has changed since the previous power outage in at least one of the specific control work area 221 and the specific control stack area 222, game progress is stopped. For example, if the processing of step S8212 is not executed, the release of game balls is prohibited. Furthermore, if the processing of step S8214 is not executed, the execution of game turns and open/close execution mode is prohibited. Furthermore, if the processing of step S8218 is not executed, the payout of game balls is prohibited.

However, even in this situation where game progress is stopped, power outage monitoring is performed in step S8202, and the hit random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated in steps S8203 and S8204, and fraud detection is performed in step S8206.

In the first timer interrupt process, setting monitoring processing is executed in step S8220. Figure 118 is a flowchart showing the setting monitoring processing. Note that steps S8301 to S8303 in the setting monitoring processing are executed using a specific control program and specific control data in the main CPU 63.

The value of the setting value counter in the specific control work area 221 is checked to determine whether the setting value of the pachinko machine 10 is normal (step S8301). Specifically, if the setting value set in the setting value counter is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

If the set value is abnormal (step S8301: NO), the game stop flag in the specific control work area 221 is set to "1" (step S8302), similar to step S7910 in the main processing (Figure 114). By setting the game stop flag to "1," a positive judgment is made in step S8207 of the first timer interrupt processing (Figure 117), preventing the processing of steps S8208 to S8221. As a result, if it is determined that the set value is abnormal, game progress is stopped. On the other hand, even when the game stop flag is set to "1," the processing of steps S8202 to S8206 in the first timer interrupt processing (Figure 117) is executed. Therefore, even when game progress is stopped, power outage monitoring is performed, and the hit random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and further fraud detection is performed.

Then, an abnormality command indicating that the setting value is abnormal is sent to the audio and light-emitting control device 81 (step S8303). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the setting value abnormality and outputs a voice message saying "Please change the setting" from the speaker unit 54. The symbol display device 41 also displays a text image saying "Please change the setting." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notifications may be configured to continue when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (step S7918) of the main process (FIG. 114) is executed.

When the gaming hall manager sees the above notification while game progress has been stopped, he or she will temporarily stop the supply of operating power to the pachinko machine 10, and then perform an operation to ensure that the setting value update process (step S7918) is executed when the supply of operating power to the pachinko machine 10 is resumed. This makes it possible to set new setting values in the setting value update process (step S7918) if a setting value abnormality occurs.

Here, the process of monitoring whether the set value is abnormal is executed by the first timer interrupt process (Figure 117), which is periodically started. This makes it possible to monitor whether the set value is abnormal even when a game is being played. This makes it possible to prevent play from continuing even when the set value is abnormal. Furthermore, monitoring whether the set value is abnormal is executed each time a monitoring trigger occurs. This makes it possible to increase the frequency with which the set value is monitored for abnormalities.

The main processing (FIG. 114) does not include a process for monitoring whether the set values are normal. If a process for monitoring whether the set values are normal were included in the process for starting the supply of operating power in the main processing (FIG. 114), not only would it be necessary to monitor the power outage flag and checksum but also to monitor whether the set values are normal when the supply of operating power starts, which would increase the monitoring load. Furthermore, if an abnormal set value was identified when the supply of operating power starts, a RAM clear process (step S7915) and a set value update process (step S7918) would be executed, which would complicate the processing configuration. In contrast, the main processing (FIG. 114) does not include a process for monitoring whether the set values are normal, which makes it possible to optimize the processing configuration for the process for starting the supply of operating power. Furthermore, even if a process for monitoring whether the set values are normal is not included in the process for starting the supply of operating power, the setting monitoring process (step S8220) is executed in the first timer interrupt process (FIG. 117) as described above, so it is possible to address an abnormal set value.

In a configuration in which the first timer interrupt processing is executed as described above, in this embodiment, as already explained, there is a second timer interrupt processing (Figure 123) separate from the first timer interrupt processing (Figure 117), and the second timer interrupt processing interrupts and is started even when the first timer interrupt processing is in the middle of execution. In this case, although not shown in the first timer interrupt processing, the timer interrupt processing is prohibited and allowed before and after each of steps S8201 to S8221. For example, the timer interrupt processing is prohibited before executing the lottery random number update processing (step S8203), and is allowed after executing the lottery random number update processing (step S8203). This makes it possible to prevent the second timer interrupt processing from interrupting and being started while the lottery random number update processing is being executed. In addition, timer interrupt processing is prohibited before executing the special image special power control processing (step S8214), and timer interrupt processing is permitted after executing the special image special power control processing (step S8214). This makes it possible to prevent the second timer interrupt processing from interrupting and starting while the special image special power control processing is being executed.

Next, we will explain the configuration for controlling the display of various display units using the main CPU 63. Figure 119 is a block diagram explaining the configuration for controlling the display of various display units using the main CPU 63.

The display control performed by the main CPU 63 includes the special chart display unit 37a, the special chart reserved display unit 37b, the regular chart display unit 38a, the regular chart reserved display unit 38b, and the first to fourth notification display devices 201-204. All of these are provided as segment display units with an array of LED display segments. These segment display units are illuminated when data corresponding to the illuminated state (for example, data "1", which is one of the binary data values) is set, and are illuminated when data corresponding to the unlit state (for example, data "0", which is the other of the binary data values) is set.

The main control board 61 is provided with a first display circuit 261 corresponding to the special map display unit 37a, a second display circuit 262 corresponding to the special map reserve display unit 37b, a third display circuit 263 corresponding to the regular map display unit 38a, a fourth display circuit 264 corresponding to the regular map reserve display unit 38b, and a fifth display circuit 265 corresponding to the first to fourth alert display devices 201-204. Note that, in the eleventh embodiment, the main control board 61 was provided with first to fourth display ICs 205-208 in one-to-one correspondence with the first to fourth alert display devices 201-204, but in this embodiment, these first to fourth display ICs 205-208 are not provided.

The first display circuit 261 provides data corresponding to the supplied display data to each of the multiple display segments of the special chart display unit 37a. As a result, each display segment of the special chart display unit 37a is illuminated or extinguished in a manner corresponding to the display data provided to the first display circuit 261. In this case, the first display circuit 261 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the special chart display unit 37a that are illuminated by the display data provided to the first display circuit 261 gradually become extinguished after the predetermined period has passed without new display data being provided to the first display circuit 261. Furthermore, with this configuration, the same display data as that used in the previous display data output process is supplied to the first display circuit 261 not only when the display content of the special chart display unit 37a is changed, but also when the display content of the special chart display unit 37a is not changed.

The number of display segments provided in the special chart display unit 37a is eight. Therefore, 8-bit data is provided to the first display circuit 261 as display data for controlling the display of the special chart display unit 37a.

The second display circuit 262 provides data corresponding to the supplied display data to each of the multiple display segments of the special chart reserved display unit 37b. As a result, each display segment of the special chart reserved display unit 37b is illuminated or extinguished in a manner corresponding to the display data provided to the second display circuit 262. In this case, the second display circuit 262 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the special chart reserved display unit 37b that are illuminated by the display data provided to the second display circuit 262 gradually become extinguished after the predetermined period has passed without new display data being provided to the second display circuit 262. Furthermore, with this configuration, the same display data as that used in the previous display data output process is supplied to the second display circuit 262 not only when the display content of the special chart reserved display unit 37b is changed, but also when the display content of the special chart reserved display unit 37b is not changed.

The number of display segments provided in the special drawing reserved display unit 37b is four. Therefore, 4 bits of data are provided to the second display circuit 262 as display data for display control of the special drawing reserved display unit 37b. However, because display data is provided in 8-bit units, 8 bits of data are also provided when display data is provided to the second display circuit 262, but 4 bits of that data are used as display data for display control of the special drawing reserved display unit 37b.

The third display circuit 263 provides data corresponding to the supplied display data to each of the multiple display segments of the map display unit 38a. As a result, each display segment of the map display unit 38a is illuminated or extinguished in a manner corresponding to the display data provided to the third display circuit 263. In this case, the third display circuit 263 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the map display unit 38a that are illuminated by the display data provided to the third display circuit 263 gradually become extinguished after the predetermined period has passed without new display data being provided to the third display circuit 263. Furthermore, with this configuration, the same display data as that used in the previous display data output process is supplied to the third display circuit 263 not only when the display content of the map display unit 38a is changed, but also when the display content of the map display unit 38a is not changed.

The number of display segments provided in the general map display unit 38a is eight. Therefore, 8-bit data is provided to the third display circuit 263 as display data for controlling the display of the general map display unit 38a.

The fourth display circuit 264 provides data corresponding to the supplied display data to each of the multiple display segments of the map reserve display unit 38b. As a result, each display segment of the map reserve display unit 38b is illuminated or extinguished in a manner corresponding to the display data provided to the fourth display circuit 264. In this case, the fourth display circuit 264 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has passed, the display data gradually approaches an all-zero state. Therefore, the display segments of the map reserve display unit 38b that are illuminated by the display data provided to the fourth display circuit 264 gradually become extinguished after the predetermined period has passed without new display data being provided to the fourth display circuit 264. Furthermore, due to this configuration, the same display data as that used in the previous display data output process is supplied to the fourth display circuit 264 not only when the display content of the map reserve display unit 38b is changed, but also when the display content of the map reserve display unit 38b is not changed.

The number of display segments provided in the regular map reserve display unit 38b is four. Therefore, 4 bits of data are provided to the fourth display circuit 264 as display data for display control of the regular map reserve display unit 38b. However, because display data is provided in 8-bit units, 8 bits of data are also provided when display data is provided to the fourth display circuit 264, but 4 bits of that data are used as display data for display control of the regular map reserve display unit 38b.

The fifth display circuit 265 provides data corresponding to the supplied display data to each of the multiple display segments provided on each of the first to fourth alarm display devices 201 to 204. As a result, each display segment of the first to fourth alarm display devices 201 to 204 is illuminated or extinguished in a manner corresponding to the display data provided to the fifth display circuit 265. In this case, although the fifth display circuit 265 can store and retain the provided display data for a predetermined period (e.g., 16 milliseconds), after the predetermined period has elapsed, the display data gradually approaches an all-0 state. Therefore, the display segments of the first to fourth alarm display devices 201 to 204 that are illuminated by the display data provided to the fifth display circuit 265 gradually become extinguished after a predetermined period has elapsed without new display data being provided to the fifth display circuit 265. Furthermore, with this configuration, not only when the display content of the first to fourth alarm display devices 201 to 204 is changed, but also when the display content of the first to fourth alarm display devices 201 to 204 is not changed, the same display data as that of the previous display data output process is supplied to the fifth display circuit 265.

Each of the first to fourth alert display devices 201-204 has seven display segments. Display data is provided in 8-bit units. When the display data of the first to fourth alert display devices 201-204 is provided to the fifth display circuit 265, 7-bit display data corresponding to the first alert display device 201 is provided as 8-bit data, followed by 7-bit display data corresponding to the second alert display device 202 as 8-bit data, followed by 7-bit display data corresponding to the third alert display device 203 as 8-bit data, and finally 7-bit display data corresponding to the fourth alert display device 204 as 8-bit data.

In a configuration in which the first to fifth display circuits 261-265 are provided as described above, the main CPU 63 supplies display data to the display IC 266. In other words, rather than a display IC 266 being provided one-to-one with the first to fifth display circuits 261-265, a single display IC 266 is provided that is common to all of the first to fifth display circuits 261-265. When the main CPU 63 supplies display data to the display IC 266, it also supplies type data to the display IC 266 indicating which of the first to fifth display circuits 261-265 the display data corresponds to.

Regarding the electrical connection between the main CPU 63 and the display IC 266 in more detail, the main CPU 63 and the display IC 266 are electrically connected using a type data signal line LN1, a type clock signal line LN2, a display data signal line LN3, and a display clock signal line LN4. These signal lines LN1 to LN4 are all signal lines for transmitting signals from the main CPU 63 to the display IC 266 via one-way communication.

Category data is transmitted serially from the main CPU 63 to the display IC 266 using the category data signal line LN1. In this case, the division of each bit of the serially transmitted category data is indicated by a category clock signal transmitted from the main CPU 63 to the display IC 266 using the category clock signal line LN2. The category data indicates which of the first to fifth display circuits 261 to 265 the display data being transmitted corresponds to. The category data is transmitted as five-bit data consisting of bits 1 to 5. If the display data corresponds to the first display circuit 261, the first bit is high and the other bits are low. If the display data corresponds to the second display circuit 262, the second bit is high and the other bits are low. If the display data corresponds to the third display circuit 263, the third bit is high and the other bits are low. If the display data corresponds to the fourth display circuit 264, the fourth bit is high and the other bits are low. If the display data corresponds to the fifth display circuit 265, the fifth bit will be at a high level and the other bits will be at a low level.

Display data is transmitted serially from the main CPU 63 to the display IC 266 using the display data signal line LN3. In this case, the division of each bit of the serially transmitted display data is indicated by a display clock signal transmitted from the main CPU 63 to the display IC 266 using the display clock signal line LN4. The display data is transmitted in 8-bit units, using the first to eighth bits.

During the second timer interrupt process (Fig. 123) described below, the main CPU 63 transmits display data corresponding to each of the first through fifth display circuits 261-265 to the display IC 266. In this case, during each processing round of the second timer interrupt process, display data is transmitted to one of the first through fifth display circuits 261-265, and the display circuits 261-265 to which display data is transmitted change by one each time a new processing round of the second timer interrupt process occurs, in the order of the nth display circuit → the n+1th display circuit. Furthermore, during the second timer interrupt process in the processing round following the processing round in which display data corresponding to the fifth display circuit 265, which is the last in the order, is transmitted, display data corresponding to the first display circuit 261, which is the first in the order, is transmitted. In the second timer interrupt process that sends display data to one of the first to fourth display circuits 261-264, only one 8-bit display data is sent, but in the second timer interrupt process that sends display data to the fifth display circuit 265, four 8-bit display data are sent, corresponding to the number of the first to fourth alarm display devices 201-204.

In the configuration in which the main CPU 63 transmits display data as described above, various storage areas referenced by the main CPU 63 to transmit display data are set in the work area 221 for specific control and the work area 223 for non-specific control. Figure 120(a) is an explanatory diagram illustrating the various buffers 271-275 provided in the work area 221 for specific control, and Figure 120(b) is an explanatory diagram illustrating the various storage areas 234, 276 provided in the work area 223 for non-specific control.

As shown in FIG. 120(a), the work area 221 for specific control is provided with a first display data buffer 271, a second display data buffer 272, a third display data buffer 273, a fourth display data buffer 274, and a fifth display data buffer 275.

The first display data buffer 271 stores display data to be supplied to the first display circuit 261. As already explained, the first display circuit 261 is provided to correspond to the special symbol display unit 37a, and therefore the first display data buffer 271 stores display data for causing the special symbol display unit 37a to perform a specified display. In this case, the storage of display data in the first display data buffer 271 is performed by the display control process (step S8216) based on the contents of the special symbol special power control process (step S8214) in the first timer interrupt process (Fig. 117). Furthermore, when the second timer interrupt process (Fig. 123) that transmits display data to the first display circuit 261 is processed, the display data stored in the first display data buffer 271 is transmitted to the display IC 266 not only when the display data stored in the first display data buffer 271 has been changed, but also when the display data has not been changed.

The second display data buffer 272 stores display data to be supplied to the second display circuit 262. As already explained, the second display circuit 262 is provided to correspond to the special symbol pending display unit 37b, and therefore the second display data buffer 272 stores display data for causing the special symbol pending display unit 37b to perform a specified display. In this case, the storage of display data in the second display data buffer 272 is performed by the display control process (step S8216) based on the contents of the special symbol special power control process (step S8214) in the first timer interrupt process (Fig. 117). Furthermore, when the second timer interrupt process (Fig. 123) that transmits display data to the second display circuit 262 is processed, the display data stored in the second display data buffer 272 is transmitted to the display IC 266 not only when the display data stored in the second display data buffer 272 has been changed, but also when the display data has not been changed.

The third display data buffer 273 stores display data to be supplied to the third display circuit 263. As already explained, the third display circuit 263 is provided to correspond to the normal map display unit 38a, and therefore the third display data buffer 273 stores display data for causing the normal map display unit 38a to perform a specified display. In this case, the storage of display data in the third display data buffer 273 is performed in the display control process (step S8216) based on the contents of the normal map normal power control process (step S8215) in the first timer interrupt process (Figure 117). Furthermore, when the second timer interrupt process (Figure 123) that transmits display data to the third display circuit 263 is processed, the display data stored in the third display data buffer 273 is transmitted to the display IC 266 not only when the display data stored in the third display data buffer 273 has been changed, but also when the display data has not been changed.

The fourth display data buffer 274 stores display data to be supplied to the fourth display circuit 264. As already explained, the fourth display circuit 264 is provided to correspond to the normal map pending display unit 38b, and therefore the fourth display data buffer 274 stores display data for causing the normal map pending display unit 38b to perform a specified display. In this case, the storage of display data in the fourth display data buffer 274 is performed in the display control process (step S8216) based on the contents of the normal map normal power control process (step S8215) in the first timer interrupt process (Figure 117). Furthermore, when the second timer interrupt process (Figure 123) that transmits display data to the fourth display circuit 264 is processed, the display data stored in the fourth display data buffer 274 is transmitted to the display IC 266 not only when the display data stored in the fourth display data buffer 274 has been changed, but also when the display data has not been changed.

The fifth display data buffer 275 stores display data to be supplied to the fifth display circuit 265. As already explained, the fifth display circuit 265 is provided to correspond to the first to fourth alarm display devices 201 to 204, and therefore the fifth display data buffer 275 stores display data for causing the first to fourth alarm display devices 201 to 204 to perform a specified display. When the second timer interrupt process for transmitting display data to the fifth display circuit 265 is processed, the display data stored in the fifth display data buffer 275 is transmitted to the display IC 266 not only when the display data stored in the fifth display data buffer 275 has been changed, but also when the display data has not been changed.

Here, the first to fourth notification display devices 201-204 display the results of game history management, and when the setting confirmation process (FIG. 115) or setting value update process (FIG. 116) is executed, the display corresponds to the current setting value. In this case, since the fifth display data buffer 275 is provided in the work area 221 for specific control, the process of storing display data in the fifth display data buffer 275 is performed as a process corresponding to specific control. On the other hand, the process for deriving the game history management results is performed as a process corresponding to non-specific control, and the 61st to 68th parameters, which are the results of game history management, are displayed sequentially on the first to fourth notification display devices 201-204.

As shown in FIG. 120(b), the work area 223 for non-specific control not only has a calculation result memory area 234 for storing the 61st to 68th parameters, but also a display target setting area 276 for storing those parameters among the 61st to 68th parameters to be displayed on the first to fourth alarm display devices 201 to 204. In this embodiment, as in the above-described 15th embodiment, the calculation result of one parameter is continuously displayed for 10 seconds. Therefore, in the processing corresponding to non-specific control, the calculation result of the parameter to be displayed is read from the calculation result memory area 234 according to a predetermined display order every 10 seconds, and the calculation result of the read parameter is stored in the display target setting area 276. When the first through fourth notification display devices 201 through 204 are in a situation where they are to display the gaming history management results, the display data stored in the display target setting area 276 is read out in the second timer interrupt process (FIG. 123), which corresponds to specific control, and the read out display data is stored in the fifth display data buffer 275.

On the other hand, when the setting confirmation process (FIG. 115) is being executed, the fifth display data buffer 275 stores display data to enable the first to fourth notification display devices 201 to 204 to display an indication that the current setting value of the pachinko machine 10 is being confirmed and an indication of the current setting value of the pachinko machine 10 in the second timer interrupt process (FIG. 123), which is a process corresponding to specific control. When the setting value update process (FIG. 116) is being executed, the fifth display data buffer 275 stores display data to enable the first to fourth notification display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being updated and an indication of the current setting value of the pachinko machine 10 in the second timer interrupt process (FIG. 123), which is a process corresponding to specific control.

In a configuration in which the first through fifth display data buffers 271-275 are provided as described above, the main CPU 63 reads display data from the display data buffer 271-275 corresponding to each second timer interrupt process (Figure 123) during that process, transmits the read display data to the display IC 266, and also transmits type data to the display IC 266 indicating which of the first through fifth display circuits 261-265 the display data corresponds to. Figure 121 is an explanatory diagram for explaining the electrical configuration of the display IC 266.

As shown in FIG. 121, the display IC 266 comprises a type data buffer 281, a selection signal output unit 282, a display data buffer 283, and a display data output unit 284. The display data buffer 283 stores display data received from the main CPU 63. The display data output unit 284 transmits the display data stored in the display data buffer 283 to the first to fifth display circuits 261 to 265. The type data buffer 281 stores type data received from the main CPU 63. The selection signal output unit 282 outputs a selection signal to designate the display circuit 261 to 265 among the first to fifth display circuits 261 to 265 that corresponds to the type data stored in the type data buffer 281 as the recipient of the display data.

In more detail, as shown in FIG. 119, the display IC 266 and the first display circuit 261 are electrically connected using a display signal group 291. The display signal group 291 is configured to enable 8 bits of display data to be transmitted at one time, and the 8-bit display data is transmitted from the display IC 266 via parallel communication. In addition, a branch signal group 292 is provided by branching from the display signal group 291, and this branch signal group 292 is electrically connected to each of the second display circuit 262, the third display circuit 263, the fourth display circuit 264, and the fifth display circuit 265. Like the display signal group 291, the branch signal group 292 is configured to enable 8 bits of display data to be transmitted at one time, and the 8-bit display data is transmitted from the display IC 266 via parallel communication.

By providing the display signal group 291 and branch signal group 292 as described above, when display data stored in the display data buffer 283 is transmitted by the display data output unit 284, the display data is supplied to all of the first through fifth display circuits 261 through 265. In this case, first through fifth selection signal lines 301 through 305 are provided to specify the display circuits 261 through 265 that should receive and use the supplied display data.

The first selection signal line 301 is provided to electrically connect the display IC 266 and the first display circuit 261. When type data corresponding to the first display circuit 261 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 sends a first selection signal to the first display circuit 261 via the first selection signal line 301 to cause the first display circuit 261 to receive and use the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261-265 via the display signal group 291 and branch signal group 292 is received and used only by the first display circuit 261.

The second selection signal line 302 is provided to electrically connect the display IC 266 and the second display circuit 262. When type data corresponding to the second display circuit 262 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 sends a second selection signal to the second display circuit 262 via the second selection signal line 302 to cause the second display circuit 262 to receive and use the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and branch signal group 292 is received and used only by the second display circuit 262.

The third selection signal line 303 is provided to electrically connect the display IC 266 and the third display circuit 263. When type data corresponding to the third display circuit 263 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 sends a third selection signal to the third display circuit 263 via the third selection signal line 303 so that the third display circuit 263 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and branch signal group 292 is received and used only by the third display circuit 263.

The fourth selection signal line 304 is provided to electrically connect the display IC 266 and the fourth display circuit 264. When type data corresponding to the fourth display circuit 264 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 sends a fourth selection signal to the fourth display circuit 264 via the fourth selection signal line 304 so that the fourth display circuit 264 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first to fifth display circuits 261 to 265 via the display signal group 291 and branch signal group 292 is received and used only by the fourth display circuit 264.

The fifth selection signal line 305 is provided to electrically connect the display IC 266 and the fifth display circuit 265. When type data corresponding to the fifth display circuit 265 is stored in the type data buffer 281, the selection signal output unit 282 of the display IC 266 sends a fifth selection signal to the fifth display circuit 265 via the fifth selection signal line 305 so that the fifth display circuit 265 receives and uses the display data supplied from the display data output unit 284. As a result, the display data supplied to all of the first through fifth display circuits 261-265 via the display signal group 291 and branch signal group 292 is received and used only by the fifth display circuit 265.

Figure 122 is a time chart showing how type data and display data are transmitted from the main CPU 63 to the display IC 266, and how the display data transmitted from the display IC 266 is received by the first display circuit 261 or the second display circuit 262. Figure 122(a) shows the period during which a type data signal is transmitted from the main CPU 63 to the display IC 266, Figure 122(b) shows the period during which a type clock signal is transmitted from the main CPU 63 to the display IC 266, Figure 122(c) shows the period during which a display data signal is transmitted from the main CPU 63 to the display IC 266, Figure 122(d) shows the period during which a display clock signal is transmitted from the main CPU 63 to the display IC 266, Figure 122(e) shows the period during which a first selection signal is transmitted from the display IC 266 to the first display circuit 261, Figure 122(f) shows the period during which a second selection signal is transmitted from the display IC 266 to the second display circuit 262, and Figure 122(g) shows the period during which display data is transmitted from the display IC 266 to the first to fifth display circuits 261 to 265. The same applies when display data is received in the third to fifth display circuits 263 to 265.

At timing t1, after the supply of operating power to the pachinko machine 10, including the main CPU 63, display IC 266, and first through fifth display circuits 261-265, begins, the main CPU 63 begins transmitting category data and display data to the display IC 266. Specifically, as shown in FIG. 122(b), a pulsed category clock signal is transmitted at timings t1, t2, t3, t4, and t5, and as shown in FIG. 122(a), a pulsed category data signal is transmitted in response to the transmission of the pulsed category clock signal at timing t1. As a result, information corresponding to the first display circuit 261 is stored in the category data buffer 281 of the display IC 266.

As shown in Figure 122(d), a pulsed display clock signal is transmitted at timings t1, t2, t3, t4, t5, t6, t7, and t8, and as shown in Figure 122(c), a pulsed display data signal is transmitted in response to the transmission of the pulsed display clock signal at timings t2, t3, t5, and t7. As a result, display data corresponding to the above information format is stored in the display data buffer 283 of the display IC 266.

Then, at timing t9, as shown in Figure 122(d), the transmission of the 8th bit of the display clock signal is completed, and at timing t9, as shown in Figure 122(e), the selection signal output unit 282 of the display IC 266 begins transmitting a first selection signal to the first display circuit 261 corresponding to the type data stored in the type data buffer 281, and at timing t9, as shown in Figure 122(g), the display data output unit 284 of the display IC 266 begins transmitting the display data stored in the display data buffer 283. As a result, the display data is received and used by the first display circuit 261.

After that, at timing t10, as shown in Figures 122(a) to 122(d), transmission of type data and display data from the main CPU 63 to the display IC 266 is newly initiated. In this case, at timing t10, transmission of the first selection signal from the display IC 266 to the first display circuit 261 is stopped, and transmission of display data from the display IC 266 to the first to fifth display circuits 261 to 265 is stopped, as shown in Figures 122(e) and 122(g).

Regarding the new transmission of category data and display data, as shown in Figure 122(b), a pulsed category clock signal is transmitted at timings t10, t11, t12, t13, and t14, and a pulsed category data signal is transmitted in response to the transmission of a pulsed category clock signal at timing t11, as shown in Figure 122(a). As a result, information corresponding to the second display circuit 262 is stored in the category data buffer 281 of the display IC 266.

As shown in Figure 122(d), a pulsed display clock signal is transmitted at timings t10, t11, t12, t13, t14, t15, t16, and t17, and as shown in Figure 122(c), a pulsed display data signal is transmitted in response to the transmission of the pulsed display clock signal at timings t10, t11, t12, t15, t16, and t17. As a result, display data corresponding to the above information format is stored in the display data buffer 283 of the display IC 266.

Then, at timing t18, as shown in FIG. 122(d), the transmission of the 8th bit of the display clock signal is completed, and at timing t18, as shown in FIG. 122(f), the selection signal output unit 282 of the display IC 266 begins transmitting a second selection signal to the second display circuit 262 corresponding to the type data stored in the type data buffer 281, and at timing t18, as shown in FIG. 122(g), the display data output unit 284 of the display IC 266 begins transmitting the display data stored in the display data buffer 283. As a result, the display data is received and used by the second display circuit 262.

For the first to fourth display circuits 261-264, only one piece of display data is transmitted in the second timer interrupt process (Fig. 123) to which display data is transmitted, but for the fifth display circuit 265, four pieces of display data are transmitted in the second timer interrupt process (Fig. 123) to which display data is transmitted, corresponding to the number of first to fourth alarm display devices 201-204. As already explained, the second timer interrupt process (Fig. 123) is initiated at the second interrupt period (specifically, 2 milliseconds), but each processing time is set so that even in processing rounds that transmit four pieces of display data, one processing round is completed within the second interrupt period.

With the above configuration, it is possible to transmit display data to multiple display circuits 261-265 using a single display IC 266. As already explained, each of the first through fifth display circuits 261-265 can store and hold the provided display data for a predetermined period (e.g., 16 milliseconds), but after the predetermined period has elapsed, the display data will gradually approach an all-zero state. In this case, if the reception of display data by each display circuit 261-265 exceeds the predetermined period, the illuminated display segments will temporarily approach an unlit state even if the display content has not changed in the special map display unit 37a, special map pending display unit 37b, regular map display unit 38a, regular map pending display unit 38b, and first through fourth notification display devices 201-204, which may result in the light flashing in the display segments. In contrast to this, in this embodiment, in addition to the first timer interrupt process (FIG. 117) that is started at a first interrupt period (specifically, 4 milliseconds), a second timer interrupt process (FIG. 123) that is started at a second interrupt period (specifically, 2 milliseconds) that is shorter than the first interrupt period is set, and the transmission of display data to the display IC 266 is carried out in a consolidated manner during the second timer interrupt process.

The second timer interrupt processing will be explained below with reference to the flowchart in Figure 123. Note that steps S8401 to S8413 in the second timer interrupt processing are executed using the specific control program and specific control data in the main CPU 63.

First, interrupt prohibition is set to prohibit the occurrence of the first timer interrupt processing (FIG. 117) and the second timer interrupt processing (FIG. 123) (step S8401). By prohibiting the occurrence of the first timer interrupt processing (FIG. 117), it is possible to prevent the first timer interrupt processing (FIG. 117) from interrupting and starting the second timer interrupt processing (FIG. 123) even if the first interrupt period has elapsed. Furthermore, by prohibiting the occurrence of the second timer interrupt processing (FIG. 123), it is possible to prevent the second timer interrupt processing (FIG. 123) from being started redundantly, even if the second interrupt period has elapsed during the execution of the second timer interrupt processing (FIG. 123).

Then, it is determined whether the setting update display flag in the work area 221 for specific control is set to "1" (step S8402). The setting update display flag is a flag that allows the main CPU 63 to determine whether the setting value update process (FIG. 116) is being executed by the main CPU 63. As already explained, the setting value update process (FIG. 116) is executed when the main process (FIG. 114) is executing the process at the start of the supply of operating power to the main CPU 63. However, the second timer interrupt process (FIG. 123) is started by interrupting even when the process at the start of the supply of operating power is being executed. Therefore, even when the main CPU 63 is executing the setting value update process (FIG. 116), the second timer interrupt process (FIG. 123) is started by interrupting.

When the setting update display flag is set to "1", this processing iteration of the second timer interrupt processing (Fig. 123) is initiated by interrupting a situation in which the setting value update processing (Fig. 116) is being executed by the main CPU 63. If a positive determination is made in step S8402, setting processing is executed in the fifth display data buffer 275 during setting update (step S8403). In this setting processing, display data is stored in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting values of the pachinko machine 10 are being updated and to display the current setting values of the pachinko machine 10.

When the display data stored in the fifth display data buffer 275 is transmitted to the fifth display circuit 265 via the display IC 266, the first to fourth alert display devices 201 to 204 display the information shown in the explanatory diagram of Figure 124(a). Specifically, when the first to fourth alert display devices 201 to 204 display information indicating that the setting values are being updated, at least one display segment in each of the first to fourth alert display devices 201 to 204 is illuminated. In other words, each of the first to fourth alert display devices 201 to 204 is in a display state. This allows the amusement hall manager to know that the first to fourth alert display devices 201 to 204 are not malfunctioning, even when a display indicating that the setting values are being updated is being displayed. Furthermore, even when the gaming history management results are displayed, at least one display segment will be illuminated in each of the first through fourth notification display devices 201-204, and each of the first through fourth notification display devices 201-204 will be in a display state.

Regarding the display content of each of the first to fourth alert display devices 201-204 in more detail, the first alert display device 201 has one central display segment illuminated and the remaining display segments unlit. Even when the gaming history management results are displayed on the first to fourth alert display devices 201-204, the central display segment of the first alert display device 201 may illuminate, but the display content of the first alert display device 201 when displaying the gaming history management results does not include display content in which the central display segment illuminates and the remaining display segments are unlit. This makes it possible to use display segments that can illuminate even when the gaming history management results are displayed, while displaying content on the first alert display device 201 when updating setting values that is not displayed in the gaming history management results.

In the second alert display device 202, as in the first alert display device 201, one central display segment is illuminated and the remaining display segments are unlit. Even when the gaming history management results are displayed on the first to fourth alert display devices 201 to 204, the one central display segment in the second alert display device 202 can be illuminated, but the display content of the second alert display device 202 when the gaming history management results are displayed does not include display content where one central display segment is illuminated and the remaining display segments are unlit. This makes it possible to use display segments that can be illuminated even when the gaming history management results are displayed, while displaying content on the second alert display device 202 when setting values are being updated that is not displayed in the gaming history management results.

On the third alert display device 203, some display segments are illuminated to display the letter "H," while the remaining display segments are unlit. In this case, the illuminated display segments may also be illuminated when the gaming history management results are displayed on the first through fourth alert display devices 201 through 204; however, the display content of the third alert display device 203 when the gaming history management results are displayed does not include the letter "H." This makes it possible to use display segments that can be illuminated even when the gaming history management results are displayed, while displaying content on the third alert display device 203 when the setting values are being updated that is not displayed in the gaming history management results. Furthermore, the display content of the third alert display device 203 when the setting values are being checked also does not include the letter "H." This makes it possible to notify the gaming hall manager that the setting values are being updated by displaying "H" on the third alert display device 203.

In the fourth alert display device 204, some display segments are lit and the remaining display segments are unlit so that a display corresponding to the current setting value is displayed. In the case of Figure 124(a), the current setting value is "Setting 2", so the fourth alert display device 204 displays "2", which corresponds to "Setting 2". By checking the fourth alert display device 204, the amusement hall manager can understand the current setting value. Note that the display content of the fourth alert display device 204 when the setting value is being updated can be displayed both when the gaming history management results are displayed and when the setting value is being checked.

Returning to the explanation of the second timer interrupt processing (FIG. 123), if a negative determination is made in step S8402, it is determined whether the setting confirmation display flag in the work area 221 for specific control is set to "1" (step S8404). The setting confirmation display flag is a flag used by the main CPU 63 to determine whether the setting confirmation processing (FIG. 115) is being executed by the main CPU 63. As already explained, the setting confirmation processing (FIG. 115) is executed when the processing executed at the start of the supply of operating power to the main CPU 63 is being executed in the main processing (FIG. 114) when the supply of operating power to the main CPU 63 is started. However, the second timer interrupt processing (FIG. 123) is started by interrupting even when the processing executed at the start of the supply of operating power is being executed. Therefore, the second timer interrupt processing (FIG. 123) is started by interrupting even when the setting confirmation processing (FIG. 115) is being executed by the main CPU 63.

When the setting confirmation display flag is set to "1", this processing iteration of the second timer interrupt process (Fig. 123) is initiated by interrupting a situation in which the setting confirmation process (Fig. 115) is being executed by the main CPU 63. If a positive determination is made in step S8404, setting processing is executed in the fifth display data buffer 275 during setting confirmation (step S8405). In this setting processing, display data is stored in the fifth display data buffer 275 to display an indication that the setting values of the pachinko machine 10 are being confirmed on the first to fourth notification display devices 201 to 204, and to display the current setting values of the pachinko machine 10.

When the display data stored in the fifth display data buffer 275 is sent to the fifth display circuit 265 via the display IC 266, the first to fourth alert display devices 201 to 204 display the information shown in the explanatory diagram in Figure 124(b). Specifically, when the first to fourth alert display devices 201 to 204 display information indicating that the setting values are being updated, at least one display segment in each of the first to fourth alert display devices 201 to 204 is illuminated. In other words, each of the first to fourth alert display devices 201 to 204 is in a display state. This allows the amusement hall manager to know that the first to fourth alert display devices 201 to 204 are not malfunctioning, even when a display indicating that the setting values are being checked is being displayed.

Regarding the display content of each of the first to fourth notification display devices 201-204 in more detail, the first notification display device 201 has one central display segment illuminated and the remaining display segments unlit. Even when the gaming history management results are displayed on the first to fourth notification display devices 201-204, the one central display segment on the first notification display device 201 may illuminate, but the display content of the first notification display device 201 when displaying the gaming history management results does not include display content where one central display segment illuminates and the remaining display segments are unlit. This makes it possible to use display segments that can illuminate even when the gaming history management results are displayed, while displaying content on the first notification display device 201 when checking setting values that is not displayed in the gaming history management results.

In the second alert display device 202, as in the first alert display device 201, one central display segment is illuminated and the remaining display segments are unlit. Even when the gaming history management results are displayed on the first to fourth alert display devices 201 to 204, the one central display segment in the second alert display device 202 can be illuminated, but the display content of the second alert display device 202 when the gaming history management results are displayed does not include display content where one central display segment is illuminated and the remaining display segments are unlit. This makes it possible to use display segments that can be illuminated even when the gaming history management results are displayed, while displaying content on the second alert display device 202 when checking setting values that is not displayed in the gaming history management results.

Here, the display content on the first alert display device 201 and the second alert display device 202 is the same whether the setting value is being updated or confirmed. This makes it possible to clearly notify the gaming hall manager through the display on the first alert display device 201 and the second alert display device 202 that the display subject on the first to fourth alert display devices 201 to 204 is related to the setting value, not the gaming history management results.

On the third alert display device 203, some display segments are illuminated to display the letter "k," while the remaining display segments are unlit. In this case, the illuminated display segments may also be illuminated when the gaming history management results are displayed on the first through fourth alert display devices 201 through 204; however, the display content of the third alert display device 203 when the gaming history management results are displayed does not include the display content displaying the letter "k." This makes it possible to use display segments that may be illuminated even when the gaming history management results are displayed, while the display content of the third alert display device 203 when checking setting values is not displayed in the gaming history management results. Furthermore, when setting values are being updated, "H" is displayed on the third alert display device 203, while when setting values are being checked, "k" is displayed on the third alert display device 203. This makes it possible to notify the amusement hall manager whether the setting value is being updated or checked by checking the display content of the third notification display device 203.

In the fourth alert display device 204, some display segments are illuminated and the remaining display segments are extinguished to display the current setting value. In the case of Figure 124 (b), the current setting value is "Setting 2", so the fourth alert display device 204 displays "2", which corresponds to "Setting 2". By checking the fourth alert display device 204, the amusement hall manager can understand the current setting value. Note that the display content of the fourth alert display device 204 when checking the setting value can be displayed both when the gaming history management results are displayed and when the setting value is being updated.

Returning to the explanation of the second timer interrupt process (FIG. 123), if a negative determination is made in step S8404, a setting process for the fifth display data buffer 275 under normal circumstances is executed (step S8406). In this case, information is read from the display target setting area 276 in the non-specific control work area 223, and display data for causing the first to fourth alarm display devices 201 to 204 to display parameters corresponding to the read information is stored in the fifth display data buffer 275. This display data is sent to the fifth display circuit 265 via the display IC 266, causing the first to fourth alarm display devices 201 to 204 to display the calculation results of the parameters currently being displayed, out of parameters 61 to 68.

When the processing of step S8403, step S8405, or step S8406 is executed, the signal transmission state through the type data signal line LN1 and type clock signal line LN2 is turned OFF (step S8407), and the signal transmission state through the display data signal line LN3 and display clock signal line LN4 is turned OFF (step S8408). After that, the type counter provided in the specific control work area 221 is updated (step S8409).

The type counter is a counter used by the main CPU 63 to identify the display data buffer to which the first through fifth display data buffers 271-275 are to be sent in the current second timer interrupt process. If the type counter value is "1," the display data to be sent is from the first display data buffer 271. If the type counter value is "2," the display data to be sent is from the second display data buffer 272. If the type counter value is "3," the display data to be sent is from the third display data buffer 273. If the type counter value is "4," the display data to be sent is from the fourth display data buffer 274. If the type counter value is "5," the display data to be sent is from the fifth display data buffer 275. The type counter update process increments the type counter value by 1, and if the value of the type counter after incrementing by 1 exceeds the upper limit of "5," the type counter value is reset to "1." This sequentially changes the display data to which the first through fifth display data buffers 271-275 are to be sent with each second timer interrupt process.

Then, the type data corresponding to the value of the type counter is read from the main ROM 64 (step S8410). Specifically, if the type counter value is "1", type data corresponding to the first display circuit 261 is read from the main ROM 64; if the type counter value is "2", type data corresponding to the second display circuit 262 is read from the main ROM 64; if the type counter value is "3", type data corresponding to the third display circuit 263 is read from the main ROM 64; if the type counter value is "4", type data corresponding to the fourth display circuit 264 is read from the main ROM 64; and if the type counter value is "5", type data corresponding to the fifth display circuit 265 is read from the main ROM 64.

Then, display data is read from the display data buffers 271-275 corresponding to the value of the type counter (step S8411). Specifically, if the type counter value is "1", display data is read from the first display data buffer 271; if the type counter value is "2", display data is read from the second display data buffer 272; if the type counter value is "3", display data is read from the third display data buffer 273; if the type counter value is "4", display data is read from the fourth display data buffer 274; and if the type counter value is "5", display data is read from the fifth display data buffer 275.

Then, a transmission process for various signals is executed (step S8412). In this transmission process, signals are output to the type data signal line LN1 and the type clock signal line LN2 so that the type data read in step S8410 is transmitted to the display IC 266. Also, in this transmission process, signals are output to the display data signal line LN3 and the display clock signal line LN4 so that the display data read in step S8411 is transmitted to the display IC 266.

Then, interrupt permission is set to allow the first timer interrupt process (Figure 117) and the second timer interrupt process (Figure 123) to occur (step S8413).

The present embodiment described above provides the following excellent effects:

By turning on the power to the pachinko machine 10 with the setting key insertion section 68a turned on using the setting key without pressing the reset button 68c, the supply of operating power to the main CPU 63 begins and the main processing (Figure 114) begins, but the reset button 68c is not pressed and the setting key insertion section 68a is turned on. This causes the setting confirmation processing to be executed when processing is being executed at the start of the supply of operating power, which is the state before the processing that allows game play to proceed in the main processing is executed. This makes it difficult to fraudulently check the setting values.

Assuming that the setting value is checked while the game is still in progress, for example, if the setting value is checked during the execution of a game, there is a risk that the system will transition to the open/close execution mode while the setting value is being checked. In this case, even though the open/close execution mode has started, it may not be possible to launch the game ball toward the special electric winning device 32. Furthermore, if the setting value is checked during the execution of the open/close execution mode, the open/close execution mode will proceed while the setting value is being checked, and in this case too, it may not be possible to launch the game ball toward the special electric winning device 32.

Considering that game progress is halted when a setting value is checked, if setting value checking is initiated while a game is in progress, the processing required to halt game progress midway may become complicated. For example, if setting value checking is initiated during the execution of a game round and game progress is to be halted midway, processing is required to halt the game round midway. In this case, if the display of the changing patterns on the pattern display device 41 is halted midway when setting value checking is initiated, and the display of the changing patterns on the pattern display device 41 is resumed when setting value checking is completed, this requires correspondingly more complex processing. Furthermore, for example, if setting value checking is initiated during the execution of the open/close execution mode and game progress is to be halted midway, processing is required to halt the open/close execution mode midway. Furthermore, if setting value checking is initiated during the execution of the changing pattern display on the normal pattern display unit 38a and game progress is to be halted midway, processing is required to halt the display of the changing patterns midway. Furthermore, if setting value confirmation is initiated during the opening execution state of the normal power device 34a and the progress of the game is to be stopped midway, processing is required to stop the opening execution state midway. On the other hand, a configuration is also possible in which the setting value confirmation is waited until all games are completed, but in this case, it becomes necessary to wait until a situation occurs in which none of the game rounds, open/close execution mode, changing display of the image on the normal picture display unit 38a, and the opening execution state of the normal power device 34a are being executed, which may result in a long wait time before setting value confirmation can begin.

In contrast, the setting confirmation process is executed when the supply of operating power to the main CPU 63 begins, during the main processing, which is executed before the processing that enables game progress is executed, during the processing that occurs when the supply of operating power begins. Therefore, the setting values are confirmed when game progress has already been stopped. This makes it possible to avoid checking the setting values while game progress is in progress, and there is no need to stop game progress midway to check the setting values, or wait until game progress is stopped to check the setting values. This makes it possible to check the setting values appropriately.

When the power to the pachinko machine 10 is turned ON while the reset button 68c is pressed, the supply of operating power to the main CPU 63 begins, and the main processing (Figure 114) begins. The reset button 68c is then pressed, and the RAM clear process (step S7915) is executed regardless of whether the setting key insertion section 68a is turned ON. This means that the operation of turning ON the power to the pachinko machine 10 while pressing the reset button 68c is uniquely linked to the execution of the RAM clear process (step S7915), making it possible to make the operation to trigger the RAM clear process (step S7915) easy to understand for the amusement hall manager.

Even if the RAM clear process (step S7915) is executed, the setting value counter in the specific control work area 221 is not cleared to "0" and the information in the setting value counter is not changed. This makes it possible to prevent the setting value from being changed even if the RAM clear process (step S7915) is executed.

Not only is the power to the pachinko machine 10 turned on while pressing the reset button 68c, but also the setting value update process (step S7918) is executed based on the power being turned on while the setting key insertion section 68a is turned on with the setting key. As already explained, the setting confirmation process (step S7914) is executed based on the power being turned on while the setting key insertion section 68a is turned on with the setting key, without pressing the reset button 68c. This makes it possible to standardize the ON operation of the setting key insertion section 68a as the operation for executing processing related to setting values. This makes it possible to make the operation content for triggering processing related to setting values easy to understand for the amusement hall manager.

When the power to the pachinko machine 10 is turned on while the setting key insertion section 68a is turned on with the setting key, and the setting confirmation process is executed without pressing the reset button 68c, the setting value update process is executed if the reset button 68c is pressed. This makes it possible to differentiate between the setting confirmation process and the setting value update process depending on whether the reset button 68c is pressed. This makes it possible to make the operation details for executing the desired process, either the setting confirmation process or the setting value update process, easier for the amusement hall manager to understand. Furthermore, by having more operation details for executing the setting value update process than the setting confirmation process, it becomes particularly difficult to perform fraudulent acts in the setting value update process.

The process of monitoring whether the set value is abnormal is executed by the first timer interrupt process (Fig. 117), which is periodically started. This makes it possible to monitor whether the set value is abnormal even while a game is in progress. This makes it possible to prevent gameplay from continuing even when the set value is abnormal.

Monitoring whether the set value is abnormal is performed each time a monitoring trigger occurs. More specifically, it is performed each time the first timer interrupt process (Figure 117) is started. This makes it possible to increase the frequency with which the set value is monitored for abnormalities.

The main processing (FIG. 114) does not include a process for monitoring whether the set values are normal. If a process for monitoring whether the set values are normal were included in the process for starting the supply of operating power in the main processing (FIG. 114), not only would it be necessary to monitor the power outage flag and checksum but also to monitor whether the set values are normal when the supply of operating power starts, which would increase the monitoring load. Furthermore, if an abnormality in the set values was identified when the supply of operating power starts, a RAM clear process (step S7915) and a set value update process (step S7918) would be executed, which would complicate the processing configuration. In contrast, the main processing (FIG. 114) does not include a process for monitoring whether the set values are normal, which makes it possible to optimize the processing configuration for the process for starting the supply of operating power. Furthermore, even if a process for monitoring whether the set values are normal is not included in the process for starting the supply of operating power, the first timer interrupt process (FIG. 117) is configured to execute a setting monitoring process (step S8220), making it possible to address an abnormality in the set values.

The display IC 266 configures the display settings for the first through fifth display circuits 261-265 according to the display data transmitted from the main CPU 63, and controls the display of the special map display unit 37a, special map reserve display unit 37b, regular map display unit 38a, regular map reserve display unit 38b, and the first through fourth alert display devices 201-204 so that the display content corresponds to the display data. This reduces the processing load on the main CPU 63. In this case, in a configuration with multiple display units, such as the special map display unit 37a, special map reserve display unit 37b, regular map display unit 38a, regular map reserve display unit 38b, and the first through fourth alert display devices 201-204, a single display IC 266 is not provided in a one-to-one correspondence with the multiple display units, but rather multiple display units share the same display IC 266. This makes it possible to increase the number of display units subject to display control while minimizing the increase in the number of display ICs 266. Furthermore, the interval at which display data is transmitted from the main CPU 63 to the display IC 266 is set so that the display settings are made by the display IC 266 to the display circuits 261-265 corresponding to each display unit before the display corresponding to the display data can no longer be maintained on each display unit. This makes it possible to properly display the display corresponding to the display data on each display unit, even in a configuration in which one display IC 266 is shared by multiple display units.

When the main CPU 63 sends display data to the display IC 266, it sends type data to the display IC 266 that identifies the type of display circuit 261-265 to which the display data is to be set. As a result, when display data is sent from the main CPU 63, the display IC 266 simply sets the display data for the display circuit 261-265 that corresponds to the type data sent from the main CPU 63. Therefore, even in a configuration in which one display IC 266 is shared by multiple display units, the configuration of the display IC 266 can be simplified.

When one update cycle is defined as each of multiple display units being the target of display data setting in a predetermined order, the main CPU 63 transmits display data so that the update cycle is repeated. This allows the main CPU 63 to simply change the display unit to which display data is sent in accordance with the predetermined order, thereby simplifying the processing configuration of the main CPU 63.

When a display unit becomes a transmission target, the main CPU 63 transmits the display data for that display unit, even if the content of the display data for that display unit is the same as the content of the display data transmitted the previous time that that display unit was the transmission target. This makes it possible to continue displaying the same data on a specific display unit, even in a configuration in which one display IC 266 is shared by multiple display units.

The main CPU 63 executes processing to send display data to the display IC 266 in the second timer interrupt processing (Figure 123), which is started by interrupting other processing when the second interrupt period is reached. This makes it possible to set the period in which display data is set for each display unit to a predetermined period. Therefore, even in a configuration in which one display IC 266 is shared by multiple display units, it is possible to have the display IC 266 set display data for each display unit before it becomes impossible to maintain the display corresponding to the display data on each display unit.

The process for transmitting display data to the first to fifth display circuits 261 to 265, which are the targets of display settings by the display IC 266, is consolidated into the second timer interrupt process (Figure 123). This makes it possible to set the display data to the first to fifth display circuits 261 to 265 at the same cycle.

When the first interrupt period arrives, the main CPU 63 interrupts other processing and executes the first timer interrupt process (Figure 117). In this case, the second interrupt period of the second timer interrupt process (Figure 123) is set to a period shorter than the first interrupt period of the first timer interrupt process (Figure 117). This makes it possible to transmit display data at a shorter period than in a configuration in which the process of transmitting display data to the display IC 266 is executed in the first timer interrupt process (Figure 117).

In addition, the process of sending display data to the display IC 266 is set in the second timer interrupt process (Fig. 123), which has a shorter interrupt period than the first timer interrupt process (Fig. 117), in which the process for progressing the game is set. This makes it possible to achieve the excellent effects already described while ensuring that the first timer interrupt process (Fig. 117) is activated at a period appropriate for executing the process for progressing the game.

The second timer interrupt process (Figure 123) is started even when the first timer interrupt process (Figure 117) is being executed. This allows the display data transmission period to be set to a predetermined period.

When the second timer interrupt process (Fig. 123) starts, the first timer interrupt process (Fig. 117) is prohibited from interrupting, and when the second timer interrupt process (Fig. 123) ends, the first timer interrupt process (Fig. 117) is permitted to interrupt and be executed. This makes it possible to prevent the first timer interrupt process (Fig. 117) from interrupting and being executed while the second timer interrupt process (Fig. 123) is being executed. This makes it possible to give priority to the process for transmitting display data.

The second timer interrupt process (Figure 123) is started by interrupting the main process (Figure 114) even when the process at the start of the supply of operating power (steps S7901 to S7918) is being executed. This makes it possible to control the display of multiple display units even when the process at the start of the supply of operating power is being executed. Furthermore, because the second timer interrupt process (Figure 123) is started by interrupting the process at the start of the supply of operating power, it is possible to control the display of multiple display units when the process at the start of the supply of operating power is being executed without complicating the processing configuration of the process at the start of the supply of operating power.

Even when the setting value update process (step S7918) is being executed in the main process (Figure 114), the second timer interrupt process (Figure 123) interrupts and is started, and in this situation, the second timer interrupt process (Figure 123) transmits display data for displaying the current setting value on the fourth alert display device 204. This makes it possible to display the current setting value on the fourth alert display device 204 when the setting value update process (step S7918) is being executed without complicating the processing configuration of the main process (Figure 114).

Even after the processing at the start of the supply of operating power has been executed in the main processing (Fig. 114), the second timer interrupt processing (Fig. 123) is initiated each time the second interrupt period elapses. By utilizing the second timer interrupt processing (Fig. 123), it is possible to control the display of multiple display units both when the processing at the start of the supply of operating power is being executed and after the processing at the start of the supply of operating power has finished.

As in the first embodiment, an update button 68b may be provided, and in the setting value update process (Fig. 116), the setting value may be updated by one step each time the update button 68b is pressed, rather than each time the reset button 68c is pressed. Furthermore, when a setting key is inserted into the setting key insertion section 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" may be set as the rotation position, and the setting value corresponding to the rotation position of the setting key insertion section 68a may be set. Furthermore, the setting key insertion section 68a may be configured to be able to be rotated further than the ON position, and each time the setting key insertion section 68a is rotated beyond the ON position, the setting value being updated may be updated to the next setting value in the sequence.

Furthermore, in the setting value update process (Figure 116), the currently selected setting value may be confirmed by turning off the setting key insertion section 68a, and the setting value update process may be terminated by further pressing the reset button 68c. Furthermore, in a configuration where the update button 68b is provided, the currently selected setting value may be confirmed by turning off the setting key insertion section 68a in the setting value update process (Figure 116), and the setting value update process may be terminated by further pressing the update button 68b.

Furthermore, the condition for executing the setting value update process (Figure 116) may not be set so that the gaming machine main body 12 is in an open state, or the condition for the front door frame 14 to be in an open state, or neither the condition for the gaming machine main body 12 to be in an open state nor the condition for the front door frame 14 to be in an open state may be set.

Furthermore, the condition for executing the setting confirmation process (Figure 115) may not be set so that the gaming machine main body 12 is in an open state, or the condition for the front door frame 14 to be in an open state, or neither the condition for the gaming machine main body 12 to be in an open state nor the condition for the front door frame 14 to be in an open state may be set.

Also, if the main processing (FIG. 114), which is executed when the supply of operating power to the main CPU 63 is started, determines that the power outage flag is not set to "1" or that the checksum is abnormal, a RAM clear processing (step S7915) may be executed. In this case, after the RAM clear processing (step S7915) is executed, a setting value update processing (step S7918) may be executed, or a notification may be issued indicating that the setting value update processing (step S7918) should be executed and the game progress may be stopped, or a processing to control the game progress may be started.

In addition, instead of being configured in the main processing (FIG. 114) so that the setting confirmation process (step S7914) is executed after the process of determining whether the power outage flag is set to "1" and the process of comparing checksums, it may be configured so that it is executed before these processes. In this case, it is possible to give priority to the process of confirming the setting value.

Furthermore, the setting monitoring process (step S8220) is not limited to being executed each time the first timer interrupt process (FIG. 117) is activated. For example, the setting monitoring process (step S8220) may be executed each time the first timer interrupt process (FIG. 117) is executed a predetermined number of times (for example, 10,000 times). In this case, it is possible to periodically monitor whether the setting values are normal, while reducing the frequency with which such monitoring is executed.

Alternatively, the setting monitoring process (step S8220) may be configured to be executed during the remaining processing (steps S7921 to S7924) in the main processing (Figure 114). In this case, it is possible to monitor whether the setting values are normal by utilizing the free time when the first timer interrupt processing (Figure 117) and the second timer interrupt processing (Figure 123) are not being executed.

Also, the setting monitoring process (step S8220) may be executed when a new round of play begins. More specifically, the setting monitoring process (step S8220) may be executed before the hit/miss determination process is executed when a new round of play begins. This makes it possible to prevent the hit/miss determination process from being executed when the setting value is abnormal.

Furthermore, if the setting monitoring process (step S8220) identifies an abnormal setting value, the process may proceed to the setting value update process (step S7918).

Also, if the setting monitoring process (step S8220) identifies an abnormal setting value, the main process (FIG. 114) may be started with the setting abnormality flag set to "1" in the specific control work area 221, or the game may be stopped with the setting abnormality flag set to "1," and the power may need to be turned OFF and ON to release the stopped game. In this case, even if no operation is performed in the main process (FIG. 114) to cause the setting value update process to be executed, by forcibly executing the setting value update process when the setting abnormality flag is set to "1," it is possible to forcibly set a new setting value using the setting value update process set in the main process (FIG. 114).

In addition, the reserved information acquired when a gaming ball enters the first operating port 33 and the reserved information acquired when a gaming ball enters the second operating port 34 may be stored separately, and the first special symbol display unit and the second special symbol display unit may be provided as the special symbol display unit 37a corresponding to the reserved information. In this case, the display of the changing patterns in the first special symbol display unit and the display of the changing patterns in the second special symbol display unit may be executed in overlapping fashion, and when a predetermined gaming state is reached, the display of the changing patterns in either special symbol display unit may be configured to continue for an extremely long period of time. In this configuration, if the setting value is to be confirmed until a situation in which no gaming is taking place becomes a long wait time. In contrast, by executing the setting confirmation process (step S7914) when the supply of operating power to the main CPU 63 begins, it is possible to confirm the setting value without incurring the above-mentioned wait time.

Furthermore, in low-frequency support mode, the duration of the variable image display on the normal image display unit 38a may be extremely long. In this configuration, if the setting value is to be checked until no game is being played, the waiting time will be long. In contrast, by executing the setting confirmation process (step S7914) when the supply of operating power to the main CPU 63 begins, it is possible to check the setting value without incurring the above-mentioned waiting time.

Furthermore, when the setting confirmation process (Figure 115) is executed, the display contents of the first to fourth alert display devices 201-204 are not limited to those in the above embodiment. For example, instead of displaying the letter "k" on the third alert display device 203, only the central display segment may be illuminated, as with the first alert display device 201 and the second alert display device 202. Furthermore, the first to third alert display devices 201-203 may be turned off, and the fourth alert display device 204 may display a value corresponding to the current setting value.

Furthermore, when the setting value update process (Figure 116) is executed, the display contents of the first to fourth alert display devices 201 to 204 are not limited to those in the above embodiment. For example, instead of displaying the letter "H" on the third alert display device 203, only the central display segment may be illuminated, as with the first alert display device 201 and the second alert display device 202. Furthermore, the first to third alert display devices 201 to 203 may be turned off, and the fourth alert display device 204 may display a value corresponding to the current setting value.

In addition, instead of being configured to simultaneously transmit type data and display data to the display IC 266, the main CPU 63 may be configured to start transmitting display data after starting transmission of type data. In this case, the transmission of display data may be started while transmission of type data is in progress, or after transmission of type data is complete. Also, the transmission of type data may be started after transmission of display data has started. In this case, the transmission of type data may be started while transmission of display data is in progress, or after transmission of display data is complete.

Furthermore, the display IC 266 is not limited to a configuration in which only one display IC is provided common to the first through fifth display circuits 261-265, but may be provided in a one-to-one correspondence with each of the first through fifth display circuits 261-265. In this configuration, if the display data storage period in each display IC provided in a one-to-one correspondence with the first through fifth display circuits 261-265 is short, unintended flashing may occur on each display unit depending on the period of time that display data is provided to each display IC. In contrast, by consolidating the processing for transmitting display data into the second timer interrupt processing (Figure 123), which has a relatively short interrupt period, as in the above embodiment, it is possible to shorten the period of time that display data is provided to each display IC, and prevent unintended flashing on each display unit.

In addition, instead of a configuration in which the winning random number counter C1 is provided in the main RAM 65, a configuration in which a random number circuit is provided to update the random numbers obtained in the win/loss determination process may be provided. In this case, the internal function register setting process in the main process (Figure 114) will perform settings to associate the random numbers of the random number circuit with the random numbers obtained in the win/loss determination process.

In addition, in the first timer interrupt processing (FIG. 117), timer interrupt processing is prohibited and permitted before and after each of steps S8201 to S8221, but this may be changed. For example, timer interrupt processing may be prohibited and permitted before and after some of the processing in the first timer interrupt processing (FIG. 117), while timer interrupt processing may not be prohibited or permitted before and after other of the processing in the first timer interrupt processing (FIG. 117). Furthermore, timer interrupt processing may be prohibited and permitted between multiple processes included in the first timer interrupt processing (FIG. 117).

Also, the first timer interrupt processing (Figure 117) may be configured so that the setting to prohibit the interrupt of the second timer interrupt processing (Figure 123) is not made. In this case, the second timer interrupt processing (Figure 123) is executed with priority over the first timer interrupt processing (Figure 117), making it possible to prioritize display control of multiple display units. Also, in this configuration, the first timer interrupt processing (Figure 117) may be configured so that the interrupt of the first timer interrupt processing (Figure 117) is prohibited to prevent the first timer interrupt processing (Figure 117) from being started multiple times, but the interrupt of the second timer interrupt processing (Figure 123) may not be prohibited.

In addition, instead of a configuration in which execution of the second timer interrupt processing (FIG. 123) takes priority over execution of the first timer interrupt processing (FIG. 117) when interrupt triggers for both the first timer interrupt processing (FIG. 117) and the second timer interrupt processing (FIG. 123) occur, a configuration in which execution of the first timer interrupt processing (FIG. 117) takes priority over execution of the second timer interrupt processing (FIG. 123) may also be adopted, or a configuration in which the timer interrupt processing whose interrupt trigger occurred earlier is started first.

In addition, instead of a configuration in which the execution of the first timer interrupt process (FIG. 117) is prohibited when the second timer interrupt process (FIG. 123) is being executed, a configuration in which the first timer interrupt process (FIG. 117) interrupts and starts even when the second timer interrupt process (FIG. 123) is being executed may be used. This makes it possible to prioritize the execution of processes for progressing the game over the display control of multiple display units.

Alternatively, the second timer interrupt processing (Figure 123) may not be set, and various processes of the second timer interrupt processing (Figure 123) may be executed separately in the main processing (Figure 114) and the first timer interrupt processing (Figure 117). For example, the setting confirmation processing (step S7914) in the main processing (Figure 114) may be configured to include processing for causing the first to fourth alarm display devices 201 to 204 to display a message indicating that the setting is being confirmed and a message corresponding to the current setting value. Alternatively, the setting value update processing (step S7918) in the main processing (Figure 114) may be configured to include processing for causing the first to fourth alarm display devices 201 to 204 to display a message indicating that the setting is being updated and a message corresponding to the current setting value. Additionally, the first timer interrupt process (Figure 117) may be configured to include processing for controlling the display of the special map display unit 37a, special map reserve display unit 37b, regular map display unit 38a, regular map reserve display unit 38b, and the first to fourth notification display devices 201 to 204.

Furthermore, the second timer interrupt processing (Figure 123) is not limited to a configuration in which only processing for display control of multiple display units is executed, and may be configured to execute processing other than the processing for display control of multiple display units in addition to or instead of the processing for display control of multiple display units. For example, a configuration may be adopted in which part of the processing for progressing the game is executed in the first timer interrupt processing (Figure 117), and the rest is executed in the second timer interrupt processing (Figure 123). In this case, it is preferable to execute processing for which a relatively short execution cycle is preferable in the second timer interrupt processing (Figure 123), which has a relatively short interrupt cycle, and execute processing for which a relatively long execution cycle does not cause problems in the first timer interrupt processing (Figure 117), which has a relatively long interrupt cycle. Furthermore, among the processes of steps S8202 to S8221 in the first timer interrupt process (FIG. 117) of the above embodiment, the power outage information storage process (step S8202) may be executed in the second timer interrupt process (FIG. 123), and the other processes may be executed in the first timer interrupt process (FIG. 117). In this case, power outage monitoring can be repeatedly executed at relatively short intervals. In addition to or instead of this configuration, the fraud detection process (step S8206) may be executed in the second timer interrupt process (FIG. 123), and the other processes may be executed in the first timer interrupt process (FIG. 117). In this case, fraud monitoring can be repeatedly executed at relatively short intervals.

Furthermore, the number of display circuits 261-265 for which the display IC 266 performs display data display settings is not limited to five, and may be two, three, four, six or more. Furthermore, the configuration is not limited to the first to fourth alarm display devices 201-204 being associated with the fifth display circuit 265, and a configuration may be adopted in which display circuits are provided in one-to-one correspondence with the first to fourth alarm display devices 201-204.

<Thirty-fourth embodiment>
In this embodiment, the processing configuration of the setting value update process executed by the main CPU 63 differs from that of the 33rd embodiment. The configuration that differs from the 33rd embodiment will be described below. Note that a description of the same configuration as the 33rd embodiment will basically be omitted. In this embodiment, an update button 68b is provided on the main control board 61, as in the first embodiment.

Figure 125 is a flowchart showing the setting value update process in this embodiment, which is executed by the main CPU 63. Note that steps S8501 to S8508 in the setting value update process are executed using the specific control program and specific control data in the main CPU 63.

First, the setting update display flag provided in the work area 221 for specific control is set to "1" (step S8501). Then, it is determined whether the value of the setting value counter provided in the work area 221 for specific control is greater than or equal to 1, corresponding to "Setting 1," and less than or equal to 6, corresponding to "Setting 6" (step S8502). If the value of the setting value counter is "0" or greater than or equal to 7, a negative determination is made in step S8502, and the setting value counter is set to "1" (step S8503). As a result, the setting value of the pachinko machine 10 becomes "Setting 1."

If a positive judgment is made in step S8502 or if the processing of step S8503 is executed, it is determined whether the reset button 68c has been pressed (step S8504). If the reset button 68c has not been pressed (step S8504: NO), and provided that the update button 68b has been pressed (step S8505: YES), the value of the setting value counter in the specific control work area 221 is incremented by 1 (step S8506). This updates the setting value by one level each time the update button 68b is pressed. If the update button 68b has not been pressed (step S8505: NO) or the setting value counter has been incremented by 1, the processing returns to step S8502. However, if it is determined in step S8502 that the value of the setting value counter is 7 or greater, the setting value counter is set to "1" in step S8503. As a result, if the update button 68b is pressed once while in "Setting 6", the setting will return to "Setting 1".

If the reset button 68c has been pressed (step S8504: YES), the current setting value is confirmed and the process proceeds to step S8507. In step S8507, it is determined whether the setting key insertion unit 68a has been turned off using the setting key. In this case, it may be configured to determine whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or whether the setting key insertion unit 68a is in an OFF state. If the setting key insertion unit 68a has not been turned off (step S8507: NO), the process of step S8507 is executed again.

If the setting key insertion section 68a is turned OFF (step S8507: YES), the setting update display flag in the specific control work area 221 is cleared to "0" (step S8508).

With the above configuration, the setting value is updated by pressing the update button 68b, the setting value is confirmed by pressing the reset button 68c, and the setting value update process is terminated by turning off the setting key insertion unit 68a. In other words, in order to terminate the setting value update process after updating the setting value, it is necessary not only to turn off the setting key insertion unit 68a but also to press the reset button 68c. This makes it more difficult to fraudulently update the setting value and then play using that setting value.

<Thirty-fifth embodiment>
In this embodiment, the processing configuration related to the display control of the first to fourth alarm display devices 201 to 204 executed by the main CPU 63 differs from that of the 33rd embodiment. The configuration that differs from the 33rd embodiment will be described below. Note that the description of the same configuration as the 33rd embodiment will basically be omitted.

Figure 126 is an explanatory diagram illustrating the electrical configuration of the calculation result storage area 234 provided in the work area 223 for non-specific control.

The calculation result memory area 234 stores information about the base value calculated by the main CPU 63. The base value is the ratio of the total number of game balls paid out to the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) in a situation that is neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode.

Regarding the calculation of the base value in detail, in this embodiment, the work area 223 for non-specific control is provided with a normal counter area 231, but is not provided with an open/close execution mode counter area 232 or a high frequency support mode counter area 233. As in the fifteenth embodiment, the normal counter area 231 is provided with a normal general winning counter 231a, a normal special line winning counter 231b, a normal first operation counter 231c, a normal second operation counter 231d, and a normal out counter 231e. In a situation that is neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode, when one game ball enters the general winning port 31, the value of the normal general winning counter 231a is incremented by 1, when one game ball enters the special electric winning device 32, the value of the normal special electric winning counter 231b is incremented by 1, when one game ball enters the first operating port 33, the value of the normal first operating counter 231c is incremented by 1, when one game ball enters the second operating port 34, the value of the normal second operating counter 231d is incremented by 1, and when one game ball enters the outlet port 24a, the value of the normal out counter 231e is incremented by 1. Then, when the values of the various counters 231a to 231e in the normal counter area 231 in a situation that is neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode are K91 to K95, the base values are as follows.
Base value: The ratio of the total number of game balls paid out (K91 x "number of prize balls for winning at the general winning port 31" + K92 x "number of prize balls for winning at the special electric winning device 32" + K93 x "number of prize balls for winning at the first operating port 33" + K94 x "number of prize balls for winning at the second operating port 34") to the total number of game balls discharged from the game area PA (K91 + K92 + K93 + K94 + K95).

The base value is calculated each time the result calculation process (Fig. 130) described below is executed in the management process (step S8920) of the first timer interrupt process (Fig. 133) described below. The values of the various counters 231a to 231e in the normal counter area 231 are cleared to "0" when the total number of game balls discharged from the play area PA (i.e., the total number of game balls supplied to the play area PA) reaches the management start reference number when the management start flag provided in the non-specific control work area 223 is not set to "1" and the mode is neither the open/close execution mode based on a jackpot result nor the high frequency support mode. Also, when the management start flag is set to "1" and the mode is neither the open/close execution mode based on a jackpot result nor the high frequency support mode, the values of the various counters 231a to 231e in the normal counter area 231 are cleared to "0" when the total number of game balls discharged from the play area PA (i.e., the total number of game balls supplied to the play area PA) reaches the shift reference number.

As in the fifteenth embodiment, the management start reference number is set to 300, which is less than the shift reference number. When a pachinko machine 10 is shipped, its operation may be checked before shipment. During this check, game balls are placed in each ball entry section and the subsequent operation is checked. The base value under such circumstances may be different from that under normal game play. Therefore, when the management start flag is not set to "1" and the machine is not in either the jackpot-based open/close execution mode or the high-frequency support mode, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the management start reference number, which is less than the shift reference number. By temporarily clearing the various counters 231a-231e in the normal counter area 231 to "0," this reduces the impact of the above-mentioned operation check on the base value under normal game play after the pachinko machine 10 is shipped. The management start reference number is not limited to 300, but can be any number greater than 300, and may be set to a number less than 300 or more than 300.

The shift reference number is set to 60,000 balls. Since a pachinko machine 10 can fire a maximum of 100 game balls per minute, 60,000 balls is the maximum number of balls fired in a 10-hour period. In this case, the typical business hours of an amusement hall are approximately 13 hours, during which time game play occurs when neither the open/close execution mode due to a jackpot result nor the high-frequency support mode is in effect. Therefore, the shift reference number is set based on the estimated maximum number of game balls fired in a single business day. By clearing the various counters 231a-231e in the normal counter area 231 to "0" each time the shift reference number is reached, it is possible to calculate a base value within the range of the shift reference number. The shift reference number is not limited to 60,000 balls and can be any number greater than or equal to 60,000 balls.

The calculation result storage area 234 has three storage areas for storing the base value information: a current status area 311, a first history area 312, a second history area 313, and a third history area 314. These various areas 311 to 314 all have the same storage capacity, specifically, a capacity of 1 byte so that base value information can be stored.

The current status area 311 stores the base value calculated in the most recent result calculation process (Figure 130). In other words, the current status area 311 stores the most recent base value.

The first history area 312 stores the final base value for the previous calculation period. In this case, if the previous calculation period occurred after the management start flag was set to "1," the first history area 312 stores the base value at the time when the total number of game balls discharged from the game area PA in a situation where the game was not in either the open/close execution mode due to a jackpot result or the high-frequency support mode during the previous calculation period (i.e., the total number of game balls supplied to the game area PA) reached the shift reference number. Furthermore, if the management start flag was set to "1" after the previous calculation period had elapsed, the first history area 312 stores the base value at the time when the total number of game balls discharged from the game area PA in a situation where the game was not in either the open/close execution mode due to a jackpot result or the high-frequency support mode during the previous calculation period (i.e., the total number of game balls supplied to the game area PA) reached the management start reference number.

The second history area 313 stores the final base value for the calculation period two periods ago. In this case, if the calculation period two periods ago was after the management start flag was set to "1," the second history area 313 stores the base value at the time when the total number of game balls discharged from the play area PA in a situation where the game was neither in the open/close execution mode due to a jackpot result nor in the high-frequency support mode during the calculation period two periods ago (i.e., the total number of game balls supplied to the play area PA) reached the shift reference number. Furthermore, if the management start flag was set to "1" after the calculation period two periods ago, the second history area 313 stores the base value at the time when the total number of game balls discharged from the play area PA in a situation where the game was neither in the open/close execution mode due to a jackpot result nor in the high-frequency support mode during the calculation period two periods ago (i.e., the total number of game balls supplied to the play area PA) reached the management start reference number.

The third history area 314 stores the final base value for the calculation period three times prior. In this case, if the calculation period three times prior is after the management start flag was set to "1," the third history area 314 stores the base value at the time when the total number of game balls discharged from the play area PA in a situation where the game was neither in the open/close execution mode due to a jackpot result nor in the high-frequency support mode during the calculation period three times prior (i.e., the total number of game balls supplied to the play area PA) reached the shift reference number. Furthermore, if the management start flag was set to "1" after the calculation period three times prior has elapsed, the third history area 314 stores the base value at the time when the total number of game balls discharged from the play area PA in a situation where the game was neither in the open/close execution mode due to a jackpot result nor in the high-frequency support mode during the calculation period three times prior (i.e., the total number of game balls supplied to the play area PA) reached the management start reference number.

The base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 are sequentially reported by the first to fourth notification display devices 201 to 204. Specifically, each time the display duration period (specifically, 5 seconds) elapses, the base value to be reported is switched in a predetermined order: current status area 311 → first history area 312 → second history area 313 → third history area 314, and this switching of the base values to be reported in this predetermined order is repeated.

Figures 127(a) to 127(d) are explanatory diagrams illustrating the display contents of the first to fourth alert display devices 201-204 when the base values stored in the various areas 311-314 are reported when the management start flag is set to "1." Figure 127(a) shows an example of the display contents of the first to fourth alert display devices 201-204 when the base value stored in the current status area 311 is reported, Figure 127(b) shows an example of the display contents of the first to fourth alert display devices 201-204 when the base value stored in the first history area 312 is reported, Figure 127(c) shows an example of the display contents of the first to fourth alert display devices 201-204 when the base value stored in the second history area 313 is reported, and Figure 127(d) shows an example of the display contents of the first to fourth alert display devices 201-204 when the base value stored in the third history area 314 is reported.

As shown in Figures 127(a) to 127(d), each of the first to fourth alarm display devices 201-204 has eight display segments 321-324. Of the eight display segments 321-324, seven display segments 321-324 are rod-shaped light-emitting areas of the same shape and size, and are arranged to form the shape of an "8." On the other hand, one display segment 321-324 is a circular light-emitting area, and is located to the lower right of the seven display segments 321-324 arranged in the shape of an "8." When reporting any of the base values for the various areas 311-314, at least one display segment 321-324 will be illuminated in each of the first to fourth alarm display devices 201-204.

The first alert display device 201 displays a message indicating that the first through fourth alert display devices 201-204 are reporting base values. Specifically, the letter "b" is displayed on the first alert display device 201 regardless of which base value is being reported for each of the various areas 311-314. If the first through fourth alert display devices 201-204 are reporting information other than base values, the letter "b" is not displayed on the first alert display device 201. As a result, by confirming that the letter "b" is being displayed on the first alert display device 201, the amusement hall manager can determine that base values are being reported on the first through fourth alert display devices 201-204.

The second alert display device 202 displays which of the various areas 311 to 314 is being reported. Specifically, when the base value in the current status area 311 is being reported, the second alert display device 202 displays the letter "L." as shown in Figure 127(a). When the base value in the first history area 312 is being reported, the second alert display device 202 displays the letter "1." as shown in Figure 127(b). When the base value in the second history area 313 is being reported, the second alert display device 202 displays the letter "2." as shown in Figure 127(c). When the base value in the third history area 314 is being reported, the second alert display device 202 displays the letter "3." as shown in Figure 127(d). This allows the amusement hall manager to check the text displayed on the second notification display device 202 and determine which calculation period the base values being reported on the first through fourth notification display devices 201-204 refer to.

On the second alarm display device 202, the circular display segments 321-324 will illuminate regardless of which base value is being reported in the various areas 311-314. As described below, on the third alarm display device 203 and the fourth alarm display device 204, a number from "0" to "9" will be displayed to indicate the base value. In this case, if the second alarm display device 202 displays a number from "1" to "3," three numbers will be lined up on the second to fourth alarm display devices 202-204, making it difficult to grasp the base value. In contrast, by illuminating the circular display segments 321-324 located at the bottom right of the second alert display device 202, even if the second alert display device 202 displays any of the numbers "1" to "3," it becomes possible to distinguish between the number displayed on the second alert display device 202 and the numbers displayed on the third alert display device 203 and fourth alert display device 204.

The third alert display device 203 and the fourth alert display device 204 display the numeric value of the base value to be notified. The base value is calculated as a decimal to two decimal places, with the digit to one decimal place of the base value being displayed on the third alert display device 203 and the digit to two decimal places of the base value being displayed on the fourth alert display device 204. Here, if the base value is "1.00", the digit "0" is displayed on both the third alert display device 203 and the fourth alert display device 204. On the other hand, if a base value has not yet been stored in the areas 311 to 314 to be notified, the character "- " is displayed on both the third alert display device 203 and the fourth alert display device 204, as shown in the explanatory diagram of Figure 128(a). As a result, even when the third and fourth notification display devices 203 and 204 display a base value calculated as a decimal point to two decimal places, it is possible to distinguish between the display content when the base value is "1.00" and when a base value has not yet been stored in the area 311-314 that is the target of notification.

The display content of the combination of the third and fourth alarm display devices 203 and 204 will be the same when the base value is "1.00" and when the base value is "0.00". However, to distinguish between the two, one of the former and latter cases may maintain an illuminated "00" display, while the other may flash "00".

Next, referring to the time chart in Figure 129, we will explain how the base values of the various areas 311-314 are reported by the first to fourth alarm display devices 201-204 when the management start flag is set to "1". Figure 129(a) shows the period during which the base value stored in the current status area 311 is reported by the first to fourth alarm display devices 201-204, Figure 129(b) shows the period during which the base value stored in the first history area 312 is reported by the first to fourth alarm display devices 201-204, Figure 129(c) shows the period during which the base value stored in the second history area 313 is reported by the first to fourth alarm display devices 201-204, and Figure 129(d) shows the period during which the base value stored in the third history area 313 is reported by the first to fourth alarm display devices 201-204. This shows the period during which the base value stored in rear 314 is reported by the first to fourth notification display devices 201 to 204, and Figure 129 (e) shows the period from when a new base value calculation period begins until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6,000) in a situation that is not in the opening/closing execution mode due to a jackpot result or the high-frequency support mode.

At timing t1, as shown in FIG. 129(a), the first to fourth alert display devices 201-204 begin to notify the base value stored in the current status area 311. During this notification, as shown in FIG. 127(a), the first alert display device 201 displays a message indicating that the base value is the target of notification, the second alert display device 202 displays a message indicating that the base value stored in the current status area 311 is the target of notification, and the third alert display device 203 and fourth alert display device 204 display a message corresponding to the base value stored in the current status area 311.

Here, as shown in FIG. 129(e), an initial calculation display is performed from timing t1 to timing t2. Specifically, from the start of a new base value calculation period until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6,000) when neither the open/close execution mode due to a jackpot result nor the high-frequency support mode is active, the first and second notification display devices 201 and 202 flash the characters to be displayed as an initial calculation display, rather than continuing to light them. Immediately after the calculation period begins, there is little game history information to calculate the base value, so the actual measured value of the base value may be significantly outside the theoretical range of base values. In contrast, by displaying the initial calculation display immediately after the calculation period begins, it is possible for the amusement hall manager to recognize that the calculation period has just begun.

In addition, in the initial calculation display, the third alert display device 203 and the fourth alert display device 204, which display numbers corresponding to the base value, continue to light the numbers, while the first alert display device 201 and the second alert display device 202 flash the characters to be displayed. This makes it possible to notify that the calculation period has just begun without reducing the visibility of the base value. Note that this is not limited to this, and the initial calculation display may be configured to flash on at least one of the third alert display device 203 and the fourth alert display device 204, or on both, or on only one of the first alert display device 201 and the second alert display device 202. Furthermore, the initial reference number is not limited to 6,000 and may be any number greater than or equal to 6,000.

At time t2, when the total number of game balls discharged from the game area PA since time t1 in a situation that is neither the open/close execution mode due to a jackpot result nor the high frequency support mode (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6,000), the initial calculation display ends, as shown in Figure 129 (e). This causes the first and second alert display devices 201 and 202 to start lighting up, as well as the third and fourth alert display devices 203 and 204.

After that, at time t3, the display duration period from time t1 has elapsed, and notification of the base value stored in the current status area 311 ends as shown in Figure 129(a), and notification of the base value stored in the first history area 312 begins as shown in Figure 129(b). In this case, the base value stored in the first history area 312 is the final base value calculation result from the previous calculation period, so the initial calculation display is not performed.

After that, at time t4, the display duration period from time t3 has elapsed, and notification of the base value stored in the first history area 312 ends as shown in Figure 129(b), and notification of the base value stored in the second history area 313 begins as shown in Figure 129(c). In this case, the base value stored in the second history area 313 is the final base value calculation result from the two calculation periods prior, so the initial calculation display is not performed.

After that, at time t5, the display duration period from time t4 has elapsed, and notification of the base value stored in the second history area 313 ends as shown in Figure 129(c), and notification of the base value stored in the third history area 314 begins as shown in Figure 129(d). In this case, the base value stored in the third history area 314 is the final base value calculation result from the three calculation periods ago, so the initial calculation display is not performed.

After that, at time t6, the display duration period from time t5 has elapsed, and as shown in FIG. 129(d), notification of the base value stored in the third history area 314 ends, and as shown in FIG. 129(a), notification of the base value stored in the current status area 311 begins. In this case, to notify that the period from when the base value calculation period newly begins until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6,000) in a situation that is neither the open/close execution mode due to a jackpot result nor the high-frequency support mode, an initial calculation display is displayed from time t6 to time t7, as shown in FIG. 129(e).

After that, at time t8, the display duration period from time t6 has elapsed, and notification of the base value stored in the current status area 311 ends as shown in FIG. 129(a), and notification of the base value stored in the first history area 312 begins as shown in FIG. 129(b). In this case, the base value stored in the first history area 312 is the final base value calculation result from the previous calculation period, so the initial calculation display is not performed.

Next, we will explain the processing configuration that enables notification of the base value as described above.

In the management processing (step S8920) of the first timer interrupt processing (Fig. 133) described below, the management execution processing program, which is processing corresponding to non-specific control, is read in step S3803, just like the management processing (Fig. 70) in the 15th embodiment. Then, in this management execution processing (Fig. 71), check processing is executed in step S3908, just like in the 15th embodiment.

During the check process, when neither the jackpot result opening/closing execution mode nor the high-frequency support mode is selected, if a single game ball is identified as having entered the general winning slot 31, the value of the normal general winning counter 231a is incremented by one; if a single game ball is identified as having entered the special electric winning device 32, the value of the normal special electric winning counter 231b is incremented by one; if a single game ball is identified as having entered the first operating slot 33, the value of the normal first operating counter 231c is incremented by one; if a single game ball is identified as having entered the second operating slot 34, the value of the normal second operating counter 231d is incremented by one; and if a single game ball is identified as having entered the outlet slot 24a, the value of the normal out counter 231e is incremented by one. Furthermore, the check process also performs result calculation processing and display processing.

Figure 130 is a flowchart showing the result calculation process. Note that steps S8601 to S8615 in the result calculation process are executed using the non-specific control program and non-specific control data in the main CPU 63.

First, a base value calculation process is performed (step S8601). In this calculation process, the base value is calculated using the values of the various counters 231a to 231e in the normal counter area 231. The method for calculating the base value has already been explained. Then, the calculated base value is overwritten in the current state area 311 (step S8602).

Then, it is determined whether the management start flag set in the non-specific control work area 223 is set to "1" (step S8603). The management start flag is set to "0" when the supply of operating power to the pachinko machine 10 is initiated for the first time after the pachinko machine 10 is manufactured. The management start flag also becomes "0" when the non-specific control work area 223, including the management start flag, is cleared to "0" and initialized. When the management start flag is set to "0" and the mode is neither the open/close execution mode due to a jackpot result nor the high-frequency support mode, the total number of game balls discharged from the play area PA (i.e., the total number of game balls supplied to the play area PA) becomes the management start reference number, and the management start flag is set to "1." Furthermore, when the management start flag is set to "1," the values of the various counters 231a to 231e in the normal counter area 231 are cleared to "0," and a new calculation period begins. This makes it possible to reduce the impact of operational checks performed at the time of shipping the pachinko machine 10 on the base value during normal game play after the pachinko machine 10 has been shipped.

If the determination in step S8603 is negative, the total number is calculated by adding up all the values of the various counters 231a to 231e in the normal counter area 231 (step S8604). It is then determined whether the calculated total number is greater than the management start reference number of 300 (step S8605).

If a positive judgment is made in step S8605, the management start flag is set to "1" (step S8606). Then, data shift processing is executed (step S8607). In the data shift processing, the information stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, and current status area 311 → first history area 312. As a result, the final base value for the calculation period two calculations ago is stored in the third history area 314 as the final base value for the calculation period three calculations ago, the final base value for the calculation period one calculation ago is stored in the second history area 313 as the final base value for the calculation period two calculations ago, and the base value last calculated in the current calculation period is stored in the first history area 312 as the final base value for the calculation period one calculation ago. In data shift processing, the LDIR command is used to shift information as described above. The LDIR command specifies the address of the area from which the information is to be stored and the address of the area to which the information is to be stored, and the information stored in the source area is shifted (copied) to the destination area.

However, when the management start flag is not set to "1", base value information is not generally stored in the first to third history areas 312 to 314. Therefore, in step S8607, essentially, only the final base value for the calculation period when the management start flag is not set to "1" is shifted to the first history area 312. Then, all counters 231a to 231e in the normal counter area 231 are cleared to "0" (step S8608).

If a positive determination is made in step S8603, the total number is calculated by adding up all the values of the various counters 231a-231e in the normal counter area 231 (step S8609). Then, it is determined whether the calculated total number is greater than the initial reference number of 6,000 (step S8610). If a negative determination is made in step S8610, the calculation initial flag provided in the non-specific control work area 223 is set to "1" (step S8611). If a positive determination is made in step S8610, the calculation initial flag is cleared to "0" (step S8612). The calculation initial flag is a flag used by the main CPU 63 to determine whether the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) since the start of a new base value calculation period has reached the initial reference number when the game is not in the open/close execution mode due to a jackpot result or the high-frequency support mode.

When the processing of step S8611 or step S8612 is executed, it is determined whether the total number calculated in step S8609 is equal to or greater than the shift reference number of 60,000 (step S8613). If the determination in step S8613 is affirmative, data shift processing is executed (step S8614). In the data shift processing, similar to step S8607, the information stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, current status area 311 → first history area 312. As a result, the final base value for the calculation period two calculations ago is stored in the third history area 314 as the final base value for the calculation period three calculations ago, the final base value for the calculation period one calculation ago is stored in the second history area 313 as the final base value for the calculation period two calculations ago, and the base value calculated last in the current calculation period is stored in the first history area 312 as the final base value for the calculation period one calculation ago. In the data shift process, the LDIR command is used to shift information as described above. The LDIR command specifies the address of the area from which the information is stored and the address of the area to which the information is to be stored, and the information stored in the source area is shifted (copied) to the destination area. Then, all counters 231a-231e in the normal counter area 231 are cleared to "0" (step S8615).

Figure 131 is a flowchart showing the display processing. Note that steps S8701 to S8714 in the display processing are executed using the non-specific control program and non-specific control data in the main CPU 63.

First, it is determined whether the management start flag provided in the work area 223 for non-specific control is set to "1" (step S8701). If a positive determination is made in step S8701, the value of the switching timing counter provided in the work area 223 for non-specific control is decremented by 1 (step S8702). The switching timing counter is a counter used by the main CPU 63 to determine when it is time to switch the base values to be notified in the first to fourth alarm display devices 201-204, among the base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 of the calculation result storage area 234. As already explained, each time the display duration (specifically, 5 seconds) elapses, the base value to be notified is switched in a predetermined order: current status area 311 → first history area 312 → second history area 313 → third history area 314, and this switching of the base value to be notified in this predetermined order is repeated.

When the processing of step S8702 is executed, it is determined whether the value of the switching timing counter after subtracting 1 is "0" to determine whether the display duration has elapsed since the base value currently being notified became the target for notification (step S8703). If a positive determination is made in step S8703, the value of the display target counter provided in the non-specific control work area 223 is incremented by 1 (step S8704). Then, if the value of the display target counter after incrementing 1 exceeds the maximum value of "3" (step S8705: YES), the value of the display target counter is cleared to "0" (step S8706).

The display target counter is a counter that allows the main CPU 63 to identify the base value to be notified on the first to fourth notification display devices 201-204 from among the base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234. Specifically, if the value of the display target counter is "0," the base value stored in the current status area 311 is the base value to be notified; if the value of the display target counter is "1," the base value stored in the first history area 312 is the base value to be notified; if the value of the display target counter is "2," the base value stored in the second history area 313 is the base value to be notified; and if the value of the display target counter is "3," the base value stored in the third history area 314 is the base value to be notified.

If a negative judgment is made in step S8705, or if the processing of step S8706 is executed, a value corresponding to the display duration (specifically, 5 seconds) is set in the switching timing counter in the non-specific control work area 223 as a value corresponding to the next switching timing of the notification target (step S8707).

If a negative judgment is made in step S8703, or if the processing of step S8707 is executed, processing is executed to set display data corresponding to the base value that is the target of the current notification in the display target setting area 276 provided in the work area 223 for non-specific control. Specifically, display type data corresponding to the value of the display target counter is first set in the display target setting area 276 (step S8708). The display type data includes display data for causing the first notification display device 201 to display an indication that the notification target of the first to fourth notification display devices 201 to 204 is the base value, and display data for causing the second notification display device 202 to display an indication of which of the current status area 311, first history area 312, second history area 313, or third history area 314 in the calculation result storage area 234 the base value of the notification target corresponds to.

Then, the base value is read from the area in the calculation result storage area 234 that corresponds to the value of the counter to be displayed—the current status area 311, the first history area 312, the second history area 313, or the third history area 314—and calculation result data corresponding to the first and second decimal places of the read base value is set in the display target setting area 276 (step S8709). The calculation result data includes display data for causing the third alarm display device 203 to display a number corresponding to the first decimal place of the base value to be notified, and display data for causing the fourth alarm display device 204 to display a number corresponding to the second decimal place of the base value to be notified.

As described above, display data consisting of display type data and calculation result data is set in the display target setting area 276. When this display data is sent to the display IC 266 by the second timer interrupt process (FIG. 134) described below, the first to fourth alarm display devices 201 to 204 display information corresponding to the display data.

In addition, the processing of step S8709 is executed each time the display processing (Figure 131) is executed, regardless of the timing of switching the base value of the notification target. As already explained, each time the calculation result storage processing (Figure 130) is executed, a base value is calculated using the current values of each counter 231a-231e in the normal counter area 231, and the calculated base value is stored in the current status area 311 of the calculation result storage area 234. In this case, as described above, the processing of step S8709 for setting the calculation result data in the display target setting area 276 is executed each time the display processing (Figure 131) is executed, regardless of the timing of switching the base value of the notification target. This makes it possible to notify users of a change to the base value in the current status area 311 when that base value is the notification target.

Then, based on the value of the display target counter, it is determined whether the base value in the current status area 311 is subject to notification (step S8710), and it is determined whether the calculation initial flag provided in the non-specific control work area 223 is set to "1" (step S8711). As already explained, the calculation initial flag is a flag used by the main CPU 63 to determine whether the total number of game balls discharged from the play area PA since the start of a new base value calculation period (i.e., the total number of game balls supplied to the play area PA) in a state other than the jackpot result open/close execution mode or the high-frequency support mode has reached the initial reference number. If both steps S8710 and S8711 result in a positive judgment, the initial display flag provided in the non-specific control work area 223 is set to "1" (step S8712). If either step S8710 or step S8711 result in a negative judgment, the initial display flag is cleared to "0" (step S8713).

The initial display flag is a flag that allows the main CPU 63 to identify a situation in which the first alarm display device 201 and the second alarm display device 202 should be flashed to indicate that the base value in the current status area 311 is the target of notification and that the base value is the initial base value calculated after the start of the calculation period. If the second timer interrupt process (FIG. 134), described below, identifies that the initial display flag is set to "1," not only is the display data stored in the display target setting area 276 sent to the display IC 266, but when the first to fourth alarm display devices 201 to 204 are to display a display corresponding to the display data, the first alarm display device 201 and the second alarm display device 202 are flashed and the third alarm display device 203 and the fourth alarm display device 204 are lit. Furthermore, if the second timer interrupt process (FIG. 134), described below, determines that the initial display flag is not set to "1," all of the first to fourth alarm display devices 201 to 204 will be lit when displaying the display corresponding to the display data stored in the display target setting area 276 on the first to fourth alarm display devices 201 to 204.

On the other hand, if the management start flag provided in the non-specific control work area 223 is not set to "1" and a negative judgment is made in step S8701, the base value is read from the current status area 311 regardless of the value of the display target counter, and calculation result data corresponding to the digits to the first and second decimal places of the read base value is set in the display target setting area 276 (step S8714). By transmitting display data corresponding to the calculation result data to the display IC 266, the digit to the first decimal place of the base value in the current status area 311 is displayed on the third alert display device 203, and the digit to the second decimal place of the base value in the current status area 311 is displayed on the fourth alert display device 204. With the above configuration, when the management start flag is not set to "1", base values from past calculation periods are not reported, and only the base value calculated for the current calculation period is reported.

When the management start flag is not set to "1", calculation result data is set in the display target setting area 276, but display type data is not set. As will be described in detail below, when a base value is notified when the management start flag is not set to "1", the display content of the first notification display device 201 and the second notification display device 202 will be different from when a base value is notified when the management start flag is set to "1".

Next, the main processing in this embodiment executed by the main CPU 63 will be described with reference to the flowchart in Figure 132. Note that steps S8801 to S8825 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, the power-on initialization process is executed (step S8801). During the power-on initialization process, for example, the main process is started and then a predetermined waiting time (specifically, one second) passes before proceeding to the next process. During this predetermined waiting period, the operation of the pattern display device 41 is started and the initial settings are completed. Access to the main RAM 65 is also permitted.

Then, the internal function register setting process is executed (step S8802). In the internal function register setting process, the interrupt period of the first timer interrupt process (Fig. 133), which is a process that periodically interrupts the main process and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt process (Fig. 134), which is a process that periodically interrupts the main process and is started, is set to a second interrupt period (specifically, 2 milliseconds), which is a period shorter than the first interrupt period.

In other words, in this embodiment, similar to the 33rd embodiment, first and second timer interrupt processes exist as timer interrupt processes so that the interrupt periods are relatively long and short. Both the first and second timer interrupt processes are started by interrupting the main process. Furthermore, the second timer interrupt process is started by interrupting the first timer interrupt process. On the other hand, the first timer interrupt process is not started by interrupting the second timer interrupt process. Furthermore, if both the first and second timer interrupt processes are not being executed and both the first and second interrupt periods have elapsed, the second timer interrupt process is started first, regardless of the order in which the periods elapse. In this respect, it can be said that the second timer interrupt process is started with priority over the first timer interrupt process. However, this is not limited to this, and the first timer interrupt process may be started with priority over the second timer interrupt process.

The internal function register setting process sets the first interrupt period of the first timer interrupt process in a specified register of the main CPU 63, and sets the second interrupt period of the second timer interrupt process in a specific register of the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs processes such as setting the numerical ranges of various counters, such as the numerical range of the winning random number counter C1.

Then, the startup processing in progress flag provided in the specific control work area 221 is set to "1" (step S8803). The startup processing in progress flag is a flag that allows the main CPU 63 to identify a situation in which, even if the first timer interrupt processing is started, the various processes set in the first timer interrupt processing, such as power outage monitoring, updating of various counters, and fraud monitoring, will be executed, but the first timer interrupt processing should be terminated without executing any processes to progress the game.

Figure 133 is a flowchart showing the first timer interrupt processing in this embodiment, which is executed by the main CPU 63. As already explained, the first timer interrupt processing is periodically started at a 4-millisecond cycle, which is the first interrupt cycle. The program corresponding to the first timer interrupt processing is set in the program for specific control.

Steps S8901 to S8905 execute the same processing as steps S301 to S305 of the timer interrupt processing (Figure 11) in the first embodiment described above. That is, power outage monitoring is performed by executing power outage information storage processing in step S8901. Specifically, similar to the power outage information storage processing (Figure 101) in the 30th embodiment described above, it monitors whether a power outage signal corresponding to a power outage has been received from the power outage monitoring board 67, and if a power outage has been identified, it executes power outage processing and then enters an infinite loop. In power outage processing, the power outage flag provided in the work area 221 for specific control is set to "1", a checksum is calculated, and the calculated checksum is saved in the work area 221 for specific control. In addition, in step S8902, a lottery random number update process is executed to update the numerical information of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power device release counter C4. In step S8903, a random number initial value update process is executed to update the numerical information of the random number initial value counter CINI. In step S8904, a variable counter update process is executed to update the numerical information of the variable type counter CS. In addition, in step S8905, a fraud detection process is executed to monitor for the occurrence of an event that has been set as a target for fraud monitoring. This fraud detection process monitors the occurrence of multiple types of events, and if it is confirmed that any of these multiple types of events has occurred, a game stop flag provided in the specific control work area 221 is set to "1."

After executing the processing of steps S8901 to S8905, it is determined whether either the game stop flag or the startup processing in progress flag provided in the work area 221 for specific control has been set to "1" (step S8906). If neither the game stop flag nor the startup processing in progress flag has been set to "1" (step S8906: NO), the processing of steps S8907 to S8920 is executed. Steps S8907 to S8919 execute the same processing as steps S8208 to S8220 of the first timer interrupt processing (Figure 117) in the 33rd embodiment. Furthermore, while step S8920 executes management processing similar to step S8221 of the first timer interrupt processing (Figure 117) in the 33rd embodiment, the content of the check processing of the management execution processing called in the management processing has already been described. This check process updates the counters 231a-231e in the normal counter area 231, and also performs result calculation processing (Figure 130) and display processing (Figure 131).

On the other hand, if at least one of the game stop flag and the startup processing flag is set to "1" (step S8906: YES), the first timer interrupt process is terminated without executing steps S8907 to S8920. In other words, not only when the game stop flag is set to "1" but also when the startup processing flag is set to "1", steps S8901 to S8905 are executed in the first timer interrupt process, but steps S8907 to S8920 are not executed.

As in the 33rd embodiment, the startup processing flag is set to "1" in the main processing (FIG. 132) when the processing at the start of the supply of operating power (steps S8801 to S8819) begins and before interrupts are permitted (step S8805), and is cleared to "0" before the processing at the start of the supply of operating power ends and the remaining processing (steps S8822 to S8825) begins. In this case, by not executing the processing of steps S8907 to S8920 when the startup processing flag is set to "1" in the first timer interrupt processing as described above, it is possible to prevent processing to progress the game while the processing at the start of the supply of operating power (steps S8801 to S8819) is being executed. On the other hand, as described above, even if the startup processing in progress flag is set to "1" during the first timer interrupt process, by executing steps S8901 to S8905, power outage monitoring is performed even when processing at the start of operating power supply (steps S8801 to S8819) is being performed, and the win random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is also performed.

In particular, even when the startup processing flag is set to "1," the power outage information storage process (step S8901) is executed, enabling power outage processing to be executed even if a power outage occurs while the processing at the start of the supply of operating power (steps S8801 to S8819) is being executed. As already explained, the power outage processing sets the power outage flag in the specific control work area 221 to "1," calculates a checksum, and stores the calculated checksum in the specific control work area 221. This prevents the restart of the supply of operating power from being identified as an abnormality in the main RAM 65. As a result, even if a power outage occurs during the setting value update process (step S8819), the setting values selected at that time can be stored and retained as the current setting values for the pachinko machine 10. Therefore, even if a power outage occurs during the execution of the setting value update process, there is no need to execute the setting value update process again when the supply of operating power is restarted.

Incidentally, when the setting value update process is being executed, interrupts are not prohibited for either the first timer interrupt process (FIG. 133) or the second timer interrupt process (FIG. 134), and interrupts can occur at any timing. In this case, when the first timer interrupt process (FIG. 133) or the second timer interrupt process (FIG. 134) interrupts and starts the main process (FIG. 132), including the setting value update process, return address information for the main process (FIG. 132) to return to after the timer interrupt process that was started is completed is saved in the specific control stack area 222, and information in various registers of the main CPU 63 immediately before the timer interrupt process was started is saved in the specific control stack area 222. Then, when the timer interrupt process that was started is completed, the main process (FIG. 132) corresponding to the return address information saved in the specific control stack area 222 is returned to, and the information saved in the specific control stack area 222 is restored to the various registers of the main CPU 63.

Returning to the explanation of the main processing (FIG. 132), after the startup processing flag is set to "1" in step S8803, a value corresponding to the initial check period (specifically, 5 seconds) is set to the checking counter provided in the specific control work area 221 (step S8804). In this embodiment, when the supply of operating power to the main CPU 63 begins, a check display is displayed on the first through fourth alarm display devices 201-204 from the start of processing in step S8804 until the initial check period has elapsed, in order to allow the amusement hall manager to confirm whether the display segments 321-324 provided on the first through fourth alarm display devices 201-204 are properly illuminated. Specifically, as shown in the explanatory diagram in FIG. 128(b), this check display maintains the illumination of all display segments 321-324 on the first through fourth alarm display devices 201-204. In step S8804, information corresponding to this initial check period is set to the checking counter.

The initial check period is set to a time longer than the longest time required for processing to control the progress of the game to begin if none of the processes in steps S8811, S8812, S8815, and S8819 described below are executed in the main processing. Therefore, game play may begin while a check display is being displayed on the first through fourth notification display devices 201 through 204.

Then, interrupt permission is set (step S8805). As a result, the first timer interrupt process (Fig. 133) is started by interrupting at the first interrupt cycle, and the second timer interrupt process (Fig. 134) is started by interrupting at the second interrupt cycle. However, because the startup process in progress flag was set to "1" in step S8803, even if the first timer interrupt process is started, the various processes of the first timer interrupt process, such as power outage monitoring, updating various counters, and fraud monitoring, are executed, but the first timer interrupt process ends without executing any processes to progress the game.

Then, in steps S8806 to S8825, the same processing as steps S7905 to S7924 of the main processing (FIG. 114) in the 33rd embodiment is executed. Specifically, in step S8806, it is determined whether the reset button 68c has been pressed. In other words, it is determined whether the power to the pachinko machine 10 has been turned on and the supply of operating power to the main CPU 63 has begun while the reset button 68c has been pressed. Here, in this embodiment, as in the 33rd embodiment, the main control unit 60 is provided with a setting key insertion unit 68a and a reset button 68c, but is not provided with an update button 68b. Furthermore, instead of first to third notification display devices 69a to 69c, the main control unit 60 is provided with first to fourth notification display devices 201 to 204, as in the 11th embodiment.

If the reset button 68c is not pressed (step S8806: NO), it is determined whether the power outage flag provided in the work area 221 for specific control is set to "1" (step S8807). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step S8807: YES), a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step S8808). The checksum calculation method is the same as in the 33rd embodiment. Then, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and saved in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped, are read from the specific control work area 221, and the read checksum is compared with the checksum calculated in step S8808 (step S8809). It is then determined whether the checksums match (step S8810).

If a negative judgment is made in step S8807 or step S8810, i.e., if the power outage flag is not set to "1" or the checksums do not match, the game stop flag provided in the specific control work area 221 is set to "1" (step S8811). Setting the game stop flag to "1" causes steps S8901 to S8905 to be executed in the first timer interrupt process (Figure 133), while a positive judgment is made in step S8906, resulting in steps S8907 to S8920 not being executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly during the previous power outage, or if the checksums do not match because the information storage state in at least one of the specific control work area 221 and the specific control stack area 222 has changed since the previous power outage, processing for power outage monitoring, updating various counters, and fraud monitoring is executed, but processing for progressing the game is not executed.

Then, an abnormality command indicating that an abnormality occurred in the power outage flag or checksum when the supply of operating power began is sent to the audio and light-emitting control device 81 (step S8812). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the information abnormality at the start of the supply of operating power, and causes the speaker unit 54 to output a voice message saying, "Please change the settings." In addition, a text image saying, "Please change the settings" is displayed on the symbol display device 41. These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notifications may be configured to continue when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (step S8819) is executed.

If the power outage flag is set to "1" and the checksum is normal (steps S8807 and S8810: YES), it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step S8813), and it is determined whether the front door frame 14 is open relative to the inner frame 13 and whether the gaming machine main body 12 is open relative to the outer frame 11 (step S8814). The front door open sensor 95 is used to detect whether the front door frame 14 is open relative to the inner frame 13, as in the 30th embodiment, and the main body open sensor 96 is used to detect whether the gaming machine main body 12 is open relative to the outer frame 11, as in the 30th embodiment. If the setting key insertion unit 68a has been turned on using the setting key (step S8813: YES), and the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S8814: YES), a setting confirmation process is executed (step S8815). Details of the setting confirmation process will be explained later.

If the reset button 68c is pressed (step S8806: YES), a RAM clear process is executed (step S8816). The contents of the RAM clear process are the same as step S7915 in the main process (FIG. 114) in the 33rd embodiment. Thereafter, if the setting key insertion unit 68a is turned ON using the setting key (step S8817: YES), and further, if the front door frame 14 is open relative to the inner frame 13 and the gaming machine main body 12 is open relative to the outer frame 11 (step S8818: YES), a setting value update process is executed (step S8819). Details of the setting value update process will be explained later.

If the processing of step S8812 is executed, if a negative judgment is made in step S8813 or step S8814, if the processing of step S8815 is executed, if a negative judgment is made in step S8817 or step S8818, or if the processing of step S8819 is executed, the startup processing in progress flag in the specific control work area 221 is cleared to "0" (step S8820). By clearing the startup processing in progress flag to "0", the state in which processing to progress the game is not executed even if the first timer interrupt processing is activated is canceled. Note that in step S8820, the power outage flag in the specific control work area 221 is also cleared to "0".

Then, a return command is sent to the audio and light emission control device 81 (step S8821). The information contained in the return command and the processing performed by the audio and light emission control device 81 when the return command is received are the same as those in step S7920 of the main processing (Figure 114) in the 33rd embodiment described above.

Then, the process proceeds to the remaining processing of steps S8822 to S8825. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134), but there will be remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time will be used to repeatedly execute the remaining processing of steps S8822 to S8825. In this respect, the remaining processing of steps S8822 to S8825 can be said to be non-periodic processing executed non-periodically. Steps S8822 to S8825 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, the second timer interrupt processing in this embodiment, which is executed by the main CPU 63, will be described with reference to the flowchart in Figure 134. Note that steps S9001 to S9014 in the second timer interrupt processing are executed by the main CPU 63 using a specific control program and specific control data.

First, interrupt prohibition is set to prohibit the occurrence of the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) (step S9001). By prohibiting the occurrence of the first timer interrupt processing (FIG. 133), it is possible to prevent the first timer interrupt processing (FIG. 133) from interrupting and starting the second timer interrupt processing (FIG. 134) even if the first interrupt period has elapsed. Furthermore, by prohibiting the occurrence of the second timer interrupt processing (FIG. 134), it is possible to prevent the second timer interrupt processing (FIG. 134) from being started redundantly, even if the second interrupt period has elapsed during the execution of the second timer interrupt processing (FIG. 134).

Then, the checking counter is updated (step S9002). In the checking counter update process, if the value of the checking counter provided in the specific control work area 221 is 1 or greater, the value of the checking counter is decremented by 1. As a result, when the checking counter is being used to measure the initial check period, the value of the checking counter is decremented periodically each time the second timer interrupt process (Figure 134) is activated.

Then, it is determined whether the setting update display flag in the work area 221 for specific control is set to "1" (step S9003). The setting update display flag is a flag that allows the main CPU 63 to determine whether the setting value update process (FIG. 137) is being executed by the main CPU 63. As already explained, the setting value update process (FIG. 137) is executed when the main process (FIG. 132) is executing the process at the start of the supply of operating power to the main CPU 63, but the second timer interrupt process (FIG. 134) is started by interrupting even when the process at the start of the supply of operating power is being executed. Therefore, even when the main CPU 63 is executing the setting value update process (FIG. 137), the second timer interrupt process (FIG. 134) is started by interrupting.

When the setting update display flag is set to "1," this means that the current second timer interrupt process (FIG. 134) was initiated by interrupting the setting value update process (FIG. 137) being executed by the main CPU 63. If a positive determination is made in step S9003, setting processing is executed in the fifth display data buffer 275 during setting update (step S9004). In this setting processing, similar to step S8403 of the second timer interrupt process (FIG. 123) in the 33rd embodiment, display data is stored in the fifth display data buffer 275 to cause the first to fourth alarm display devices 201 to 204 to display an indication that the setting value of the pachinko machine 10 is being updated and an indication of the current setting value of the pachinko machine 10. As a result, similar to the 33rd embodiment, the first to fourth alarm display devices 201 to 204 display an indication that the setting value is being updated and an indication of the current setting value.

If a negative determination is made in step S9003, it is determined whether the setting confirmation display flag in the work area 221 for specific control is set to "1" (step S9005). The setting confirmation display flag is a flag used by the main CPU 63 to determine whether the setting confirmation process (FIG. 136) is being executed by the main CPU 63. As already explained, the setting confirmation process (FIG. 136) is executed when the main process (FIG. 132) is executing the process at the start of the supply of operating power to the main CPU 63. However, the second timer interrupt process (FIG. 134) is started by interrupting even when the process at the start of the supply of operating power is being executed. Therefore, even when the setting confirmation process (FIG. 136) is being executed by the main CPU 63, the second timer interrupt process (FIG. 134) is started by interrupting.

When the setting confirmation display flag is set to "1," this means that the current second timer interrupt process (FIG. 134) was initiated as an interrupt while the setting confirmation process (FIG. 137) was being executed by the main CPU 63. If a positive determination is made in step S9005, setting processing is executed in the fifth display data buffer 275 during setting confirmation (step S9006). In this setting processing, similar to step S8405 of the second timer interrupt process (FIG. 123) in the 33rd embodiment, display data is stored in the fifth display data buffer 275 to cause the first to fourth alarm display devices 201 to 204 to display an indication that the setting values of the pachinko machine 10 are being checked and an indication of the current setting values of the pachinko machine 10. As a result, similar to the 33rd embodiment, the first to fourth alarm display devices 201 to 204 display an indication that the setting values are being checked and an indication of the current setting values.

If a negative determination is made in step S9005, normal setting processing is executed (step S9007). Normal setting processing will be described in detail later.

If step S9004, step S9006, or step S9007 has been executed, steps S9008 to S9014 are executed. The processing content of steps S9008 to S9014 is the same as steps S8407 to S8413 in the second timer interrupt processing (Figure 123) in the 33rd embodiment.

Specifically, first, the transmission state of signals through the category data signal line LN1 and category clock signal line LN2 is turned OFF (step S9008), and then the transmission state of signals through the display data signal line LN3 and display clock signal line LN4 is turned OFF (step S9009). After that, the category counter provided in the specific control work area 221 is updated (step S9010).

The type counter is a counter used by the main CPU 63 to identify the display data buffer to which the first through fifth display data buffers 271-275 are to be sent in the current second timer interrupt process. If the type counter value is "1," the display data to be sent is from the first display data buffer 271. If the type counter value is "2," the display data to be sent is from the second display data buffer 272. If the type counter value is "3," the display data to be sent is from the third display data buffer 273. If the type counter value is "4," the display data to be sent is from the fourth display data buffer 274. If the type counter value is "5," the display data to be sent is from the fifth display data buffer 275. The type counter update process increments the type counter value by 1, and if the value of the type counter after incrementing by 1 exceeds the upper limit of "5," the type counter value is reset to "1." This sequentially changes the display data to which the first through fifth display data buffers 271-275 are to be sent with each second timer interrupt process.

Then, the type data corresponding to the value of the type counter is read from the main ROM 64 (step S9011). Specifically, if the type counter value is "1", type data corresponding to the first display circuit 261 is read from the main ROM 64; if the type counter value is "2", type data corresponding to the second display circuit 262 is read from the main ROM 64; if the type counter value is "3", type data corresponding to the third display circuit 263 is read from the main ROM 64; if the type counter value is "4", type data corresponding to the fourth display circuit 264 is read from the main ROM 64; and if the type counter value is "5", type data corresponding to the fifth display circuit 265 is read from the main ROM 64.

Then, display data is read from the display data buffers 271-275 corresponding to the value of the type counter (step S9012). Specifically, if the type counter value is "1", display data is read from the first display data buffer 271; if the type counter value is "2", display data is read from the second display data buffer 272; if the type counter value is "3", display data is read from the third display data buffer 273; if the type counter value is "4", display data is read from the fourth display data buffer 274; and if the type counter value is "5", display data is read from the fifth display data buffer 275.

Then, a transmission process for various signals is executed (step S9013). In this transmission process, signals are output to the type data signal line LN1 and the type clock signal line LN2 so that the type data read in step S9011 is transmitted to the display IC 266. In addition, in this transmission process, signals are output to the display data signal line LN3 and the display clock signal line LN4 so that the display data read in step S9012 is transmitted to the display IC 266.

Then, interrupt permission is set to allow the first timer interrupt process (Figure 133) and the second timer interrupt process (Figure 134) to occur (step S9014).

Figure 135 is a flowchart showing the normal setting process in step S9007 of the second timer interrupt process (Figure 134). Note that steps S9101 to S9109 in the normal setting process are executed by the main CPU 63 using a program and data for specific control.

First, it is determined whether the value of the check counter provided in the specific control work area 221 is 1 or greater (step S9101). If the value of the check counter is 1 or greater (step S9101: YES), this means that the initial check period is in progress. In this case, check display data is set in the fifth display data buffer 275 in the specific control work area 221 (step S9102). As already explained, the display data set in the fifth display data buffer 275 is display data for controlling the display of the first to fourth alarm display devices 201-204. Furthermore, the check display data is display data for causing the first to fourth alarm display devices 201-204 to display a check display, i.e., display data for causing all display segments 321-324 in each of the first to fourth alarm display devices 201-204 to emit light. When the check display data is supplied to the display IC 266, all display segments 321-324 in each of the first through fourth alert display devices 201-204 are illuminated as a check display, as shown in the explanatory diagram in Figure 128(b). This allows the amusement hall manager to determine whether each of the display segments 321-324 in the first through fourth alert display devices 201-204 is illuminating normally.

The initial check period can be canceled when checking settings or updating setting values. This cancellation feature will be explained below. Figure 136 is a flowchart showing the setting confirmation process executed in step S8815 of the main processing (Figure 132). Note that steps S9201 to S9206 in the setting confirmation process are executed using a specific control program and specific control data in the main CPU 63.

First, an operation instruction command is sent to the audio and light control device 81 (step S9201). Upon receiving this operation instruction command, the audio and light control device 81 outputs a voice message from the speaker unit 54 saying, "Please operate the reset button 68c." This notification continues until the reset button 68c is pressed.

Then, it is determined whether the reset button 68c has been pressed (step S9202). If the reset button 68c has not been pressed, the system waits in step S9202. If the reset button 68c has been pressed (step S9202: YES), the checking counter provided in the work area 221 for specific control is cleared to "0" (step S9203). This cancels the initial check period.

Then, the setting confirmation display flag provided in the specific control work area 221 is set to "1" (step S9204). By setting the setting confirmation display flag to "1", the second timer interrupt process (FIG. 134) makes a positive determination in step S9005, as already explained, and stores display data in the fifth display data buffer 275 to cause the first to fourth alarm display devices 201 to 204 to display an indication that the setting values of the pachinko machine 10 are being checked and an indication of the current setting values of the pachinko machine 10 (step S9006). As a result, as in the 33rd embodiment above, the first to fourth alarm display devices 201 to 204 display an indication that the setting values are being checked and an indication of the current setting values.

Subsequently, provided that the setting key insertion section 68a has been turned OFF (step S9205: YES), the setting confirmation display flag in the specific control work area 221 is cleared to "0" (step S9206). This cancels the state in which the first to fourth notification display devices 201 to 204 display the current setting value of the pachinko machine 10 and indicate that the current setting value of the pachinko machine 10 is being confirmed. In this case, the first to fourth notification display devices 201 to 204 begin displaying the base value.

When the setting confirmation process is initiated as described above, the initial check period is canceled midway and the first to fourth alarm display devices 201 to 204 display the current setting values, provided that the reset button 68c is pressed. As a result, when the supply of operating power to the main CPU 63 is initiated and the main processing (Figure 132) is initiated by the main CPU 63, even if the initial check period is initiated and the first to fourth alarm display devices 201 to 204 display check displays while the processing at the start of operating power supply in the main processing is being executed, the initial check period can be canceled and the first to fourth alarm display devices 201 to 204 can display the current setting values if the setting values are to be confirmed while the processing at the start of operating power supply is being executed. This makes it possible to confirm the setting values without waiting for the initial check period to elapse.

In addition, even when the setting confirmation process (Figure 136) is executed during the main process (Figure 132), the initial check period starts first, so it is possible to check the setting values after confirming whether each display segment 321-324 on each of the first through fourth alarm display devices 201-204 can normally emit light. This allows the setting values to be checked accurately.

Figure 137 is a flowchart showing the setting value update process executed in step S8819 of the main processing (Figure 132). Note that steps S9301 to S9310 in the setting value update process are executed using the specific control program and specific control data in the main CPU 63.

First, an update start command is sent to the audio and light emitting control device 81 (step S9301). Upon receiving this update start command, the audio and light emitting control device 81 outputs a voice message from the speaker unit 54 saying "Settings are being changed." This notification continues until the setting value update process is completed.

Then, it is determined whether the value of the setting value counter provided in the specific control work area 221 is greater than or equal to 1, corresponding to "Setting 1," and less than or equal to 6, corresponding to "Setting 6" (step S9302). If the value of the setting value counter is "0" or greater than or equal to 7, a negative determination is made in step S9302, and the setting value counter is set to "1" (step S9303). As a result, the setting value of the pachinko machine 10 becomes "Setting 1."

If a positive determination is made in step S9302 or if the processing of step S9303 is executed, it is determined whether the setting key insertion unit 68a has been turned off using the setting key (step S9304). In this case, the configuration may be such that it determines whether the setting key insertion unit 68a has switched from an ON state to an OFF state, or whether the setting key insertion unit 68a is in the OFF state.

If the setting key insertion section 68a has not been turned OFF (step S9304: NO), it is determined whether the reset button 68c has been pressed (step S9305). If the reset button 68c has been pressed (step S9305: YES), and provided that the setting update display flag provided in the specific control work area 221 is not set to "1" (step S9306: NO), the setting update display flag is set to "1" (step S9307), and the checking counter provided in the specific control work area 221 is cleared to "0" (step S9308).

By clearing the checking counter to "0", the initial check period is canceled. Furthermore, by setting the setting update display flag to "1", the second timer interrupt process (FIG. 134) makes a positive determination in step S9003, as already explained, and stores display data in the fifth display data buffer 275 to cause the first to fourth notification display devices 201 to 204 to display an indication that the setting values of the pachinko machine 10 are being updated and an indication of the current setting values of the pachinko machine 10 (step S9004). As a result, as in the 33rd embodiment above, the first to fourth notification display devices 201 to 204 display an indication that the setting values are being updated and an indication of the current setting values.

If a positive determination is made in step S9306, or if the processing of step S9308 is executed, the value of the setting value counter in the work area 221 for specific control is incremented by 1 (step S9309). As a result, the setting value is updated to the next higher level each time the reset button 68c is pressed. Furthermore, if the reset button 68c is not pressed (step S9305: NO) or the setting value counter value is incremented by 1, processing returns to step S9302. However, if it is determined in step S9302 that the setting value counter value is 7 or greater, the setting value counter is set to "1" in step S9303. As a result, if the reset button 68c is pressed once when the setting is "6," the setting returns to "1."

If the setting key insertion section 68a has been turned OFF (step S9304: YES), the setting update display flag in the specific control work area 221 is cleared to "0" (step S9310). This cancels the first to fourth notification display devices 201 to 204 from displaying an indication that the setting values of the pachinko machine 10 are being updated and from displaying the current setting values of the pachinko machine 10. In this case, the first to fourth notification display devices 201 to 204 will begin displaying the base values.

When the setting value update process is performed as described above, the initial check period is canceled midway and the first to fourth alarm display devices 201 to 204 display the current setting value, provided that the reset button 68c is pressed. As a result, when the supply of operating power to the main CPU 63 is started and the main processing (Figure 132) is initiated by the main CPU 63, even if the initial check period is started and the first to fourth alarm display devices 201 to 204 display a check display while the processing at the start of operating power supply in the main processing is being executed, if the setting value is updated while the processing at the start of operating power supply is being executed, the initial check period can be canceled and the first to fourth alarm display devices 201 to 204 display the current setting value. This makes it possible to update the setting value while checking the current setting value, without waiting for the initial check period to elapse.

In addition, even when the setting value update process (Figure 137) is executed during the main process (Figure 132), the initial check period starts first, so the setting value can be updated after confirming whether each display segment 321-324 in each of the first through fourth alarm display devices 201-204 can normally emit light. This allows the setting value to be updated accurately.

In addition, when the reset button 68c is pressed to update the setting value during the setting value update process (Figure 137), the initial check period is canceled. This means that when the reset button 68c is pressed to update the setting value, the initial check period is also canceled, making it easier to cancel the initial check period.

Returning to the explanation of the normal setting process (Figure 135), if the value of the checking counter is "0" and it is not the initial check period (step S9101: NO), it is determined whether the management start flag provided in the non-specific control work area 223 is set to "1" (step S9103). If the management start flag is not set to "1" (step S9103: NO), a setting process for the pre-control start display is executed for the first and second alarm display devices 201, 202 (step S9104). In this setting process, display data for lighting all display segments 321, 322 on each of the first and second alarm display devices 201, 202 is set in the fifth display data buffer 275. Note that the first and second alarm display devices 201 and 202 are not limited to a configuration in which all display segments 321 and 322 are illuminated, and the first and second alarm display devices 201 and 202 may be configured so that all display segments 321 and 322 are flashing.

Then, the calculation result data set in the display target setting area 276 in the work area 223 for non-specific control is read (step S9105), and the read calculation result data is set in the fifth display data buffer 275 as display data to be applied to the third and fourth alarm display devices 203, 204 (step S9106). As already explained, in the display process (FIG. 131), if the management start flag is not set to "1" (step S8701: NO), the base value is read from the current status area 311, and the calculation result data corresponding to the digits to the first and second decimal places of the read base value are set in the display target setting area 276 (step S8714). In step S9106, this calculation result data is set in the fifth display data buffer 275 as display data to be applied to the third and fourth alarm display devices 203, 204.

When the display data set in the fifth display data buffer 275 in steps S9104 and S9106 is supplied to the display IC 266, as shown in the explanatory diagram of FIG. 128(c), with all display segments 321, 322 illuminated in each of the first and second alert display devices 201, 202, the third alert display device 203 displays the first decimal place of the base value calculated for the current calculation period, and the fourth alert display device 204 displays the second decimal place of the base value calculated for the current calculation period. By displaying the number corresponding to the base value on the third and fourth alert display devices 203, 204 while all display segments 321, 322 illuminate in each of the first and second alert display devices 201, 202, it is possible to make the amusement hall manager aware that the currently reported base value is the base value in a situation where the management start flag is not set to "1".

Furthermore, when the management start flag is set to "1", as already explained, the base value to be notified in the first to fourth notification display devices 201-204 is switched in the predetermined order of current status area 311 → first history area 312 → second history area 313 → third history area 314 each time the display duration period (specifically, 5 seconds) elapses. In contrast, when the management start flag is not set to "1", the base value in the current status area 311 remains the value to be notified. This makes it possible to check the current base value at any time when an operation check of the pachinko machine 10 is performed at the time of shipment.

If the management start flag is set to "1" (step S9103: YES), the display data set in the display target setting area 276 in the work area 223 for non-specific control is read, and the read display data is set in the fifth display data buffer 275 (step S9107). When the display data is supplied to the display IC 266, if the base value in the current status area 311 is the subject of notification, a display such as that shown in the explanatory diagram of FIG. 127(a) is made on the first to fourth alert display devices 201 to 204; if the base value in the first history area 312 is the subject of notification, a display such as that shown in the explanatory diagram of FIG. 127(b) is made on the first to fourth alert display devices 201 to 204; if the base value in the second history area 313 is the subject of notification, a display such as that shown in the explanatory diagram of FIG. 127(c) is made on the first to fourth alert display devices 201 to 204; and if the base value in the third history area 314 is the subject of notification, a display such as that shown in the explanatory diagram of FIG. 127(d) is made on the first to fourth alert display devices 201 to 204.

Then, it is determined whether the initial display flag provided in the work area 223 for non-specific control is set to "1" (step S9108). As already explained, the initial display flag is a flag used by the main CPU 63 to identify a situation in which the first alarm display device 201 and the second alarm display device 202 should be flashed to notify the user that the base value in the current status area 311 is the target of notification, and that this base value is the initial base value calculated after the start of the calculation period. If the initial display flag is set to "1" (step S9108: YES), a flashing setting process is executed for the first and second alarm display devices 201, 202 (step S9109).

In this blinking setting process, when a display corresponding to the display data currently set in the fifth display data buffer 275 is displayed on the first and second alarm display devices 201, 202, the display is set to blink. Specifically, to set the display data for the first and second alarm display devices 201, 202, data corresponding to the display data currently set in the fifth display data buffer 275 is sent to the display IC 266 until a predetermined lighting period (e.g., 0.5 seconds) has elapsed, and then data that turns off all display segments 321, 322 of the first and second alarm display devices 201, 202 is sent to the display IC 266 until a predetermined lighting period (e.g., 0.5 seconds) has elapsed, and then these predetermined lighting periods and predetermined lighting periods are alternately repeated. As a result, if the base value in the current state area 311 becomes the target of notification immediately after a new calculation period for the base value has begun, the first and second notification display devices 201, 202 will display the initial calculation result, allowing the amusement hall manager to understand that the current base value being reported on the first through fourth notification display devices 201-204 is the value immediately after the start of the new calculation period.

Next, the display contents of the first to fourth notification display devices 201 to 204 when the supply of operating power to the main CPU 63 is started will be explained with reference to the time chart in Figure 138. Figure 138(a) shows the initial check period, Figure 138(b) shows the pre-management display period in which the base values are displayed on the first to fourth notification display devices 201 to 204 when the management start flag is not set to "1", Figure 138(c) shows the normal display period in which the base values stored in the various areas 311 to 314 of the calculation result storage area 234 are displayed sequentially on the first to fourth notification display devices 201 to 204, and Figure 138(d) shows the display period in which the setting values of the pachinko machine 10 are updated. Figure 138(e) shows a display indicating that the setting values of the pachinko machine 10 are being checked and a display indicating the current setting values of the pachinko machine 10 are being displayed on the first to fourth notification display devices 201 to 204 during a setting update display period, and Figure 138(f) shows the timing when the reset button 68c is pressed.

First, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is not set to "1" and the setting confirmation process (Figure 136) and setting value update process (Figure 137) are not executed during the processing at the start of the supply of operating power.

At timing t1, the initial check period begins as shown in Figure 138(a). This causes the first to fourth notification display devices 201-204 to start displaying check information, as shown in the explanatory diagram in Figure 128(b).

After that, at timing t2, the initial check period ends without being canceled midway, as shown in Figure 138(a). In this case, at timing t2, the pre-management display period begins, as shown in Figure 138(b). During the pre-management display period, as shown in the explanatory diagram in Figure 128(c), all display segments 321, 322 are illuminated on the first alert display device 201 and second alert display device 202, and numbers corresponding to the current base value are displayed on the third alert display device 203 and fourth alert display device 204.

After that, at timing t3, when the management start flag is not set to "1" and the game is not in either the jackpot result open/close execution mode or the high-frequency support mode, the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the management start reference number, which is less than the shift reference number. This sets the management start flag to "1," ending the pre-management start display period as shown in Figure 138(b). In this case, the normal display period begins at timing t3 as shown in Figure 138(c). During the normal display period, the base values stored in the various areas 311-314 in the calculation result storage area 234 are sequentially reported by the first to fourth notification display devices 201-204 as shown in Figures 127(a) to 127(d).

Next, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is set to "1" and the setting confirmation process (Figure 136) and setting value update process (Figure 137) are not executed during the processing at the start of the supply of operating power.

At timing t4, the initial check period begins as shown in Figure 138(a). This causes the first to fourth notification display devices 201-204 to start displaying check information, as shown in the explanatory diagram in Figure 128(b).

Then, at timing t5, the initial check period ends without being canceled midway, as shown in Figure 138(a). In this case, at timing t5, the normal display period begins, as shown in Figure 138(c). During the normal display period, the base values stored in the various areas 311-314 in the calculation result storage area 234 are sequentially reported by the first to fourth notification display devices 201-204, as shown in Figures 127(a) to 127(d).

Next, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is set to "1" and the setting value update process (Figure 137) is executed during the process at the start of the supply of operating power.

At timing t6, the initial check period begins as shown in Figure 138(a). This causes the first to fourth notification display devices 201-204 to start displaying check information, as shown in the explanatory diagram in Figure 128(b).

Then, during the initial check period, the setting value update process (Figure 137) is started, and at timing t7, the reset button 68c is pressed as shown in Figure 138(f). This ends the initial check period midway at timing t7 as shown in Figure 138(a), and at timing t7, the setting update display period begins as shown in Figure 138(d).

Then, at timing t8, the setting update display period ends as shown in Figure 138(d). In this case, at timing t8, the normal display period begins as shown in Figure 138(c). During the normal display period, the base values stored in the various areas 311-314 in the calculation result storage area 234 are sequentially reported by the first to fourth notification display devices 201-204 as shown in Figures 127(a) to 127(d).

Next, we will explain the case where the supply of operating power to the main CPU 63 is started when the management start flag is set to "1" and the setting confirmation process (Figure 136) is executed during the process at the start of the supply of operating power.

At timing t9, the initial check period begins as shown in Figure 138(a). This causes the first to fourth notification display devices 201-204 to start displaying check information, as shown in the explanatory diagram in Figure 128(b).

Then, during the initial check period, the setting confirmation process (Figure 136) is started, and at timing t10, the reset button 68c is pressed as shown in Figure 138(f). This ends the initial check period midway at timing t10 as shown in Figure 138(a), and at timing t10, the setting confirmation display period begins as shown in Figure 138(e).

Then, at timing t11, the setting confirmation display period ends as shown in Figure 138(e). In this case, at timing t11, the normal display period begins as shown in Figure 138(c). During the normal display period, the base values stored in the various areas 311-314 in the calculation result storage area 234 are sequentially displayed by the first to fourth display devices 201-204 as shown in Figures 127(a) to 127(d).

In addition, if the supply of operating power to the main CPU 63 begins when the management start flag is not set to "1," and the setting confirmation process (Figure 136) or setting value update process (Figure 137) is executed during the processing at the start of the supply of operating power, and the initial check period is canceled midway, the pre-management display period will begin after the setting update display period or setting confirmation display period ends.

The present embodiment described above provides the following excellent effects:

An initial check period may occur during which each display segment 321-324 on each of the first through fourth alarm display devices 201-204 is illuminated as a check display. This makes it possible to check whether each display segment 321-324 is illuminated, and to confirm whether the first through fourth alarm display devices 201-204 are operating normally.

When the supply of operating power to the main CPU 63 begins, an initial check period for the first to fourth alarm display devices 201-204 begins. This makes it possible to quickly check whether the first to fourth alarm display devices 201-204 are operating normally when the supply of operating power begins.

An initial check period for the first through fourth alarm display devices 201-204 begins each time the supply of operating power to the main CPU 63 begins. This makes it possible to check whether the first through fourth alarm display devices 201-204 are operating normally each time the supply of operating power begins.

When the supply of operating power to the main CPU 63 begins, the initial check period for the first through fourth alarm display devices 201-204 begins without the need for any special operations. This makes it easy to check whether the first through fourth alarm display devices 201-204 are operating normally.

If a cancellation trigger occurs even before the initial check period has elapsed, the check display on the first to fourth notification display devices 201 to 204 will be terminated. This makes it possible to terminate the check display even during the initial check period and display another display on the first to fourth notification display devices 201 to 204.

When the supply of operating power to the main CPU 63 begins but before processing to control the progress of the game is executed, an initial check period begins and the above-mentioned check display begins on the first through fourth notification display devices 201-204. This makes it possible to check whether the first through fourth notification display devices 201-204 are operating normally before game play begins.

In a configuration in which predetermined setting-related processes such as the setting confirmation process (FIG. 136) and the setting value update process (FIG. 137) are executed while processing is being executed when the supply of operating power is started, the initial check period is initiated while processing is being executed when the supply of operating power is started. This makes it possible to integrate not only the predetermined setting-related processes but also the processing for starting the initial check period into the processing when the supply of operating power is started.

In the setting confirmation process (Figure 136) and setting value update process (Figure 137), the first to fourth alert display devices 201-204 are configured to display the current setting values. Before these specified setting-related processes are executed, an initial check period begins and the first to fourth alert display devices 201-204 start displaying the check display. This makes it possible to check the current setting values using the first to fourth alert display devices 201-204 after checking whether the first to fourth alert display devices 201-204 are operating normally. This allows for accurate confirmation of setting values.

If the setting confirmation process (FIG. 136) or the setting value update process (FIG. 137) is executed during the initial check period, the above check display on the first to fourth alert display devices 201 to 204 will be terminated midway, even if the initial check period has not yet elapsed. As a result, when the setting confirmation process (FIG. 136) or the setting value update process (FIG. 137) is executed, the above check process on the first to fourth alert display devices 201 to 204 can be terminated without waiting for the initial check period to elapse, and the current setting values can be displayed on the first to fourth alert display devices 201 to 204. This makes it possible to check the current setting values early.

If the setting confirmation process (FIG. 136) or setting value update process (FIG. 137) is executed during the initial check period and the reset button 68c is pressed, the check display on the first to fourth alert display devices 201-204 will be terminated midway, even if the initial check period has not yet elapsed. This makes it possible to terminate the initial check period at any time after the setting confirmation process (FIG. 136) or setting value update process (FIG. 137) has begun. For example, when the setting confirmation process (FIG. 136) or setting value update process (FIG. 137) has begun, the amusement hall manager can thoroughly confirm that the first to fourth alert display devices 201-204 are operating normally, and then terminate the check display on the first to fourth alert display devices 201-204 and begin displaying the current setting values.

Furthermore, in the setting value update process (Figure 137), pressing the reset button 68c updates the setting value of the selected item. In this case, by arranging the first to fourth notification display devices 201 to 204 to end the check display and start displaying the current setting value when the reset button 68c is pressed as described above, there is no need for a dedicated operation to end the check display and start displaying the current setting value. This makes it possible to improve the operability of updating setting values.

The calculation result storage area 234 stores multiple base values derived using information from the normal counter area 231 for different periods. This makes it possible to grasp the base values for multiple periods, and therefore accurately grasp the ratio of the number of prize balls to the number of game balls supplied to the game area PA.

The calculation result storage area 234 is provided with a current state area 311, which stores the most recent base value, and first to third history areas 312 to 314, which store base values derived earlier. This makes it possible to grasp the ratio of the number of prize balls to the number of game balls supplied to the game area PA not only for the most recent time, but also for past times.

Before one calculation period has elapsed, the base value, which is repeatedly calculated at relatively short intervals, is stored in the current status area 311, and the base value calculated when one calculation period has elapsed is stored in the first to third history areas 312 to 314. This makes it possible to grasp the most recent ratio of the number of prize balls to the number of game balls supplied to the play area PA, as well as grasp the above ratio in the past in units of one calculation period. Furthermore, because the first to third history areas 312 to 314 store base values in units of one calculation period, it is possible to reduce the number of base values stored in the first to third history areas 312 to 314.

When a calculation period has elapsed, the various counters 231a-231e in the normal counter area 231 are cleared to "0." This makes it possible to reduce the storage capacity required in the normal counter area 231. Furthermore, even if the various counters 231a-231e in the normal counter area 231 are configured to be cleared to "0" in this way, the base values calculated when a calculation period has elapsed are stored in the first to third history areas 312-314, making it possible to later determine the ratio of the number of prize balls to the number of game balls supplied to the game area PA during past calculation periods.

Multiple history areas 312-314 are provided as areas for storing past base values. This makes it possible to compare base values from multiple past calculation periods.

The base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 are displayed sequentially on the first through fourth notification display devices 201-204. This makes it possible to individually grasp the base values for multiple calculation periods while limiting the number of notification devices 201-204.

Even when processing is being performed at the start of the supply of operating power, the power outage information storage process (step S8901) is executed, which monitors for the occurrence of a power outage and executes power outage processing if a power outage is identified. This makes it possible to respond appropriately if a power outage occurs while processing is being performed at the start of the supply of operating power.

In a configuration in which the first timer interrupt process (Figure 133) includes the power outage information storage process (step S8901), the first timer interrupt process is initiated even when processing is being executed at the start of the supply of operating power. This makes it possible to periodically monitor for the occurrence of a power outage even when processing is being executed at the start of the supply of operating power.

The first timer interrupt process (Figure 133) is started even when remaining processing is being executed after the processing at the start of the supply of operating power has finished. This makes it possible to periodically monitor for the occurrence of a power outage while processing at the start of the supply of operating power is being executed by using the first timer interrupt process, which is started by interrupting remaining processing.

If the first timer interrupt process (Fig. 133) is started as an interrupt while processing is being executed when the supply of operating power begins, the startup processing in progress flag provided in the specific control work area 221 is set to "1", and processing to continue play will not be executed. This makes it possible to prevent processing to continue play from being executed while processing is being executed when the supply of operating power begins, in a configuration in which the first timer interrupt process is started as an interrupt and power outages are periodically monitored, even when processing is being executed when the supply of operating power begins.

In a configuration in which the setting value update process (Figure 137) is executed while processing is being executed at the start of the supply of operating power, the power outage information storage process (step S8901) is executed even while processing is being executed at the start of the supply of operating power. This makes it possible to appropriately respond to a power outage that occurs while setting the setting values to be used.

The check display on the first to fourth alert display devices 201-204 is not limited to being terminated when the initial check period has elapsed, but may instead be configured to continue until an operation to terminate the check display is performed. For example, the operation to terminate the check display may involve operating the reset button 68c regardless of whether the setting confirmation process (FIG. 136) or the setting value update process (FIG. 137) is being executed, or an operation unit other than the reset button 68c may be operated. In this case, the check display on the first to fourth alert display devices 201-204 continues until it is time to check the base value or setting value on the first to fourth alert display devices 201-204. This makes it possible to check the base value or setting value after confirming whether the first to fourth alert display devices 201-204 are normal. Furthermore, because the check display is terminated based on operation of the operation unit, the check display can be terminated at the desired timing.

Also, the first to fourth notification display devices 201 to 204 may be configured to start a check display when a predetermined operation unit, such as the update button 68b or reset button 68c, is operated, regardless of whether the supply of operating power has started. In this case, it is possible to start the check display at the desired timing when checking the base value or set value. In this configuration, the check display may also be configured to end when a predetermined period (e.g., 5 seconds) has elapsed, or when the predetermined operation unit operated to start the check display or a different operation unit is operated.

Also, if the supply of operating power to the main CPU 63 is initiated while a specific operation unit other than the reset button 68c, such as the update button 68b, is operated, the check display of the first to fourth notification display devices 201-204 may be initiated, but if the supply of operating power to the main CPU 63 is initiated without the specific operation unit being operated, the check display may not be initiated. In this case, in a configuration in which the check display is initiated when the supply of operating power is initiated, the amusement hall manager can select whether or not to initiate the check display by operation.

Furthermore, the configuration is not limited to displaying the base value on the first to fourth alert display devices 201-204 regardless of whether the gaming machine main body 12 is in the open state. Alternatively, the base value may be displayed on the first to fourth alert display devices 201-204 when the gaming machine main body 12 is determined to be in the open state based on the detection results of the main body open sensor 96. In this case, when the gaming machine main body 12 is in the open state, the first to fourth alert display devices 201-204 may first start displaying the check display, and then the base value may be displayed on the first to fourth alert display devices 201-204. This makes it possible to check whether the first to fourth alert display devices 201-204 are normal before checking the base value. Furthermore, in this configuration, the check display may be terminated after a predetermined period (e.g., 5 seconds) has elapsed. Alternatively, the check display may be terminated when the predetermined operation unit operated to start the check display or a different operation unit is operated.

Also, if the main processing (FIG. 132) is started when the conditions for executing the setting confirmation processing (FIG. 136) are met, the check display of the first to fourth notification display devices 201 to 204 may not be started, but if the main processing is started when the conditions for executing the setting confirmation processing are not met, the check display may be started. In this case, it is possible to prevent the check display from being displayed if it has been determined that the setting value will be confirmed.

Alternatively, if the main processing (FIG. 132) is started when the conditions for executing the setting value update processing (FIG. 137) are met, the check display of the first to fourth notification display devices 201 to 204 may not be started, but if the main processing is started when the conditions for executing the setting value update processing are not met, the check display may be started. In this case, it is possible to prevent the check display from being displayed when it is confirmed that the setting value will be updated.

Furthermore, if the main processing (FIG. 132) is started with either the conditions for executing the setting confirmation processing (FIG. 136) or the conditions for executing the setting value update processing (FIG. 137) satisfied, the check display of the first to fourth notification display devices 201 to 204 may not be started, but if the main processing is started with neither the conditions for executing the setting confirmation processing nor the conditions for executing the setting value update processing satisfied, the check display may be started. In this case, it is possible to prevent the check display from being displayed if it has been confirmed that the setting value will be confirmed or updated.

Furthermore, the check display is not limited to a configuration in which each of the display segments 321-324 on each of the first to fourth alarm display devices 201-204 remains lit, and each of the display segments 321-324 on each of the first to fourth alarm display devices 201-204 may be set to a flashing state. Furthermore, the check display may be configured such that each of the display segments 321-324 on each of the first to fourth alarm display devices 201-204 sequentially lights up one by one or a portion of multiple segments at a time, with each of the display segments 321-324 lighting up at least once within the initial check period.

Furthermore, the process of displaying a check mark on the first to fourth notification display devices 201 to 204 is not limited to a configuration in which it is executed as a process corresponding to specific control, but may also be configured to be executed as a process corresponding to non-specific control.

Furthermore, if a base value is not stored in any of the first to third history areas 312-314 of the calculation result storage area 234, that history area 312-314 may not be the target of notification on the first to fourth alarm display devices 201-204. In this case, for example, if a base value is stored in the current status area 311 and the first history area 312, but a base value is not stored in the second history area 313 and the third history area 314, the target of notification on the first to fourth alarm display devices 201-204 will be switched between the current status area 311 and the first history area 312 each time the display duration period elapses, and the second history area 313 and the third history area 314 will not be the target of notification.

In addition, the current status area 311, first history area 312, second history area 313 and third history area 314 of the calculation result memory area 234 are configured to store a base value expressed as a decimal to two decimal places, but this is not limited to this, and the configuration may also be such that information on a combination of the digit to the first decimal place and the digit to the second decimal place of the base value is stored, or the configuration may be such that information on a combination of the total number of game balls paid out to enable the base value to be calculated (K91 x "number of prize balls for winning at the general winning port 31" + K92 x "number of prize balls for winning at the special electric winning device 32" + K93 x "number of prize balls for winning at the first operating port 33" + K94 x "number of prize balls for winning at the second operating port 34") and the total number of game balls discharged from the skill area PA (K91 + K92 + K93 + K94 + K95) is stored. In the former case, the information in the various areas 311-314 can be set directly in the display target setting area 276; in the latter case, the information in the various areas 311-314 is used to calculate a base value, and then the information on the digits to the first and second decimal places extracted from that base value is set in the display target setting area 276.

Furthermore, the calculation result storage area 234 may be configured to have only the current status area 311 and the first history area 312 as areas for storing base values, or may be configured to have only the current status area 311, the first history area 312, and the second history area 313. Furthermore, it may be configured to have four or more areas as history areas for storing information on past base values.

Furthermore, the calculation result storage area 234 is not limited to a configuration in which the various areas 311 to 314 have fixed addresses and the base value is shifted within these various areas 311 to 314 as needed; the various areas 311 to 314 may also be configured as ring buffers.

In addition, instead of calculating a base value as mode information, the 61st to 68th parameters may be calculated as in the fifteenth embodiment. In this case, all of the 61st to 68th parameters may be stored in the current status area 311, the first history area 312, the second history area 313, and the third history area 314 of the calculation result storage area 234, respectively. Alternatively, the 61st to 68th parameters may be stored in the current status area 311, but only some parameters, such as the 61st parameter, may be stored in the first to third history areas 312 to 314.

Furthermore, in addition to or instead of the base value, the probability of a jackpot result occurring may be calculated and stored as mode information, or the probability of a high-frequency support mode occurring may be calculated and stored.

Furthermore, the trigger for shifting the base values in the various areas 311-314 in the calculation result storage area 234 is not limited to when the total number of game balls discharged from the game area PA exceeds the shift reference number, but may be configured to cause a shift when a predetermined period of time (e.g., 8 hours) has elapsed, or when the supply of operating power to the main CPU 63 is stopped, or when the supply of operating power to the main CPU 63 is started, or when the setting value of the pachinko machine 10 is changed. There may also be multiple triggers for a shift.

Furthermore, the display segments 321, 322 on each of the first and second alarm display devices 202 are not limited to being maintained in an illuminating state until the management start flag provided in the non-specific control work area 223 is set to "1", but may be configured so that the display segments 321, 322 on each of the first and second alarm display devices 202 are flashing. Furthermore, until the management start flag is set to "1", the first to fourth alarm display devices 201-204 may be configured to repeatedly display "bL.--" → "b1.--" → "b2.--" → "b3.--".

In addition, until the management start flag provided in the work area 223 for non-specific control is set to "1", a check display in which the display segments 321-324 on each of the first to fourth alarm display devices 201-204 are illuminated is not displayed, and instead the display segments 321, 322 on each of the first and second alarm display devices 201, 202 are illuminated or flashing, and a display corresponding to the current base value is displayed on the third and fourth alarm display devices 203, 204, indicating that the management start flag has not been set to "1".

Furthermore, if the power outage flag is not set to "1" or the checksums do not match, the game stop flag is set to "1" and game progress is stopped, the first to fourth alarm display devices 201 to 204 may be configured to illuminate the display segments 321 to 324 in the same way as the check displays, or the display segments 321 to 324 may be configured to flash.

Furthermore, display control of the first to fourth alarm display devices 201-204 is not limited to being performed by the main CPU 63, but may also be performed by a dedicated control means, the audio and light control device 81, or the display control device 82. In this case, when a base value is displayed on the first to fourth alarm display devices 201-204, the base value to be notified is transmitted from the main CPU 63 to the control means that serves as the main controller. When a set value is displayed on the first to fourth alarm display devices 201-204, the set value to be notified is transmitted from the main CPU 63 to the control means that serves as the main controller. Furthermore, when the main CPU 63 performs processing at the start of operating power supply, information corresponding to the start of the check display is transmitted from the main CPU 63 to the control means that serves as the main controller, so that the check display is initiated on the first to fourth alarm display devices 201-204 while the processing at the start of operating power supply is being executed.

<Thirty-sixth embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 35th embodiment. The configuration that differs from the 35th embodiment will be described below. Note that the description of the same configuration as the 35th embodiment will basically be omitted.

Figure 139 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S9401 to S9426 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Steps S9401 to S9403 execute the same processing as steps S8801 to S8803 of the main processing (Figure 132) in the 35th embodiment. Then, interrupt permission is set (step S9404). As a result, the first timer interrupt processing (Figure 133) is started at the first interrupt cycle, and the second timer interrupt processing (Figure 134) is started at the second interrupt cycle. However, because the startup processing in progress flag was set to "1" in step S9403, even if the first timer interrupt processing was started, the various processes of the first timer interrupt processing, such as power outage monitoring, updating of various counters, and fraud monitoring, are executed, but the first timer interrupt processing is terminated without executing any processes to progress the game.

After that, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the work area 221 for specific control (step S9405). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment above. If a value of 1 or greater is set in the checking counter, a check display is displayed on the first to fourth notification display devices 201 to 204, as in the 35th embodiment above.

Then, it is determined whether the value of the checking counter is "0" (step S9406). Then, in step S9406, the system waits until the value of the checking counter becomes "0". As a result, the check display on the first to fourth notification display devices 201 to 204 continues until the initial check period set in step S9405 has elapsed.

Then, steps S9407 to S9426 are executed. The processing content of steps S9407 to S9426 is the same as steps S8806 to S8825 in the main processing (Figure 132) in the 35th embodiment.

With the above configuration, when the supply of operating power to the main CPU 63 begins and the main CPU 63 starts processing at the start of the supply of operating power, a check display is displayed on the first through fourth notification display devices 201 through 204, and the processing at the start of the supply of operating power is halted in this state until the initial check period has elapsed. This makes it possible to prevent setting confirmation and setting value updates from being performed during the initial check period, thereby minimizing an increase in processing load. It also makes it possible to prevent gameplay from starting during the initial check period.

<Thirty-seventh embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 35th embodiment. The configuration that differs from the 35th embodiment will be described below. Note that the description of the same configuration as the 35th embodiment will basically be omitted.

Figure 140 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S9501 to S9525 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Steps S9501 to S9518 are identical to steps S7901 to S7918 of the main processing (Figure 114) in the 33rd embodiment. Then, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step S9519). The value set in the checking counter is decremented by 1 each time the second timer interrupt processing (Figure 134) is initiated, as in the 35th embodiment. If a value of 1 or greater is set in the checking counter, the check display continues on the first to fourth notification display devices 201 to 204, as in the 35th embodiment.

Then, processing from step S9520 onwards is executed. The processing content of steps S9520 to S9525 is the same as steps S7919 to S7924 in the main processing (Figure 114) in the 33rd embodiment described above.

With the above configuration, when the supply of operating power to the main CPU 63 is initiated, the initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps S9501 to S9518) and before the remaining processing (steps S9522 to S9525) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, making it possible to reduce the processing load while the processing at the start of the supply of operating power is being executed.

The setting confirmation process (step S9514) and setting value update process (step S9518) are executed as processes when the supply of operating power starts, whereas the initial check period starts after the processes when the supply of operating power starts finish. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, it does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

When the supply of operating power to the main CPU 63 begins, a check display is displayed on the first to fourth alarm display devices 201-204, regardless of whether the setting confirmation process (step S9514) or the setting value update process (step S9518) is executed, or whether neither the setting confirmation process (step S9514) nor the setting value update process (step S9518) is executed. This makes it possible to check whether the first to fourth alarm display devices 201-204 are operating normally, regardless of the situation when the supply of operating power to the main CPU 63 begins.

The main processing of the master CPU 63 (FIG. 140) is a process that is executed both when either the setting confirmation process (step S9514) or the setting value update process (step S9518) is executed, and when neither the setting confirmation process (step S9514) nor the setting value update process (step S9518) is executed. When either the setting confirmation process (step S9514) or the setting value update process (step S9518) is executed, a process that starts a check display on the first through fourth alarm display devices 201-204 is set as a process that is executed later in the order of execution than the setting confirmation process (step S9514) and the setting value update process (step S9518). By setting the process that starts a check display on the first through fourth alarm display devices 201-204 as a common process in this way, it is possible to achieve the excellent effects already described while simplifying the processing configuration.

The main CPU 63 can start processing to progress the game even when a check display is being executed on the first through fourth notification display devices 201 through 204. This makes it possible to prevent delays in the start of processing to progress the game, even in a configuration in which a check display is executed on the first through fourth notification display devices 201 through 204 after the setting confirmation process (step S9514) or the setting value update process (step S9518) is executed.

It is also possible to configure the system so that processing from step S9520 onwards does not begin until the initial check period has elapsed. In this case, it is possible to prevent game play from starting while check displays are being displayed on the first through fourth notification display devices 201 through 204.

<Thirty-eighth embodiment>
In this embodiment, the processing configuration of the normal setting process executed by the main CPU 63 differs from that of the 35th embodiment. The configuration that differs from the 35th embodiment will be described below. Note that the description of the same configuration as the 35th embodiment will basically be omitted.

Figure 141 is a flowchart showing the normal setting process in this embodiment, which is executed by the main CPU 63. Note that steps S9601 to S9605 in the normal setting process are executed using the specific control program and specific control data in the main CPU 63.

First, it is determined whether the management start flag provided in the non-specific control work area 223 is set to "1" (step S9601). If the management start flag is not set to "1" (step S9601: NO), the check display data is set in the fifth display data buffer 275 in the specific control work area 221 (step S9602). When the check display data is supplied to the display IC 266, the check display is initiated on the first through fourth alert display devices 201-204. Specifically, all display segments 321-324 on each of the first through fourth alert display devices 201-204 are illuminated. This allows the amusement hall manager to determine whether each display segment 321-324 on the first through fourth alert display devices 201-204 is illuminated normally.

If the management start flag is set to "1" (step S9601: YES), steps S9603 to S9605 are executed. The processing content of steps S9603 to S9605 is the same as steps S9107 to S9109 in the normal setting processing (Figure 135) in the 35th embodiment described above. By executing steps S9603 to S9605, the base values stored in the various areas 311 to 314 of the calculation result storage area 234 are sequentially reported on the first to fourth notification display devices 201 to 204, and if the base value in the current status area 311 is reported immediately after the start of a new calculation period, the first and second notification display devices 201 and 202 display the initial calculation value.

With the above configuration, when the management start flag is not set to "1," an initial check period occurs in which a check display is displayed on the first to fourth notification display devices 201-204. This makes it possible to limit the situation in which the initial check period occurs when the supply of operating power to the main CPU 63 begins to a situation in which the management start flag is not set to "1," such as when the pachinko machine 10 is shipped.

<Thirty-ninth embodiment>
In this embodiment, the configuration related to the setting values is different from that of the 33rd embodiment. The configuration that differs from the 33rd embodiment will be described below. Note that the description of the same configuration as the 33rd embodiment will basically be omitted.

Figures 142(a) to 142(d) are explanatory diagrams illustrating the setting correspondence memory area 325 provided in the main ROM 64.

The setting correspondence memory area 325 contains a win/lose table for low probability mode, a win/lose table for high probability mode, and display data for setting values used to display the current setting values on the first to fourth notification display devices 201-204 during the setting confirmation process (Figure 115) and setting value update process (Figure 116), corresponding to the setting values of the pachinko machine 10. More specifically, the setting correspondence memory area 325 includes a first setting information memory area 325a, a second setting information memory area 325b, a third setting information memory area 325c, a fourth setting information memory area 325d, a fifth setting information memory area 325e, and a sixth setting information memory area 325f.

Each of the first through sixth setting information storage areas 325a through 325f includes a storage area for storing a low-probability mode win/fail table that is referenced when the win/fail lottery mode is the low-probability mode, a storage area for storing a high-probability mode win/fail table that is referenced when the win/fail lottery mode is the high-probability mode, and a storage area for storing setting value display data that is used to display the current setting values on the first through fourth notification display devices 201 through 204 during the setting confirmation process (Figure 115) and the setting value update process (Figure 116). In each of the first through sixth setting information storage areas 325a through 325f, a predetermined multi-byte area is reserved as a storage area for storing the low-probability mode win/fail table, a predetermined multi-byte area is reserved as a storage area for storing the high-probability mode win/fail table, and a 1-byte area is reserved as a storage area for storing the setting value display data. Therefore, each of the first to sixth setting information storage areas 325a to 325f has a storage capacity of multiple bytes. In this case, the starting address of the first setting information storage area 325a is A(1), the starting address of the second setting information storage area 325b is A(2), the starting address of the third setting information storage area 325c is A(3), the starting address of the fourth setting information storage area 325d is A(4), the starting address of the fifth setting information storage area 325e is A(5), and the starting address of the sixth setting information storage area 325f is A(6).

In the first form of pachinko machine 10 in this embodiment, the setting values for the pachinko machine 10 are set to six levels, "Setting 1" to "Setting 6," as in the 33rd embodiment. In this case, the probability of a jackpot result in low probability mode differs for each of "Setting 1" to "Setting 6," while the probability of a jackpot result in high probability mode is the same for each of "Setting 1" to "Setting 6." Therefore, as shown in FIG. 142(a), the first setting information storage area 325a stores a first low-probability hit/miss table LT(1) corresponding to "Setting 1" in the storage area for storing the hit/miss table for low probability mode, stores a common high-probability hit/miss table HT common to "Setting 1" to "Setting 6" in the storage area for storing the hit/miss table for high probability mode, and stores display data for displaying "1" in the storage area for storing display data for setting values. In the second setting information storage area 325b, a second low-probability pass/fail table LT (2) corresponding to "Setting 2" is stored in the storage area for storing the pass/fail table for the low-probability mode, a common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the pass/fail table for the high-probability mode, and display data for displaying "2" is stored in the storage area for storing display data for the setting value.

In the third setting information storage area 325c, the third low-probability pass/fail table LT (3) corresponding to "Setting 3" is stored in the storage area for storing the pass/fail table for the low probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the pass/fail table for the high probability mode, and display data for displaying "3" is stored in the storage area for storing display data for setting values. In the fourth setting information storage area 325d, the fourth low-probability pass/fail table LT (4) corresponding to "Setting 4" is stored in the storage area for storing the pass/fail table for the low probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the pass/fail table for the high probability mode, and display data for displaying "4" is stored in the storage area for storing display data for setting values.

In the fifth setting information storage area 325e, the fifth low-probability pass/fail table LT (5) corresponding to "Setting 5" is stored in the storage area for storing the pass/fail table for the low probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the pass/fail table for the high probability mode, and display data for displaying "5" is stored in the storage area for storing display data for setting values. In the sixth setting information storage area 325f, the sixth low-probability pass/fail table LT (6) corresponding to "Setting 6" is stored in the storage area for storing the pass/fail table for the low probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the pass/fail table for the high probability mode, and display data for displaying "6" is stored in the storage area for storing display data for setting values.

In the first configuration described above, the probability of a jackpot result in low probability mode increases with a larger setting value. On the other hand, the probability of a jackpot result in high probability mode is the same regardless of the setting value. Since the probability of a jackpot result in high probability mode is 1/30, the probability of a jackpot result in high probability mode, even with "Setting 1," is higher than the jackpot probability in low probability mode with "Setting 6."

In the first form in which "Setting 1" to "Setting 6" are set as setting values, the process of reading the win/loss table executed in step S503 is described below in order to execute the win/loss determination process in step S504 of the special chart change start process (Figure 13). Figure 143 is a flowchart showing the win/loss table reading process. Note that the processes of steps S9701 to S9705 in the win/loss table reading process are executed using the specific control program and specific control data in the main CPU 63.

First, the value of the setting value counter provided in the specific control work area 221 in the main RAM 65 is read (step S9701). The setting value counter is a counter that allows the main CPU 63 to determine which of the first to sixth setting information storage areas 325a to 325f in the setting correspondence storage area 325 should be referenced when reading the pass/fail table and when reading the setting value display data.

Then, from among the first through sixth setting information storage areas 325a through 325f in the setting correspondence storage area 325, a storage area corresponding to the setting value counter value read in step S9701 is selected (step S9702). The setting value counter is configured to take on a value between "1" and "6," as in the 33rd embodiment. If the setting value counter value is "1," the first setting information storage area 325a is selected; if the setting value counter value is "2," the second setting information storage area 325b is selected; if the setting value counter value is "3," the third setting information storage area 325c is selected; if the setting value counter value is "4," the fourth setting information storage area 325d is selected; if the setting value counter value is "5," the fifth setting information storage area 325e is selected; and if the setting value counter value is "6," the sixth setting information storage area 325f is selected.

When making this selection, a correspondence table pre-stored in the main ROM 64 is referenced. This correspondence table defines the correspondence between the value of the setting value counter and the starting addresses of the first through sixth setting information storage areas 325a through 325f. Specifically, a value of "1" in the setting value counter sets the starting address A(1) of the first setting information storage area 325a, a value of "2" in the setting value counter sets the starting address A(2) of the second setting information storage area 325b, a value of "3" in the setting value counter sets the starting address A(3) of the third setting information storage area 325c, a value of "4" in the setting value counter sets the starting address A(4) of the fourth setting information storage area 325d, a value of "5" in the setting value counter sets the starting address A(5) of the fifth setting information storage area 325e, and a value of "6" in the setting value counter sets the starting address A(6) of the sixth setting information storage area 325f.

Thereafter, if the current win/loss lottery mode is the low probability mode (step S9703: NO), the win/loss table for the low probability mode is read from the setting information storage area 325a-325f selected in step S9702 (step S9704). On the other hand, if the current win/loss lottery mode is the high probability mode (step S9703: YES), the win/loss table for the high probability mode is read from the setting information storage area 325a-325f selected in step S9702 (step S9705).

By executing the win/loss table read process as described above, the win/loss table corresponding to the current win/loss lottery mode is read from the setting information storage area 325a-325f corresponding to the value of the setting value counter. Then, in the win/loss determination process (step S504) of the special chart change start process (Figure 13), the read win/loss table is used to determine whether the current play corresponds to a jackpot result.

Next, we will explain the processing that occurs when the second timer interrupt processing (FIG. 123) interrupts and starts while the setting value update processing (step S7918) is being executed in the main processing (FIG. 114) in the main CPU 63. In this case, the second timer interrupt processing (FIG. 123) executes setting processing for the fifth display data buffer 275 while the setting value is being updated (step S8403). FIG. 144 is a flowchart showing setting processing for the fifth display data buffer 275 while the setting is being updated. Note that the processing of steps S9801 to S9805 in this setting processing is executed using a specific control program and specific control data in the main CPU 63.

First, the value of the setting value counter provided in the specific control work area 221 in the main RAM 65 is read (step S9801). Then, from among the first through sixth setting information storage areas 325a through 325f in the setting correspondence storage area 325, a storage area corresponding to the setting value counter value read in step S9801 is selected (step S9802). As in the 33rd embodiment, the setting value counter is configured to take a value between "1" and "6." If the setting value counter value is "1," the first setting information storage area 325a is selected; if the setting value counter value is "2," the second setting information storage area 325b is selected; if the setting value counter value is "3," the third setting information storage area 325c is selected; if the setting value counter value is "4," the fourth setting information storage area 325d is selected; if the setting value counter value is "5," the fifth setting information storage area 325e is selected; and if the setting value counter value is "6," the sixth setting information storage area 325f is selected. When making this selection, a correspondence table pre-stored in the main ROM 64 is referenced, similar to the win/lose table read process (Figure 143).

Then, display data for the setting values is read from the setting information storage area 325a-325f selected in step S9802 (step S9803). The read display data for the setting values is then set in the fifth display data buffer 275 in the specific control work area 221 as display data to be applied to the fourth alert display device 204 (step S9804). Also, display data for displaying on the first to third alert display devices 201-203 an indication that the setting values of the pachinko machine 10 are being updated is set in the fifth display data buffer 275 (step S9805).

As a result of the setting process for the fifth display data buffer 275 being executed while the settings are being updated as described above, a display corresponding to the display data set in the fifth display data buffer 275 in step S9805 is displayed on the first to third alert display devices 201 to 203, and a display corresponding to the display data set in the fifth display data buffer 275 in step S9804 is displayed on the fourth alert display device 204. As a result, as shown in the explanatory diagram of FIG. 124(a), for example, a display indicating that the setting values of the pachinko machine 10 are being updated and a display showing the current setting values of the pachinko machine 10 are displayed on the first to fourth alert display devices 201 to 204.

In addition, when the second timer interrupt process (FIG. 123) is initiated during the main process (FIG. 114) in the master CPU 63 while the setting confirmation process (step S7914) is being executed, the setting process (step S8405) to the fifth display data buffer 275 during setting confirmation is executed. This process is similar to the setting process (FIG. 144) to the fifth display data buffer 275 during setting update with regard to the setting of the display data for the setting value.

Here, in the pachinko machine 10 of the first form, six setting values, from "Setting 1" to "Setting 6," are set as the setting values for the pachinko machine 10; however, depending on the model and type of pachinko machine 10, fewer setting values than six may be used. Specifically, in the pachinko machine 10 of the second form shown in the explanatory diagram of Figure 142(b), three setting values, "Setting 1," "Setting 3," and "Setting 6," in the pachinko machine 10 of the third form shown in the explanatory diagram of Figure 142(c), four setting values, "Setting 1," "Setting 2," "Setting 3," and "Setting 4," in the pachinko machine 10 of the fourth form shown in the explanatory diagram of Figure 142(d), only one setting value, "Setting 1," is set. In this case, regardless of whether the pachinko machine 10 is of the second to fourth form, the setting correspondence memory area 325, which has first to sixth setting information memory areas 325a to 325f that allow for the setting of six levels of setting values, is used, just like the pachinko machine 10 of the first form.

In more detail regarding the use of the setting correspondence memory area 325 in the second form of pachinko machine 10, as shown in the explanatory diagram of FIG. 142(b), various information corresponding to "Setting 1" is stored in the first setting information memory area 325a and the fourth setting information memory area 325d. In other words, in the first setting information memory area 325a and the fourth setting information memory area 325d, the first low-probability hit/miss table LT(1) corresponding to "Setting 1" is stored in the memory area for storing the hit/miss table for the low probability mode, the first high-probability hit/miss table HT(1) corresponding to "Setting 1" is stored in the memory area for storing the hit/miss table for the high probability mode, and display data for displaying "1" is stored in the memory area for storing display data for setting values.

The second setting information storage area 325b and the fifth setting information storage area 325e store various information corresponding to "Setting 3." That is, in the second setting information storage area 325b and the fifth setting information storage area 325e, the third low-probability pass/fail table LT(3) corresponding to "Setting 3" is stored in the storage area for storing the pass/fail table for the low-probability mode, the third high-probability pass/fail table HT(3) corresponding to "Setting 3" is stored in the storage area for storing the pass/fail table for the high-probability mode, and display data for displaying "3" is stored in the storage area for storing display data for setting values.

The third setting information storage area 325c and the sixth setting information storage area 325f store various information corresponding to "Setting 6." In other words, in the third setting information storage area 325c and the sixth setting information storage area 325f, the sixth low-probability pass/fail table LT(6) corresponding to "Setting 6" is stored in the storage area for storing the pass/fail table for the low-probability mode, the sixth high-probability pass/fail table HT(6) corresponding to "Setting 6" is stored in the storage area for storing the pass/fail table for the high-probability mode, and display data for displaying "6" is stored in the storage area for storing display data for setting values.

In the case of the second configuration described above, even if a setting correspondence memory area 325 having first through sixth setting information memory areas 325a through 325f is used, there are fewer setting values set than the six levels, which is the number of first through sixth setting information memory areas 325a through 325f. The probability of a jackpot result in low probability mode increases with a larger setting value, and the probability of a jackpot result in high probability mode also increases with a larger setting value. The jackpot probability in high probability mode at "Setting 1" is higher than the jackpot probability in low probability mode at "Setting 6."

In the case of the second form of configuration described above, in the process of reading the pass/fail table (Figure 143), the pass/fail table corresponding to "Setting 1" is read whether the value of the setting value counter is "1" or "4", the pass/fail table corresponding to "Setting 3" is read whether the value of the setting value counter is "2" or "5", and the pass/fail table corresponding to "Setting 6" is read whether the value of the setting value counter is "3" or "6".

The process for reading the pass/fail table (Figure 143) is configured to read the pass/fail table from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting value levels. This makes it possible to use the same processing configuration for the process for reading the pass/fail table (Figure 143) as when a six-level setting value is set, even when a three-level setting value is set.

In the second configuration described above, when a setting correspondence memory area 325 capable of setting six setting values is used, three setting values are set, and therefore the number of setting value levels that can be set in the setting correspondence memory area 325 is divisible by the number of setting value levels to be used. In other words, the number of setting value levels to be used is a divisor of the maximum number of setting value levels that can be set in the setting correspondence memory area 325, but is a number different from that maximum number. In this case, the same number of setting information memory areas 325a-325f are assigned to each setting value to be used, and setting values are assigned to the first through sixth setting information memory areas 325a-325f so that when three setting values arranged one by one in ascending order are considered as one group, the group is repeated. As a result, if the reset button 68c is repeatedly operated during the setting value update process (FIG. 116) when the setting value counter value is "1," the setting values displayed on the first to fourth notification display devices 201-204 will change in the following order: "1" → "3" → "6" → "1" → "3" → "6" → "1" → ... In other words, a different setting value will be displayed with each operation of the reset button 68c, and if one display cycle is defined as when all settable setting values are displayed once, a certain number of display cycles will be repeated. This makes it easier to update the setting values.

During the setting process (Fig. 144) for the fifth display data buffer 275 during setting updates, the display data for the setting value is read from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting value stages. This makes it possible to make the processing configuration of the setting process (Fig. 144) the same as when a six-stage setting value is set, even when a three-stage setting value is set.

In addition, in the second form of pachinko machine 10, various information corresponding to "Setting 1" may be stored in the first setting information storage area 325a and the second setting information storage area 325b, various information corresponding to "Setting 3" may be stored in the third setting information storage area 325c and the fourth setting information storage area 325d, and various information corresponding to "Setting 6" may be stored in the fifth setting information storage area 325e and the sixth setting information storage area 325f. In other words, the same number of setting information storage areas 325a to 325f may be assigned to each setting value to be used, and the same setting value may be set in consecutive setting information storage areas 325a to 325f in relation to the value of the setting value counter. In this case, if the reset button 68c is repeatedly operated during the setting value update process (Figure 116) when the value of the setting value counter is "1", the setting values displayed on the first to fourth alarm display devices 201-204 will change in the following order: "1" → "1" → "3" → "3" → "6" → "6" → "1" → ...

In more detail regarding the use of the setting correspondence memory area 325 in the third form of pachinko machine 10, as shown in the explanatory diagram of Figure 142 (c), various information corresponding to "Setting 1" is stored in the first setting information memory area 325a and the second setting information memory area 325b. In other words, in the first setting information memory area 325a and the second setting information memory area 325b, the first low-probability win/loss table LT(1) corresponding to "Setting 1" is stored in the memory area for storing the win/loss table for the low probability mode, the common high-probability win/loss table HT common to "Setting 1" to "Setting 6" is stored in the memory area for storing the win/loss table for the high probability mode, and display data for displaying "1" is stored in the memory area for storing display data for setting values.

The third setting information storage area 325c and the fourth setting information storage area 325d store various information corresponding to "Setting 2." In other words, in the third setting information storage area 325c and the fourth setting information storage area 325d, the second low-probability pass/fail table LT (2) corresponding to "Setting 2" is stored in the storage area for storing the pass/fail table for the low-probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the display data for the setting value, and display data for displaying "2" is stored in the storage area for storing the display data for the setting value.

The fifth setting information storage area 325e stores various information corresponding to "Setting 3." In other words, in the fifth setting information storage area 325e, the third low-probability pass/fail table LT (3) corresponding to "Setting 3" is stored in the storage area for storing the pass/fail table for the low-probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the display data for the setting value, and display data for displaying "3" is stored in the storage area for storing the display data for the setting value.

The sixth setting information storage area 325f stores various information corresponding to "Setting 4." In other words, in the sixth setting information storage area 325f, the fourth low-probability pass/fail table LT (4) corresponding to "Setting 4" is stored in the storage area for storing the pass/fail table for the low-probability mode, the common high-probability pass/fail table HT common to "Setting 1" to "Setting 6" is stored in the storage area for storing the display data for the setting value, and display data for displaying "4" is stored in the storage area for storing the display data for the setting value.

In the case of the third configuration described above, even if a setting correspondence memory area 325 having first through sixth setting information memory areas 325a through 325f is used, fewer setting values are set than the six levels, which is the number of first through sixth setting information memory areas 325a through 325f. The probability of a jackpot result in low probability mode increases with a larger setting value, while the probability of a jackpot result in high probability mode is the same regardless of the setting value. Since the probability of a jackpot result in high probability mode is 1/30, the probability of a jackpot result in high probability mode, even with "Setting 1," is higher than the jackpot probability in low probability mode with "Setting 4."

In the case of the configuration of the third form described above, in the process of reading the pass/fail table (Figure 143), the pass/fail table corresponding to "Setting 1" is read regardless of whether the value of the setting value counter is "1" or "2", the pass/fail table corresponding to "Setting 2" is read regardless of whether the value of the setting value counter is "3" or "4", the pass/fail table corresponding to "Setting 3" is read when the value of the setting value counter is "5", and the pass/fail table corresponding to "Setting 4" is read when the value of the setting value counter is "6".

The process for reading the pass/fail table (Figure 143) is configured to read the pass/fail table from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting value levels. This makes it possible to use the same processing configuration for the process for reading the pass/fail table (Figure 143) as when a six-level setting value is set, even when a four-level setting value is set.

In the configuration of the third embodiment described above, when a setting correspondence memory area 325 capable of setting six setting values is used, four setting values are set, and therefore the number of setting value levels that can be set in the setting correspondence memory area 325 cannot be divided evenly by the number of setting value levels to be used. In this case, two consecutive setting information memory areas 325a-325d are assigned to each of "Setting 1" and "Setting 2" in relation to the value of the setting value counter, and one setting information memory area 325e, 325f is assigned to each of "Setting 3" and "Setting 4." As a result, if the reset button 68c is repeatedly operated during the setting value update process (Figure 116) when the setting value counter value is "1," the setting values displayed on the first through fourth notification display devices 201-204 will change in the following order: "1" → "1" → "2" → "2" → "3" → "4" → "1" → ...

During the setting process (Fig. 144) for the fifth display data buffer 275 during a setting update, the display data for the setting value is read from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting value stages. This makes it possible to make the processing configuration of the setting process (Fig. 144) the same as when a six-stage setting value is set, even when a four-stage setting value is set.

Note that, in order to change the display of the setting values on the first through fourth alarm display devices 201-204 in response to a single operation of the reset button 68c during the setting value update process (Figure 116), it is preferable to ensure that information corresponding to the same setting value is not set in consecutive setting information storage areas 325a-325f in relation to the value of the setting value counter. For example, a possible configuration is to set information corresponding to "Setting 1" in the first setting information storage area 325a, information corresponding to "Setting 2" in the second setting information storage area 325b, information corresponding to "Setting 3" in the third setting information storage area 325c, information corresponding to "Setting 4" in the fourth setting information storage area 325d, information corresponding to "Setting 1" in the fifth setting information storage area 325e, and information corresponding to "Setting 2" in the sixth setting information storage area 325f. In this case, if the reset button 68c is repeatedly operated during the setting value update process (Figure 116) when the value of the setting value counter is "1", the setting values displayed on the first to fourth alarm display devices 201-204 will change in the following order: "1" → "2" → "3" → "4" → "1" → "2" → "1" → ...

In more detail regarding the use of the setting correspondence memory area 325 in the fourth form of pachinko machine 10, as shown in the explanatory diagram of Figure 142 (d), various information corresponding to "Setting 1" is stored in all of the first to sixth setting information memory areas 325a to 325f. In other words, in the first to sixth setting information memory areas 325a to 325f, the first low-probability win/loss table LT(1) corresponding to "Setting 1" is stored in the memory area for storing the win/loss table for the low-probability mode, the common high-probability win/loss table HT common to "Setting 1" to "Setting 6" is stored in the memory area for storing the win/loss table for the high-probability mode, and display data for displaying "1" is stored in the memory area for storing display data for setting values.

In the case of the fourth form configuration described above, even when the configuration uses a setting correspondence memory area 325 having first to sixth setting information memory areas 325a to 325f, only one type of setting value is set. Even when only one type of setting value is set, the process of reading the pass/fail table (Figure 143) reads the pass/fail table from the setting information memory area 325 corresponding to the value of the setting value counter. This makes it possible to use the same processing configuration for the process of reading the pass/fail table (Figure 143) as when six levels of setting values are set, even when only one type of setting value is set.

In the case of the fourth form configuration described above, since there is no need to set a setting value, there is generally no need to execute the setting value update process (Figure 116). However, if an abnormality in the setting value occurs, the setting value update process (Figure 116) may be executed. In this case, "Setting 1" is assigned to all of the first through sixth setting information storage areas 325a through 325f. Therefore, if the reset button 68c is repeatedly operated during the setting value update process (Figure 116) when the setting value counter value is "1," the setting value displayed on the first through fourth alarm display devices 201 through 204 will continue to display "1" as follows: "1" → "1" → "1" → "1" → "1" → "1" → "1" → "1" → ...

During the setting process (Fig. 144) for the fifth display data buffer 275 during setting updates, the display data for the setting value is read from the setting information storage area 325 corresponding to the value of the setting value counter, regardless of the number of setting value stages. This makes it possible to make the processing configuration of the setting process (Fig. 144) the same as when six setting value stages are set, even when only one type of setting value is set.

The present embodiment described above provides the following excellent effects:

Since the setting value to be used is set from multiple levels of setting values corresponding to the player's level of advantage, the player will expect the more advantageous setting value to be used. In this case, in pachinko machines 10 of the second to fourth forms, a first predetermined number (specifically, six) of setting information storage areas 325a to 325f are provided for storing win/lose tables corresponding to the setting values, and the number of types of setting values to be used is fewer than the first predetermined number. This makes it possible to share the configuration of the setting correspondence storage area 325 with the pachinko machine 10 of the first form, in which the number of types of setting values to be used is the first predetermined number, and simplifies the design work for the pachinko machine 10 when changing the number of types of setting values.

During the setting value update process (step S7918), each time the reset button 68c is operated, the numerical information of the setting value counter provided in the specific control work area 221 is changed, thereby changing the setting value to be used. The correct/incorrect table in the setting information storage area 325a-325f corresponding to the changed numerical information is used in the correct/incorrect determination process, thereby executing the correct/incorrect determination process in a manner corresponding to the setting value to be used. In this case, each correct/incorrect table for the setting value that can be set is stored in at least one setting information storage area 325a-325f, and the same correct/incorrect table is stored in multiple setting information storage areas 325a-325f that are part of the first predetermined number. As a result, it is possible to reduce the number of types of setting values to be used to less than the first predetermined number, while still utilizing the first predetermined number of setting information storage areas 325a-325f and the configuration that determines the setting value to be used using the setting value counter.

The system reads a pass/fail table from the setting information storage area 325a-325f corresponding to the numerical information of the setting value counter, and uses that read pass/fail table to execute the pass/fail determination process. This makes it possible to use the same configuration for reading a pass/fail table when executing the pass/fail determination process, even if the number of setting value types to be used is less than the first predetermined number.

When the setting value update process (step S7918) is executed, the display data for the setting value is read from the setting information storage areas 325a-325f corresponding to the numerical information of the setting value counter, and the display corresponding to the read display data for the setting value is performed on the fourth notification display device 204. This makes it possible to use the same configuration for reading display data for the setting value when performing a display corresponding to the setting value, even if the number of types of setting values to be used is less than the first predetermined number.

The number of levels of the setting value to be used is a divisor of the maximum number of levels of setting values that can be set in the setting correspondence memory area 325, but is different from that maximum number of levels. In this case, the same number of setting information memory areas 325a-325f are assigned to each setting value to be used, and setting values are assigned to the first through sixth setting information memory areas 325a-325f so that when three setting values arranged one by one in ascending order are considered as one group, the group is repeated. As a result, if the reset button 68c is repeatedly operated during the setting value update process (Figure 116) when the setting value counter value is "1," the setting values displayed on the first through fourth alarm display devices 201-204 will change in the following order: "1" → "3" → "6" → "1" → "3" → "6" → "1" → ... In other words, each time the reset button 68c is pressed, a different setting value is displayed, and if one display cycle is defined as when each of the settable setting values is displayed once, then a certain number of display cycles will be repeated. This makes it easier to update the setting values.

In addition, in a configuration in which the high probability mode win/loss table does not change according to the setting value, the high probability mode win/loss table may be stored in a memory area different from the setting correspondence memory area 325 in the main ROM 64, rather than being stored in the first to sixth setting information memory areas 325a to 325f of the setting correspondence memory area 325.

Also, if there is only one setting value to be used, the pass/fail table corresponding to that setting value may be set in only one setting information storage area 325a-325f, and no pass/fail tables may be set in the remaining setting information storage areas 325a-325f. Also, if there are multiple levels of setting values to be used but the number of levels is fewer than the number of first through sixth setting information storage areas 325a-325f, the pass/fail table corresponding to each setting value may be set in only one corresponding setting information storage area 325a-325f, and no pass/fail tables may be set in the remaining setting information storage areas 325a-325f. In this configuration, by making the numerical information corresponding to setting information storage areas 325a-325 that do not have a pass/fail table set numerical information that cannot be selected by the setting value counter, it is possible to prevent setting information storage areas 325a-325f that do not have a pass/fail table set from being selected when reading out the pass/fail table or reading out the setting value display data.

<Fortieth Embodiment>
In the above-mentioned 39th embodiment, a setting correspondence memory area 325 capable of setting six levels of setting values is used, but in this embodiment, a setting correspondence memory area 326 capable of setting three levels of setting values is used.

Figures 145(a) to 145(c) are explanatory diagrams illustrating the setting correspondence memory area 326 pre-stored in the main ROM 64.

The setting correspondence memory area 326 is provided with a first setting information memory area 326a, a second setting information memory area 326b, and a third setting information memory area 326c. In the first form of pachinko machine 10 shown in FIG. 145(a), various information corresponding to "Setting 1" is set in the first setting information memory area 326a, various information corresponding to "Setting 2" is set in the second setting information memory area 326b, and various information corresponding to "Setting 3" is set in the third setting information memory area 326c. In other words, in the first form of pachinko machine 10, the maximum number of setting values that can be set is set in the setting correspondence memory area 326.

In the pachinko machine 10 of the second form shown in Figure 145 (b), various information corresponding to "Setting 1" is set in all of the first to third setting information storage areas 326a to 326c. In other words, in the pachinko machine 10 of the second form, only one type of setting value is set using the setting correspondence storage area 326, which can be set to three levels of setting values.

In the third form of pachinko machine 10 shown in Figure 145 (c), various information corresponding to "Setting 1" is set in the first setting information storage area 326a and the second setting information storage area 326b, and various information corresponding to "Setting 3" is set in the third setting information storage area 326c. In other words, in the third form of pachinko machine 10, two levels of setting values are set using the setting correspondence storage area 326, which can set three levels of setting values.

With the above configuration, the setting corresponding memory area 326, which can be set to three levels of setting values, can be used as is for the second and third form pachinko machines 10, which use setting values with fewer levels than three. Furthermore, as with the 39th embodiment, the processing configuration for reading the win/lose table (Figure 143) and the processing configuration for setting the fifth display data buffer 275 during setting updates (Figure 144) can be used in common for the first to third form pachinko machines 10.

<Forty-first embodiment>
This embodiment differs from the 33rd embodiment in that when the setting confirmation process (step S7914) or the setting value update process (step S7918) is being executed in the main process (FIG. 114) in the master CPU 63, a predetermined notification is executed on a display unit that is visible from the front side of the pachinko machine 10. Below, the configurations that differ from the 33rd embodiment will be explained. Note that explanations of the same configurations as the 33rd embodiment will basically be omitted.

Figure 146 (a) is an explanatory diagram illustrating various display units provided in an area that is visible from the front of the pachinko machine 10 through the window panel 52 that defines the front surface of the pachinko machine 10.

Various display units are provided, including a special map display unit 37a, a special map reserved display unit 37b, a regular map display unit 38a, and a regular map reserved display unit 38b. These functions are the same as those in the first embodiment. The special map display unit 37a and the regular map display unit 38a are arranged side by side, and a round display unit 330 is arranged side by side with the special map display unit 37a and the regular map display unit 38a.

The round display section 330, like the special display section 37a and the regular display section 38a, has seven display segments 331-337. All seven display segments 331-337 are rod-shaped light-emitting areas of the same shape and size, and are arranged to form the number "8." The illumination of the seven display segments 331-337 is individually controlled.

The round display unit 330 notifies the player of the number of rounds that will occur in the open/close execution mode triggered by a jackpot result. In this embodiment, the jackpot results that can be selected when a jackpot is won in the win/loss determination process include a first jackpot result that triggers a transition to the open/close execution mode, in which the number of rounds is relatively small, and a second jackpot result that triggers a transition to the open/close execution mode, in which the number of rounds is relatively large. Specifically, in the open/close execution mode triggered by the first jackpot result, two rounds are played, and in the open/close execution mode triggered by the second jackpot result, 16 rounds are played.

The first jackpot result includes a jackpot result in which the win/loss lottery mode becomes a low probability mode and the support mode becomes a low frequency support mode after the opening/closing execution mode has ended, and a jackpot result in which the win/loss lottery mode becomes a high probability mode and the support mode becomes a high frequency support mode after the opening/closing execution mode has ended. The second jackpot result includes a jackpot result in which the win/loss lottery mode becomes a low probability mode and the support mode becomes a low frequency support mode after the opening/closing execution mode has ended, and a jackpot result in which the win/loss lottery mode becomes a high probability mode and the support mode becomes a high frequency support mode after the opening/closing execution mode has ended.

Figure 146 (b) is an explanatory diagram illustrating the display content of the round display section 330.

When the opening and closing execution mode is initiated in response to a jackpot result, the round display unit 330 changes from a non-display state in which all display segments 331-337 are unlit to a display state in which at least some of the display segments 331-337 are illuminated. While the opening and closing execution mode continues, the display content displayed on the round display unit 330 at the start of the opening and closing execution mode is maintained. Then, when the opening and closing execution mode ends, the round display unit 330 changes from a display state to a non-display state.

In the open/close execution mode, in which two rounds of play are executed, the first to fourth display segments 331 to 334 of the round display unit 330 are turned off, and the fifth to seventh display segments 335 to 337 are turned on, as shown in FIG. 146(b). In the open/close execution mode, in which 16 rounds of play are executed, the first to fourth display segments 331 to 334 of the round display unit 330 are turned on, and the fifth to seventh display segments 335 to 337 are turned off, as shown in FIG. 146(b). This allows the gaming hall manager to check the round display unit 330 when the open/close execution mode is being executed on the pachinko machine 10 and determine which type of open/close execution mode that mode corresponds to.

When the setting value update process (step S7918) is being executed during the main processing (Figure 114) in the master CPU 63, a corresponding display is made on the round display unit 330. Specifically, when the setting value update process (step S7918) is being executed, as shown in Figure 146 (b), the first display segment 331, third display segment 333, fifth display segment 335, and seventh display segment 337 of the round display unit 330 are turned off, and the second display segment 332, fourth display segment 334, and sixth display segment 336 are turned on.

The display on the round display unit 330 corresponding to the setting value update process (step S7918) begins when the setting value update process (step S7918) is initiated, and ends when the setting value update process (step S7918) is terminated. This display content differs from the display content displayed on the round display unit 330 when the open/close execution mode is executed, and also differs from the display content displayed on the round display unit 330 when the setting confirmation process (step S7914), described below, is executed. This allows the amusement hall manager to easily determine whether the setting value update process (step S7918) is being executed by checking the round display unit 330. This determination can also be made using the round display unit 330.

When the setting confirmation process (step S7914) is being executed during the main processing (Figure 114) in the master CPU 63, a corresponding display is made on the round display unit 330. Specifically, when the setting confirmation process (step S7914) is being executed, as shown in Figure 146 (b), the first display segment 331, third display segment 333, fifth display segment 335, and seventh display segment 337 of the round display unit 330 are lit, and the second display segment 332, fourth display segment 334, and sixth display segment 336 are unlit.

The display on the round display unit 330 corresponding to the setting confirmation process (step S7914) begins when the setting confirmation process (step S7914) is initiated, and ends when the setting confirmation process (step S7914) ends. This display content differs from the display content displayed on the round display unit 330 when the open/close execution mode is executed, and also differs from the display content displayed on the round display unit 330 when the setting value update process (step S7918) is executed. This allows the amusement hall manager to easily determine whether the setting confirmation process (step S7914) is being executed by checking the round display unit 330. This determination can also be made using the round display unit 330.

When the setting confirmation process (step S7914) and the setting value update process (step S7918) are executed in the main process (Figure 114), no processing is executed to progress the game. Therefore, when the open/close execution mode is being executed, the setting confirmation process (step S7914) and the setting value update process (step S7918) are not executed. Furthermore, when one of the setting confirmation process (step S7914) and the setting value update process (step S7918) is being executed, the other is not executed. Therefore, even if the round display unit 330 is used as a display unit for both displays, there will be no overlapping situations in which each display should be executed.

The display content of the round display unit 330 is not limited to the above, and can be any as long as it is possible to distinguish each situation from the display content of the round display unit 330. For example, one of the display corresponding to the setting confirmation process (step S7914) and the setting value update process (step S7918) may be configured so that all of the first to seventh display segments 331 to 337 are lit. Also, one of the display corresponding to the setting confirmation process (step S7914) and the setting value update process (step S7918) may be configured so that all of the first to seventh display segments 331 to 337 are lit and maintained in that state, and the other may be configured so that all of the first to seventh display segments 331 to 337 are flashing.

In addition, instead of a configuration in which the round display unit 330 displays the display corresponding to the setting confirmation process and the display corresponding to the setting value update process, these displays may be made on the special map display unit 37a, or on the regular map display unit 38a. Alternatively, a configuration may be adopted in which a display corresponding to the setting confirmation process is made on one of the special map display unit 37a, regular map display unit 38a, and round display unit 330, and a display corresponding to the setting value update process is made on the other display unit.

In addition, in a configuration in which the reserved information acquired based on the game ball entering the first actuation port 33 and the reserved information acquired based on the game ball entering the second actuation port 34 are stored separately, and the special symbol display unit 37a is provided with a first special symbol display unit in which a game round is executed triggered by the reserved information corresponding to the first actuation port 33, and a second special symbol display unit in which a game round is executed triggered by the reserved information corresponding to the second actuation port 34, the first special symbol display unit may be configured to display a display corresponding to the setting confirmation process and a display corresponding to the setting value update process, or the second special symbol display unit may be configured to display a display corresponding to the setting confirmation process and a display corresponding to the setting value update process, or the first special symbol display unit may be configured to display a display corresponding to the setting confirmation process and the second special symbol display unit may be configured to display a display corresponding to the setting value update process.

Alternatively, a dedicated display unit may be provided for displaying that the setting confirmation process is being executed, or a dedicated display unit may be provided for displaying that the setting value update process is being executed, or a dedicated display unit may be provided for displaying that the setting confirmation process is being executed or that the setting value update process is being executed. In this case, the display of the dedicated display unit may be controlled by the main CPU 63, or the display may be controlled by the audio and light emission control device 81 or the display control device 82.

<Forty-second embodiment>
In this embodiment, the processing configurations of the main processing and the first timer interrupt processing are different from those of the 33rd embodiment. The configurations that differ from the 33rd embodiment will be described below. Note that the description of the configurations that are the same as those of the 33rd embodiment will basically be omitted.

Figure 147 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps S9901 to S9923 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, the power-on initialization process is executed (step S9901). During the power-on initialization process, for example, the main process is started and then a predetermined waiting time (specifically, one second) passes before proceeding to the next process. During this predetermined waiting period, the operation of the pattern display device 41 is started and the initial settings are completed. In addition, access to the main RAM 65 is permitted.

Then, internal function register setting processing is executed (step S9902). In the internal function register setting processing, similar to step S7902 of the main processing (FIG. 114) in the 33rd embodiment, the interrupt period of the first timer interrupt processing (FIG. 148), which is processing that periodically interrupts the main processing and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt processing (FIG. 123), which is processing that periodically interrupts the main processing and is started, is set to a second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

Then, interrupt permission is set for the second timer interrupt process (Figure 123) (step S9903). As a result, the second timer interrupt process (Figure 123) is started by interrupting at the second interrupt period. On the other hand, interrupt permission is not set for the first timer interrupt process (Figure 148). As a result, the first timer interrupt process (Figure 148) remains in an interrupt-disabled state.

Then, steps S9904 to S9917 are executed. The processing content of steps S9904 to S9917 is the same as steps S7905 to S7918 in the main processing (Figure 114) in the 33rd embodiment.

After steps S9904 to S9917 are completed, interrupt permission is set for the first timer interrupt process (Fig. 148) (step S9918). This causes the first timer interrupt process (Fig. 148) to be started at the first interrupt period. In other words, the first timer interrupt process (Fig. 117) is started at the first interrupt period, and the second timer interrupt process (Fig. 123) is started at the second interrupt period. Thereafter, steps S9919 to S9923 execute the same processing as steps S7920 to S7924 of the main process (Fig. 114) in the 33rd embodiment.

Figure 148 is a flowchart showing the first timer interrupt processing in this embodiment, which is executed by the main CPU 63. As already explained, the first timer interrupt processing is periodically started at a 4-millisecond cycle, which is the first interrupt cycle. The program corresponding to the first timer interrupt processing is set in the program for specific control.

First, interrupt prohibition is set to prohibit the occurrence of the first timer interrupt processing (FIG. 148) and the second timer interrupt processing (FIG. 123) (step SA101). By prohibiting the occurrence of the first timer interrupt processing (FIG. 148), it is possible to prevent the first timer interrupt processing (FIG. 148) from being started redundantly even if the first interrupt period has elapsed during the execution of the first timer interrupt processing (FIG. 148). Furthermore, by prohibiting the occurrence of the second timer interrupt processing (FIG. 123), it is possible to prevent the second timer interrupt processing (FIG. 123) from interrupting the first timer interrupt processing (FIG. 148) and starting it, even if the second interrupt period has elapsed.

Then, steps SA102 to SA121 execute the same processing as steps S8202 to S8221 of the first timer interrupt processing (FIG. 117) in the 33rd embodiment described above. If a positive determination is made in step SA107, or if the processing of step SA121 is executed, interrupt permission is set (step SA122) to allow the first timer interrupt processing (FIG. 148) and second timer interrupt processing (FIG. 123) to occur.

With the above configuration, when processing is being executed in the main processing (FIG. 147) at the start of the supply of operating power, an interrupt by the second timer interrupt processing (FIG. 123) is permitted, but an interrupt by the first timer interrupt processing (FIG. 148) is not permitted. This makes it possible to execute display control of the first to fourth notification display devices 201-204 by the second timer interrupt processing (FIG. 123) even when processing is being executed at the start of the supply of operating power, while preventing the execution of processing to control the progress of the game by the first timer interrupt processing (FIG. 148).

In addition, the first timer interrupt process (Fig. 148) does not interrupt the second timer interrupt process (Fig. 123) and start, and the second timer interrupt process (Fig. 123) does not interrupt the first timer interrupt process (Fig. 148) and start. This makes it possible to prevent duplicate timer interrupt processes from being started.

<Forty-third embodiment>
In this embodiment, the configuration for displaying the base value on the first to fourth notification display devices 201 to 204 differs from that of the thirty-fifth embodiment. The following describes the configuration that differs from the thirty-fifth embodiment. Note that the description of the same configuration as the thirty-fifth embodiment will basically be omitted.

In this embodiment, as in the 35th embodiment, the non-specific control work area 223 is provided with a normal counter area 231. As in the 15th embodiment, the normal counter area 231 is provided with a normal general winning counter 231a, a normal special winning counter 231b, a normal first operation counter 231c, a normal second operation counter 231d, and a normal out counter 231e. In a situation that is neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode, when one game ball enters the general winning port 31, the value of the normal general winning counter 231a is incremented by 1, when one game ball enters the special electric winning device 32, the value of the normal special electric winning counter 231b is incremented by 1, when one game ball enters the first operating port 33, the value of the normal first operating counter 231c is incremented by 1, when one game ball enters the second operating port 34, the value of the normal second operating counter 231d is incremented by 1, and when one game ball enters the outlet port 24a, the value of the normal out counter 231e is incremented by 1. Then, when the values of the various counters 231a to 231e in the normal counter area 231 in a situation that is neither the opening/closing execution mode due to a jackpot result nor the high-frequency support mode are K91 to K95, the base values are as follows.
Base value: The ratio of the total number of game balls paid out (K91 x "number of prize balls for winning at the general winning port 31" + K92 x "number of prize balls for winning at the special electric winning device 32" + K93 x "number of prize balls for winning at the first operating port 33" + K94 x "number of prize balls for winning at the second operating port 34") to the total number of game balls discharged from the game area PA (K91 + K92 + K93 + K94 + K95).

In addition to the normal counter area 231, the non-specific control work area 223 also has a calculation result storage area 234. As in the 35th embodiment, the calculation result storage area 234 has a current status area 311, a first history area 312, a second history area 313, and a third history area 314 as storage areas for storing base value information (see Figure 126). The current status area 311 stores the most recent base value calculated in the result calculation process (Figure 149). The first history area 312 stores the final base value for the calculation period one period before. The second history area 313 stores the final base value for the calculation period two periods before. The third history area 314 stores the final base value for the calculation period three periods before.

Figure 149 is a flowchart showing the result calculation process in this embodiment, which is executed by the main CPU 63. Note that in the management process (step S8920) of the first timer interrupt process (Figure 133), a program for the management execution process, which is a process corresponding to non-specific control, is read out in step S3803, similar to the management process (Figure 70) in the 15th embodiment. Then, in this management execution process (Figure 71), a check process is executed in step S3908, similar to the 15th embodiment. In this check process, the result calculation process is executed, and the display process (Figure 150), described below, is also executed. Furthermore, the processes of steps SA201 to SA217 in the result calculation process are executed using the program for non-specific control and data for non-specific control in the main CPU 63.

First, a base value calculation process is performed (step SA201). In this calculation process, the base value is calculated using the values of the various counters 231a to 231e in the normal counter area 231, as in the 35th embodiment. In this embodiment, the calculation of the base value is not completed in a single processing run of the result calculation process, but is completed by performing the result calculation process a predetermined number of times.

Specifically, in a predetermined processing round of the result calculation process in which a new calculation of the base value is started, in step SA201, if the values of the various counters 231a to 231e in the normal counter area 231 are K91 to K95, K91 x "number of prize balls for winning at the general winning port 31", K92 x "number of prize balls for winning at the special electric winning device 32", K93 x "number of prize balls for winning at the first operating port 33", K94 x "number of prize balls for winning at the second operating port 34", and the total number of game balls discharged from the skill area PA (K91 + K92 + K93 + K94 + K95) are calculated, and each of these calculation results is stored in a calculation memory area provided in the work area 223 for non-specific control. Then, in step SA201 of the result calculation process for the processing cycle one cycle after the predetermined processing cycle, the various information stored in the calculation memory area is used to calculate the total number of game balls to be paid out (K91 x "number of prize balls for winning at the general winning port 31" + K92 x "number of prize balls for winning at the special electric winning device 32" + K93 x "number of prize balls for winning at the first operating port 33" + K94 x "number of prize balls for winning at the second operating port 34"), and the calculation result is stored in the calculation memory area. Then, in step SA201 of the result calculation process for the processing cycle two cycles after the predetermined processing cycle, the various information stored in the calculation memory area is used to calculate the base value.

In other words, in this embodiment, the result calculation process must be executed three times to calculate one base value. In this case, the result calculation process is called and executed by the first timer interrupt process (Figure 133), so it is executed every time the first interrupt period (specifically, 4 milliseconds) has elapsed. Therefore, one base value is calculated at approximately 12 millisecond intervals. However, this is not limited to this, and the period for calculating one base value may be shorter or longer than 12 millisecond intervals.

As described above, by configuring the result calculation process to be performed multiple times to calculate a single base value, it is possible to reduce the processing load required to calculate the base value. In particular, because the result calculation process is performed as a process corresponding to non-specific control, executing the result calculation process not only requires reading the program and data for non-specific control, but also saving information from the various registers of the main CPU 63 that was used in the process corresponding to specific control. In this case, reducing the processing load required to calculate the base value makes it possible to reduce the processing load required to perform the result calculation process, which in turn reduces the processing load required to execute the process corresponding to non-specific control.

Even in a configuration in which the result calculation process is performed multiple times to calculate a single base value, each piece of information during the calculation of the base value in each result calculation process is written to the work area 223 for non-specific control. This makes it possible to store and retain each piece of information during the calculation of the base value, even if the information in the various registers of the main CPU 63 used in the processing corresponding to non-specific control is erased as processing corresponding to specific control is performed between one processing run of the result calculation process and the next.

Even in a configuration in which the result calculation process is executed multiple times to calculate a single base value, the values of all counters 231a-231e in the normal counter area 231 are extracted in the first result calculation process to calculate a new base value, and the extracted values are used to calculate the base value for that calculation. This makes it possible to calculate a single base value without being affected by the change in values, even if the values of the counters 231a-231e in the normal counter area 231 are changed while the single base value is being calculated.

After the base value calculation process is performed in step SA201, it is determined whether the calculation of one base value has been completed in the result calculation process for this processing round (step SA202). If the calculation of one base value has not been completed (step SA202: NO), the processes of steps SA203 to SA205 are not performed, and the base value is not overwritten in the current area 311 of the calculation result storage area 234.

If calculation of a base value has been completed (step SA202: YES), the calculated base value is overwritten in the current state area 311 (step SA203). Then, it is determined whether the shift trigger flag provided in the non-specific control work area 223 is set to "1" (step SA204). In this embodiment, if the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000) in a situation other than the jackpot result opening/closing execution mode or the high-frequency support mode, and calculation of a new base value is completed, data shift processing (step SA216) is executed in the calculation result storage area 234. In this data shift process, the information stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, current status area 311 → first history area 312, and then the current status area 311 is cleared to "0." The shift trigger flag is a flag that allows the main CPU 63 to identify the situation after the total number of gaming balls has reached the shift reference number and before the data shift process is executed.

If the shift trigger flag is set to "1" (step SA204: YES), the shift calculation completion flag provided in the non-specific control work area 223 is set to "1" (step SA205). The shift calculation completion flag is a flag that the main CPU 63 uses to determine that calculation of one base value has been completed after the total number of game balls has reached the shift reference number.

If a negative determination is made in step SA202, if a negative determination is made in step SA204, or if the processing of step SA205 is executed, it is determined whether the management start flag provided in the non-specific control work area 223 is set to "1" (step SA206). If the management start flag is not set to "1" (step SA206: NO), pre-management start processing is executed (step SA207). In the pre-management start processing, the processing of steps S8604 to S8608 of the result calculation processing (Figure 130) in the 35th embodiment described above is executed.

If the management start flag is set to "1" (step SA206: YES), it is determined whether the shift trigger flag in the non-specific control work area 223 is set to "1" (step SA208). If the shift trigger flag is not set to "1" (step SA208: NO), the total number is calculated by adding up all the values of the various counters 231a to 231e in the normal counter area 231 (step SA209). It is then determined whether the calculated total number is equal to or greater than the shift reference number of 60,000 (step SA210).

If a positive determination is made in step SA210, the shift trigger flag in the non-specific control work area 223 is set to "1" (step SA211). The pre-shift display flag provided in the non-specific control work area 223 is also set to "1" (step SA212). The pre-shift display flag is a flag that the main CPU 63 uses to identify a situation in which the first to fourth notification display devices 201-204 should start a pre-shift display corresponding to the total number of game balls reaching the shift reference number.

If the shift trigger flag is set to "1" and a positive determination is made in step SA208, it is determined whether the shift calculation completion flag in the non-specific control work area 223 is set to "1" (step SA213). As already explained, the shift calculation completion flag is set to "1" when calculation of one base value is completed after the total number of game balls reaches the shift reference number. If a positive determination is made in step SA213, the shift trigger flag in the non-specific control work area 223 is cleared to "0" (step SA214). In addition, the shift calculation completion flag in the non-specific control work area 223 is cleared to "0" (step SA215).

Then, data shift processing is executed (step SA216). In the data shift processing, the information stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 is shifted in the following order: second history area 313 → third history area 314, first history area 312 → second history area 313, and current status area 311 → first history area 312. The current status area 311 is then cleared to "0." As a result, the final base value for the calculation period two times prior is stored in the third history area 314 as the final base value for the calculation period three times prior; the final base value for the calculation period one time prior is stored in the second history area 313 as the final base value for the calculation period two times prior; and the base value calculated after the total number of game balls in the current calculation period reaches the shift reference number is stored in the first history area 312 as the final base value for the calculation period one time prior. Additionally, no base value is stored in the current area 311. When shifting information as described above in the data shift process, the LDIR command is used. The LDIR command specifies the address of the source area where the information is to be stored and the address of the destination area where the information is to be stored, and the information stored in the source area is shifted (copied) to the destination area. Then, all counters 231a-231e in the normal counter area 231 are cleared to "0" (step SA217).

Figure 150 is a flowchart showing the display processing in this embodiment, which is executed by the main CPU 63. Note that steps SA301 to SA320 in the display processing are executed using the non-specific control program and non-specific control data in the main CPU 63.

First, it is determined whether the management start flag in the non-specific control work area 223 is set to "1" (step SA301). If the determination in step SA301 is negative, similar to step S8714 of the display processing (FIG. 131) in the 35th embodiment described above, the base value is read from the current status area 311, and calculation result data corresponding to the digits in the first and second decimal places of the read base value is set in the display target setting area 276 (step SA302). When display data corresponding to the calculation result data is transmitted to the display IC 266, the digit in the first decimal place of the base value in the current status area 311 is displayed on the third alarm display device 203, and the digit in the second decimal place of the base value in the current status area 311 is displayed on the fourth alarm display device 204. With the above configuration, when the management start flag is not set to "1," base values from past calculation periods are not reported, and only the base value calculated for the current calculation period is reported. Note that when the base value is notified when the management start flag is not set to "1," the display contents of the first to fourth notification display devices 201 to 204 are the same as those in the 35th embodiment.

If a positive determination is made in step SA301, the value of the switching timing counter provided in the non-specific control work area 223 is decremented by 1 (step SA303). The switching timing counter is a counter that allows the main CPU 63 to determine the timing for switching the display content of the first to fourth alarm display devices 201-204 when the first to fourth alarm display devices 201-204 are displaying information related to the base value.

In this embodiment, when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) does not reach the shift reference number when neither the jackpot result opening/closing execution mode nor the high-frequency support mode is active, the base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 are displayed for a display duration (specifically, 5 seconds), and an interval non-display is performed for an interval period (specifically, 1 second) between the base value displays to notify the player that a change in the base value to be notified will occur. Specifically, the interval non-display is performed by turning off all display segments 321-324 in each of the first through fourth notification display devices 201-204, thereby turning the first through fourth notification display devices 201-204 into a non-display state. By hiding the interval display before the base value to be notified is switched in the predetermined order of current area 311 → first history area 312 → second history area 313 → third history area 314, it is possible to make the amusement hall manager clearly aware that the base value to be notified is being switched.

When the total number of gaming balls reaches the shift reference number, the first through fourth alert display devices 201-204 display the corresponding pre-shift display. Specifically, the pre-shift display displays "A." on each of the first through fourth alert display devices 201-204. The "A." display content is not displayed on the first through fourth alert display devices 201-204 during either the display duration of the display corresponding to the base value or the interval period during which the interval display is not displayed. This allows the overall display content of the first through fourth alert display devices 201-204 in a situation where the pre-shift display is displayed to be different from the display duration of the display corresponding to the base value or the interval period during which the interval display is not displayed. Therefore, by confirming that the pre-shift display is being displayed on the first through fourth alert display devices 201-204, the amusement hall manager can understand that the total number of gaming balls has reached the shift reference number, and a shift of the base value will be performed.

The contents of the pre-shift display differ from the contents displayed on the first to fourth alert display devices 201-204 when a check display is being displayed, the contents displayed on the first to fourth alert display devices 201-204 when the pre-management flag is not set to "1", the contents displayed on the first to fourth alert display devices 201-204 when the setting confirmation process (Figure 136) is being executed, and the contents displayed on the first to fourth alert display devices 201-204 when the setting value update process (Figure 137) is being executed. For this reason, by confirming that the pre-shift display is being displayed on the first to fourth alert display devices 201-204, the amusement hall manager can understand that the total number of game balls has reached the shift reference number, and that a base value shift will be performed.

The execution period of the pre-shift display is set to a period longer than the interval period (specifically, 1 second) during which the interval display is hidden. The execution period of the pre-shift display is also set to a period longer than the display duration of the display corresponding to the base value (specifically, 5 seconds). Specifically, the execution period of the pre-shift display is set to 8 seconds. However, this is not limited to this, and the execution period of the pre-shift display may be longer than the interval period but shorter than the display duration of the display corresponding to the base value, or may be shorter than the interval period. However, to ensure that the amusement hall manager is clearly aware that the pre-shift display is being displayed, it is preferable that the execution period of the pre-shift display be set to a period longer than the interval period.

As already explained, the result calculation process (Figure 149) must be executed multiple times to complete the calculation of one base value. Specifically, the calculation cycle for one base value is 12 milliseconds. Furthermore, the data shift process (step SA216), in which base value information is shifted between the various areas 311-314 of the calculation result storage area 234 when the total number of gaming balls reaches the shift reference number, is executed after a new base value is calculated after the shift reference number is reached. In this case, the execution period for the pre-shift display is set to a period longer than the longest period required for the data shift process (step SA216) to be completed when the total number of gaming balls reaches the shift reference number. This makes it possible to complete the new calculation of one base value and the base value data shift process (step SA216) while the pre-shift display is being displayed on the first through fourth notification display devices 201-204.

Returning to the explanation of the display processing (FIG. 150), when the processing of step SA303 is executed, it is determined whether the value of the switching timing counter after subtracting 1 is "0" to determine whether the currently measured period among the base value display duration, the interval period during which interval non-display is performed, and the execution period of the pre-shift display has elapsed (step SA304). If a positive determination is made in step SA304, it is determined whether a situation exists where pre-shift display should be started by determining whether a pre-shift display flag in the work area 223 for non-specific control is set to "1" (step SA305). If a negative determination is made in step SA305, it is determined whether a "1" is set to the interval flag provided in the work area 223 for non-specific control (step SA306). The interval flag is a flag that allows the main CPU 63 to determine whether a situation exists where interval non-display should be started.

If the determination in step SA306 is negative, it means that the base value is the target for which notification should be initiated at the current switching timing on the first to fourth notification display devices 201 to 204. In this case, the value of the display target counter provided in the non-specific control work area 223 is incremented by 1 (step SA307). Then, if the value of the display target counter after incrementing by 1 exceeds the maximum value of "3" (step SA308: YES), the value of the display target counter is cleared to "0" (step SA309).

The display target counter is a counter that allows the main CPU 63 to identify the base value to be notified on the first to fourth notification display devices 201-204 from among the base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234. Specifically, if the value of the display target counter is "0," the base value stored in the current status area 311 is the base value to be notified; if the value of the display target counter is "1," the base value stored in the first history area 312 is the base value to be notified; if the value of the display target counter is "2," the base value stored in the second history area 313 is the base value to be notified; and if the value of the display target counter is "3," the base value stored in the third history area 314 is the base value to be notified.

If a negative judgment is made in step SA308, or if the processing of step SA309 is executed, a value corresponding to the display duration (specifically, 5 seconds) for displaying the base value is set as the value corresponding to the next switching timing in the switching timing counter in the non-specific control work area 223 (step SA310). Then, the interval flag in the non-specific control work area 223 is set to "1" (step SA311). As a result, if the pre-shift display flag in the non-specific control work area 223 has not been set to "1" by the time the next switching timing arrives, interval display will be hidden when the next switching timing arrives.

Then, processing is performed to set display data corresponding to the base value that is the target of the current notification in the display target setting area 276 provided in the work area 223 for non-specific control. Specifically, similar to step S8708 of the display processing (FIG. 131) in the 35th embodiment above, display type data corresponding to the value of the display target counter is set in the display target setting area 276 (step SA312). The display type data includes display data for causing the first notification display device 201 to display an indication that the notification target of the first to fourth notification display devices 201 to 204 is the base value, and display data for causing the second notification display device 202 to display an indication of which of the current status area 311, first history area 312, second history area 313, or third history area 314 in the calculation result storage area 234 the base value of the notification target corresponds to.

Then, similar to step S8709 of the display process (FIG. 131) in the 35th embodiment, a base value is read from the area in the calculation result storage area 234 that corresponds to the value of the counter to be displayed—the current status area 311, the first history area 312, the second history area 313, or the third history area 314—and calculation result data corresponding to the digits to the first and second decimal places of the read base value is set in the display target setting area 276 (step SA313). The calculation result data includes display data for causing the third alarm display device 203 to display a number corresponding to the digit to the first decimal place of the base value to be notified, and display data for causing the fourth alarm display device 204 to display a number corresponding to the digit to the second decimal place of the base value to be notified.

When display data consisting of display type data and calculation result data is set in the display target setting area 276, the display data is sent to the display IC 266 by the second timer interrupt processing (Figure 134), as in the 35th embodiment above, and a display corresponding to the display data is made on the first to fourth alarm display devices 201 to 204. In other words, when the base value in the current status area 311 is the subject of notification, a display such as that shown in FIG. 127(a) is displayed on the first to fourth notification display devices 201 to 204, when the base value in the first history area 312 is the subject of notification, a display such as that shown in FIG. 127(b) is displayed on the first to fourth notification display devices 201 to 204, when the base value in the second history area 313 is the subject of notification, a display such as that shown in FIG. 127(c) is displayed on the first to fourth notification display devices 201 to 204, and when the base value in the third history area 314 is the subject of notification, a display such as that shown in FIG. 127(d) is displayed on the first to fourth notification display devices 201 to 204.

If a positive determination is made in step SA306 because the interval flag in the non-specific control work area 223 is set to "1," this means that the first to fourth alarm display devices 201-204 should start notifying the user at the current switching timing as the interval non-display setting. In this case, an interval setting process is executed (step SA314). In this setting process, a value corresponding to the interval period (specifically, 1 second) is set in the switching timing counter in the non-specific control work area 223 as the value corresponding to the next switching timing. Then, the interval flag in the non-specific control work area 223 is cleared to "0" (step SA315). As a result, if the pre-shift display flag in the non-specific control work area 223 has not been set to "1" by the time the next switching timing arrives, the base value will be displayed when the next switching timing arrives.

Then, interval data is set in the display target setting area 276 provided in the non-specific control work area 223 (step SA316). The interval data is data for causing the first through fourth alert display devices 201-204 to perform interval non-display; specifically, it is data for turning off all display segments 321-324 in each of the first through fourth alert display devices 201-204. By setting the interval data as display data in the display target setting area 276, the interval data is sent to the display IC 266 in the second timer interrupt process (Figure 134), and all of the first through fourth alert display devices 201-204 are placed in a non-display state. The amusement hall manager, who confirms that the first through fourth alert display devices 201-204 are in a non-display state, can understand that an interval period has occurred.

If a positive determination is made in step SA305 because the pre-shift display flag in the non-specific control work area 223 is set to "1," this means that the first to fourth alarm display devices 201 to 204 should start announcing the pre-shift display in response to the current switching timing. In this case, a process for setting the pre-shift display period is executed (step SA317). In this setting process, a value corresponding to the execution period of the pre-shift display (specifically, 8 seconds) is set in the switching timing counter in the non-specific control work area 223 as a value corresponding to the next switching timing.

Then, the interval flag in the non-specific control work area 223 is cleared to "0," and the pre-shift display flag in the non-specific control work area 223 is cleared to "0" (step SA318). Furthermore, the display target counter in the non-specific control work area 223 is set to the maximum value, "3" (step SA319). By clearing the interval flag to "0," if the execution period for the pre-shift display has elapsed, the next notification target becomes the base value. Then, if a negative determination is made in step SA306 to notify the base value, the value of the display target counter after incrementing it by 1 in step SA307 exceeds the maximum value, and a positive determination is made in step SA308, clearing the value of the display target counter to "0." As a result, if the execution period for the pre-shift display has elapsed, the next notification target becomes the base value, and that base value becomes the base value in the current state area 311 of the calculation result storage area 234.

In other words, when a pre-shift display is performed, notification of the base value begins regardless of whether the notification target before the pre-shift display was the base value or the interval non-display. This makes it possible to check the base value when the pre-shift display ends without waiting for the interval period to elapse. Furthermore, regardless of whether the base value last to be notified before the pre-shift display was the current status area 311, the first history area 312, the second history area 313, or the third history area 314 of the calculation result storage area 234, notification begins with the base value in the current status area 311 when the pre-shift display ends. This makes it possible to return the notification order of base values in the current status area 311, the first history area 312, the second history area 313, and the third history area 314 to the initial notification order, making it easier for the amusement hall manager to recognize that a base value shift has just occurred.

Then, pre-shift display data is set in the display target setting area 276 provided in the non-specific control work area 223 (step SA320). The pre-shift display data is data for causing the first through fourth alert display devices 201-204 to display the pre-shift display; specifically, it is data for causing each of the first through fourth alert display devices 201-204 to display "A.". By setting the pre-shift display data as display data in the display target setting area 276, the pre-shift display data is sent to the display IC 266 in the second timer interrupt process (FIG. 134), and "A." is displayed on each of the first through fourth alert display devices 201-204. The amusement hall manager, who confirms that the pre-shift display is being displayed on the first through fourth alert display devices 201-204, can determine that the pre-shift display is currently being displayed.

Next, referring to the time chart in Figure 151, we will explain how the base values of the various areas 311-314 are reported by the first to fourth alarm display devices 201-204 when the management start flag is set to "1". Figure 151(a) shows the period during which the base value stored in the current status area 311 is reported by the first to fourth alarm display devices 201-204, Figure 151(b) shows the period during which the base value stored in the first history area 312 is reported by the first to fourth alarm display devices 201-204, Figure 151(c) shows the period during which the base value stored in the second history area 313 is reported by the first to fourth alarm display devices 201-204, Figure 151(d) shows the period during which the base value stored in the third history area 314 is reported by the first to fourth alarm display devices 201-204, and Figure 151(e) shows the period during which interval non-display is performed on the first to fourth notification display devices 201-204, FIG. 151(f) shows the period during which pre-shift display is performed on the first to fourth notification display devices 201-204, and FIG. 151(g) shows the timing when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000) after the base value calculation period has newly started and when the mode is neither the open/close execution mode due to a jackpot result nor the high-frequency support mode.

At timing t1, as shown in FIG. 151(a), the first to fourth alert display devices 201-204 begin to notify the base value stored in the current status area 311. During this notification, as shown in FIG. 127(a), the first alert display device 201 displays a message indicating that the base value is the target of notification, the second alert display device 202 displays a message indicating that the base value stored in the current status area 311 is the target of notification, and the third alert display device 203 and fourth alert display device 204 display a message corresponding to the base value stored in the current status area 311.

After that, at time t2, the display duration period from time t1 has elapsed, and notification of the base value stored in the current status area 311 is terminated as shown in FIG. 151(a), and interval non-display is initiated on the first to fourth notification display devices 201-204 as shown in FIG. 151(e). This interval non-display is terminated at time t3, when the interval period has elapsed from time t2, as shown in FIG. 151(e).

At timing t3, as shown in Figure 151 (b), notification of the base value stored in the first history area 312 begins on the first to fourth alert display devices 201 to 204. During this notification, as shown in Figure 127 (b), the first alert display device 201 displays a message indicating that the base value is the target of notification, the second alert display device 202 displays a message indicating that the base value stored in the first history area 312 is the target of notification, and the third alert display device 203 and fourth alert display device 204 display a message corresponding to the base value stored in the first history area 312.

After that, at time t4, the display duration period from time t3 has elapsed, and notification of the base value stored in the first history area 312 is terminated as shown in FIG. 151(b), and interval non-display is initiated on the first to fourth notification display devices 201-204 as shown in FIG. 151(e). This interval non-display is terminated at time t5, when the interval period has elapsed from time t4, as shown in FIG. 151(e).

At timing t5, as shown in Figure 151 (c), the first to fourth alert display devices 201 to 204 begin to notify the base value stored in the second history area 313. During this notification, as shown in Figure 127 (c), the first alert display device 201 displays an indication that the base value is the subject of notification, the second alert display device 202 displays an indication that the base value stored in the second history area 313 is the subject of notification, and the third alert display device 203 and fourth alert display device 204 display an indication corresponding to the base value stored in the second history area 313.

After that, at time t6, the display duration period from time t5 has elapsed, and notification of the base value stored in the second history area 313 is terminated as shown in Figure 151(c), and interval non-display is initiated on the first to fourth notification display devices 201-204 as shown in Figure 151(e). This interval non-display is terminated at time t7, when the interval period has elapsed from time t6, as shown in Figure 151(e).

At timing t7, as shown in FIG. 151(d), the first to fourth alert display devices 201-204 begin to notify the base value stored in the third history area 314. During this notification, as shown in FIG. 127(d), the first alert display device 201 displays a message indicating that the base value is the target of notification, the second alert display device 202 displays a message indicating that the base value stored in the third history area 314 is the target of notification, and the third alert display device 203 and fourth alert display device 204 display a message corresponding to the base value stored in the third history area 314.

After that, at time t8, the display duration period from time t7 has elapsed, and as shown in Figure 151(d), notification of the base value stored in the third history area 314 ends, and as shown in Figure 151(e), interval non-display begins on the first to fourth notification display devices 201-204. This interval non-display ends at time t9, when the interval period has elapsed from time t8, as shown in Figure 151(e).

After that, from timing t9 to timing t10, similar to timing t1 to timing t2, displays corresponding to the base values stored in the current status area 311 are displayed on the first to fourth alert display devices 201 to 204 as shown in FIG. 151(a). Then, from timing t10 to timing t11, similar to timing t2 to timing t3, interval non-display is displayed on the first to fourth alert display devices 201 to 204 as shown in FIG. 151(e). Then, at timing t11, similar to timing t3, displays corresponding to the base values stored in the first history area 312 are initiated on the first to fourth alert display devices 201 to 204 as shown in FIG. 151(b).

Subsequently, at time t12, while the display corresponding to the base value stored in the first history area 312 is being displayed, the total number of game balls discharged from the game area PA since the start of the new base value calculation period (i.e., the total number of game balls supplied to the game area PA) in a situation that is neither the open/close execution mode due to a jackpot result nor the high-frequency support mode reaches the shift reference number (specifically, 60,000), as shown in FIG. 151(g). However, at time t12, the display duration period has not yet elapsed since the display corresponding to the base value in the first history area 312 began at time t11, so the display corresponding to the base value in the first history area 312 continues, as shown in FIG. 151(b). This makes it possible to start displaying the pre-shift display on the first through fourth notification display devices 201-204 after displaying the current notification target on the first through fourth notification display devices 201-204 for the scheduled period, even if the timing at which the total number of game balls reaches the shift reference number is arbitrary.

After that, at timing t13, the display duration period from timing t11 has elapsed, and as shown in FIG. 151(b), the notification of the base value stored in the first history area 312 is terminated, and as shown in FIG. 151(f), the pre-shift display is initiated on the first to fourth notification display devices 201-204. Even if the total number of game balls reaches the shift reference number while another base value is being notified, the pre-shift display is initiated on the first to fourth notification display devices 201-204 once the display duration for that base value notification has elapsed. Even if the total number of game balls reaches the shift reference number while an interval non-display is being performed, the pre-shift display is initiated on the first to fourth notification display devices 201-204 once the interval period for that interval non-display has elapsed.

After that, at time t14, the execution period of the pre-shift display has elapsed since time t13, and the pre-shift display ends as shown in FIG. 151(f), and notification of the base value stored in the current status area 311 begins on the first to fourth notification display devices 201-204 as shown in FIG. 151(a). In other words, even if the notification target when the pre-shift display begins is the base value in the first history area 312, once the pre-shift display ends, notification begins with the base value in the current status area 311 that corresponds to the first notification order in the base value notification order.

After that, at time t15, the display duration period from time t14 has elapsed, and notification of the base value stored in the current status area 311 is terminated as shown in FIG. 151(a), and interval non-display is initiated on the first to fourth notification display devices 201-204 as shown in FIG. 151(e). This interval non-display is terminated at time t16, when the interval period has elapsed from time t15, as shown in FIG. 151(e), and display corresponding to the base value in the first history area 312 is initiated on the first to fourth notification display devices 201-204 as shown in FIG. 151(b).

The present embodiment described above provides the following excellent effects:

The base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 of the calculation result storage area 234 are displayed sequentially on the first to fourth notification display devices 201 to 204. This makes it possible to individually notify each base value corresponding to a different period while limiting the number of first to fourth notification display devices 201 to 204. Furthermore, because each base value is displayed in a predetermined order, it is easier for the amusement hall manager to understand the type of base value being displayed.

The display order of base values is determined in association with each of the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234. This simplifies the processing configuration for identifying the type of base value to be displayed when starting a new display of base values.

Before the display of one base value changes to the display of the next base value, the first through fourth notification display devices 201-204 enter an interval non-display state. This allows the amusement hall manager to clearly understand that the type of base value being displayed has changed.

In a configuration in which base values are displayed sequentially on the first through fourth notification display devices 201-204, if the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000) after a new base value calculation period has started and the game is not in either the open/close execution mode due to a jackpot result or the high-frequency support mode, a pre-shift display is displayed on the first through fourth notification display devices 201-204. This makes it possible to use the first through fourth notification display devices 201-204 to notify that the total number of game balls has reached the shift reference number.

When the total number of gaming balls reaches the shift reference number, the base values stored in the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234 are shifted to later storage areas in the storage order, and the various counters 231a-231e in the normal counter area 231 are cleared to "0," and calculation of the base value for a new calculation period begins. Therefore, when the total number of gaming balls reaches the shift reference number, the content of the base value notification on the first through fourth notification display devices 201-204 changes. In this case, when the total number of gaming balls reaches the shift reference number, the pre-shift display is displayed and then the notification of the base value resumes, making it possible to make the amusement hall manager aware that the content of the base value notification will change when the total number of gaming balls reaches the shift reference number.

If the total number of game balls reaches the shift reference number while the base value is being displayed, the pre-shift display will begin after the display duration of the base value has elapsed. This makes it possible to start the pre-shift display without interfering with the display of the base value that is already being displayed.

In a configuration in which multiple base values stored in the calculation result storage area 234 are displayed sequentially in a predetermined display order, after the pre-shift display is performed, the base value is displayed starting from the first base value in the predetermined display order. This makes it possible to check the base value again starting from the first base value in the predetermined display order when the total number of game balls reaches the shift reference number.

In a configuration in which base values are calculated using the result calculation process (Figure 149), the result calculation process is executed multiple times from the start of calculation of one base value until the calculation of that base value is completed. This makes it possible to reduce the processing load required to execute the result calculation process compared to a configuration in which base value calculation is completed in a single result calculation process.

In a configuration in which, when the total number of gaming balls reaches the shift reference number, a new base value is derived at the time the shift reference number is reached and then base value data shift processing (step SA216) is executed, when the total number of gaming balls reaches the shift reference number, a pre-shift display is performed on the first to fourth alert display devices 201 to 204. This makes it possible to display a pre-shift display on the first to fourth alert display devices 201 to 204 when a new base value is derived and base value data shift processing is being performed, making it possible to prevent the previous base value from continuing to be displayed even when the shift reference number has been reached.

In addition, from the start of the base value calculation period until the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the initial reference number (specifically, 6,000) in a situation that is neither the open/close execution mode due to a jackpot result nor the high-frequency support mode, the first to fourth notification display devices 201 to 204 may be configured to display an initial calculation when the base value of the current status area 311 is displayed, as in the 35th embodiment above.

Also, if the total number of game balls reaches the shift reference number (specifically, 60,000) while the first to fourth alert display devices 201 to 204 are in the interval non-display mode, the pre-shift display may be immediately initiated; if the total number of game balls reaches the shift reference number (specifically, 60,000) while the base value is being displayed on the first to fourth alert display devices 201 to 204, the pre-shift display may be initiated after the display duration of the base value has elapsed. This makes it possible to start the pre-shift display early without prematurely terminating the display of the base value that is already being displayed.

Furthermore, the display content of the pre-shift display is not limited to the above, and while the display content of at least a portion of the first to fourth alert display devices 201-204 may be display content that can be displayed in other situations, the display content of the entire first to fourth alert display devices 201-204 may be display content that is not displayed in other situations. Furthermore, when the pre-shift display is performed, at least one display segment 321-324 is lit on each of the first to fourth alert display devices 201-204, but for some of the first to fourth alert display devices 201-204, all display segments 321-324 may be extinguished. Furthermore, when the pre-shift display is performed, the display content of the pre-shift display is not limited to being maintained throughout the execution period of the pre-shift display, and the display content of the pre-shift display may be configured to flash throughout the execution period of the pre-shift display.

Furthermore, the execution period of the pre-shift display is not limited to a fixed configuration, and may be configured to vary depending on the time required from when the total number of game balls reaches the shift reference number (specifically, 60,000) until a new base value is calculated and the base value data shift process is completed, for example.

Also, when the total number of game balls reaches the shift reference number, the pre-shift display may be configured to start after the display of the last base value (i.e., the base value stored in the third history area 314) in the display cycle of each base value currently being performed by the first to fourth notification display devices 201 to 204 is completed. This makes it possible to start a new display cycle of each base value via the pre-shift display after the display cycle of each base value is completed.

Also, when the total number of gaming balls reaches the shift reference number, calculation of the base value may be started using the various counters 231a-231e in the normal counter area 231 at that time, and when calculation of the base value is completed, data shift processing (step SA216) may be performed. In this case, it is possible to accurately calculate the base value at the time when the total number of gaming balls reaches the shift reference number.

In addition, instead of displaying an interval display during the interval period, a predetermined display may be displayed on at least some of the first to fourth alarm display devices 201-204, and the entire display of the first to fourth alarm display devices 201-204 may display an interval display that has display content different from the display content that would occur in a situation where a base value is being reported. For example, the first to fourth alarm display devices 201-204 may be configured so that only the central display segments 321-324 are lit to display "-", or some of the first to fourth alarm display devices 201-204 may display "-" while the remaining display devices are in a non-display state.

Alternatively, an interval period may not be set. In this case, when the display duration period for one base value has elapsed, the display of the next base value to be displayed will begin on the first through fourth notification display devices 201-204.

<Forty-fourth embodiment>
In this embodiment, the start timing of the pre-shift display is different from that of the 43rd embodiment. The following describes the configuration that is different from the 43rd embodiment. Note that the description of the same configuration as the 43rd embodiment will basically be omitted.

The start timing of the pre-shift display in this embodiment will be explained with reference to the time chart in Figure 152. Figure 152(a) shows the period during which the base value stored in the current status area 311 is reported by the first to fourth notification display devices 201 to 204, Figure 152(b) shows the period during which the base value stored in the first history area 312 is reported by the first to fourth notification display devices 201 to 204, Figure 152(c) shows the period during which the base value stored in the second history area 313 is reported by the first to fourth notification display devices 201 to 204, Figure 152(d) shows the period during which the base value stored in the third history area 314 is reported by the first to fourth notification display devices 201 to 204, and Figure 152(e) shows the period during which interval non-display is performed on the first to fourth notification display devices 201-204, FIG. 152(f) shows the period during which pre-shift display is performed on the first to fourth notification display devices 201-204, and FIG. 152(g) shows the timing when the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000) after the base value calculation period has newly started and when the mode is neither the open/close execution mode due to a jackpot result nor the high-frequency support mode.

At times t1 to t11, similar to the time charts of Figures 151(a) to 151(g) in the 43rd embodiment, the first to fourth alarm display devices 201 to 204 alternate between displaying a value corresponding to the base value over the display duration period and not displaying a value for the interval period, and the display corresponding to the base value is repeated in the order of the current status area 311, first history area 312, second history area 313, and third history area 314 in the calculation result storage area 234. Then, at time t11, the first to fourth alarm display devices 201 to 204 begin displaying a value corresponding to the base value stored in the first history area 312, as shown in Figure 152(b).

Then, at time t12, while the display corresponding to the base value stored in the first history area 312 is in progress, the total number of game balls discharged from the game area PA since the start of the new base value calculation period (i.e., the total number of game balls supplied to the game area PA) in a state other than the jackpot result open/close execution mode or the high frequency support mode reaches the shift reference number (specifically, 60,000), as shown in FIG. 152(g). In this case, at time t12, although the display duration period has not yet elapsed since the display corresponding to the base value in the first history area 312 began at time t11, the display of the base value stored in the first history area 312 ends, as shown in FIG. 152(b), and the pre-shift display begins on the first through fourth notification display devices 201-204, as shown in FIG. 152(f).

Even if the total number of game balls reaches the shift reference number while another base value is being notified, the pre-shift display will begin on the first to fourth notification display devices 201 to 204 at that time. Even if the total number of game balls reaches the shift reference number while the interval non-display is being performed, the pre-shift display will begin on the first to fourth notification display devices 201 to 204 at that time.

After that, at time t13, the execution period of the pre-shift display has elapsed since time t12, and the pre-shift display ends as shown in FIG. 152(f), and notification of the base value stored in the current status area 311 begins on the first to fourth notification display devices 201-204 as shown in FIG. 152(a). In other words, even if the notification target when the pre-shift display begins is the base value in the first history area 312, once the pre-shift display ends, notification begins with the base value in the current status area 311 that corresponds to the first notification order in the base value notification order.

After that, at time t14, the display duration period from time t13 has elapsed, and notification of the base value stored in the current status area 311 is terminated as shown in FIG. 152(a), and interval non-display is initiated on the first to fourth notification display devices 201-204 as shown in FIG. 152(e). This interval non-display is terminated at time t15, when the interval period has elapsed from time t14, as shown in FIG. 152(e), and display corresponding to the base value in the first history area 312 is initiated on the first to fourth notification display devices 201-204 as shown in FIG. 152(b).

With the above configuration, if the total number of game balls discharged from the game area PA (i.e., the total number of game balls supplied to the game area PA) reaches the shift reference number (specifically, 60,000) after the start of a new base value calculation period when the game is not in either the open/close execution mode due to a jackpot result or the high-frequency support mode, the first through fourth notification display devices 201-204 will begin displaying the pre-shift information at that time. This makes it possible to begin the pre-shift information early, making it possible to provide early notification that the total number of game balls has reached the shift reference number.

<Forty-fifth embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 35th embodiment. The configuration that differs from the 35th embodiment will be described below. Note that the description of the same configuration as the 35th embodiment will basically be omitted.

Figure 153 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SA401 to SA425 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, the power-on initialization process is executed (step SA401). During the power-on initialization process, for example, the main process is started and the process waits until a predetermined waiting time (specifically, one second) has elapsed before proceeding to the next process. During this predetermined waiting period, the operation of the pattern display device 41 is started and the initial settings are completed. Access to the main RAM 65 is also permitted.

Then, the internal function register setting process is executed (step SA402). In the internal function register setting process, as in the 35th embodiment, the interrupt period of the first timer interrupt process (FIG. 133), which is a process that periodically interrupts the main process and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt process (FIG. 134), which is a process that periodically interrupts the main process and is started, is set to a second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, as in the 35th embodiment, there are first timer interrupt processing (FIG. 133) and second timer interrupt processing (FIG. 134) so that the interrupt periods are relatively long and short as timer interrupt processing. Both the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are started by interrupting the main processing. Also, the second timer interrupt processing (FIG. 134) is started by interrupting the first timer interrupt processing (FIG. 133). On the other hand, the first timer interrupt processing (FIG. 133) is not started by interrupting the second timer interrupt processing (FIG. 134). Also, if both the first interrupt period and the second interrupt period have elapsed when both the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are not being executed, the second timer interrupt processing (FIG. 134) is started first, regardless of the order in which the periods elapse. In this regard, it can be said that the second timer interrupt process (FIG. 134) is started with priority over the first timer interrupt process (FIG. 133). However, this is not limited to this, and the first timer interrupt process (FIG. 133) may be started with priority over the second timer interrupt process (FIG. 134).

The internal function register setting process sets the first interrupt period of the first timer interrupt process (Figure 133) in a specified register of the main CPU 63, and sets the second interrupt period of the second timer interrupt process (Figure 134) in a specific register of the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs processes such as setting the numerical ranges of various counters, such as the numerical range of the winning random number counter C1.

Then, the startup processing in progress flag provided in the work area 221 for specific control is set to "1" (step SA403). As with the 35th embodiment described above, the startup processing in progress flag is a flag that allows the main CPU 63 to identify a situation in which, even if the first timer interrupt processing (FIG. 133) is started, the various processes set in the first timer interrupt processing (FIG. 133) for power outage monitoring, updating of various counters, and fraud monitoring will be executed, but the first timer interrupt processing (FIG. 133) should be terminated without executing any processes for progressing the game.

As in the 35th embodiment, the startup processing flag is set to "1" when the processing at the start of the supply of operating power (steps SA401 to SA418) begins in the main processing (Fig. 153) and before interrupt permission (step SA404) is performed, and is cleared to "0" before the processing at the start of the supply of operating power ends and the remaining processing (steps SA422 to SA425) begins. In this case, as in the 35th embodiment, if the startup processing flag is set to "1" in the first timer interrupt processing (Fig. 133), the processing of steps S8907 to S8920 is not executed, thereby making it possible to prevent processing to progress the game while the processing at the start of the supply of operating power (steps SA401 to SA418) is being executed. On the other hand, as described above, even if the startup processing in progress flag is set to "1" in the first timer interrupt processing (FIG. 133), by executing steps S8901 to S8905, power outage monitoring is performed even when processing at the start of operating power supply (steps SA401 to SA418) is being performed, and the win random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is also performed.

In particular, even when the startup processing flag is set to "1," the power outage information storage process (step S8901) is executed, making it possible to execute power outage processing even if a power outage occurs while processing at the start of operating power supply (steps SA401 to SA418) is being executed. As with the 35th embodiment, power outage processing involves setting the power outage flag in the specific control work area 221 to "1," calculating a checksum, and storing the calculated checksum in the specific control work area 221. This prevents the occurrence of an abnormality in the main RAM 65 from being identified when operating power supply is restarted. As a result, if a power outage occurs during the setting confirmation process (step SA415) or the setting value update process (step SA418), it becomes possible to identify that a power outage occurred during these setting-related processes at the start of the next operating power supply.

Incidentally, when the setting confirmation process (step SA415) or the setting value update process (step SA418) is being executed, interrupts are not prohibited for either the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134), and interrupts can occur at any time. In this case, when the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134) interrupts and starts the main process (Figure 153) including the setting confirmation process (step SA415) and the setting value update process (step SA418), information about the return address of the main process (Figure 153) to return to after the timer interrupt process that was started is completed is saved in the specific control stack area 222, and information about the various registers of the main CPU 63 immediately before the timer interrupt process is started is saved in the specific control stack area 222. When the timer interrupt process that was the target of activation is completed, the process returns to the main process (FIG. 153) corresponding to the return address information saved in the specific control stack area 222, and the information saved in the specific control stack area 222 is restored to the various registers of the main CPU 63.

After setting the startup processing flag to "1" in step SA403, interrupt permission is set (step SA404). As a result, the first timer interrupt processing (Fig. 133) is started by interrupting at the first interrupt period, and the second timer interrupt processing (Fig. 134) is started by interrupting at the second interrupt period. However, because the startup processing flag was set to "1" in step SA403, even if the first timer interrupt processing (Fig. 133) is started, the various processes of the first timer interrupt processing (Fig. 133) for power outage monitoring, updating various counters, and fraud monitoring are executed, but the first timer interrupt processing (Fig. 133) is terminated without executing any processes for progressing the game.

Then, it is determined whether the reset button 68c has been pressed (step SA405). In other words, it is determined whether the power to the pachinko machine 10 has been turned on while the reset button 68c is pressed, and the supply of operating power to the main CPU 63 has begun. In this embodiment, as in the 35th embodiment, the main control unit 60 is provided with a setting key insertion unit 68a and a reset button 68c, but is not provided with an update button 68b. Furthermore, as in the 11th embodiment, the main control unit 60 is provided with first to fourth notification display devices 201 to 204, rather than first to third notification display devices 69a to 69c.

If the reset button 68c is not pressed (step SA405: NO), it is determined whether the power outage flag provided in the specific control work area 221 is set to "1" (step SA406). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step SA406: YES), a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step SA407). The checksum calculation method is the same as in the 33rd embodiment. Then, the checksums for the specific control work area 221 and the specific control stack area 222 calculated and stored in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped are read, and the read checksums are compared with the checksum calculated in step SA407 (step SA408). It is then determined whether the checksums match (step SA409).

If a negative judgment is made in step SA406 or step SA409, i.e., if the power outage flag is not set to "1" or the checksums do not match, the game stop flag provided in the specific control work area 221 is set to "1" (step SA410). Setting the game stop flag to "1" causes steps S8901 to S8905 to be executed in the first timer interrupt process (Figure 133), while a positive judgment is made in step S8906 and steps S8907 to S8920 are not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly during the previous power outage, or if the checksums do not match because the information storage state in at least one of the specific control work area 221 and the specific control stack area 222 has changed since the previous power outage, the processes for power outage monitoring, updating various counters, and fraud monitoring are executed, but the processes for progressing the game are not executed.

Then, an abnormality command indicating that an abnormality occurred in the power outage flag or checksum when the supply of operating power began is sent to the audio and light-emitting control device 81 (step SA411). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the information abnormality at the start of the supply of operating power, and causes the speaker unit 54 to output a voice message saying "Please change the settings." The message also appears as a text image saying "Please change the settings" on the symbol display device 41. These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notifications may be continued when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (step SA418) is executed.

If the power outage flag is set to "1" and the checksum is normal (step SA406 and step SA409: YES), the process determines whether the setting update display flag provided in the specific control work area 221 is set to "1" (step SA412). As in the 35th embodiment, the setting update display flag is a flag used by the main CPU 63 to identify that the setting value update process (step SA418) is being executed. When the setting update display flag is set to "1," the first through fourth alarm display devices 201-204 display an indication that the setting values are being updated and an indication of the setting values being updated. The setting update display flag is set to "1" when the setting value update process (step SA418) is initiated and cleared to "0" when the setting value update process (step SA418) is terminated. Therefore, the setting update display flag is not generally set to "1" when the setting value update process (step SA418) is not being executed. However, if the supply of operating power to the main CPU 63 is stopped while the setting value update process (step SA418) is being executed, the setting update display flag will be set to "1" when the supply of operating power to the main CPU 63 is subsequently started. This state in which the setting update display flag is set to "1" is maintained until the RAM clear process (step SA416) is executed or the process of clearing the setting update display flag to "0" is executed in the setting value update process (step SA418).

If the setting update display flag is not set to "1" and a negative judgment is made in step SA412, it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step SA413). If the setting key insertion unit 68a has been turned ON using the setting key (step SA413: YES), setting confirmation processing is executed (step SA415). Even if the setting key insertion unit 68a has not been turned ON using the setting key (step SA413: NO), if the setting confirmation display flag provided in the specific control work area 221 is set to "1" (step SA414: YES), setting confirmation processing is executed (step SA415). The setting confirmation processing will be described later.

As in the 35th embodiment, the setting confirmation display flag is a flag used by the main CPU 63 to identify that the setting confirmation process (step SA415) is being executed. When the setting confirmation display flag is set to "1," the first through fourth alarm display devices 201-204 display a message indicating that the setting values are being confirmed and a message indicating the currently set setting values. The setting confirmation display flag is set to "1" when the setting confirmation process (step SA415) is initiated and cleared to "0" when the setting confirmation process (step SA415) is terminated. Therefore, the setting confirmation display flag is not generally set to "1" when the setting confirmation process (step SA415) is not being executed. However, if the supply of operating power to the main CPU 63 is stopped while the setting confirmation process (step SA415) is being executed, the setting confirmation display flag will be set to "1" when the supply of operating power to the main CPU 63 is subsequently resumed. The setting confirmation display flag remains set to "1" until the RAM clear process (step SA416) is executed, or the setting confirmation display flag is cleared to "0" during the setting confirmation process (step SA415).

If the reset button 68c is pressed (step SA405: YES), a RAM clear process is executed (step SA416). In the RAM clear process, the specific control work area 221 is cleared to "0" and an initial setting is executed, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (specifically, the setting reference area 341, described below). This clears the area indicating whether the win/loss lottery mode is in the high-probability mode to "0," so the win/loss lottery mode becomes the low-probability mode regardless of the win/loss lottery mode in effect immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserve storage area 65a and the normal power reserve area 65c provided in the work area 221 for specific control are also cleared to "0," thereby erasing the reserve information for the special map display unit 37a and the reserve information for the normal map display unit 38a. The setting update display flag and setting confirmation display flag provided in the work area 221 for specific control are cleared to "0." The setting update area 342 (described below) provided in the work area 221 for specific control is also cleared to "0." The RAM clear process also clears the stack area 222 for specific control to "0" and performs initial settings. The RAM clear process also clears various registers of the main CPU 63 to "0" before performing initial settings. This initial setting process performs the same processing as the internal function register setting process of step SA402. Note that the process for clearing the work area 223 for non-specific control and the process for performing initial settings are not performed for the work area 223 for non-specific control and the stack area 224 for non-specific control.

Then, it is determined whether the setting key insertion unit 68a has been turned on using the setting key (step SA417). If it has been turned on (step SA417: YES), a setting value update process is executed (step SA418). The setting value update process will be described later.

If the processing of step SA411 is executed, if a negative judgment is made in step SA414, if the processing of step SA415 is executed, if a negative judgment is made in step SA417, or if the processing of step SA418 is executed, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SA419). The value set in the checking counter is decremented by 1 each time the second timer interrupt processing (Figure 134) is initiated, as in the 35th embodiment above. If a value of 1 or greater is set in the checking counter, the check display continues on the first to fourth alarm display devices 201 to 204, as in the 35th embodiment above.

With the above configuration, when the supply of operating power to the main CPU 63 begins, the initial check period begins after the main CPU 63 completes the processing at the start of the supply of operating power (steps SA401 to SA418) and before the remaining processing (steps SA422 to SA425) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, making it possible to reduce the processing load while the processing at the start of the supply of operating power is being executed.

Furthermore, while the setting confirmation process (step SA415) and the setting value update process (step SA418) are executed as processes when the supply of operating power starts, the initial check period starts after the processes when the supply of operating power starts have finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

Then, the startup processing in progress flag in the specific control work area 221 is cleared to "0" (step SA420). When the startup processing in progress flag is cleared to "0," if the first timer interrupt process (FIG. 133) is initiated, a negative judgment is made in step S8906, which causes the processes of steps S8901 to S8905 as well as steps S8907 to S8920 to be executed, thereby canceling the state in which processes for progressing the game are not executed. Note that in step SA420, the power outage flag in the specific control work area 221 is also cleared to "0."

Then, a return command is sent to the audio and light emission control device 81 (step SA421). The information contained in the return command and the processing performed by the audio and light emission control device 81 when the return command is received are the same as those in step S7920 of the main processing (Figure 114) in the 33rd embodiment described above.

Then, the remaining processing of steps SA422 to SA425 continues. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134), but there is remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps SA422 to SA425. In this respect, the remaining processing of steps SA422 to SA425 can be said to be non-periodic processing executed non-periodically. Steps SA422 to SA425 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, we will explain the configuration related to setting values in this embodiment. Figure 154 is an explanatory diagram illustrating the contents of the storage area related to setting values provided in the work area 221 for specific control.

As shown in FIG. 154, the work area 221 for specific control has a setting reference area 341 and a setting update area 342. The setting reference area 341 is a memory area that stores information used by the main CPU 63 to identify the current setting values of the pachinko machine 10. In step S503 of the special chart variation start processing (FIG. 13), the current setting values of the pachinko machine 10 are identified using the information stored in the setting reference area 341, and a win/loss table corresponding to the identified setting values is read. Then, in step S504, the win/loss determination processing is executed using the read win/loss table. Furthermore, when the setting confirmation display flag in the work area 221 for specific control is set to "1", the setting values corresponding to the information stored in the setting reference area 341 are displayed on the fourth notification display device 204.

The setting reference area 341 stores numerical information as setting value information. Specifically, if numerical information of "1" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 1." If numerical information of "2" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 2." If numerical information of "3" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 3." If numerical information of "4" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 4." If numerical information of "5" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 5." If numerical information of "6" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 6."

The setting update area 342 stores information about setting values being updated during the setting value update process (step SA418). In other words, during the setting value update process (step SA418), the setting value information for the selected item is updated each time the reset button 68c is pressed. During this update, the setting value information stored in the setting reference area 341 remains unchanged; instead, the setting value information stored in the setting update area 342 is changed. This allows the setting values to be updated while retaining the setting value information that was set before the setting value update process (step SA418) began. When the setting value update process (step SA418) is terminated, the setting value information stored in the setting update area 342 at that time is overwritten in the setting reference area 341. As a result, the setting values updated during the setting value update process (step SA418) are set as the current setting values for the pachinko machine 10. Furthermore, when the setting update display flag in the specific control work area 221 is set to "1", the setting value corresponding to the information stored in the setting update area 342 is displayed on the fourth notification display device 204.

The setting update area 342 stores numerical information as setting value information. Specifically, if numerical information of "1" is stored in the setting update area 342, the setting value to be updated (to be selected or changed) will be "Setting 1." If numerical information of "2" is stored in the setting update area 342, the setting value to be updated will be "Setting 2." If numerical information of "3" is stored in the setting update area 342, the setting value to be updated will be "Setting 3." If numerical information of "4" is stored in the setting update area 342, the setting value to be updated will be "Setting 4." If numerical information of "5" is stored in the setting update area 342, the setting value to be updated will be "Setting 5." If numerical information of "6" is stored in the setting update area 342, the setting value to be updated will be "Setting 6."

Figure 155 is a flowchart showing the setting confirmation process executed in step SA415 of the main processing (Figure 153). Note that steps SA501 to SA504 in the setting confirmation process are executed using a specific control program and specific control data in the main CPU 63.

On the condition that the setting confirmation display flag provided in the specific control work area 221 is not set to "1" (step SA501: NO), the setting confirmation display flag is set to "1" (step SA502). When the setting confirmation display flag is set to "1", a positive determination is made in step S9005 of the second timer interrupt process (FIG. 134), and setting processing to the fifth display data buffer 275 during setting confirmation (step S9006) is executed.

Figure 156 is a flowchart showing the setting process for the fifth display data buffer 275 during setting confirmation. Note that steps SA601 to SA603 in this setting process are executed using a specific control program and specific control data in the main CPU 63.

First, the display data for the setting value corresponding to the setting value information stored in the setting reference area 341 of the specific control work area 221 is read (step SA601). The read display data for the setting value is then set in the fifth display data buffer 275 in the specific control work area 221 as display data to be applied to the fourth alert display device 204 (step SA602). Furthermore, display data for causing the first to third alert display devices 201 to 203 to display an indication that the setting value of the pachinko machine 10 is being checked is set in the fifth display data buffer 275 (step SA603).

As a result of the setting process for the fifth display data buffer 275 being executed while the settings are being confirmed as described above, a display corresponding to the display data set in the fifth display data buffer 275 in step SA603 is displayed on the first to third alert display devices 201 to 203, and a display corresponding to the display data set in the fifth display data buffer 275 in step SA602 is displayed on the fourth alert display device 204. As a result, as shown in the explanatory diagram of FIG. 124(b), for example, a display indicating that the setting values of the pachinko machine 10 are being confirmed and a display showing the current setting values of the pachinko machine 10 are displayed on the first to fourth alert display devices 201 to 204.

Returning to the explanation of the setting confirmation process (Figure 155), if a positive determination is made in step SA501 or if the process of step SA502 is executed, it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SA503). Specifically, it is determined whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state. Therefore, a negative determination is made in step SA503 not only when the setting key insertion unit 68a is maintained in the ON state, but also when the setting confirmation process is started when the setting key insertion unit 68a is in the OFF state and the OFF state is maintained. If it is not determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SA503: NO), the process of step SA503 is repeated.

If it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SA503: YES), the setting confirmation display flag in the specific control work area 221 is cleared to "0" (step SA504). As a result, a negative determination is made in step S9005 of the second timer interrupt process (FIG. 134), and the setting process to the fifth display data buffer 275 during setting confirmation (step S9006) is not executed. Therefore, the first to fourth notification display devices 201 to 204 are no longer displaying the indication that the current setting value of the pachinko machine 10 is being confirmed and the current setting value of the pachinko machine 10.

As described above, when the power to the pachinko machine 10 is turned on with the setting key insertion section 68a turned on using the setting key without pressing the reset button 68c, the supply of operating power to the main CPU 63 begins and the main processing (Figure 153) begins. This results in the reset button 68c not being pressed and the setting key insertion section 68a being turned on, and the setting confirmation processing (Figure 155) being executed when processing is being executed at the start of the supply of operating power, which is the state before the processing that allows game play to proceed in the main processing (Figure 153) is executed. This makes it possible to check the setting values when no game is being played.

Figure 157 is a flowchart showing the setting value update process executed in step SA418 of the main processing (Figure 153). Note that steps SA701 to SA710 in the setting value update process are executed using a specific control program and specific control data in the main CPU 63.

First, it is determined whether the setting update display flag provided in the work area 221 for specific control is set to "1" (step SA701). If the setting update display flag is not set to "1" (step SA701: NO), the setting update display flag is set to "1" (step SA702). Then, the setting value information stored in the setting reference area 341 in the work area 221 for specific control is overwritten in the setting update area 342 in the work area 221 for specific control (step SA703). As a result, the setting value information that was set when the supply of operating power was last stopped is set in the setting update area 342.

On the other hand, if the supply of operating power is stopped while the setting value update process is being executed, and then the supply of operating power is resumed and the setting value update process is started without executing the RAM clear process (step SA416) of the main process (Figure 153), and the setting update display flag is already set to "1" (step SA701: YES), the process of step SA703 is not executed. In this case, the process from step SA704 onwards will be executed with the setting value information set in the setting update area 342 during the setting value update process before the supply of operating power was stopped remaining unchanged.

If the setting update display flag is set to "1", a positive determination is made in step S9003 of the second timer interrupt process (Figure 134), and setting processing (step S9004) is executed for the fifth display data buffer 275 during setting update.

Figure 158 is a flowchart showing the setting process for the fifth display data buffer 275 during setting update. Note that steps SA801 to SA803 in this setting process are executed using a specific control program and specific control data in the main CPU 63.

First, the display data for the setting value corresponding to the setting value information stored in the setting update area 342 of the specific control work area 221 is read (step SA801). The read display data for the setting value is then set in the fifth display data buffer 275 in the specific control work area 221 as display data to be applied to the fourth alert display device 204 (step SA802). Furthermore, display data for causing the first to third alert display devices 201 to 203 to display an indication that the setting value of the pachinko machine 10 is being updated is set in the fifth display data buffer 275 (step SA803).

As a result of the setting process being executed on the fifth display data buffer 275 during the setting update as described above, the first to third alert display devices 201 to 203 display a display corresponding to the display data set in the fifth display data buffer 275 in step SA803, and the fourth alert display device 204 displays a display corresponding to the display data set in the fifth display data buffer 275 in step SA802. As a result, as shown in the explanatory diagram of FIG. 124(a), for example, a display indicating that the setting values of the pachinko machine 10 are being updated and a display of the setting values selected to be updated for the pachinko machine 10 are displayed on the first to fourth alert display devices 201 to 204.

Returning to the explanation of the setting value update process (Figure 157), if a positive judgment is made in step SA701 or if the processing of step SA703 is executed, it is determined whether the setting value information stored in the setting update area 342 is any of "1" to "6" (step SA704). If it is not any of "1" to "6" (step SA704: NO), "1" is set in the setting update area 342 (step SA705). As a result, the setting value to be updated becomes "Setting 1".

If a positive determination is made in step SA704 or if the processing of step SA705 is executed, a determination is made as to whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SA706). Specifically, a determination is made as to whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state. Therefore, a negative determination is made in step SA706 not only when the setting key insertion unit 68a is maintained in the ON state, but also when the setting value update processing is started when the setting key insertion unit 68a is in the OFF state and the OFF state is maintained.

If the determination in step SA706 is negative, and the reset button 68c has been pressed (step SA707: YES), the value in the setting update area 342 is incremented by 1 (step SA708). As a result, the setting value is updated to the next higher level each time the reset button 68c is pressed. If the reset button 68c has not been pressed (step SA707: NO) or the value in the setting update area 342 is incremented by 1, the process returns to step SA704. However, if the determination in step SA704 is that the value in the setting update area 342 is 7 or greater, "1" is set in the setting update area 342 in step SA705. As a result, if the reset button 68c is pressed once when the setting is "6," the setting will return to "1."

If it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SA706: YES), the setting value information stored in the setting update area 342 is overwritten in the setting reference area 341 (step SA709). As a result, the setting value information resulting from the update in this setting value update process is set in the setting reference area 341, and the setting value corresponding to this set information becomes the current setting value of the pachinko machine 10.

Then, the setting update display flag in the specific control work area 221 is cleared to "0" (step SA710). As a result, a negative determination is made in step S9003 of the second timer interrupt process (FIG. 134), and the setting process (step S9004) to the fifth display data buffer 275 during the setting update is not executed. Therefore, the first to fourth notification display devices 201 to 204 are no longer displaying the indication that the current setting values of the pachinko machine 10 are being updated, and the setting values selected for update for the pachinko machine 10 are no longer displayed.

As described above, not only is the power to the pachinko machine 10 turned on while pressing the reset button 68c, but also the setting value update process (Figure 157) is executed based on the power being turned on while the setting key insertion section 68a is turned on using the setting key. Also, as already explained, the setting confirmation process (Figure 155) is executed based on the power being turned on while the setting key insertion section 68a is turned on using the setting key, without pressing the reset button 68c. This makes it possible to standardize the ON operation of the setting key insertion section 68a as the operation for executing setting-related processes related to setting values. This makes it possible to make the operations required to trigger setting-related processes easier to understand for the amusement hall manager.

In addition, when the setting key insertion section 68a is turned on with the setting key while the pachinko machine 10 is powered on, if the reset button 68c is not pressed, a setting confirmation process is executed, but if the reset button 68c is pressed, a setting value update process is executed. This makes it possible to differentiate between the setting confirmation process and the setting value update process depending on whether the reset button 68c is pressed. This makes it possible to make the operation details for executing the desired process, either the setting confirmation process or the setting value update process, easier for the amusement hall manager to understand. Furthermore, by having more operation details for executing the setting value update process than the setting confirmation process, it becomes particularly difficult to perform fraudulent acts in the setting value update process.

Next, we will explain, with reference to the diagram in Figure 159, the processing executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (Figure 157) or setting confirmation processing (Figure 155) is being executed.

First, we will explain the processing that is executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed if power outage processing is executed when neither the setting value update processing (Figure 157) nor the setting confirmation processing (Figure 155) has been executed.

If the supply of operating power is resumed without the setting key insertion section 68a being turned ON and without the reset button 68c being pressed (i.e., in the case of "no operation"), the main processing (Fig. 153) does not execute any of the RAM clear processing (step SA416), setting value update processing (step SA418), and setting confirmation processing (step SA415). If the supply of operating power is resumed while the setting key insertion section 68a is not turned ON but the reset button 68c is pressed (i.e., in the case of a "RAM clear operation"), the main processing (Fig. 153) executes the RAM clear processing (step SA416), but does not execute the setting value update processing (step SA418) or setting confirmation processing (step SA415). When the supply of operating power is resumed while the setting key insertion section 68a is turned ON and the reset button 68c is pressed (i.e., when a "setting change operation" is performed), the main processing (FIG. 153) executes a RAM clear process (step SA416) and a setting value update process (step SA418), but does not execute a setting confirmation process (step SA415). When the supply of operating power is resumed while the setting key insertion section 68a is turned ON but the reset button 68c is not pressed (i.e., when a "setting confirmation operation" is performed), the setting confirmation process (step SA415) is executed, but does not execute a RAM clear process (step SA416) or a setting value update process (step SA418).

Next, we will explain the processing that is executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (step SA418) is being executed (i.e., when the setting update display flag is set to "1").

If the supply of operating power is resumed when a "RAM clear operation" has been performed, the RAM clear process (step SA416) is executed in the main processing (Fig. 153), but the setting value update process (step SA418) and setting confirmation process (step SA415) are not executed. In other words, even if power outage processing is executed while the setting value update process (step SA418) is being executed, if a "RAM clear operation" is performed when the supply of operating power is subsequently resumed, the RAM clear process (step SA416) is executed without resuming or newly executing the setting value update process (step SA418). This makes it possible to prioritize the execution of only the RAM clear process (step SA416) in response to a "RAM clear operation." In this case, if power outage processing was performed before step SA709 was performed in the setting value update processing (step SA418), information about the setting values updated in the setting value update processing (step SA418) (i.e., the changed setting values) is not set in the setting reference area 341, and therefore the setting values that were set before the setting value update processing (step SA418) was started will remain in use even after the supply of operating power is resumed. Note that the setting update display flag is cleared to "0" when the RAM clear processing (step SA416) is performed.

If the supply of operating power is resumed after a "setting change operation" has been performed, the main processing (FIG. 153) will execute a RAM clear process (step SA416) and a setting value update process (step SA418), but will not execute the setting confirmation process (step SA415). In other words, even if power outage processing is executed while the setting value update process (step SA418) is being executed, if a "setting change operation" is subsequently performed when the supply of operating power is resumed, the RAM clear process (step SA416) will be executed and then the setting value update process (step SA418) will be started anew.

When the RAM clear process (step SA416) is executed, the setting update display flag in the specific control work area 221 is cleared to "0" as already explained. Therefore, in the setting value update process (FIG. 157), a negative determination is made in step SA701, and the setting value information stored in the setting reference area 341 is overwritten in the setting update area 342. Therefore, if power outage processing is executed before step SA709 is executed in the setting value update process (step SA418) before the supply of operating power is stopped, the setting value information updated in the setting value update process (step SA418) is invalidated because it is not set in the setting reference area 341. In this case, in the setting value update process (step SA418) after the supply of operating power is resumed, the setting value is updated from the setting value that was set before the setting value update process (step SA418) was started before the supply of operating power was stopped.

If the supply of operating power is resumed when no operation is performed, or when the supply of operating power is resumed when a "settings check operation" is performed, the main processing (Fig. 153) will make a positive determination in step SA412, provided that no abnormalities have occurred in the power outage flag and checksum, and the setting value update processing (step SA418) will be executed without executing the RAM clear processing (step SA416). If the RAM clear processing (step SA416) is not executed, the setting update display flag in the specific control work area 221 will remain set to "1." Therefore, the setting value information in the setting update area 342 will be maintained as is by making a positive determination in step SA701 in the setting value update processing (Fig. 157). Therefore, the setting value update will resume from the setting value that was in the middle of being updated in the setting value update processing (step SA418) before the supply of operating power was stopped. As a result, if power outage processing is performed during the setting value update processing (step SA418) and the "RAM clear operation" is not performed when the supply of operating power is subsequently resumed, it is possible to resume the setting value update processing (step SA418) even if the "setting change operation" is not performed.

In particular, it is conceivable that the power to the pachinko machine 10 may be accidentally turned OFF while the setting value update process (step SA418) is being performed. In this case, it is conceivable that the power to the pachinko machine 10 may be immediately turned ON. In this case, it is conceivable that the power to the pachinko machine 10 may be turned ON while the setting key insertion portion 68a is still ON and without pressing the reset button 68c. In this case, the supply of operating power will be resumed when the "setting confirmation operation" is performed. In such a situation, the setting value update process (step SA418) is executed as described above, and the update of the setting value is resumed from the setting value that was being updated in the setting value update process (step SA418) before the supply of operating power was stopped in the setting value update process (step SA418). This makes it possible to resume updating the setting value without any problems, even if an event such as the one described above occurs.

Next, we will explain the processing that is executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting confirmation processing (step SA415) is being executed (i.e., the setting confirmation display flag is set to "1").

If the supply of operating power is resumed after a "RAM clear operation" has been performed, the main processing (FIG. 153) executes the RAM clear process (step SA416), but the setting value update process (step SA418) and the setting confirmation process (step SA415) are not executed. In other words, even if power outage processing is executed while the setting confirmation process (step SA415) is being executed, if a "RAM clear operation" is performed when the supply of operating power is subsequently resumed, the RAM clear process (step SA416) is executed without newly executing the setting confirmation process (step SA415). This makes it possible to prioritize the execution of only the RAM clear process (step SA416) in response to a "RAM clear operation." Note that the setting confirmation display flag is cleared to "0" when the RAM clear process (step SA416) is executed.

If the supply of operating power is resumed when a "setting change operation" has been performed, the main processing (Fig. 153) executes a RAM clear process (step SA416) and a setting value update process (step SA418), but does not execute a setting confirmation process (step SA415). In other words, even if power outage processing is executed while the setting confirmation process (step SA415) is being executed, if a "setting change operation" is performed when the supply of operating power is subsequently resumed, the RAM clear process (step SA416) is executed and then the setting value update process (step SA418) is executed, without newly executing the setting confirmation process (step SA415). This makes it possible to prioritize the execution of the RAM clear process (step SA416) and the setting value update process (step SA418) in response to a "setting change operation." Furthermore, even if the setting confirmation process (step SA415) is not executed in this manner, the setting value update process (step SA418) is executed, causing the setting value to be updated to be displayed on the fourth alert display device 204, and when the setting value update process (step SA418) is completed, information about the setting value to be updated at that time is set in the setting reference area 341, allowing the amusement hall manager to check the current setting values of the pachinko machine 10. Furthermore, the setting confirmation display flag is cleared to "0" when the RAM clear process (step SA416) is executed.

If the supply of operating power is resumed after the "settings check operation" has been performed, the main processing (Fig. 153) executes the settings check process (step SA415) on the condition that no abnormalities have occurred in the power outage flag and checksum. As a result, even if power outage processing is executed during the settings check process (step SA415), it is possible to resume checking the setting values by performing the "settings check operation" when the supply of operating power is resumed.

If the supply of operating power is resumed in a "no operation" state, the main processing (FIG. 153) will make a positive determination in step SA414 on the condition that no abnormalities have occurred in the power outage flag and checksum, and the setting confirmation processing (step SA415) will be executed even if the setting key insertion unit 68a has not been turned ON. This makes it possible to resume checking the setting values even if the power outage processing is executed during the setting confirmation processing (step SA415) and the supply of operating power is subsequently resumed in a "no operation" state.

Next, the end timing of the setting value update process (FIG. 157) and the setting confirmation process (FIG. 155) in relation to the operation state of the setting key insertion unit 68a will be explained with reference to the time chart in FIG. 160. FIG. 160(a) shows the period when the power to the pachinko machine 10 is ON, FIG. 160(b) shows the period when the setting key insertion unit 68a is ON, FIG. 160(c) shows the period when the setting value update process (FIG. 157) is being executed, FIG. 160(d) shows the period when the setting confirmation process (FIG. 155) is being executed, and FIG. 160(e) shows the period when power outage processing is being executed.

First, we will explain the normal execution of the setting value update process (Figure 157) and setting confirmation process (Figure 155).

At timing t1, as shown in Figure 160(b), the setting key insertion section 68a is turned ON using the setting key, and then at timing t2, as shown in Figure 160(a), the power to the pachinko machine 10 is turned ON. In this case, the reset button 68c is also pressed. Therefore, at timing t3, as shown in Figure 160(c), the setting value update process (Figure 157) is initiated. Thereafter, at timing t4, as shown in Figure 160(b), the setting key insertion section 68a changes from an ON state to an OFF state. This ends the setting value update process (Figure 157) as shown in Figure 160(c).

Furthermore, at timing t5, as shown in FIG. 160(b), the setting key insertion section 68a is turned ON using the setting key, and then at timing t6, as shown in FIG. 160(a), the power to the pachinko machine 10 is turned ON. In this case, the reset button 68c is not pressed. Therefore, at timing t7, as shown in FIG. 160(d), the setting confirmation process (FIG. 155) is started. Thereafter, at timing t8, as shown in FIG. 160(b), the setting key insertion section 68a changes from an ON state to an OFF state. This ends the setting confirmation process (FIG. 155), as shown in FIG. 160(d).

Next, we will explain what happens when power outage processing is performed during the setting value update processing (Figure 157) and the status is "no operation" when the supply of operating power is subsequently resumed.

At timing t9, as shown in FIG. 160(b), the setting key insertion section 68a is turned ON using the setting key, and then at timing t10, as shown in FIG. 160(a), the power to the pachinko machine 10 is turned ON. In this case, the reset button 68c is also pressed. Therefore, at timing t11, as shown in FIG. 160(c), the setting value update process (FIG. 157) is started. Then, at timing t12 while the setting value update process (FIG. 157) is being executed, the power to the pachinko machine 10 is turned OFF or a sudden commercial power outage occurs, turning the power OFF as shown in FIG. 160(a), and power outage processing is started as shown in FIG. 160(e). In this case, the setting value update process (FIG. 157) ends at timing t12 as shown in FIG. 160(c), and power outage processing ends at timing t13 as shown in FIG. 160(e).

After that, at timing t14, the setting key insertion section 68a is turned OFF as shown in Figure 160(b), and in this state, at timing t15, the power to the pachinko machine 10 is turned ON as shown in Figure 160(a). In this case, the reset button 68c is not pressed. In other words, the power to the pachinko machine 10 is turned ON without any operation. However, the last time the power to the pachinko machine 10 was turned OFF, power outage processing was executed during the setting value update processing (Figure 157). Therefore, at timing t16, the setting value update processing (Figure 157) is started as shown in Figure 160(c). In this case, the setting value update process (FIG. 157) is terminated when it is determined that the setting key insertion section 68a has switched from an ON state to an OFF state, so even if the setting key insertion section 68a has been maintained in an OFF state since the start of the setting value update process (FIG. 157), the termination condition for the setting value update process (FIG. 157) is not met.

Then, at timing t17 while the setting value update process (Fig. 157) is being executed, the setting key insertion section 68a is turned ON using the setting key, as shown in Fig. 160(b), and then at timing t18, as shown in Fig. 160(b), the setting key insertion section 68a changes from being turned ON to being turned OFF. This ends the setting value update process (Fig. 157), as shown in Fig. 160(c).

Next, we will explain what happens when power outage processing is performed during the settings confirmation processing (Figure 155) and the status is "no operation" when the supply of operating power is subsequently resumed.

At timing t19, the setting key insertion section 68a is turned ON using the setting key, as shown in FIG. 160(b), and then at timing t20, the power to the pachinko machine 10 is turned ON, as shown in FIG. 160(a). In this case, the reset button 68c is not pressed. Therefore, at timing t21, the setting confirmation process (FIG. 155) is started, as shown in FIG. 160(d). Then, at timing t22 while the setting confirmation process (FIG. 155) is being executed, the power to the pachinko machine 10 is turned OFF or a sudden commercial power outage occurs, turning the power OFF as shown in FIG. 160(a), and power outage processing is started, as shown in FIG. 160(e). In this case, the setting confirmation process (FIG. 155) ends at timing t22, as shown in FIG. 160(d), and power outage processing ends at timing t23, as shown in FIG. 160(e).

After that, at timing t24, the setting key insertion section 68a is turned OFF as shown in Figure 160(b), and in this state, at timing t25, the power to the pachinko machine 10 is turned ON as shown in Figure 160(a). In this case, the reset button 68c is not pressed. In other words, the power to the pachinko machine 10 is turned ON without any operation. However, the last time the power to the pachinko machine 10 was turned OFF, power outage processing was executed in the middle of the setting confirmation processing (Figure 155). Therefore, at timing t26, the setting confirmation processing (Figure 155) is started as shown in Figure 160(d). In this case, the setting confirmation process (FIG. 155) is terminated when it is determined that the setting key insertion unit 68a has switched from an ON state to an OFF state, so even if the setting key insertion unit 68a has been maintained in an OFF state since the start of the setting confirmation process (FIG. 155), the termination condition for the setting confirmation process (FIG. 155) is not met.

After that, at timing t27 while the setting confirmation process (Fig. 155) is being executed, the setting key insertion section 68a is turned ON using the setting key, as shown in Fig. 160(b), and then at timing t28, as shown in Fig. 160(b), the setting key insertion section 68a changes from being turned ON to being turned OFF. This ends the setting confirmation process (Fig. 155), as shown in Fig. 160(d).

The present embodiment described above provides the following excellent effects:

In order for the setting value update process (Fig. 157) to be executed, when the supply of operating power begins, it is necessary to perform a "setting change operation" by turning on the setting key insertion section 68a and pressing the reset button 68c. This makes it difficult to attempt to change the setting values illegally. In this case, if the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, the setting value update process (Fig. 157) can be executed when the supply of operating power is resumed, even if a "setting change operation" has not been performed. This makes it possible to prioritize the execution of the setting value update process (Fig. 157).

If the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and then the "setting confirmation operation" is performed to check the setting values when the supply of operating power is resumed, the setting value update process (Fig. 157) will be executed instead of the setting confirmation process (Fig. 155). This makes it possible to prioritize changing the setting values over checking the setting values, and prevents gameplay from starting even when the setting value changes for the target device have not actually been completed.

When the setting value update process (Figure 157) is being executed, the setting values selected to be updated are displayed on the first to fourth notification display devices 201-204. This makes it possible to change the setting values while understanding the setting values selected to be updated. Furthermore, by displaying the setting values selected to be updated in this way, it is possible to essentially check the setting values even in a configuration where the setting value update process (Figure 157) takes priority when the "setting confirmation operation" has been performed when the supply of operating power is resumed.

When the setting value update process (Fig. 157) is being executed, the first to fourth notification display devices 201-204 not only display the setting values selected for update, but also display the status of the setting value update process (Fig. 157) being executed. This makes it easier for the amusement hall manager to know that the setting value update process (Fig. 157) has started, even if the "setting confirmation operation" was performed when the supply of operating power is resumed.

If the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and the supply of operating power is subsequently resumed if "no operation" is performed or if a "setting confirmation operation" is performed, the setting value will be changed from the setting value selected before the supply of operating power was stopped. This makes it possible to continue changing the setting value from the setting value selected before the supply of operating power was stopped.

If the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and then the supply of operating power is resumed and a "setting change operation" is performed, the setting value will be changed from the currently used setting value. This makes it possible to change the initial setting value when starting to change the setting value depending on the operation content when the supply of operating power is resumed.

Even if the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, the setting value update process (Fig. 157) will not be executed if the "RAM clear operation" is performed when the supply of operating power is resumed. As a result, even if the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, if there is no need to execute the setting value update process (Fig. 157) afterwards, the "RAM clear operation" can be performed when the supply of operating power is resumed to prevent the setting value update process (Fig. 157) from being executed.

In order for the setting confirmation process (Fig. 155) to be executed, when the supply of operating power is started, it is necessary to perform a "setting confirmation operation" by turning on the setting key insertion section 68a. This makes it difficult to attempt to illegally check the setting values. In this case, if the supply of operating power is stopped while the setting confirmation process (Fig. 155) is being executed, the setting confirmation process (Fig. 155) may be executed when the supply of operating power is resumed, even if the "setting confirmation operation" has not been performed. This makes it possible to prioritize the execution of the setting confirmation process (Fig. 155).

Even if the supply of operating power is stopped while the setting confirmation process (Fig. 155) is being executed, if the supply of operating power is resumed and a "setting change operation" is performed, the setting value update process (Fig. 157) will be executed without executing the setting confirmation process (Fig. 155). This makes it possible to prioritize setting value changes over setting value confirmation.

The work area 221 for specific control is provided with a setting reference area 341 and a setting update area 342. Information corresponding to the setting values to be used is stored in the setting reference area 341, and information corresponding to setting values that are in the process of being changed while the setting value update process (Figure 157) is being executed is stored in the setting update area 342. This makes it possible to change the setting values to be updated in the setting value update process (Figure 157) while storing and retaining information about the setting values that were set before the setting value update process (Figure 157) was started in the setting reference area 341.

If the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and if "no operation" or a "setting confirmation operation" is performed when the supply of operating power is subsequently resumed, the setting value will begin changing from the setting value corresponding to the information stored in the setting update area 342, and if a "setting change operation" is performed when the supply of operating power is subsequently resumed, the setting value will begin changing from the setting value corresponding to the information stored in the setting reference area 341. This makes it possible to appropriately handle each of these situations.

In order to start the setting value update process (Fig. 157), it is necessary to use the setting key to turn the setting key insertion section 68a ON, making it difficult to illegally start the setting value update process (Fig. 157). In this case, the setting value update process (Fig. 157) will not end simply because the setting key insertion section 68a is turned OFF, but will end if the setting key insertion section 68a is turned OFF from an ON state. As a result, even if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the setting value update process (FIG. 157) is started when the supply of operating power is subsequently resumed and the setting key insertion unit 68a is in the OFF state due to "no operation," the setting value update process (FIG. 157) will not be terminated immediately. Instead, the setting value update process (FIG. 157) can be terminated by first turning the setting key insertion unit 68a ON and then turning it OFF, making it possible for the amusement hall manager to terminate the setting value update process (FIG. 157) at a time that is convenient for them.

In order to start the setting confirmation process (Fig. 155), it is necessary to use the setting key to turn on the setting key insertion section 68a, making it difficult to fraudulently start the setting confirmation process (Fig. 155). In this case, the setting confirmation process (Fig. 155) will not end simply because the setting key insertion section 68a is turned off, but will end if the setting key insertion section 68a is turned off from an ON state. As a result, even if the supply of operating power is stopped while the setting confirmation process (FIG. 155) is being executed, and the setting confirmation process (FIG. 155) is started when the supply of operating power is subsequently resumed and the setting key insertion unit 68a is in the OFF state due to "no operation," the setting confirmation process (FIG. 155) will not be immediately terminated. Instead, the setting confirmation process (FIG. 155) can be terminated by first turning the setting key insertion unit 68a ON and then turning it OFF, making it possible for the amusement hall manager to terminate the setting confirmation process (FIG. 155) at a time that is convenient for them.

When the supply of operating power to the main CPU 63 begins, an initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps SA401 to SA418) and before the remaining processing (steps SA422 to SA425) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, thereby reducing the processing load while the processing at the start of the supply of operating power is being executed.

The setting confirmation process (Figure 155) and setting value update process (Figure 157) are executed as processes when the supply of operating power starts, whereas the initial check period starts after the processes when the supply of operating power starts have finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

When the supply of operating power to the main CPU 63 begins, a check display is displayed on the first to fourth alarm display devices 201-204, regardless of whether the setting confirmation process (Figure 155) or the setting value update process (Figure 157) is executed, or whether neither the setting confirmation process (Figure 155) nor the setting value update process (Figure 157) is executed. This makes it possible to check whether the first to fourth alarm display devices 201-204 are normal, regardless of the situation when the supply of operating power to the main CPU 63 begins.

The main processing (FIG. 153) of the master CPU 63 is a process that is executed both when either the setting confirmation processing (FIG. 155) or the setting value update processing (FIG. 157) is executed, and when neither the setting confirmation processing (FIG. 155) nor the setting value update processing (FIG. 157) is executed. When either the setting confirmation processing (FIG. 155) or the setting value update processing (FIG. 157) is executed, a process that starts a check display on the first to fourth alarm display devices 201 to 204 is set as a process that is executed later in the order of execution than the setting confirmation processing (FIG. 155) and the setting value update processing (FIG. 157). In this way, by setting the process that starts a check display on the first to fourth alarm display devices 201 to 204 as a common process, it is possible to achieve the excellent effects already described while simplifying the processing configuration.

The main CPU 63 can start processing to progress the game even when a check display is being executed on the first through fourth notification display devices 201 through 204. This makes it possible to prevent delays in the start of processing to progress the game, even in a configuration in which a check display is executed on the first through fourth notification display devices 201 through 204 after the setting confirmation process (FIG. 155) or setting value update process (FIG. 157) is executed.

Note that if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and if the supply of operating power is resumed and there is "no operation," the setting value update process (FIG. 157) is not limited to being configured to start from the setting value that was being changed before the supply of operating power was stopped, but may be configured to start from the setting value currently being used that is stored in the setting reference area 341. Also, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and if the supply of operating power is resumed and there is "no operation," the setting value update process (FIG. 157) may be configured to be executed after the RAM clear process (step SA416) is executed, or the RAM clear process (step SA416) may be executed after the setting value update process (FIG. 157).

Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the supply of operating power is resumed and there is no operation, the setting value update process (FIG. 157) may not be executed. In this case, the setting value information stored in the setting reference area 341 may be overwritten in the setting update area 342 when the next setting value update process (FIG. 157) is started.

In addition, if the supply of operating power is stopped while the setting confirmation process (Fig. 155) is being executed, and the supply of operating power is resumed, the setting confirmation process (Fig. 155) may not be executed if "no operation" is performed.

Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and then the supply of operating power is resumed and a "RAM clear operation" is performed, the setting value update process (FIG. 157) may be executed after the RAM clear process (step SA416) is executed. In this case, the setting value update process (FIG. 157) may be configured to start from the setting value that was being changed before the supply of operating power was stopped, or may be configured to start from the setting value currently being used that is stored in the setting reference area 341.

Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the supply of operating power is resumed and a "RAM clear operation" is performed, the setting value update process (FIG. 157) may be executed without executing the RAM clear process (step SA416), or the RAM clear process (step SA416) may be executed after the setting value update process (FIG. 157) is executed. In this case, the setting value update process (FIG. 157) may be configured to start from the setting value that was being changed before the supply of operating power was stopped, or may be configured to start from the setting value currently being used that is stored in the setting reference area 341.

Furthermore, if the supply of operating power is stopped while the setting confirmation process (FIG. 155) is being executed, and the supply of operating power is resumed and a "RAM clear operation" is performed, the setting confirmation process (FIG. 155) may be executed after the RAM clear process (step SA416), or the setting confirmation process (FIG. 155) may be executed without executing the RAM clear process (step SA416), or the RAM clear process (step SA416) may be executed after the setting confirmation process (FIG. 155).

Furthermore, if the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and then the supply of operating power is resumed and a "setting change operation" is performed, the setting value update process (Fig. 157) is configured to start from the setting value currently in use that is stored in the setting reference area 341. However, the setting value update process (Fig. 157) may also be configured to start from the setting value that was in the middle of being changed before the supply of operating power was stopped.

Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and then the supply of operating power is resumed and a "setting change operation" is performed, the setting value update process (FIG. 157) may be executed without executing the RAM clear process (step SA416), or the RAM clear process (step SA416) may be executed after the setting value update process (FIG. 157) is executed. In this case, the setting value update process (FIG. 157) may be configured to start from the setting value that was being changed before the supply of operating power was stopped, or may be configured to start from the setting value currently being used that is stored in the setting reference area 341.

Furthermore, if the supply of operating power is stopped while the setting confirmation process (Fig. 155) is being executed, and then the supply of operating power is resumed and a "setting change operation" is performed, the setting value update process (Fig. 157) is configured to start from the currently used setting value stored in the setting reference area 341. However, the setting value update process (Fig. 157) may also be configured to start from the setting value that was in the middle of being changed before the supply of operating power was stopped.

Furthermore, if the supply of operating power is stopped while the setting confirmation process (Figure 155) is being executed, and the supply of operating power is resumed and a "setting change operation" is performed, the setting value update process (Figure 157) may be executed without executing the RAM clear process (step SA416), or the RAM clear process (step SA416) may be executed after the setting value update process (Figure 157) is executed.

Furthermore, if the supply of operating power is stopped while the setting confirmation process (FIG. 155) is being executed, and then the supply of operating power is resumed and a "setting change operation" is performed, the setting confirmation process (FIG. 155) may be executed without the setting value update process (FIG. 157) being executed, or the setting value update process (FIG. 157) may be executed after the setting confirmation process (FIG. 155) is executed, or the setting value update process (FIG. 157) may be executed after the setting confirmation process (FIG. 155) is executed. Furthermore, if the supply of operating power is stopped while the setting confirmation process (FIG. 155) is being executed, and then the supply of operating power is resumed and a "setting change operation" is performed, then neither the setting confirmation process (FIG. 155) nor the setting value update process (FIG. 157) may be executed.

Furthermore, if the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and the supply of operating power is resumed and a "setting confirmation operation" is performed, the setting value update process (Fig. 157) is not limited to being configured to start from the setting value that was being changed before the supply of operating power was stopped, but may also be configured to start from the setting value currently being used that is stored in the setting reference area 341.

Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the supply of operating power is resumed and a "setting confirmation operation" is performed, the setting value update process (FIG. 157) may be executed after the RAM clear process (step SA416) is executed, or the setting value update process (FIG. 157) may be executed after the RAM clear process (step SA416) is executed.

Also, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the supply of operating power is resumed and a "settings confirmation operation" is performed, the setting confirmation process (FIG. 155) may be executed without executing the setting value update process (FIG. 157). In this case, the setting value information stored in the setting reference area 341 may be overwritten in the setting update area 342 when the next setting value update process (FIG. 157) is started.

Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the supply of operating power is resumed and a "setting confirmation operation" is performed, the setting value update process (FIG. 157) may be configured to be executed after the setting confirmation process (FIG. 155), or the setting value update process (FIG. 157) may be configured to be executed after the setting confirmation process (FIG. 155). Furthermore, if the supply of operating power is stopped while the setting value update process (FIG. 157) is being executed, and the supply of operating power is resumed and a "setting confirmation operation" is performed, neither the setting confirmation process (FIG. 155) nor the setting value update process (FIG. 157) may be configured to be executed.

Furthermore, if the supply of operating power is initiated when the setting update display flag in the specific control work area 221 is set to "1," the second timer interrupt process (Fig. 134) is permitted to interrupt after a predetermined wait time has elapsed in the power-on initial setting process (step SA401), and the first to fourth alarm display devices 201 to 204 are thereby not limited to displaying an indication that the setting values are being updated and an indication of the setting values corresponding to the information stored in the setting update area 342; these indications may be initiated without waiting for the predetermined wait time to elapse. Furthermore, even if the setting update display flag is set to "1," the first to fourth alarm display devices 201 to 204 may be configured to display an indication that the setting values are being updated and an indication of the setting values corresponding to the information stored in the setting update area 342, provided that the setting value update process (Fig. 157) is being executed. In this case, it is possible to prevent these displays from occurring when the setting value update process (Figure 157) is not being executed.

Furthermore, if the supply of operating power is initiated when the setting confirmation display flag in the specific control work area 221 is set to "1," the second timer interrupt process (Fig. 134) is permitted to interrupt after a predetermined wait time has elapsed in the power-on initial setting process (step SA401), and the first to fourth alarm display devices 201 to 204 are thereby not limited to displaying an indication that the setting values are being confirmed and an indication of the setting values corresponding to the information stored in the setting reference area 341; these indications may be initiated without waiting for the predetermined wait time to elapse. Furthermore, even if the setting confirmation display flag is set to "1," the first to fourth alarm display devices 201 to 204 may be configured to display an indication that the setting values are being confirmed and an indication of the setting values corresponding to the information stored in the setting update area 342, provided that the setting confirmation process (Fig. 155) is being executed. In this case, it is possible to prevent these messages from being displayed when the settings confirmation process (Figure 155) is not being executed.

Furthermore, when the setting value update process (Figure 157) is being executed, the pattern display device 41 may be configured to display an image indicating that the setting value is being updated, and in addition to or instead of this display, an image showing the operating procedure for updating the setting value may be displayed, and the display light-emitting unit 53 or speaker unit 54 may be configured to issue a notification indicating that the setting value is being updated. In this case, it is possible to clearly make the amusement hall manager aware that the setting value update process (Figure 157) is being executed.

Furthermore, when the setting confirmation process (Figure 155) is being executed, the pattern display device 41 may be configured to display an image indicating that the setting value is being confirmed, and in addition to or instead of this display, an image showing the operating procedure for confirming the setting value may be displayed, or the display light-emitting unit 53 or speaker unit 54 may be configured to issue a notification indicating that the setting value is being confirmed. In this case, it is possible to clearly make the amusement hall manager aware that the setting confirmation process (Figure 155) is being executed.

The operating unit operated to update the setting value in the setting value update process (Figure 157) is not limited to the reset button 68c, but may be a dedicated operating unit such as the update button 68b, or an operating unit provided on the main control unit 60 for canceling an abnormal state. Furthermore, when a setting key is inserted into the setting key insertion unit 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" may be set as the rotation position, and the setting value corresponding to the rotation position of the setting key insertion unit 68a may be set. Furthermore, the setting key insertion unit 68a may be configured to be able to be rotated further than the ON position, and each time a rotation operation beyond the ON position is performed, the setting value being updated is updated to the next setting value in the sequence.

Furthermore, when the setting value update process (Figure 157) is executed, the pachinko machine 10 may be configured to output a corresponding signal to the amusement hall's management computer. In this case, the signal output may be configured to be performed for a predetermined period of time (e.g., 100 milliseconds), and the signal output may be configured to continue while the setting value update process (Figure 157) is being executed. This allows the amusement hall's management computer to know that the setting value update process (Figure 157) has been executed in the pachinko machine 10.

Furthermore, when the setting confirmation process (Fig. 155) is executed, the pachinko machine 10 may be configured to output a corresponding signal to the amusement hall's management computer. In this case, the signal output may be configured to continue for a predetermined period of time (e.g., 100 milliseconds), or the signal output may be configured to continue while the setting confirmation process (Fig. 155) is being executed. This allows the amusement hall's management computer to know that the setting confirmation process (Fig. 155) has been executed on the pachinko machine 10.

Furthermore, the configuration in which processing is terminated when a key insertion unit is changed from an ON state to an OFF state may be applied to processes other than the setting confirmation process (FIG. 155) and the setting value update process (FIG. 157). For example, a configuration may be adopted in which a specific key insertion unit must be operated to the ON position in order to display the base value on the first to fourth notification display devices 201 to 204, and the display may be terminated when it is determined that the specific key insertion unit has been changed from an ON state to an OFF state.

Also, the configuration may be such that the condition for starting the setting value update process (Fig. 157) is that the opening target, which is at least one of the gaming machine main body 12 and the front door frame 14, has been operated to open. In this configuration, if the supply of operating power is stopped while the setting value update process (Fig. 157) is being executed, and if "no operation" or a "setting confirmation operation" is performed when the supply of operating power is resumed, the setting value update process (Fig. 157) may be started even if the opening target has not been operated to open.

Also, the configuration may be such that the condition for starting the setting confirmation process (Fig. 155) is that the target to be opened, which is at least one of the gaming machine main body 12 and the front door frame 14, has been operated to open. In this configuration, if the supply of operating power is stopped while the setting confirmation process (Fig. 155) is being executed and "no operation" is displayed when the supply of operating power is resumed, the setting confirmation process (Fig. 155) may be started even if the target to be opened has not been operated to open.

Furthermore, the areas to be initialized in the main RAM 65 may be different between the RAM clearing process executed before the setting value update process (Figure 157) and the RAM clearing process executed without the setting value update process being executed.

Furthermore, when the setting value update process (Fig. 157) is initiated when the setting update display flag is not set to "1," the setting value is not limited to being changed from the setting value corresponding to the information stored in the setting reference area 341, but may be changed from a predetermined initial setting value. The initial value may be, for example, "Setting 1," "Setting 6," or another setting value.

Furthermore, in addition to or instead of a configuration in which the setting value update process (FIG. 157) is executed as a process when the supply of operating power starts, a configuration in which the setting value update process (FIG. 157) is executed based on a "setting change operation" being performed after the processing when the supply of operating power starts has finished may be adopted. Even in this configuration, if the setting value update process (FIG. 157) finishes before the normal termination trigger occurs, the setting value update process (FIG. 157) can be configured to be executed even if a "setting change operation" has not been performed, making it possible to prioritize the setting value change work.

In addition to or instead of a configuration in which the setting confirmation process (FIG. 155) is executed as a process when the supply of operating power begins, a configuration in which the setting confirmation process (FIG. 155) is executed based on a "setting confirmation operation" being performed after the processing when the supply of operating power begins has ended may be adopted. Even in this configuration, if the setting confirmation process (FIG. 155) ends before the normal termination trigger occurs, the setting confirmation process (FIG. 155) will be executed even if a "setting confirmation operation" has not been performed, making it possible to prioritize the task of checking the setting values.

<Forty-sixth embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the above-mentioned 45th embodiment. The configuration that differs from the above-mentioned 45th embodiment will be described below. Note that the description of the configuration that is the same as the above-mentioned 45th embodiment will basically be omitted.

Figure 161 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SA901 to SA925 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Steps SA901 to SA904 are identical to steps SA401 to SA404 of the main processing (Figure 153) in the 45th embodiment. Then, a determination is made as to whether the setting update display flag provided in the specific control work area 221 is set to "1" (step SA905). If the supply of operating power is stopped and then resumed while the setting value update processing (step SA918) is being performed, the main processing will be started with the setting update display flag set to "1."

If a negative judgment is made in step SA905, it is determined whether the reset button 68c has been pressed (step SA906). In other words, it is determined whether the power to the pachinko machine 10 has been turned on while the reset button 68c has been pressed, and whether the supply of operating power to the main CPU 63 has begun.

If the reset button 68c is not pressed (step SA906: NO), it is determined whether the power outage flag provided in the specific control work area 221 is set to "1" (step SA907). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step SA907: YES), a checksum is calculated for the specific control work area 221 and the specific control stack area 222 (step SA908). The checksum calculation method is the same as in the 33rd embodiment. Then, the checksums for the specific control work area 221 and the specific control stack area 222 calculated and stored in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped are read, and the read checksums are compared with the checksum calculated in step SA908 (step SA909). It is then determined whether the checksums match (step SA910).

If a negative judgment is made in step SA907 or step SA910, i.e., if the power outage flag is not set to "1" or the checksums do not match, the game stop flag provided in the specific control work area 221 is set to "1" (step SA911). In addition, an abnormality command indicating that an abnormality has occurred with the power outage flag or checksum when the supply of operating power begins is sent to the audio and light emission control device 81 (step SA912). The processing content of these steps SA911 and SA912 is the same as step SA410 and step SA411 of the main processing (Figure 153) in the 45th embodiment described above.

If the power outage flag is set to "1" and the checksum is normal (step SA907 and step SA910: YES), it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step SA913). If the setting key insertion unit 68a has been turned ON using the setting key (step SA913: YES), a setting confirmation process is executed (step SA914). The content of the setting confirmation process is the same as that of the 45th embodiment. In other words, in this embodiment, even if the setting confirmation display flag provided in the specific control work area 221 is set to "1," the setting confirmation process is not executed unless the setting key insertion unit 68a is turned ON. Therefore, even if the supply of operating power is stopped while the setting confirmation process is being executed, the setting confirmation process is not executed unless the supply of operating power is resumed when the "setting confirmation operation" is performed.

If the setting update display flag is set to "1" (step SA905: YES), or if the reset button 68c is pressed (step SA906: YES), RAM clear processing is executed (step SA915). The content of the RAM clear processing is the same as the RAM clear processing (step SA416) in the main processing (Figure 153) in the 45th embodiment described above.

If the setting update display flag is set to "1" (step SA916: YES), the setting value update process is executed (step SA918) regardless of whether the setting key insertion unit 68a is turned ON. On the other hand, if the setting update display flag is not set to "1" (step SA916: NO), the setting value update process is executed (step SA918) on the condition that the setting key insertion unit 68a is turned ON (step SA917: YES). In other words, if the supply of operating power is stopped while the setting value update process is being executed, the RAM clear process (step SA915) is executed, and then the setting value update process (step SA918) is newly started, regardless of the operation performed when the supply of operating power is subsequently resumed.

When step SA912 is executed, when a negative determination is made in step SA913, when step SA914 is executed, when a negative determination is made in step SA917, or when step SA918 is executed, steps SA919 to SA925 are executed. The processing content of steps SA919 to SA925 is the same as steps SA419 to SA425 in the main processing (Figure 153) in the 45th embodiment described above.

Figure 162 is an explanatory diagram illustrating the processing executed in the main processing (Figure 161) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (step SA918) or setting confirmation processing (step SA914) is being executed.

If power outage processing is performed when neither the setting value update processing (step SA918) nor the setting confirmation processing (step SA914) has been performed, the content of the processing performed in the main processing (Fig. 161) when the supply of operating power is subsequently resumed is the same as in the 45th embodiment. In other words, if the supply of operating power is resumed in a "no operation" situation, the RAM clear processing (step SA915), setting value update processing (step SA918), and setting confirmation processing (step SA914) are not performed in the main processing (Fig. 161). Furthermore, if the supply of operating power is resumed in a situation where a "RAM clear operation" has been performed, the RAM clear processing (step SA915) is performed in the main processing (Fig. 161), but the setting value update processing (step SA918) and setting confirmation processing (step SA914) are not performed. If the supply of operating power is resumed when a "settings change operation" has been performed, the main processing (FIG. 161) executes a RAM clear process (step SA915) and a setting value update process (step SA918), but does not execute a setting confirmation process (step SA914). If the supply of operating power is resumed when a "settings confirmation operation" has been performed, the main processing (FIG. 161) executes a setting confirmation process (step SA914), but does not execute a RAM clear process (step SA915) or a setting value update process (step SA918).

Next, we will explain the processing that is executed in the main processing (Figure 161) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (step SA918) is being executed (i.e., when the setting update display flag is set to "1").

When the supply of operating power is resumed without any operation, when a RAM clear operation is performed, when a setting change operation is performed, or when a setting check operation is performed, the main processing (FIG. 161) executes a RAM clear process (step SA915) and a setting value update process (step SA918), but does not execute a setting check process (step SA914). In other words, if power outage processing is executed while the setting value update process (step SA918) is being executed, regardless of the operation performed when the supply of operating power is subsequently resumed, the RAM clear process (step SA915) is executed and then the setting value update process (step SA918) is newly initiated.

With the above configuration, if the supply of operating power is stopped during the setting value update process (step SA918), when the supply of operating power is resumed, the RAM clear process (step SA915) is executed and the setting value update process (step SA918) is restarted anew, regardless of the operation of the setting key insertion section 68a and the reset button 68c when the pachinko machine 10 is powered on. This ensures that if the supply of operating power is stopped during a setting value update, an opportunity to update the setting value and then complete the process is provided if the supply of operating power is subsequently resumed. Therefore, even if the supply of operating power is stopped during a setting value update, if the supply of operating power is subsequently resumed, it is possible to prevent gameplay from starting with the setting values that were in effect before the previous setting value update process (step SA918) was started.

Furthermore, if the supply of operating power is stopped during the setting value update process (step SA918), the setting value update process (step SA918) is executed after the RAM clear process (step SA915) regardless of the operation content when the supply of operating power is resumed. This makes it possible to achieve the above-mentioned excellent effects while simplifying the processing configuration compared to a configuration in which the processing content to be executed changes depending on the operation content.

Next, we will explain the processing that is executed in the main processing (Figure 161) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting confirmation processing (step SA914) is being executed (i.e., the setting confirmation display flag is set to "1").

If power outage processing is executed while the setting confirmation processing (step SA914) is being executed (i.e., while the setting confirmation display flag is set to "1"), the processing executed in the main processing (FIG. 161) when the supply of operating power is subsequently resumed is the same as the processing executed in the main processing (FIG. 161) when power outage processing is executed while neither the setting value update processing (FIG. 157) nor the setting confirmation processing (FIG. 155) is being executed and the supply of operating power is subsequently resumed. In other words, even if the supply of operating power is stopped while the setting confirmation processing (step SA914) is being executed, when the supply of operating power is subsequently resumed, processing corresponding to the operation performed when the pachinko machine 10 was turned on will be executed.

Unlike changing the setting values, checking the setting values does not affect gameplay even if it is terminated midway and not resumed. Therefore, even if the supply of operating power is interrupted while checking the setting values, by having the process corresponding to the operation performed when the pachinko machine 10 is turned on executed, it is possible to give priority to the operation performed when the power is turned on by the gaming hall manager.

<Forty-seventh embodiment>
In this embodiment, when a power outage process is executed while the setting value update process (step SA918) or the setting confirmation process (step SA914) is being executed, the content of the process executed in the main process (FIG. 161) upon resumption of the supply of operating power thereafter differs from that of the 45th embodiment. The following describes the configuration that differs from the 45th embodiment. Note that a description of the same configuration as the 45th embodiment will generally be omitted.

Figure 163 is an explanatory diagram for explaining the processing executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (Figure 157) or setting confirmation processing (Figure 155) is being executed.

If power outage processing is executed when neither the setting value update processing (FIG. 157) nor the setting confirmation processing (FIG. 155) is being executed, the content of the processing executed in the main processing (FIG. 153) when the supply of operating power is subsequently resumed is the same as in the 45th embodiment. Also, if power outage processing is executed when the setting confirmation processing (step FIG. 155) is being executed (i.e., when the setting confirmation display flag is set to "1"), the content of the processing executed in the main processing (FIG. 153) when the supply of operating power is subsequently resumed is the same as in the 46th embodiment.

If power outage processing is performed while the setting value update processing (Fig. 157) is being executed (i.e., the setting update display flag is set to "1"), the processing executed in the main processing (Fig. 153) when the supply of operating power is subsequently resumed is, in the case of "no operation" or "setting confirmation operation," the setting value update processing (Fig. 157) is resumed, as in the 45th embodiment above. Furthermore, in the case of "RAM clear operation" and "setting change operation," the setting value update processing (Fig. 157) is resumed after the RAM clear processing (step SA416) is executed. In this case, in the RAM clear processing (step SA416), not only the setting reference area 341 provided in the work area 221 for specific control, but also the setting update display flag and setting update area 342 provided in the work area 221 for specific control are excluded from initialization. Therefore, even if the RAM clear process (step SA416) is executed while the setting update display flag is set to "1," the setting update display flag will be set to "1" when the subsequent setting value update process (FIG. 157) begins, and setting value updating will begin from the setting value information currently stored in the setting update area 342.

With the above configuration, if the supply of operating power is stopped while updating the setting value, not only is the setting value update process (Fig. 157) executed reliably when the supply of operating power is subsequently resumed, but it is also possible to resume updating the setting value from the setting value that was in the middle of being updated immediately before the supply of operating power was stopped. This makes it possible to continue changing the setting value as is.

<Forty-eighth embodiment>
In this embodiment, when a power outage process is executed while the setting value update process (step SA918) or the setting confirmation process (step SA914) is being executed, the content of the process executed in the main process (FIG. 161) upon resumption of the supply of operating power thereafter differs from that of the 45th embodiment. The following describes the configuration that differs from the 45th embodiment. Note that a description of the same configuration as the 45th embodiment will generally be omitted.

Figure 164 is an explanatory diagram for explaining the processing executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (Figure 157) or setting confirmation processing (Figure 155) is being executed.

If power outage processing is executed when neither the setting value update processing (FIG. 157) nor the setting confirmation processing (FIG. 155) is being executed, the content of the processing executed in the main processing (FIG. 153) when the supply of operating power is subsequently resumed is the same as in the 45th embodiment. Also, if power outage processing is executed when the setting confirmation processing (step FIG. 155) is being executed (i.e., when the setting confirmation display flag is set to "1"), the content of the processing executed in the main processing (FIG. 153) when the supply of operating power is subsequently resumed is the same as in the 46th embodiment.

When power outage processing is executed in a situation where the setting value update processing (Figure 157) is being executed (i.e., when the setting update display flag is set to "1"), the content of the processing executed in the main processing (Figure 153) when the supply of operating power is subsequently resumed is the same as the content of the processing executed in the main processing (Figure 153) when power outage processing is executed in a situation where neither the setting value update processing (Figure 157) nor the setting confirmation processing (Figure 155) is being executed, in the cases of "no operation," "RAM clear operation," and "setting confirmation operation." In other words, in the case of "no operation," none of the RAM clear processing (step SA416), setting value update processing (FIG. 157), and setting confirmation processing (FIG. 155) are executed; in the case of a "RAM clear operation," the RAM clear processing (step SA416) is executed, but the setting value update processing (FIG. 157) and setting confirmation processing (FIG. 155) are not executed; and in the case of a "setting confirmation operation," the setting confirmation processing (FIG. 155) is executed, but the RAM clear processing (step SA416) and setting value update processing (FIG. 157) are not executed.

In contrast, in the case of a "setting change operation," the setting value update process (FIG. 157) is resumed after the RAM clear process (step SA416) is executed. In this case, the RAM clear process (step SA416) excludes from initialization not only the setting reference area 341 provided in the work area 221 for specific control, but also the setting update display flag and setting update area 342 provided in the work area 221 for specific control. Therefore, even if the RAM clear process (step SA416) is executed when the setting update display flag is set to "1," the setting update display flag will be set to "1" when the subsequent setting value update process (FIG. 157) begins, and the setting value update will begin from the setting value information currently stored in the setting update area 342.

With the above configuration, even if the supply of operating power is interrupted while the setting value is being updated, it is possible to prioritize the execution of processing corresponding to the operation performed by the amusement hall manager when the supply of operating power is subsequently resumed.

In addition, if the supply of operating power is stopped while a setting value is being updated, and the supply of operating power is resumed while a "setting change operation" is being performed, it is possible to resume updating the setting value from the setting value that was in the middle of being updated just before the supply of operating power was stopped. This makes it possible to continue changing the setting value as is.

<Forty-ninth embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the above-mentioned 45th embodiment. The configuration that differs from the above-mentioned 45th embodiment will be described below. Note that the description of the configuration that is the same as the above-mentioned 45th embodiment will basically be omitted.

Figure 165 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SB101 to SB128 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, the power-on initialization process is executed (step SB101). During the power-on initialization process, for example, the main process is started and the process waits until a predetermined waiting time (specifically, one second) has elapsed before proceeding to the next process. During this predetermined waiting period, the operation of the pattern display device 41 is started and the initial settings are completed. Access to the main RAM 65 is also permitted.

Then, the internal function register setting process is executed (step SB102). In the internal function register setting process, as in the 35th embodiment, the interrupt period of the first timer interrupt process (FIG. 133), which is a process that periodically interrupts the main process and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt process (FIG. 134), which is a process that periodically interrupts the main process and is started, is set to a second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, as in the 35th embodiment, there are first timer interrupt processing (FIG. 133) and second timer interrupt processing (FIG. 134) so that the interrupt periods are relatively long and short as timer interrupt processing. Both the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are started by interrupting the main processing. Also, the second timer interrupt processing (FIG. 134) is started by interrupting the first timer interrupt processing (FIG. 133). On the other hand, the first timer interrupt processing (FIG. 133) is not started by interrupting the second timer interrupt processing (FIG. 134). Also, if both the first interrupt period and the second interrupt period have elapsed when both the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are not being executed, the second timer interrupt processing (FIG. 134) is started first, regardless of the order in which the periods elapse. In this regard, it can be said that the second timer interrupt process (FIG. 134) is started with priority over the first timer interrupt process (FIG. 133). However, this is not limited to this, and the first timer interrupt process (FIG. 133) may be started with priority over the second timer interrupt process (FIG. 134).

The internal function register setting process sets the first interrupt period of the first timer interrupt process (Figure 133) in a specified register of the main CPU 63, and sets the second interrupt period of the second timer interrupt process (Figure 134) in a specific register of the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs processes such as setting the numerical ranges of various counters, such as the numerical range of the winning random number counter C1.

Then, the startup processing in progress flag provided in the work area 221 for specific control is set to "1" (step SB103). As with the 35th embodiment described above, the startup processing in progress flag is a flag that allows the main CPU 63 to identify a situation in which, even if the first timer interrupt processing (FIG. 133) is started, the various processes set in the first timer interrupt processing (FIG. 133) for power outage monitoring, updating of various counters, and fraud monitoring will be executed, but the first timer interrupt processing (FIG. 133) should be terminated without executing any processes for progressing the game.

The startup processing flag is set to "1" when the processing at the start of the supply of operating power (steps SB101 to SB122) begins during the main processing (Fig. 165), and is cleared to "0" after the processing at the start of the supply of operating power (steps SB101 to SB122) ends and before the remaining processing (steps SB125 to SB128) begins. As with the 35th embodiment, in the first timer interrupt processing (Fig. 133), if the startup processing flag is set to "1," steps S8907 to S8920 are not executed, thereby preventing the execution of processing to progress the game when the setting confirmation processing (Fig. 166) or setting value update processing (Fig. 167), described below, is being executed during the processing at the start of the supply of operating power (steps SB101 to SB122). On the other hand, as described above, even if the startup processing in progress flag is set to "1" in the first timer interrupt processing (FIG. 133), by executing steps S8901 to S8905, power outage monitoring is performed even when the setting confirmation processing (FIG. 166) or setting value update processing (FIG. 167), described below, of the processing performed when the supply of operating power starts (steps SB101 to SB122) is being performed, and the win random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is also performed.

In particular, even when the startup processing flag is set to "1," the power outage information storage process (step S8901) is executed. This allows for power outage processing to be executed even if a power outage occurs while the setting confirmation process (FIG. 166) or setting value update process (FIG. 167), described below, among the processes at the start of operating power supply (steps SB101 to SB122), is being executed. As with the 35th embodiment, the power outage processing sets the power outage flag in the specific control work area 221 to "1," calculates a checksum, and stores the calculated checksum in the specific control work area 221. This prevents the restart of operating power supply from being identified as an abnormality in the main RAM 65. As a result, if a power outage occurs during the setting confirmation process (FIG. 166) or setting value update process (FIG. 167), it becomes possible to identify that the power outage occurred during these setting-related processes at the start of the next operating power supply.

Incidentally, when the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167) is being executed, interrupts are not prohibited for either the first timer interrupt process (FIG. 133) or the second timer interrupt process (FIG. 134), and interrupts can occur at any time. In this case, when the first timer interrupt process (FIG. 133) or the second timer interrupt process (FIG. 134) interrupts and is started during the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167), the return address information for the main process (FIG. 165) to return to after the timer interrupt process that was started is completed is saved in the specific control stack area 222, and the information of the various registers of the main CPU 63 immediately before the timer interrupt process is started is saved in the specific control stack area 222. When the timer interrupt process that was the target of activation is completed, the process returns to the main process (Fig. 165) corresponding to the return address information saved in the specific control stack area 222, and the information saved in the specific control stack area 222 is restored to the various registers of the main CPU 63.

After setting the startup processing in progress flag to "1" in step SB103, it is determined whether the power outage flag provided in the work area 221 for specific control is set to "1" (step SB104). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step SB104: YES), it is determined whether the checksum is normal (step SB105). Specifically, first, checksums are calculated for the specific control work area 221 and the specific control stack area 222. The checksum calculation method is the same as in the 33rd embodiment. Then, the checksums for the specific control work area 221 and the specific control stack area 222 that were calculated and saved in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped are read, and the read checksums are compared with the checksums calculated as described above during the current main processing. It is then determined whether the checksums match.

If the checksums match (step SB105: YES), it is determined whether the setting value corresponding to the information stored in the setting reference area 341 (see FIG. 154) in the specific control work area 221 is within the normal range (step SB106). The setting reference area 341 is a memory area that stores information used by the main CPU 63 to identify the current setting value of the pachinko machine 10, as in the 45th embodiment. If the setting reference area 341 stores the numerical information "1," the current setting value of the pachinko machine 10 is "Setting 1." If the setting reference area 341 stores the numerical information "2," the current setting value of the pachinko machine 10 is "Setting 2." If the setting reference area 341 stores the numerical information "3," the current setting value of the pachinko machine 10 is "Setting 3." If the setting reference area 341 stores the numerical information "4," the current setting value of the pachinko machine 10 is "Setting 4." If the numerical information "5" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 5." If the numerical information "6" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 6." In step SB106, it is determined whether the setting value information stored in the setting reference area 341 is any of "1" to "6."

If all of steps SB104 through SB106 return a positive judgment, the process determines whether the setting update display flag provided in the work area 221 for specific control is set to "1" (step SB107). As with the 35th embodiment, the setting update display flag is a flag used by the main CPU 63 to identify that the setting value update process (FIG. 167) is being executed. When the setting update display flag is set to "1," the first through fourth alarm display devices 201 through 204 display an indication that the setting values are being updated and an indication of the setting values currently being updated. The setting update display flag is set to "1" when the setting value update process (FIG. 167) is initiated and cleared to "0" when the setting value update process (FIG. 167) is terminated. Therefore, the setting update display flag is generally not set to "1" when the setting value update process (FIG. 167) is not being executed. However, if the supply of operating power to the main CPU 63 is stopped while the setting value update process (FIG. 167) is being executed, the setting update display flag will be set to "1" when the supply of operating power to the main CPU 63 is subsequently started. This state in which the setting update display flag is set to "1" is maintained until the process of clearing the setting update display flag to "0" is executed in the setting value update process (FIG. 167).

If a negative judgment is made in step SB107 because the setting update display flag is not set to "1," a judgment is made as to whether the reset button 68c has been pressed (step SB108). In other words, a judgment is made as to whether the power to the pachinko machine 10 has been turned on and the supply of operating power to the main CPU 63 has begun while the reset button 68c has been pressed. In this embodiment, as in the 35th embodiment, the main control unit 60 is provided with a setting key insertion unit 68a and a reset button 68c, but is not provided with an update button 68b. Furthermore, as in the 11th embodiment, the main control unit 60 is provided with first to fourth notification display devices 201 to 204, rather than first to third notification display devices 69a to 69c.

If the reset button 68c is not pressed (step SB108: NO), it is determined whether the game stop flag in the work area 221 for specific control is set to "1" (step SB109). The game stop flag is set to "1" if the power outage flag is not set to "1", if the checksums do not match, or if the setting value is abnormal. When the game stop flag is set to "1", steps S8901 to S8905 are executed in the first timer interrupt process (Figure 133), while a positive determination is made in step S8906, so steps S8907 to S8920 are not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was shut off, if the checksums do not match because the information storage state has changed since the previous power outage in at least one of the specific control work area 221 and the specific control stack area 222, or if the setting values are abnormal, processing for power outage monitoring, updating various counters, and fraud monitoring will be executed, but processing for progressing the game will not be executed. If a positive determination is made in step SB109, processing of steps SB121 and SB122, described below, will be executed.

If the determination in step SB109 is negative, it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step SB110). If the setting key insertion unit 68a has been turned ON using the setting key (step SB110: YES), setting confirmation processing is executed (step SB112). Also, even if the setting key insertion unit 68a has not been turned ON using the setting key (step SB110: NO), if the setting confirmation display flag provided in the specific control work area 221 is set to "1" (step SB111: YES), setting confirmation processing is executed (step SB112).

As in the 35th embodiment, the setting confirmation display flag is a flag used by the main CPU 63 to identify that the setting confirmation process (Figure 166) is being executed. When the setting confirmation display flag is set to "1," the first to fourth alarm display devices 201-204 display a message indicating that the setting value is being confirmed and a message indicating the currently set setting value. The setting confirmation display flag is set to "1" when the setting confirmation process (Figure 166) is initiated and cleared to "0" when the setting confirmation process (Figure 166) is terminated. Therefore, when the setting confirmation process (Figure 166) is not being executed, the setting confirmation display flag is generally not set to "1." However, if the supply of operating power to the main CPU 63 is stopped while the setting confirmation process (Figure 166) is being executed, the setting confirmation display flag will be set to "1" when the supply of operating power to the main CPU 63 is subsequently resumed. This setting confirmation display flag will remain set to "1" until the first RAM clear process (step SB117) described below is executed, the setting value update process (Fig. 167) described below is executed, or the setting confirmation display flag is cleared to "0" during the setting confirmation process (Fig. 166).

As described above, the setting confirmation process (Fig. 166) is executed not only when the reset button 68c is not pressed and the setting key insertion section 68a is ON (i.e., when a "setting confirmation operation" is performed), but also when the reset button 68c is not pressed and the setting confirmation display flag is set to "1." Therefore, if a power outage process is executed while the setting confirmation process (Fig. 166) is being executed, the setting confirmation process (Fig. 166) will be executed even if a "setting confirmation operation" is not performed when the supply of operating power is subsequently resumed. This allows the current settings of the pachinko machine 10 to be continuously confirmed. On the other hand, even if a power outage process is executed while the setting confirmation process (Fig. 166) is being executed, if the reset button 68c is pressed when the supply of operating power is subsequently resumed, the setting confirmation process (Fig. 166) will not be executed, and the first RAM clear process (step SB117) and the setting value update process (Fig. 167) corresponding to the operation performed when the supply of operating power is resumed will be executed. This makes it possible to prioritize the execution of the first RAM clear process (step SB117) or the setting value update process (FIG. 167) over the setting confirmation process (FIG. 166).

Here, we will explain the setting confirmation process executed in step SB112. Figure 166 is a flowchart showing the setting confirmation process. Note that steps SB201 to SB207 in the setting confirmation process are executed using a specific control program and specific control data in the main CPU 63.

First, interrupt permission is set (step SB201). This causes the first timer interrupt process (Figure 133) to be started at the first interrupt period, and the second timer interrupt process (Figure 134) to be started at the second interrupt period.

In this embodiment, during the processing at the start of the supply of operating power (steps SB101 to SB122), interrupts for the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are generally prohibited, while interrupts are permitted during the setting confirmation processing (FIG. 166) and the setting value update processing (FIG. 167). Therefore, during the processing at the start of the supply of operating power (steps SB101 to SB122), when the setting confirmation processing (FIG. 166) and the setting value update processing (FIG. 167) are not being executed, execution of the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) is prohibited, and when the setting confirmation processing (FIG. 166) or the setting value update processing (FIG. 167) is being executed, execution of the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) is permitted. However, when the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167) is being executed, the startup process in progress flag is set to "1", so even if the first timer interrupt process (FIG. 133) is started, the various processes of the first timer interrupt process (FIG. 133) such as power outage monitoring, updating of various counters, and fraud monitoring will be executed, but the first timer interrupt process (FIG. 133) will end without executing any processes to progress the game.

Then, on the condition that the setting confirmation display flag provided in the specific control work area 221 is not set to "1," the setting confirmation display flag is set to "1" (step SB202). When the setting confirmation display flag is set to "1," a positive determination is made in step S9005 of the second timer interrupt process (FIG. 134), and setting processing for the fifth display data buffer 275 during setting confirmation (step S9006) is executed. The processing content of the setting processing for the fifth display data buffer 275 during setting confirmation is the same as that of the 45th embodiment described above. By executing this processing, for example, as shown in the explanatory diagram of FIG. 124(b), a display indicating that the setting values of the pachinko machine 10 are being confirmed and a display showing the current setting values of the pachinko machine 10 are displayed on the first to fourth notification display devices 201 to 204.

Then, a confirmation start command is sent to the audio and light-emitting control device 81 (step SB203). Upon receiving the confirmation start command, the audio and light-emitting control device 81 controls the display control device 82 so that an image indicating that the setting confirmation process (FIG. 166) is being executed and an image allowing the user to recognize the operation details for terminating the setting confirmation process (FIG. 166) are displayed on the symbol display device 41. This allows the amusement hall manager to recognize that the current setting values of the pachinko machine 10 are being confirmed, and also allows the amusement hall manager to recognize the operation details required to terminate the setting confirmation process (FIG. 166). Note that the notification may be performed by at least one of the display light-emitting unit 53 and the speaker unit 54, in addition to or instead of being performed by the symbol display device 41. Furthermore, an external output indicating that the setting confirmation process (FIG. 166) is being executed may be provided to a device external to the pachinko machine 10, such as the amusement hall's management computer.

Then, it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SB204). Specifically, similar to the setting confirmation process (FIG. 155) in the 45th embodiment, it is determined whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state. Therefore, a negative determination is made in step SB204 not only when the setting key insertion unit 68a is maintained in the ON state, but also when the setting confirmation process (FIG. 166) is started when the setting key insertion unit 68a is in the OFF state and the OFF state is maintained. If it has not been determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SB204: NO), the processing of step SB204 is repeated.

If it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SB204: YES), the setting confirmation display flag in the specific control work area 221 is cleared to "0" (step SB205). As a result, a negative determination is made in step S9005 of the second timer interrupt process (FIG. 134), and the setting process to the fifth display data buffer 275 during setting confirmation (step S9006) is not executed. Therefore, the first to fourth notification display devices 201 to 204 are no longer displaying the indication that the current setting value of the pachinko machine 10 is being confirmed and the current setting value of the pachinko machine 10.

Then, interrupts are disabled (step SB206). As a result, when the setting confirmation process (Fig. 166) is terminated and the process at the start of the supply of operating power (steps SB101 to SB122) in the main process (Fig. 165) is resumed, interrupts from the first timer interrupt process (Fig. 133) and the second timer interrupt process (Fig. 134) are disabled.

Then, a confirmation return command is sent to the audio and light emission control device 81 (step SB207). By receiving the confirmation return command, the audio and light emission control device 81 determines that the processing at the start of the supply of operating power (steps SB101 to SB122) in the main CPU 63 has ended, and determines that the setting confirmation processing (Figure 166) was executed in the processing at the start of the current supply of operating power (steps SB101 to SB122). Then, it executes processing corresponding to the receipt of the confirmation return command. The details of this processing will be explained later.

As described above, when the power to the pachinko machine 10 is turned on with the setting key insertion section 68a turned on using the setting key without pressing the reset button 68c, the supply of operating power to the main CPU 63 begins and the main processing (Figure 165) begins. This results in the reset button 68c not being pressed and the setting key insertion section 68a being turned on, and the setting confirmation processing (Figure 166) being executed when processing is being executed at the start of the supply of operating power, which is the state before the processing for progressing play in the main processing (Figure 165) is executed. This makes it possible to check the setting values when no play is being played.

Returning to the explanation of the main processing (FIG. 165), if the setting key insertion unit 68a has not been turned ON using the setting key and the setting confirmation display flag is not set to "1" (steps SB110 and SB111: NO), a normal return command is sent to the audio and light emission control device 81 (step SB113). By receiving the normal return command, the audio and light emission control device 81 determines that the processing performed at the start of the supply of operating power (steps SB101 to SB122) in the main CPU 63 has ended, and determines that none of the first RAM clear processing (step SB117), setting confirmation processing (FIG. 166), or setting value update processing (FIG. 167) has been performed during the processing performed at the start of the current supply of operating power (steps SB101 to SB122). The audio and light emission control device 81 then executes processing corresponding to the receipt of the normal return command. The details of this processing will be explained later.

On the other hand, if it is determined in step SB108 that the reset button 68c has been pressed and the setting key insertion section 68a has been turned ON using the setting key (step SB108 and step SB114: YES), or if it is determined in step SB107 that the setting update display flag is set to "1", a setting value update process is executed (step SB115). As described above, the setting value update process (FIG. 167) is executed not only when the reset button 68c is pressed and the setting key insertion section 68a is turned ON (i.e., when a "setting change operation" is performed), but also when the setting update display flag is set to "1" regardless of whether the reset button 68c is pressed or the setting key insertion section 68a is turned ON. Therefore, if power outage processing is executed while the setting value update process (FIG. 167) is being executed, the setting value update process (FIG. 167) will be executed regardless of whether the operation performed when the supply of operating power is subsequently resumed is "no operation," "RAM clear operation," "setting change operation," or "setting confirmation operation." This allows the execution of the setting value update process (FIG. 167) to be prioritized.

Here, we will explain the setting value update process executed in step SB115. Figure 167 is a flowchart showing the setting value update process. Note that steps SB301 to SB314 in the setting value update process are executed using the specific control program and specific control data in the main CPU 63.

First, interrupt permission is set (step SB301). This causes the first timer interrupt process (Figure 133) to be started at the first interrupt period, and the second timer interrupt process (Figure 134) to be started at the second interrupt period.

In this embodiment, during the processing at the start of the supply of operating power (steps SB101 to SB122), interrupts for the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are generally prohibited, while interrupts are permitted during the setting confirmation processing (FIG. 166) and the setting value update processing (FIG. 167). Therefore, during the processing at the start of the supply of operating power (steps SB101 to SB122), when the setting confirmation processing (FIG. 166) and the setting value update processing (FIG. 167) are not being executed, execution of the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) is prohibited, and when the setting confirmation processing (FIG. 166) or the setting value update processing (FIG. 167) is being executed, execution of the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) is permitted. However, when the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167) is being executed, the startup process in progress flag is set to "1", so even if the first timer interrupt process (FIG. 133) is started, the various processes of the first timer interrupt process (FIG. 133) such as power outage monitoring, updating of various counters, and fraud monitoring will be executed, but the first timer interrupt process (FIG. 133) will end without executing any processes to progress the game.

Then, on the condition that the setting update display flag provided in the work area 221 for specific control is not set to "1," the setting update display flag is set to "1" (step SB302). When the setting update display flag is set to "1," a positive determination is made in step S9003 of the second timer interrupt process (FIG. 134), and setting processing for the fifth display data buffer 275 during setting update (step S9004) is executed. The processing content of the setting processing for the fifth display data buffer 275 during setting update is the same as that of the 45th embodiment described above. By executing this processing, as shown in the explanatory diagram of FIG. 124(a), for example, a display indicating that the setting values of the pachinko machine 10 are being updated and a display of the setting values selected to be updated for the pachinko machine 10 are displayed on the first to fourth notification display devices 201 to 204.

After that, initial settings are made at the start (step SB303). During this initial setting, the game stop flag set in the specific control work area 221 is cleared to "0." The game stop flag is set to "1" in step SB119 of the main processing (Fig. 165) when the power outage flag is not set to "1" because power outage processing was not performed properly during the previous power outage (step SB104: NO), when the checksums do not match for at least one of the specific control work area 221 and the specific control stack area 222 because the information storage state has changed since the previous power outage (step SB105: NO), or when the setting value corresponding to the information stored in the setting reference area 341 is not within the normal range (step SB106: NO). By setting the game stop flag to "1," steps S8901 to S8905 are executed in the first timer interrupt process (FIG. 133), but a positive determination in step S8906 prevents steps S8907 to S8920 from being executed. As a result, when an information abnormality occurs in the main RAM 65 as described above, processing for power outage monitoring, updating of various counters, and fraud monitoring is executed, but processing for progressing the game is not executed. By clearing the game stop flag to "0" in the processing of step SB303, it is possible to release the state in which an information abnormality in the main RAM 65 has been identified when the setting value update process (FIG. 167) is executed.

Then, "1" is set in the setting update area 342 (see FIG. 154) in the work area 221 for specific control (step SB304). The setting update area 342 is a memory area that stores information about setting values being updated during the setting value update process (FIG. 167), as in the 45th embodiment. If the setting update area 342 stores numerical information of "1," the setting value to be updated (selected or changed) becomes "Setting 1." If the setting update area 342 stores numerical information of "2," the setting value to be updated becomes "Setting 2." If the setting update area 342 stores numerical information of "3," the setting value to be updated becomes "Setting 3." If the setting update area 342 stores numerical information of "4," the setting value to be updated becomes "Setting 4." If the setting update area 342 stores numerical information of "5," the setting value to be updated becomes "Setting 5." If the setting update area 342 stores numerical information of "6," the setting value to be updated becomes "Setting 6."

By setting "1" in the setting update area 342 in step SB304, the setting value to be updated becomes "Setting 1." In other words, in this embodiment, regardless of the current setting value of the pachinko machine 10, when the setting value update process (Figure 167) is started, the setting value to be updated becomes "Setting 1."

An update start command is then sent to the audio and light-emitting control device 81 (step SB305). Upon receiving the update start command, the audio and light-emitting control device 81 controls the display control device 82 so that an image indicating that the setting value update process (FIG. 167) is being executed, an image enabling the user to recognize the operation details for changing the setting value, and an image enabling the user to recognize the operation details for terminating the setting value update process (FIG. 167) are displayed on the symbol display device 41. This allows the amusement hall manager to recognize that the setting value is being changed, and also allows the amusement hall manager to recognize the operation details required to change the setting value and the operation details required to terminate the setting value update process (FIG. 167). Note that the notification may be performed by at least one of the display light-emitting unit 53 and the speaker unit 54, in addition to or instead of being performed by the symbol display device 41. Furthermore, an external output indicating that the setting value update process (FIG. 167) is being executed may be provided to a device external to the pachinko machine 10, such as the amusement hall's management computer.

Then, it is determined whether the setting value information stored in the setting update area 342 is any of "1" to "6" (step SB306). If it is not any of "1" to "6" (step SB306: NO), "1" is set in the setting update area 342 (step SB307). As a result, the setting value to be updated becomes "Setting 1."

If a positive determination is made in step SB306 or if the processing of step SB307 is executed, it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SB308). Specifically, it is determined whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state. Therefore, a negative determination is made in step SB308 not only when the setting key insertion unit 68a is maintained in the ON state, but also when the setting value update processing is started when the setting key insertion unit 68a is in the OFF state and the OFF state is maintained.

If the determination in step SB308 is negative, and the reset button 68c has been pressed (step SB309: YES), the value in the setting update area 342 is incremented by 1 (step SB310). As a result, the setting value is updated to the next higher level each time the reset button 68c is pressed. If the reset button 68c has not been pressed (step SB309: NO) or the value in the setting update area 342 is incremented by 1, the process returns to step SB306. However, if the determination in step SB306 is that the value in the setting update area 342 is 7 or greater, "1" is set in the setting update area 342 in step SB307. As a result, if the reset button 68c is pressed once when the setting is "6," the setting will return to "1."

If it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SB308: YES), the setting value information stored in the setting update area 342 is overwritten in the setting reference area 341 (step SB311). As a result, the setting value information resulting from the update in this setting value update process (FIG. 167) is set in the setting reference area 341, and the setting value corresponding to this set information becomes the current setting value of the pachinko machine 10.

Then, interrupts are disabled (step SB312). As a result, when the setting value update process (Fig. 167) is terminated and the process at the start of operating power supply (steps SB101 to SB122) in the main process (Fig. 165) is returned to, interrupts from the first timer interrupt process (Fig. 133) and the second timer interrupt process (Fig. 134) are disabled.

Then, a second RAM clear process is executed (step SB313). In the second RAM clear process, similar to the RAM clear process (step SA416) in the 45th embodiment, the specific control work area 221 is cleared to "0" and initial settings are executed, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (i.e., the setting reference area 341). This clears to "0" the area indicating whether the win/loss lottery mode is the high probability mode, so the win/loss lottery mode becomes the low probability mode regardless of the win/loss lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being executed, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserve storage area 65a and the normal power reserve area 65c provided in the work area 221 for specific control are also cleared to "0," thereby erasing the reserve information for the special chart display unit 37a and the reserve information for the normal chart display unit 38a. The setting update display flag and the setting confirmation display flag provided in the work area 221 for specific control are cleared to "0." The setting update area 342 provided in the work area 221 for specific control is cleared to "0." The game stop flag provided in the work area 221 for specific control is cleared to "0." The second RAM clearing process clears the stack area 222 for specific control to "0" and performs initial settings. The second RAM clearing process also clears various registers of the main CPU 63 to "0" and then performs initial settings. This initial setting process executes the same processing as the internal function register setting process in step SB102. Note that the process for clearing the work area 223 for non-specific control and the process for initializing the stack area 224 for non-specific control to "0" are not executed.

Then, a restore command for update is sent to the audio and light emitting control device 81 (step SB314). By receiving the restore command for update, the audio and light emitting control device 81 determines that the processing at the start of the supply of operating power (steps SB101 to SB122) in the main CPU 63 has ended, and also determines that the setting value update processing (Figure 167) was executed in the processing at the start of the current supply of operating power (steps SB101 to SB122). Then, it executes processing corresponding to the reception of the restore command for update. The details of this processing will be explained later.

As described above, the setting value update process (Figure 167) is executed not only when the reset button 68c is pressed while the pachinko machine 10 is powered on, but also when the setting key insertion section 68a is turned on using the setting key. Furthermore, as already explained, the setting confirmation process (Figure 166) is executed when the pachinko machine 10 is powered on while the setting key insertion section 68a is turned on using the setting key, without pressing the reset button 68c. This makes it possible to standardize the ON operation of the setting key insertion section 68a as the operation for executing setting-related processes related to setting values. Therefore, the operation content for triggering setting-related processes can be made easy to understand for the amusement hall manager.

Furthermore, when the power to the pachinko machine 10 is turned on while the setting key insertion section 68a is turned on with the setting key, if the reset button 68c is not pressed, the setting confirmation process (FIG. 166) is executed, whereas if the reset button 68c is pressed, the setting value update process (FIG. 167) is executed. This makes it possible to differentiate between the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) depending on whether the reset button 68c is pressed. This makes it possible to make the operation details for executing the desired process, either the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167), easier for the amusement hall manager to understand. Furthermore, by providing more operation details for executing the setting value update process (FIG. 167) than the setting confirmation process (FIG. 166), it becomes particularly difficult to perform fraudulent acts in the setting value update process (FIG. 167).

Returning to the explanation of the main processing (Figure 165), if it is determined in step SB108 that the reset button 68c has been pressed and that the setting key insertion section 68a has not been turned ON using the setting key (step SB114: NO), it is determined whether the game stop flag in the specific control work area 221 is set to "1" (step SB116). The game stop flag is set to "1" if the power outage flag is not set to "1," if the checksums do not match, or if the setting value is abnormal. When the game stop flag is set to "1," steps S8901 to S8905 are executed in the first timer interrupt processing (Figure 133), while a positive determination is made in step S8906, so steps S8907 to S8920 are not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was shut down, if the checksums do not match because the information storage state has changed since the previous power outage in at least one of the specific control work area 221 and the specific control stack area 222, or if the setting value is abnormal, processing will be executed to monitor the power outage, update various counters, and monitor for fraud, but processing to progress the game will not be executed.

If the game stop flag is not set to "1" (step SB116: NO), the first RAM clear process is executed (step SB117). In the first RAM clear process, similar to the RAM clear process (step SA416) in the 45th embodiment, the specific control work area 221 is cleared to "0" and initialized, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (i.e., the setting reference area 341). This clears the area indicating whether the win/loss lottery mode is in the high-probability mode to "0," thereby changing the win/loss lottery mode to the low-probability mode regardless of the win/loss lottery mode in effect immediately before the supply of operating power to the pachinko machine 10 was stopped. Furthermore, a game round is not being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserve storage area 65a and normal power reserve area 65c provided in the work area 221 for specific control are also cleared to "0", thereby erasing the reserve information for the special map display unit 37a and the reserve information for the normal map display unit 38a. The setting update display flag and setting confirmation display flag provided in the work area 221 for specific control are also cleared to "0". The setting update area 342 provided in the work area 221 for specific control is also cleared to "0". In the first RAM clear process, the stack area 222 for specific control is cleared to "0" and initial settings are performed. In the first RAM clear process, various registers of the main CPU 63 are also cleared to "0" and initial settings are then performed. In this initial setting, processing similar to the internal function register setting process of step SB102 is performed.

The process for clearing the non-specific control work area 223 and the non-specific control stack area 224 to "0" and the process for initializing the same are not executed. The first RAM clear process (step SB117) is identical to the second RAM clear process (step SB313) in the setting value update process (FIG. 167), but some of the process details may be different. For example, an area that is cleared to "0" and initialized in the first RAM clear process (step SB117) may not be cleared to "0" and initialized in the second RAM clear process (step SB313), and an area that is cleared to "0" and initialized in the second RAM clear process (step SB313) may not be cleared to "0" and initialized in the first RAM clear process (step SB117).

Then, a clear-time recovery command is sent to the audio and light emission control device 81 (step SB118). By receiving the clear-time recovery command, the audio and light emission control device 81 determines that the processing at the start of the supply of operating power (steps SB101 to SB122) in the main CPU 63 has ended, and also determines that the first RAM clear processing (step SB117) was executed during the processing at the start of the current supply of operating power (steps SB101 to SB122). The audio and light emission control device 81 then executes processing corresponding to the receipt of the clear-time recovery command. The details of this processing will be explained later.

If a negative judgment is made in any of steps SB104 to SB106 in the main processing (Fig. 165), i.e., if the power outage flag is not set to "1", if the checksum does not match, or if the setting value is abnormal, the game stop flag in the specific control work area 221 is set to "1" (step SB119). As already explained, when the game stop flag is set to "1", the processing of steps S8901 to S8905 is executed in the first timer interrupt processing (Fig. 133), while a positive judgment is made in step S8906, the processing of steps S8907 to S8920 is not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was shut down, if the checksums do not match because the information storage state has changed since the previous power outage in at least one of the specific control work area 221 and the specific control stack area 222, or if the setting value is abnormal, processing will be executed to monitor the power outage, update various counters, and monitor for fraud, but processing to progress the game will not be executed.

Then, it is determined whether the reset button 68c has been pressed (step SB120). If the reset button 68c has not been pressed (step SB120: NO), an abnormality command indicating that an abnormality occurred with the power outage flag, checksum, or setting value when the supply of operating power began is sent to the audio and light-emitting control device 81 (step SB121). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the information abnormality when the supply of operating power began, and causes the speaker unit 54 to output a voice message saying, "Please change the settings." It also causes the symbol display device 41 to display a text image saying, "Please change the settings." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notification will resume when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (Figure 167) is executed.

Then, external output processing in the event of an abnormality is executed (step SB122). In the external output processing in the event of an abnormality, processing is executed to externally output an abnormality signal to the gaming hall's management computer. In this case, the signal output of the abnormality signal is performed for a predetermined period (e.g., 100 milliseconds). However, this is not limited to this, and the signal output of the abnormality signal may continue when the game stop flag is set to "1," and the signal output of the abnormality signal may be stopped when the game stop flag is cleared to "0." The abnormality signal may also be output when an abnormality other than an abnormality related to the power outage flag, checksum, or setting value occurs. For example, an abnormality signal is also output externally when the fraud detection processing (step S8905) of the first timer interrupt processing (Figure 133) identifies the occurrence of monitored fraud (detection of unauthorized radio waves or unauthorized magnetic fields). However, the configuration is not limited to this dual-use abnormality signal; it is also possible to configure the system so that dedicated abnormality signals are output externally for abnormalities related to the power outage flag, checksum, or set value, or to configure the system so that abnormality signals corresponding to abnormalities related to the power outage flag, checksum, and set value are output externally.

If the reset button 68c is pressed (step SB120: YES), the system determines whether the setting key insertion unit 68a has been turned ON using the setting key (step SB114). If the reset button 68c is pressed and the setting key insertion unit 68a has been turned ON using the setting key (step SB114 and step SB120: YES), the system executes the setting value update process (step SB115). The details of the setting value update process have already been described. In other words, if operating power is supplied to the main CPU 63 while a "setting change operation" is being performed, the setting value update process (Fig. 167) is executed even if a negative determination is made in any of steps SB104 to SB106 due to an abnormality in the main RAM 65. This allows the setting value change to be prioritized. Furthermore, as already described, in the setting value update process (Fig. 167), the game stop flag is cleared to "0" by the initial setting at the start of the game in step SB303. As a result, when the setting value update process (Figure 167) is executed, it becomes possible to resolve the abnormality in the main RAM 65 after the setting value update is complete.

On the other hand, if the reset button 68c has been pressed but the setting key insertion section 68a has not been turned ON (step SB120: YES, step SB114: NO), it is determined whether the game stop flag in the specific control work area 221 has been set to "1" (step SB116). Since the game stop flag is naturally set to "1" when processing step SB116 after the game stop flag has been set to "1" in step SB119, a positive determination is made in step SB116. In this case, an abnormal command is sent to the sound and light emission control device 81 in step SB121, and an abnormal signal is output externally in step SB122.

In other words, if an abnormality occurs with the power outage flag, checksum, or setting value and a negative judgment is made in any of steps SB104 to SB106, the first RAM clear process (step SB117) is not executed, even if the supply of operating power to the main CPU 63 is initiated while the "RAM clear operation" is being performed. Similarly, the first RAM clear process (step SB117) is not executed even if the supply of operating power to the main CPU 63 is initiated while the "RAM clear operation" is being performed and the game stop flag is set to "1." This prevents the game stop flag from being cleared to "1" even if the supply of operating power to the main CPU 63 is initiated while the "RAM clear operation" is being performed. In contrast, if a "setting change operation" is being performed, the setting value update process (Fig. 167) is executed regardless of whether the game stop flag is set to "1," and the game stop flag is cleared to "0" during the initial setting (step SB303) at the start of the setting value update process (Fig. 167). As a result, in order to cancel the state in which the game stop flag is set to "1", it becomes necessary to execute the setting value update process (Fig. 167). Therefore, when an information abnormality occurs in the work area 221 for specific control, it is possible to not only perform the process to initialize the work area 221 for specific control, but also to require the setting value to be reset.

Furthermore, when the supply of operating power to the main CPU 63 is initiated while the game stop flag is set to "1," if a "setting change operation" has not been performed, i.e., if "no operation" has been performed, or if a "RAM clear operation" or "setting confirmation operation" has been performed, a positive determination is made in step SB109 or step SB116, causing an abnormality command to be sent in step SB121 and external output processing in the event of an abnormality to be executed in step SB122. As a result, when the game stop flag is set to "1," an abnormality alert is issued in the pachinko machine 10 and an external output in the event of an abnormality is sent to the outside of the pachinko machine 10 each time the supply of operating power to the main CPU 63 is initiated, regardless of the results of steps SB104 to SB106 in the subsequent main processing, unless the setting value update processing (FIG. 167) is executed. This makes it possible to make the gaming hall manager aware that the setting value should be changed.

When step SB112, step SB113, step SB115, step SB118, or step SB122 is executed, information corresponding to the initial check period (specifically, 5 seconds) is set in a checking counter provided in the specific control work area 221 (step SB123). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment. If a value of 1 or greater is set in the checking counter, the first to fourth notification display devices 201 to 204 continue to display the check information, as in the 35th embodiment.

With the above configuration, when the supply of operating power to the main CPU 63 begins, the initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps SB101 to SB122) and before the remaining processing (steps SB125 to SB128) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, thereby reducing the processing load while the processing at the start of the supply of operating power is being executed.

Furthermore, while the setting confirmation process (FIG. 166) and setting value update process (FIG. 167) are executed as processes at the start of the supply of operating power (steps SB101 to SB122), the initial check period begins after the processes at the start of the supply of operating power have finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

Then, the startup processing in progress flag in the specific control work area 221 is cleared to "0" (step SB124). When the startup processing in progress flag is cleared to "0," if the first timer interrupt process (FIG. 133) is initiated, a negative judgment is made in step S8906, which causes the processes of steps S8901 to S8905 as well as steps S8907 to S8920 to be executed, thereby canceling the state in which processes for progressing the game are not executed. Note that in step SB124, the power outage flag in the specific control work area 221 is also cleared to "0."

Then, the process proceeds to the remaining processing of steps SB125 to SB128. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134), but there is remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps SB125 to SB128. In this respect, the remaining processing of steps SB125 to SB128 can be said to be non-periodic processing executed non-periodically. Steps SB125 to SB128 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

Next, we will explain, with reference to the time chart in Figure 168, how the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134) are permitted when the processing at the start of the supply of operating power (steps SB101 to SB122) is being executed. FIG. 168(a) shows the period during which the power to the pachinko machine 10 is ON, FIG. 168(b) shows the period during which processing at the start of the supply of operating power (steps SB101 to SB122) is being executed, FIG. 168(c) shows the period during which the startup processing flag in the specific control work area 221 is set to "1", FIG. 168(d) shows the period during which remaining processing (steps SB125 to SB128) is being executed, FIG. 168(e) shows the period during which interrupts are permitted, FIG. 168(f) shows the period during which first timer interrupt processing (FIG. 133) or second timer interrupt processing (FIG. 134) is being executed, FIG. 168(g) shows the period during which setting value update processing (FIG. 167) is being executed, and FIG. 168(h) shows the period during which setting confirmation processing (FIG. 166) is being executed.

First, we will explain the case where neither the setting confirmation process (Figure 166) nor the setting value update process (Figure 167) is executed during the process at the start of operating power supply (steps SB101 to SB122).

At timing t1, the power to the pachinko machine 10 is turned ON as shown in Figure 168(a). In this case, the power to the pachinko machine 10 is turned ON in a "no operation" situation, where none of the "RAM clear operation," "setting change operation," or "setting confirmation operation" is performed. At timing t1, the main CPU 63 starts processing (steps SB101 to SB122) when the supply of operating power begins as shown in Figure 168(b). Also, as shown in Figure 168(c), the startup processing in progress flag in the work area 221 for specific control is set to "1."

After that, at timing t2, the processing at the start of the supply of operating power (steps SB101 to SB122) ends as shown in Figure 168(b), and the remaining processing (steps SB125 to SB128) begins as shown in Figure 168(d). Also, at timing t2, the startup processing in progress flag in the specific control work area 221 is cleared to "0" as shown in Figure 168(c). Note that when the remaining processing (steps SB125 to SB128) begins, interrupts are not permitted as shown in Figure 168(e).

After that, at timing t3, the remaining processing (steps SB125 to SB128) is completed as shown in FIG. 168(d), and interrupts are permitted as shown in FIG. 168(e). This causes the timer interrupt processing to begin as shown in FIG. 168(f). In this case, the second timer interrupt processing (FIG. 134) is executed first, and the first timer interrupt processing (FIG. 133) is executed when the second timer interrupt processing (FIG. 134) is completed. However, this is not limited to this, and the first timer interrupt processing (FIG. 133) may be executed first, and the second timer interrupt processing (FIG. 134) may be executed when the first timer interrupt processing (FIG. 133) is completed.

Next, we will explain the case where the setting value update process (Figure 167) is performed during the process at the start of operating power supply (steps SB101 to SB122).

At timing t4, the power to the pachinko machine 10 is turned ON, as shown in Figure 168 (a). In this case, the power to the pachinko machine 10 is turned ON while a "setting change operation" has been performed. At timing t4, the main CPU 63 starts processing (steps SB101 to SB122) when the supply of operating power begins, as shown in Figure 168 (b). Also, as shown in Figure 168 (c), the startup processing in progress flag in the work area 221 for specific control is set to "1".

Then, at timing t5, the setting value update process (FIG. 167) is initiated as shown in FIG. 168(g). In this case, an interrupt is permitted at timing t5 as shown in FIG. 168(e). The permitted interrupt causes the timer interrupt process to be initiated at timing t6 as shown in FIG. 168(f). In this case, the second timer interrupt process (FIG. 134) is executed first, and the first timer interrupt process (FIG. 133) is executed when the second timer interrupt process (FIG. 134) is completed. However, this is not limited to this, and the first timer interrupt process (FIG. 133) may be executed first, and the second timer interrupt process (FIG. 134) may be executed when the first timer interrupt process (FIG. 133) is completed. Furthermore, even if the first timer interrupt process (FIG. 133) is executed, since the startup process in progress flag is set to "1" as shown in FIG. 168(c), processes for power outage monitoring, updating various counters, and fraud monitoring are executed, but processes for progressing the game are not executed.

The timer interrupt processing ends at timing t7, as shown in Figure 168(f), and then the setting value update processing (Figure 167) ends at timing t8, as shown in Figure 168(g). Then, at timing t8, the processing at the start of the supply of operating power (steps SB101 to SB122) ends as shown in Figure 168(b), and the startup processing in progress flag is cleared to "0" as shown in Figure 168(c). Also, at timing t8, the remaining processing (steps SB125 to SB128) begins as shown in Figure 168(d).

Next, we will explain the case where the setting confirmation process (Figure 166) is executed during the process at the start of the supply of operating power (steps SB101 to SB122).

At timing t9, the power to the pachinko machine 10 is turned ON, as shown in Figure 168 (a). In this case, the power to the pachinko machine 10 is turned ON when the "setting confirmation operation" has been performed. At timing t9, the main CPU 63 starts processing (steps SB101 to SB122) when the supply of operating power begins, as shown in Figure 168 (b). Also, as shown in Figure 168 (c), the startup processing in progress flag in the work area 221 for specific control is set to "1".

Then, at timing t10, the setting confirmation process (Fig. 166) is started as shown in Fig. 168(h). In this case, an interrupt is permitted at timing t10 as shown in Fig. 168(e). With the interrupt permitted, the timer interrupt process is started at timing t11 as shown in Fig. 168(f). In this case, the second timer interrupt process (Fig. 134) is executed first, and when the second timer interrupt process (Fig. 134) has finished, the first timer interrupt process (Fig. 133) is executed. However, this is not limited to this, and a configuration may also be adopted in which the first timer interrupt process (Fig. 133) is executed first, and when the first timer interrupt process (Fig. 133) has finished, the second timer interrupt process (Fig. 134) is executed. Furthermore, even if the first timer interrupt process (Fig. 133) is executed, the startup process in progress flag is set to "1" as shown in Fig. 168 (c), so while processes for power outage monitoring, updating various counters, and fraud monitoring are executed, processes for progressing the game are not executed.

The timer interrupt processing ends at timing t12, as shown in Figure 168(f), and then the setting confirmation processing (Figure 166) ends at timing t13, as shown in Figure 168(h). Then, at timing t13, the processing at the start of the supply of operating power (steps SB101 to SB122) ends, as shown in Figure 168(b), and the startup processing in progress flag is cleared to "0," as shown in Figure 168(c). Also, at timing t13, the remaining processing (steps SB125 to SB128) begins, as shown in Figure 168(d).

As described above, when the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) are not being executed during the process at the start of the supply of operating power (steps SB101 to SB122), the first timer interrupt process (FIG. 133) and the second timer interrupt process (FIG. 134) are prohibited from being executed. However, when the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167) is being executed, the first timer interrupt process (FIG. 133) and the second timer interrupt process (FIG. 134) are permitted to be executed. By preventing the timer interrupt process from interrupting and starting during the process at the start of the supply of operating power (steps SB101 to SB122) when the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) are not being executed, it is possible to complete the process at the start of the supply of operating power (steps SB101 to SB122) more quickly.

On the other hand, when the setting confirmation process (Figure 166) and the setting value update process (Figure 167) are executed, the process is executed in response to the operation of the amusement hall manager, so the period spent on these processes is long. In this case, if the timer interrupt process remains prohibited even when the setting confirmation process (Figure 166) and the setting value update process (Figure 167) are being executed, the timing at which the timer interrupt process starts to be executed will be extremely delayed. In contrast, when the setting confirmation process (Figure 166) or the setting value update process (Figure 167) is executed, the timer interrupt process is permitted to be executed. This makes it possible to prevent the timing at which the timer interrupt process starts to be executed from being extremely delayed. Additionally, while the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) are being executed, the second timer interrupt process (FIG. 134), which executes processing to control the display of the first to fourth alarm display devices 201 to 204, interrupts and is executed, making it possible to use the second timer interrupt process (FIG. 134) to display setting values on the first to fourth alarm display devices 201 to 204.

In addition, when the setting confirmation process (Fig. 166) or the setting value update process (Fig. 167) is being executed, the startup process in progress flag is set to "1". Therefore, even if the first timer interrupt process (Fig. 133) is started when the setting confirmation process (Fig. 166) or the setting value update process (Fig. 167) is being executed, the various processes of the first timer interrupt process (Fig. 133) for power outage monitoring, updating various counters, and fraud monitoring will be executed, while processes for progressing the game will not be executed.

Next, the processing progress when an abnormality occurs related to the power outage flag, checksum, or setting value will be explained with reference to the time chart in Figure 169. Figure 169(a) shows the period during which the power to the pachinko machine 10 is ON, Figure 169(b) shows the period during which the processing at the start of the supply of operating power (steps SB101 to SB122) is being executed, Figure 169(c) shows the period during which the remaining processing (steps SB125 to SB128) is being executed, Figure 169(d) shows the period during which the first timer interrupt processing (Figure 133) or the second timer interrupt processing (Figure 134) is being executed, Figure 169(e) shows the period during which the game stop flag in the specific control work area 221 is set to "1", Figure 169(f) shows the period during which an abnormality signal is being externally output, and Figure 169(g) shows the period during which the setting value update processing (Figure 167) is being executed.

At timing t1, the power to the pachinko machine 10 is turned ON as shown in Figure 169 (a). In this case, the power to the pachinko machine 10 is turned ON in a "no operation" situation, where none of the "RAM clear operation," "setting change operation," or "setting confirmation operation" is performed. At timing t1, the main CPU 63 starts processing (steps SB101 to SB122) when the supply of operating power begins, as shown in Figure 168 (b).

After that, at time t2, an abnormality is identified regarding the power outage flag, checksum, or set value, and the game stop flag in the specific control work area 221 is set to "1" as shown in Figure 169 (e). Also, at time t2, external output of an abnormality signal begins as shown in Figure 169 (f). This enables the gaming hall's management computer to identify that an abnormality has occurred in the pachinko machine 10 regarding the power outage flag, checksum, or set value.

Then, at timing t3, as shown in FIG. 169(b), the processing at the start of the supply of operating power (steps SB101 to SB122) ends, and the remaining processing (steps SB125 to SB128) begins, as shown in FIG. 169(c). Furthermore, at timing t4, as shown in FIG. 169(f), the external output of the abnormality signal ends. By continuing the external output of the abnormality signal for a predetermined period (e.g., 100 milliseconds) from timing t2 to timing t4, the amusement hall's management computer can accurately identify that an abnormality has occurred in the pachinko machine 10 related to the power outage flag, checksum, or setting value. Furthermore, by keeping the external output of the abnormality signal constant for a predetermined period, the processing configuration for externally outputting the abnormality signal can be simplified. In addition to externally outputting the abnormality signal, abnormality alerts are also executed by the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54.

Then, at timing t5, the remaining processing (steps SB125 to SB128) ends, as shown in FIG. 169(c). Then, from timing t5 to timing t6, timer interrupt processing is executed, as shown in FIG. 169(d). From timing t6 to timing t7, remaining processing (steps SB125 to SB128) is executed, as shown in FIG. 169(c). Then, from timing t7 to timing t8, timer interrupt processing is executed, as shown in FIG. 169(d). However, because the game stop flag is set to "1" as shown in FIG. 169(e), even if the first timer interrupt processing (FIG. 133) is executed, processing for power outage monitoring, updating of various counters, and fraud monitoring is executed, but processing for progressing the game is not executed. At timing t8, power outage processing is executed in the first timer interrupt processing (FIG. 133), and the power to the pachinko machine 10 is turned off, as shown in FIG. 169(a).

After that, at timing t9, the power to the pachinko machine 10 is turned ON again as shown in FIG. 169(a), and the processing for starting the supply of operating power (steps SB101 to SB122) begins as shown in FIG. 169(b). In this case, the game stop flag in the specific control work area 221 is set to "1" as shown in FIG. 169(e). Therefore, an abnormality signal is externally output from timing t10 to timing t12 as shown in FIG. 169(f). This allows the gaming hall's management computer to once again recognize that an abnormality has occurred in the pachinko machine 10 related to the power outage flag, checksum, or setting value. In addition to externally outputting the abnormality signal, abnormality alerts are also executed in the symbol display device 41, display light-emitting unit 53, and speaker unit 54.

Furthermore, as shown in FIG. 169(b), the processing at the start of the supply of operating power (steps SB101 to SB122) ends at timing t11, and the remaining processing (steps SB125 to SB128) is executed from timing t11 to timing t13, as shown in FIG. 169(c). Then, as shown in FIG. 169(d), timer interrupt processing is executed at timing t13. However, because the game stop flag is set to "1" as shown in FIG. 169(e), even if the first timer interrupt processing (FIG. 133) is executed, processing for power outage monitoring, updating various counters, and fraud monitoring is executed, but processing for progressing the game is not executed. At timing t14, power outage processing is executed in the first timer interrupt processing (FIG. 133), and the power to the pachinko machine 10 is turned off, as shown in FIG. 169(a).

Then, at timing t15, the power supply of the pachinko machine 10 is turned ON again, as shown in FIG. 169(a), and the processing for starting the supply of operating power (steps SB101 to SB122) is initiated, as shown in FIG. 169(b). Then, as shown in FIG. 169(g), the setting value update processing (FIG. 167) is executed from timing t16 to timing t17. Execution of the setting value update processing (FIG. 167) not only changes the setting value, but also clears the game stop flag in the specific control work area 221 to "0" as shown in FIG. 169(e). This resolves the state in which the execution of processing to progress the game was prevented due to the occurrence of an information anomaly in the specific control work area 221. Then, as shown in FIG. 169(c), the remaining processing (steps SB125 to SB128) is executed from timing t17 to timing t18, and the timer interrupt processing is initiated at timing t18 as shown in FIG. 169(d).

As described above, if an abnormality occurs in the power outage flag, checksum, or setting value, and a negative judgment is made in any of steps SB104 to SB106 in the main processing (Figure 165), the game stop flag in the specific control work area 221 is set to "1," and processing to continue game play is not executed. This makes it possible to prevent game play from occurring despite an information abnormality occurring in the specific control work area 221.

Furthermore, the state in which the game stop flag is set to "1" will not be resolved unless the setting value update process (Fig. 167) is executed. As a result, in order to resolve the state in which the game stop flag is set to "1", it becomes necessary to execute the setting value update process (Fig. 167), and when an information abnormality occurs in the work area 221 for specific control, it becomes possible to require not only the process for initializing the work area 221 for specific control but also the resetting of the setting value.

Next, the display contents of the first to fourth notification display devices 201 to 204 when the supply of operating power to the main CPU 63 is started will be explained with reference to the time chart in Figure 170. Figure 170(a) shows the period during which the processing at the start of the supply of operating power (steps SB101 to SB122) is being executed, Figure 170(b) shows the period during which the processing after the processing at the start of the supply of operating power (steps SB101 to SB122) has ended is executed, Figure 170(c) shows the initial check period, Figure 170(d) shows the period during which the setting value update processing (Figure 167) is being executed, and Figure 170(e) shows the state during which the setting values of the pachinko machine 10 are being updated. FIG. 170(f) shows the period during which the setting update display is performed on the first to fourth notification display devices 201-204, during which a display indicating that the setting values of the pachinko machine 10 are being checked and a display indicating the current setting values of the pachinko machine 10 are displayed; FIG. 170(g) shows the period during which the setting confirmation display is performed on the first to fourth notification display devices 201-204, during which a display indicating that the setting values of the pachinko machine 10 are being checked and a display indicating the current setting values of the pachinko machine 10 are displayed.

First, we will explain the case where neither the setting confirmation process (Figure 166) nor the setting value update process (Figure 167) is executed during the process at the start of operating power supply (steps SB101 to SB122).

As shown in Figure 170(a), processing at the start of the supply of operating power (steps SB101 to SB122) is executed from time t1 to time t2. Then, as shown in Figure 170(b), processing begins after the processing at the start of the supply of operating power (steps SB101 to SB122) has ended at time t2. In this case, the initial check period begins at time t2 when the checking counter is set in step SB122 of the main processing (Figure 165). This causes check displays to begin on the first through fourth notification display devices 201 to 204 (see Figure 128(b)). Even during this initial check period, processing to progress the game is executed, so game play can be played while check displays are being displayed on the first through fourth notification display devices 201 to 204. Then, the initial check period ends at time t3 as shown in Figure 170(c). This causes the first to fourth notification display devices 201 to 204 to begin displaying the base value.

Next, we will explain the case where the setting value update process (Figure 167) is performed during the process at the start of operating power supply (steps SB101 to SB122).

At timing t4, as shown in Figure 170(a), processing begins when the supply of operating power starts (steps SB101 to SB122). Then, from timing t5 to timing t6, as shown in Figure 170(d), the setting value update processing (Figure 167) is executed. In this case, the setting update display period extends from timing t5 to timing t6, as shown in Figure 170(e).

Then, at timing t6, as shown in Figure 170(b), processing begins after the processing at the start of the supply of operating power (steps SB101 to SB122) has finished. In this case, at timing t6, the initial check period begins by executing the processing for setting the checking counter in step SB122 of the main processing (Figure 165). This causes the first to fourth alert display devices 201 to 204 to start displaying check information (see Figure 128(b)). Even during this initial check period, processing for progressing the game is executed, so game play can be played while the first to fourth alert display devices 201 to 204 are displaying check information. Then, at timing t7, as shown in Figure 170(c), the initial check period ends. This causes the first to fourth alert display devices 201 to 204 to start displaying base values.

Next, we will explain the case where the setting confirmation process (Figure 166) is executed during the process at the start of the supply of operating power (steps SB101 to SB122).

At timing t8, as shown in Figure 170(a), processing begins when the supply of operating power starts (steps SB101 to SB122). Then, from timing t9 to timing t10, as shown in Figure 170(f), the setting confirmation processing (Figure 166) is executed. In this case, as shown in Figure 170(g), the setting confirmation display period lasts from timing t9 to timing t10.

Then, at timing t10, as shown in FIG. 170(b), processing begins after the processing at the start of the supply of operating power (steps SB101 to SB122) has finished. In this case, at timing t10, the initial check period begins by executing the process of setting the checking counter in step SB122 of the main processing (FIG. 165). This causes the first to fourth alert display devices 201 to 204 to start displaying check information (see FIG. 128(b)). Even during this initial check period, processing to progress the game is executed, so game play can be played while the first to fourth alert display devices 201 to 204 are displaying check information. Then, at timing t11, as shown in FIG. 170(c), the initial check period ends. This causes the first to fourth alert display devices 201 to 204 to start displaying base values.

With the above configuration, when the supply of operating power to the main CPU 63 begins, the initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps SB101 to SB122) and before the remaining processing (steps SB125 to SB128) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, thereby reducing the processing load while the processing at the start of the supply of operating power is being executed.

Furthermore, while the setting confirmation process (FIG. 166) and setting value update process (FIG. 167) are executed as processes at the start of the supply of operating power (steps SB101 to SB122), the initial check period begins after the processes at the start of the supply of operating power have finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

Next, with reference to the diagram in Figure 171, we will explain the processing executed in the main processing (Figure 165) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting value update processing (Figure 167) or setting confirmation processing (Figure 166) is being executed.

First, we will explain the processing executed in the main processing (Figure 165) when the supply of operating power is resumed after a power outage processing is executed when neither the setting value update processing (Figure 167) nor the setting confirmation processing (Figure 166) has been executed.

If the supply of operating power is resumed in a "no operation" situation, the main processing (Fig. 165) does not execute the first RAM clear processing (step SB117), the setting value update processing (Fig. 167), or the setting confirmation processing (Fig. 166). Also, if the supply of operating power is resumed in a situation where a "RAM clear operation" has been performed, the main processing (Fig. 165) executes the first RAM clear processing (step SB117), but the setting value update processing (Fig. 167) and the setting confirmation processing (Fig. 166) are not executed. If the supply of operating power is resumed in a situation where a "setting change operation" has been performed, the main processing (Fig. 165) executes the setting value update processing (Fig. 167), but the first RAM clear processing (step SB117) and the setting confirmation processing (Fig. 166) are not executed. If the supply of operating power is resumed after the "settings check operation" has been performed, the settings check process (FIG. 166) is executed in the main process (FIG. 165), but the first RAM clear process (step SB117) and the setting value update process (FIG. 167) are not executed.

Next, we will explain the processing that is executed in the main processing (Figure 165) when the supply of operating power is resumed if power outage processing is executed while the setting value update processing (Figure 167) is being executed (i.e., when the setting update display flag is set to "1").

When the supply of operating power is resumed with no operation, when the supply of operating power is resumed with a "RAM clear operation", when the supply of operating power is resumed with a "settings change operation", or when the supply of operating power is resumed with a "settings check operation", the main processing (Fig. 165) executes the setting value update processing (Fig. 167), but the setting check processing (Fig. 166) is not executed. In other words, if the power outage processing is executed while the setting value update processing (Fig. 167) is being executed, the setting value update processing (Fig. 167) will be started anew regardless of the operation performed when the supply of operating power is subsequently resumed.

With the above configuration, if the supply of operating power is stopped during the setting value update process (Fig. 167), when the supply of operating power is resumed, the setting value update process (Fig. 167) can be restarted anew, regardless of the operation of the setting key insertion section 68a and reset button 68c when the pachinko machine 10 is turned on. This ensures that an opportunity to complete the setting value update is created. Therefore, it is possible to prevent gameplay from starting before the setting value update is complete.

Furthermore, if the supply of operating power is stopped during the setting value update process (Fig. 167), the setting value update process (Fig. 167) is executed uniquely regardless of the operation content when the supply of operating power is resumed. This makes it possible to achieve the above-mentioned excellent effects while simplifying the processing configuration compared to a configuration in which the processing content to be executed changes depending on the operation content.

Next, we will explain the processing that is executed in the main processing (Figure 165) when the supply of operating power is subsequently resumed if power outage processing is executed while the setting confirmation processing (Figure 166) is being executed (i.e., when the setting confirmation display flag is set to "1").

If the supply of operating power is resumed after a "RAM clear operation" has been performed, the first RAM clear process (step SB117) is executed in the main process (Fig. 165), but the setting value update process (Fig. 167) and the setting confirmation process (Fig. 166) are not executed. In other words, even if power outage processing is executed while the setting confirmation process (Fig. 166) is being executed, if a "RAM clear operation" is performed when the supply of operating power is subsequently resumed, the first RAM clear process (step SB117) is executed without newly executing the setting confirmation process (Fig. 166). This makes it possible to prioritize the execution of the first RAM clear process (step SB117) over the "RAM clear operation." Note that the setting confirmation display flag is cleared to "0" when the first RAM clear process (step SB117) is executed.

If the supply of operating power is resumed after a "setting change operation" has been performed, the main processing (Figure 165) executes the setting value update processing (Figure 167), but the setting confirmation processing (Figure 166) is not executed. In other words, even if the power outage processing is executed while the setting confirmation processing (Figure 166) is being executed, if a "setting change operation" is performed when the supply of operating power is subsequently resumed, the setting value update processing (Figure 167) is executed without newly executing the setting confirmation processing (Figure 166). This makes it possible to prioritize the execution of the setting value update processing (Figure 167) for the "setting change operation." Furthermore, even if the setting confirmation processing (Figure 166) is not executed in this way, the setting value to be updated is displayed on the fourth alarm display device 204 by executing the setting value update processing (Figure 167), and when the setting value update processing (Figure 167) is completed, information about the setting value currently being updated is set in the setting reference area 341, allowing the amusement hall manager to check the current setting values of the pachinko machine 10. Note that the setting confirmation display flag is cleared to "0" when the second RAM clear process (step SB313) is executed during the setting value update process (FIG. 167).

If the supply of operating power is resumed after the "settings check operation" has been performed, the main processing (Fig. 165) will execute the settings check processing (Fig. 166) on the condition that no abnormalities have occurred in the power outage flag, checksum, or setting values. As a result, even if power outage processing is executed during the settings check processing (Fig. 166), it is possible to resume checking the setting values by performing the "settings check operation" when the supply of operating power is resumed.

If the supply of operating power is resumed in a "no operation" state, the main processing (Fig. 165) will execute the setting confirmation processing (Fig. 166) even if the setting key insertion section 68a has not been turned ON, provided that no abnormalities have occurred with the power outage flag, checksum, or setting values. This makes it possible to resume checking the setting values even if the power outage processing is executed during the setting confirmation processing (Fig. 166) and the supply of operating power is subsequently resumed in a "no operation" state.

Next, we will explain the processing executed by the audio and light emission control device 81. Prior to explaining this processing, we will explain the electrical configuration of the audio and light emission control device 81 with reference to the explanatory diagram in Figure 172.

The audio/light emission control device 81 is equipped with an audio/light emission control board 351. The audio/light emission control board 351 is equipped with an audio/light side MPU 352. The audio/light side MPU 352 incorporates an audio/light side CPU 353, which is a processing device including a control unit and a calculation unit, as well as an audio/light side ROM 354 and an audio/light side RAM 355. In addition to the above elements, the audio/light side MPU 352 also incorporates an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits such as random number generators, etc.

The acousto-optical side ROM 354 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or NAND flash memory, and is used for read-only purposes. The acousto-optical side ROM 354 stores various control programs and fixed value data executed by the acousto-optical side CPU 353.

The sound/light side RAM 355 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as SRAM and DRAM, and is used for both reading and writing. The sound/light side RAM 355 is randomly accessible, and when compared for the same data capacity, it takes less time to read data than the sound/light side ROM 354. The sound/light side RAM 355 temporarily stores various data for the execution of the control program stored in the sound/light side ROM 354.

In addition to the sound/light side MPU 352, the sound/light emission control board 351 is also equipped with an RTC 356 and RTC memory 357. The RTC 356 is a real-time clock that constantly measures date and time information and is capable of outputting the measured date and time information (hereinafter also referred to as date and time information) in accordance with instructions from the sound/light side CPU 353. The RTC 356 is equipped with a backup power supply, making it possible to measure date and time information even when the power to the pachinko machine 10 is cut off. Furthermore, the RTC 356 is not limited to a configuration in which date and time information is measured, and may be configured to measure only time information.

The RTC memory 357 is a memory (i.e., a volatile memory means) such as SRAM or DRAM that requires an external power supply to retain its data, and is used for both reading and writing. The RTC memory 357 stores the date and time information of the RTC 356 in accordance with instructions from the sound/light CPU 353. The date and time information stored in the RTC memory 357 is read by the sound/light CPU 353 as needed. The sound/light CPU 353 determines the reference time based on the date and time information stored in the RTC memory 357, and executes processing to execute a time-responsive effect every time a predetermined time (e.g., one hour) has elapsed based on the reference time. The RTC memory 357 is configured to receive backup power from a backup power supply provided for the RTC 356, allowing the date and time information to be stored and retained even when the pachinko machine 10 is powered off. However, this is not a limitation, and the RTC memory 357 may be an EEPROM or other memory that does not require an external power supply to retain information.

Next, the performance control process executed by the sound/light side CPU 353 will be explained with reference to the flowchart in Figure 173. Note that the performance control process is executed when the supply of operating power to the sound/light side CPU 353 begins.

If an update start command is received from the main CPU 63 (step SB401: YES), the update notification setting process is executed (step SB402). As previously explained, the update start command is sent to the audio/visual CPU 353 when the main CPU 63 starts the setting value update process (FIG. 167). In the update notification setting process, the display control device 82 controls the display so that an image indicating that the setting value update process (FIG. 167) is being executed, an image enabling the user to recognize the operation details for changing the setting value, and an image enabling the user to recognize the operation details for terminating the setting value update process (FIG. 167) are displayed on the symbol display device 41. This allows the amusement hall manager to recognize that the setting value is being changed and to recognize the operation details required to change the setting value and the operation details required to terminate the setting value update process (FIG. 167). Note that the notification may be performed by at least one of the display light-emitting unit 53 and the speaker unit 54, in addition to or instead of being performed by the symbol display device 41.

If a confirmation start command has been received from the main CPU 63 (step SB403: YES), the confirmation notification setting process is executed (step SB404). As already explained, the confirmation start command is sent to the sound/light CPU 353 when the main CPU 63 starts the setting confirmation process (FIG. 166). In the confirmation notification setting process, the display control device 82 controls the display so that an image indicating that the setting confirmation process (FIG. 166) is being executed and an image enabling the user to recognize the operation details for terminating the setting confirmation process (FIG. 166) are displayed on the symbol display device 41. This allows the amusement hall manager to recognize that the current setting values of the pachinko machine 10 are being confirmed, and also allows the amusement hall manager to recognize the operation details required to terminate the setting confirmation process (FIG. 166). Note that the notification may be executed by at least one of the display light-emitting unit 53 and the speaker unit 54, in addition to or instead of being executed by the symbol display device 41.

When steps SB401 to SB404 are executed, it is determined whether any of the following commands has been received from the main CPU 63: a normal return command, a return command when clearing, a return command when checking, or a return command when updating (step SB405). A normal return command is sent when the processing at the start of the supply of operating power (steps SB101 to SB122) has ended without the first RAM clear processing (step SB117), the setting confirmation processing (Figure 166), or the setting value update processing (Figure 167) being executed. A return command when clearing is sent when the first RAM clear processing (step SB117) has been executed and the processing at the start of the supply of operating power (steps SB101 to SB122) has ended. A return command when checking is sent when the setting confirmation processing (Figure 166) has been executed and the processing at the start of the supply of operating power (steps SB101 to SB122) has ended. The restore command during an update is sent when the setting value update process (Figure 167) is executed and the process at the start of the supply of operating power (steps SB101 to SB122) is completed.

If these return commands have not been received (step SB405: NO), processing returns to step SB401. The main CPU 63 sends one of the return commands to the sound/light CPU 353 when the processing at the start of the supply of operating power (steps SB101 to SB122) is completed. In this case, as described above, the sound/light CPU 353 will not execute processing from step SB406 onwards until it receives one of the return commands from the main CPU 63. This makes it possible to prevent the sound/light CPU 353 from starting to control the execution of normal effects while the main CPU 63 is executing the processing at the start of the supply of operating power (steps SB101 to SB122).

In addition, in a situation where no recovery command has been received, it is possible that an update start command or a confirmation start command will be received from the main CPU 63. If an update start command is received, it is necessary to issue a notification corresponding to the execution of the setting value update process (Figure 167), as already explained, and if a confirmation start command is received, it is necessary to issue a notification corresponding to the execution of the setting confirmation process (Figure 166), as already explained. In this case, the audio-visual CPU 353 will not execute the processing from step SB406 onwards until it receives one of the recovery commands from the main CPU 63, thereby making it possible to appropriately start a notification corresponding to the reception of an update start command or a confirmation start command.

If any return command is received from the main CPU 63 (step SB405: YES), it is determined whether the received return command is a normal return command (step SB406). As already explained, a normal return command is sent when the processing at the start of the supply of operating power (steps SB101 to SB122) is completed without executing any of the first RAM clear processing (step SB117), setting confirmation processing (FIG. 166), and setting value update processing (FIG. 167). If a normal return command is received (step SB406: YES), the current date and time information of the RTC 356 is read, and the read date and time information is stored in the RTC memory 357 (step SB407). This causes the date and time information that serves as the reference for determining the timing to execute a time-dependent effect to be stored in the RTC memory 357.

If the return command received this time is not a normal return command (step SB406: NO) but a return command during update (step SB408: YES), the update notification termination process is executed (step SB409). As already explained, the update return command is sent to the audio/visual side CPU 353 when the setting value update process (Figure 167) is terminated by the main side CPU 63. The update notification termination process terminates the notification corresponding to the setting value update process (Figure 167) started in step SB402.

If the currently received return command is not a return command during update (step SB408: NO) but a return command during confirmation (step SB410: YES), the confirmation notification termination process is executed (step SB411). As already explained, the confirmation return command is sent to the audio/visual CPU 353 when the setting confirmation process (Figure 166) is terminated by the main CPU 63. The confirmation notification termination process terminates the notification corresponding to the setting confirmation process (Figure 166) started in step SB404.

If the processing of step SB407 is executed, the processing of step SB409 is executed, a negative determination is made in step SB410, or the processing of step SB411 is executed, processing is executed to control the execution of normal effects. Specifically, it is first determined whether it is time to start a time-dependent effect (step SB412).

A time-responsive effect is an effect that is executed each time a predetermined time (e.g., one hour) has elapsed, based on a reference time corresponding to the date and time information stored in the RTC memory 357. In a time-responsive effect, the display light-emitting unit 53 produces a light-emitting effect corresponding to the time-responsive effect, the speaker unit 54 produces a sound output effect corresponding to the time-responsive effect, and the pattern display device 41 produces a display effect corresponding to the time-responsive effect.

When a time-responsive effect is started while a game-round effect is being executed, the display light-emitting unit 53 and speaker unit 54 execute the time-responsive effect with priority over the game-round effect, while the pattern display device 41 displays an image corresponding to the time-responsive effect with an image display corresponding to the game-round effect displayed in a reduced size on part of the display surface of the pattern display device 41. When a time-responsive effect is started while an opening/closing execution mode effect is being executed, the display light-emitting unit 53 and speaker unit 54 execute the time-responsive effect with priority over the opening/closing execution mode effect, while the pattern display device 41 displays an image corresponding to the time-responsive effect with an image display corresponding to the opening/closing execution mode effect displayed in a reduced size on part of the display surface of the pattern display device 41.

This configuration executes time-responsive effects each time a predetermined time (e.g., one hour) has elapsed, based on a reference time corresponding to the date and time information stored in the RTC memory 357. Therefore, if the reference times of multiple adjacent pachinko machines 10 in an amusement hall are the same, it is possible to simultaneously start time-responsive effects on those multiple pachinko machines 10. Furthermore, since multiple pachinko machines 10 are powered on at the same time in an amusement hall, the reference times of those multiple pachinko machines 10 will generally be the same.

In step SB412, the reference time is determined based on the date and time information stored in the RTC memory 357. The current date and time information of the RTC 356 is also read. A determination is then made as to whether the difference between the reference time and the time corresponding to the current date and time information read from the RTC 356 is an integer multiple of a predetermined time. If a positive determination is made in step SB412, a process for setting a time-responsive effect is executed (step SB413). In the process for setting a time-responsive effect, settings are made to execute a time-responsive effect using the display light-emitting unit 53 and the speaker unit 54, and a command is sent to the display control device 82 to execute a time-responsive effect using the pattern display device 41. Note that the execution content of the time-responsive effect may be configured to differ depending on the number of times the time-responsive effect is executed when the reference time corresponding to the date and time information stored in the RTC memory 357 is used as a reference.

If a negative judgment is made in step SB412 or if the processing of step SB413 is executed, other processing is executed (step SB414). In other processing, when a command to start a game-round presentation is received from the main CPU 63, the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are set to start the game-round presentation; when the situation is such that the game-round presentation should proceed, the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are set to proceed with the game-round presentation; and when the situation is such that the game-round presentation should end, the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are set to end the game-round presentation. In other processes, when a command to start the performance for the open/close execution mode is received from the main CPU 63, the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are set to start the performance for the open/close execution mode; when the situation is such that the performance for the open/close execution mode should proceed, the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are set to proceed with the performance for the open/close execution mode; and when the situation is such that the performance for the open/close execution mode should end, the pattern display device 41, display light-emitting unit 53, and speaker unit 54 are set to end the performance for the open/close execution mode.

Next, the actions corresponding to the processing executed in the processing (steps SB101 to SB122) when the supply of operating power to the main CPU 63 starts will be explained with reference to the explanatory diagram in Figure 174.

If none of the first RAM clear process (step SB117), setting confirmation process (FIG. 166), or setting value update process (FIG. 167) is executed during the process at the start of the supply of operating power in the main CPU 63 (steps SB101 to SB122), the main CPU 63 sends a normal return command to the sound/light CPU 353 when the process at the start of the supply of operating power (steps SB101 to SB122) ends. When the sound/light CPU 353 receives a normal return command, it does not execute any notification control in response. On the other hand, when the sound/light CPU 353 receives a normal return command, it stores the current date and time information measured by the RTC 356 in the RTC memory 357. As a result, information corresponding to the reference time referenced to identify the trigger for executing a time-responsive effect is newly stored in the RTC memory 357.

If the first RAM clear process (step SB117) is executed during the process at the start of the supply of operating power in the main CPU 63 (steps SB101 to SB122), the main CPU 63 sends a clear restore command to the sound/light CPU 353 when the process at the start of the supply of operating power (steps SB101 to SB122) ends. When the sound/light CPU 353 receives the clear restore command, it does not execute any notification control in response. Furthermore, even if the sound/light CPU 353 receives the clear restore command, it does not store the current date and time information measured by the RTC 356 in the RTC memory 357. Because backup power is supplied to the RTC memory 357, if no new date and time information is stored in the RTC memory 357, the date and time information stored in the RTC memory 357 before the pachinko machine 10 was powered off is retained.

If the setting value update process (FIG. 167) is executed during the process at the start of the supply of operating power in the main CPU 63 (steps SB101 to SB122), the main CPU 63 sends an update return command to the sound/light CPU 353 when the process at the start of the supply of operating power (steps SB101 to SB122) ends. When the sound/light CPU 353 receives the update return command, it terminates the notification corresponding to the execution of the setting value update process (FIG. 167). Furthermore, even if the sound/light CPU 353 receives the update return command, it does not store the current date and time information measured by the RTC 356 in the RTC memory 357. Because backup power is supplied to the RTC memory 357, if no new date and time information is stored in the RTC memory 357, the date and time information stored in the RTC memory 357 before the pachinko machine 10 was powered off is retained.

If the setting confirmation process (FIG. 166) is executed during the process at the start of the supply of operating power in the main CPU 63 (steps SB101 to SB122), the main CPU 63 sends a confirmation return command to the sound/light CPU 353 when the process at the start of the supply of operating power (steps SB101 to SB122) ends. When the sound/light CPU 353 receives the confirmation return command, it terminates the notification corresponding to the execution of the setting confirmation process (FIG. 166). Even if the sound/light CPU 353 receives the confirmation return command, it does not store the current date and time information measured by the RTC 356 in the RTC memory 357. Because backup power is supplied to the RTC memory 357, if no new date and time information is stored in the RTC memory 357, the date and time information stored in the RTC memory 357 before the pachinko machine 10 was powered off is retained.

The present embodiment described above provides the following excellent effects:

When the setting value update process (Fig. 167) is started, the setting value is changed from a predetermined starting setting value. This makes it possible to change the setting value from a fixed starting setting value in the setting value update process (Fig. 167), regardless of the setting value to be used before the setting value update process (Fig. 167) was started. This makes it easy for the operator to understand the work involved in changing the setting value.

The setting value corresponding to the start mentioned above is specifically "Setting 1," which has the lowest degree of advantage. Therefore, when the setting value update process (Figure 167) is started, the setting value is changed from "Setting 1," which has the lowest degree of advantage. This means that even if the amusement hall manager unintentionally ends the setting value update process (Figure 167) immediately after it has started, the setting value with the lowest degree of advantage will be used, preventing unintended disadvantages to the amusement hall even if play begins in such a situation.

The work area 221 for specific control is provided with a setting reference area 341 and a setting update area 342. Information corresponding to the setting values to be used is stored in the setting reference area 341, and information corresponding to setting values that are in the process of being changed while the setting value update process (Figure 167) is being executed is stored in the setting update area 342. This makes it possible to change the setting values to be updated in the setting value update process (Figure 167) while storing and retaining information about the setting values that were set before the setting value update process (Figure 167) was started in the setting reference area 341.

When the supply of operating power is started, the main CPU 63 sends a clear return command if it executes the first RAM clear process (step SB117), sends an update return command if it executes the setting value update process (Figure 167), sends a confirmation return command if it executes the setting confirmation process (Figure 166), and sends a normal return command if none of the first RAM clear process (step SB117), setting value update process (Figure 167), or setting confirmation process (Figure 166) is executed. This makes it possible for control corresponding to the type of start status when the supply of operating power is started to be performed not only by the main CPU 63 but also by the audio/optical CPU 353.

Whether the sound/light side CPU 353 receives a normal return command, a return command upon clearing, a return command upon updating, or a return command upon confirmation, it makes a positive judgment at step SB405 of the presentation control process (Fig. 173) and enters a state in which it executes the processes of steps SB412 to SB414. On the other hand, if it receives a normal return command, it executes a write process to the RTC memory 357 (step SB407); if it receives a return command upon updating, it executes an end process for the update notification (step SB409); if it receives a return command upon confirmation, it executes an end process for the confirmation notification (step SB411); and if it receives a return command upon clearing, it does not execute any dedicated process. This allows the sound/light side CPU 353 to start processing corresponding to the progress of the game when any one of the return commands is received, and allows the sound/light side CPU 353 to execute control corresponding to each return command.

After sending one of the return commands, the main CPU 63 ends the processing at the start of the supply of operating power (steps SB101 to SB122) and begins processing for controlling the progress of the game (steps S8907 to S8920). When the sound/light CPU 353 receives one of the return commands, it controls the execution of effects corresponding to the progress of the game. This makes it possible for the sound/light CPU 353 to control the execution of effects corresponding to the progress of the game after the main CPU 63 is in a state where it can execute processing for controlling the progress of the game. In this case, the sound/light CPU 353 executes processing corresponding to each return command. This makes it possible to use multiple return commands that differ in the execution content of processing at the start of the supply of operating power in the sound/light CPU 353, allowing the sound/light CPU 353 to recognize the trigger for starting execution control of effects corresponding to the progress of the game.

The time-responsive effect is executed when the timing for the time-responsive effect is reached based on the date and time information stored in the RTC memory 357, making it possible to execute the time-responsive effect at a specified time. In this case, if the first RAM clear process (step SB117), the setting value update process (FIG. 167), or the setting confirmation process (FIG. 166) is executed when the supply of operating power to the main CPU 63 is started, no new date and time information is stored in the RTC memory 357. On the other hand, if none of the first RAM clear process (step SB117), the setting value update process (FIG. 167), or the setting confirmation process (FIG. 166) is executed, the current date and time information measured by the RTC 356 is stored in the RTC memory 357. This makes it possible to create a situation in which new date and time information is stored in the RTC memory 357 or a situation in which new date and time information is not stored in the RTC memory 357, depending on the processing executed by the main CPU 63 when the supply of operating power to the main CPU 63 is started.

When the supply of operating power to the main CPU 63 is started, if a "RAM clear operation" is performed, the first RAM clear process (step SB117) is executed; if a "setting change operation" is performed, the setting value update process (Fig. 167) is executed; and if a "setting confirmation operation" is performed, the setting confirmation process (Fig. 166) is executed. On the other hand, when the supply of operating power to the main CPU 63 is started in a "no operation" situation, none of the first RAM clear process (step SB117), setting value update process (Fig. 167), and setting confirmation process (Fig. 166) are executed. In this case, when the supply of operating power to the main CPU 63 is started as described above, if the first RAM clearing process (step SB117), the setting value update process (FIG. 167), or the setting confirmation process (FIG. 166) is executed, no new date and time information is stored in the RTC memory 357. On the other hand, if none of the first RAM clearing process (step SB117), the setting value update process (FIG. 167), or the setting confirmation process (FIG. 166) is executed, the current date and time information measured by the RTC 356 is stored in the RTC memory 357. This allows the amusement hall manager to select whether new date and time information is stored in the RTC memory 357 or whether new date and time information is not stored in the RTC memory 357 when the pachinko machine 10 is turned on.

When the supply of operating power to the main CPU 63 begins, the initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps SB101 to SB122) and before the remaining processing (steps SB125 to SB128) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, thereby reducing the processing load while the processing at the start of the supply of operating power is being executed.

The setting confirmation process (Figure 166) and setting value update process (Figure 167) are executed as part of the process at the start of the supply of operating power (steps SB101 to SB122), whereas the initial check period begins after the process at the start of the supply of operating power has finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

When the supply of operating power to the main CPU 63 begins, a check display is displayed on the first to fourth alarm display devices 201-204, regardless of whether the setting confirmation process (Figure 166) or the setting value update process (Figure 167) is executed, or whether neither the setting confirmation process (Figure 166) nor the setting value update process (Figure 167) is executed. This makes it possible to check whether the first to fourth alarm display devices 201-204 are normal, regardless of the situation when the supply of operating power to the main CPU 63 begins.

The main processing (FIG. 165) of the master CPU 63 is a process that is executed both when either the setting confirmation processing (FIG. 166) or the setting value update processing (FIG. 167) is executed, and when neither the setting confirmation processing (FIG. 166) nor the setting value update processing (FIG. 167) is executed. When either the setting confirmation processing (FIG. 166) or the setting value update processing (FIG. 167) is executed, a process that starts a check display on the first to fourth alarm display devices 201 to 204 is set as a process that is executed later in the order of execution than the setting confirmation processing (FIG. 166) and the setting value update processing (FIG. 167). In this way, by setting the process that starts a check display on the first to fourth alarm display devices 201 to 204 as a common process, it is possible to achieve the excellent effects already described while simplifying the processing configuration.

The main CPU 63 can start processing to progress the game even when a check display is being executed on the first to fourth notification display devices 201 to 204. This makes it possible to prevent delays in the start of processing to progress the game, even in a configuration in which a check display is executed on the first to fourth notification display devices 201 to 204 after the setting confirmation process (FIG. 166) or setting value update process (FIG. 167) is executed.

When the supply of operating power to the main CPU 63 begins, the process at the start of the supply of operating power (steps SB101 to SB122) executes a process to monitor whether the setting values of the target devices are within the normal range. If the setting values of the target devices are abnormal, a restricted state is entered in which processing to progress the game is not initiated. This makes it possible to prevent processing to progress the game from being initiated even if the setting values of the target devices are abnormal.

The process for monitoring whether the setting value of the target device is within the normal range is executed in step S8919 of the first timer interrupt process (Fig. 133) even after the process at the start of the supply of operating power (steps SB101 to SB122) has ended. This makes it possible to deal with any abnormal setting value of the target device that may become abnormal as the game progresses.

When the supply of operating power to the main CPU 63 begins, the process at the start of the supply of operating power (steps SB101 to SB122) is executed. This process not only monitors whether the setting values of the target devices are within the normal range, but also whether the power outage flag in the specific control work area 221 is set to "1," and whether the checksums of the specific control work area 221 and the specific control stack area 222 are normal. If the power outage flag is not set to "1" or the checksum is abnormal, a restricted state is entered in which processing to progress the game is not initiated. This makes it possible to prevent processing to progress the game from being initiated even when an information abnormality has occurred in the main RAM 65.

The above-mentioned restricted state will resume when the supply of operating power is restarted, even if the supply of operating power is stopped. This makes it possible to ensure that a state in which the execution of processing to progress a game is restricted due to an information abnormality occurring in the main RAM 65 will not be released simply by stopping the supply of operating power.

The above restricted state is released by executing the setting value update process (Figure 167). This makes it possible to set new setting values to be used when the state in which game progress was restricted due to an information abnormality occurring in the main RAM 65 is released.

Even in the above restricted state, power outage monitoring and various counter update processes are executed. This makes it possible to ensure that necessary processes are executed even when game progress is restricted as described above. In particular, by executing power outage monitoring, it becomes possible to respond appropriately in the event of a power outage even when game progress is restricted.

When the above-mentioned restricted state occurs, a notification is sent to inform the user that the setting value for the target device should be changed. This makes it possible to prompt the amusement hall manager to resolve any abnormal information regarding the main RAM 65.

If an information abnormality occurs in the main RAM 65, an abnormality signal is output to the amusement hall's management computer. This makes it possible to prompt the amusement hall manager to resolve any information abnormalities that occur in the main RAM 65.

If an abnormality other than an information abnormality occurs in the main RAM 65, an abnormality signal is output to the amusement hall's management computer. This makes it possible to use the same configuration for external output.

Even if the supply of operating power to the main CPU 63 is stopped in a restricted state in which game progress is restricted due to an information abnormality occurring in the main RAM 65, if the restricted state is not yet lifted when the supply of operating power is resumed, an abnormality signal will be output externally again. As a result, in a restricted state, an abnormality signal will be output externally every time the supply of operating power is resumed. This makes it easier for the gaming hall manager to recognize that an information abnormality has occurred in the main RAM 65.

When the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) are not being executed during the process at the start of the supply of operating power (steps SB101 to SB122), the first timer interrupt process (FIG. 133) and the second timer interrupt process (FIG. 134) are prohibited from being executed. However, when the setting confirmation process (FIG. 166) or the setting value update process (FIG. 167) is being executed, the first timer interrupt process (FIG. 133) and the second timer interrupt process (FIG. 134) are permitted to be executed. By preventing the timer interrupt process from interrupting and starting during the process at the start of the supply of operating power (steps SB101 to SB122) when the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) are not being executed, the process at the start of the supply of operating power (steps SB101 to SB122) can be completed more quickly.

On the other hand, when the setting confirmation process (Figure 166) and the setting value update process (Figure 167) are executed, the process is executed in response to the operation of the amusement hall manager, so the period spent on these processes is long. In this case, if the timer interrupt process remains prohibited even when the setting confirmation process (Figure 166) and the setting value update process (Figure 167) are being executed, the timing at which the timer interrupt process starts to be executed will be extremely delayed. In contrast, when the setting confirmation process (Figure 166) or the setting value update process (Figure 167) is executed, the timer interrupt process is permitted to be executed. This makes it possible to prevent the timing at which the timer interrupt process starts to be executed from being extremely delayed. Additionally, while the setting confirmation process (FIG. 166) and the setting value update process (FIG. 167) are being executed, the second timer interrupt process (FIG. 134), which executes processing to control the display of the first to fourth alarm display devices 201 to 204, interrupts and is executed, making it possible to use the second timer interrupt process (FIG. 134) to display setting values on the first to fourth alarm display devices 201 to 204.

In addition, when the setting confirmation process (Fig. 166) or the setting value update process (Fig. 167) is being executed, the startup process in progress flag is set to "1". Therefore, even if the first timer interrupt process (Fig. 133) is started when the setting confirmation process (Fig. 166) or the setting value update process (Fig. 167) is being executed, the various processes of the first timer interrupt process (Fig. 133) for power outage monitoring, updating various counters, and fraud monitoring will be executed, while processes for progressing the game will not be executed.

Note that the present invention is not limited to a configuration in which new storage of date and time information occurs in the RTC memory 357 when none of the first RAM clearing process (step SB117), setting value update process (FIG. 167), and setting confirmation process (FIG. 166) is executed, and new storage of date and time information does not occur in the RTC memory 357 when any of the first RAM clearing process (step SB117), setting value update process (FIG. 167), and setting confirmation process (FIG. 166) is executed. For example, a configuration in which new storage of date and time information occurs in the RTC memory 357 may be adopted when none of the first RAM clearing process (step SB117), setting value update process (FIG. 167), and setting confirmation process (FIG. 166) is executed, or when the first RAM clearing process (step SB117) is executed. Alternatively, the configuration may be such that new date and time information is stored in the RTC memory 357 when none of the first RAM clearing process (step SB117), the setting value update process (FIG. 167), and the setting confirmation process (FIG. 166) is executed, or when the setting value update process (FIG. 167) is executed. Alternatively, the configuration may be such that new date and time information is stored in the RTC memory 357 when none of the first RAM clearing process (step SB117), the setting value update process (FIG. 167), and the setting confirmation process (FIG. 166) is executed, or when the setting confirmation process (FIG. 166) is executed.

In addition, the configuration may be such that new storage of date and time information occurs in the RTC memory 357 when none of the first RAM clearing process (step SB117), setting value update process (Figure 167), and setting confirmation process (Figure 166) is executed, when the setting value update process (Figure 167) is executed, or when the setting confirmation process (Figure 166) is executed.In addition, the configuration may be such that new storage of date and time information occurs in the RTC memory 357 when none of the first RAM clearing process (step SB117), setting value update process (Figure 167), and setting confirmation process (Figure 166) is executed, when the first RAM clearing process (step SB117) is executed, or when the setting confirmation process (Figure 166) is executed. Furthermore, if none of the first RAM clearing process (step SB117), setting value update process (FIG. 167), and setting confirmation process (FIG. 166) is executed, or if the first RAM clearing process (step SB117) is executed, or if the setting value update process (FIG. 167) is executed, new storage of date and time information in the RTC memory 357 may occur.

Also, a configuration may be adopted in which new date and time information is stored in the RTC memory 357 when the first RAM clearing process (step SB117) is executed, but new date and time information is not stored in the RTC memory 357 in other cases.Also, a configuration may be adopted in which new date and time information is stored in the RTC memory 357 when the setting value update process (Figure 167) is executed, but new date and time information is not stored in the RTC memory 357 in other cases.Also, a configuration may be adopted in which new date and time information is stored in the RTC memory 357 when the setting confirmation process (Figure 166) is executed, but new date and time information is not stored in the RTC memory 357 in other cases.Also, a configuration may be adopted in which new date and time information is stored in the RTC memory 357 when the first RAM clearing process (step SB117) or the setting value update process (Figure 167) is executed, but new date and time information is not stored in the RTC memory 357 in other cases. It is also possible to configure the system so that new storage of date and time information occurs in the RTC memory 357 when the first RAM clear process (step SB117) or the setting confirmation process (FIG. 166) is executed, but that new storage of date and time information does not occur in the RTC memory 357 in other cases. It is also possible to configure the system so that new storage of date and time information occurs in the RTC memory 357 when the setting value update process (FIG. 167) or the setting confirmation process (FIG. 166) is executed, but that new storage of date and time information does not occur in the RTC memory 357 in other cases.

Also, when the setting value update process (Figure 167) is executed, the entire work area 221 for specific control, including the setting reference area 341 and the setting update area 342, may be cleared to "0" during the initial setting process (step SB303) at the start, and initialization may be performed. In this case, the second RAM clear process (step SB313) may not be executed during the setting value update process (Figure 167).

In addition, when the setting value update process (Figure 167) is initiated, the setting value may be changed starting from a predetermined setting value other than "Setting 1." For example, the setting value may be changed starting from "Setting 2," "Setting 3," "Setting 4," "Setting 5," or "Setting 6."

Furthermore, when the setting value update process (Figure 167) is initiated, the setting value information stored in the setting reference area 341 may be overwritten in the setting update area 342, as in the 45th embodiment above, thereby initiating a change of the setting value from the setting value that had been set as the target for use up until that point.

Also, the process for sending various return commands in the main process (Figure 165) may be configured to be set as a process before the remaining processes (steps SB125 to SB128) are started. In this case, when any of the first RAM clear process (step SB117), setting value update process (Figure 167), and setting confirmation process (Figure 166) is executed, a corresponding flag may be set, and the process for sending the various return commands may send a return command corresponding to the state of that flag to the audio/visual side CPU 353.

In addition to or instead of a configuration in which a time-responsive effect is executed each time a predetermined time elapses based on the date and time information stored in the RTC memory 357, a configuration in which monitoring for the occurrence of a predetermined abnormality occurs each time a predetermined time elapses based on the date and time information stored in the RTC memory 357 may be adopted, or a configuration in which a base value is reported each time a predetermined time elapses based on the date and time information stored in the RTC memory 357 may be adopted. In this case, the RTC 356 and the RTC memory 357 may be provided on the main control board 61, and the main CPU 63 may perform the abnormality monitoring or report the base value. By simultaneously monitoring abnormalities on multiple pachinko machines 10 installed in a gaming hall and reporting the results, for example, via the symbol display device 41, it becomes possible to periodically monitor multiple pachinko machines 10 collectively for the occurrence of a predetermined abnormality. Furthermore, by simultaneously reporting the base value via the symbol display device 41, it becomes possible to periodically monitor multiple pachinko machines 10 collectively. Note that the various notifications mentioned above are not limited to being made by the pachinko machine 10 itself, but may also be made by external output to the gaming hall's management computer.

Furthermore, if the main processing (Fig. 165) determines that the power outage flag is not set to "1", if it determines that the checksum is abnormal, or if it determines that the setting value in the setting reference area 341 is abnormal, the setting value update processing (Fig. 165) may be forcibly executed regardless of whether a "setting change operation" has been performed. This makes it possible to immediately change the setting value if an information abnormality occurs in the main RAM 65.

<Fiftieth embodiment>
In this embodiment, the processing configuration of the performance control process executed by the sound/light CPU 353 is different from that of the 49th embodiment. The configuration that differs from the 49th embodiment will be explained below. Note that the explanation of the same configuration as the 49th embodiment will basically be omitted.

Figure 175 is a flowchart showing the performance control process in this embodiment executed by the sound and light side CPU 353.

Steps SB501 to SB505 are identical to steps SB401 to SB405 of the performance control process (Figure 173) in the 49th embodiment. If a normal return command, a return command upon clearing, a return command upon confirmation, or a return command upon updating is received from the main CPU 63 (step SB505: YES), a determination is made as to whether the return command received this time is a return command other than a normal return command (step SB506).

If the currently received return command is either a return command upon clearing, a return command upon confirmation, or a return command upon updating (step SB506: YES), the current date and time information of the RTC 356 is read, and the read date and time information is stored in the RTC memory 357 (step SB407), similar to step SB407 of the performance control process (FIG. 173) in the 49th embodiment. As a result, the date and time information that serves as the reference when determining the timing to execute a time-responsive performance is stored in the RTC memory 357.

Steps SB508 to SB514 execute the same processing as steps SB408 to SB414 of the performance control processing (Figure 173) in the 49th embodiment described above.

Figure 176 is an explanatory diagram illustrating the actions corresponding to the processing executed when the supply of operating power to the main CPU 63 starts (steps SB101 to SB122).

Similar to the 49th embodiment described above, in the processing at the start of the supply of operating power in the main CPU 63 (steps SB101 to SB122), if none of the first RAM clear processing (step SB117), setting confirmation processing (FIG. 166), and setting value update processing (FIG. 167) is executed, the main CPU 63 sends a normal return command to the sound/light side CPU 353; if the first RAM clear processing (step SB117) is executed, the main CPU 63 sends a return command at the time of clearing to the sound/light side CPU 353; if the setting value update processing (FIG. 167) is executed, the main CPU 63 sends a return command at the time of updating to the sound/light side CPU 353; and if the setting confirmation processing (FIG. 166) is executed, the main CPU 63 sends a return command at the time of confirmation to the sound/light side CPU 353.

As in the 49th embodiment above, when the sound/light side CPU 353 receives a return command during update, it terminates the notification corresponding to the execution of the setting value update process (Figure 167), and when it receives a return command during confirmation, it terminates the notification corresponding to the execution of the setting confirmation process (Figure 166). Also, as in the 49th embodiment above, even if the sound/light side CPU 353 receives a normal return command or a return command during clearing, it does not execute any control related to the notification.

When the sound/light side CPU 353 receives any of the clearing return command, updating return command, and confirmation return command, it stores the current date and time information measured by the RTC 356 in the RTC memory 357. As a result, information corresponding to the reference time referenced to determine the timing of the execution of the time-responsive effect is newly stored in the RTC memory 357. On the other hand, even when the sound/light side CPU 353 receives a normal return command, it does not store the current date and time information measured by the RTC 356 in the RTC memory 357. Because backup power is supplied to the RTC memory 357, if no new date and time information is stored in the RTC memory 357, the date and time information stored in the RTC memory 357 before the power to the pachinko machine 10 was turned off is retained.

According to the above configuration, if any of the first RAM clearing process (step SB117), setting value update process (Figure 167), and setting confirmation process (Figure 166) is executed during the processing at the start of supplying operating power (steps SB101 to SB122), the date and time information stored in the RTC memory 357 is rewritten to the current date and time information measured by the RTC 356, whereas if none of the first RAM clearing process (step SB117), setting value update process (Figure 167), and setting confirmation process (Figure 166) is executed during the processing at the start of supplying operating power (steps SB101 to SB122), the date and time information stored in the RTC memory 357 is not rewritten. As a result, even if the power to the pachinko machine 10 is turned OFF temporarily for maintenance or an operation check of the pachinko machine 10 while the amusement hall is open, the date and time information stored in the RTC memory 357 can be prevented from being rewritten by turning the power to the pachinko machine 10 ON in a "no operation" state when the supply of operating power is subsequently resumed. Therefore, when the power to the pachinko machine 10 is turned OFF temporarily while the amusement hall is open and then the supply of operating power is resumed, it is possible to improve operability by resuming the supply of operating power to the pachinko machine 10 while maintaining the same reference time for time-responsive effects between the pachinko machine 10 and surrounding pachinko machines 10 in the amusement hall.

In addition, by turning on the power to the pachinko machine 10 in a "no operation" state, the date and time information stored in the RTC memory 357 is not rewritten, so when the power to the pachinko machine 10 is turned on in a way that does not rewrite the date and time information stored in the RTC memory 357, it is possible to prevent unintended processes such as the first RAM clear process (step SB117), setting value update process (Figure 167), and setting confirmation process (Figure 166) from being executed.

<Fifty-first embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 49th embodiment. The configuration that differs from the 49th embodiment will be described below. Note that the description of the same configuration as the 49th embodiment will basically be omitted.

Figure 177 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SB601 to SB630 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Steps SB601 to SB622 execute the same processing as steps SB101 to SB122 in the main processing (Figure 165) in the 49th embodiment described above.

When step SB612, step SB613, step SB615, step SB618, or step SB622 is executed, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SB623). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment. If a value of 1 or greater is set in the checking counter, the check display continues on the first to fourth notification display devices 201 to 204, as in the 35th embodiment.

With the above configuration, when the supply of operating power to the main CPU 63 begins, the initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps SB601 to SB622) and before the remaining processing (steps SB627 to SB630) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, thereby reducing the processing load while the processing at the start of the supply of operating power is being executed.

Furthermore, while the setting confirmation process (FIG. 166) and setting value update process (FIG. 167) are executed as processes at the start of the supply of operating power (steps SB601 to SB622), the initial check period begins after the processes at the start of the supply of operating power have finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

Then, interrupt permission is set (step SB624). As a result, the first timer interrupt process (Fig. 133) is started by interrupting at the first interrupt period, and the second timer interrupt process (Fig. 134) is started by interrupting at the second interrupt period. When the second timer interrupt process (Fig. 134) is started by interrupting, the first to fourth notification display devices 201 to 204 are controlled to display a check display when the checking counter is set to a value of 1 or greater.

Then, it is determined whether the value of the checking counter in the specific control work area 221 is "0" (step SB625). The process waits in step SB625 until the value of the checking counter reaches "0." In this case, the startup processing flag in the specific control work area 221 remains set to "1." Therefore, even if the first timer interrupt process (FIG. 133) interrupts and starts, the various processes of the first timer interrupt process (FIG. 133), such as power outage monitoring, updating of various counters, and fraud monitoring, are executed, but the first timer interrupt process (FIG. 133) is terminated without executing any process to progress the game. Therefore, until the initial check period set in step SB623 has elapsed, the check display continues on the first through fourth alarm display devices 201-204, even though execution of processes to progress the game is prevented.

Then, the startup processing in progress flag in the specific control work area 221 is cleared to "0" (step SB626). When the startup processing in progress flag is cleared to "0," if the first timer interrupt process (FIG. 133) is initiated, a negative judgment is made in step S8906, which causes the processes of steps S8901 to S8905 as well as steps S8907 to S8920 to be executed, thereby canceling the state in which processes for progressing the game are not executed. Note that in step SB626, the power outage flag in the specific control work area 221 is also cleared to "0."

Then, the remaining processing of steps SB627 to SB630 continues. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134), but there is remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps SB627 to SB630. In this respect, the remaining processing of steps SB627 to SB630 can be said to be non-periodic processing executed non-periodically. Steps SB627 to SB630 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

With the above configuration, when the execution of processing to progress a game is blocked, a check display is displayed on the first through fourth notification display devices 201-204. This makes it possible to check whether the first through fourth notification display devices 201-204 are operating normally even when a game is not being played.

<Fifty-second embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 49th embodiment. The configuration that differs from the 49th embodiment will be described below. Note that the description of the same configuration as the 49th embodiment will basically be omitted.

Figure 178 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SB701 to SB734 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Unlike the 49th embodiment, the main processing of this embodiment does not execute the power-on initial setting process. Therefore, when the main processing is started, processing from step SB701 onwards begins without waiting for the predetermined wait time to elapse. Note that although the power-on initial setting process is not executed, access to the main RAM 65 is permitted when the main processing is started.

The main processing first executes the internal function register setting process (step SB701), similar to step SB102 of the main processing (FIG. 165) in the 49th embodiment, and then sets the startup processing in progress flag in the specific control work area 221 to "1" (step SB702), similar to step SB103 of the main processing (FIG. 165) in the 49th embodiment. Then, on the condition that the power outage flag is set to "1," the checksum is normal, the setting value is normal, and the setting update display flag in the specific control work area 221 is not set to "1" (steps SB703 to SB705: YES, step SB706: NO), it is determined whether the reset button 68c has been pressed (step SB707).

If the reset button 68c is not pressed (step SB707: NO), the system determines whether the game stop flag in the specific control work area 221 is set to "1" (step SB708). If the game stop flag is not set to "1" and the setting key insertion unit 68a is turned on using the setting key (step SB708: NO, step SB709: YES), or if the game stop flag is not set to "1" and the setting key insertion unit 68a is not turned on using the setting key and the setting confirmation display flag in the specific control work area 221 is set to "1" (steps SB708 and SB709: NO, step SB710: YES), the system executes a setting confirmation process (step SB711). This setting confirmation process executes steps SB201 to SB202 and steps SB204 to SB207 in the setting confirmation process of the 49th embodiment (FIG. 166).

In other words, in the setting confirmation process of this embodiment, a confirmation start command is not sent to the audio/visual CPU 353. Therefore, even if the setting confirmation process is executed in this embodiment, a notification corresponding to the setting confirmation process is not executed by the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54. As already explained in this embodiment, when the main process is started, the process from step SB701 onwards starts without waiting for the predetermined wait time to elapse, so it is possible that the operation start and initial setup of the pattern display device 41 have not yet been completed when the setting confirmation process is started. In response to this, by preventing the pattern display device 41 from executing a notification corresponding to the setting confirmation process as described above, it is possible to prevent display control of the pattern display device 41 from being started when the initial setup has not yet been completed. Note that a configuration may be adopted in which a notification corresponding to the setting confirmation process is executed by the display light-emitting unit 53 and the speaker unit 54 but not by the pattern display device 41.

After the setting confirmation process is executed, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SB712). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment. If the checking counter is set to a value of 1 or greater, the first to fourth alarm display devices 201 to 204 continue to display check information, as in the 35th embodiment. In other words, if the setting confirmation process is executed during the process at the start of the supply of operating power (steps SB701 to SB729), the first to fourth alarm display devices 201 to 204 begin displaying check information after the setting confirmation process is completed, and the check information is displayed when the process is not waiting to proceed.

If the reset button 68c has not been pressed, the game stop flag has not been set to "1", the setting key insertion section 68a has not been turned ON using the setting key, and the setting confirmation display flag in the specific control work area 221 has not been set to "1" (steps SB707 to SB710: NO), information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SB713). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (Figure 134) is activated, as in the 35th embodiment. If a value greater than 1 is set in the checking counter, the check display continues on the first to fourth notification display devices 201 to 204, as in the 35th embodiment.

Then, interrupt permission is set (step SB714). As a result, the first timer interrupt process (Fig. 133) is started by interrupting at the first interrupt cycle, and the second timer interrupt process (Fig. 134) is started by interrupting at the second interrupt cycle. When the second timer interrupt process (Fig. 134) is started by interrupting, the first to fourth notification display devices 201 to 204 are controlled to display a check display when the checking counter is set to a value of 1 or greater.

Then, the wait process is executed (step SB715). The wait process waits until the value of the check counter in the specific control work area 221 reaches "0." In this case, the startup process flag in the specific control work area 221 remains set to "1." Therefore, even if the first timer interrupt process (Fig. 133) interrupts and starts, the various processes of the first timer interrupt process (Fig. 133) for power outage monitoring, updating various counters, and fraud monitoring are executed, while the first timer interrupt process (Fig. 133) ends without executing any processes for progressing the game. Therefore, until the initial check period set in step SB713 has elapsed, the check display continues on the first through fourth notification display devices 201-204, even though execution of processes for progressing the game is prevented. Furthermore, during the waiting time in the wait process, the operation start and initial setting of the symbol display device 41 are completed. In other words, by utilizing the wait period that prevents the execution of processing to progress the game until the symbol display device 41 starts operating and the initial settings are complete, it is possible to cause the first through fourth notification display devices 201-204 to display check displays. After the wait processing (step SB715) is completed, a normal return command is sent to the sound/light side CPU 353 (step SB716), similar to step SB113 of the main processing (FIG. 165) in the 49th embodiment.

If the reset button 68c is pressed and the setting key insertion section 68a is turned ON using the setting key (step SB707 and step SB717: YES), the setting value update process is executed (step SB718). Also, regardless of whether the above-mentioned "setting change operation" has been performed, if the setting update display flag in the specific control work area 221 is set to "1" (step SB706: YES), the setting value update process is executed (step SB717). In the setting value update process, steps SB301 to SB304 and steps SB306 to SB314 are executed in the setting value update process of the 49th embodiment (FIG. 167).

In other words, in the setting value update process of this embodiment, an update start command is not sent to the audio/visual side CPU 353. Therefore, even if the setting value update process is executed in this embodiment, a notification corresponding to the setting value update process is not executed by the pattern display device 41, the display light-emitting unit 53, and the speaker unit 54. As already explained in this embodiment, when the main process is started, the process from step SB701 onwards starts without waiting for the predetermined wait time to elapse, so it is possible that the operation start and initial setup of the pattern display device 41 have not yet been completed when the setting value update process is started. In response to this, by preventing the pattern display device 41 from executing a notification corresponding to the setting value update process as described above, it is possible to prevent display control of the pattern display device 41 from being started when the initial setup has not yet been completed. Note that a configuration may be adopted in which a notification corresponding to the setting value update process is executed by the display light-emitting unit 53 and the speaker unit 54 but not by the pattern display device 41.

After the setting value update process is executed, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SB719). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment. If the checking counter is set to a value of 1 or greater, the first to fourth alarm display devices 201-204 continue to display check information, as in the 35th embodiment. In other words, if the setting value update process is executed during the process at the start of operating power supply (steps SB701 to SB729), the first to fourth alarm display devices 201-204 begin displaying check information after the setting value update process is completed, and the check information is displayed when the process is not pending.

If the reset button 68c is pressed but the setting key insertion section 68a is not turned ON (step SB707: YES, step SB717: NO), the first RAM clear process is executed (step SB721) provided that the game stop flag in the specific control work area 221 is not set to "1" (step SB720: NO). The content of the first RAM clear process is the same as the first RAM clear process (step SB117) in the main process (Figure 165) in the 49th embodiment.

Then, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SB722). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment. If a value of 1 or greater is set in the checking counter, the check display continues on the first to fourth notification display devices 201 to 204, as in the 35th embodiment.

Then, interrupt permission is set (step SB723). As a result, the first timer interrupt process (Fig. 133) is started by interrupting at the first interrupt period, and the second timer interrupt process (Fig. 134) is started by interrupting at the second interrupt period. When the second timer interrupt process (Fig. 134) is started by interrupting, the first to fourth notification display devices 201 to 204 are controlled to display a check display when the checking counter is set to a value of 1 or greater.

Then, the wait process is executed (step SB724). The wait process waits until the value of the check counter in the specific control work area 221 reaches "0." In this case, the startup process flag in the specific control work area 221 remains set to "1." Therefore, even if the first timer interrupt process (Fig. 133) interrupts and starts, the various processes of the first timer interrupt process (Fig. 133) for power outage monitoring, updating various counters, and fraud monitoring are executed, while the first timer interrupt process (Fig. 133) ends without executing any processes for progressing the game. Therefore, until the initial check period set in step SB722 has elapsed, the check display continues on the first through fourth notification display devices 201-204, even though execution of processes for progressing the game is prevented. Furthermore, during the waiting time in the wait process, the operation start and initial configuration of the symbol display device 41 are completed. In other words, the first through fourth notification display devices 201-204 can display checks during the wait period, which prevents the execution of processing to progress the game until the symbol display device 41 starts operating and the initial settings are complete. After the wait processing (step SB724) is completed, a return command upon clearing is sent to the sound/light side CPU 353 (step SB725), similar to step SB118 of the main processing (FIG. 165) in the 49th embodiment.

If a negative judgment is made in any of steps SB703 to SB705, the game stop flag in the specific control work area 221 is set to "1" (step SB726), and then it is determined whether the reset button 68c has been pressed (step SB727). If the reset button 68c has been pressed and the setting key insertion section 68a has been turned ON using the setting key (steps SB717 and SB727: YES), a setting value update process is executed in step SB718, and a checking counter setting process is executed in step SB719. The contents of these processes have already been explained.

If the reset button 68c has not been pressed (step SB727: NO), if it is determined in step SB720 that the game stop flag is set to "1", or if it is determined in step SB708 that the game stop flag is set to "1", steps SB728 and SB729 are executed. The processing content of steps SB728 and SB729 is the same as steps SB121 and SB122 of the main processing (Figure 165) in the 49th embodiment.

When step SB712, step SB716, step SB719, step SB725, or step SB729 is executed, the startup processing flag in the specific control work area 221 is cleared to "0" (step SB730). When the startup processing flag is cleared to "0," and the first timer interrupt process (FIG. 133) is initiated, a negative judgment is made in step S8906, which causes not only the processes of steps S8901 to S8905 but also the processes of steps S8907 to S8920 to be executed, thereby canceling the state in which processing to progress the game is not being executed. In addition, step SB730 also clears the power outage flag in the specific control work area 221 to "0."

Then, the process proceeds to the remaining processing of steps SB731 to SB734. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134), but there is remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps SB731 to SB734. In this respect, the remaining processing of steps SB731 to SB734 can be said to be non-periodic processing executed non-periodically. Steps SB731 to SB734 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

With the above configuration, if the setting confirmation process (step SB711) and setting value update process (step SB718) are not executed during the process at the start of the supply of operating power (steps SB701 to SB729), the check display will continue on the first through fourth notification display devices 201 to 204 while waiting for the process to proceed during the wait process. This makes it possible to display the check display on the first through fourth notification display devices 201 to 204 by utilizing the wait period that prevents the execution of the process to progress the game until the symbol display device 41 starts operating and the initial settings are complete. It also makes it possible to ensure an opportunity to check the check display on the first through fourth notification display devices 201 to 204 before the process to progress the game begins.

On the other hand, the setting confirmation process (step SB711) or setting value update process (step SB718) will not end until the setting key insertion unit 68a is turned OFF by at least the gaming hall manager. Therefore, by the time the setting confirmation process (step SB711) or setting value update process (step SB718) is completed, more time will have passed than the time required for the symbol display device 41 to start operating and for initial settings to be completed. In this case, by not executing the wait process when the setting confirmation process (step SB711) or setting value update process (step SB718) is executed, it is possible to prevent the time required for processing to progress the game from becoming excessively long when the setting confirmation process (step SB711) or setting value update process (step SB718) is executed.

In addition, when the setting confirmation process (step SB711) or the setting value update process (step SB718) is executed, a check display is displayed on the first to fourth alert display devices 201-204 after the setting confirmation process (step SB711) or the setting value update process (step SB718) is completed. This makes it possible to display a check display on the first to fourth alert display devices 201-204 without affecting the display of setting values using the first to fourth alert display devices 201-204.

<Fifty-third embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 49th embodiment. The configuration that differs from the 49th embodiment will be described below. Note that the description of the same configuration as the 49th embodiment will basically be omitted.

Figure 179 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SB801 to SB826 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

First, the power-on initialization process is executed (step SB801). During the power-on initialization process, for example, the main process is started and the process waits until a predetermined waiting time (specifically, one second) has elapsed before proceeding to the next process. During this predetermined waiting period, the operation of the pattern display device 41 is started and the initial settings are completed. In addition, access to the main RAM 65 is permitted.

Then, the internal function register setting process is executed (step SB802). In the internal function register setting process, as in the 35th embodiment, the interrupt period of the first timer interrupt process (FIG. 133), which is a process that periodically interrupts the main process and is started, is set to the first interrupt period (specifically, 4 milliseconds), and the interrupt period of the second timer interrupt process (FIG. 134), which is a process that periodically interrupts the main process and is started, is set to a second interrupt period (specifically, 2 milliseconds), which is shorter than the first interrupt period.

In other words, in this embodiment, as in the 35th embodiment, there are first timer interrupt processing (FIG. 133) and second timer interrupt processing (FIG. 134) so that the interrupt periods are relatively long and short as timer interrupt processing. Both the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are started by interrupting the main processing. Also, the second timer interrupt processing (FIG. 134) is started by interrupting the first timer interrupt processing (FIG. 133). On the other hand, the first timer interrupt processing (FIG. 133) is not started by interrupting the second timer interrupt processing (FIG. 134). Also, if both the first interrupt period and the second interrupt period have elapsed when both the first timer interrupt processing (FIG. 133) and the second timer interrupt processing (FIG. 134) are not being executed, the second timer interrupt processing (FIG. 134) is started first, regardless of the order in which the periods elapse. In this regard, it can be said that the second timer interrupt process (FIG. 134) is started with priority over the first timer interrupt process (FIG. 133). However, this is not limited to this, and the first timer interrupt process (FIG. 133) may be started with priority over the second timer interrupt process (FIG. 134).

The internal function register setting process sets the first interrupt period of the first timer interrupt process (Figure 133) in a specified register of the main CPU 63, and sets the second interrupt period of the second timer interrupt process (Figure 134) in a specific register of the main CPU 63. In addition to setting the first and second interrupt periods, the internal function register setting process also performs processes such as setting the numerical ranges of various counters, such as the numerical range of the winning random number counter C1.

Then, the startup processing in progress flag provided in the work area 221 for specific control is set to "1" (step SB803). As with the 35th embodiment described above, the startup processing in progress flag is a flag that allows the main CPU 63 to identify a situation in which, even if the first timer interrupt processing (FIG. 133) is started, the various processes set in the first timer interrupt processing (FIG. 133) for power outage monitoring, updating of various counters, and fraud monitoring will be executed, but the first timer interrupt processing (FIG. 133) should be terminated without executing any processes for progressing the game.

The startup processing flag is set to "1" when the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) begins during the main processing (Fig. 165), and is cleared to "0" before the processing at the start of the supply of operating power ends and the remaining processing (steps SB819 to SB822) begins. As with the 35th embodiment, in the first timer interrupt processing (Fig. 133), if the startup processing flag is set to "1," the processing of steps S8907 to S8920 is not executed. This makes it possible to prevent the processing for progressing the game from being executed when the setting confirmation processing (step SB810) or setting value update processing (Fig. 181), described below, is being executed during the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826). On the other hand, as described above, even if the startup processing in progress flag is set to "1" in the first timer interrupt processing (FIG. 133), by executing steps S8901 to S8905, power outage monitoring is performed even when the setting confirmation processing (step SB810) or setting value update processing (FIG. 181), described below, of the processing performed when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826) is being performed, and the win random number counter C1, jackpot type counter C2, reach random number counter C3, and random number initial value counter CINI are updated, and fraud detection is also performed.

In particular, even when the startup processing flag is set to "1," the power outage information storage process (step S8901) is executed. This allows for power outage processing to be executed even if a power outage occurs while the setting confirmation process (step SB810) or setting value update process (FIG. 181), described below, is being executed among the processes performed when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826). As with the 35th embodiment, the power outage processing sets the power outage flag in the specific control work area 221 to "1," calculates a checksum, and stores the calculated checksum in the specific control work area 221. This prevents the restart of the supply of operating power from being identified as an abnormality in the main RAM 65. As a result, if a power outage occurs during the setting confirmation process (step SB810) or setting value update process (FIG. 181), it becomes possible to identify that the power outage occurred during these setting-related processes at the start of the next supply of operating power.

Incidentally, when the setting confirmation process (step SB810) or the setting value update process (Figure 181) is being executed, interrupts are not prohibited for either the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134), and interrupts can occur at any time. In this case, when the first timer interrupt process (Figure 133) or the second timer interrupt process (Figure 134) interrupts and is started during the setting confirmation process (step SB810) or the setting value update process (Figure 181), the return address information for the main process (Figure 179) to return to after the timer interrupt process that was started is completed is saved in the specific control stack area 222, and the information of the various registers of the main CPU 63 immediately before the timer interrupt process is started is saved in the specific control stack area 222. When the timer interrupt process that was the target of activation is completed, the process returns to the main process (FIG. 179) corresponding to the return address information saved in the specific control stack area 222, and the information saved in the specific control stack area 222 is restored to the various registers of the main CPU 63.

After setting the startup processing in progress flag to "1" in step SB803, it is determined whether the power outage flag provided in the work area 221 for specific control is set to "1" (step SB804). The power outage flag is set to "1" when power outage processing is executed in the power outage information storage processing (step S8901) of the first timer interrupt processing (Figure 133). The power outage flag is a flag that allows the main CPU 63 to determine whether power outage processing was performed appropriately the previous time the power was shut off.

If the power outage flag is set to "1" (step SB804: YES), it is determined whether the checksum is normal (step SB805). Specifically, the checksums are first calculated for the specific control work area 221 and the specific control stack area 222. The checksum calculation method is the same as in the 33rd embodiment. Then, the checksums for the specific control work area 221 and the specific control stack area 222, which were calculated and stored in the specific control work area 221 during the power outage processing executed immediately before the supply of operating power to the main CPU 63 was stopped, are read, and the read checksums are compared with the checksums calculated as described above during the current main processing. It is then determined whether the checksums match.

If the checksums match (step SB805: YES), it is determined whether the setting value corresponding to the information stored in the setting reference area 341 (see FIG. 154) in the specific control work area 221 is within the normal range (step SB806). The setting reference area 341 is a memory area that stores information used by the main CPU 63 to identify the current setting value of the pachinko machine 10, as in the 45th embodiment. If the setting reference area 341 stores the numerical information "1," the current setting value of the pachinko machine 10 is "Setting 1." If the setting reference area 341 stores the numerical information "2," the current setting value of the pachinko machine 10 is "Setting 2." If the setting reference area 341 stores the numerical information "3," the current setting value of the pachinko machine 10 is "Setting 3." If the setting reference area 341 stores the numerical information "4," the current setting value of the pachinko machine 10 is "Setting 4." If the numerical information "5" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 5." If the numerical information "6" is stored in the setting reference area 341, the current setting value of the pachinko machine 10 will be "Setting 6." In step SB806, it is determined whether the setting value information stored in the setting reference area 341 is any of "1" to "6."

If a positive determination is made in all of steps SB804 to SB806, it is determined whether the reset button 68c has been pressed (step SB807). In other words, it is determined whether the power to the pachinko machine 10 has been turned on while the reset button 68c is being pressed, and the supply of operating power to the main CPU 63 has begun. In this embodiment, as in the 35th embodiment, the main control unit 60 is provided with a setting key insertion unit 68a and a reset button 68c, but is not provided with an update button 68b. Furthermore, as in the 11th embodiment, the main control unit 60 is provided with first to fourth notification display devices 201 to 204, rather than first to third notification display devices 69a to 69c.

If the reset button 68c has not been pressed (step SB807: NO), it is determined whether the game stop flag or setting update display flag provided in the specific control work area 221 is set to "1" (step SB808).

The game stop flag is set to "1" if the power outage flag is not set to "1," if the checksums do not match, or if the setting value is abnormal. When the game stop flag is set to "1," steps S8901 to S8905 are executed in the first timer interrupt process (Figure 133), while a positive judgment in step S8906 prevents steps S8907 to S8920 from being executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly during the previous power outage, if the checksums do not match due to changes in the storage state of information in at least one of the specific control work area 221 and the specific control stack area 222 since the previous power outage, or if the setting value is abnormal, processing for power outage monitoring, updating various counters, and fraud monitoring is executed, but processing for progressing game play is not executed.

As in the 35th embodiment, the setting update display flag is a flag used by the main CPU 63 to identify that the setting value update process (Figure 181) is being executed. When the setting update display flag is set to "1," the first to fourth alarm display devices 201-204 display an indication that the setting values are being updated and an indication of the setting values currently being updated. The setting update display flag is set to "1" when the setting value update process (Figure 181) is initiated and cleared to "0" when the setting value update process (Figure 181) is terminated. Therefore, the setting update display flag is not generally set to "1" when the setting value update process (Figure 181) is not being executed. However, if the supply of operating power to the main CPU 63 is stopped while the setting value update process (Figure 181) is being executed, the setting update display flag will be set to "1" when the supply of operating power to the main CPU 63 is subsequently started. This setting update display flag will remain set to "1" until the setting value update process (Figure 181) clears the setting update display flag to "0."

If a negative judgment is made in step SB808 because the game stop flag and the setting update display flag are not set to "1," it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step SB809). If the setting key insertion unit 68a has been turned ON using the setting key (step SB809: YES), a setting confirmation process is executed (step SB810). The content of the setting confirmation process is the same as the setting confirmation process in the 49th embodiment (Figure 166). Note that in this embodiment, even if the supply of operating power is stopped while the setting confirmation process is being executed, the setting confirmation process will not be executed unless a "setting confirmation operation" is performed when the supply of operating power is resumed.

If the setting key insertion unit 68a has not been turned ON using the setting key (step SB809: NO), a return to normal command is sent to the audio and light control device 81 (step SB811). The processing executed by the audio and light control device 81 when it receives the return to normal command is the same as that in the 49th embodiment described above.

On the other hand, if it is determined in step SB807 that the reset button 68c has been pressed and that the setting key insertion section 68a has been turned ON using the setting key (step SB807 and step SB812: YES), the setting value update process is executed (step SB813). In other words, in this embodiment, even if the setting update display flag in the specific control work area 221 is set to "1," the setting value update process is not executed unless a "setting change operation" is performed when the supply of operating power to the main CPU 63 begins. Details of the setting value update process will be explained later.

If it is determined in step SB807 that the reset button 68c has been pressed, and it is determined that the setting key insertion unit 68a has not been turned ON using the setting key (step SB812: NO), it is determined whether the game stop flag or setting update display flag in the specific control work area 221 is set to "1" (step SB814).

If both the game stop flag and the setting update display flag are not set to "1" (step SB814: NO), the first RAM clear process is executed (step SB815). In the first RAM clear process, similar to the RAM clear process (step SA416) in the 45th embodiment, the specific control work area 221 is cleared to "0" and initialized, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (i.e., the setting reference area 341). This clears the area indicating whether the win/loss lottery mode is in the high-probability mode to "0," thereby changing the win/loss lottery mode to the low-probability mode regardless of the win/loss lottery mode in effect immediately before the supply of operating power to the pachinko machine 10 was stopped. Furthermore, a game round is not being played, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserve storage area 65a and the normal power reserve area 65c provided in the work area 221 for specific control are also cleared to "0," thereby erasing the reserve information for the special map display unit 37a and the reserve information for the normal map display unit 38a. The setting update display flag and setting confirmation display flag provided in the work area 221 for specific control are cleared to "0." The setting update area 342 provided in the work area 221 for specific control is cleared to "0." The first RAM clearing process clears the stack area 222 for specific control to "0" and performs initial settings. The first RAM clearing process also clears various registers of the main CPU 63 to "0" and then performs initial settings. This initial setting process performs the same processing as the internal function register setting process in step SB802. Note that the process for clearing the work area 223 for non-specific control and the process for performing initial settings are not performed for the stack area 224 for non-specific control and the work area 223 for non-specific control.

Then, a clear-time return command is sent to the audio and light emission control device 81 (step SB816). The processing executed by the audio and light emission control device 81 when a clear-time return command is received is the same as that of the 49th embodiment described above.

When step SB810, step SB811, step SB813, or step SB816 is executed, information corresponding to the initial check period (specifically, 5 seconds) is set in the checking counter provided in the specific control work area 221 (step SB817). The value set in the checking counter is decremented by 1 each time the second timer interrupt process (FIG. 134) is initiated, as in the 35th embodiment. If a value of 1 or greater is set in the checking counter, the check display continues on the first to fourth notification display devices 201 to 204, as in the 35th embodiment.

With the above configuration, when the supply of operating power to the main CPU 63 begins, the initial check period begins after the main CPU 63 has completed the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) and before the remaining processing (steps SB819 to SB822) begins. This eliminates the need to control the initial check period while the processing at the start of the supply of operating power is being executed, thereby reducing the processing load while the processing at the start of the supply of operating power is being executed.

Furthermore, while the setting confirmation process (step SB810) and the setting value update process (FIG. 181) are executed as processes at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826), the initial check period begins after the processes at the start of the supply of operating power have finished. This makes it possible to ensure that even if a check display is performed on the first to fourth alarm display devices 201 to 204 during the initial check period, this does not affect the display of setting values using the first to fourth alarm display devices 201 to 204.

Then, the startup processing in progress flag in the specific control work area 221 is cleared to "0" (step SB818). When the startup processing in progress flag is cleared to "0," if the first timer interrupt process (FIG. 133) is initiated, a negative judgment is made in step S8906, which causes the processes of steps S8901 to S8905 as well as steps S8907 to S8920 to be executed, thereby canceling the state in which processes for progressing the game are not executed. Note that in step SB818, the power outage flag in the specific control work area 221 is also cleared to "0."

Then, the process proceeds to the remaining processing of steps SB819 to SB822. In other words, the main CPU 63 is configured to periodically execute the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134), but there is remaining time between one timer interrupt processing and the next. This remaining time will vary depending on the completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining processing of steps SB819 to SB822. In this respect, the remaining processing of steps SB819 to SB822 can be said to be non-periodic processing executed non-periodically. Steps SB819 to SB822 execute the same processing as steps S113 to S116 of the main processing (Figure 9) in the first embodiment described above.

If a negative judgment is made in any of steps SB804 to SB806 in the main processing (Figure 179), i.e., if the power outage flag is not set to "1", if the checksum does not match, or if the setting value is abnormal, the game stop flag in the specific control work area 221 is set to "1" (step SB823). As already explained, when the game stop flag is set to "1", the processing of steps S8901 to S8905 is executed in the first timer interrupt processing (Figure 133), while a positive judgment is made in step S8906, the processing of steps S8907 to S8920 is not executed. As a result, if the power outage flag is not set to "1" because power outage processing was not performed properly the previous time the power was shut down, if the checksums do not match because the information storage state has changed since the previous power outage in at least one of the specific control work area 221 and the specific control stack area 222, or if the setting value is abnormal, processing will be executed to monitor the power outage, update various counters, and monitor for fraud, but processing to progress the game will not be executed.

Then, it is determined whether the reset button 68c has been pressed (step SB824). If the reset button 68c has not been pressed (step SB824: NO), an abnormality command indicating that an abnormality occurred with the power outage flag, checksum, or setting value when the supply of operating power began is sent to the audio and light-emitting control device 81 (step SB825). Upon receiving the abnormality command, the audio and light-emitting control device 81 causes the display light-emitting unit 53 to emit light in a manner corresponding to the information abnormality when the supply of operating power began, and outputs a voice message saying "Please change the settings" from the speaker unit 54. It also causes the symbol display device 41 to display a text image saying "Please change the settings." These notifications are maintained until the supply of operating power to the pachinko machine 10 is stopped, and are terminated when the supply of operating power to the pachinko machine 10 is stopped. However, even if the supply of operating power to the pachinko machine 10 is temporarily stopped, the above notification will resume when the supply of operating power to the pachinko machine 10 is resumed until the setting value update process (Figure 181) is executed.

Then, external output processing in the event of an abnormality is executed (step SB826). In the external output processing in the event of an abnormality, processing is executed to externally output an abnormality signal to the amusement hall's management computer. In this case, the signal output of the abnormality signal is performed for a predetermined period (e.g., 100 milliseconds). However, this is not limited to this, and the signal output of the abnormality signal may continue when an event that triggers execution of the processing of step SB826 occurs, and the signal output of the abnormality signal may be stopped when an event that triggers execution of the processing of step SB826 does not occur. Furthermore, the abnormality signal is not output only in step SB826, but may also be output by other processing. For example, an abnormality signal is output externally when the fraud detection processing (step S8905) of the first timer interrupt processing (Figure 133) identifies the occurrence of fraud (detection of unauthorized radio waves or unauthorized magnetic fields) that is being monitored. However, this is not limited to a configuration in which the abnormality signal is used for both purposes, and a dedicated abnormality signal for step SB826 may be output externally.

If the reset button 68c is pressed (step SB824: YES), it is determined whether the setting key insertion unit 68a has been turned ON using the setting key (step SB812). If the reset button 68c is pressed and the setting key insertion unit 68a has been turned ON using the setting key (step SB812 and step SB824: YES), the setting value update process is executed (step SB813). In other words, if operating power is supplied to the main CPU 63 while a "setting change operation" is being performed, the setting value update process (Figure 181) is executed even if a negative determination is made in any of steps SB804 to SB806 due to an abnormality in the main RAM 65. This allows the setting value change to be prioritized.

On the other hand, if the reset button 68c has been pressed but the setting key insertion section 68a has not been turned ON (step SB824: YES, step SB812: NO), a determination is made as to whether the game stop flag or setting update display flag in the specific control work area 221 is set to "1" (step SB814). Since the game stop flag is naturally set to "1" by the processing of step SB814 after the game stop flag is set to "1" in step SB823, a positive determination is made in step SB814. In this case, an abnormality command is sent to the sound and light emission control device 81 in step SB825, and an abnormality signal is output externally in step SB826. Subsequently, the processing proceeds to the remaining processing of steps SB819 to SB822 without executing the processing of steps SB817 and SB818.

In other words, if an abnormality occurs with the power outage flag, checksum, or setting value and a negative judgment is made in any of steps SB804 to SB806, the first RAM clear process (step SB815) is not executed, even if the supply of operating power to the main CPU 63 is initiated while the "RAM clear operation" is being performed. Similarly, the first RAM clear process (step SB815) is not executed even if the supply of operating power to the main CPU 63 is initiated while the "RAM clear operation" is being performed and the game stop flag is set to "1." This prevents the game stop flag from being cleared from "1" even if the supply of operating power to the main CPU 63 is initiated while the "RAM clear operation" is being performed. In contrast, if a "setting change operation" is being performed, the setting value update process (Fig. 181) is executed regardless of whether the game stop flag is set to "1." Furthermore, the game stop flag is cleared to "0" by the initial setting at the start of the setting value update process (Fig. 181), as will be described in detail below. As a result, in order to cancel the state in which the game stop flag is set to "1", it becomes necessary to execute the setting value update process (Fig. 181). Therefore, when an information abnormality occurs in the work area 221 for specific control, it is possible to not only execute the process to initialize the work area 221 for specific control, but also to reset the setting value.

Here, if it is determined in step SB807 that the reset button 68c has not been pressed, and if it is determined in step SB808 that the game stop flag or setting update display flag in the specific control work area 221 is set to "1," an abnormal command is sent to the sound and light emission control device 81 in step SB825, and an abnormal signal is output externally in step SB826. After these processes are performed, the process proceeds to the remaining processes of steps SB819 to SB822 without performing the processes of steps SB817 and SB818. Furthermore, even if step SB807 determines that the reset button 68c has been pressed and step SB812 determines that the setting key insertion section 68a has not been turned ON (i.e., a "RAM clear operation" has been performed), if the game stop flag or setting update display flag in the specific control work area 221 is set to "1," a positive determination is made in step SB814, an abnormality command is sent to the sound and light emission control device 81 in step SB825, and an abnormality signal is output externally in step SB826. After these processes are performed, the process proceeds to the remaining processes of steps SB819 to SB822 without performing the processes of steps SB817 and SB818.

Next, we will explain the subsequent processing when the supply of operating power to the main CPU 63 is stopped while the setting value update process (Figure 181) is being executed, with reference to the time chart in Figure 180. FIG. 180(a) shows the period during which the power to the pachinko machine 10 is ON, FIG. 180(b) shows the period during which processing is being performed when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826), FIG. 180(c) shows the period during which processing is being performed after the processing when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826) has finished, FIG. 180(d) shows the period during which setting value update processing (FIG. 181) is being performed, FIG. 180(e) shows the period during which the setting update display flag in the specific control work area 221 is set to "1", FIG. 180(f) shows the period during which the startup processing in progress flag in the specific control work area 221 is set to "1", and FIG. 180(g) shows the period during which an abnormality signal is being output externally.

At timing t1, the power to the pachinko machine 10 is turned ON as shown in Figure 180(a). In this case, the power to the pachinko machine 10 is turned ON while a "setting change operation" has been performed. At timing t1, as shown in Figure 180(b), the main CPU 63 starts processing when the supply of operating power begins (steps SB801 to SB818, steps SB823 to SB826), and the startup processing in progress flag in the work area 221 for specific control is set to "1" as shown in Figure 180(f).

Then, at timing t2, the setting value update process (Figure 181) is started as shown in Figure 180(d). In this case, at timing t2, the setting update display flag in the work area 221 for specific control is set to "1" as shown in Figure 180(e).

Then, as shown in FIG. 180(d), at timing t3 while the setting value update process (FIG. 181) is being executed, the power to the pachinko machine 10 is turned off, thereby stopping the supply of operating power to the main CPU 63. Therefore, as shown in FIG. 180(b), the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) ends, and the setting value update process (FIG. 181) ends, as shown in FIG. 180(d).

After that, at timing t4, the power to the pachinko machine 10 is turned ON again, as shown in Figure 180(a). In this case, the power to the pachinko machine 10 is turned ON when the "RAM clear operation" has been performed. At timing t4, as shown in Figure 180(b), the main CPU 63 starts processing when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826). Also, as shown in Figures 180(e) and 180(f), both the setting update display flag and the startup processing in progress flag in the specific control work area 221 remain set to "1", as they were before the previous shutdown of the supply of operating power.

In this case, the pachinko machine 10 is powered on when the "RAM clear operation" is performed while the setting update display flag is set to "1." Therefore, the first RAM clear process (step SB815) is not executed, and an abnormality signal is output externally for a predetermined period (e.g., 100 milliseconds) from timing t5 to timing t7, as shown in FIG. 180 (g). Furthermore, at timing t5, an abnormality notification is initiated based on the transmission of the abnormality command.

As shown in Figure 180(b), the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) that began at time t4 ends at time t6. Then, at time t6, processing begins after the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) has ended.

In this case, as shown in Figure 180 (f), the startup processing in progress flag in the specific control work area 221 is set to "1", so even if the first timer interrupt processing (Figure 133) is started, processing for power outage monitoring, updating various counters, and fraud monitoring is executed, but processing for progressing the game is not executed. Then, at timing t8, as shown in Figure 180 (a), the power to the pachinko machine 10 is turned off, stopping the supply of operating power to the main CPU 63. Also, at timing t8, post-supply processing ends as shown in Figure 180 (c).

After that, at timing t9, the power to the pachinko machine 10 is turned ON again, as shown in Figure 180(a). In this case, the power to the pachinko machine 10 is turned ON while a "setting change operation" has been performed. At timing t9, as shown in Figure 180(b), the main CPU 63 starts processing when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826). Also, as shown in Figures 180(e) and 180(f), both the setting update display flag and the startup processing in progress flag in the specific control work area 221 remain set to "1", as they were before the previous shutdown of the supply of operating power.

Then, the setting value update process (Figure 181) is executed from time t10 to time t11, as shown in Figure 180(d). In this case, the setting value update process (Figure 181) ends normally. Then, at time t11, the setting update display flag is cleared to "0," as shown in Figure 180(e). Also, at time t11, the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) ends, as shown in Figure 180(b). As a result, at time t11, the startup processing in progress flag is cleared to "0," as shown in Figure 180(f). Then, at time t11, the processing after the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) ends begins, as shown in Figure 180(c). In this case, the startup processing flag has already been cleared to "0," so when the first timer interrupt process (Fig. 133) is started, not only will it perform processes to monitor for power outages, update various counters, and monitor for fraud, but it will also perform processes to allow the game to proceed.

If the supply of operating power to the main CPU 63 is stopped while the setting value update process (Figure 181) is being executed as described above, unless a "setting change operation" is performed when the supply of operating power to the main CPU 63 is resumed, the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826) will involve sending an abnormal command to the audio and light emission control device 81 and outputting an abnormal signal externally, and even if a "RAM clear operation" has been performed, the first RAM clear process (step SB815) will not be executed, and even if a "setting confirmation operation" has been performed, the setting confirmation process (step SB810) will not be executed. Furthermore, when an abnormal command is sent to the audio/light-emitting control device 81 and an abnormal signal is externally output, the remaining processing (steps SB819 to SB822) is executed without clearing the startup processing in progress flag to "0" in the specific control work area 221 (step SB818). Therefore, even if the first timer interrupt processing (FIG. 133) is initiated, processing for power outage monitoring, updating various counters, and fraud monitoring is executed, but processing for progressing the game is not executed. As a result, if the supply of operating power to the main CPU 63 is stopped while the setting value update processing (FIG. 181) is being executed, it becomes necessary to resume the supply of operating power to the main CPU 63 when a "setting change operation" is performed and execute the setting value update processing (FIG. 181). This makes it possible to reliably change the setting value.

Next, the setting value update process in this embodiment, which is executed in step SB813 of the main processing (Figure 179), will be described with reference to the flowchart in Figure 181. Note that the processing in steps SB901 to SB918 in the setting value update process is executed using the specific control program and specific control data in the main CPU 63.

First, the OFF confirmation flag 361 is set to "1" (step SB901). The OFF confirmation flag 361 is provided in the specific control work area 221, as shown in the explanatory diagram of FIG. 182. Even in this embodiment, in the setting value update process (FIG. 181), the value of the setting update area 342 in the specific control work area 221, i.e., the setting value to be updated, is incremented by 1 each time the reset button 68c is pressed. In this case, to ensure that the setting value to be updated is incremented by only "1" for each press of the reset button 68c, when the reset button 68c changes from a non-operated state to an operated state, i.e., when the detection signal from the detection sensor that detects the operation of the reset button 68c switches from a non-operated state to an operated state, the value of the setting update area 342 is incremented by 1, thereby incrementing the setting value to be updated by 1.

In this configuration, the OFF confirmation flag 361 is a flag used to check whether the timing is when pressing the reset button 68c has begun when checking whether the reset button 68c has been pressed during the setting value update process (FIG. 181). After the process (step SB910) for determining whether the reset button 68c has been pressed during the setting value update process (FIG. 181) is executed, if it is determined that the reset button 68c has been pressed, the OFF confirmation flag 361 is set to "1" or remains set to "1", and if it is determined that the reset button 68c has not been pressed, the OFF confirmation flag 361 is cleared to "0" or remains set to "0".

As already explained, the setting value update process (Figure 181) is executed on the condition that it is determined in step SB807 or step SB824 of the main process (Figure 179) that the reset button 68c has been pressed. In step SB807 or step SB824, the main CPU 63 determines whether the reset button 68c has been pressed by directly monitoring the input port to which a detection signal from a detection sensor that detects whether the reset button 68c has been pressed is input. In this case, rather than checking the start and end timing of the reset button 68c being pressed, it checks whether the reset button 68c is being pressed. Therefore, in step SB807 or step SB824, the OFF confirmation flag 361 is not checked, and a positive determination is made if a signal corresponding to the reset button 68c being pressed is input to the input port.

However, in this configuration, depending on the relationship between the timing at which the pressing of the reset button 68c to start the setting value update process (Fig. 181) ends when the pachinko machine 10 is powered on and the timing at which the setting value update process (Fig. 181) begins, the pressing may or may not trigger an increment of 1 to the setting value to be updated. This means that the update mode of the setting value to be updated will change depending on the timing at which the pressing of the reset button 68c ends when the pachinko machine 10 is powered on, reducing operability. In contrast, in a configuration in which the setting value to be updated is incremented by 1 when it is determined that the reset button 68c has been pressed while the OFF confirmation flag 361 is set to "0," by setting the OFF confirmation flag 361 to "1" in step SB901, which is executed before the process of determining whether the reset button 68c has been pressed, when the setting value update process (FIG. 181) is started, it is possible to prevent the setting value to be updated from being incremented by 1 due to the reset button 68c being pressed when the pachinko machine 10 is powered on.

After executing the processing of step SB901, interrupt permission is set (step SB902). As a result, the first timer interrupt processing (Fig. 133) is started by interrupting at the first interrupt period, and the second timer interrupt processing (Fig. 134) is started by interrupting at the second interrupt period. In this embodiment, as in the 49th embodiment, interrupts of the first timer interrupt processing (Fig. 133) and the second timer interrupt processing (Fig. 134) are basically prohibited in the processing when the supply of operating power starts (steps SB801 to SB818, steps SB823 to SB826), but interrupts are allowed in the setting confirmation processing (step SB810) and the setting value update processing (Fig. 181). Therefore, in the processing at the start of the supply of operating power (steps SB801 to SB818, steps SB823 to SB826), when the setting confirmation processing (step SB810) and the setting value update processing (Figure 181) are not being executed, the execution of the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134) is prohibited, and when the setting confirmation processing (step SB810) or the setting value update processing (Figure 181) is being executed, the execution of the first timer interrupt processing (Figure 133) and the second timer interrupt processing (Figure 134) is permitted. However, when the setting confirmation process (step SB810) or the setting value update process (FIG. 181) is being executed, the startup process in progress flag is set to "1", so even if the first timer interrupt process (FIG. 133) is started, the various processes of the first timer interrupt process (FIG. 133) such as power outage monitoring, updating of various counters, and fraud monitoring will be executed, but the first timer interrupt process (FIG. 133) will end without executing any processes to progress the game.

Then, on the condition that the setting update display flag provided in the specific control work area 221 is not set to "1," the setting update display flag is set to "1" (step SB903). When the setting update display flag is set to "1," a positive determination is made in step S9003 of the second timer interrupt process (FIG. 134), and setting processing for the fifth display data buffer 275 during setting update (step S9004) is executed. The processing content of the setting processing for the fifth display data buffer 275 during setting update is the same as that of the 45th embodiment described above. By executing this processing, for example, as shown in the explanatory diagram of FIG. 124(a), a display indicating that the setting values of the pachinko machine 10 are being updated and a display of the setting values selected to be updated for the pachinko machine 10 are displayed on the first to fourth notification display devices 201 to 204.

After that, initial settings are made at the start (step SB904). During this initial setting, the game stop flag set in the specific control work area 221 is cleared to "0." The game stop flag is set to "1" in step SB823 of the main processing (Fig. 179) when the power outage flag is not set to "1" because power outage processing was not performed properly during the previous power outage (step SB804: NO), when the checksums do not match for at least one of the specific control work area 221 and the specific control stack area 222 because the information storage state has changed since the previous power outage (step SB805: NO), or when the setting value corresponding to the information stored in the setting reference area 341 is not within the normal range (step SB806: NO). By setting the game stop flag to "1", steps S8901 to S8905 are executed in the first timer interrupt process (FIG. 133), but a positive determination in step S8906 prevents steps S8907 to S8920 from being executed. As a result, when an information abnormality occurs in the main RAM 65 as described above, processing for power outage monitoring, updating of various counters, and fraud monitoring is executed, but processing for progressing the game is not executed. By clearing the game stop flag to "0" in the processing of step SB904, it is possible to release the state in which an information abnormality in the main RAM 65 has been identified when the setting value update process (FIG. 181) is executed.

Then, "1" is set in the setting update area 342 (see FIG. 154) in the work area 221 for specific control (step SB905). The setting update area 342 is a memory area that stores information about setting values being updated during the setting value update process (FIG. 181), as in the 45th embodiment. If the setting update area 342 stores numerical information of "1," the setting value to be updated (selected or changed) becomes "Setting 1." If the setting update area 342 stores numerical information of "2," the setting value to be updated becomes "Setting 2." If the setting update area 342 stores numerical information of "3," the setting value to be updated becomes "Setting 3." If the setting update area 342 stores numerical information of "4," the setting value to be updated becomes "Setting 4." If the setting update area 342 stores numerical information of "5," the setting value to be updated becomes "Setting 5." If the setting update area 342 stores numerical information of "6," the setting value to be updated becomes "Setting 6."

By setting "1" in the setting update area 342 in step SB905, the setting value to be updated becomes "Setting 1." In other words, in this embodiment, regardless of the current setting value of the pachinko machine 10, when the setting value update process (Figure 181) is started, the setting value to be updated becomes "Setting 1."

An update start command is then sent to the audio and light-emitting control device 81 (step SB906). Upon receiving the update start command, the audio and light-emitting control device 81 controls the display control device 82 so that an image indicating that the setting value update process (FIG. 181) is being executed, an image enabling the user to recognize the operation details for changing the setting value, and an image enabling the user to recognize the operation details for terminating the setting value update process (FIG. 181) are displayed on the symbol display device 41. This allows the amusement hall manager to recognize that the setting value is being changed, and also allows the amusement hall manager to recognize the operation details required to change the setting value and the operation details required to terminate the setting value update process (FIG. 181). Note that the notification may be performed by at least one of the display light-emitting unit 53 and the speaker unit 54, in addition to or instead of being performed by the symbol display device 41. Furthermore, an external output indicating that the setting value update process (FIG. 181) is being executed may be provided to a device external to the pachinko machine 10, such as the amusement hall's management computer.

Then, it is determined whether the setting value information stored in the setting update area 342 is any of "1" to "6" (step SB907). If it is not any of "1" to "6" (step SB907: NO), "1" is set in the setting update area 342 (step SB908). As a result, the setting value to be updated becomes "Setting 1."

If a positive determination is made in step SB907 or if the processing of step SB908 is executed, it is determined whether the setting key insertion unit 68a has switched from the ON state to the OFF state using the setting key (step SB909). Specifically, it is determined whether the reception state of the signal received from the detection sensor that detects the state of the setting key insertion unit 68a has changed from a reception state corresponding to the ON state to a reception state corresponding to the OFF state.

If a negative determination is made in step SB909, it is determined whether the reset button 68c has been pressed (step SB910). Specifically, it is determined whether the reset button 68c has been pressed by directly monitoring the input port to which a detection signal from a detection sensor that detects whether the reset button 68c has been pressed is input. If the reset button 68c has not been pressed (step SB910: NO), the OFF confirmation flag 361 in the specific control work area 221 is cleared to "0" (step SB911), and the process returns to step SB907.

If the reset button 68c is being pressed (step SB910: YES), it is determined whether the value of the OFF confirmation flag 361 in the specific control work area 221 is "0" (step SB912). If the OFF confirmation flag 361 is set to "1" (step SB912: NO), this means that the current confirmation timing is not the start timing of the reset button 68c being pressed, but rather that the reset button 68c is still being pressed, and the process returns to step SB907 without incrementing the setting value to be updated by 1.

If the value of the OFF confirmation flag 361 is "0" (step SB912: YES), this indicates that the current confirmation timing is the start timing for pressing the reset button 68c. In this case, after the OFF confirmation flag 361 is set to "1" (step SB913), the value of the setting update area 342 is incremented by one (step SB914). This updates the setting value to the next higher level each time the reset button 68c is pressed. If the reset button 68c is not pressed (step SB910: NO), if the OFF confirmation flag 361 is set to "1" (step SB912: NO), or if the value of the setting update area 342 is incremented by one (step SB914), the process returns to step SB907. However, if it is determined in step SB907 that the value of the setting update area 342 is 7 or greater, the setting update area 342 is set to "1" in step SB908. As a result, if the reset button 68c is pressed once while in "Setting 6", the setting will return to "Setting 1".

If it is determined that the setting key insertion unit 68a has switched from the ON state to the OFF state (step SB909: YES), the setting value information stored in the setting update area 342 is overwritten in the setting reference area 341 (step SB915). As a result, the setting value information resulting from the update in this setting value update process (Figure 181) is set in the setting reference area 341, and the setting value corresponding to this set information becomes the current setting value of the pachinko machine 10.

Then, interrupts are disabled (step SB916). As a result, when the setting value update process (FIG. 181) is terminated and the process at the start of operating power supply in the main process (FIG. 179) (steps SB801 to SB818, steps SB823 to SB826) is returned to, interrupts for the first timer interrupt process (FIG. 133) and the second timer interrupt process (FIG. 134) are disabled.

Then, a second RAM clear process is executed (step SB917). In the second RAM clear process, similar to the RAM clear process (step SA416) in the 45th embodiment, the specific control work area 221 is cleared to "0" and initial settings are executed, except for the area in the specific control work area 221 where setting value information indicating the setting state of the pachinko machine 10 is set (i.e., the setting reference area 341). This clears to "0" the area indicating whether the win/loss lottery mode is the high-probability mode, so the win/loss lottery mode becomes the low-probability mode regardless of the win/loss lottery mode immediately before the supply of operating power to the pachinko machine 10 is stopped. Furthermore, a game round is not being executed, the open/close execution mode is not being executed, the normal map display unit 38a is not displaying a variable value, and the normal power device 34a is in a closed state. In addition, the reserve storage area 65a and the normal power reserve area 65c provided in the specific control work area 221 are also cleared to "0," thereby erasing the reserve information for the special map display unit 37a and the reserve information for the normal map display unit 38a. The setting update display flag and the setting confirmation display flag provided in the specific control work area 221 are cleared to "0." The setting update area 342 provided in the specific control work area 221 is cleared to "0." The game stop flag provided in the specific control work area 221 is cleared to "0." The second RAM clearing process clears the specific control stack area 222 to "0" and performs initial settings. The second RAM clearing process also clears various registers of the main CPU 63 to "0" and then performs initial settings. This initial setting process executes the same processing as the internal function register setting process in step SB802. Note that the process for clearing the non-specific control work area 223 and the non-specific control stack area 224 to "0" and the process for performing initial settings are not executed.

Then, a restore command for the update is sent to the audio and light emission control device 81 (step SB918). The processing executed by the audio and light emission control device 81 when the restore command for the update is received is the same as that of the 49th embodiment described above.

Next, the manner in which the setting values to be updated are updated will be explained with reference to the time chart in Figure 183. Figure 183(a) shows the period during which the power to the pachinko machine 10 is ON, Figure 183(b) shows the operation status of the setting key insertion section 68a, Figure 183(c) shows the operation status of the reset button 68c, Figure 183(d) shows the period during which the setting value update process (Figure 181) is being executed, Figure 183(e) shows the setting status of the OFF confirmation flag 361, and Figure 183(f) shows the timing of updating the setting values.

First, we will explain a comparative example in which the OFF confirmation flag 361 is not set to "1" when the setting value update process (Figure 181) is started.

At timing t1, as shown in Figure 183(b), the setting key insertion section 68a is turned ON using the setting key, and as shown in Figure 183(c), the reset button 68c is pressed. Then, at timing t2, while the setting key insertion section 68a is being turned ON and the reset button 68c is being pressed, the power to the pachinko machine 10 is turned ON, as shown in Figure 183(a). In this case, the power to the pachinko machine 10 is being turned ON while a "setting change operation" has been performed, and therefore the setting value update process (Figure 181) is initiated at timing t3, as shown in Figure 183(d).

In this comparative example, when the setting value update process (Figure 181) is initiated, the OFF confirmation flag 361 is not set to "1", so at timing t3, as shown in Figure 183(e), the value of the OFF confirmation flag 361 is "0". Thereafter, at timing t4, when the reset button 68c continues to be pressed during the power-on operation, it is determined that the reset button 68c is being pressed while the value of the OFF confirmation flag 361 is "0", and the setting value to be updated is incremented by 1, as shown in Figure 183(f). Also, at timing t4, the OFF confirmation flag 361 is set to "1", as shown in Figure 183(e).

In other words, in the above comparative example, if the reset button 68c is pressed when the power is turned on and continues to be pressed even after the setting value update process (Figure 181) has begun, the setting value to be updated will be incremented by 1 in response to this pressing operation. In this case, the setting value to be updated will be updated even though the amusement hall manager has no intention of updating it.

Next, we will explain this embodiment in which the OFF confirmation flag 361 is set to "1" when the setting value update process (Figure 181) is started.

At timing t5, as shown in FIG. 183(b), the setting key insertion section 68a is turned ON using the setting key, and the reset button 68c is pressed, as shown in FIG. 183(c). Then, at timing t6, while the setting key insertion section 68a is being turned ON and the reset button 68c is being pressed, the power to the pachinko machine 10 is turned ON, as shown in FIG. 183(a). In this case, the power to the pachinko machine 10 is being turned ON while a "setting change operation" has been performed, and therefore the setting value update process (FIG. 181) is initiated at timing t7, as shown in FIG. 183(d). When the setting value update process (FIG. 181) is initiated, step SB901 is executed to set the OFF confirmation flag 361 to "1." Therefore, at timing t7, the OFF confirmation flag 361 is set to "1," as shown in FIG. 183(e). The timing at which this OFF confirmation flag 361 is set to "1" occurs before the timing at which it is determined whether the reset button 68c has been pressed in the setting value update process (FIG. 181), and therefore the setting value to be updated will not be incremented by 1 even if the reset button 68c continues to be pressed during the power-on operation, as shown in FIG. 183(f). Thereafter, at timing t8, as shown in FIG. 183(c), the pressing of the reset button 68c is terminated, and the OFF confirmation flag 361 is cleared to "0" as shown in FIG. 183(e).

Then, as shown in Figure 183(c), the reset button 68c is pressed from timing t9 to timing t10, from timing t11 to timing t12, and from timing t13 to timing t14. In this case, the reset button 68c is pressed when the value of the OFF confirmation flag 361 is "0" at timing t9, timing t11, and timing t13, and therefore the setting value to be updated is incremented by 1 at each of these timings, as shown in Figure 183(f).

Then, at timing t15, the setting key insertion section 68a is turned OFF as shown in Figure 183(b), which ends the setting value update process (Figure 181) at timing t15 as shown in Figure 183(d).

As described above, when the OFF confirmation flag 361 is set to "0" and it is determined that the reset button 68c has been pressed, the setting value to be updated is incremented by 1. When the setting value update process (FIG. 181) is initiated, the OFF confirmation flag 361 is set to "1" in step SB901, which is executed prior to the process of determining whether the reset button 68c has been pressed. This makes it possible to prevent the setting value to be updated from being incremented by 1 due to the reset button 68c being pressed when the pachinko machine 10 is powered on.

The present embodiment described above provides the following excellent effects:

When the setting value update process (Fig. 181) is started, the setting value is changed from a predetermined starting setting value. This makes it possible to change the setting value from a fixed starting setting value in the setting value update process (Fig. 181), regardless of the setting value to be used before the setting value update process (Fig. 181) was started. This makes it easy for the operator to understand the work involved in changing the setting value.

The setting value corresponding to the start mentioned above is specifically "Setting 1," which has the lowest degree of advantage. Therefore, when the setting value update process (Figure 181) is started, the setting value is changed from "Setting 1," which has the lowest degree of advantage. This means that even if the amusement hall manager unintentionally ends the setting value update process (Figure 181) immediately after it has started, the setting value with the lowest degree of advantage will be used, preventing unintended disadvantages to the amusement hall even if play begins in such a situation.

The work area 221 for specific control is provided with a setting reference area 341 and a setting update area 342. Information corresponding to the setting values to be used is stored in the setting reference area 341, and information corresponding to setting values that are in the process of being changed while the setting value update process (Figure 181) is being executed is stored in the setting update area 342. This makes it possible to change the setting values to be updated in the setting value update process (Figure 181) while storing and retaining information about the setting values that were set before the setting value update process (Figure 181) was started in the setting reference area 341.

If the supply of operating power to the main CPU 63 is stopped while the setting value update process (Figure 181) is being executed, a restricted state will be entered in which processing to progress the game will not be started when the supply of operating power to the main CPU 63 is subsequently resumed. This makes it possible to prevent processing to progress the game from being started even though the setting value update process (Figure 181) has not been completed.

Even if the supply of operating power to the main CPU 63 is stopped while the setting value update process (Figure 181) is being executed, the above-mentioned restricted state will not occur if a "setting change operation" is performed when the supply of operating power to the main CPU 63 is subsequently resumed. This makes it possible to prevent the execution of processes for progressing the game from being restricted even when setting values are changed.

Even in the above restricted state, power outage monitoring and various counter update processes are executed. This makes it possible to ensure that necessary processes are executed even when game progress is restricted as described above. In particular, by executing power outage monitoring, it becomes possible to respond appropriately in the event of a power outage even when game progress is restricted.

The above-mentioned restricted state will resume when the supply of operating power is restarted, even if the supply of operating power is stopped. This makes it possible to ensure that the state in which the execution of processing to progress the game is restricted by stopping the supply of operating power to the main CPU 63 while the setting value update process (Figure 181) is being executed will not be released simply by stopping the supply of operating power.

In a configuration in which the setting value to be updated is incremented by 1 when it is determined that the reset button 68c has been pressed while the OFF confirmation flag 361 in the specific control work area 221 is set to "0," when the setting value update process (FIG. 181) is initiated, the OFF confirmation flag 361 is set to "1" in step SB901, which is executed prior to the process of determining whether the reset button 68c has been pressed. This makes it possible to prevent the setting value to be updated from being incremented by 1 due to the reset button 68c being pressed when the pachinko machine 10 is powered on.

In addition, if the supply of operating power to the main CPU 63 is stopped during the setting value update process (Figure 181), and the setting confirmation process (step SB810) is executed when the supply of operating power to the main CPU 63 is subsequently resumed, the setting update display flag may be cleared to "0" and the execution of the process to proceed with the game may not be restricted. Execution of the setting confirmation process (step SB810) notifies the current setting value to be used, allowing the amusement hall manager to understand the setting value to be used. In such a case, even if the execution of the process to proceed with the game is not restricted, the game will not proceed with setting values that the amusement hall manager did not intend.

Furthermore, if the supply of operating power to the main CPU 63 is stopped during the setting value update process (Fig. 181), the setting value update process (Fig. 181) may be forcibly executed when the supply of operating power is subsequently resumed, regardless of whether a "setting change operation" has been performed. This makes it possible to forcibly change the setting value.

Furthermore, if the supply of operating power to the main CPU 63 is stopped during the setting confirmation process (step SB810), a restricted state may be established in which the execution of processing for progressing the game is restricted when the supply of operating power is subsequently resumed. In this case, the restricted state may not be established if the setting confirmation process (step SB810) is executed when the supply of operating power is resumed. In addition to or instead of this configuration, the restricted state may not be established if the setting value update process (Figure 181) is executed when the supply of operating power is resumed.

Furthermore, if the supply of operating power to the main CPU 63 is stopped during the setting confirmation process (step SB810), the setting confirmation process (step SB810) may be forcibly executed when the supply of operating power is subsequently resumed, regardless of whether the "setting confirmation operation" has been performed. This makes it possible to forcibly check the setting values.

In addition, in the setting value update process (FIG. 181), if it is determined that the reset button 68c has not been pressed in the earlier processing run of two consecutive processing runs and that the reset button 68c has been pressed in the later processing run, the setting value of the selected object is changed. However, this is not limited to this, and the setting value of the selected object may be changed if it is determined that the reset button 68c has not been pressed in each of multiple consecutive past processing runs and that the reset button 68c has been pressed in that situation in one processing run or multiple consecutive processing runs. Even in this case, when the setting value update process (FIG. 181) is initiated, information regarding the confirmation history of pressing the reset button 68c in multiple consecutive past processing runs is rewritten to information corresponding to the reset button 68c having been pressed. This makes it possible to prevent the setting value of the selected object from being changed in the setting value update process (FIG. 181) by pressing the reset button 68c to start the setting value update process (FIG. 181).

<Fifty-fourth embodiment>
In this embodiment, the processing configuration of the main processing executed by the main CPU 63 is different from that of the 53rd embodiment. The configuration that differs from the 53rd embodiment will be described below. Note that the description of the same configuration as the 53rd embodiment will basically be omitted.

Figure 184 is a flowchart showing the main processing in this embodiment, which is executed by the main CPU 63. Note that steps SC101 to SC128 in the main processing are executed using a specific control program and specific control data in the main CPU 63.

Steps SC101 to SC106 are identical to steps SB801 to SB806 in the main processing (Figure 179) in the 53rd embodiment. If all of steps SC104 to SC106 return a positive determination, a determination is made as to whether the reset button 68c has been pressed (step SC107). If the reset button 68c has not been pressed (step SC107: NO), a determination is made as to whether the setting update display flag in the specific control work area 221 has been set to "1" (step SC108). If the reset button 68c has not been pressed and the setting update display flag has not been set to "1" (step SC107 and step SC108: NO), a determination is made as to whether the game stop flag in the specific control work area 221 has been set to "1" (step SC109). If the game stop flag has been set to "1," an abnormality command is sent in step SC127, and external output processing in the event of an abnormality is executed in step SC128.

If the game stop flag is not set to "1" (step SC109: NO), proceed to step SC110. Steps SC110 to SC112 execute the same processing as steps SB809 to SB811 of the main processing (Figure 179) in the 53rd embodiment described above.

If it is determined in step SC107 that the reset button 68c has been pressed, or if it is determined in step SC108 that the setting update display flag has been set to "1," it is determined in step SC113 whether the setting key insertion unit 68a has been turned ON using the setting key. If it is determined that the setting key insertion unit 68a has been turned ON (step SC113: YES), the OFF confirmation flag 361 in the specific control work area 221 is set to "1" (step SC114), and then the setting value update process is executed (step SC115). Note that steps SC116 to SC128 execute the same processes as steps SB114 to SB826 in the main process (FIG. 179) in the 53rd embodiment described above.

In other words, in this embodiment, if the supply of operating power to the main CPU 63 is stopped during the execution of the setting value update process (step SC115), and the supply of operating power to the main CPU 63 is resumed in a "no operation" situation or a "RAM clear operation" situation, the situation in which the processing for progressing the game is blocked continues, as in the 53rd embodiment. However, the setting value update process (step SC115) is executed not only when the supply of operating power to the main CPU 63 is resumed in a "setting change operation" situation, but also when the supply of operating power to the main CPU 63 is resumed in a "setting confirmation operation" situation. This makes it easier to execute the setting value update process (step SC115) when the supply of operating power to the main CPU 63 is resumed after the supply of operating power to the main CPU 63 was stopped during the execution of the setting value update process (step SC115).

In particular, in a configuration where a "setting change operation" requires the setting key insertion unit 68a to be turned ON using the setting key and the reset button 68c to be pressed, and a "setting confirmation operation" requires the setting key insertion unit 68a to be turned ON using the setting key, if the setting update display flag is set to "1," the setting value update process (step SC115) will be executed even if the reset button 68c is not pressed, because the setting key insertion unit 68a is turned ON. This makes it possible to quickly restore the power to the ON state after a "setting change operation" has been performed, by turning the power to the pachinko machine 10 ON to initiate the setting value update process (step SC115), even if the power is accidentally turned OFF during the process, while the setting key insertion unit 68a remains ON, even if the reset button 68c is not pressed.

In addition, in this embodiment, if it is determined in step SC112 that the setting key insertion section 68a has been operated ON, the OFF confirmation flag 361 in the specific control work area 221 is set to "1" in step SC114 before the setting value update process (step SC115) is started. This makes it possible to prevent the setting value to be updated from being incremented by 1 when the reset button 68c is pressed during the power ON operation, even if the OFF confirmation flag 361 is not set to "1" when the setting value update process (step SC115) is started. Incidentally, in the setting value update process (step SC115) of this embodiment, the process of step SB901 of the setting value update process (FIG. 181) in the 53rd embodiment is not executed, and steps SB902 to SB918 are executed.

In the setting value update process (step SC115), the setting value of the selection target is changed if it is determined that the reset button 68c has not been pressed in the earlier processing run of two consecutive processing runs and that the reset button 68c has been pressed in the later processing run. However, this is not limited to this. The setting value of the selection target may be changed if it is determined that the reset button 68c has not been pressed in each of multiple consecutive past processing runs and that the reset button 68c has been pressed in that situation in one processing run or multiple consecutive processing runs. Even in this case, when the setting value update process (step SC115) is initiated, information regarding the confirmation history of pressing the reset button 68c in multiple consecutive past processing runs is rewritten to information corresponding to the reset button 68c having been pressed. This makes it possible to prevent the setting value of the selection target from being changed in the setting value update process (FIG. 181) by pressing the reset button 68c to start the setting value update process (FIG. 181).

<Other Embodiments>
The present invention is not limited to the above-described embodiment, and various modifications and improvements are possible within the scope of the spirit of the present invention. For example, the following modifications may be made. The following alternative configurations may be applied individually or in combination to the configurations of the above-described embodiment.

(1) In the first to fourteenth embodiments described above, the number of times the open/close execution mode occurs per unit play is calculated as a parameter indicating the frequency of the open/close execution mode. However, in addition to or instead of this, the number of times the open/close execution mode occurs may be calculated by dividing the result by the total number of game balls ejected from the play area PA. Furthermore, in addition to or instead of this, the number of times the open/close execution mode occurs may be calculated by dividing the result by the total number of balls that enter the first actuation port 33 and the second actuation port 34. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(2) In the first to fourteenth embodiments described above, the number of times the high-frequency support mode occurred per unit play and the ratio of the number of times the high-frequency support mode occurred to the number of times the open/close execution mode occurred were calculated as parameters indicating the frequency of the high-frequency support mode. However, in addition to or instead of this, the number of times the high-frequency support mode occurred may be calculated by dividing the result by the total number of game balls ejected from the play area PA. Furthermore, in addition to or instead of this, the number of times the high-frequency support mode occurred may be calculated by dividing the result by the total number of balls that entered the first actuation port 33 and the number of balls that entered the second actuation port 34. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(3) The game results that trigger the opening/closing execution mode may include not only a jackpot result but also a small jackpot result. If a small jackpot result occurs, the opening/closing execution mode occurs, but the win/lose lottery mode and support mode do not change before and after the opening/closing execution mode. Alternatively, the opening/closing execution mode resulting in a small jackpot result may be configured to switch to a low-frequency winning mode. In this case, if a jackpot result occurs, history information corresponding to the occurrence of the jackpot result may be stored in the history memory 117, and if a small jackpot result occurs, history information corresponding to the occurrence of the small jackpot result may be stored in the history memory 117. In this configuration, a parameter indicating the frequency of jackpot results and a parameter indicating the frequency of small jackpot results may be calculated using the history information stored in the history memory 117. This configuration may also be applied to the fifteenth to fifty-fourth embodiments.

In addition, the probability of winning a small win result may be configured to change depending on the setting state of the pachinko machine 10, or it may not change. If the probability of winning a small win result is configured to change depending on the setting state of the pachinko machine 10, the higher the setting value, the higher the probability of winning a small win result, or the higher the setting value, the lower the probability of winning a small win result.

Furthermore, in a configuration in which a small jackpot result exists, the allocation ratio of the type of jackpot result in the event of a jackpot may be configured to differ between the reserved information acquired when a gaming ball enters the first actuation port 33 and the reserved information acquired when a gaming ball enters the second actuation port 34. Furthermore, when aiming for the ball to enter the first actuation port 33, a firing operation is performed so that the gaming ball flows down the area in the play area PA to the left of the variable display unit 36, and when aiming for the ball to enter the second actuation port 34, a firing operation is performed so that the gaming ball flows down the area in the play area PA to the right of the variable display unit 36. Furthermore, a small jackpot result may be generated based on the reserved information acquired when a gaming ball enters the first actuation port 33.

In this configuration, the following 51st parameter may be present as a result of managing the game history. The normal period is the sum of the execution period of the opening/closing execution mode triggered by a small win result based on a ball entering the first operating port 33 and the execution period of the low-frequency support mode rather than the opening/closing execution mode. The number of balls entering the outlet 24a during the normal period is the number of balls entering K51, the number of balls entering the general winning port 31 during the normal period is the number of balls entering K52, the number of balls entering the special winning device 32 during the normal period is the number of balls entering K53, the number of balls entering the first operating port 33 during the normal period is the number of balls entering K54, and the number of balls entering the second operating port 34 during the normal period is the number of balls entering K55.
Parameter 51: Total number of game balls paid out during the normal period (K52 x "number of prize balls for winning the general winning port 31" + K53 x "number of prize balls for winning the special winning device 32" + K54 x "number of prize balls for winning the first operating port 33" + K55 x "number of prize balls for winning the second operating port 34") / Proportion of total number of game balls discharged from the technique area PA during the normal period (K51 + K52 + K53 + K54 + K55). In a configuration in which the above parameter 51 is calculated, if the probability of winning a small jackpot varies depending on the settings of the pachinko machine 10, the normal value of parameter 51 will vary depending on the settings of the pachinko machine 10. Therefore, it is preferable that the history information used to calculate parameter 51 be erased when the settings of the pachinko machine 10 are changed. On the other hand, if the probability of winning a small jackpot does not change according to the setting state of the pachinko machine 10, the normal value of the 51st parameter does not change according to the setting state of the pachinko machine 10. Therefore, it is preferable that the history information used to calculate the 51st parameter is not erased even if the setting state of the pachinko machine 10 is changed.

(4) In the first to fourteenth embodiments described above, instead of storing history information corresponding to the occurrence of the open/close execution mode in the history memory 117 regardless of the type of jackpot result, history information corresponding to the type of jackpot result may be stored in the history memory 117. In this case, a parameter indicating the frequency of occurrence for each type of jackpot result may be calculated. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(5) In the first to fourteenth embodiments described above, various parameters (the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters) are periodically calculated. However, this is not limited to this. For example, various parameters may be calculated when the total number of game balls discharged from the game area PA reaches a calculation trigger number (e.g., 10,000 balls), when the supply of operating power to the pachinko machine 10 is stopped, or when the number of game plays reaches a calculation trigger number (e.g., 1,000 plays). In this case, the history memory 117 may be cleared to "0" when the various parameters are calculated. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(6) In the first to fourteenth embodiments, all of the first to eighth parameters, the eleventh to eighteenth parameters, the twenty-first to twenty-sixth parameters, the thirty-first parameter, and the forty-first to forty-second parameters are calculated each time a parameter calculation timing is reached. However, this is not limited to this. Only some of the parameters may be calculated at a single calculation timing, with the parameter group to be calculated changing sequentially each time a calculation timing is reached. For example, the first to eighth parameters may be calculated at one calculation timing, the eleventh to eighteenth parameters may be calculated at the next calculation timing, the twenty-first to twenty-sixth parameters may be calculated at the next calculation timing, and the thirty-first parameter and the forty-first to forty-second parameters may be calculated at the next calculation timing. Thereafter, the change of the parameters to be calculated in this order may be repeated each time a calculation timing is reached. This reduces the processing load required to calculate parameters at a single calculation timing. This configuration may also be applied to the fifteenth to fifty-fourth embodiments.

(7) In the first to fourteenth embodiments described above, the calculation of various parameters may be performed using the history information in the history memory 117, provided that a game is being played. For example, the calculation of various parameters may be performed provided that a game ball is being supplied to the game area PA. This prevents the calculation of various parameters from being repeated unnecessarily even when no game is being played. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(8) The first to fourteenth embodiments described above are not limited to a configuration in which a management IC 66 is provided separately from the main CPU 63, and the functions of the management IC 66 may be performed by the main CPU 63. In this case, the correspondence information is pre-stored in the main ROM 64. Also, a configuration in which a history memory 117, a calculation result memory 131, and a separate storage memory 171 are provided separately from the main RAM 65 may be used, and the functions of the history memory 117, the calculation result memory 131, and the separate storage memory 171 may be performed in the main RAM 65. In a configuration in which the main RAM 65 functions as the history memory 117, the calculation result memory 131, and the separate storage memory 171, when the clearing process (steps S105 and S117) of the main RAM 65 is executed, some or all of the areas corresponding to the history memory 117, the calculation result memory 131, and the separate storage memory 171 may be cleared to "0." Alternatively, the areas corresponding to the history memory 117, the calculation result memory 131, and the separate storage memory 171 may be excluded from the "0" clearing process and cleared to "0" when the corresponding clearing condition in each of the above embodiments is met. Furthermore, the manual operations for clearing the areas corresponding to the history memory 117, the calculation result memory 131, and the separate storage memory 171 may be different from those for other areas of the main RAM 65. Furthermore, the function of the management IC 66 may be performed by the audio and light-emitting control device 81.

(9) In the first to fourteenth embodiments described above, when a new setting is made to the setting state of the pachinko machine 10, the history information in the history memory 117 is stored and maintained without being erased, while the various parameters stored in the calculation result memory 131 may be erased. This makes it possible to prevent the various parameters calculated before a new setting is made from being notified after the new setting is made. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(10) In the third to fifth embodiments described above, even if a new setting is made to the setting status of the pachinko machine 10 (i.e., even if the setting value update process is executed by the main CPU 63), the process of clearing the history memory 117 may not be executed if the setting value has not changed before or after the setting. This makes it possible to prevent the history information in the history memory 117 from being erased even if the setting value has not been changed.

In this configuration, even if the clear process (step S117) is executed, all areas in the main RAM 65 for storing setting values are excluded from being cleared to "0." This allows the main CPU 63 to determine whether the setting value has changed before and after the setting value update process (step S118). In this case, if the main CPU 63 determines that the setting value has not changed, it may output a signal to the management CPU 112 to prevent the management CPU 112 from executing the setting update recognition process. Alternatively, if the main CPU 63 determines that the setting value has changed, it may output a signal to the management CPU 112 to prevent the management CPU 112 from executing the setting update recognition process.

Furthermore, when a signal indicating that a new setting has been made to the setting status of the pachinko machine 10 is received from the main CPU 63, the management CPU 112 may be configured to determine whether the setting value has been changed by referring to the history information stored in the history memory 117. In this case, if the management CPU 112 determines that the setting value has not been changed, it will not execute the process of clearing the history memory 117, and if the management CPU 112 determines that the setting value has been changed, it will execute the process of clearing the history memory 117.

(11) In the third to fifth embodiments described above, even if a new setting is made to the setting state of the pachinko machine 10 (i.e., even if the setting value update process is executed by the main CPU 63), if the setting value has not changed before and after the setting, the calculation process of various parameters triggered by the new setting state may not be executed. This makes it possible to prevent various parameters from being calculated in response to the new setting state even if the setting value has not changed.

In this configuration, even if the clear process (step S117) is executed, all areas in the main RAM 65 for storing setting values are excluded from being cleared to "0." This allows the main CPU 63 to determine whether the setting value has changed before and after the setting value update process (step S118). In this case, if the main CPU 63 determines that the setting value has not changed, it may output a signal to the management CPU 112 to prevent the management CPU 112 from executing the setting update recognition process. Alternatively, if the main CPU 63 determines that the setting value has changed, it may output a signal to the management CPU 112 to prevent the management CPU 112 from executing the setting update recognition process.

Furthermore, when a signal indicating that a new setting has been made to the setting state of the pachinko machine 10 is received from the main CPU 63, the management CPU 112 may be configured to determine whether the setting value has been changed by referring to the history information stored in the history memory 117. In this case, if the management CPU 112 determines that the setting value has not been changed, it will not perform calculations of various parameters triggered by the new setting of the current setting state, and if the management CPU 112 determines that the setting value has been changed, it will perform calculations of various parameters triggered by the new setting of the current setting state.

(12) In the third to fifth embodiments, when a new setting is made to the setting state of the pachinko machine 10, instead of calculating various parameters in the various calculation processes (step S1807) at that time, the various parameters stored in the calculation result memory 131 at that time may be stored in the target area among the first to fifth separate storage areas 172 to 176 of the separate storage memory 171, and the information stored in the calculation result memory 131 may be cleared to "0." In this case, since there is no need to calculate various parameters when a new setting is made to the setting state of the pachinko machine 10, it is possible to quickly complete the storage of various parameters in the separate storage memory 171.

(13) In the third to fifth embodiments, the contents of the various parameters stored in the first to fifth separate storage areas 172 to 176 of the separate storage memory 171 may be configured to be displayed on the first to third notification display devices 69a to 69c or other display devices when a predetermined display start operation is performed. The predetermined display start operation may be performed by operating a dedicated operation unit, or by performing a predetermined dedicated operation on an operation unit for performing other operations. This makes it possible to easily check the various parameters stored in the separate storage memory 171.

(14) While the configuration is such that all of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 are targets for storing history information (or ball entry history), this is not limited to this, and only some of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 may be targets for storing history information. For example, only the general winning opening 31, special electric winning device 32, and second operating opening 34 may be targets for storing history information, or only the general winning opening 31 may be targets for storing history information. Even in this case, it is possible to grasp the ball entry patterns of game balls over a specified period for the ball entry sections for which history information is stored.

(15) Signal paths 118a-118c are configured to transmit information corresponding to the game ball's entry results for the first entry port detection sensor 42a, the second entry port detection sensor 43a, and the third entry port detection sensor 44a, respectively. However, this is not limited to this. Information corresponding to the entry results for the same type of entry port may be transmitted as a single type of information, even in a configuration in which there are multiple entry ports of the same type and multiple entry port detection sensors corresponding to them. This makes it possible to reduce the number of types of information transmitted from the main CPU 63 to the management IC 66.

(16) In the first to fourteenth embodiments described above, the correspondence information indicating the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each of the buffers 122a to 122o is transmitted from the main CPU 63 to the management IC 66. However, this is not limited to this, and the correspondence information may be pre-stored in the management IC 66. In this case, there is no need to execute processing to cause the management IC 66 to recognize the correspondence information, which reduces the processing load on the main CPU 63.

(17) In the first to fourteenth embodiments described above, the transmission of correspondence information indicating the correspondence between the type of information transmitted from the main CPU 63 to the management IC 66 and each of the buffers 122a to 122o to the management IC 66 is performed when the supply of operating power to the main CPU 63 begins. However, this is not limited to this. For example, the main CPU 63 and the management IC 66 may be capable of two-way communication, and the correspondence information may be transmitted from the main CPU 63 to the management IC 66 upon receiving a signal from the management IC 66 requesting the transmission of the correspondence information. In this case, the correspondence memory 116 is provided as a non-volatile memory and configured to be used for both reading and writing. The correspondence information provided from the main CPU 63 to the management IC 66 after the pachinko machine 10 is shipped is stored and retained in the correspondence memory 116 even if the supply of operating power to the main CPU 63 is stopped. This reduces the frequency with which the correspondence information is transmitted.

(18) In the first to fourteenth embodiments described above, the correspondence information indicating the correspondence between the type of information sent from the main CPU 63 to the management IC 66 and each buffer 122a to 122o is transmitted from the main CPU 63 to the management IC 66 using signal paths 118a to 118g for transmitting the detection results of each ball entry detection sensor 42a to 48a. However, this is not limited to this, and a dedicated signal path may be provided for transmitting the correspondence information from the main CPU 63 to the management IC 66. This allows the management IC 66 to determine what type of information is being received from the main CPU 63 based on the type of buffer 122a to 122o that receives that information.

(19) In the first to fourteenth embodiments described above, information is transmitted from the main CPU 63 to the management IC 66, but information is not transmitted from the management IC 66 to the main CPU 63. However, this is not limited to this, and information may be transmitted from the management IC 66 to the main CPU 63. For example, various parameters calculated by the management CPU 112 based on history information may be transmitted to the main CPU 63. In this case, the main CPU 63 may be configured to directly control the notification means so that notifications corresponding to the contents of the various received parameters are issued. Alternatively, the main CPU 63 may be configured to transmit commands corresponding to the contents of the various received parameters to the audio and light-emitting control device 81, thereby enabling notifications corresponding to the contents of the various parameters to be issued using the pattern display device 41, display light-emitting unit 53, and speaker unit 54.

(20) In the first to fourteenth embodiments described above, when the supply of operating power to the main CPU 63 is initiated, the main CPU 63 or the management CPU 112 may calculate various parameters based on the history information stored in the history memory 117, and the contents of the calculated various parameters may be notified using the symbol display device 41, the display light-emitting unit 53, the speaker unit 54, etc. In this case, when the amusement hall opens for business, it may be possible to check whether the ball entry behavior in the game area PA on the previous business day was normal. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(21) In the first to fourteenth embodiments, if various parameters calculated based on the history information stored in the history memory 117 result in abnormal results, the pachinko machine 10 may be configured to prevent play from starting until a prohibition release operation is performed. Examples of configurations that prevent play from starting include prohibiting the launch of game balls, disabling each ball entry detection sensor 42a-49a, or not executing a win/loss determination process even if a win occurs in the first actuation port 33 or the second actuation port 34. The prohibition release operation may also be performed by restarting the power to the pachinko machine 10 while the reset button 68c is pressed, or by operating an operating means that becomes operable when the gaming machine main body 12 is opened relative to the outer frame 11. This makes it possible to prevent play from continuing even when the game ball entry pattern in the play area PA is abnormal. It also makes it possible to prevent play from continuing even when the frequency of the opening/closing execution mode is abnormal. This configuration may also be applied to the above 15th to 54th embodiments.

(22) In the first to fourteenth embodiments, while history information corresponding to the detection results of the ball entry detection sensors 42a to 48a is stored in the history memory 117, the calculation of various parameters using that history information may not be performed by either the main CPU 63 or the management CPU 112. In this case, the history information may be read by an external device electrically connected to the reading terminal 68d, and the operator performing the reading operation may calculate various parameters using the read history information, or the external device may calculate various parameters using the read history information. In this case, it is possible to reduce the processing load on the main CPU 63 and the management CPU 112. This configuration may also be applied to the fifteenth to fifty-fourth embodiments.

(23) In the first to fourteenth embodiments described above, the management IC 66 may be provided with a power supply separate from that of the main CPU 63, and the management IC 66 may be configured to be able to calculate various parameters using history information and output history information or various parameters even if the supply of operating power to the main CPU 63 is stopped. This makes it possible to read history information and various parameters using an external device even when the supply of operating power to the main CPU 63 is stopped.

(24) In the first to fourteenth embodiments described above, the read terminal 68d used to read the program from the main ROM 64 is configured to also be used as a terminal used to read history information or various parameters by an external device. However, this is not limited to this, and the terminal used to read history information or various parameters by an external device may be provided separately from the read terminal 68d used to read the program from the main ROM 64. In this case, the terminal used to read history information or various parameters may be provided in the MPU 62, or may be provided in a position on the main control board 61 separate from the MPU 62.

(25) In the first to fourteenth embodiments, the correspondence memory 116, history memory 117, and calculation result memory 131 are not limited to configurations in which they are provided as non-volatile storage means such as flash memory. For example, any of these memories 116, 117, and 131 may be provided as volatile storage means that require a power supply to store and retain information, and backup power may be supplied to that memory so that information can be stored and retained even if the supply of operating power to the main CPU 63 is stopped. In this case, a dedicated backup power device may be provided for that memory, or backup power may be supplied to that memory from the power supply and launch control device 78 that supplies backup power to the main RAM 65.

(26) In the first to fourteenth embodiments, the management IC 66 is not limited to a configuration in which it includes a management CPU 112 as a general-purpose CPU and performs storage of history information and calculation of various parameters based on the programs and data stored in the management ROM 113. A configuration in which a hardware circuit designed to perform these functions is formed in the management IC 66 may also be used. Specifically, for example, in the first embodiment, when the hardware circuit receives a signal from the main CPU 63 indicating that a gaming ball has been detected by any of the detection sensors 42a to 48a, it stores correspondence information corresponding to the buffer that received the signal from the correspondence memory 116 to the history memory 117, and also stores the information of the RTC 115 at that time in the history memory 117. Furthermore, in the sixth embodiment, when the hardware circuit receives a signal from the main CPU 63 indicating that a gaming ball has been detected by any of the detection sensors 42a to 48a, it increments the value of a counter corresponding to the buffer that received the signal by one. Furthermore, when a calculation trigger occurs, such as in the first embodiment, the hardware circuit calculates various parameters using the history information at that time. Furthermore, when a trigger occurs to output to the read terminal 68d, the hardware circuit outputs the various parameters that are the calculation results, as well as the history information.

(27) In the first to fourteenth embodiments described above, the main CPU 63 and the management IC 66 may be configured as separate chips, separate boards, or separate control devices.

(28) The number of game balls entering the outlet 24a is counted, while history information including RTC information may be stored for balls entering bonus-trigger entry sections, such as the general entry section 31, the special electric entry device 32, the first actuation section 33, and the second actuation section 34, which trigger the payout of prize balls and the win/loss determination process. This makes it possible to extract the history of game balls entering bonus-trigger entry sections, and to calculate the frequency of game balls entering each bonus-trigger entry section relative to the total number of game balls dispensed.

(29) The configuration may include events other than those described in the above embodiments as predetermined events that trigger the storage of history information. For example, the configuration may be such that at least one of the following events is stored as history information: the lower tray 56a becoming full, the timing at which the full state began, and the timing at which the full state was released; the configuration may be such that at least one of the following events is stored as history information: the tank 75 becoming ball-free, the timing at which the ball-free state began, and the timing at which the ball-free state was released; and the configuration may be such that at least one of the following events is stored as history information: the dispensing device 76 becoming abnormal, the timing at which the abnormal state of the dispensing device 76 began, and the timing at which the abnormal state of the dispensing device 76 was released. In this case, it is possible to grasp the frequency of occurrence of these events.

(30) In the first embodiment described above, the 16th buffer 122p of the input port 121 in the management I/F 111 was configured to correspond to an output instruction signal in advance during the design stage of the management IC 66. However, this is not limited to this configuration. The management IC 66 may recognize that the 16th buffer 122p corresponds to an output instruction signal when a type identification command is sent from the main CPU 63. Also, in the first embodiment described above, the 15th buffer 122o of the input port 121 in the management I/F 111 was configured to correspond to a setting value update signal in advance during the design stage of the management IC 66. However, this is not limited to this configuration. The management IC 66 may recognize that the 15th buffer 122o corresponds to a setting value update signal when a type identification command is sent from the main CPU 63. In this case, it is not necessary to previously set in the management IC 66 the correspondence between each buffer 122a to 122p and the type of signal input to each buffer 122a to 122p.

(31) In the first to fourteenth embodiments, the management IC 66 may be configured to send a normal operation signal to the main CPU 63 when it is operating normally. In this case, the main CPU 63 can monitor whether the management IC 66 is operating normally.

(32) The display device that displays the setting values being updated during the setting value update process is not limited to the first to fourth notification display devices 201 to 204, but may be the graphic display device 41 or a dedicated display device. Furthermore, the display device that displays the setting values during the setting confirmation process is not limited to the first to fourth notification display devices 201 to 204, but may be the graphic display device 41 or a dedicated display device.

(33) The operating unit operated to update the setting value in the setting value update process is not limited to the update button 68b, but may be the reset button 68c. Furthermore, when a setting key is inserted into the setting key insertion unit 68a and rotated, positions corresponding to "Setting 1" to "Setting 6" may be set as the rotation position, and the setting value corresponding to the rotation position of the setting key insertion unit 68a may be set. Furthermore, the setting key insertion unit 68a may be configured to be able to be rotated further than the ON position, and each time a rotation operation beyond the ON position is performed, the setting value being updated is updated to the next setting value in the sequence.

(34) In the first to tenth and fifteenth to twenty-first embodiments, the first to third notification display devices 69a to 69c are arranged horizontally, but they may also be arranged vertically, diagonally, or in two rows. Furthermore, in the eleventh to fourteenth and twenty-second to forty-fourth embodiments, the first to fourth notification display devices 201 to 204 are arranged horizontally, but they may also be arranged vertically, diagonally, or in two rows. Furthermore, in the fifteenth to twenty-first embodiments, the first to fourth notification display devices 201 to 204 may be used as display devices for displaying the results of game history management.

(35) In the first to fourteenth embodiments described above, the history information used to calculate parameters whose normal values change depending on the settings of the pachinko machine 10 (hereinafter referred to as "variable history information") and the history information used to calculate parameters whose normal values do not change depending on the settings of the pachinko machine 10 (hereinafter referred to as "non-variable history information") may be stored in different areas of the history memory 117. In this case, when the settings of the pachinko machine 10 are newly set or changed, the area in the history memory 117 where the variable history information is stored may be cleared to "0," while the area in the history memory 117 where the non-variable history information is stored may not be cleared to "0." This allows accurate calculation of parameters whose normal values change depending on the settings of the pachinko machine 10 even after the settings are changed, and improves the accuracy of calculation of parameters whose normal values do not change depending on the settings of the pachinko machine 10. This configuration may also be applied to the fifteenth to fifty-fourth embodiments described above.

(36) In the above fifteenth to twenty-first embodiments, the stack area 222 for specific control and the stack area 224 for non-specific control may not be pre-designated in the main RAM 65. Even in this case, areas corresponding to these stack areas 222, 224 will be designated in the main RAM 65 during the design stage of the pachinko machine 10. However, if the storage capacity of the area is exceeded and the storage process for information designated in that area is executed, unintended information will be written to an area not originally intended. Therefore, the main RAM 65 may be cleared to "0."

(37) In the above-mentioned 15th to 21st embodiments, when the clearing process of the main RAM 65 (steps S105, S117) is executed, the work area 221 for specific control and the stack area 222 for specific control are cleared to "0", but the work area 223 for non-specific control and the stack area 224 for non-specific control are not cleared to "0". However, instead, the clearing process of the main RAM 65 (steps S105, S117) may be configured to clear not only the work area 221 for specific control and the stack area 222 for specific control but also the work area 223 for non-specific control and the stack area 224 for non-specific control to "0". Furthermore, in the process of clearing the main RAM 65 (steps S105 and S117), not only the specific control work area 221 and specific control stack area 222 but also the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 are cleared to "0", but the calculation result storage area 234 may not be cleared to "0". In this case, it is possible to protect the information stored in the calculation result storage area 234.

(38) In the above fifteenth to twenty-fifth embodiments, the operation for clearing the specific control work area 221 and the specific control stack area 222 to "0" may be configured to be different from the operation for clearing the non-specific control work area 223 and the non-specific control stack area 224 to "0." For example, when the supply of operating power to the pachinko machine 10 is started while the reset button 68c is being operated, the specific control work area 221 and the specific control stack area 222 may be cleared to "0," and when the supply of operating power to the pachinko machine 10 is started while the update button 68b is being operated, the non-specific control work area 223 and the non-specific control stack area 224 may be cleared to "0." This makes it possible to selectively erase each piece of information. Furthermore, in this configuration, if the supply of operating power to the pachinko machine 10 is started while both the update button 68b and the reset button 68c are being operated, the specific control work area 221, the specific control stack area 222, the non-specific control work area 223, and the non-specific control stack area 224 may all be cleared to "0." This makes it possible to improve the ease of use when erasing information from each of the areas 221 to 224 collectively in a configuration that allows selective erasure as described above.

(39) In the above-described fifteenth to eighteenth and twentieth embodiments, similar to the nineteenth embodiment, the stack pointer information of the main CPU 63 may be saved to the work area 223 for non-specific control when processing corresponding to non-specific control starts, and the saved information may be restored to the stack pointer of the main CPU 63 when processing corresponding to specific control returns. This makes it possible to restore the state of the stack pointer of the main CPU 63 to the state before processing corresponding to non-specific control was started when processing corresponding to non-specific control ends, even if the configuration allows the stack pointer information of the main CPU 63 to change when processing corresponding to non-specific control starts.

(40) In the above fifteenth to twenty-fifth embodiments, the processing corresponding to non-specific control was configured to include processing for collecting game history information, processing for calculating various parameters using the collected history information, and processing for reporting the results of that calculation. However, it is also possible to configure the system so that only some of these processes are executed as processing corresponding to non-specific control, with the rest executed as processing corresponding to specific control. Furthermore, in addition to or instead of the processing for collecting game history information, processing for calculating various parameters using the collected history information, and processing for reporting the results of that calculation, it is also possible to configure the system so that processing other than these processes is executed as processing corresponding to non-specific control. For example, it is also possible to configure the system so that at least one of the processes of fraud monitoring and reporting the monitoring results is executed as processing corresponding to non-specific control.

(41) In the above-described fifteenth to twenty-fifth embodiments, when the main CPU 63 returns from a state in which processing corresponding to non-specific control is being executed to processing corresponding to specific control, none of the flag register, stack pointer, and various registers of the main CPU 63 are saved to the main RAM 65. However, instead, when the main CPU 63 returns from a state in which processing corresponding to non-specific control is being executed to processing corresponding to specific control, at least some of the information in the flag register, stack pointer, and various registers of the main CPU 63 may be saved to the main RAM 65, and the saved information may be restored to the corresponding storage area of the main CPU 63 when processing corresponding to non-specific control is resumed. This makes it possible to carry over and use information from the main CPU 63 used in processing corresponding to non-specific control.

(42) In the above-mentioned 15th to 25th embodiments, various parameters are calculated when the total number of game balls discharged from the play area reaches 6,000. However, the total number of game balls that triggers this calculation may be greater or less than 6,000. For example, various parameters may be calculated when the total number of game balls discharged from the play area reaches 60,000. In this case, the memory capacity required to store the game history information increases. However, by storing the game history information in a management RAM 241 external to the MPU 62, as in the above-mentioned 21st embodiment, it is possible to flexibly respond to this increase in memory capacity.

(43) In the above-mentioned 15th to 25th embodiments, the 61st to 68th parameters are calculated as the results of managing the gaming history. However, in addition to or instead of this, at least some of the 31st, 41st, and 42nd parameters in the above-mentioned first embodiment may also be calculated.

(44) In the above-mentioned 15th to 25th embodiments, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, not only the work area 221 for specific control and the stack area 222 for specific control but also the work area 223 for non-specific control and the stack area 224 for non-specific control may be configured to be cleared to "0." In this case, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234 are cleared to "0."

Furthermore, when a process to set a new setting for the pachinko machine 10 is executed or when the setting for the pachinko machine 10 is changed, the specific control work area 221 and specific control stack area 222 as well as the normal counter area 231, the open/close execution mode counter area 232, and the high frequency support mode counter area 233 may be cleared to "0", but the calculation result storage area 234 may not be cleared to "0". In this case, it is possible to protect the information stored in the calculation result storage area 234.

Furthermore, when a process to set a new setting for the pachinko machine 10 is executed or when the setting for the pachinko machine 10 is changed, the work area 221 for specific control and the stack area 222 for specific control may be cleared to "0", but the work area 223 for non-specific control and the stack area 224 for non-specific control may not be cleared to "0". In this case, it is possible to protect the information stored in the work area 223 for non-specific control and the stack area 224 for non-specific control.

Furthermore, if the above configuration (43) is provided, when a process for newly setting the setting state of the pachinko machine 10 is executed or when the setting state of the pachinko machine 10 is changed, the history information used to calculate the 31st, 41st, and 42nd parameters in the first embodiment above is erased, but the normal counter area 231, the open/close execution mode counter area 232, the high frequency support mode counter area 233, and the calculation result storage area 234 may not be cleared to "0."

(45) In the first to fifty-fourth embodiments described above, instead of using the total number of game balls discharged from the game area PA to calculate various parameters, the total number of game balls supplied to the game area PA may be used. In this case, for example, a detection sensor may be provided to detect game balls that have been launched from the game ball launching mechanism 27 and reached the game area PA, and the number of game balls supplied to the game area PA may be measured based on the detection results of the detection sensor. In this configuration, since there is no need to measure the number of game balls discharged from the outlet 24a, the outlet detection sensor 48a may not be provided.

(46) In the above fifteenth to fifty-fourth embodiments, at least a portion of the information in the various registers and stack pointers of the main CPU 63 may be saved to the stack area 222 for specific control or the stack area 224 for non-specific control by a load command. In this case, it is necessary to update the stack pointer information of the main CPU 63 when saving the information to the stack areas 222, 224. It is also possible to restore the information saved to the stack areas 222, 224 to the corresponding memory area of the main CPU 63 by a load command. In this case, too, it is necessary to update the stack pointer information of the main CPU 63 when restoring the information from the stack areas 222, 224.

(47) In each of the above embodiments, when the setting value update process is being executed, a corresponding notification may be issued by either the symbol display device 41, the display light-emitting unit 53, or the speaker unit 54. This allows the amusement hall manager to clearly understand that the setting value update process is being executed.

(48) In each of the above embodiments, the history of newly set values may be stored in the main RAM 65. Alternatively, the history of newly set values may be stored in RAM provided in the audio and light emitting control device 81. In this case, each time a set value update process is completed, a command including information on the set value set in the set value update process is sent from the main CPU 63 to the audio and light emitting control device 81, and each time the audio and light emitting control device 81 receives the command, information indicating that a new set value has been set and information indicating the set value at that time are cumulatively stored in the RAM of the audio and light emitting control device 81. In this configuration, when a specified operation is performed, the setting history of set values cumulatively stored in the RAM of the audio and light emitting control device 81 may be displayed on the pattern display device 41.

(49) In each of the above embodiments, when a new setting value is set in the setting value update process, the information stored in the payout control device 77 indicating the number of game balls to be paid out is not erased. However, instead, the information indicating the number of game balls to be paid out may be erased. Also, if the setting value update process is executed but the setting value is not changed, the information indicating the number of game balls to be paid out may not be erased, and if the setting value is changed, the information indicating the number of game balls to be paid out may be erased.

(50) In each of the above embodiments, if the setting value update process is executed but the setting value is not changed, the areas 221-224 of the main RAM 65 are not cleared to "0." However, if the setting value is changed, at least some of the areas 221-224 of the main RAM 65 may be cleared to "0." For example, if the setting value is changed, the areas other than the setting value counter in the specific control work area 221 may be cleared to "0."

(51) In the above-mentioned 22nd to 54th embodiments, the operation of the movable object related to the game profit may be continued even when the main CPU 63 is executing the process to confirm the setting value in the setting confirmation process (Figure 87). For example, in a configuration in which a V zone and a non-V zone are provided in the ball entry means that allows balls to enter in the open/close execution mode, and a distribution member that distributes game balls that enter the ball entry means to either the V zone or the non-V zone is provided, the operation of the distribution member may be continued even when the process to confirm the setting value is being executed in the setting confirmation process. In this case, it becomes possible to prevent an attempt to stop the operation of the distribution member by fraudulently creating a situation in which the process to confirm the setting value is being executed in the setting confirmation process. In addition to the above-mentioned distribution member, other possible movable objects that continue to operate even when the setting confirmation process is executing a process to confirm the setting value include a distribution member that distributes game balls between an advantageous opening into which a game ball that has entered the ball entry means will subsequently trigger a round of play, and an outlet opening from which a game ball that has entered the ball entry means will be discharged without entering an advantageous opening.

(52) In the above 22nd to 54th embodiments, at least one of the work area 223 for non-specific control and the stack area 224 for non-specific control may be configured not to be monitored for information abnormalities. In this case, even if it is determined that an information abnormality has occurred in the work area 221 for specific control and the stack area 222 for specific control, by configuring the work area 223 for non-specific control and the stack area 224 for non-specific control not to be cleared to "0," it is possible to prevent a situation from occurring in which the work area 223 for non-specific control and the stack area 224 for non-specific control are cleared to "0" due to the occurrence of an information abnormality.

(53) In the above 22nd to 54th embodiments, the monitoring of whether or not an information abnormality has occurred in the work area 221 for specific control, the stack area 222 for specific control, the work area 223 for non-specific control, and the stack area 224 for non-specific control may all be performed by processing corresponding to non-specific control. Furthermore, the processing for clearing each area 221 to 224 to "0" when an information abnormality has occurred may all be performed by processing corresponding to non-specific control.

(54) In each of the above embodiments, the main RAM 65 requires a power supply to store and retain information, and backup power is supplied to the main RAM 65 even when the power to the pachinko machine 10 is turned off. However, the main RAM 65 may also be configured as a non-volatile memory that does not require a power supply to store and retain information.

(55) In each of the above embodiments, the various clearing processes for the main RAM 65 may be configured to initialize the target area of the main RAM 65 by executing a process to clear the target area to "0" and a process to initialize the target area. Alternatively, the target area may be initialized by executing a process to initialize the target area without executing a process to clear the target area to "0."

(56) In each of the above embodiments, if the setting key insertion portion 68a is turned ON when the supply of operating power to the main CPU 63 begins, the setting value update process may be executed without any additional operation. Alternatively, instead of the setting key insertion portion 68a being turned ON/OFF by a setting key, a setting switch that is turned ON/OFF directly by hand may be provided. Alternatively, if the setting key insertion portion 68a is not provided, and the reset button 68c is pressed when the supply of operating power to the main CPU 63 begins, the setting value update process may be executed without any additional operation. In this case, a cover member may be provided that can be switched between a closed state that covers the reset button 68c and an open state that does not cover it, and a locking device may be provided that locks the cover member in the closed position.

(57) During the setting value update process, if the setting key insertion section 68a is held in the OFF position for a predetermined period of time, the selected setting value may be confirmed and the setting value update process may be terminated. Alternatively, if a reference termination period (e.g., 5 minutes) has elapsed since the setting value update process began, the selected setting value may be automatically confirmed and the setting value update process may be terminated. Alternatively, during the setting value update process, if the update button 68b or reset button 68c is pressed and held for a period of time equal to or longer than the reference termination period (e.g., 10 seconds), the selected setting value may be confirmed and the setting value update process may be terminated.

(58) In a configuration in which the setting key insertion unit 68a can be rotated beyond the ON position, and the setting value being updated is updated to the next setting value in the sequence each time the setting key insertion unit 68a is rotated beyond the ON position, a setting confirmation process that allows the setting value to be confirmed may be initiated when the supply of operating power to the main CPU 63 is started while the setting key insertion unit 68a is in the ON position, and the setting confirmation process may be terminated when the setting key insertion unit 68a is in the OFF position. Alternatively, a setting confirmation process that allows the setting value to be confirmed may be initiated when the supply of operating power to the main CPU 63 is started while the update button 68b or the reset button 68c is pressed, and the setting confirmation process may be terminated when the button is released. Alternatively, instead of the setting key insertion section 68a that is turned ON/OFF by a setting key, a setting switch that is turned ON/OFF directly by hand may be provided. When the setting switch is turned ON and the supply of operating power to the main CPU 63 begins, a setting confirmation process that allows the setting value to be confirmed may be initiated, and when the setting switch is turned OFF or turned ON after being turned OFF, the setting confirmation process may be terminated. Also, instead of the setting key insertion section 68a that is turned ON/OFF by a setting key, a setting switch that is turned ON/OFF directly by hand may be provided. When the setting switch is turned ON and the supply of operating power to the main CPU 63 begins, a setting confirmation process that allows the setting value to be confirmed may be initiated, and when the reset button 68c is pressed, the setting confirmation process may be terminated.

(59) In each of the above embodiments, when a setting confirmation process or a setting value update process is executed, an image corresponding to the procedure may be displayed on the pattern display device 41, and audio corresponding to the procedure may be output from the speaker unit 54 to support this. For example, in the setting value update process in the 33rd embodiment, a configuration may be adopted in which pressing the reset button 68c notifies the user that the setting value will be changed by one level, and turning the setting key insertion unit 68a OFF notifies the user that the setting value update process will be terminated. This makes it easier to update the setting values. Note that the display control of the pattern display device 41 and the sound output control of the speaker unit 54 are performed by the audio and light emission control device 81. Therefore, when a setting confirmation process or a setting value update process is initiated, a corresponding command must be transmitted from the main CPU 63, and when a setting confirmation process or a setting value update process is terminated, a corresponding command must be transmitted from the main CPU 63.

(60) In each of the above embodiments, the check display on the first to fourth alert display devices 201 to 204 may not be terminated when the initial check period has elapsed, but may continue until an operation to terminate the check display is performed. The operation to terminate the check display may be, for example, operation of the reset button 68c regardless of whether the setting confirmation process or the setting value update process is being executed, or operation of an operation unit other than the reset button 68c. In this case, the check display on the first to fourth alert display devices 201 to 204 continues until it is time to check the base value or setting value on the first to fourth alert display devices 201 to 204. This makes it possible to check the base value or setting value after confirming whether the first to fourth alert display devices 201 to 204 are normal. Furthermore, because the check display is terminated based on operation of the operation unit, it is possible to terminate the check display at a desired timing.

(61) In each of the above embodiments, the first to fourth notification display devices 201 to 204 may be configured to start a check display when a predetermined operation unit, such as the update button 68b or the reset button 68c, is operated, regardless of whether the supply of operating power has started. In this case, it is possible to start the check display at a desired timing when checking the base value or set value. In this configuration, the check display may be ended when a predetermined period (e.g., 5 seconds) has elapsed, or the check display may be ended when the predetermined operation unit operated to start the check display or a different operation unit is operated.

(62) In each of the above embodiments, if the supply of operating power to the main CPU 63 is initiated while a specific operation unit other than the reset button 68c, such as the update button 68b, is operated, the check display of the first to fourth notification display devices 201 to 204 may be initiated, but if the supply of operating power to the main CPU 63 is initiated without the specific operation unit being operated, the check display may not be initiated. In this case, in a configuration in which the check display is initiated when the supply of operating power is initiated, the amusement hall manager may be able to select whether or not to initiate the check display by operation.

(63) In each of the above embodiments, the base values may not be displayed on the first to fourth alert display devices 201-204 regardless of whether the gaming machine main body 12 is in the open state. Instead, the base values may be displayed on the first to fourth alert display devices 201-204 only when the gaming machine main body 12 is determined to be in the open state based on the detection results of the main body open sensor 96. In this case, when the gaming machine main body 12 is in the open state, the check displays on the first to fourth alert display devices 201-204 may first be initiated, and then the base values may be displayed on the first to fourth alert display devices 201-204. This makes it possible to check whether the first to fourth alert display devices 201-204 are normal before checking the base values. Furthermore, in this configuration, the check display may be terminated after a predetermined period (e.g., 5 seconds) has elapsed. Alternatively, the check display may be terminated when the predetermined operation unit operated to initiate the check display or a different operation unit is operated.

(64) In each of the above embodiments, if the main processing is started with the conditions for executing the setting confirmation processing satisfied, the check display of the first to fourth notification display devices 201 to 204 may not be started, but if the main processing is started with the conditions for executing the setting confirmation processing not satisfied, the check display may be started. In this case, it is possible to prevent the check display from being displayed if it has been determined that the setting value will be confirmed.

(65) In each of the above embodiments, the check display of the first to fourth notification display devices 201 to 204 may not be started if the main processing is started when the conditions for executing the setting value update processing are met, but may be started if the main processing is started when the conditions for executing the setting value update processing are not met. In this case, it is possible to prevent the check display from being displayed if it is confirmed that the setting value will be updated.

(66) In each of the above embodiments, if the main processing is started with either the conditions for executing the setting confirmation processing or the conditions for executing the setting value update processing satisfied, the check display of the first to fourth notification display devices 201 to 204 may not be started, but if the main processing is started with neither the conditions for executing the setting confirmation processing nor the conditions for executing the setting value update processing satisfied, the check display may be started. In this case, it is possible to prevent the check display from being displayed if it has been confirmed that the setting value will be confirmed or updated.

(67) In each of the above embodiments, the check display may be configured such that each of the display segments 321-324 on each of the first to fourth alarm display devices 201-204 flashes rather than remaining illuminated. Also, the check display may be configured such that each of the display segments 321-324 on each of the first to fourth alarm display devices 201-204 sequentially illuminates one by one or a portion of each segment, and each of the display segments 321-324 illuminates at least once within the initial check period.

(68) In each of the above embodiments, the process of displaying a check mark on the first to fourth notification display devices 201 to 204 may be configured to be executed as a process corresponding to a non-specific control, rather than as a process corresponding to a specific control.

(69) In each of the above embodiments, display control of the first to fourth alarm display devices 201-204 may not be performed by the main CPU 63, but may be performed by a dedicated control means, the audio and light control device 81, or the display control device 82. In this case, when a base value is displayed on the first to fourth alarm display devices 201-204, the base value to be notified is transmitted from the main CPU 63 to the control means that serves as the main controller. When a set value is displayed on the first to fourth alarm display devices 201-204, the set value to be notified is transmitted from the main CPU 63 to the control means that serves as the main controller. Furthermore, when the main CPU 63 executes processing at the start of operating power supply, information corresponding to the start of a check display is transmitted from the main CPU 63 to the control means that serves as the main controller so that a check display is initiated on the first to fourth alarm display devices 201-204 while the processing at the start of operating power supply is being executed.

(70) In each of the above embodiments, if the power outage flag is not set to "1" or the checksums do not match, causing the game stop flag to be set to "1" and game progress to be stopped, the first to fourth alarm display devices 201 to 204 may be configured so that each display segment 321 to 324 is illuminated, similar to the check display, or each display segment 321 to 324 may be configured to flash.

(71) In each of the above embodiments, the setting value update process may be configured to be executed not only when the supply of operating power to the main CPU 63 is started, but also when a setting change trigger occurs after the processing at the start of the supply of operating power has ended. This makes it possible to eliminate the need to turn the power of the pachinko machine 10 OFF and ON when starting the setting value update process.

(72) In each of the above embodiments, the relationship between the "setting change operation" and the "setting confirmation operation" may be reversed. In other words, a "setting confirmation operation" may be identified as being performed when the reset button 68c is pressed and the setting key insertion section 68a is turned ON, and a "setting change operation" may be identified as being performed when the reset button 68c is not pressed and the setting key insertion section 68a is turned ON. Furthermore, a configuration may be adopted in which there is no overlap between the "setting change operation" and the "setting confirmation operation."

(73) In each of the above embodiments, the setting value update process is started when the supply of operating power to the main CPU 63 is started while the reset button 68c is pressed, and instead of changing the setting value of the selected object each time the reset button 68c is pressed during the setting value update process, the operation unit operated to start the setting value update process and the operation unit operated to change the setting value of the selected object during the setting value update process may not be the same.

(74) Instead of a configuration in which the display control device 82 is controlled by the audio and light emitting control device 81 based on commands sent from the main control device 60, a configuration in which the display control device 82 controls the audio and light emitting control device 81 based on commands sent from the main control device 60 may be adopted. Also, instead of a configuration in which the audio and light emitting control device 81 and the display control device 82 are provided separately, both control devices may be provided as a single control device, or the functions of one of these control devices may be integrated into the main control device 60, or both functions of these control devices may be integrated into the main control device 60. Also, the configuration of the commands sent from the main control device 60 to the audio and light emitting control device 81 and the configuration of the commands sent from the audio and light emitting control device 81 to the display control device 82 may be arbitrary.

(75) The present invention can also be applied to other types of pachinko machines that differ from the above embodiments, such as pachinko machines in which an electric device opens a predetermined number of times when a gaming ball enters a specific area of a special device, pachinko machines in which a right is generated and a jackpot is awarded when a gaming ball enters a specific area of a special device, pachinko machines with other devices, arrange ball machines, mahjong ball machines, etc.

The present invention can also be applied to non-ball gaming machines, such as slot machines, which have multiple reels with multiple symbols circumferentially printed on them, and which start the reels by inserting a medal and operating the start lever, and which award players a special prize, such as a medal payout, if a specific symbol or combination of symbols appears on an active line visible through a display window after the reels stop when the stop switch is operated or a predetermined time has passed.

The present invention can also be applied to a gaming machine that combines a pachinko machine and a slot machine, in which the gaming machine main body is supported on an outer frame so that it can be opened and closed, is equipped with a storage section and a take-up device, and the reels begin to rotate when the start lever is operated after a predetermined number of gaming balls stored in the storage section have been taken in by the take-up device.

When applying the present invention to slot machines or gaming machines that combine pachinko and slot machines, for example, the results of the lottery process for winning roles executed when a game is started by operating the start lever may be stored as history information, and the history information may be used to calculate the actual winning probability for each role. Alternatively, when a transition to a special gaming state such as a bonus game occurs, the occurrence may be stored as history information, and the history information may be used to calculate the actual probability of transitioning to the special gaming state. Alternatively, the ratio of the number of games played in the special gaming state to the total number of games played may be calculated. Such history information and various parameters may be readable by an external device, or notifications corresponding to the calculation results of various parameters may be issued by the gaming machine itself. Furthermore, a configuration may be adopted in which there are multiple setting states, such as "Setting 1" to "Setting 6," and the winning probability in the lottery process for winning roles may vary depending on the setting state. In this case, the configurations described in the above embodiments may be applied to the handling of history information, the calculation of various parameters, and the handling of repeated changes when a setting state is newly set or when a setting value is changed.

(76) The characteristic configurations of the above first to fifty-fourth embodiments may be mutually applied in any combination. For example, the characteristic configurations of the first embodiment, the sixth embodiment, the tenth embodiment, the thirtieth embodiment, and the forty-fifth embodiment may be combined; the characteristic configurations of the second embodiment, the fourth embodiment, the eighth embodiment, the eleventh embodiment, the thirty-third embodiment, and the forty-third embodiment may be combined; the characteristic configurations of the first embodiment, the fifteenth embodiment, the twenty-first embodiment, the twenty-ninth embodiment, the thirty-fourth embodiment, and the forty-ninth embodiment may be combined; or the characteristic configurations of the second embodiment, the sixteenth embodiment, the twenty-second embodiment, the thirty-fifth embodiment, the thirty-ninth embodiment, and the fifty-third embodiment may be combined. Furthermore, the configuration of the above-mentioned alternative embodiments may be applied in any combination to a configuration in which the characteristic configurations of the above-mentioned first to fifty-fourth embodiments are applied in a predetermined combination.

<Inventions extracted from the above embodiments>
The following describes the features of the inventions extracted from the above-described embodiments, while indicating, as necessary, their effects, etc. Note that, for ease of understanding, the corresponding configurations in the above-described embodiments are indicated in parentheses, etc. as appropriate, but the invention is not limited to the specific configurations indicated in parentheses, etc.

<Features Group A>
Feature A1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when the game is played in the history storage means (the history memory 117);
an information erasing means for erasing at least a part of the history information stored in the history storage means, on the condition that the setting value to be used has been set by the setting means (a function for executing the process of step S1809 in the management CPU 112 in the third embodiment, a function for executing the process of step S2109 in the management CPU 112 in the fifth embodiment, a function for executing the processes of steps S2306 to S2308 in the management CPU 112 in the sixth embodiment, and a function for executing the process of step S2608 in the management CPU 112 in the eighth embodiment);
A gaming machine characterized by comprising:

According to Feature A1, the setting value to be used is set from multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be used. Furthermore, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the historical information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the historical information.

In this case, at least a portion of the history information stored in the history storage means is erased when at least one of the conditions is that the setting value to be used has been newly set. This makes it possible to adjust the contents of the history storage means so that the frequency of occurrence of a specified event can be appropriately managed in a situation after the setting value to be used has been newly set.

Feature A2. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) that acquires special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
and a bonus awarding means (a function of executing the processes of steps S409 to S412 in the main CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the award correspondence result that the special information corresponds to the award information in the award determination.
A gaming machine described in feature A1, characterized in that the probability of the award corresponding result being obtained in the award determination varies depending on the set value.

Feature A2 makes it possible to vary the probability of a bonus corresponding result in a so-called pachinko machine according to a set value. In this case, by incorporating the configuration of feature A1, it becomes possible to adjust the contents of the history storage means so that the frequency of occurrence of a specified event can be appropriately managed in a situation after the probability of a bonus corresponding result has been changed.

Feature A3. A gaming machine as described in Feature A1 or A2, wherein the information erasing means erases all of the history information stored in the history storage means, with at least one condition being that the setting value to be used has been set by the setting means.

According to Feature A3, when a setting value to be used is newly set, all history information stored in the history storage means is erased, making it possible to determine the frequency of occurrence of a specified event based on the timing when the setting value to be used is newly set.

Feature A4. A gaming machine as described in Feature A1 or A2, wherein the information erasing means erases a portion of the history information stored in the history storage means and leaves a portion of the history information stored in the history storage means, on the condition that at least one of the setting values to be used has been set by the setting means.

According to Feature A4, when a new setting value to be used is set, it is possible to erase history information that is not necessary for managing the frequency of occurrence of a specified event thereafter, and retain history information that is necessary for managing the frequency of occurrence of the specified event thereafter. This makes it possible to optimally manage the frequency of occurrence of a specified event after a new setting value to be used is set.

Feature A5: The history information stored in the history storage means includes first history information (history information indicating that an opening/closing execution mode has occurred) in which the occurrence probability of the predetermined event corresponding to the history information varies depending on the set value, and second history information (history information indicating that a game ball has been discharged from the game area PA) in which the occurrence probability does not vary depending on the set value,
The gaming machine described in feature A4 is characterized in that the information erasing means erases the first history information stored in the history memory means and leaves the second history information stored in the history memory means, with at least one condition being that the setting value to be used has been set by the setting means.

According to Feature A5, when a setting value to be used is newly set, first history information corresponding to a predetermined event whose occurrence probability varies depending on the setting value is erased, while second history information corresponding to a predetermined event whose occurrence probability does not vary depending on the setting value is not erased. As a result, if first history information from before the setting value to be used is newly set is carried over after the setting value is newly set, first history information that is undesirable for determining the occurrence frequency of the predetermined event corresponding to the first history information can be erased when the setting value is newly set. On the other hand, by not erasing second history information even when a setting value to be used is newly set, it is possible to ensure a large amount of second history information to be referenced when determining the occurrence frequency of the predetermined event corresponding to the second history information, thereby enabling the occurrence frequency of the predetermined event corresponding to the second history information to be accurately determined.

Feature A6. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) that acquires special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
and a bonus awarding means (a function of executing the processes of steps S409 to S412 in the main CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the award correspondence result that the special information corresponds to the award information in the award determination.
The probability of the grant corresponding result being obtained in the grant determination varies depending on the set value,
the first history information includes information corresponding to the granting of the benefit,
A gaming machine described in feature A5, characterized in that the second history information includes information corresponding to the ejection of gaming balls from the gaming area in a predetermined manner.

According to feature A6, the probability of awarding a bonus varies depending on the setting value, so by erasing the first history information when a new setting value is set to be used, it becomes possible to determine the frequency at which a bonus will be awarded under the circumstances of the newly set setting value. On the other hand, since the frequency at which game balls are dispensed from the game area does not vary depending on the setting value, by not erasing the second history information even when a new setting value is set to be used, it becomes possible to accurately determine the frequency at which game balls are dispensed from the game area in a predetermined manner.

Feature A7. A gaming machine described in any one of Features A1 to A6, wherein the information erasing means erases at least a portion of the history information when the setting means sets the setting value to be used and a predetermined amount or more of the history information is stored in the history storage means.

According to Feature A7, if the history storage means does not store a predetermined amount of predetermined history information, the history information is not erased even if a new setting value to be used is set. This makes it possible to prevent the history information from being repeatedly erased from the history storage means even if new setting values are repeatedly set in a situation where no game is being played.

Feature A8. A gaming machine according to any one of Features A1 to A7, characterized in that it is equipped with information derivation means (a function for executing the processing of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the processing of step S2107 in the management CPU 112 in the fifth embodiment) that derives aspect information corresponding to game results over a predetermined period of time using the history information stored in the history storage means, with at least one condition being that the setting value to be used has been set by the setting means.

According to Feature A8, in a configuration including Feature A1 above, in which at least a portion of the history information stored in the history storage means is erased when at least one condition is met, that is, when a new setting value to be used is set, the history information stored in the history storage means is used to derive behavior information corresponding to game results over a predetermined period of time. This makes it possible to ascertain the results of game history management, such as the frequency of occurrence of a predetermined event, in the situation before the setting value was changed, even if at least a portion of the history information is erased when the setting value is changed.

Feature A9. The gaming machine described in Feature A8, further comprising a mode information storage means (separate storage memory 171) for storing the mode information derived by the information derivation means.

According to Feature A9, when a new setting value to be used is made, and behavior information corresponding to the game results over a predetermined period is derived using history information stored in the history storage means, that behavior information is stored in the behavior information storage means. This makes it possible to grasp the game history management results in the situation before the setting value was changed at any time thereafter, even if the setting value is changed.

Feature A10. The gaming machine described in Feature A9, wherein the mode information storage means is capable of storing multiple pieces of mode information.

According to Feature A10, since the mode information storage means can store multiple pieces of mode information, it is possible to grasp the results of managing game history over multiple periods based on the timing at which new setting values were set. Furthermore, even if new setting values are repeatedly set in situations where no game is being played, it is possible to increase the likelihood that mode information derived using history information from situations where game play is actually being played will remain in the mode information storage means.

Feature A11. The aspect information storage means is capable of storing a predetermined number of pieces of aspect information,
This gaming machine is a gaming machine described in feature A9 or A10, characterized in that it is equipped with a means for executing special processing when the setting of the setting value to be used by the setting means occurs more than the specified number of times under specified conditions (in the third embodiment, a function for executing monitoring processing of repeated changes in the management CPU 112, and in the fourth embodiment, a function for executing monitoring processing of repeated changes in the main CPU 63).

According to Feature A11, if new setting values are repeatedly set in a situation where no game is being played, special processing is executed to prevent the behavior information derived using historical information on situations where game play is actually being played from remaining in the behavior information storage means. This makes it possible to deal with such behavior.

Feature A12. The gaming machine described in any one of Features A8 to A11, wherein the information deriving means derives the behavior information when a predetermined amount or more of the history information is stored in the history storage means.

According to feature A12, behavior information is derived when a predetermined amount or more of predetermined history information is stored in the history storage means, making it possible to prevent behavior information from being derived unnecessarily.

Feature A13. A gaming machine according to any one of Features A1 to A12, wherein the information erasing means does not erase the history information until a specific amount of the predetermined history information is stored in the history storage means after the setting means sets the setting value to be used, and erases the history information stored in the history storage means before the setting value was set when a specific amount of the predetermined history information is stored in the history storage means after the setting means sets the setting value to be used.

According to Feature A13, even if a new setting value is set to be used, the history information stored before the new setting is not erased until a specific amount of predetermined history information is newly stored in the history storage means. This makes it possible to identify the results of game history management for a specified period of time even if a new setting value is set.

Feature A14: The history storage means includes a first history storage means (first history memory 191) and a second history storage means (second history memory 192),
The history storage execution means
a means for storing the history information corresponding to the predetermined event in both the first history storage means and the second history storage means when the predetermined event occurs within a predetermined period from when the setting value to be used is set by the setting means to when a cancellation condition is met (a function for executing the process of step S2604 in the management-side CPU 112);
a means for storing the corresponding history information in one of the first history storage means and the second history storage means, whichever is set as the storage target, when the predetermined event occurs during a period other than the predetermined period (a function for executing the process of step S2603 in the management-side CPU 112);
Equipped with
A gaming machine described in any one of features A1 to A13, characterized in that when the release condition is met, the information erasure means erases the history information stored in the first history storage means or the second history storage means, whichever was previously set as the storage target.

According to Feature A14, even if a new setting value is set to be used, the history information stored before the new setting is not erased until a specific amount of history information is newly stored in the history storage means. This makes it possible to identify the results of game history management for a specified period of time even if a new setting value is set. Furthermore, this effect can be achieved simply by appropriately switching the history storage means that stores history information between the first history storage means and the second history storage means.

Feature A15. A gaming machine as described in Feature A14, characterized in that it is equipped with information derivation means (a function for executing the processing of step S2703 in the management CPU 112) that derives behavior information corresponding to game results over a predetermined period of time using the history information stored in either the first history storage means or the second history storage means, whichever is set as the storage target.

Feature A15 makes it possible to appropriately derive behavior information using history information, even in situations where a new setting of the set value causes history information to be stored in both the first history storage means and the second history storage means.

In addition, with respect to the configuration of features A1 to A15, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group B>
Feature B1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when the game is played in the history storage means (the history memory 117);
Equipped with
A gaming machine characterized in that the specified history information stored in the history storage means before the setting value to be used is set by the setting means is stored and retained in the history storage means even after the setting value to be used is set by the setting means.

According to Feature B1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be used. Furthermore, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the historical information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the historical information.

In this case, even if a new setting value to be used is set, the history information stored in the history storage means is not erased but retained. This makes it possible to continue storing previous history information in the history storage means even when a new setting value to be used is set, and makes it possible to identify the results of game history management using history information accumulated in the history storage means over a long period of time.

Feature B2. A gaming machine according to Feature B1, characterized in that the history storage execution means includes setting time storage execution means (a function for executing the processing of step S1307 in the management CPU 112 in the first embodiment, and a function for executing the processing of step S2408 in the management CPU 112 in the seventh embodiment) that stores the corresponding history information in the history storage means when the setting value to be used is set by the setting means.

According to Feature B2, in a configuration in which history information is not erased but is stored and maintained even when a new setting value is set, history information corresponding to the new setting value is stored in the history storage means. This makes it possible to distinguish between history information before and after the new setting value is set.

Feature B3. The gaming machine described in Feature B2, wherein the setting storage execution means, when the setting value to be used is set by the setting means, stores information corresponding to the set setting value as the history information in the history storage means.

Feature B3 makes it possible to identify previously set values by referencing history information.

Feature B4. A gaming machine described in any one of Features B1 to B3, wherein the history storage means includes multiple corresponding history storage means (history memories 181-186 for settings 1-6) corresponding to the multiple types of setting values that can be set by the setting means.

According to feature B4, a response history storage means is provided corresponding to each setting value, making it possible to store history information separately for each setting value.

Feature B5. A gaming machine as described in Feature B4, characterized in that it is equipped with a means (a function for executing the processing of step S2406 in the management CPU 112) for, when the setting value to be used is set by the setting means, designating the correspondence history storage means corresponding to the set setting value as the storage target for the subsequent history information.

According to feature B5, when a new setting value to be used is set, the corresponding history storage means corresponding to that setting value is used to store subsequent history information, making it possible to store history information separately for each setting value.

Feature B6. A gaming machine as described in Feature B5, characterized in that it is equipped with information deriving means (a function for executing display output processing in the management CPU 112) that derives behavior information corresponding to game results over a predetermined period of time using the history information stored in the corresponding history storage means that is the storage target.

Feature B6 makes it possible to derive mode information corresponding to the currently set setting value in a configuration in which history information is stored separately for each setting value.

Feature B7. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) that acquires special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
and a bonus awarding means (a function of executing the processes of steps S409 to S412 in the main CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the award correspondence result that the special information corresponds to the award information in the award determination.
A gaming machine according to any one of features B1 to B6, characterized in that the probability of the award corresponding result being obtained in the award determination varies depending on the set value.

Feature B7 makes it possible to vary the probability of a winning result in a so-called pachinko machine according to a set value.

In addition, with respect to the configuration of features B1 to B7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group C>
Feature C1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when the game is played in the history storage means (the history memory 117);
a post-setting handling means (a function for executing the processes of step S2506 and steps S2605 to S2609 in the management CPU 112) that does not erase the history information after the setting means sets the setting value to be used and until a specific amount of the predetermined history information is stored in the history storage means;
A gaming machine characterized by comprising:

According to feature C1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be used. Furthermore, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the historical information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the historical information.

In this case, even if a new setting value is set, the history information stored before the new setting is not erased until a specific amount of predetermined history information is newly stored in the history storage means. This makes it possible to identify the results of game history management for a specified period of time even if a new setting value is set.

Feature C2. The gaming machine described in Feature C1, wherein the post-setting response means erases the history information stored in the history storage means before the setting value to be used was set if the history information stored in the history storage means exceeds the specified amount after the setting means sets the setting value to be used.

According to feature C2, when a specific amount of history information that enables the management results of the gaming history for a specific period of time after a new setting of the setting value has been made is stored in the history storage means, the history information that was stored in the history storage means before the new setting of the setting value was made is erased. This makes it possible to prevent unnecessary history information from continuing to be stored in the history storage means.

Feature C3: The history storage means includes a first history storage means (first history memory 191) and a second history storage means (second history memory 192),
The history storage execution means
a means for storing the corresponding history information in one of the first history storage means and the second history storage means, which is set as the storage target when the predetermined event occurs (a function for executing the process of step S2603 in the management-side CPU 112);
means for storing the history information corresponding to the predetermined event in both the first history storage means and the second history storage means in response to the occurrence of the predetermined event from the time when the setting value to be used is set by the setting means until the predetermined amount of history information is stored in the one of the first history storage means and the second history storage means that is not set as the storage target (a function for executing the process of step S2604 in the management-side CPU 112);
Equipped with
The post-setting response means includes:
a means for switching the storage target between the first history storage means and the second history storage means when the predetermined amount of history information is stored in the one of the first history storage means and the second history storage means that is not set as the storage target after the setting value to be used is set by the setting means; and
means for erasing the history information of one of the first history storage means and the second history storage means that has been set as the storage target, when the predetermined amount of history information is stored in the other of the first history storage means and the second history storage means that has not been set as the storage target after the setting value to be used has been set by the setting means; and a function for executing the process of step S2608 in the management-side CPU 112.
A gaming machine according to feature C1 or C2, characterized in that it is equipped with:

According to feature C3, even if a new setting value is set to be used, the history information stored before the new setting is not erased until a specific amount of history information is newly stored in the history storage means. This makes it possible to identify the results of game history management for a specified period of time even if a new setting value is set. Furthermore, this effect can be achieved simply by appropriately switching the history storage means that stores history information between the first history storage means and the second history storage means.

Feature C4. A gaming machine as described in Feature C3, characterized in that it is equipped with information derivation means (a function for executing the processing of step S2703 in the management CPU 112) that derives behavior information corresponding to game results over a predetermined period of time using the history information stored in either the first history storage means or the second history storage means, whichever is set as the storage target.

Feature C4 makes it possible to appropriately derive behavior information using history information, even in situations where a new setting of the set value causes history information to be stored in both the first history storage means and the second history storage means.

Feature C5. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) that acquires special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
and a bonus awarding means (a function of executing the processes of steps S409 to S412 in the main CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the award correspondence result that the special information corresponds to the award information in the award determination.
A gaming machine according to any one of features C1 to C4, characterized in that the probability of the award corresponding result being obtained in the award determination varies depending on the set value.

Feature C5 makes it possible to vary the probability of a winning result in a so-called pachinko machine according to a set value.

In addition, with respect to the configuration of features C1 to C5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group D>
Feature D1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a special execution means for executing special processing under at least one condition that the setting of the setting value to be used by the setting means is executed under a special situation (a function for executing a process for monitoring repeated changes in the management CPU 112 in the third embodiment, a function for executing a process for monitoring repeated changes in the main CPU 63 in the fourth embodiment, and a function for making a negative determination in step S2106 in the management CPU 112 in the fifth embodiment);
A gaming machine characterized by comprising:

According to feature D1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, special processing is executed under at least one condition that the new setting value to be used is set under special circumstances. This makes it possible to deal with cases in which a new setting value is set under unfavorable circumstances.

Feature D2. The gaming machine described in Feature D1, wherein the special execution means executes the special processing under at least one condition that the setting of the setting value to be used by the setting means has been executed a specific number of times or more in the special situation.

According to feature D2, even if a new setting value to be used is set in a special situation, special processing will not be executed if the number of times it has been set is less than a specific number. This makes it possible to prevent special processing from being executed even if a legitimate worker sets a new setting value in a special situation less than a specific number of times.

Feature D3. A gaming machine as described in Feature D1 or D2, wherein the special execution means executes the special processing under at least one condition that the setting means has set the setting value to be used, in a situation where no play has been performed since the setting means set the setting value to be used, or a situation where no play has been performed equal to or greater than a predetermined standard since the setting means set the setting value to be used.

Feature D3 executes special processing when a new setting value to be used is set when no game is being played or when no game is being played substantially, making it possible to deal with such an action if it occurs.

Feature D4. A gaming machine described in any one of Features D1 to D3, wherein the special execution means executes a notification process as the special process.

According to feature D4, the notification process is executed when at least one condition is met: a new setting of the setting value to be used is performed under special circumstances. This makes it possible to prompt the user to take action when a new setting value is performed under unfavorable circumstances.

Feature D5. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when a game is played in the history storage means (history memory 117);
information deriving means (a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment) for deriving aspect information corresponding to the results of games during a predetermined period using the history information stored in the history storage means, with the setting of the setting value to be used by the setting means being at least one of the conditions;
A gaming machine according to any one of features D1 to D4, characterized in that it is equipped with:

According to feature D5, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information.

In this case, when a new setting value is set, the historical information stored in the history storage means is used to derive behavior information corresponding to game results over a specified period. This makes it possible to understand the results of game history management, such as the frequency of occurrence of specified events in the situation before the setting value was changed.

Feature D6. The gaming machine described in Feature D5, wherein the special execution means, as the special processing, does not cause the information derivation means to derive the mode information, on at least one condition that the setting means has set the setting value to be used in the special situation.

According to feature D6, even if a new setting value to be used is set, if the setting is set in an undesirable situation, behavior information is not derived. This makes it possible to prevent behavior information from being derived unnecessarily.

Feature D7. A gaming machine as described in Feature D5 or D6, characterized in that it is equipped with a mode information storage means (separate storage memory 171) that stores the mode information derived by the information derivation means.

According to feature D7, when a new setting value to be used is made, and behavior information corresponding to the game results over a predetermined period is derived using history information stored in the history storage means, that behavior information is stored in the behavior information storage means. This makes it possible to grasp the game history management results in the situation before the setting value was changed at any time thereafter, even if the setting value is changed.

Feature D8. The gaming machine described in Feature D7, wherein the mode information storage means is capable of storing multiple pieces of mode information.

Feature D8 allows the mode information storage means to store multiple pieces of mode information, making it possible to grasp the results of game history management over multiple periods based on the timing at which new setting values were set. Furthermore, even if new setting values are repeatedly set when no game is being played, it is possible to increase the likelihood that mode information derived using history information from situations in which game play is actually being played will remain in the mode information storage means.

Feature D9. The aspect information storage means is capable of storing a predetermined number of pieces of aspect information,
A gaming machine described in feature D7 or D8, characterized in that the special execution means executes the special processing when the setting of the setting value to be used by the setting means occurs more than the specified number of times in the special situation.

Feature D9 executes special processing when new settings are repeatedly made in situations where no game is being played, so that the behavior information derived using historical information about situations where game play is actually being played does not remain in the behavior information storage means. This makes it possible to deal with such behavior.

Feature D10. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) that acquires special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
and a bonus awarding means (a function of executing the processes of steps S409 to S412 in the main CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the award correspondence result that the special information corresponds to the award information in the award determination.
A gaming machine described in any one of features D1 to D9, characterized in that the probability of the award corresponding result being obtained in the award determination varies depending on the set value.

Feature D10 makes it possible to vary the probability of a winning result in a so-called pachinko machine according to a set value.

In addition, with respect to the configuration of features D1 to D10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group E>
Feature E1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a history storage execution means (a function of executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when the game is played in the history storage means (the history memory 117);
information deriving means (a function for executing the process of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the process of step S2107 in the management CPU 112 in the fifth embodiment) for deriving aspect information corresponding to the results of games during a predetermined period using the history information stored in the history storage means, with the setting of the setting value to be used by the setting means being at least one of the conditions;
A gaming machine characterized by comprising:

According to feature E1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be used. Furthermore, when a predetermined event occurs, corresponding historical information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the historical information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the historical information.

In this case, when a new setting value is set, the historical information stored in the history storage means is used to derive behavior information corresponding to game results over a specified period. This makes it possible to understand the results of game history management, such as the frequency of occurrence of specified events in the situation before the setting value was changed.

Feature E2. A gaming machine as described in Feature E1, characterized in that it is equipped with a mode information storage means (separate storage memory 171) that stores the mode information derived by the information derivation means.

According to feature E2, when a new setting value to be used is made and historical information stored in the history storage means is used to derive behavior information corresponding to game results over a predetermined period, that behavior information is stored in the behavior information storage means. This makes it possible to grasp, at any time thereafter, the management results of the game history in the situation before the setting value was changed, even if the setting value is changed.

Feature E3. The gaming machine described in Feature E2, wherein the mode information storage means is capable of storing multiple pieces of mode information.

Feature E3 allows the mode information storage means to store multiple pieces of mode information, making it possible to grasp the results of game history management over multiple periods based on the timing at which new setting values were set. Furthermore, even if new setting values are repeatedly set in situations where no game is being played, it is possible to increase the likelihood that mode information derived using history information from situations where game play is actually being played will remain in the mode information storage means.

Feature E4: The aspect information storage means is capable of storing a predetermined number of pieces of aspect information;
This gaming machine is a gaming machine described in feature E2 or E3, characterized in that it is equipped with a means for executing special processing when the setting of the setting value to be used by the setting means occurs more than the specified number of times under specified conditions (in the third embodiment, a function for executing monitoring processing of repeated changes in the management CPU 112, and in the fourth embodiment, a function for executing monitoring processing of repeated changes in the main CPU 63).

According to feature E4, if new setting values are repeatedly set in a situation where no game is being played, special processing is executed to prevent the behavior information derived using historical information on situations where game play is actually being played from remaining in the behavior information storage means. This makes it possible to deal with such behavior.

Feature E5. A gaming machine described in any one of Features E1 to E4, wherein the information deriving means derives the behavior information when a predetermined amount or more of the history information is stored in the history storage means.

Feature E5 derives behavior information when a predetermined amount of history information or more is stored in the history storage means, thereby preventing unnecessary derivation of behavior information.

Feature E6. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) that acquires special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
and a bonus awarding means (a function of executing the processes of steps S409 to S412 in the main CPU 63) for awarding a bonus (opening/closing execution mode) to a player based on the award correspondence result that the special information corresponds to the award information in the award determination.
A gaming machine described in any one of features E1 to E5, characterized in that the probability of the award corresponding result being obtained in the award determination varies depending on the set value.

Feature E6 makes it possible to vary the probability of a winning result in a so-called pachinko machine according to a set value.

In addition, with respect to the configuration of features E1 to E6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned feature group A, feature group B, feature group C, feature group D, and feature group E can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be managed appropriately, and there is still room for improvement in this regard.

<Feature Group F>
Feature F1. Ball entry means (first actuation port 33, second actuation port 34) through which game balls flowing down the game area can enter;
An information acquisition means (a function of executing the processing of step S401 in the main CPU 63) for acquiring special information based on the game ball entering the ball entry means;
An assignment determination means (a function of executing the processing of steps S503 and S504 in the main CPU 63) that determines whether the special information corresponds to the assignment information;
A bonus granting means (a function for executing the processes of steps S409 to S412 in the main CPU 63) grants a bonus (opening/closing execution mode) to the player based on the result of the bonus determination that the special information corresponds to the bonus information;
A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
Equipped with
The award determination means has a high probability mode and a low probability mode as modes of the award determination so that the probability of the award corresponding result being achieved is relatively high or low,
A gaming machine characterized in that the probability of achieving the award corresponding result varies at least in the low probability mode depending on the set value.

Feature F1 makes it possible to vary the probability of a prize-winning result in at least the low-probability mode of a so-called pachinko machine according to a setting value. This makes it possible to create situations in which the probability of a prize-winning result in the low-probability mode is favorable or unfavorable, even with a single gaming machine. This makes it possible to increase the enjoyment of the game.

Feature F2. A gaming machine as described in Feature F1, wherein the probability of obtaining the corresponding award result in the high probability mode does not vary according to the set value.

According to feature F2, the probability of an award corresponding result in low probability mode varies according to the set value, while the probability of an award corresponding result in high probability mode does not vary according to the set value, thereby making it possible to limit the influence of the set value to the situation in low probability mode.

Feature F3. There are multiple types of the above benefits,
A gaming machine according to feature F1 or F2, characterized in that the selection mode of the benefit does not change according to the set value.

Feature F3 allows the probability of a corresponding award result in low probability mode to vary according to a set value, while the bonus selection method does not vary according to the set value, thereby limiting the influence of the set value to the situation in low probability mode.

In addition, with respect to the configuration of features F1 to F3, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned feature group F can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, with gaming machines such as those exemplified above, it is necessary to increase the enjoyment of the game, and there is still room for improvement in this regard.

<Feature Group G>
Feature G1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when a game is played in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results for a predetermined period using the history information stored in the history storage means (a function for executing the processing of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the processing of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the processing of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing display processing in the management side CPU 112) that controls the display of the information display means (the first to third notification display devices 69a to 69c in the first to tenth embodiments, and the first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is performed;
a second information display control means for controlling the display of the information display means so that a display corresponding to information different from the mode information is performed (a function for executing the processing of steps S202 and S208 in the main CPU 63 in the first to tenth embodiments; a function for executing the processing of steps S3101, S3103, and S3109 in the main CPU 63 in the eleventh embodiment; a function for executing the processing of steps S3201, S3202, S3204, and S3210 in the main CPU 63 in the twelfth embodiment; and a function for executing the processing for abnormality display in the main CPU 63 in the thirteenth embodiment);
A gaming machine characterized by comprising:

According to feature G1, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, using the history information stored in the history storage means, behavior information corresponding to the results of play over a predetermined period is derived. A display corresponding to the behavior information is then performed on the information display means. This makes it possible to grasp the results of management of the gaming history, such as the frequency of occurrence of a predetermined event. Furthermore, the information display means not only displays corresponding to the behavior information, but also displays corresponding to other information. This allows for effective use of the information display means.

Feature G2. A gaming machine as described in Feature G1, characterized in that the period during which the information display means displays the mode information is distinct from the period during which the information display means displays the other information.

Feature G2 makes it possible to determine whether the display on the information display means is displaying either mode information or other information by grasping the display status on the information display means.

Feature G3. The gaming machine described in Feature G1 or G2, wherein the second information display control means controls the display of the information display means so that a display corresponding to the different information is displayed in a different manner than the display manner in which the display corresponding to the manner information is displayed.

Feature G3 makes it possible to determine whether the display mode of the information display means is displaying either mode information or other information.

Feature G4. A gaming machine according to any one of Features G1 to G3, characterized in that the information display means comprises multiple individual information display means (first to third alert display devices 69a to 69c in the first to tenth embodiments, and first to fourth alert display devices 201 to 204 in the eleventh to fourteenth embodiments) each capable of displaying multiple types of information.

Feature G4 enables the display of a wide variety of behavioral information by using multiple individual information display means to display information corresponding to the behavioral information. Furthermore, the existence of multiple individual information display means makes it possible to significantly differ the display mode between when a display corresponding to behavioral information is displayed and when a display corresponding to other information is displayed.

Feature G5. A gaming machine as described in Feature G4, wherein the second information display control means, when causing a display corresponding to the separate information to be performed, causes certain individual information display means among the plurality of individual information display means that are not in a hidden state when a display corresponding to the mode information is performed (first alert display device 69a and second alert display device 69b in the first to tenth embodiments; first alert display device 201, second alert display device 202, and third alert display device 203 in the eleventh and twelfth embodiments; first alert display device 201 and second alert display device 202 in the thirteenth embodiment) to be in a hidden state.

According to feature G5, a specific individual information display means that is not in a hidden state when a display corresponding to mode information is made is made in a hidden state when a display corresponding to other information is made. This makes it possible to clearly identify whether a display corresponding to mode information or a display corresponding to other information is being made simply by determining the type of individual information display means that is in a hidden state.

Feature G6: When the second information display control means causes a display corresponding to the separate information to be performed, a specific individual information display means (the third alert display device 69c in the first to tenth embodiments, the fourth alert display device 204 in the eleventh and twelfth embodiments, and the third alert display device 203 and the fourth alert display device 204 in the thirteenth embodiment) that is to be in a display state when the mode information is displayed among the plurality of individual information display means is in a display state;
A gaming machine described in feature G5, characterized in that the display content of the specific individual information display means when a display corresponding to the other information is made can be displayed on the specific individual information display means when a display corresponding to the mode information is made.

Feature G6 allows the display content that can be displayed when a display corresponding to mode information is made on a specific individual information display means to also be displayed when a display corresponding to other information is made, thereby eliminating restrictions on the display content when a display corresponding to mode information is made. Furthermore, even if a specific individual information display means is configured to display the same content, a specific individual information display means that has the configuration of feature G5 and does not become hidden when a display corresponding to mode information is made becomes hidden when a display corresponding to other information is made, making it possible to identify which display is being made on multiple individual information display means.

Feature G7. A gaming machine described in Feature G5 or G6, wherein the first information display control means, when causing a display corresponding to the mode information to be performed, causes each of the multiple individual information display means to be in a display state.

According to feature G7, when a display corresponding to mode information is made, each of the multiple individual information display means is in a display state, making it possible to clearly distinguish this from a display corresponding to other information in which a specific individual information display means is in a non-display state.

Feature G8. A gaming machine described in any one of Features G5 to G7, wherein the first information display control means sequentially changes the display of the status information on the information display means, and the predetermined individual information display means is not maintained in a non-display state even when the display of the status information is changed.

According to feature G8, when a display corresponding to the mode information is being displayed, the specified individual information display means is not maintained in a non-display state. This makes it possible to identify whether a display corresponding to the mode information or a display corresponding to other information is being displayed on the multiple individual information display means, regardless of the timing at which the multiple individual information display means are checked.

Feature G9. A gaming machine described in any one of Features G5 to G8, characterized in that the second information display control means causes one specific individual information display means (the third alert display device 69c in the first to tenth embodiments, and the fourth alert display device 204 in the eleventh and twelfth embodiments) among the plurality of individual information display means to display information corresponding to the different information, and causes the remaining individual information display means to be in a non-display state.

According to feature G9, when a display corresponding to other information is made, only one individual information display means is in a display state, making it easier to determine whether a display corresponding to other information is being made.

Feature G10. The plurality of individual information display means are arranged in a predetermined direction,
A gaming machine described in feature G9, characterized in that the specific individual information display means is located at the end of the specified direction among the multiple individual information display means arranged in the specified direction.

According to feature G10, the individual information display means on which the display corresponding to the separate information is performed is located at the end in a predetermined direction, making it easier to determine whether or not a display corresponding to the separate information is being performed.

Feature G11. The first information display control means causes a display corresponding to the type of the aspect information to be displayed on an individual information display means to be a type display target that is a part of the plurality of individual information display means (the first alert display device 69a in the first to tenth embodiments, and the first alert display device 201 and the second alert display device 202 in the eleventh to fourteenth embodiments), and causes a display corresponding to the content of the aspect information to be displayed on an individual information display means to be a result display target that is a part of the plurality of individual information display means (the second alert display device 69b and the third alert display device 69c in the first to tenth embodiments, and the third alert display device 203 and the fourth alert display device 204 in the eleventh to fourteenth embodiments),
A gaming machine according to any one of features G5 to G10, wherein the predetermined individual information display means corresponds to the individual information display means of the type display target.

According to feature G11, when a display corresponding to mode information is made, the individual information display means of the type display target makes a display corresponding to the type of mode information to be displayed, and the individual information display means of the result display target makes a display corresponding to the content of the mode information to be displayed. This makes it easier to understand the mode information to be displayed. In this case, when a display corresponding to other information is made, the individual information display means of the type display target is in a hidden state, so the hidden state of type display corresponds to other information, making it easier to understand that other information is being displayed.

Feature G12: The information display means has a plurality of unit light-emitting elements (display segments 201a to 201g, 202a to 202g), and is configured to be able to perform a predetermined display by combining unit light-emitting elements that are in an emitting state among the plurality of unit light-emitting elements,
The second information display control means causes a display corresponding to the other information to be made by turning on a unit light-emitting element among the plurality of unit light-emitting elements that can be turned on when a display corresponding to the status information is made to a light-emitting state, and causes a combination of unit light-emitting elements that will be turned on when a display corresponding to the other information is made to be a combination that does not exist when a display corresponding to the status information is made.

According to feature G12, by making unit light-emitting elements that can be made luminous when a display corresponding to mode information is made luminous, a display corresponding to other information is made, which makes it possible to diversify the displays corresponding to mode information while minimizing restrictions on the content of the displays corresponding to mode information. On the other hand, the combination of unit light-emitting elements that are made luminous when a display corresponding to other information is made is a combination that does not exist when a display corresponding to mode information is made. As a result, by knowing the combination of unit light-emitting elements that are made luminous, it becomes possible to know whether a display corresponding to mode information or a display corresponding to other information is being made.

Feature G13: There are a plurality of display modes of the display corresponding to the mode information in the information display means,
A gaming machine as described in feature G12, characterized in that among the plurality of unit light-emitting units, there are no unit light-emitting units that do not emit light even when all displays corresponding to the mode information of the plurality of modes are made.

According to feature G13, when a display corresponding to the status information is made, any combination of unit light-emitting elements is made to emit light, which makes it possible to diversify the display corresponding to the status information while minimizing restrictions on the content of the display corresponding to the status information.

Feature G14: The vehicle is provided with a plurality of individual information display means, including the specific individual information display means (the third alert display device 69c in the first to tenth embodiments, the fourth alert display device 204 in the eleventh and twelfth embodiments, and the third alert display device 203 and the fourth alert display device 204 in the thirteenth embodiment),
A gaming machine described in feature G12 or G13, characterized in that when the second information display control means causes a display corresponding to the different information to be displayed, a predetermined individual information display means (first alert display device 69a and second alert display device 69b in the first to tenth embodiments, first alert display device 201, second alert display device 202 and third alert display device 203 in the 11th and 12th embodiments, first alert display device 201 and second alert display device 202 in the 13th embodiment) among the plurality of individual information display means that is not displayed in a hidden state when a display corresponding to the mode information is displayed.

According to feature G14, a specific individual information display means that is not in a hidden state when a display corresponding to mode information is made is made in a hidden state when a display corresponding to other information is made. This makes it possible to clearly identify whether a display corresponding to mode information or a display corresponding to other information is being made simply by determining the type of individual information display means that is in a hidden state.

Feature G15. Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level,
A gaming machine described in any one of features G1 to G14, characterized in that the second information display control means displays corresponding to the other information in a situation where the setting value can be changed.

Feature G15 allows the information display means that displays information corresponding to the mode information to also serve as a display means for notifying users that the setting value can be changed.

Feature G16. The gaming machine described in Feature G15, wherein the second information display control means displays information corresponding to the currently selected setting value as the display corresponding to the other information.

Feature G16 makes it possible to use the information display means that displays corresponding to the mode information as a display means for displaying setting values that are being changed.

Feature G17. A gaming machine described in any one of Features G1 to G16, wherein the second information display control means causes a display corresponding to an abnormal state of the gaming machine to be displayed as the display corresponding to the separate information.

Feature G17 makes it possible to use the information display means that displays corresponding to status information as a display means for displaying information corresponding to abnormal states of the gaming machine.

Feature G18. The gaming machine described in Feature G17, wherein the second information display control means, when causing a display corresponding to the abnormal condition to be displayed when the abnormal condition is not occurring, causes a display corresponding to the absence of the abnormal condition to be displayed.

Feature G18 makes it possible to clearly identify whether an abnormal condition has occurred by checking the information display means.

In addition, with respect to the configuration of features G1 to G18, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature H group>
Feature H1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when a game is played in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results for a predetermined period using the history information stored in the history storage means (a function for executing the processing of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the processing of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the processing of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing display processing in the management side CPU 112) that controls the display of the information display means (the first to third notification display devices 69a to 69c in the first to tenth embodiments, and the first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is performed;
a second information display control means for controlling the display of the information display means so that a display corresponding to information different from the mode information is performed (a function for executing the processing of steps S202 and S208 in the main CPU 63 in the first to tenth embodiments; a function for executing the processing of steps S3101, S3103, and S3109 in the main CPU 63 in the eleventh embodiment; a function for executing the processing of steps S3201, S3202, S3204, and S3210 in the main CPU 63 in the twelfth embodiment; and a function for executing the processing for abnormality display in the main CPU 63 in the thirteenth embodiment);
Equipped with
the information display means has a plurality of unit light-emitting elements (display segments 201a to 201g, 202a to 202g), and is configured to be able to perform a predetermined display by combining unit light-emitting elements that are in a light-emitting state among the plurality of unit light-emitting elements,
The second information display control means causes a display corresponding to the other information to be made by turning on a unit light-emitting element among the plurality of unit light-emitting elements that can be turned on when a display corresponding to the status information is made to a lighting state, and causes a combination of unit light-emitting elements that will be turned on when a display corresponding to the other information is made to be a combination that does not exist when a display corresponding to the status information is made.

According to feature H1, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, unauthorized access to or unauthorized modification of the history information can be prevented. Furthermore, behavior information corresponding to the results of play over a predetermined period is derived using the history information stored in the history storage means. A display corresponding to the behavior information is then performed on the information display means. This makes it possible to grasp the results of management of the gaming history, such as the frequency of occurrence of a predetermined event. Furthermore, the information display means not only displays corresponding to the behavior information, but also displays corresponding to other information. This allows for effective use of the information display means.

In addition, by making the unit light-emitting elements that can be made to emit light when a display corresponding to mode information is made emit light, a display corresponding to other information is made, which makes it possible to diversify the displays corresponding to mode information while minimizing restrictions on the content of the displays corresponding to mode information. On the other hand, the combination of unit light-emitting elements that emit light when a display corresponding to other information is made is a combination that does not exist when a display corresponding to mode information is made. In this way, by knowing the combination of unit light-emitting elements that emit light, it becomes possible to know whether a display corresponding to mode information or a display corresponding to other information is being made.

Feature H2: There are a plurality of display modes of the display corresponding to the mode information in the information display means,
A gaming machine as described in feature H1, characterized in that among the plurality of unit light-emitting units, there are no unit light-emitting units that do not emit light even when all displays corresponding to the mode information of the plurality of modes are made.

According to feature H2, when a display corresponding to the mode information is made, any combination of unit light-emitting elements is made luminous, which makes it possible to diversify the display corresponding to the mode information while minimizing restrictions on the content of the display corresponding to the mode information.

Feature H3: The vehicle is provided with a plurality of individual information display means, including the specific individual information display means (the third alert display device 69c in the first to tenth embodiments, the fourth alert display device 204 in the eleventh and twelfth embodiments, and the third alert display device 203 and the fourth alert display device 204 in the thirteenth embodiment),
A gaming machine described in feature H1 or H2, characterized in that when the second information display control means causes a display corresponding to the different information to be made, a predetermined individual information display means (the first alert display device 69a and the second alert display device 69b in the first to tenth embodiments, the first alert display device 201, the second alert display device 202, and the third alert display device 203 in the 11th and 12th embodiments, and the first alert display device 201 and the second alert display device 202 in the 13th embodiment) among the plurality of individual information display means that is not made invisible when a display corresponding to the mode information is made is made invisible.

According to feature H3, a specific individual information display means that is not in a hidden state when a display corresponding to mode information is made is made in a hidden state when a display corresponding to other information is made. This makes it possible to clearly identify whether a display corresponding to mode information or a display corresponding to other information is being made simply by determining the type of individual information display means that is in a hidden state.

Feature H4. The gaming machine described in Feature H3, wherein the first information display control means, when causing a display corresponding to the mode information to be performed, causes each of the multiple individual information display means to be in a display state.

According to feature H4, when a display corresponding to mode information is made, each of the multiple individual information display means is in a display state, making it possible to clearly distinguish this from a case where a display corresponding to other information is made, in which a specific individual information display means is in a non-display state.

Feature H5. A gaming machine as described in Feature H3 or H4, wherein the first information display control means sequentially changes the display of the status information on the information display means, and the predetermined individual information display means is not maintained in a non-display state even when the display of the status information is changed.

According to feature H5, when a display corresponding to the mode information is being displayed, the specified individual information display means is not maintained in a non-display state. This makes it possible to identify whether a display corresponding to the mode information or a display corresponding to other information is being displayed on the multiple individual information display means, regardless of the timing at which the multiple individual information display means are checked.

Feature H6: Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level,
A gaming machine described in any one of features H1 to H5, characterized in that the second information display control means displays corresponding to the other information in a situation where the setting value can be changed.

Feature H6 makes it possible to use the information display means that displays information corresponding to the mode information as a display means for notifying users that the setting value can be changed.

Feature H7. The gaming machine described in Feature H6, wherein the second information display control means displays information corresponding to the currently selected setting value as the display corresponding to the other information.

Feature H7 makes it possible to use the information display means that displays the mode information as a display means for displaying setting values that are being changed.

In addition, with respect to the configuration of features H1 to H7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group I>
Feature I1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when a game is played in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results for a predetermined period using the history information stored in the history storage means (a function for executing the processing of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the processing of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the processing of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing display processing in the management side CPU 112) that controls the display of the information display means (the first to fourth notification display devices 201 to 204) so that a display corresponding to the aspect information derived by the information derivation means is performed;
A second information display control means (a function of executing an abnormality display process in the main CPU 63) that controls the display of the information display means so that a display corresponding to an abnormal state of the gaming machine is displayed;
A gaming machine characterized by comprising:

According to feature I1, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and maintain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, unauthorized access to or unauthorized modification of the history information can be prevented. Furthermore, using the history information stored in the history storage means, behavior information corresponding to the results of gaming over a predetermined period is derived. A display corresponding to the behavior information is then performed on the information display means. This makes it possible to grasp the results of gaming history management, such as the frequency of occurrence of a predetermined event. Furthermore, the information display means not only displays corresponding to the behavior information, but also displays corresponding to abnormal conditions of the gaming machine. This allows for effective use of the information display means.

Feature I2. The gaming machine described in Feature I1, wherein the second information display control means, when causing a display corresponding to the abnormal condition to be displayed when the abnormal condition is not occurring, causes a display corresponding to the absence of the abnormal condition to be displayed.

Feature I2 makes it possible to clearly identify whether an abnormal condition has occurred by checking the information display means.

Feature I3. A gaming machine as described in Feature I1 or I2, wherein the period during which the information display means displays a message corresponding to the status information is distinct from the period during which the information display means displays a message corresponding to the abnormal state.

According to feature I3, by understanding the status of the display being performed on the information display means, it is possible to identify whether the display being performed on the information display means is a display corresponding to status information or a display corresponding to an abnormal state.

Feature I4. The gaming machine described in Feature G1 or G2, wherein the second information display control means controls the display of the information display means so that a display corresponding to the abnormal state is displayed in a different manner than when a display corresponding to the status information is displayed.

According to feature I4, by understanding the display mode of the information display means, it is possible to identify whether the display on the information display means is displaying a display corresponding to mode information or a display corresponding to an abnormal state.

Feature I5. A gaming machine according to any one of Features I1 to I4, characterized in that the information display means comprises multiple individual information display means (first to fourth notification display devices 201 to 204), each capable of displaying multiple types of information.

According to Feature I5, by using multiple individual information display means to display information corresponding to status information, it is possible to display a wide variety of status information. Furthermore, the existence of multiple individual information display means makes it possible to significantly differ the display mode when a display corresponding to status information is made from a display corresponding to an abnormal state.

Feature I6. A gaming machine as described in Feature I5, wherein the second information display control means, when causing a display corresponding to the abnormal state, causes certain individual information display means (first alert display device 201 and second alert display device 202) among the plurality of individual information display means that are not in a non-display state when a display corresponding to the status information is made to be in a non-display state.

According to Feature I6, a specific individual information display means that is not in a hidden state when a display corresponding to status information is being displayed is in a hidden state when a display corresponding to an abnormal state is being displayed. This makes it possible to clearly identify whether a display corresponding to status information or a display corresponding to an abnormal state is being displayed, simply by determining the type of individual information display means that is in a hidden state.

Feature I7. When the second information display control means causes a display corresponding to the abnormal state to be performed, it causes specific individual information display means (the third alarm display device 203 and the fourth alarm display device 204) among the plurality of individual information display means to be in a display state when the mode information is displayed,
A gaming machine described in feature I6, characterized in that the display content of the specific individual information display means when a display corresponding to the abnormal state is made can be displayed on the specific individual information display means when a display corresponding to the status information is made.

According to Feature I7, the display content that can be displayed when a display corresponding to status information is made on a specific individual information display means can also be displayed when a display corresponding to an abnormal state is made, thereby making it possible to avoid restricting the display content when a display corresponding to status information is made. Furthermore, even if a specific individual information display means is configured to be able to display the same content, a specific individual information display means that has the configuration of Feature I7 and does not go into a hidden state when a display corresponding to status information is made goes into a hidden state when a display corresponding to an abnormal state is made, making it possible to identify which display is being made on multiple individual information display means.

Feature I8. A gaming machine as described in Feature I6 or I7, wherein the first information display control means, when causing a display corresponding to the mode information to be performed, causes each of the multiple individual information display means to be in a display state.

According to feature I8, when a display corresponding to status information is made, each of the multiple individual information display means is in a display state, making it possible to clearly distinguish this from a display corresponding to an abnormal state in which a specific individual information display means is in a non-display state.

Feature I9. A gaming machine described in any one of Features I6 to I8, wherein the first information display control means sequentially changes the display of the status information on the information display means, and the predetermined individual information display means is not maintained in a non-display state even when the display of the status information is changed.

According to Feature I9, when a display corresponding to status information is being displayed, the specified individual information display means is not maintained in a non-display state. This makes it possible to identify whether a display corresponding to status information or a display corresponding to an abnormal state is being displayed on the multiple individual information display means, regardless of the timing at which the multiple individual information display means are checked.

In addition, with respect to the configuration of features I1 to I9, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature J group>
Feature J1. A history storage execution means (a function for executing a history setting process in the management CPU 112) for storing game history information corresponding to a predetermined event that occurs when a game is played in the history storage means (history memory 117);
information derivation means for deriving aspect information corresponding to game results for a predetermined period using the history information stored in the history storage means (a function for executing the processing of steps S1402 to S1412 in the management CPU 112 in the first embodiment, a function for executing the processing of step S1807 in the management CPU 112 in the third embodiment, and a function for executing the processing of step S2107 in the management CPU 112 in the fifth embodiment);
a first information display control means (a function of executing display processing in the management side CPU 112) that controls the display of the information display means (the first to third notification display devices 69a to 69c in the first to tenth embodiments, and the first to fourth notification display devices 201 to 204 in the eleventh to fourteenth embodiments) so that a display corresponding to the aspect information derived by the information derivation means is performed;
Equipped with
The first information display control means sequentially changes the display corresponding to the status information on the information display means, and is characterized in that the information display means is not maintained in a non-display state even when the display corresponding to the status information is changed.

According to feature J1, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, using the history information stored in the history storage means, behavior information corresponding to the results of play over a predetermined period is derived. A display corresponding to the behavior information is then displayed on the information display means. This makes it possible to grasp the results of management of the gaming history, such as the frequency of occurrence of a predetermined event. Furthermore, when a display corresponding to the behavior information is displayed, the information display means is not maintained in a non-display state. This makes it possible to identify the display corresponding to the behavior information regardless of when the information display means is checked.

Feature J2. A gaming machine as described in Feature J1, characterized in that the information display means includes multiple individual information display means (first to third alert display devices 69a to 69c in the first to tenth embodiments, and first to fourth alert display devices 201 to 204 in the eleventh to fourteenth embodiments) each capable of displaying multiple types of information.

Feature J2 enables the display of a wide variety of behavioral information by using multiple individual information display means to display information corresponding to the behavioral information.

Feature J3. A gaming machine as described in Feature J2, wherein the first information display control means, when causing a display corresponding to the mode information to be performed, causes each of the plurality of individual information display means to be in a display state.

According to feature J3, when a display corresponding to the status information is made, each of the multiple individual information display means is in a display state, and is maintained in a display state even when the display corresponding to the status information is changed. This makes it easier to understand the status information.

Feature J4. A gaming machine as described in Feature J2 or J3, wherein the first information display control means causes a display corresponding to the type of the status information to be displayed on an individual information display means that is a part of the plurality of individual information display means and is a type display target (first alert display device 69a in the first to tenth embodiments, first alert display device 201 and second alert display device 202 in the eleventh to fourteenth embodiments), and causes a display corresponding to the content of the status information to be displayed on an individual information display means that is a part of the plurality of individual information display means and is a result display target (second alert display device 69b and third alert display device 69c in the first to tenth embodiments, third alert display device 203 and fourth alert display device 204 in the eleventh to fourteenth embodiments).

According to feature J4, when a display corresponding to the aspect information is made, the individual information display means for the type display target makes a display corresponding to the type of aspect information to be displayed, and the individual information display means for the result display target makes a display corresponding to the content of the aspect information to be displayed. This makes it easier to understand the aspect information to be displayed.

In addition, with respect to the configuration of features J1 to J4, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature K group>
Feature K1: When a predetermined event occurs as a result of a game being played, history storage execution means (a function of executing history setting processing in the management CPU 112) is provided, which stores the corresponding game history information in the history storage means (history memory 117),
The gaming machine is characterized in that the history storage execution means is equipped with a means (a function of making a negative judgment in step S3501 in the main CPU 63) that prevents the history information from being stored in the history storage means even if the specified event occurs when a restricted situation is present.

According to feature K1, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, since history information is not stored in restricted situations even if a predetermined event occurs, it is possible to prevent history information from being stored in situations where it is undesirable to store history information.

Feature K2. A gaming machine as described in Feature K1, wherein the restricted state can occur from the start of the supply of operating power to the history storage and execution means until the occurrence of a restriction release event.

Feature K2 makes it possible to prevent the occurrence of a specified event due to an operation check immediately after the start of the supply of operating power from being stored as history information.

Feature K3: A means for setting the limiting state when the supply of operating power to the history storage execution means is started and the limiting condition is met (a function for executing the process of step S3610 in the main CPU 63);
A means for not setting the limiting state when the supply of operating power to the history storage execution means is started and the limiting condition is not satisfied (a function for executing the processing of step S3621 in the main CPU 63);
The gaming machine described in feature K2 is characterized by comprising:

According to feature K3, the restricted situation may or may not be set depending on whether the restrictive conditions are met. This makes it possible to prevent the restricted situation from being set as necessary.

Feature K4. A gaming machine described in any one of Features K1 to K3, characterized in that the restricted state can occur from the time when the supply of operating power to the history storage execution means begins until the number of gaming balls discharged from the gaming area reaches or exceeds a predetermined reference number.

Feature K4 makes it possible to prevent history information from being stored until the number of game balls discharged from the game area reaches or exceeds a predetermined reference number after the supply of operating power begins.

Feature K5. When a predetermined event occurs as a result of a game being played, history information corresponding to that event is stored in the history storage means (normal counter area 231, open/close execution mode counter area 232, high frequency support mode counter area 233). History storage execution means (functions of executing normal goal entry management processing in the main CPU 63, goal entry management processing during the open/close execution mode, and goal entry management processing during the high frequency support mode);
An information deriving means (a function for executing the processing of step S4208 in the main CPU 63) for deriving behavior information corresponding to the game results for a predetermined period using the history information stored in the history storage means;
Equipped with
The gaming machine is characterized in that the information deriving means does not derive the mode information when a restricted situation occurs.

According to feature K5, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it is possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, the history information stored in the history storage means is used to derive behavior information corresponding to the results of play over a predetermined period. This makes it possible to understand the results of management of the gaming history, such as the frequency of occurrence of a predetermined event. Furthermore, since behavior information is not derived in restricted situations even if a predetermined event occurs, it is possible to prevent behavior information from being derived in situations where it is undesirable to derive behavior information.

Feature K6. A gaming machine as described in Feature K5, wherein the restricted state can occur from the start of the supply of operating power to the history storage and execution means until the occurrence of a restriction release event.

Feature K6 makes it possible to prevent the derivation of behavior information using historical information based on the occurrence of a specified event during an operation check immediately after the start of the supply of operating power.

Feature K7. A gaming machine as described in Feature K5 or K6, wherein the restricted state can occur from the time when the supply of operating power to the history storage execution means begins until the number of gaming balls discharged from the gaming area reaches or exceeds a predetermined reference number.

Feature K7 makes it possible to prevent mode information from being derived from the time the supply of operating power begins until the number of game balls discharged from the game area reaches or exceeds a predetermined reference number.

In addition, with respect to the configuration of features K1 to K7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned feature group G, feature group H, feature group I, feature group J, and feature group K can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be managed appropriately, and there is still room for improvement in this regard.

<Feature L group>
Feature L1: A control unit (main CPU 63) executes various processes and temporarily stores information in an internal storage unit (register of the main CPU 63) when the processes are executed.
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 21st embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
a save execution means for saving predetermined information, which is at least a part of the information stored in the internal storage means, to predetermined storage means (main RAM 65) when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed or when the situation changes to one in which the second predetermined processing is being executed (in the fifteenth embodiment, a function for executing the processing of step S3802 and steps S3902 to S3907 in the main CPU 63; in the sixteenth embodiment, a function for executing the processing of step S4402 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63);
a restoration execution means for restoring the predetermined information saved in the predetermined storage means to the internal storage means when or after the second predetermined processing is completed (in the fifteenth embodiment, a function for executing the processing of step S3804 and step S3910 to step S3915 in the main CPU 63; in the sixteenth embodiment, a function for executing the processing of step S4404 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of step S4510 to step S4515 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4605 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of step S4705 and step S4706 in the main CPU 63);
A gaming machine characterized by comprising:

According to feature L1, when the situation changes from one in which a first predetermined process is being executed to one in which a second predetermined process is being executed, or when the situation changes to one in which a second predetermined process is being executed, at least some of the information stored in the internal storage means is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being overwritten when the first predetermined process is executed when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the information saved in the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process when the second predetermined process is terminated, based on the state of the internal storage means before the second predetermined process was executed. As a result, various controls can be performed optimally.

Feature L2. The gaming machine described in Feature L1, wherein the predetermined information is a portion of the information stored in the internal storage means.

According to feature L2, only a portion of the information stored in the internal storage means is saved to the specified storage means, making it possible to reduce the storage capacity required to save the information from the internal storage means in the specified storage means.

Feature L3: The internal storage means includes at least a first storage area (WA register, BC register, DE register, HL register, IX register, and IY register) and a second storage area (registers other than the WA register, BC register, DE register, HL register, IX register, and IY register),
the second predetermined process execution means is configured to store information in the first storage area during the second predetermined process, but not to store information in the second storage area;
The gaming machine according to feature L2, wherein the save execution means saves the information stored in the first memory area to the predetermined memory means.

According to Feature L3, when the situation changes from one in which a first predetermined process is being executed to one in which a second predetermined process is being executed, or when the situation changes to one in which a second predetermined process is being executed, information in the first storage area of the internal storage means that is to be stored in the second predetermined process is saved to the predetermined storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the second predetermined process is executed when the second predetermined process is completed, while also reducing the storage capacity required in the predetermined storage means to save the information from the internal storage means.

Feature L4: The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
A gaming machine according to any one of features L1 to L3, wherein the save execution means saves the specified information in the second specified memory area.

According to Feature L4, by providing the predetermined storage means with a first predetermined storage area and a second predetermined storage area, it is possible to clearly differentiate the storage destination of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first predetermined process and the second predetermined process from being erased when the other process is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, at least some of the information stored in the internal storage means is saved to the second predetermined storage area. This makes it possible to save information in the internal storage means immediately before the second predetermined process is started, and to save that information without using the first predetermined storage area.

Feature L5: The saving execution means
a means for saving first predetermined information, which is part of the information stored in the internal storage means, to the first predetermined storage area during the first predetermined processing when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed (a function for executing the processing of step S3802 in the main CPU 63 in the fifteenth embodiment, and a function for executing the processing of step S4402 in the main CPU 63 in the sixteenth embodiment);
a means for saving second predetermined information, which is part of the information stored in the internal storage means, to the second predetermined storage area during the second predetermined processing when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed (a function for executing the processing of steps S3902 to S3907 in the main CPU 63 in the fifteenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63 in the seventeenth embodiment, a function for executing the processing of step S4602 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processing of steps S4702 and S4703 in the main CPU 63 in the nineteenth embodiment);
A gaming machine according to feature L4, characterized in that it is equipped with:

According to Feature L5, first predetermined information, which is a portion of the information stored in the internal storage means, is saved to a first predetermined storage area by a first predetermined process, and second predetermined information, which is a portion of the information stored in the internal storage means, is saved to a second predetermined storage area by a second predetermined process. This makes it possible to save each piece of information stored in the internal storage means at a time that is convenient for it, and also makes it possible to distribute the processing for saving information between the first predetermined process and the second predetermined process.

Feature L6. The gaming machine described in Feature L5, wherein the first predetermined information is information in a flag register provided in the internal storage means.

Feature L6 makes it possible to properly save the information in the flag register while the first predetermined process is being executed.

Feature L7. The second predetermined storage area is
a stack area (non-specific control stack area 224) in which information can be written by a push command and in which information can be read by a pop command;
a work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
A gaming machine according to any one of features L4 to L6, wherein the save execution means saves the specified information to one of the stack area and the work area.

According to Feature L7, when the situation changes from one in which a first predetermined process is being executed to one in which a second predetermined process is being executed, or when the situation changes to one in which a second predetermined process is being executed, at least some of the information stored in the internal storage means is saved to one of the stack area and work area in the second predetermined storage area. This makes it possible to consolidate the destinations for saving information and simplify the processing configuration for saving and restoring.

Feature L8. The gaming machine described in Feature L7, wherein the save execution means saves the specified information to the work area.

According to feature L8, by using the work area as the destination for saving at least some of the information stored in the internal storage means, it is possible to save that information without making cumulative changes to the stack pointer.

Feature L9. The first predetermined storage area is capable of storing and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine described in any one of features L4 to L8, characterized in that the second specified memory area is capable of storing information and reading information when the second specified process is executed, and is capable of reading information but is unable to store information when the first specified process is executed.

Feature L9 makes it possible to treat the first specified storage area as a storage area dedicated to the first specified process, and to treat the second specified storage area as a storage area dedicated to the second specified process.

Feature L10. The predetermined storage means is
a stack area (non-specific control stack area 224) in which information can be written by a push command and in which information can be read by a pop command;
a work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
A gaming machine according to any one of features L1 to L9, wherein the save execution means saves the specified information in one of the stack area and the work area.

Feature L10 makes it possible to consolidate destinations for saving specific information, thereby simplifying the processing configuration for saving and restoring specific information.

Feature L11. The gaming machine described in Feature L10, wherein the save execution means saves the specified information to the work area.

According to feature L11, by saving specific information to the work area, it is possible to save the information without making cumulative changes to the stack pointer.

Feature L12: The predetermined information is a part of the information stored in the internal storage means,
The gaming machine described in feature L11 is characterized in that the save execution means is equipped with a means (a function of executing the processing of step S3802 in the main CPU 63) for saving specific information, which is a portion of the information stored in the internal storage means, to the stack area when the situation changes from one in which the first specified processing is being executed to one in which the second specified processing is being executed, or when the situation changes to one in which the second specified processing is being executed.

According to feature L12, in a configuration in which predetermined information is saved to a work area, specific information is saved to a stack area. This makes it possible to distribute and save information stored in the internal storage means between the work area and the stack area.

Feature L13. A gaming machine described in Feature L12, wherein the predetermined information contains more information than the specific information.

According to feature L13, predetermined information, which has a larger volume than specific information, is saved in the work area, making it possible to prevent a large amount of information from being cumulatively stored in the stack area when saving information stored in the internal storage means.

Feature L14: When a state in which the first predetermined process is being executed changes to a state in which the second predetermined process is being executed, or when a state in which the second predetermined process is being executed changes, information in the stack pointer provided in the internal storage means becomes fixed information;
A gaming machine described in any one of features L1 to L13, characterized in that information of a stack pointer provided in the internal storage means is not subject to saving by the saving execution means.

According to feature L14, there is no need to reserve capacity in the specified storage means for saving stack pointer information, which makes it possible to reduce the capacity of the specified storage means. Furthermore, even in a configuration in which stack pointer information is not saved in this way, when the situation changes from executing the first specified process to executing the second specified process, or when the situation changes to executing the second specified process, the stack pointer information becomes fixed information, so it is possible to restore the stack pointer information to the state it was in before the second specified process was started, without having to save the stack pointer information as described above.

Feature L15. A gaming machine according to Feature L14, characterized in that it is equipped with means for setting the fixed information in the stack pointer when or after the second predetermined processing is completed (a function for executing the processing of step S3909 in the main CPU 63 in the 15th embodiment, a function for executing the processing of step S4509 in the main CPU 63 in the 17th embodiment, and a function for executing the processing of step S4604 in the main CPU 63 in the 18th embodiment).

Feature L15 enables the stack pointer to be restored to the state it had before the second specified process was started when or after the second specified process is terminated.

Feature L16. A gaming machine as described in Feature L14 or L15, characterized in that it is equipped with means for setting second response start information corresponding to the second predetermined processing in the stack pointer when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed, or when the situation changes to one in which the second predetermined processing is being executed (in the 15th embodiment, a function for executing the processing of step S3901 in the main CPU 63; in the 17th embodiment, a function for executing the processing of step S4501 in the main CPU 63; and in the 18th embodiment, a function for executing the processing of step S4601 in the main CPU 63).

According to feature L16, when the second predetermined process is started, second corresponding start information corresponding to the second predetermined process is set in the stack pointer, making it possible to store information in the stack area at an appropriate address during the second predetermined process.

Feature L17. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine described in any one of features L1 to L16, wherein the second predetermined process includes a process for managing a gaming history.

According to feature L17, processing for controlling the progress of a game is executed as the first predetermined processing, and processing for managing the game history is executed as the second predetermined processing, thereby making it possible to prevent information used in the processing for managing the game history from being overwritten when the processing for controlling the progress of a game is executed.

Feature L18: The predetermined storage means
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature L17 is characterized in that the second specified memory area is equipped with a history memory area (normal counter area 231, counter area 232 for open/close execution mode, counter area 233 for high frequency support mode) in which corresponding game history information is stored when a specified event occurs as a result of the game being played.

According to feature L18, when a predetermined event occurs, corresponding history information is stored in the history memory area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it becomes possible to prevent the information stored in the history memory area from being overwritten when the process for controlling the progress of a game is executed.

Feature L19. A gaming machine according to Feature L18, wherein the second predetermined processing execution means includes information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

Feature L19 enables the deriving of behavior information corresponding to game results over a specified period of time using history information stored in the history storage area, making it possible to ascertain the results of game history management, such as the frequency of occurrence of specified events.

Feature L20. The gaming machine described in Feature L19, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature L20, when behavior information corresponding to game results over a predetermined period is derived using history information, the behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first predetermined process and a process for managing game history as the second predetermined process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

In addition, with respect to the configuration of features L1 to L20, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature M group>
Feature M1. The device is provided with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when the processes are executed,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 21st embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
a save execution means for saving predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed, or when the situation changes to one in which the second predetermined processing is being executed (a function for executing the processing of steps S3902 to S3907 in the main CPU 63 in the fifteenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63 in the seventeenth embodiment, a function for executing the processing of step S4602 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processing of steps S4701 and S4703 in the main CPU 63 in the nineteenth embodiment);
a restoration execution means for restoring the predetermined information saved in the predetermined storage means to the internal storage means when or after the second predetermined processing is completed (a function for executing the processing of steps S3910 to S3915 in the main CPU 63 in the fifteenth embodiment, a function for executing the processing of steps S4510 to S4515 in the main CPU 63 in the seventeenth embodiment, a function for executing the processing of step S4605 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processing of steps S4705 and S4706 in the main CPU 63 in the nineteenth embodiment);
Equipped with
The saving execution means saves the predetermined information into the predetermined storage means in response to a load command.

According to feature M1, when the situation changes from when the first predetermined process is being executed to when the second predetermined process is being executed, or when the situation changes to when the second predetermined process is being executed, predetermined information, which is at least a portion of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being overwritten when the first predetermined process is executed when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the predetermined information saved to the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process from the state of the internal storage means before the execution of the second predetermined process when the second predetermined process is terminated. When the situation changes from when the first predetermined process is being executed to when the second predetermined process is being executed, or when the situation changes to when the second predetermined process is being executed, the predetermined information is saved to the predetermined storage means by a load instruction. This makes it possible to save the predetermined information without changing the stack pointer.

Feature M2. The predetermined storage means is
a stack area (a non-specific control stack area 224) in which information can be written by a push command and in which information can be read by a pop command;
a work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
The gaming machine according to feature M1, wherein the save execution means saves the specified information in the work area.

According to feature M2, the work area is used as the destination for saving specified information, which is at least a portion of the information stored in the internal storage means, making it possible to save that information without making cumulative changes to the stack pointer.

Feature M3: The predetermined information is a part of the information stored in the internal storage means,
The gaming machine described in feature M2 is characterized in that the save execution means is equipped with a means (a function of executing the processing of step S3802 in the main CPU 63) for saving specific information, which is a portion of the information stored in the internal storage means, to the stack area when the situation changes from one in which the first specified processing is being executed to one in which the second specified processing is being executed, or when the situation changes to one in which the second specified processing is being executed.

According to feature M3, in a configuration in which predetermined information is saved to a work area, specific information is saved to a stack area. This makes it possible to split and save information stored in the internal storage means between the work area and the stack area.

Feature M4. A gaming machine as described in Feature M3, wherein the predetermined information contains more information than the specific information.

Feature M4 allows predetermined information, which has a larger volume than specific information, to be saved in the work area, thereby preventing a large amount of information from being cumulatively stored in the stack area when saving information stored in the internal storage means.

Feature M5. The work area is
a first work area (a work area 221 for specific control) in which information is stored when the first predetermined process is executed;
a second work area (a work area 223 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
A gaming machine according to any one of features M2 to M4, wherein the save execution means saves the specified information in the second work area.

According to feature M5, by providing the work area with a first work area and a second work area, it is possible to clearly differentiate the storage destination of information in the work area between the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, at least some of the information stored in the internal storage means is saved to the second work area. This makes it possible to save information in the internal storage means immediately before the second predetermined process is started, and to save that information without using the first work area.

Feature M6. The first work area is capable of storing and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine described in feature M5, characterized in that the second work area is capable of storing information and reading information when the second specified process is executed, and is capable of reading information but is unable to store information when the first specified process is executed.

Feature M6 makes it possible to treat the first work area as a storage area dedicated to the first specified process, and to treat the second work area as a storage area dedicated to the second specified process.

Feature M7: A control means (main CPU 63) is provided that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when the processes are executed,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 21st embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
a save execution means for saving predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed, or when the situation changes to one in which the second predetermined processing is being executed (a function for executing the processing of steps S3902 to S3907 in the main CPU 63 in the fifteenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63 in the seventeenth embodiment, a function for executing the processing of step S4602 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processing of steps S4701 and S4703 in the main CPU 63 in the nineteenth embodiment);
a restoration execution means for restoring the predetermined information saved in the predetermined storage means to the internal storage means when or after the second predetermined processing is completed (a function for executing the processing of steps S3910 to S3915 in the main CPU 63 in the fifteenth embodiment, a function for executing the processing of steps S4510 to S4515 in the main CPU 63 in the seventeenth embodiment, a function for executing the processing of step S4605 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processing of steps S4705 and S4706 in the main CPU 63 in the nineteenth embodiment);
Equipped with
The predetermined storage means includes:
a stack area (a non-specific control stack area 224) in which information can be written by a push command and in which information can be read by a pop command;
a work area (non-specific control work area 223) in which information can be written and read by a load command;
Equipped with
The gaming machine is characterized in that the save execution means saves the specified information to one of the stack area and the work area.

According to feature M7, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, predetermined information, which is at least a portion of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being overwritten when the first predetermined process is executed when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the predetermined information saved in the predetermined storage means is restored to the internal storage means. This makes it possible, when the second predetermined process is terminated, to execute a process different from the second predetermined process from the state of the internal storage means before the second predetermined process was executed.

In addition, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the specified information is saved to one of the stack area and work area in the specified storage means. This makes it possible to consolidate the destinations for saving information and simplify the processing configuration for saving and restoring.

In addition, with respect to the configuration of features M1 to M7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature N group>
Feature N1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 21st embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
Equipped with
A gaming machine characterized in that when the situation changes from executing the first specified processing to executing the second specified processing, the information of the stack pointer stored in the internal storage means becomes fixed information.

According to feature N1, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process, the stack pointer information stored in the internal storage means becomes fixed, so there is no need to save the stack pointer information when starting the second predetermined process. This eliminates the need to allocate a storage area for saving the stack pointer information. Furthermore, when the situation changes from the execution of the first predetermined process to the execution of the second predetermined process, the stack pointer information becomes fixed, so it is possible to restore the stack pointer information to what it was before the second predetermined process was started, without having to save the stack pointer information as described above.

Feature N2. A gaming machine as described in Feature N1, characterized in that it is equipped with means for setting the fixed information in the stack pointer when or after the second predetermined processing is completed (a function for executing the processing of step S3909 in the main CPU 63 in the 15th embodiment, a function for executing the processing of step S4509 in the main CPU 63 in the 17th embodiment, and a function for executing the processing of step S4604 in the main CPU 63 in the 18th embodiment).

According to feature N2, when or after the second predetermined process is terminated, it is possible to restore the stack pointer information to the state before the second predetermined process was started.

Feature N3. A gaming machine as described in Feature N1 or N2, characterized in that it is equipped with means for setting second response start information corresponding to the second predetermined processing in the stack pointer when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed (in the 15th embodiment, a function for executing the processing of step S3901 in the main CPU 63; in the 17th embodiment, a function for executing the processing of step S4501 in the main CPU 63; and in the 18th embodiment, a function for executing the processing of step S4601 in the main CPU 63).

According to feature N3, when the second predetermined process is started, second corresponding start information corresponding to the second predetermined process is set in the stack pointer, making it possible to store information in the stack area at an appropriate address during the second predetermined process.

Feature N4. A save execution means for saving predetermined information, which is at least a part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65) when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed or when the situation changes to one in which the second predetermined processing is being executed (in the fifteenth embodiment, a function for executing the processing of step S3802 and steps S3902 to S3907 in the main CPU 63; in the sixteenth embodiment, a function for executing the processing of step S4402 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of steps S4502 to S4507 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4602 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of steps S4701 and S4703 in the main CPU 63);
a restoration execution means for restoring the predetermined information saved in the predetermined storage means to the internal storage means when or after the second predetermined processing is completed (in the fifteenth embodiment, a function for executing the processing of step S3804 and step S3910 to step S3915 in the main CPU 63; in the sixteenth embodiment, a function for executing the processing of step S4404 in the main CPU 63; in the seventeenth embodiment, a function for executing the processing of step S4510 to step S4515 in the main CPU 63; in the eighteenth embodiment, a function for executing the processing of step S4605 in the main CPU 63; and in the nineteenth embodiment, a function for executing the processing of step S4705 and step S4706 in the main CPU 63);
Equipped with
A gaming machine described in any one of features N1 to N3, characterized in that the information of the stack pointer provided in the internal storage means is not subject to saving by the saving execution means.

According to Feature N4, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, at least some of the information stored in the internal storage means is saved to the predetermined storage means. This makes it possible to prevent the information stored in the internal storage means from being overwritten when the first predetermined process is executed when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the information saved in the predetermined storage means is restored to the internal storage means. This makes it possible to execute a process different from the second predetermined process when the second predetermined process is terminated, from the state of the internal storage means before the execution of the second predetermined process. Furthermore, because stack pointer information is not subject to saving, there is no need to reserve capacity in the predetermined storage means for saving stack pointer information. This makes it possible to reduce the capacity of the predetermined storage means. Furthermore, even in a configuration in which stack pointer information is not saved in this way, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the stack pointer information becomes fixed information, so it is possible to restore the stack pointer information to the state it was in before the second predetermined process was started, without having to save the stack pointer information as described above.

Feature N5: The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature N4 is characterized in that the save execution means saves the specified information to the second specified memory area.

According to Feature N5, by providing the predetermined storage means with a first predetermined storage area and a second predetermined storage area, it is possible to clearly differentiate the storage destination of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first predetermined process and the second predetermined process from being erased when the other process is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, at least some of the information stored in the internal storage means is saved to the second predetermined storage area. This makes it possible to save information in the internal storage means immediately before the second predetermined process is started, and to save that information without using the first predetermined storage area.

Feature N6. The first predetermined storage area is capable of storing and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine described in feature N5, characterized in that the second specified memory area is capable of storing information and reading information when the second specified process is executed, and is capable of reading information but is unable to store information when the first specified process is executed.

Feature N6 makes it possible to treat the first specified storage area as a storage area dedicated to the first specified process, and to treat the second specified storage area as a storage area dedicated to the second specified process.

In addition, for the configuration of features N1 to N6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature O group>
Feature O1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 21st embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
When the state where the first predetermined processing is being executed changes to the state where the second predetermined processing is being executed or when the state where the second predetermined processing is being executed changes to a state where a predetermined memory area (WA register, BC register, DE register, HL register, IX register, and IY register) which is at least a part of the memory area in the internal memory means is set to a predetermined state (a function of executing the processing of steps S4803 to S4808 in the main CPU 63);
A second state setting means (a function of executing the processes of steps S4903 to S4908 in the main CPU 63) that sets the state of the predetermined storage area to the predetermined state when or after the second predetermined process is completed;
A gaming machine characterized by comprising:

According to Feature O1, when the situation changes from one in which a first predetermined process is being executed to one in which a second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the state of the predetermined storage area of the internal storage means is set to the predetermined state, and when the second predetermined process is completed or after it has been completed, the state of the predetermined storage area is set to the predetermined state again. This makes it possible to set the state of the predetermined storage area to the predetermined state before and after the second predetermined process. This makes it possible to prevent the state of the predetermined storage area due to one of the first predetermined process and the second predetermined process from affecting the other process. As a result, various controls can be performed optimally.

Feature O2. The gaming machine described in Feature O1, wherein the predetermined state is a state when the supply of operating power to the control means begins.

According to Feature O2, the specified storage area is set to the specified state when the supply of operating power to the control means begins, which simplifies the processing configuration for setting the specified state.

Feature O3. A gaming machine according to Feature O1 or O2, wherein the predetermined state is a state in which the predetermined memory area is cleared to "0."

According to Feature O3, the specified memory area is set to a "0" cleared state as the specified state, which simplifies the processing configuration for setting the specified state.

Feature O4. A gaming machine described in any one of Features O1 to O3, wherein the specified memory area is a partial memory area of the internal memory means.

Feature O4 allows only a portion of the storage area of the internal storage means to be set to a predetermined state, thereby reducing the processing load required to set the storage area to a predetermined state.

Feature O5. The internal storage means includes at least the predetermined storage area and another storage area (registers other than the WA register, the BC register, the DE register, the HL register, the IX register, and the IY register),
the second predetermined process execution means is configured to store information in the predetermined storage area during the second predetermined process, but not to store information in the separate storage area;
A gaming machine described in feature O4, characterized in that the first state setting means and the second state setting means are configured not to change the state of the separate memory area.

According to Feature O5, when the situation changes from one in which a first predetermined process is being executed to one in which a second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the predetermined storage area in the internal storage means that is the target of storing information in the second predetermined process is set to a predetermined state. This makes it possible to prevent the state of the predetermined storage area from being affected by the first predetermined process from affecting the second predetermined process. Furthermore, because the state of the separate storage area is not changed, it is possible to prevent setting the predetermined state when the second predetermined process is started from affecting processing after the second predetermined process has ended.

Feature O6. A gaming machine described in any one of Features O1 to O5, characterized in that the information in the specified memory area before the first state setting means sets the specified state is information that is not used after the second specified processing is completed.

Feature O6 makes it possible to prevent the processing after the second predetermined processing is completed from being affected even if the predetermined storage area is set to a predetermined state when the second predetermined processing is executed or when the second predetermined processing is executed.

Feature O7. When the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed or when the situation where the second predetermined processing is being executed is reached, a save execution means (a function of executing the processing of step S4802 in the main CPU 63) saves predetermined information (information in the flag register), which is part of the information stored in the internal storage means, to a predetermined storage means (main RAM 65);
A restoration execution means (a function of executing the processing of step S4810 in the main CPU 63) that restores the specified information saved in the specified storage means to the internal storage means when or after the second specified processing is completed;
A gaming machine according to any one of features O1 to O6, characterized in that it is equipped with:

According to Feature O7, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, predetermined information, which is part of the information stored in the internal storage means, is saved to the predetermined storage means. This makes it possible to prevent information stored in the internal storage means when the first predetermined process is executed and which will be required when the first predetermined process is subsequently executed from being overwritten when the second predetermined process is executed. Furthermore, when or after the second predetermined process is terminated, the predetermined information saved in the predetermined storage means is restored to the internal storage means. This makes it possible, when the second predetermined process is terminated, to execute a process different from the second predetermined process from the state of the internal storage means before the second predetermined process was executed.

Feature O8. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine described in any one of features O1 to O7, wherein the second predetermined process includes a process for managing gaming history.

According to Feature O8, a process for controlling the progress of a game is executed as the first predetermined process, and a process for managing the game history is executed as the second predetermined process, thereby making it possible to prevent information used in the process for managing the game history from being overwritten when the process for controlling the progress of a game is executed.

Feature O9. The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature O8 is characterized in that the second specified memory area is equipped with a history memory area (normal counter area 231, counter area 232 for open/close execution mode, counter area 233 for high frequency support mode) in which corresponding game history information is stored when a specified event occurs as a result of the game being played.

According to Feature O9, when a predetermined event occurs, corresponding history information is stored in the history memory area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, unauthorized access to or unauthorized modification of the history information can be prevented. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it becomes possible to prevent the information stored in the history memory area from being overwritten when the process for controlling the progress of a game is executed.

Feature O10. A gaming machine as described in Feature O9, wherein the second predetermined processing execution means includes information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

According to Feature O10, by using the history information stored in the history storage area to derive behavior information corresponding to game results over a specified period, it becomes possible to grasp the results of game history management, such as the frequency of occurrence of specified events.

Feature O11. The gaming machine described in Feature O10, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to Feature O11, when behavior information corresponding to game results over a predetermined period is derived using history information, that behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first predetermined process and a process for managing game history as the second predetermined process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

In addition, with respect to the configuration of features O1 to O11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature P group>
Feature P1: Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 21st embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the fifteenth to twenty-first embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
A gaming machine characterized by comprising:

According to feature P1, a first predetermined storage area and a second predetermined storage area are provided, with the first predetermined storage area being treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area being treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destinations of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in the first predetermined process or the second predetermined process from being erased when the other process is executed.

Feature P2. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine according to feature P1, characterized in that the second predetermined process includes a process for managing gaming history.

According to feature P2, processing for controlling the progress of a game is executed as the first predetermined processing, and processing for managing the game history is executed as the second predetermined processing, making it possible to prevent information used in the processing for managing the game history from being overwritten when the processing for controlling the progress of a game is executed.

Feature P3. A gaming machine as described in Feature P2, wherein the second predetermined memory area includes history memory areas (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which game history information corresponding to a predetermined event that occurs as a result of the execution of a game is stored.

According to feature P3, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten when the process for controlling the progress of a game is executed.

Feature P4. A gaming machine as described in Feature P3, wherein the second predetermined processing execution means is equipped with information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

Feature P4 allows the history information stored in the history storage area to be used to derive behavior information corresponding to game results over a specified period, making it possible to ascertain the results of game history management, such as the frequency of occurrence of specified events.

Feature P5. A gaming machine according to Feature P4, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature P5, when behavior information corresponding to game results over a specified period is derived using history information, that behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first specified process and a process for managing game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

Feature P6: A first saving means (a function for executing the process of step S3802 in the main CPU 63 in the fifteenth embodiment, and a function for executing the process of step S4402 in the main CPU 63 in the sixteenth embodiment) for saving the first predetermined information, which is part of the information stored in the internal storage means, to the first predetermined storage area during the first predetermined processing when the situation changes from the situation where the first predetermined processing is being executed to the situation where the second predetermined processing is being executed;
a second saving means for saving second predetermined information, which is part of the information stored in the internal storage means, to the second predetermined storage area during the second predetermined processing when the situation changes from one in which the first predetermined processing is being executed to one in which the second predetermined processing is being executed (a function for executing the processing of steps S3902 to S3907 in the main CPU 63 in the fifteenth embodiment; a function for executing the processing of steps S4502 to S4507 in the main CPU 63 in the seventeenth embodiment; a function for executing the processing of step S4602 in the main CPU 63 in the eighteenth embodiment; and a function for executing the processing of steps S4701 and S4703 in the main CPU 63 in the nineteenth embodiment);
A gaming machine according to any one of features P1 to P5, characterized in that it is equipped with:

According to feature P6, first predetermined information, which is a portion of the information stored in the internal storage means, is saved to a first predetermined storage area by a first predetermined process, and second predetermined information, which is a portion of the information stored in the internal storage means, is saved to a second predetermined storage area by a second predetermined process. This makes it possible to save each piece of information stored in the internal storage means at a time that is convenient for it, and also makes it possible to distribute the processing for saving information between the first predetermined process and the second predetermined process.

Feature P7: A first restoration execution means (a function for executing the processing of step S3804 in the main CPU 63 in the fifteenth embodiment, and a function for executing the processing of step S4404 in the main CPU 63 in the sixteenth embodiment) that restores the first predetermined information saved in the first predetermined storage area to the internal storage means when or after the second predetermined processing is completed;
a second return execution means for returning the second predetermined information saved in the second predetermined storage area to the internal storage means when or after the second predetermined processing is completed (a function for executing the processing of steps S3910 to S3915 in the main CPU 63 in the fifteenth embodiment, a function for executing the processing of steps S4510 to S4515 in the main CPU 63 in the seventeenth embodiment, a function for executing the processing of step S4605 in the main CPU 63 in the eighteenth embodiment, and a function for executing the processing of steps S4705 and S4706 in the main CPU 63 in the nineteenth embodiment);
The gaming machine described in feature P6 is characterized by comprising:

According to Feature P7, when or after the second predetermined processing is completed, the first predetermined information saved in the first predetermined storage area is restored to the internal storage means, and the second predetermined information saved in the second predetermined storage area is restored to the internal storage means, making it possible to restore the state of the internal storage means to the state before the second predetermined processing was started.

Feature P8. A gaming machine as described in Feature P6 or P7, wherein the first predetermined information includes information from a flag register provided in the internal storage means.

Feature P8 makes it possible to properly save the information in the flag register while the first predetermined process is being executed.

Feature P9. A gaming machine described in any one of Features P6 to P8, wherein the second predetermined information includes information from all registers of the internal storage means.

Feature P9 allows the information in all registers of the internal storage means to be saved together, eliminating the need to selectively save register information.

Feature P10. The second predetermined storage area is
a stack area (a stack area 224 for non-specific control) in which information is written by a push command and in which information is read by a pop command;
a work area (non-specific control work area 223) in which information is written and read by a load command;
Equipped with
The gaming machine described in feature P9 is characterized in that the second save execution means saves the second predetermined information to one of the stack area and the work area.

According to feature P10, the information in all registers of the internal storage means is saved to either the stack area or the work area in the second predetermined storage area. This makes it possible to centralize the save destination for all register information, simplifying the processing configuration for saving and restoring the information.

Feature P11. The gaming machine described in Feature P10, wherein the second save execution means saves the second specified information to the stack area.

Feature P11 makes it possible to save information from all registers without using work area.

Feature P12. A gaming machine described in any one of Features P6 to P11, wherein the second predetermined information includes stack pointer information for the internal storage means.

Feature P12 makes it possible to properly save stack pointer information while the first specified process is being executed.

In addition, with respect to the configuration of features P1 to P12, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned feature group L, feature group M, feature group N, feature group O, and feature group P can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

However, gaming machines such as those exemplified above require various controls to be performed appropriately, and there is still room for improvement in this regard.

<Feature Q group>
Feature Q1. A control means (MPU 62) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when the processes are executed;
a history storage means (management RAM 241) that is provided as a chip separate from the control means and is capable of temporarily storing information;
Equipped with
The control means is a gaming machine characterized by having a history memory execution means (a function that executes normal ball entry management processing in the main CPU 63, ball entry management processing during the opening and closing execution mode, and ball entry management processing during the high frequency support mode) that stores corresponding game history information in the history memory means when a specified event occurs as a result of the game being played.

According to feature Q1, when a predetermined event occurs, corresponding history information is stored in the history storage means. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, because the history storage means is provided as a chip separate from the control means, it is possible to increase the memory capacity for storing history information while using general-purpose control means.

Feature Q2. A gaming machine as described in Feature Q1, characterized in that the control means is equipped with a predetermined storage means (main RAM 65) that temporarily stores information when various processes are executed.

Feature Q2 allows a configuration that includes not only a predetermined storage means provided in the control means but also a history storage means provided as a chip separate from the control means to store history information in the history storage means, thereby enabling the storage and retention of a large amount of history information.

Feature Q3. The gaming machine described in Feature Q2, wherein the control means temporarily stores information in the specified storage means when executing processing related to the history information.

According to feature Q3, in a configuration in which history storage means for storing history information is provided as a chip separate from the control means, when processing related to the history information is executed, the information is temporarily stored in a predetermined storage means provided in the control means, making it possible to prevent an extreme decrease in processing speed when processing related to the history information is executed.

Feature Q4. A gaming machine described in any one of Features Q1 to Q3, characterized in that the control means is equipped with information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage means to derive behavior information corresponding to game results over a predetermined period of time.

Feature Q4 allows the historical information stored in the history storage means to be used to derive behavioral information corresponding to game results over a specified period, making it possible to ascertain the results of game history management, such as the frequency of occurrence of specified events.

Feature Q5. A gaming machine as described in Feature Q4, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature Q5, when behavior information corresponding to game results over a specified period is derived using history information, that behavior information is stored in the behavior information storage area. This makes it possible to grasp the results of game history management at any time.

In addition, with respect to the configuration of features Q1 to Q5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group Q can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be managed appropriately, and there is still room for improvement in this regard.

<Feature R group>
Feature R1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a situation generating means for generating a setting possible situation in which the setting value to be used can be changed based on the occurrence of a plurality of events including a first event and a second event when the supply of operating power to the control means having the setting means is started (a function for executing the processing of steps S5003 to S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63 in another embodiment, and a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63 in the 23rd embodiment);
A gaming machine characterized by comprising:

According to feature R1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will hope that the more advantageous setting value will be the setting value to be used. In this case, in order for the setting value to be used to be set, multiple events including the first and second events must occur when the supply of operating power to the control means begins. This makes it difficult to fraudulently set the setting value to be used.

Feature R2. Equipped with an open detection means for detecting that the opening/closing body (front door frame 14) is in the open state (a function for executing the processing of step S5005 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of step S5505 in the main CPU 63 in another embodiment, and a function for executing the processing of step S5703 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R1 is characterized in that the situation generation means determines that the first event has occurred based on the fact that the opening/closing body is in an open state being detected by the opening detection means.

According to feature R2, the opening/closing body must be in the open state in order for the setting value to be set to be used. This makes it possible to highlight any fraudulent attempts to set the setting value to be used, thereby making it easier to discover such fraud.

Feature R3. Equipped with separate opening detection means for detecting that the separate opening/closing body (the gaming machine main body 12) is in the open state (a function for executing the processing of step S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of step S5506 in the main CPU 63 in another embodiment, and a function for executing the processing of step S5704 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R2 is characterized in that the situation generation means determines that the second event has occurred based on the fact that the separate opening/closing body is in an open state being detected by the separate opening detection means.

According to feature R3, in order to set the target setting value, not only must the opening/closing device be in the open state, but a separate opening/closing device must also be in the open state. This makes it more difficult to fraudulently set the target setting value, and also makes such fraudulent behavior more noticeable.

Feature R4: The setting means is configured to perform at least one of selecting the setting value to be used and setting the setting value to be used based on the operation of a predetermined operation means (update button 68b, reset button 68c),
A gaming machine according to feature R2 or R3, characterized in that the predetermined operating means is configured to be operable by opening a separate opening/closing body.

According to feature R4, the target setting value cannot be set unless an opening/closing body other than the separate opening/closing body that is opened to enable operation of the specified operating means is opened. This makes it difficult to fraudulently set the target setting value, and also makes such fraudulent behavior more noticeable.

Feature R5. The opening and closing body defines the front side of the gaming machine of the gaming area into which the gaming balls flow,
A gaming machine described in any one of features R2 to R4, characterized in that the gaming area is opened to the front of the gaming machine when the opening/closing body is opened.

According to feature R5, in order to set the setting value to be used, the opening and closing member must be in the open state, opening the gaming area to the front of the gaming machine. This makes it more difficult to fraudulently set the setting value to be used, and also makes such fraudulent behavior more noticeable.

Feature R6. A gaming machine described in any one of Features R1 to R5, wherein the situation generation means determines that one of the plurality of events has occurred based on a predetermined operation being performed using a setting key in the setting key insertion section (setting key insertion section 68a).

According to feature R6, in order to set the setting value to be used, it is necessary not only to perform a specific operation using the setting key on the setting key insertion section, but also to cause a separate event to occur. This makes it difficult to fraudulently set the setting value to be used.

Feature R7. A gaming machine described in any one of Features R1 to R6, wherein the situation generation means identifies that one of the plurality of events has occurred based on the occurrence of a predetermined gaming event (operation of the launch operation device 28, entry of a ball into the through gate 35) that occurs when a game is played.

According to feature R7, in order to set the setting value to be used, not only does it require the occurrence of a specific game event that occurs when a game is played, but it also requires the occurrence of a separate event. This makes it more difficult to fraudulently set the setting value to be used.

Feature R8. A gaming machine described in any one of Features R1 to R7, wherein the situation generation means determines that one of the plurality of events has occurred based on the detection of a gaming ball by ball entry detection means (gate detection sensor 49a) that detects that a gaming ball has entered a predetermined ball entry section provided in the gaming area.

According to feature R8, in order for the setting value to be used to be set, a game ball must be thrown into a specified ball entry area, and a separate event must occur. This makes it more difficult to fraudulently set the setting value to be used.

Feature R9. A setting value notification means (a function of executing a setting confirmation process in the main CPU 63) is provided, which notifies the setting value to be used set by the setting means by the notification means,
A gaming machine described in any one of features R1 to R8, characterized in that the setting value notification means notifies the setting value to be used, which is set by the setting means, based on the occurrence of multiple events including the first event and the second event.

Feature R9 makes it difficult to fraudulently check setting values. Furthermore, the amusement hall manager only needs to trigger the first and second events whether setting a setting value to be used or checking a setting value, which standardizes the tasks and makes it easier to understand each task.

Feature R10. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a situation generating means for creating a setting possible situation in which the setting means can set the setting value to be used, based on the occurrence of a plurality of events including both a predetermined operation using a setting key on a setting key insertion section (setting key insertion section 68a) and another event different from the predetermined operation using the setting key on the setting key insertion section (a function for executing the processing of steps S5003 to S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63 in another embodiment, and a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63 in the 23rd embodiment);
A gaming machine characterized by comprising:

According to Feature R10, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will hope that the more advantageous setting value will be the one to be used. In this case, in order to set the setting value to be used, it is necessary not only to perform a specified operation using the setting key on the setting key insertion section, but also to cause a separate event to occur. This makes it difficult to fraudulently set the setting value to be used.

Feature R11. Equipped with an open detection means for detecting that the opening/closing body (front door frame 14) is in the open state (a function for executing the processing of step S5005 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of step S5505 in the main CPU 63 in another embodiment, and a function for executing the processing of step S5703 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R10 is characterized in that the situation generation means determines that the different event has occurred based on the fact that the opening/closing body is in an open state being detected by the opening detection means.

According to feature R11, the opening/closing body must be in the open state in order for the setting value to be set to be used. This makes it possible to highlight any fraudulent attempts to set the setting value to be used, thereby making it easier to discover such fraud.

Feature R12. Equipped with separate opening detection means for detecting that the separate opening/closing body (the gaming machine main body 12) is in the open state (a function for executing the processing of step S5006 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of step S5506 in the main CPU 63 in another embodiment, and a function for executing the processing of step S5704 in the main CPU 63 in the 23rd embodiment),
The gaming machine described in feature R11 is characterized in that the situation generation means determines that one of the multiple events has occurred based on the fact that the separate opening/closing body is in an open state being recognized by the separate opening recognition means.

According to feature R12, in order to set the setting value to be used, not only must the opening/closing device be in the open state, but a separate opening/closing device must also be in the open state. This makes it more difficult to fraudulently set the setting value to be used, and also makes such fraudulent behavior more noticeable.

Feature R13: The setting means is configured to perform at least one of selecting the setting value to be used and setting the setting value to be used based on operation of a predetermined operation means (update button 68b, reset button 68c),
A gaming machine according to feature R11 or R12, characterized in that the predetermined operating means is configured to be operable by opening a separate opening/closing body.

According to feature R13, the target setting value cannot be set unless an opening/closing body different from the separate opening/closing body that is opened to enable operation of the specified operating means is opened. This makes it difficult to fraudulently set the target setting value and makes such fraudulent behavior more noticeable.

Feature R14. The opening and closing body defines the front side of the gaming machine of the gaming area into which the gaming balls flow,
A gaming machine described in any one of features R11 to R13, characterized in that the gaming area is opened to the front of the gaming machine when the opening/closing body is opened.

According to feature R14, in order to set the setting value to be used, the opening and closing member must be in the open state, opening the gaming area to the front of the gaming machine. This makes it more difficult to fraudulently set the setting value to be used, and also makes such fraudulent behavior more noticeable.

Feature R15. A gaming machine described in any one of Features R10 to R14, wherein the situation generation means identifies that one of the plurality of events has occurred based on the occurrence of a predetermined gaming event (operation of the launch operation device 28, entry of a ball into the through gate 35) that occurs when a game is played.

According to feature R15, in order to set the setting value to be used, it is necessary not only to perform a predetermined operation using the setting key in the setting key insertion section, but also to trigger a predetermined game event that occurs when a game is played. This makes it difficult to fraudulently set the setting value to be used.

Feature R16. A gaming machine described in any one of Features R10 to R15, wherein the situation generation means determines that one of the plurality of events has occurred based on the detection of a gaming ball by ball entry detection means (gate detection sensor 49a) that detects that a gaming ball has entered a predetermined ball entry section provided in the gaming area.

According to feature R16, in order to set the setting value to be used, it is necessary not only to perform a predetermined operation using the setting key in the setting key insertion section, but also to have a game ball enter a predetermined ball entry section. This makes it difficult to fraudulently set the setting value to be used.

Feature R17. A setting value notification means (a function of executing a setting confirmation process in the main CPU 63) is provided, which notifies the setting value to be used set by the setting means by a notification means,
A gaming machine described in any one of features R10 to R16, characterized in that the setting value notification means notifies the setting value to be used, which is set by the setting means, based on the occurrence of multiple events including both the specified operation using the setting key on the setting key insertion section and the separate event.

Feature R17 makes it difficult to fraudulently check setting values. Furthermore, whether setting a setting value to be used or checking a setting value, the amusement hall manager simply performs a specific operation using the setting key in the setting key insertion section and causes a separate event, which standardizes the tasks and makes it easier to understand each task.

In addition, in relation to the configuration of features R1 to R17, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned group of features R can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

However, with gaming machines such as those exemplified above, it is necessary to deal with fraudulent gaming machines, and there is still room for improvement in this regard.

<Feature S group>
Feature S1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a situation generating means for creating a setting possible situation in which the setting value to be used can be changed (in the 22nd embodiment, a function for executing the processing of steps S5003 to S5006 and steps S5401 to S5408 in the main CPU 63; in another embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63; in the 23rd embodiment, a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63; in the 24th embodiment, a function for executing the processing of steps S5801 to S5804 in the main CPU 63; and in the 25th embodiment, a function for executing the processing of steps S5901 to S5904 in the main CPU 63);
A setting value grasping means for grasping whether the setting value before the setting possible state is reached and the setting value set by the setting means are the same (in the 22nd embodiment, a function for executing the processing of steps S5017 and S5111 to S5112 in the main CPU 63, and in another embodiment, a function for executing the processing of steps S5611 to S5612 in the main CPU 63);
A gaming machine characterized by comprising:

According to Feature S1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, it is possible to determine whether the setting value before the setting situation becomes possible and the setting value set in the setting situation are the same. This makes it possible to execute processing that corresponds to whether the setting values are the same across the setting situation. Therefore, when the setting value to be used is set, it is possible to create a favorable situation for the setting result, and the setting value setting process can be carried out efficiently.

Feature S2. A gaming machine according to Feature S1, characterized in that it is equipped with a simultaneous processing means (a function for executing the processing of step S5113 in the main CPU 63 in the 22nd embodiment, or a function for executing the processing of step S5613 in the main CPU 63 in another embodiment) that executes corresponding simultaneous processing based on the setting value grasping means grasping that the setting value before the setting-enabled state is reached is the same as the setting value set by the setting means.

Feature S2 enables execution of identical processing when the setting values are identical across setting availability situations, thereby creating a favorable situation for identical setting values.

Feature S3. The gaming machine described in Feature S2, wherein the simultaneous time means executes processing to issue a notification corresponding to the fact that the setting value has not been changed, as the simultaneous time processing.

Feature S3 makes it possible to notify the gaming hall manager or other personnel that the setting value is the same across setting availability situations.

Feature S4. A gaming machine described in any one of Features S1 to S3, characterized in that it is equipped with non-identical time means (a function for executing the processing of step S5114 in the main CPU 63 in the 22nd embodiment, or a function for executing the processing of step S5614 in the main CPU 63 in another embodiment) that executes corresponding non-identical time processing based on the setting value grasping means grasping that the setting value before the setting possible state occurs is different from the setting value set by the setting means.

Feature S4 enables the execution of non-identical processing when the setting value is not the same across setting availability situations, thereby creating a favorable situation for changing the setting value.

Feature S5. The gaming machine described in Feature S4, wherein the non-identical time means executes processing to issue a notification corresponding to a change in the setting value as the non-identical time processing.

Feature S5 makes it possible to notify the gaming hall manager or other personnel that a setting value has been changed between setting availability situations.

Feature S6. A gaming machine described in any one of Features S1 to S5, wherein the situation generation means brings about the setting possible situation when, after the supply of operating power to the control means having the setting means has begun, it becomes necessary to erase information from the storage means that stores the setting value.

Feature S6 enables a setting status to be entered when it becomes necessary to erase information from the storage means that stores the setting value, preventing gameplay from continuing even though the setting value information has been erased. In this case, the configuration of feature S1 described above is provided, and it is possible to determine whether the setting value before the setting status becomes available is the same as the setting value set in the setting status. This makes it possible to execute processing that corresponds to whether the setting values are the same across the setting status.

Feature S7. A gaming machine according to Feature S6, characterized in that it comprises means for issuing a notification that the setting value has not been changed, based on the setting value grasping means grasping that the setting value before the setting-enabled state is reached and the setting value set by the setting means are the same (a function for executing the processing of step S5113 in the main CPU 63 in the 22nd embodiment, and a function for executing the processing of step S5613 in the main CPU 63 in another embodiment).

According to feature S7, even if a setting becomes possible due to the erasure of information from the storage means, if the setting value remains the same between the setting possible state and the setting possible state, a notification is issued indicating that the setting value has not been changed. This makes it possible to notify the player that the setting value has not been changed even if a setting becomes possible during play, allowing the player to continue playing with peace of mind even if a setting becomes possible during play.

Feature S8. The situation generation means
a first status generating means for causing the setting possible status to be established based on the start of supply of operating power to the control means having the setting means (in the 22nd embodiment, a function for executing the processing of steps S5003 to S5006 in the main CPU 63; in another embodiment, a function for executing the processing of steps S5503 to S5507 in the main CPU 63; in the 23rd embodiment, a function for executing the processing of steps S5703 to S5705 and step S5715 in the main CPU 63);
a second situation generating means for causing the setting possible situation to occur based on the need to erase information from the storage means for storing the setting value after the supply of operating power to the control means has started (a function for executing the processing of steps S5401 to S5408 in the main CPU 63 in the 22nd embodiment, a function for executing the processing of steps S5801 to S5804 in the main CPU 63 in the 24th embodiment, and a function for executing the processing of steps S5901 to S5904 in the main CPU 63 in the 25th embodiment);
Equipped with
A gaming machine described in any one of features S1 to S7, characterized in that the setting value grasping means grasps whether the setting value before the settable situation occurs is the same as the setting value set by the setting means, regardless of whether the settable situation is caused by the first situation generating means or the second situation generating means.

According to feature S8, when it becomes necessary to erase information from the storage means that stores the setting values, a setting status is established, making it possible to prevent gameplay from continuing even though the setting value information has been erased. In this case, by using the same processing as when a setting status is established based on the start of the supply of operating power to the control means, when a setting status is established as a result of information from the storage means being erased, processing can be executed to determine whether the setting values are the same across the setting status.

In addition, with respect to the configuration of features S1 to S8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above group of features S can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, when a set value that determines the machine's advantage is set, it is necessary to create an optimal situation for that setting, and there is still room for improvement in this regard.

<Feature T group>
Feature T1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 25th embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the 15th to 25th embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
a first monitoring execution means for monitoring whether the first predetermined storage area is normal (in the 22nd embodiment, a function for executing the processing of steps S5401 to S5404 in the main CPU 63; in the 24th embodiment, a function for executing the processing of steps S5801 to S5804 in the main CPU 63; in the 25th embodiment, a function for executing the processing of steps S5901 to S5904 in the main CPU 63; and in the 32nd embodiment, a function for executing the processing of steps S7701 to S7703 in the main CPU 63);
a second monitoring execution means for monitoring whether the second predetermined storage area is normal (in the 22nd embodiment, a function for executing the processing of steps S5405 to S5408 in the main CPU 63; in the 24th embodiment, a function for executing the processing of steps S5809, S5810, S5812, and S5813 in the main CPU 63; in the 25th embodiment, a function for executing the processing of steps S6101, S6102, S6105, and S6106 in the main CPU 63; and in the 32nd embodiment, a function for executing the processing of steps S7706 to S7708 in the main CPU 63);
A gaming machine characterized by comprising:

According to Feature T1, a first predetermined storage area and a second predetermined storage area are provided, with the first predetermined storage area being treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area being treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destinations of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. Furthermore, by monitoring whether the first predetermined storage area is normal and monitoring whether the second predetermined storage area is normal, it becomes possible to determine whether the first and second predetermined processes can each be executed normally.

Feature T2. A gaming machine as described in Feature T1, wherein monitoring by the first monitoring execution means and monitoring by the second monitoring execution means are performed by either the first predetermined process or the second predetermined process.

According to feature T2, monitoring of whether the first specified storage area is normal and monitoring of whether the second specified storage area is normal are performed in one of the first specified process and the second specified process. This simplifies the processing configuration compared to a configuration in which monitoring of each storage area is performed in a distributed manner between the first specified process and the second specified process.

Feature T3. A gaming machine described in Feature T1 or T2, wherein monitoring by the first monitoring execution means and monitoring by the second monitoring execution means are performed by the first predetermined processing.

Feature T3 makes it possible to monitor whether the first specified storage area is normal and whether the second specified storage area is normal, all in one process.

Feature T4. A gaming machine according to any one of Features T1 to T3, characterized in that it is equipped with a predetermined erasure means (a function for executing the processing of step S5410 in the main CPU 63 in the 22nd embodiment; a function for executing the processing of steps S5806, S5811, and S5814 in the main CPU 63 in the 24th embodiment; a function for executing the processing of steps S5906, S6103, and S6107 in the main CPU 63) that erases information from the first predetermined storage area based on the first monitoring execution means identifying an abnormality in the first predetermined storage area.

According to feature T4, if the first specified storage area is abnormal, the information in the first specified storage area is erased, making it possible to prevent the first specified process from being executed while the first specified storage area remains abnormal.

Feature T5. The gaming machine described in Feature T4, wherein the predetermined erasure means erases information from the first predetermined memory area and erases information from the second predetermined memory area based on the first monitoring execution means identifying an abnormality in the first predetermined memory area.

According to feature T5, if the first specified storage area is abnormal, not only the first specified storage area but also the second specified storage area is erased. This makes it possible to erase information from the second specified storage area regardless of the monitoring results by the second monitoring execution means if there is a possibility that an abnormality has occurred in the second specified storage area.

Feature T6. A gaming machine as described in Feature T4 or T5, wherein the predetermined erasure means erases information from the second predetermined storage area based on the second monitoring execution means identifying an abnormality in the second predetermined storage area.

According to feature T6, if the first specified storage area is abnormal, the information in the first specified storage area is erased, thereby preventing the first specified process from being executed while the first specified storage area remains abnormal.

Feature T7. The gaming machine described in Feature T6, wherein the predetermined erasure means erases the information in the second predetermined memory area and erases the information in the first predetermined memory area based on the second monitoring execution means identifying an abnormality in the second predetermined memory area.

According to feature T7, if the second predetermined storage area is abnormal, not only the second predetermined storage area but also the first predetermined storage area is erased. This makes it possible to erase information from the first predetermined storage area regardless of the monitoring results by the first monitoring execution means if there is a possibility that an abnormality has occurred in the first predetermined storage area.

Feature T8. A gaming machine described in any one of Features T4 to T7, wherein the process for erasing information by the predetermined erasing means is executed by either the first predetermined process or the second predetermined process.

According to feature T8, the process of erasing information from each specified storage area based on the identification of an abnormality is executed in a centralized manner using either the first specified process or the second specified process. This simplifies the processing configuration compared to a configuration in which the erasure of information from each storage area is executed in a distributed manner using the first specified process and the second specified process.

Feature T9. A gaming machine described in any one of Features T4 to T7, wherein the process for erasing information by the predetermined erasing means is executed in the first predetermined process.

Feature T9 makes it possible to centrally execute the process of erasing information from each specified storage area based on the identification of an abnormality in the first specified process.

Feature T10. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine according to any one of features T1 to T9, wherein the second predetermined process includes a process for managing a gaming history.

According to feature T10, processing for controlling the progress of a game is executed as the first predetermined processing, and processing for managing the game history is executed as the second predetermined processing, thereby making it possible to prevent information used in the processing for managing the game history from being overwritten when the processing for controlling the progress of a game is executed.

Feature T11. A gaming machine as described in Feature T10, wherein the second predetermined memory area includes history memory areas (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which game history information corresponding to a predetermined event that occurs as a result of the execution of a game is stored.

According to feature T11, when a predetermined event occurs, corresponding history information is stored in the history memory area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, unauthorized access to or unauthorized modification of the history information can be prevented. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it becomes possible to prevent the information stored in the history memory area from being overwritten when the process for controlling the progress of a game is executed.

Feature T12. A gaming machine as described in Feature T11, wherein the second predetermined processing execution means is equipped with information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

Feature T12 enables the management results of gaming history, such as the frequency of occurrence of specified events, to be ascertained by deriving behavior information corresponding to gaming results over a specified period of time using history information stored in the history storage area.

Feature T13. A gaming machine as described in Feature T12, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature T13, when behavior information corresponding to game results over a predetermined period is derived using history information, that behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first predetermined process and a process for managing game history as the second predetermined process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

In addition, with respect to the configuration of features T1 to T13, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature U group>
Feature U1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a second predetermined processing among the various processing;
A state setting means for setting the state of a flag register provided in the internal storage means to a specific state when the state of executing the first predetermined processing changes to the state of executing the second predetermined processing or when the state of executing the second predetermined processing changes (in the 26th embodiment, a function for executing the processing of steps S6202 to S6204 and step S6211 in the main CPU 63; in the 27th embodiment, a function for executing the processing of steps S6302 to S6307 and step S6312 in the main CPU 63);
A gaming machine characterized by comprising:

According to feature U1, when the situation changes from one in which a first predetermined process is being executed to one in which a second predetermined process is being executed, or when the situation changes to one in which a second predetermined process is being executed, the state of the flag register in the internal storage means is set to a specific state. This makes it possible to start the second predetermined process when the state of the flag register is in a predetermined specific state. This makes it possible to perform various controls in an optimal manner.

Feature U2. A gaming machine according to Feature U1, wherein the specific state is a state in which the supply of operating power to the control means is initiated.

According to feature U2, the flag register is set to the specific state when the supply of operating power to the control means begins, which simplifies the processing configuration for setting the specific state.

Feature U3. A gaming machine according to Feature U1 or U2, wherein the specific state is a state in which the flag register is cleared to "0."

According to feature U3, the flag register is set to a cleared state of "0" as a specific state, which simplifies the processing configuration for setting the specific state.

Feature U4. A gaming machine described in any one of Features U1 to U3, characterized in that it is equipped with means for causing the state of the flag register to become the specific state when or after the second predetermined processing is completed (in the 26th embodiment, a function for executing the processing of steps S6213 to S6218 in the main CPU 63, and in the 27th embodiment, a function for executing the processing of steps S6314 to S6322 in the main CPU 63).

According to feature U4, the state of the flag register is set to a specific state not only when the state transitions from executing the first predetermined process to executing the second predetermined process or when the state transitions to executing the second predetermined process, but also when the second predetermined process is terminated or has been terminated. This makes it possible to resume the first predetermined process when the state of the flag register is in a predetermined specific state. It also makes it possible to set the state of the flag register to a specific state before and after the second predetermined process. This makes it possible to prevent the state of the flag register resulting from one of the first and second predetermined processes from affecting the other process.

Feature U5: A predetermined storage means (main RAM 65) is provided in which information is temporarily stored when processing is executed by the control means,
The state setting means
A means for changing the state of a predetermined storage area in the predetermined storage means to the specific state (in the 26th embodiment, a function for executing the processing of steps S6202 to S6204 in the main CPU 63, and in the 27th embodiment, a function for executing the processing of steps S6302 to S6307 in the main CPU 63);
A means for storing the information stored in the predetermined storage area in the flag register, thereby causing the state of the flag register to become the specific state (in the 26th embodiment, a function for executing the processing of step S6211 in the main CPU 63, and in the 27th embodiment, a function for executing the processing of step S6312 in the main CPU 63);
A gaming machine according to any one of features U1 to U4, characterized in that it is equipped with:

According to feature U5, even if the configuration does not allow the state of the flag register to be directly set to a specific state as a command from the control means, it is possible to set the state of the flag register to a specific state by writing information to a specified storage means and reading that information.

Feature U6. The predetermined storage means is
a stack area (a stack area 222 for specific control) into which the control means can write information in response to a push command and into which the control means can read information in response to a pop command;
a work area (a work area 221 for specific control) in which the control means can write and read information in response to a load command;
Equipped with
A gaming machine described in feature U5, characterized in that the specified memory area is provided in the stack area.

Feature U6 makes it possible to set the state of the flag register to a specific state by writing information to the stack area and reading that information, even in a configuration where information stored in the work area cannot be written directly to the flag register.

Feature U7. When the situation changes from the situation where the first predetermined process is being executed to the situation where the second predetermined process is being executed or when the situation where the second predetermined process is being executed is reached, a means for causing the state of a predetermined register provided in the internal storage means to become a predetermined state (in the 26th embodiment, a function for executing the processes of steps S6205 to S6210 in the main CPU 63, and in the 27th embodiment, a function for executing the processes of steps S6308 to S6311 in the main CPU 63),
A gaming machine described in any one of features U1 to U6, characterized in that the state setting means sets the state of the flag register to the specific state after the state of the specified register is set to the specified state.

The state of the flag register can change each time various processes are executed by the control means. In this case, according to feature U7, the state of the flag register is set to a specific state after the state of the specified register is set to a specific state, making it possible to ensure that the flag register is in the specific state immediately before the second specified process is started.

Feature U8. The device is provided with a control unit (main CPU 63) that executes various processes and temporarily stores information in an internal storage unit (register of the main CPU 63) when the processes are executed,
The control means is a gaming machine characterized by having a means for causing the state of the flag register to become a specific state (in the 26th embodiment, a function for executing the processing of steps S6202 to S6204 and step S6211 in the main CPU 63, and in the 27th embodiment, a function for executing the processing of steps S6302 to S6307 and step S6312 in the main CPU 63).

Feature U8 makes it possible to set the state of the flag register to a specific state as needed.

In addition, with respect to the configuration of features U1 to U8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group V>
Feature V1. Equipped with a control means (main CPU 63) that executes various processes and temporarily stores information in an internal storage means (register of the main CPU 63) when executing the processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a second predetermined processing among the various processing;
a save execution means for saving information of a flag register provided in the internal storage means to a predetermined storage means (main RAM 65) when the state where the first predetermined processing is being executed changes to the state where the second predetermined processing is being executed or when the state where the second predetermined processing is being executed is reached (a function for executing the processing of step S3802 in the main CPU 63 in the 15th embodiment, a function for executing the processing of step S4402 in the main CPU 63 in the 16th embodiment, a function for executing the processing of step S4802 in the main CPU 63 in the 20th embodiment, a function for executing the processing of steps S6402 to S6405 in the main CPU 63 in the 28th embodiment, and a function for executing the processing of steps S6502 to S6509 in the main CPU 63 in the 29th embodiment);
a restoration execution means for restoring the information of the flag register saved in the predetermined storage means to the flag register when or after the second predetermined processing is completed (a function for executing the processing of step S3804 in the main CPU 63 in the 15th embodiment, a function for executing the processing of step S4404 in the main CPU 63 in the 16th embodiment, a function for executing the processing of step S4810 in the main CPU 63 in the 20th embodiment, a function for executing the processing of steps S6407 to S6415 in the main CPU 63 in the 28th embodiment, and a function for executing the processing of steps S6511 to S6518 in the main CPU 63 in the 29th embodiment);
A gaming machine characterized by comprising:

According to feature V1, when the situation changes from one in which the first predetermined process is being executed to one in which the second predetermined process is being executed, or when the situation changes to one in which the second predetermined process is being executed, the information in the flag register is saved to a predetermined storage means. This makes it possible to prevent the information stored in the flag register from being overwritten when the first predetermined process is executed when the second predetermined process is executed. Furthermore, when or after the second predetermined process is completed, the information saved in the predetermined storage means is restored to the flag register. This makes it possible to execute a process different from the second predetermined process when the second predetermined process is completed, based on the state of the flag register before the second predetermined process was executed. As a result, various controls can be performed optimally.

Feature V2. The predetermined storage means is
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine described in feature V1 is characterized in that the save execution means saves the information of the flag register to the first predetermined memory area.

According to Feature V2, by providing the predetermined storage means with a first predetermined storage area and a second predetermined storage area, it is possible to clearly differentiate the storage destination of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first predetermined process and the second predetermined process from being erased when the other process is executed. In this case, when the situation changes from executing the first predetermined process to executing the second predetermined process, or when the situation changes to executing the second predetermined process, the information in the flag register is saved to the first predetermined storage area. This makes it possible to save the information in the flag register immediately before the second predetermined process is started, and to save that information without using the second predetermined storage area.

Feature V3. The first predetermined storage area is capable of storing and reading information when the first predetermined process is executed, and is capable of reading information but is not capable of storing information when the second predetermined process is executed;
A gaming machine described in feature V2, characterized in that the second specified memory area is capable of storing information and reading information when the second specified process is executed, and is capable of reading information but is unable to store information when the first specified process is executed.

Feature V3 makes it possible to treat the first specified storage area as a storage area dedicated to the first specified process, and to treat the second specified storage area as a storage area dedicated to the second specified process.

Feature V4. The predetermined storage means is
a stack area (a stack area 222 for specific control) in which information can be written by a push command and in which information can be read by a pop command;
a work area (a work area 221 for specific control) in which information can be written and read by a load command;
Equipped with
A gaming machine described in any one of features V1 to V3, wherein the save execution means saves the information of the flag register to one of the stack area and the work area.

According to Feature V4, when the situation changes from executing a first predetermined process to executing a second predetermined process, or when the situation changes to executing a second predetermined process, the information in the flag register is saved to either the stack area or the work area in the second predetermined storage area. This makes it possible to consolidate the destinations for saving information and simplify the processing configuration for saving and restoring.

Feature V5. The gaming machine described in Feature V4, wherein the save execution means saves the information in the flag register to the work area.

With feature V5, the flag register information is saved to the work area, making it possible to save that information without making cumulative changes to the stack pointer.

Feature V6: The saving execution means
A means for storing information of the flag register in a predetermined register provided in the internal storage means (a function for executing the processes of steps S6402 and S6403 in the main CPU 63 in the 28th embodiment, and a function for executing the processes of steps S6502 to S6505 in the main CPU 63 in the 29th embodiment);
A means for storing the information of the flag register stored in the predetermined register in the predetermined storage means (a function for executing the processing of step S6404 in the main CPU 63 in the 28th embodiment, and a function for executing the processing of step S6506 in the main CPU 63 in the 29th embodiment);
A gaming machine according to any one of features V1 to V5, characterized in that it is equipped with:

According to Feature V6, even if the configuration does not allow the information in the flag register to be directly saved to the specified storage means as an instruction from the control means, it is possible to save the information in the flag register to the specified storage means by writing information to the specified register and writing the information stored in the specified register to the specified storage means.

In addition, with respect to the configuration of features V1 to V6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature W group>
Feature W1. Equipped with a control means (main CPU 63) that executes various processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
An abnormal event monitoring means (program monitoring unit 252) for monitoring whether an abnormal event has occurred;
an erasure status generating means (a reset signal output unit 251) that generates a status in which an information erasure process is executed on at least the first predetermined storage area based on the abnormal event being identified by the abnormal event monitoring means;
A gaming machine characterized by comprising:

According to Feature W1, a first predetermined storage area and a second predetermined storage area are provided, with the first predetermined storage area treated as a storage area dedicated to the first predetermined process and the second predetermined storage area treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destinations of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. Furthermore, upon identifying that an abnormal event has occurred, an information erasure process is executed on at least the first predetermined storage area. This makes it possible to prevent the first predetermined process from being executed with the information in the first predetermined storage area remaining intact, despite the occurrence of an abnormal event.

Feature W2. The control means
A means for executing a process to store power outage response information when the supply of operating power to the control means is stopped (a function for executing the processes of steps S6709 and S6710 in the main CPU 63 in the 30th embodiment, and a function for executing the processes of steps S7609 to S7611 in the main CPU 63 in the 32nd embodiment);
When the supply of operating power to the control means is started and processing at the start of supply is executed in a situation where the power outage response information is not stored, a means for erasing the information is executed at least for the first predetermined storage area (in the 30th embodiment, a function for executing processing of step S6607 in the main CPU 63; in the 31st embodiment, a function for executing clear processing in the event of an abnormality in the main CPU 63; in the 32nd embodiment, a function for executing processing of steps S7704, S7705, S7808 and S7810 in the main CPU 63);
Equipped with
The gaming machine described in feature W1 is characterized in that the erasure status generation means causes the control means to execute the processing at the start of supply in a situation where the power outage response information is not stored, based on the abnormal event monitoring means identifying that the abnormal event has occurred.

According to feature W2, when the supply of operating power to the control means is initiated and supply start processing is executed in a situation where power outage response information is not stored, an information deletion process is executed on at least the first predetermined storage area. This makes it possible to prevent the first predetermined processing from being executed with the information in the first predetermined storage area retained when the supply of operating power to the control means is initiated in a situation where power outage processing is not being performed appropriately. In this case, based on the identification of the occurrence of an abnormal event, the control means executes supply start processing in a situation where power outage response information is not stored. This makes it possible to execute information deletion processing in response to the occurrence of an abnormal event by utilizing a configuration that executes information deletion processing when supply start processing is executed by the control means in a situation where power outage response information is not stored.

Feature W3. The control means executes various processes when a reset signal is received, and starts the process at the start of supply when a change occurs from a state in which the reset signal is not received to a state in which the reset signal is received while operating power is being supplied,
The gaming machine described in feature W2 is characterized in that the erasure status generation means, based on the abnormal event monitoring means identifying that the abnormal event has occurred, causes the control means to create a situation in which the reset signal is not received and then creates a situation in which the control means receives the reset signal.

Feature W3 makes it possible to achieve the excellent effects described above by switching the reception state of the reset signal.

Feature W4. The control means is configured to temporarily store information in an internal storage means (a register and a program counter of the main CPU 63) when executing a process, and is configured to temporarily save the information stored in the internal storage means to the first predetermined storage area,
the abnormal event monitoring means monitors whether or not an abnormality has occurred in the information stored in the internal storage means as the abnormal event;
A gaming machine described in any one of features W1 to W3, characterized in that the erasure status generation means generates a situation in which the information erasure process is executed on at least both the first specified memory area and the internal memory means.

According to feature W4, the information stored in the internal storage means can be temporarily saved to the first predetermined storage area. Therefore, if an abnormality occurs with the information stored in the internal storage means, there is a possibility that an abnormality also occurs with the information stored in the first predetermined storage area. In this case, if an abnormality occurs with the information stored in the internal storage means, an information deletion process is executed not only on the internal storage means but also on the first predetermined storage area. This makes it possible to prevent the first predetermined process from being executed in an unaffected state, even if an abnormality has occurred with the information stored in the first predetermined storage area.

Feature W5. A gaming machine described in any one of Features W1 to W4, wherein the erasure status generation means prevents the information erasure process from being executed on the second predetermined storage area even if the abnormal event monitoring means identifies that the abnormal event has occurred.

Feature W5 makes it possible to store and retain information in the second specified storage area even if an abnormal event occurs.

Feature W6. A gaming machine described in any one of Features W1 to W4, wherein the erasure status generation means generates a situation in which the information erasure process is executed on both the first predetermined storage area and the second predetermined storage area based on the abnormal event monitoring means identifying the occurrence of the abnormal event.

According to feature W6, upon identifying that an abnormal event has occurred, information erasure processing is performed on both the first and second specified storage areas. This makes it possible to prevent the first specified processing from being executed while the information in the first specified storage area is still retained, even though an abnormal event has occurred, and it also makes it possible to prevent the second specified processing from being executed while the information in the second specified storage area is still retained, even though an abnormal event has occurred.

Feature W7. A gaming machine as described in Feature W6, characterized in that the process of erasing the information from the first predetermined storage area is executed by the first predetermined process, and the process of erasing the information from the second predetermined storage area is executed by the second predetermined process.

Feature W7 makes it possible to treat the first specified storage area as a storage area dedicated to the first specified processing, and the second specified storage area as a storage area dedicated to the second specified processing, even when erasing information.

Feature W8. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine described in any one of features W1 to W7, wherein the second predetermined process includes a process for managing gaming history.

According to feature W8, processing for controlling the progress of a game is executed as the first predetermined processing, and processing for managing the game history is executed as the second predetermined processing, making it possible to prevent information used in the processing for managing the game history from being overwritten when the processing for controlling the progress of a game is executed.

Feature W9. A gaming machine as described in Feature W8, wherein the second predetermined memory area includes history memory areas (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which game history information corresponding to a predetermined event that occurs as a result of the execution of a game is stored.

According to feature W9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, by storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten when the process for controlling the progress of a game is executed.

Feature W10. A gaming machine as described in Feature W9, wherein the second predetermined processing execution means includes information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

Feature W10 allows the history information stored in the history storage area to be used to derive behavior information corresponding to game results over a specified period, making it possible to ascertain the results of game history management, such as the frequency of occurrence of specified events.

Feature W11. A gaming machine as described in Feature W10, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature W11, when behavior information corresponding to game results over a specified period is derived using history information, that behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first specified process and a process for managing game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

In addition, with respect to the configuration of features W1 to W11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature X group>
Feature X1. Equipped with a control means (main CPU 63) that executes various processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
Equipped with
The gaming machine is characterized in that the second predetermined processing execution means is equipped with an erasure execution means that, based on the occurrence of an erasure trigger, causes an information erasure process to be executed on the second predetermined memory area as the second predetermined processing (in the 25th embodiment, a function of executing the processes of steps S6103 and S6107 in the main CPU 63; in the 30th embodiment, a function of executing the process of step S7204 in the main CPU 63; in the 31st embodiment, a function of executing the process of step S7508 in the main CPU 63; and in the 32nd embodiment, a function of executing the processes of steps S7808 and S7810 in the main CPU 63).

According to Feature X1, a first predetermined storage area and a second predetermined storage area are provided, with the first predetermined storage area being treated as a storage area dedicated to the first predetermined process, and the second predetermined storage area being treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destinations of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in the first predetermined process or the second predetermined process from being erased when the other process is executed.

In addition, when an erasure trigger occurs, an information erasure process is executed on the second specified storage area, so it is possible to prevent the second specified processing from being executed in a state where the information in the second specified storage area is retained as is, even if some abnormality has occurred in the second specified storage area. Furthermore, because the information erasure process is executed by the second specified processing, it is possible to prevent the first specified processing from intervening in the update of the information in the second specified storage area.

Feature X2. A gaming machine as described in Feature X1, wherein the erasure execution means executes the information erasure process for the second predetermined memory area while preventing information not to be erased (management monitoring flags, return address information, and information in various registers) from being erased.

According to Feature X2, the process of erasing information from the second specified storage area is performed while preventing the erasure of information that is not to be erased from the second specified storage area. This makes it possible to perform the process of erasing information from the second specified storage area while preventing the erasure of necessary information.

Feature X3. The second predetermined processing execution means is provided with a storage execution means (a function for executing steps S7102 to S7107 in the main CPU 63 in the 30th embodiment, a function for executing steps S7502 to S7507 in the main CPU 63 in the 31st embodiment, and a function for executing steps S7802 to S7807 in the main CPU 63 in the 32nd embodiment) that stores return correspondence information (return address information, various register information) required when returning to a situation in which the first predetermined processing is executed when the situation changes from a situation in which the first predetermined processing is executed to a situation in which the second predetermined processing is executed or when the situation in which the second predetermined processing is executed is reached) in the second predetermined storage area,
The gaming machine described in feature X2 is characterized in that the erasure execution means executes the information erasure process on the second specified memory area while preventing the return correspondence information from being erased as the non-erasure target information.

Feature X3 makes it possible to perform information deletion processing for the second specified storage area while preventing the erasure of the return correspondence information required when returning from a situation in which the second specified processing is being executed to a situation in which the first specified processing is being executed.

Feature X4. The gaming machine described in Feature X3, wherein the storage and execution means stores, as the return correspondence information, information on the return address of the program when the second predetermined processing is terminated and the first predetermined processing is returned to, in the second predetermined storage area.

According to feature X4, when returning to the first predetermined processing, the information erasure process is performed on the second predetermined storage area while preventing the program's return address information from being erased. Therefore, even if the information erasure process is performed on the second predetermined storage area, it is possible to return to the predetermined program in the first predetermined processing when the second predetermined processing is completed.

Feature X5. The control means is configured to temporarily store information in an internal storage means (a register of the main CPU 63) when executing processing,
The gaming machine according to feature X3 or X4, wherein the storage execution means stores the information stored in the internal storage means as the return correspondence information in the second predetermined storage area.

According to feature X5, the information erasure process is performed on the second specified storage area while preventing the information in the internal storage means used in the first specified processing from being erased. Therefore, even if the information erasure process is performed on the second specified storage area, the information used in the first specified processing can be restored to the internal storage means when the second specified processing is completed.

Feature X6. A gaming machine described in any one of Features X1 to X5, wherein the erasure execution means executes the information erasure process on the second specified storage area when an abnormality occurs in the second specified storage area, as the erasure trigger.

Feature X6 allows an information erasure process to be performed on the second specified storage area when an abnormality occurs in the second specified storage area, thereby preventing the second specified process from being performed while an abnormality remains in the second specified storage area.

Feature X7. A gaming machine according to Feature X6, wherein the second predetermined processing execution means includes, as the second predetermined processing, a means for monitoring whether the second predetermined storage area is normal (in the 30th embodiment, a function for executing the processing of steps S7201 to S7203 in the main CPU 63).

According to feature X7, not only is the information erasure process for the second specified storage area performed in the second specified processing, but monitoring of whether the second specified storage area is normal is also performed in the second specified processing without the intervention of the first specified processing. This makes it possible to perform monitoring of whether the second specified storage area is normal and the information erasure process for the second specified storage area as a series of processes in the second specified processing.

Feature X8. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine according to any one of features X1 to X7, wherein the second predetermined process includes a process for managing a gaming history.

According to feature X8, processing for controlling the progress of a game is executed as the first predetermined processing, and processing for managing the game history is executed as the second predetermined processing, thereby making it possible to prevent information used in the processing for managing the game history from being overwritten when the processing for controlling the progress of a game is executed.

Feature X9. A gaming machine as described in Feature X8, wherein the second predetermined memory area includes history memory areas (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which game history information corresponding to a predetermined event that occurs as a result of the execution of a game is stored.

According to feature X9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten when the process for controlling the progress of a game is executed.

Feature X10. A gaming machine as described in Feature X9, wherein the second predetermined processing execution means includes information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

Feature X10 allows the history information stored in the history storage area to be used to derive behavior information corresponding to game results over a specified period, making it possible to ascertain the results of game history management, such as the frequency of occurrence of specified events.

Feature X11. The gaming machine described in Feature X10, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to feature X11, when behavior information corresponding to game results over a specified period is derived using history information, that behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first specified process and a process for managing game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

In addition, with respect to the configuration of features X1 to X11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Characteristic Group Y>
Feature Y1: Equipped with a control means (main CPU 63) that executes various processes,
The control means
A first predetermined processing execution means (a function of executing processing other than the management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a first predetermined processing among the various processing;
A second predetermined processing execution means (a function of executing management execution processing in the main CPU 63 in the 15th to 34th embodiments) that executes a second predetermined processing among the various processing;
a first predetermined storage area (a work area 221 for specific control, a stack area 222 for specific control) in which information is stored when the first predetermined process is executed;
a second predetermined storage area (a work area 223 for non-specific control, a stack area 224 for non-specific control) in which information is stored when the second predetermined process is executed;
a first calculation means for calculating first reference numerical information corresponding to the plurality of pieces of information stored in the first predetermined storage area (a function for executing the processing of steps S6604 and S6710 in the main CPU 63 in the 30th embodiment, a function for executing the processing of step S7304 in the main CPU 63 in the 31st embodiment, and a function for executing the processing of steps S7610 and S7701 in the main CPU 63 in the 32nd embodiment);
A gaming machine characterized by comprising:

According to Feature Y1, a first predetermined storage area and a second predetermined storage area are provided, with the first predetermined storage area treated as a storage area dedicated to the first predetermined process and the second predetermined storage area treated as a storage area dedicated to the second predetermined process. This makes it possible to clearly differentiate the storage destinations of information in the predetermined storage means for the first predetermined process and the second predetermined process. This makes it possible to prevent information used in one of the first and second predetermined processes from being erased when the other process is executed. In this case, first reference numerical information corresponding to the multiple pieces of information stored in the first predetermined storage area is calculated. By using this first reference numerical information, it becomes possible to determine whether an information anomaly has occurred in only the first predetermined storage area.

Feature Y2. A gaming machine according to Feature Y1, characterized in that it is equipped with information erasure means (a function for executing the processing of step S6607 in the main CPU 63 in the 30th embodiment, a function for executing the processing of steps S7401 and S7402 in the main CPU 63 in the 31st embodiment, and a function for executing the processing of steps S7704 and S7705 in the main CPU 63) that causes information erasure processing to be executed on the first predetermined memory area based on the identification of the occurrence of an abnormality in the first reference numerical information calculated by the first calculation means.

According to feature Y2, if an abnormality is identified in the first reference numerical information, an information erasure process is performed on the first specified storage area, thereby preventing the first specified process from being performed while the information in the first specified storage area is retained as is, even if an information abnormality has occurred.

Feature Y3. The first calculation means
A first power outage calculation means (a function for executing the processing of step S6710 in the main CPU 63 in the 30th embodiment, and a function for executing the processing of step S7610 in the main CPU 63 in the 32nd embodiment) that calculates the first reference numerical information when the supply of operating power to the control means is stopped;
a first power-on time calculation means for calculating the first reference numerical information when the supply of operating power to the control means is started (a function for executing the processing of step S6604 in the main CPU 63 in the 30th embodiment, a function for executing the processing of step S7304 in the main CPU 63 in the 31st embodiment, and a function for executing the processing of step S7701 in the main CPU 63 in the 32nd embodiment);
Equipped with
The gaming machine described in feature Y2 is characterized in that the information erasure means performs the information erasure process on at least the first specified memory area based on the fact that the first reference numerical information calculated by the first power outage calculation means does not match the first reference numerical information calculated by the first power in calculation means.

According to feature Y3, it is possible to determine whether information in the first predetermined storage area is stored across a situation in which the supply of operating power is stopped by calculating the first reference numerical information. If information in the first predetermined storage area is not stored across a situation in which the supply of operating power is stopped, an information deletion process is performed on the first predetermined storage area, making it possible to prevent the first predetermined process from being executed while the information in the first predetermined storage area remains intact despite the occurrence of an information anomaly.

Feature Y4. A gaming machine described in Feature Y2 or Y3, wherein the information erasing means does not execute the information erasing process for the second predetermined memory area even if it identifies the occurrence of an abnormality in the first reference numerical information calculated by the first calculation means.

According to feature Y4, when an abnormality is identified in the first reference numerical information, an information erasure process is performed on the first specified storage area, but an information erasure process is not performed on the second specified storage area. This makes it possible to prevent information in the second specified storage area from being erased when an information abnormality occurs in the first specified storage area.

Feature Y5. A gaming machine described in any one of Features Y1 to Y4, characterized in that the first reference numerical information is information that does not change depending on the information stored in the second predetermined memory area.

Feature Y5 enables, in a configuration in which a first predetermined storage area and a second predetermined storage area exist, information anomalies relating to the first predetermined storage area to be individually identified using the first reference numerical information.

Feature Y6. A gaming machine described in any one of Features Y1 to Y5, characterized in that it is equipped with second calculation means (a function for executing the processing of steps S7611 and S7706 in the main CPU 63) that calculates second reference numerical information corresponding to the multiple pieces of information stored in the second predetermined memory area.

According to feature Y6, second reference numerical information corresponding to multiple pieces of information stored in a second specified storage area is calculated. By using this second reference numerical information, it is possible to determine whether an information anomaly has occurred in only the second specified storage area.

Feature Y7. A gaming machine as described in Feature Y6, characterized in that it is equipped with a means (a function for executing the processing of steps S7808 and S7810 in the main CPU 63) for causing an information erasure process to be performed on at least the second specified memory area based on the identification of an abnormality in the second reference numerical information calculated by the second calculation means.

According to feature Y7, if an abnormality is identified in the second reference numerical information, an information erasure process is performed on the second specified storage area, thereby preventing the second specified process from being performed while the information in the second specified storage area is retained as is, even if an information abnormality has occurred.

Feature Y8. The first predetermined process includes a process for controlling the progress of a game,
A gaming machine described in any one of features Y1 to Y7, characterized in that the second predetermined process includes a process for managing gaming history.

According to feature Y8, processing for controlling the progress of a game is executed as the first predetermined processing, and processing for managing the game history is executed as the second predetermined processing, thereby making it possible to prevent information used in the processing for managing the game history from being overwritten when the processing for controlling the progress of a game is executed.

Feature Y9. A gaming machine as described in Feature Y8, wherein the second predetermined memory area includes history memory areas (normal counter area 231, open/close execution mode counter area 232, high-frequency support mode counter area 233) in which game history information corresponding to a predetermined event that occurs as a result of the execution of a game is stored.

According to feature Y9, when a predetermined event occurs, corresponding history information is stored in the history storage area. This allows the gaming machine to store and retain information for managing the number of times or frequency of occurrence of a predetermined event, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of a predetermined event. Furthermore, since the history information is stored in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, by executing a process for controlling the progress of a game as the first predetermined process and a process for managing the game history as the second predetermined process, it is possible to prevent the information stored in the history storage area from being overwritten when the process for controlling the progress of a game is executed.

Feature Y10. A gaming machine according to Feature Y9, wherein the second predetermined processing execution means includes information derivation means (a function for executing the processing of step S4208 in the main CPU 63) that uses the history information stored in the history storage area to derive behavior information corresponding to game results over a predetermined period of time.

According to Feature Y10, by using the history information stored in the history storage area to derive behavior information corresponding to game results over a specified period, it becomes possible to ascertain the results of game history management, such as the frequency of occurrence of specified events.

Feature Y11. A gaming machine as described in Feature Y10, wherein the second predetermined storage area includes a mode information storage area (computation result storage area 234) that stores the mode information derived by the information derivation means.

According to Feature Y11, when behavior information corresponding to game results over a specified period is derived using history information, that behavior information is stored in a behavior information storage area. This makes it possible to grasp the results of game history management at any time. Furthermore, by executing a process for controlling game progress as the first specified process and a process for managing game history as the second specified process, it becomes possible to prevent the information stored in the behavior information storage area from being overwritten when the process for controlling game progress is executed.

In addition, with respect to the configuration of features Y1 to Y11, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group T, feature group U, feature group V, feature group W, feature group X, and feature group Y can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

However, gaming machines such as those exemplified above require various controls to be performed appropriately, and there is still room for improvement in this regard.

<Feature Z group>
Feature Z1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A situation generating means (a function of executing the processes of steps S7905, S7916, and S7917 in the main CPU 63) that causes a setting possible situation in which the setting value to be used can be changed;
When the supply of operating power to the control means (main CPU 63) having the setting means is started and processing at the start of supply is being executed, a setting notification means (a function for executing a setting confirmation process in the main CPU 63) is configured to notify the setting value of the target to be used in a situation where the setting is not possible;
A gaming machine characterized by comprising:

According to Feature Z1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will hope that the more advantageous setting value will be the one to be used. In this case, to check the setting value that is set to be used, it is necessary to temporarily stop the supply of operating power to the control means and then restart the supply of operating power to the control means. This makes it difficult to fraudulently check the setting value. Furthermore, because the setting value is notified while processing is being executed at the start of supply, there is no need to notify the setting value when play is interrupted. This makes it possible to preferably notify the setting value.

Feature Z2. The gaming machine described in Feature Z1, wherein the situation generation means causes the settable situation to occur when the supply start processing is being executed.

Feature Z2 makes it possible to combine the setting availability situation in which the target setting value can be set and the situation in which the target setting value is not settable but is notified, into the situation in which processing is being performed at the start of supply.

Feature Z3. A first identification means (a function of executing the processes of step S7912 and step S7916 in the main CPU 63) is provided to identify the occurrence of a first trigger event,
The gaming machine described in feature Z1 or Z2 is characterized in that the setting notification means notifies the setting value of the target to be used in a situation where the setting is not possible, based on the situation where the processing at the start of supply is being executed and the occurrence of the first trigger event has been identified by the first identification means.

According to Feature Z3, in order to notify the setting value of the device being used, it is necessary not only to start the supply of operating power to the control means but also to cause a first trigger event to occur. This makes it difficult to fraudulently check the setting value.

Feature Z4. A gaming machine as described in Feature Z3, wherein the first trigger event is a predetermined operation using a setting key in the setting key insertion section (setting key insertion section 68a).

According to feature Z4, in order to notify the settings of the device being used, a specific operation using the setting key in the setting key insertion section must be performed. This makes it difficult to fraudulently check the setting values.

Feature Z5. The setting notification means notifies the setting value of the target to be used in the situation where the setting is not possible when a notification condition is met based on the situation where the supply start processing is being executed and the occurrence of the first trigger event is identified by the first identification means,
the situation generating means sets the setting possible situation when a setting condition is met based on the situation in which the supply start processing is being executed and the occurrence of the first trigger event is identified by the first identifying means,
A gaming machine described in feature Z3 or Z4, characterized in that the notification condition and the set condition are different.

According to feature Z5, in both cases of generating a setting possible state and reporting the setting value of the target device, it is necessary not only to start the supply of operating power to the control means but also to generate a first trigger event. This makes it difficult to fraudulently set the setting value of the target device or fraudulently check the setting value of the target device. On the other hand, because the setting conditions for generating a setting possible state and the reporting conditions for reporting the setting value of the target device are different, it is possible to independently generate either the setting possible state or a state in which the setting value of the target device is reported.

Feature Z6. A second identification means (a function for executing the processing of step S7905 in the main CPU 63) for identifying the occurrence of a second trigger event is provided,
the set condition is satisfied based on the situation in which, in a situation in which the supply start processing is being executed, the occurrence of the first triggering event is identified by the first identification means and the occurrence of the second triggering event is identified by the second identification means;
The gaming machine described in feature Z5 is characterized in that the notification condition is met based on the situation in which, when the processing at the start of supply is being executed, the occurrence of the first triggering event is identified by the first identification means and the occurrence of the second triggering event is not identified by the second identification means.

According to feature Z6, in order to create a setting possible state, it is necessary to start the supply of operating power to the control means and not only cause the first trigger event to occur but also cause the second trigger event to occur. This makes it possible to further complicate the operation for creating a setting possible state in a configuration where not only the supply of operating power to the control means but also the first trigger event must occur, whether the setting value to be used is to be set or the setting value to be notified. This makes it possible to more effectively prevent attempts to fraudulently set the setting value to be used.

Feature Z7. A gaming machine described in Feature Z6, wherein the second trigger event is the operation of a predetermined operation means (reset button 68c).

According to feature Z7, in order to generate a setting enable state, it is necessary not only to start the supply of operating power to the control means and generate a first trigger event, but also to operate a specified operating means. This makes it difficult to fraudulently set the setting value to be used, while also preventing the operations required to legitimately generate a setting enable state from becoming overly complicated.

Feature Z8. A gaming machine as described in Feature Z6 or Z7, characterized in that it is equipped with information erasing means (a function for executing the processing of step S7915 in the main CPU 63) that executes information erasing processing based on the situation in which the occurrence of the second trigger event is identified by the second identification means while the processing at the start of supply is being executed.

Feature Z8 makes it possible to differentiate between the conditions for generating a setting possible state and the conditions for notifying the setting value to be used in a state where setting is not possible, by utilizing the second trigger event required to execute the information erasure process.

Feature Z9. The gaming machine described in Feature Z8, wherein the information erasing means executes the information erasing process even when the setting possible situation occurs.

Feature Z9 makes it possible to execute information erasure processing when the setting becomes possible.

Feature Z10. A gaming machine as described in Feature Z8 or Z9, characterized in that if, during the execution of the supply start processing, the second identification means identifies the occurrence of the second triggering event, but the first identification means does not identify the occurrence of the first triggering event, the setting-enabled situation is not met, but the information erasure process is executed by the information erasure means.

According to feature Z10, depending on whether or not a first trigger event occurs when the supply of operating power to the control means is initiated, it is possible to select between a case in which the information erasure process is executed and the setting becomes possible, and a case in which the information erasure process is executed but the setting does not become possible.

In addition, with respect to the configuration of features Z1 to Z10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature group a>
Feature a1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
A situation generating means (a function of executing the processes of steps S7905, S7916, and S7917 in the main CPU 63) that causes a setting possible situation in which the setting value to be used can be changed;
An information erasing means for executing information erasing processing (a function for executing the processing of step S7915 in the main CPU 63);
A setting notification means (a function for executing a setting confirmation process in the main CPU 63) that notifies the setting value of the target to be used in a situation where the setting is not possible;
A first identification means (a function of executing the processes of step S7912 and step S7916 in the main CPU 63) that identifies the occurrence of a first trigger event;
A second identification means (a function of executing the processing of step S7905 in the main CPU 63) that identifies the occurrence of a second trigger event;
Equipped with
the situation generating means brings about the settable situation based on a situation in which the first specifying means specifies the occurrence of the first triggering event and the second specifying means specifies the occurrence of the second triggering event in a situation in which supply of operating power to the control means having the setting means has started and processing at the start of supply is being executed,
the information erasing means executes the information erasing process based on the situation in which the occurrence of the second trigger event is identified by the second identification means while the supply start process is being executed, and
In a situation where the supply start processing is being executed, if the occurrence of the second trigger event is specified by the second specifying means and the occurrence of the first trigger event is not specified by the first specifying means, the setting is not possible, but the information erasing processing is executed by the information erasing means,
The setting notification means of the gaming machine is characterized in that it notifies the setting value of the object to be used in a situation where the setting is not possible, based on the situation where the first identification means identifies the occurrence of the first trigger event when the processing at the start of supply is being executed, and the second identification means does not identify the occurrence of the second trigger event.

According to feature a1, the setting value to be used is set from multiple setting values corresponding to the player's level of advantage, so the player will hope that the more advantageous setting value will be the one to be used. Furthermore, because the system is configured to be able to execute an information erasure process, it is possible to prevent play from being carried out even when an information anomaly has occurred. Furthermore, because the system is configured to be able to notify the setting value to be used, it is possible to check the setting value.

In this case, in order to check the setting value set for use, it is necessary to start the supply of operating power to the control means and cause the first trigger event to occur. This makes it difficult to fraudulently check the setting value.

Furthermore, in order to create a setting possible state, it is necessary to start the supply of operating power to the control means and not only cause the first trigger event to occur but also cause the second trigger event to occur. This makes it possible to further complicate the operation for creating a setting possible state, in a configuration where not only the supply of operating power to the control means but also the first trigger event must occur, whether the setting value to be used is to be set or the setting value to be notified. This makes it possible to more effectively prevent attempts to fraudulently set the setting value to be used.

In addition, by utilizing the second trigger event required to execute the information erasure process, it is possible to differentiate the conditions for generating a setting possible state from the conditions for notifying the setting value to be used in a state where setting is not possible.

In addition, depending on whether or not the first trigger event occurs when the supply of operating power to the control means begins, it is possible to select between a case in which the information erasure process is executed and the setting becomes possible, and a case in which the information erasure process is executed but the setting does not become possible.

Feature a2. A gaming machine as described in Feature a1, wherein the first triggering event is a predetermined operation being performed using a setting key in the setting key insertion section (setting key insertion section 68a).

According to feature a2, in order to notify the settings of the device being used, a specific operation using the setting key in the setting key insertion section must be performed. This makes it difficult to fraudulently check the setting values.

Feature a3. A gaming machine as described in Feature a1 or a2, wherein the second triggering event is the operation of a predetermined operation means (reset button 68c).

According to feature a3, in order to create a setting possible state, it is necessary not only to start the supply of operating power to the control means and cause the first trigger event, but also to operate the specified operating means. This makes it difficult to fraudulently set the setting value to be used, while also preventing the operations required to legitimately create a setting possible state from becoming overly complicated.

In addition, with respect to the configuration of features a1 to a3, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned feature group Z and feature group A can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above require a configuration that allows for efficient confirmation of the setting values that determine the machine's advantageous position, and there is still room for improvement in this regard.

<Feature group b>
Feature b1. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
A situation generating means (a function of executing the processes of steps S7905, S7916, and S7917 in the main CPU 63) that causes a setting possible situation in which the setting value to be used can be changed;
A setting monitoring means (a function for executing the processing of step S8220 in the main CPU 63) for executing a setting monitoring process to monitor whether the setting value of the target to be used is abnormal;
Equipped with
A gaming machine characterized in that the setting monitoring process is not included in the supply start process that is executed when the supply of operating power to a control means having the setting means is started.

According to feature b1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be the one to be used. In addition, a setting monitoring process is executed to monitor whether the setting value to be used is abnormal, so if the setting value to be used is abnormal, it can be addressed. Furthermore, because the setting monitoring process is not included in the processing at the start of supply, it is possible to achieve the excellent effects described above without increasing the processing load of the processing at the start of supply.

Feature b2. The gaming machine described in Feature b1, wherein the situation generation means generates the settable situation when the supply start processing is being executed.

Feature b2 allows for a setting to occur when the supply start processing is being executed, making it possible to set the setting value to be used before game play begins. In this case, the setting value to be used is set in the supply start processing, which increases the processing load of the supply start processing. In contrast, the configuration of feature b1 described above does not include a setting monitoring process in the supply start processing, making it possible to monitor whether the setting value to be used is abnormal while preventing a further increase in the processing load of the supply start processing.

Feature b3. A gaming machine as described in Feature b1 or b2, wherein the setting monitoring means executes the setting monitoring process after the supply start process is completed.

According to feature b3, the setting monitoring process is executed after the processing at the start of supply is completed, making it possible to monitor whether the setting values of the target device are abnormal while preventing the processing load of the processing at the start of supply from increasing.

Feature b4. A gaming machine as described in Feature b3, wherein the setting monitoring means executes the setting monitoring process each time a monitoring trigger occurs after the supply start process is completed.

According to feature b4, after the processing at the start of supply is completed, the setting monitoring process is executed each time a monitoring trigger occurs, making it easier to identify abnormal settings in the target device.

Feature b5: A means for executing an interrupt process that is periodically started (a function for executing a first timer interrupt process in the main CPU 63) is provided,
A gaming machine according to any one of features b1 to b4, characterized in that the setting monitoring process is included in the interrupt process.

Feature b5 allows the settings monitoring process to be executed each time the device is periodically started, thereby increasing the frequency with which settings in use are monitored for abnormalities.

Feature b6. A gaming machine according to any one of Features b1 to b5, wherein the setting monitoring means includes means for regulating the progress of the game based on the setting value of the target to be used being identified as abnormal during the setting monitoring process (a function for executing the processes of steps S8207 and S8302 in the main CPU 63).

Feature b6 restricts gameplay progress when an abnormal setting value is identified for a target, preventing gameplay from continuing despite the abnormal setting value for the target.

Feature b7. A gaming machine according to any one of Features b1 to b6, wherein the setting monitoring means is equipped with a means (a function for executing the processing of step S8303 in the main CPU 63) for issuing a notification to the player to make the player aware that the setting possible situation should occur, based on the setting monitoring process identifying an abnormality in the setting value of the target to be used.

According to feature b7, if an abnormal setting value for the target is identified, a notification is issued to make the player aware that a setting enablement situation should be created. Therefore, if an abnormal setting value for the target is detected, it is possible to prompt the amusement hall manager to resolve the abnormality.

In addition, with respect to the configuration of features b1 to b7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group B can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to properly manage the setting values that determine the machine's advantageous degree, and there is still room for improvement in this regard.

<Feature group c>
Feature c1. Predetermined display means (first to fourth notification display devices 201 to 204),
A predetermined display control means (a function of executing a second timer interrupt process in the main CPU 63) that controls the display of the predetermined display means;
Equipped with
The gaming machine is characterized in that the specified display control means is equipped with a check control means (in the 35th embodiment, a function of executing the processing of step S9102 in the main CPU 63, and in the 38th embodiment, a function of executing the processing of step S9602 in the main CPU 63) that causes the specified display means to display a check display that allows confirmation of whether the specified display means is normal or not based on the occurrence of a check trigger.

According to feature c1, when a check trigger occurs, a check display is displayed on the specified display means. This makes it possible to check whether the specified display means is functioning normally.

Feature c2: The predetermined display means has a plurality of light-emitting portions (display segments 321 to 324),
The gaming machine described in feature c1 is characterized in that the check display is a display that allows confirmation that each of the multiple light-emitting sections can be in an emitting state.

According to feature c2, each of the multiple light-emitting elements of the specified display means is illuminated as a check display. This makes it possible to check whether each of the multiple light-emitting elements of the specified display means is illuminated.

Feature c3. A gaming machine according to feature c1 or c2, wherein the check trigger occurs when the supply of operating power begins.

Feature c3 displays a check message when the supply of operating power begins, allowing you to quickly check whether the specified display means is functioning normally.

Feature c4. A gaming machine according to any one of features c1 to c3, wherein the check trigger occurs each time the supply of operating power is started.

Feature c4 makes it possible to check whether the specified display means is normal each time the supply of operating power begins.

Feature c5. A gaming machine according to any one of Features c1 to c4, wherein the check trigger occurs when the supply of operating power begins, without requiring any operation to generate the check trigger.

Feature c5 allows a check display to be displayed without requiring any special operation when the supply of operating power begins, making it easy to check whether the specified display means is functioning normally.

Feature c6. A gaming machine described in any one of Features c1 to c5, wherein the check control means causes the predetermined display means to display the check indication when the supply of operating power has started and the check trigger has occurred, and does not cause the predetermined display means to display the check indication when the supply of operating power has started and the check trigger has not occurred.

According to feature c6, when the supply of operating power has started and a check trigger has occurred, a check display is displayed, making it possible to check whether the specified display means is normal before play begins on the gaming machine. On the other hand, when the supply of operating power has started but a check trigger has not occurred, a check display is not displayed, making it possible to prevent a check display from being displayed in situations where it is not necessary.

Feature c7: The gaming machine is provided with a means for storing information in a usage correspondence storage means (management start flag) based on whether the gaming machine has been used in a predetermined manner (a function for executing the processing of step S8606 in the main CPU 63);
The gaming machine described in feature c6 is characterized in that the check control means, when the supply of operating power has started and the information stored in the usage correspondence memory means does not correspond to the usage correspondence information, determines that the check trigger has occurred and causes the specified display means to display the check display, and when the supply of operating power has started and the information stored in the usage correspondence memory means corresponds to the usage correspondence information, determines that the check trigger has not occurred and does not cause the specified display means to display the check display.

According to feature c7, until the gaming machine is used in a predetermined manner, a check display is displayed on the predetermined display means when the supply of operating power is initiated, and even if the supply of operating power is initiated based on the gaming machine being used in a predetermined manner, the check display is not displayed on the predetermined display means. This makes it possible to confirm whether the predetermined display means is normal, for example, by displaying a check display on the predetermined display means when the supply of operating power is initiated at the time of shipping the gaming machine, and after the gaming machine is installed in an amusement hall, it becomes possible to prevent the check display from being displayed on the predetermined display means even if the supply of operating power is initiated.

Feature c8. The check control means
A display termination means (a function of executing the processing of step S9002 in the main CPU 63 and a function of making a negative determination in step S9101) that terminates the check display in the predetermined display means based on the occurrence of a termination trigger;
A canceling means for terminating the check display in the predetermined display means based on the occurrence of a canceling trigger even in a situation where the termination trigger has not occurred (a function for executing the processing of step S9203 in the main CPU 63 and a function for making a negative determination in step S9101, a function for executing the processing of step S9308 in the main CPU 63 and a function for making a negative determination in step S9101);
A gaming machine according to any one of features c1 to c7, characterized in that it is provided with:

According to feature c8, the check display is terminated when a cancellation trigger occurs, even if a trigger for terminating the check display has not occurred. Therefore, even if a check display is being displayed on a specified display means, the check display can be terminated midway and another display can be displayed.

Feature c9. A gaming machine according to Feature c8, wherein the cancellation trigger occurs when a predetermined operation means (reset button 68c) is operated.

According to feature c9, a cancellation trigger occurs when a specified operating means is operated, making it possible to end the check display at any time.

Feature c10. The predetermined display control means includes an alternative display control means (a function of executing the processes of steps S9004 and S9006 in the main CPU 63) that causes an alternative display different from the check display to be performed when an alternative display execution situation occurs,
The gaming machine according to feature c8 or c9, wherein the cancellation trigger occurs based on the different display execution status.

According to feature c10, the check display is terminated when a cancellation trigger occurs due to the execution of a separate display, making it possible to prioritize the separate display over the check display.

Feature c11. A gaming machine described in any one of Features c1 to c10, characterized in that it is equipped with a means for suspending the progress of processing while the check display is being executed by the predetermined display means (a function for executing the processing of step S9406 in the main CPU 63).

Feature c11 allows a check display to be displayed on a specified display means while the progress of processing is on hold, making it possible to display the check display while minimizing an increase in processing load.

Feature c12. A gaming machine described in any one of Features c1 to c11, wherein the check control means starts the check display on the predetermined display means before processing for controlling the progress of the game is executed when the supply of operating power is started.

Feature c12 makes it possible to check whether the specified display means is normal when the supply of operating power begins and before a game is played on the gaming machine.

Feature c13. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
A means for executing processing at the start of supply of operating power based on the start of supply of operating power (a function for executing the processing of steps S8801 to S8819 in the main CPU 63 in the 35th embodiment, and a function for executing the processing of steps S9401 to S9420 in the main CPU 63 in the 36th embodiment);
Equipped with
a configuration in which predetermined setting-related processes (setting confirmation process, setting value update process) relating to the setting values can be executed while the process at the start of supply of operating power is being executed,
The gaming machine described in feature c12 is characterized in that the check control means starts the check display on the specified display means when processing is being executed at the start of the supply of operating power.

According to feature c13, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be the one to be used. In addition, predetermined setting-related processing related to the setting value can be executed when processing is being executed at the start of the supply of operating power. This makes it possible to execute setting-related processing at a stage before game play begins. In this case, a check display is initiated on the predetermined display means when processing is being executed at the start of the supply of operating power. This makes it possible to integrate not only the predetermined setting-related processing but also the processing for initiating a check display on the predetermined display means into the processing at the start of the supply of operating power.

Feature c14. A gaming machine according to Feature c13, wherein the check control means includes means for starting the check display on the predetermined display means before the timing for executing the predetermined setting-related processing arrives (in the 35th embodiment, a function for executing the processing of steps S8804 and S8805 in the main CPU 63, and in the 36th embodiment, a function for executing the processing of steps S9404 and S9405 in the main CPU 63).

Feature c14 makes it possible to check whether a specified display means is operating normally before a specified setting-related process is executed.

Feature c15. A gaming machine as described in Feature c13 or c14, wherein the predetermined display control means includes a means for displaying the current setting value on the predetermined display means when the predetermined setting-related process is executed (a function for executing the processes of steps S9004 and S9006 in the main CPU 63).

According to feature c15, when a predetermined setting-related process is executed, the current setting value is displayed on the predetermined display means, allowing the amusement hall manager to ascertain the current setting value by checking the predetermined display means. In this case, with the configuration of feature c13 above, the process at the start of the supply of operating power not only includes the predetermined setting-related process but also the process for starting a check display on the predetermined display means. Therefore, the work of checking the predetermined display means to determine whether the predetermined display means is normal and the work of checking the predetermined display means to ascertain the current setting value can be performed together while the process at the start of the supply of operating power is being executed.

Furthermore, when the configuration of feature c14 above is provided, the predetermined display means starts displaying a check before displaying the current setting value on the predetermined display means. Therefore, after checking whether the predetermined display means is normal, it is possible to check the current setting value using the predetermined display means. This makes it possible to accurately check the setting value.

Feature c16. The check control means
A means for starting the check display on the predetermined display means before the timing when the predetermined setting-related processing can be executed (a function for executing the processing of steps S8804 and S8805 in the main CPU 63);
A means for terminating the check display based on the occurrence of a cancellation trigger in the predetermined setting-related processing while the check display is being displayed (a function for executing the processing of step S9203 in the main CPU 63 and a function for making a negative determination in step S9101, a function for executing the processing of step S9308 in the main CPU 63 and a function for making a negative determination in step S9101);
The gaming machine according to feature c15, further comprising:

According to feature c16, the check display is initiated on the predetermined display means before the current setting value is displayed on the predetermined display means. This makes it possible to check the current setting value using the predetermined display means after confirming whether the predetermined display means is normal. This allows for accurate checking of the setting value. Furthermore, when the check display is being displayed, a predetermined setting-related process is executed and a cancellation trigger occurs, and the check display is terminated. This makes it possible to terminate the check display and display the current setting value on the predetermined display means without waiting for the check display to end, when the predetermined setting-related process is executed. This allows for early confirmation of the current setting value.

Feature c17. A gaming machine according to Feature c16, wherein the cancellation trigger occurs based on the operation of a predetermined operation means (reset button 68c).

According to feature c17, a cancellation trigger occurs when a specified operating means is operated, making it possible to end the check display at any time.

Feature c18. A gaming machine according to any one of Features c13 to c17, characterized in that it is equipped with a means for executing processing to bring about a setting-enabled state in which the setting value to be used can be changed as the predetermined setting-related processing (in the 35th embodiment, a function for making affirmative determinations in steps S8806, S8817, and S8818 in the main CPU 63; in the 36th embodiment, a function for making affirmative determinations in steps S9407, S9418, and S9419 in the main CPU 63).

Feature c18 makes it possible to consolidate the processing performed when the supply of operating power begins, not only the processing for setting the setting values to be used, but also the processing for starting a check display on a specified display means.

Feature c19: The setting unit updates the setting value to be used based on the operation of a predetermined operation unit (reset button 68c) in the setting enabled state,
The check control means
A means for starting the check display on the predetermined display means before the setting possible state is reached (a function for executing the processing of steps S8804 and S8805 in the main CPU 63);
A means for terminating the check display based on the operation of the predetermined operation means in the setting possible state when the check display is being displayed (a function for executing the processing of step S9203 in the main CPU 63 and a function for making a negative determination in step S9101, a function for executing the processing of step S9308 in the main CPU 63 and a function for making a negative determination in step S9101);
Equipped with
The gaming machine described in feature c18 is characterized in that the predetermined display control means is equipped with a means (a function for executing the processing of steps S9004 and S9006 in the main CPU 63) for causing the predetermined display means to display the current setting value after the check display has ended in the setting possible status.

According to feature c19, the check display is initiated on the predetermined display means before the current setting value is displayed on the predetermined display means. This makes it possible to check the current setting value using the predetermined display means after checking whether the predetermined display means is normal. This allows for accurate checking of the setting value. Furthermore, when the setting becomes possible while the check display is being displayed, the check display is terminated and the current setting value is displayed based on the operation of the predetermined operating means. This makes it possible to terminate the check display and display the current setting value on the predetermined display means when the setting becomes possible without waiting for the check display to end. This allows for early confirmation of the current setting value.

Furthermore, in a configuration in which the setting value to be used is updated based on the operation of a specified operating means when the setting is possible, the check display is ended and the current setting value is displayed based on the operation of a specified operating means when the setting is possible, so no dedicated operation is required to end the check display and display the current setting value. This makes it possible to improve the efficiency of the task of updating the setting value to be used.

Feature c20. A gaming machine described in any one of Features c13 to c19, characterized in that it is equipped with a means for executing processing to display the current setting value on the predetermined display means as the predetermined setting-related processing (a function for executing processing for confirming settings in the main CPU 63).

Feature c20 makes it possible to consolidate the processing performed when the supply of operating power is started, not only the processing for checking the current setting value, but also the processing for starting a check display on a specified display means.

Feature c21. A gaming machine described in any one of Features c1 to c20, wherein the predetermined display control means is equipped with a means for causing the predetermined display means to display information corresponding to the results of game history management (a function for executing the processing of steps S8708, S8709, and S9107 in the main CPU 63).

Feature c21 makes it possible to notify the gaming hall manager of the results of gaming history management. In this case, by having the configuration of feature c1 and displaying a check display on the specified display means, it becomes possible to confirm whether the information corresponding to the results of gaming history management on the specified display means is being displayed accurately.

In addition, with respect to the configuration of features c1 to c21, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature group d>
Feature d1. Predetermined display means (first to fourth notification display devices 201 to 204),
A predetermined display control means (a function of executing a second timer interrupt process in the main CPU 63) that controls the display of the predetermined display means;
Equipped with
The gaming machine is characterized in that the specified display control means is equipped with a check control means (in the 35th embodiment, a function of executing processing of step S9102 in the main CPU 63, and in the 38th embodiment, a function of executing processing of step S9602 in the main CPU 63) that causes the specified display control means to display a check that allows confirmation of whether the specified display means is normal before processing to control the progress of the game is executed when the supply of operating power begins.

According to feature d1, the check display is displayed on the specified display means, making it possible to confirm whether the specified display means is operating normally. Furthermore, since the check display is displayed when the supply of operating power begins and before the process for controlling the progress of play is executed, it becomes possible to confirm whether the specified display means is operating normally before play is performed on the gaming machine once the supply of operating power begins.

Feature d2. A setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
A means for executing processing at the start of supply of operating power based on the start of supply of operating power (a function for executing the processing of steps S8801 to S8819 in the main CPU 63 in the 35th embodiment, and a function for executing the processing of steps S9401 to S9420 in the main CPU 63 in the 36th embodiment);
Equipped with
a configuration in which predetermined setting-related processes (setting confirmation process, setting value update process) relating to the setting values can be executed while the process at the start of supply of operating power is being executed,
The gaming machine described in feature d1 is characterized in that the check control means starts the check display on the specified display means when processing is being executed at the start of the supply of operating power.

According to feature d2, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect that the more advantageous setting value will be the one to be used. In addition, predetermined setting-related processing related to the setting value can be executed when processing is being executed at the start of the supply of operating power. This makes it possible to execute setting-related processing at a stage before game play begins. In this case, a check display is initiated on the predetermined display means when processing is being executed at the start of the supply of operating power. This makes it possible to integrate not only the predetermined setting-related processing but also the processing for initiating a check display on the predetermined display means into the processing at the start of the supply of operating power.

Feature d3. A gaming machine according to Feature d2, wherein the check control means is equipped with means for starting the check display on the predetermined display means before the timing for executing the predetermined setting-related processing arrives (in the 35th embodiment, a function for executing the processing of steps S8804 and S8805 in the main CPU 63, and in the 36th embodiment, a function for executing the processing of steps S9404 and S9405 in the main CPU 63).

Feature d3 makes it possible to check whether the specified display means is functioning normally before executing the specified setting-related process.

Feature d4. A gaming machine as described in Feature d2 or d3, wherein the predetermined display control means includes a means for causing the predetermined display means to display the current setting value when the predetermined setting-related process is executed (a function for executing the processes of steps S9004 and S9006 in the main CPU 63).

According to feature d4, when a predetermined setting-related process is executed, the current setting value is displayed on the predetermined display means, allowing the amusement hall manager to ascertain the current setting value by checking the predetermined display means. In this case, with the configuration of feature d2 above, the process at the start of the supply of operating power not only includes the predetermined setting-related process but also the process for starting a check display on the predetermined display means. Therefore, the tasks of checking the predetermined display means to determine whether the predetermined display means is operating normally and checking the predetermined display means to ascertain the current setting value can be performed together while the process at the start of the supply of operating power is being executed.

Furthermore, when the configuration of feature d3 above is provided, the predetermined display means starts displaying a check before displaying the current setting value on the predetermined display means. Therefore, after checking whether the predetermined display means is normal, it is possible to check the current setting value using the predetermined display means. This makes it possible to accurately check the setting value.

Feature d5. The check control means
A means for starting the check display on the predetermined display means before the timing when the predetermined setting-related processing can be executed (a function for executing the processing of steps S8804 and S8805 in the main CPU 63);
A means for terminating the check display based on the occurrence of a cancellation trigger in the predetermined setting-related processing while the check display is being displayed (a function for executing the processing of step S9203 in the main CPU 63 and a function for making a negative determination in step S9101, a function for executing the processing of step S9308 in the main CPU 63 and a function for making a negative determination in step S9101);
The gaming machine according to feature d4 is characterized by comprising:

According to feature d5, the check display is initiated on the predetermined display means before the current setting value is displayed on the predetermined display means. This makes it possible to check the current setting value using the predetermined display means after checking whether the predetermined display means is normal. This allows for accurate checking of the setting value. Furthermore, when the check display is being displayed, a predetermined setting-related process is executed and a cancellation trigger occurs, and the check display is terminated. This makes it possible to terminate the check display and display the current setting value on the predetermined display means without waiting for the check display to end, when the predetermined setting-related process is executed. This allows for early confirmation of the current setting value.

Feature d6. A gaming machine according to Feature d5, wherein the cancellation trigger occurs upon operation of a predetermined operation means (reset button 68c).

Feature d6 triggers a cancellation trigger when a specific operating means is operated, making it possible to end the check display at any time.

Feature d7. A gaming machine according to any one of Features d2 to d6, characterized in that it is equipped with a means for executing processing to bring about a setting-enabled state in which the setting value to be used can be changed as the predetermined setting-related processing (in the 35th embodiment, a function for making affirmative determinations in steps S8806, S8817, and S8818 in the main CPU 63; in the 36th embodiment, a function for making affirmative determinations in steps S9407, S9418, and S9419 in the main CPU 63).

Feature d7 makes it possible to consolidate the processing performed when the supply of operating power begins, not only the processing for setting the setting values to be used, but also the processing for starting a check display on a specified display means.

Feature d8: The setting unit updates the setting value to be used based on the operation of a predetermined operation unit (reset button 68c) in the setting enabled state,
The check control means
A means for starting the check display on the predetermined display means before the setting possible state is reached (a function for executing the processing of steps S8804 and S8805 in the main CPU 63);
A means for terminating the check display based on the operation of the predetermined operation means in the setting possible state when the check display is being displayed (a function for executing the processing of step S9203 in the main CPU 63 and a function for making a negative determination in step S9101, a function for executing the processing of step S9308 in the main CPU 63 and a function for making a negative determination in step S9101);
Equipped with
The gaming machine described in feature d7 is characterized in that the specified display control means is equipped with a means (a function for executing the processing of steps S9004 and S9006 in the main CPU 63) for causing the specified display means to display the current setting value after the check display has ended in the setting possible status.

According to feature d8, the check display is initiated on the specified display means before the current setting value is displayed on the specified display means. This makes it possible to check the current setting value using the specified display means after checking whether the specified display means is normal. This allows for accurate checking of the setting value. Furthermore, when the check display is being displayed and the setting becomes possible and the specified operating means is operated, the check display is terminated and the current setting value is displayed. This makes it possible to terminate the check display and display the current setting value on the specified display means when the setting becomes possible, without having to wait for the check display to end. This allows for early confirmation of the current setting value.

Furthermore, in a configuration in which the setting value to be used is updated based on the operation of a specified operating means when the setting is possible, the check display is ended and the current setting value is displayed based on the operation of a specified operating means when the setting is possible, so no dedicated operation is required to end the check display and display the current setting value. This makes it possible to improve the efficiency of the task of updating the setting value to be used.

Feature d9. A gaming machine described in any one of Features d2 to d8, characterized in that it is equipped with a means for executing processing to display the current setting value on the predetermined display means as the predetermined setting-related processing (a function for executing processing for confirming settings in the main CPU 63).

Feature d9 makes it possible to consolidate the processing performed when the supply of operating power is started, not only the processing for checking the current setting value, but also the processing for starting a check display on a specified display means.

Feature d10. A gaming machine described in any one of Features d1 to d9, characterized in that the predetermined display control means is equipped with a means for displaying information corresponding to the results of game history management on the predetermined display means (a function for executing the processing of steps S8708, S8709, and S9107 in the main CPU 63).

Feature d10 makes it possible to notify the gaming hall manager of the results of gaming history management. In this case, by having the configuration of feature d1 and displaying a check display on the specified display means, it becomes possible to confirm whether the information corresponding to the results of gaming history management on the specified display means is being displayed accurately.

In addition, with respect to the configuration of features d1 to d10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group c and feature group d can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above require a configuration that makes it possible to check whether the display on the specified display means is accurate, and there is still room for improvement in this regard.

<Feature group e>
Feature e1. A history storage execution means (a function for executing normal ball entry management processing in the main CPU 63) for storing game history information corresponding to a predetermined event that occurs when a game is executed in the history storage means (normal counter area 231);
An information deriving means (a function for executing the processing of step S8601 in the main CPU 63) for deriving mode information (base value) corresponding to the game result using the history information stored in the history storage means;
A behavior information storage means (a calculation result storage area 234) for storing the behavior information derived by the information derivation means;
Equipped with
The gaming machine is characterized in that the mode information storage means is capable of storing a plurality of pieces of mode information derived at different times by the information derivation means.

According to feature e1, when a predetermined event occurs, corresponding history information is stored in the history storage means. Storing the history information in the gaming machine itself prevents unauthorized access to or unauthorized modification of the history information. Furthermore, behavior information corresponding to the game results is derived using the history information stored in the history storage means, and the derived behavior information is stored in the behavior information storage means. This allows the gaming machine to store and retain information for managing the number of occurrences or frequency of predetermined events, and by using this managed information, it becomes possible to appropriately manage the frequency of occurrence of predetermined events. Furthermore, the behavior information storage means can store multiple pieces of behavior information derived at different times. This makes it possible to grasp the frequency of occurrence of predetermined events over multiple time periods, thereby enabling accurate understanding of the frequency of occurrence of predetermined events.

Feature e2. The aspect information storage means is
a most recent storage area (current state area 311) for storing the most recent aspect information derived by the information derivation means;
A gaming machine described in feature e1, characterized in that it is equipped with a past memory area (first to third history areas 312 to 314) that stores the status information derived by the information derivation means before the status information stored in the most recent memory area.

Feature e2 stores both the most recent behavior information and past behavior information derived before that, making it possible to grasp the occurrence frequency of a specified event not only for the most recent event but also for past events.

Feature e3. A period lapse determination means (a function of executing the processes of steps S8605 and S8613 in the main CPU 63) that determines that a predetermined period has passed from the occurrence of a period start trigger to the occurrence of a period end trigger;
A most recent storage execution means (a function of executing the processing of step S8602 in the main CPU 63) that stores the behavior information derived by the information derivation means in the most recent storage area in a situation where the period elapse determination means has not determined that the predetermined period has elapsed;
a past memory execution means (a function of executing the processing of steps S8607 and S8614 in the main CPU 63) for storing, in the past memory area, period-corresponding status information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means, based on the determination by the period elapse determination means that the predetermined period has elapsed;
The gaming machine according to feature e2, characterized in that it is provided with:

According to feature e3, behavior information derived when a predetermined period has not yet elapsed is stored in the most recent memory area, and behavior information derived when a predetermined period has elapsed is stored in the past memory area. This makes it possible to grasp the most recent occurrence frequency of a predetermined event, as well as the past occurrence frequency of a predetermined event in units of a predetermined period. Furthermore, because behavior information in units of a predetermined period is stored in the past memory area, it is possible to reduce the amount of behavior information stored in the past memory area.

Feature e4. A gaming machine as described in Feature e3, characterized in that it is equipped with a means (a function for executing the processing of steps S8608 and S8615 in the main CPU 63) for erasing the history information stored in the history storage means based on the period elapse determination means determining that the predetermined period has elapsed.

According to feature e4, the history information stored in the history information storage means is deleted after a predetermined period of time has elapsed, thereby reducing the storage capacity required by the history information storage means. Furthermore, even if the history information is deleted after a predetermined period of time has elapsed, behavior information derived using the history information for that predetermined period of time is stored in the past storage area, making it possible to later determine the frequency of occurrence of a predetermined event during that predetermined period of time.

Feature e5. A gaming machine described in any one of Features e2 to e4, wherein the past memory area is capable of storing multiple pieces of the behavior information derived at different times.

According to feature e5, multiple pieces of behavioral information are stored in the past memory area, making it possible to compare the occurrence frequency of a specified event corresponding to multiple time periods.

Feature e6. A period lapse determination means (a function of executing the processes of steps S8605 and S8613 in the main CPU 63) that determines that a predetermined period has elapsed from the occurrence of a predetermined period start trigger to the occurrence of a predetermined period end trigger;
a past memory execution means (a function of executing the processing of steps S8607 and S8614 in the main CPU 63) for storing, in the mode information storage means, period-corresponding status information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means, based on the determination by the period elapse determination means that the predetermined period has elapsed;
Equipped with
A gaming machine described in any one of features e1 to e5, characterized in that the mode information storage means is capable of storing multiple period-corresponding mode information corresponding to each of the different specified periods.

Feature e6 stores multiple pieces of past behavior information derived for a specified period, making it possible to compare the occurrence frequencies of specified events corresponding to multiple periods while limiting the amount of behavior information stored in the behavior information storage means.

Feature e7. A gaming machine as described in Feature e6, characterized in that it is equipped with a means (a function for executing the processing of steps S8608 and S8615 in the main CPU 63) for erasing the history information stored in the history storage means based on the period elapse determination means determining that the predetermined period has elapsed.

According to feature e7, the history information stored in the history information storage means is deleted after a predetermined period of time has elapsed, thereby reducing the storage capacity required by the history information storage means. Furthermore, even if the history information is deleted after a predetermined period of time has elapsed, behavior information derived using the history information for that predetermined period of time is stored in the past storage area, making it possible to later determine the frequency of occurrence of a predetermined event during that predetermined period of time.

Feature e8. A gaming machine described in any one of Features e1 to e7, characterized in that it includes a means for controlling the notification means (first to fourth notification display devices 201 to 204) so that notifications corresponding to each of the plurality of status information stored in the status information storage means are sequentially executed (a function for executing the processing of steps S8702 to S8709 in the main CPU 63).

According to feature e8, a notification corresponding to the behavior information is issued by the notification means. This makes it possible to grasp the frequency of occurrence of a predetermined event. Furthermore, because notifications corresponding to each of the multiple behavior information are issued sequentially, it is possible to grasp the frequency of occurrence of a predetermined event over multiple time periods individually while limiting the number of notification means.

Feature e9: The mode information storage means includes a first storage area (first history area 312) capable of storing the mode information, and a second storage area (second history area 313) capable of storing the mode information,
This gaming machine is a gaming machine described in any one of features e1 to e8, characterized in that it is equipped with a means (a function to execute the processing of steps S8607 and S8614 in the main CPU 63) for shifting the status information stored in the first memory area to the second memory area by an instruction including at least an LDIR instruction when an opportunity to shift information occurs.

Feature e9 enables shifting of behavior information between storage areas using a simple processing configuration.

In addition, with respect to the configuration of features e1 to e9, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group e can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be managed appropriately, and there is still room for improvement in this regard.

<Feature f group>
Feature f1. A means for executing processing at the start of supply of operating power based on the start of supply of operating power (a function for executing the processing of steps S8801 to S8819 in the main CPU 63 in the 35th embodiment, and a function for executing the processing of steps S9401 to S9420 in the main CPU 63 in the 36th embodiment);
A power outage monitoring means (a function for executing the processing of step S8901 in the main CPU 63) that enables a power outage monitoring process to be executed to monitor the occurrence of a power outage when the processing at the start of the supply of the operating power is being executed;
A gaming machine characterized by comprising:

Feature f1 allows power outage monitoring processing to be performed even when processing is being performed at the start of the supply of operating power, making it possible to respond appropriately if a power outage occurs while processing is being performed at the start of the supply of operating power.

Feature f2: The device is provided with a means for executing a periodically activated interrupt process (a function for executing a first timer interrupt process in the main CPU 63),
The interrupt processing includes the power outage monitoring processing,
A gaming machine described in feature f1, characterized in that the interrupt processing can be interrupted and started when processing is being executed when the supply of operating power begins.

According to feature f2, interrupt processing is periodically initiated even when processing is being executed when the supply of operating power begins. This makes it possible to periodically monitor for the occurrence of power outages even when processing is being executed when the supply of operating power begins.

Feature f3. A gaming machine according to Feature f2, characterized in that the interrupt processing can be initiated by interrupting even in a situation where post-termination processing (steps S8822 to S8825 in the main CPU 63) is being executed after the processing at the start of the supply of operating power has ended.

Feature f3 makes it possible to periodically monitor for power outages while processing is being executed at the start of the supply of operating power, by using interrupt processing that can be initiated while processing is being executed after termination.

Feature f4: The interrupt process includes a progress response process (steps S8907 to S8920 in the main CPU 63) executed to control the progress of the game,
When the interrupt process is started while the process at the start of supplying the operating power is being executed, the power outage monitoring process is executed, but the progress response process is not executed.
A gaming machine described in feature f3, characterized in that when the interrupt processing is started in an interrupting situation in which the post-termination processing is being executed, both the power outage monitoring processing and the progress response processing can be executed.

Feature f4 enables a configuration in which interrupt processing that can be started in an interrupt situation where post-termination processing is being executed is used to periodically monitor for the occurrence of a power outage while processing at the start of the supply of operating power is being executed, so that even if interrupt processing is started in an interrupt situation where processing at the start of the supply of operating power is being executed, progress response processing for controlling the progress of the game is not executed.

Feature f5. Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level,
A gaming machine described in any one of features f1 to f4, characterized in that when processing is being executed at the start of the supply of operating power, a configurable situation can occur in which the setting value to be used can be changed.

Feature f5 allows power outage monitoring to be performed even when the target setting value is being set, making it possible to respond appropriately even if a power outage occurs while the target setting value is being set.

Feature f6. A gaming machine according to Feature f5, characterized in that if the supply of operating power is stopped after the occurrence of a power outage is identified by the power outage monitoring process, when the supply of operating power is resumed, it is possible to play the game with the setting values that were set as targets for use before the supply of operating power was stopped.

According to feature f6, even if a power outage occurs while the setting values to be used are being set, the power outage monitoring process will identify the occurrence of the power outage, and when the supply of operating power is resumed, it will be possible to play with the setting values selected at the time the power outage occurred as the setting values to be used. As a result, even if a power outage occurs while the setting values to be used are being set, there is no need to reset the setting values when the supply of operating power is resumed.

In addition, with respect to the configuration of features f1 to f6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group f can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Amusement machines such as those exemplified above need to deal appropriately with power outages, and there is still room for improvement in this regard.

<Feature g group>
Feature g1. A setting correspondence storage means (setting correspondence storage area 325 in the 39th embodiment, setting correspondence storage area 326 in the 40th embodiment) having a first predetermined number of setting correspondence storage areas (first to sixth setting information storage areas 325a to 325f in the 39th embodiment, first to third setting information storage areas 326a to 326c in the 40th embodiment) for storing setting correspondence information (a win/loss table for a low probability mode, a win/loss table for a high probability mode) corresponding to the player's advantage;
A setting means for setting the setting value to be used (a function for executing a setting value update process in the main CPU 63);
A profit-related means (a function for executing a special chart variation start process in the main CPU 63) for executing a profit-related process (step S504) related to the player's profit by using the setting correspondence information stored in the setting correspondence memory area corresponding to the setting value set by the setting means;
Equipped with
A gaming machine characterized in that the number of types of setting values that can be set by the setting means is less than the first predetermined number.

According to feature g1, the setting value to be used is set from multiple levels of setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, in a configuration in which a first predetermined number of setting correspondence memory areas are provided for storing setting correspondence information corresponding to setting values, the number of types of setting values to be used is less than the first predetermined number. This makes it possible to share the configuration related to the setting correspondence memory means with gaming machines in which the number of types of setting values to be used is the first predetermined number, and simplifies the design work of gaming machines when the number of types of setting values is changed. As a result, it is possible to create an optimal configuration related to setting values.

Feature g2: A correspondence information storage unit (a setting value counter in the work area 221 for specific control) is provided that can store and hold correspondence information corresponding to each of the first predetermined number of setting correspondence storage areas,
the setting means sets the setting value to be used by changing the correspondence information stored and held in the correspondence information storage means based on a change operation;
The gaming machine described in feature g1 is configured such that the setting correspondence information of the setting values that can be set by the setting means is stored in at least one of the setting correspondence memory areas, and the same setting correspondence information is stored in multiple setting correspondence memory areas that are part of the first predetermined number, thereby causing the setting correspondence information to be stored in all of the first predetermined number of setting correspondence memory areas.

According to feature g2, the setting value to be used is changed by changing the correspondence information stored in the correspondence information storage means based on the change operation, and the setting correspondence information in the setting correspondence memory area corresponding to the changed correspondence information is used in the benefit-related processing, thereby executing the benefit-related processing in a manner corresponding to the setting value to be used. In this case, the setting correspondence information for the setting value that can be set by the setting means is stored in at least one setting correspondence memory area, and the same setting correspondence information is stored in multiple setting correspondence memory areas that are part of the first predetermined number, so that the setting correspondence information is stored in all of the first predetermined number of setting correspondence memory areas. This makes it possible to reduce the number of types of setting values to be used to a number less than the first predetermined number, while still using the first predetermined number of setting correspondence memory areas and the configuration that determines the setting value to be used using the correspondence information storage means.

Feature g3. The profit-related means is
A means for reading the setting correspondence information from the setting correspondence storage area corresponding to the corresponding information stored in the corresponding information storage means (a function for executing a reading process of the win/fail table in the main CPU 63);
A means for executing the profit-related processing using the read setting correspondence information (a function for executing the processing of step S504 in the main CPU 63);
The gaming machine according to feature g2 is characterized by comprising:

According to feature g3, even if the number of types of setting values to be used is less than the first predetermined number, the benefit-related processing can be executed using the setting correspondence information read from the setting correspondence storage area corresponding to the correspondence information stored and held in the correspondence information storage means, making it possible to use the configuration that reads setting correspondence information when executing the benefit-related processing as is.

Feature g4: A predetermined display control means (a function of executing the processes of steps S9801 to S9804 in the main CPU 63) is provided that causes a predetermined display means (the fourth notification display device 204) to display a display corresponding to the current setting value in a situation where the correspondence information stored and held in the correspondence information storage means can be changed,
The predetermined display control means
A means for reading display information of the setting value corresponding to the setting correspondence information stored in the setting correspondence storage area corresponding to the correspondence information of the correspondence information storage means (a function for executing the processing of steps S9801 to S9803 in the main CPU 63);
A means for causing the predetermined display means to display a display corresponding to the display information of the read setting value (a function for executing the process of step S9804 in the main CPU 63);
The gaming machine according to feature g2 or g3 is characterized by comprising:

According to feature g4, when changing a setting value to be used, it is possible to change the setting value while checking the display corresponding to the current setting value displayed on the specified display means. In this case, even if the number of types of setting values to be used is less than the first specified number, the configuration reads display information for the setting value corresponding to the setting correspondence information in the setting correspondence storage area corresponding to the correspondence information in the correspondence information storage means, and causes the specified display means to display corresponding to the read display information for the setting value. This makes it possible to directly use the configuration for reading display information for the setting value when executing a display corresponding to the setting value.

Feature g5: The number of types of the set values that can be set by the setting means is a divisor of the first predetermined number and is different from the first predetermined number;
A gaming machine described in feature g4, characterized in that the number of setting correspondence memory areas in which the setting correspondence information corresponding to each setting value is stored is the same for each setting value.

Feature g5 makes it possible to make the frequency at which the display corresponding to each setting value is displayed on the specified display means uniform for each setting value, even if the number of types of setting values to be used is less than the first predetermined number.

Feature g6. A gaming machine as described in Feature g4 or g5, wherein the setting correspondence memory areas corresponding to the correspondence information in consecutive order in the change order of the correspondence information stored and maintained in the correspondence information storage means do not store the setting correspondence information corresponding to the same setting value.

Feature g6 makes it possible to change the setting value to be displayed on the specified display means each time a change operation is performed. This makes it possible to improve the operability of the change operation even in a configuration in which the number of types of setting values to be used is less than the first specified number.

In addition, with respect to the configuration of features g1 to g6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group g can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to optimize the configuration of the setting values that determine the machine's advantageous degree, and there is still room for improvement in this regard.

<Feature h group>
Feature h1. Display means (special map display unit 37a, special map reserve display unit 37b, general map display unit 38a, general map reserve display unit 38b, first to fourth notification display devices 201-204, first to fifth display circuits 261-265),
A display control means (main CPU 63) that transmits display data (display data signal, display clock signal) corresponding to the display content to be displayed on the display means;
a display execution means (display IC 266) for, when the display data is transmitted by the display control means, setting the display on the display means so that the display content corresponds to the display data;
In a gaming machine equipped with
A plurality of the display means is provided,
The display control means includes a sequential transmission means (a function of executing a second timer interrupt process in the main CPU 63) that sequentially transmits the display data corresponding to each of the plurality of display means to the display execution means,
when the display data is transmitted by the display control means, the display execution means performs the display setting on one of the plurality of display means to which the display data is to be set, so that the display content corresponds to the display data;
A gaming machine characterized in that the transmission interval of the display data from the sequential transmission means to the display execution means is a transmission interval that allows the display setting by the display execution means to be performed on each display means before it becomes impossible to maintain the display corresponding to the display data on each display means.

According to feature h1, the display execution means performs display settings for the display means in accordance with the display data transmitted from the display control means, thereby controlling the display of the display means so that the display content corresponds to the display data. This reduces the processing load on the display control means. In this case, in a configuration in which multiple display means are provided, display execution means are not provided in one-to-one correspondence with the multiple display means, but rather a single display execution means is shared by the multiple display means. This makes it possible to increase the number of display means while suppressing an increase in the number of display execution means. Furthermore, the transmission interval of display data from the display control means to the display execution means is set to a transmission interval in which the display execution means performs display settings for each display means before each display means can no longer maintain a display corresponding to the display data. This makes it possible to appropriately display a display corresponding to the display data on each display means, even in a configuration in which a single display execution means is shared by multiple display means. The above makes it possible to provide a suitable configuration for controlling the display of the display means.

Feature h2. A gaming machine according to Feature h1, wherein when the sequential transmission means transmits the display data to the display execution means, the sequential transmission means transmits identifiable information (a type data signal, a type clock signal) to the display execution means that enables identification of the type of the display means for which the display data is set.

According to feature h2, when display data is transmitted from the display control means, the display execution means simply sets the display data for the display means corresponding to the identifiable information transmitted from the display control means. This makes it possible to simplify the configuration of the display execution means, even in a configuration in which one display execution means is shared by multiple display means.

Feature h3. A gaming machine according to Feature h1 or h2, wherein the sequential transmission means transmits the display data so that an update cycle is repeated, where one update cycle is defined as each of the plurality of display means being the setting target of the display data in a predetermined order.

Feature h3 allows the display control means to change the display means to which display data is sent in a predetermined order, thereby simplifying the processing configuration of the display control means.

Feature h4. A gaming machine described in any one of Features h1 to h3, wherein the sequential transmission means transmits display data for one of the display means when that display means becomes the transmission target, even if the content of the display data for that display means is identical to the content of the display data transmitted the previous time that that display means was the transmission target.

Feature h4 allows display data to be transmitted even if the content of the data has not been changed. This makes it possible to continue displaying the same content on a specific display means even in a configuration where one display execution means is shared by multiple display means.

Feature h5. A gaming machine described in any one of Features h1 to h4, wherein the sequential transmission means executes processing to transmit the display data in a predetermined interrupt process (second timer interrupt process) that is initiated when a predetermined process is being executed by the display control means.

According to feature h5, processing for transmitting display data is executed using a predetermined interrupt process, so the cycle at which display data is set on each display means can be set to a predetermined cycle. Therefore, even in a configuration in which one display execution means is shared by multiple display means, it is possible for the display execution means to set display data on each display means before each display means can no longer maintain the display corresponding to the display data.

Feature h6. A gaming machine according to Feature h5, wherein the processing for transmitting the display data by the display execution means to the multiple display means that are the targets of the display setting is integrated into the predetermined interrupt processing.

Feature h6 makes it possible to set the same cycle for setting display data on each display means that is the target of display settings by the display execution means.

Feature h7: The display control means includes a means for interrupting and starting a specific interrupt process (first timer interrupt process) when the predetermined process is being executed (a function for executing the first timer interrupt process in the main CPU 63),
A gaming machine according to feature h5 or h6, characterized in that the interrupt period of the predetermined interrupt process is shorter than the interrupt period of the specific interrupt process.

According to feature h7, processing is executed in which display data is sent to the display execution means in a predetermined interrupt process that has a shorter period than the interrupt period of the specific interrupt process. This makes it possible to send display data in a shorter period than in a configuration in which processing is executed in which display data is sent to the display execution means in a specific interrupt process.

Feature h8. A gaming machine as described in Feature h7, wherein processing for progressing the game is executed during the specific interrupt processing.

Feature h8 allows specific interrupt processing to be initiated at an appropriate period for executing processing to progress the game, while still achieving the excellent effects already described.

Feature h9. A gaming machine as described in Feature h7 or h8, wherein the predetermined interrupt process is initiated even when the specific interrupt process is being executed.

According to feature h9, the predetermined interrupt process is initiated even when a specific interrupt process is being executed, so that the transmission period for display data can be set to a predetermined period even in a configuration in which the specific interrupt process is initiated by an interrupt.

Feature h10. A gaming machine described in any one of Features h7 to h9, characterized in that an interrupt of the specific interrupt process is prohibited when the predetermined interrupt process is started, and an interrupt of the specific interrupt process is permitted when the predetermined interrupt process is ended.

Feature h10 makes it possible to prevent specific interrupt processing from interrupting execution when a predetermined interrupt processing is being executed. This allows the processing for transmitting display data to be given priority.

Feature h11. The display control means comprises a means for executing processing at the start of supply of operating power when the supply of operating power is started (a function for executing the processing of steps S7901 to S7918 in the main CPU 63 in the 33rd embodiment, a function for executing the processing of steps S8801 to S8819 in the main CPU 63 in the 35th embodiment, a function for executing the processing of steps S9401 to S9420 in the main CPU 63 in the 36th embodiment, a function for executing the processing of steps S9501 to S9518 in the main CPU 63 in the 37th embodiment, and a function for executing the processing of steps S9901 to S9917 in the main CPU 63),
A gaming machine described in any one of features h5 to h10, characterized in that the specified interrupt processing is started by interrupting even when processing is being executed at the start of the supply of operating power.

Feature h11 makes it possible to control the display of multiple display means even when processing is being executed at the start of the supply of operating power. Furthermore, because a predetermined interrupt process is initiated by interrupting the processing executed at the start of the supply of operating power, it is possible to control the display of multiple display means even when processing is being executed at the start of the supply of operating power without complicating the processing configuration of the processing executed at the start of the supply of operating power.

Feature h12. Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a configuration in which, in a state in which the process at the start of supply of the operating power is being executed, a setting possible state can be entered in which the setting value to be used can be changed;
The gaming machine described in feature h11 is characterized in that the sequential transmission means transmits the display data to the display execution means so that a display corresponding to the current setting value is displayed on a specified display means in the setting possible situation.

According to feature h12, the current setting value is displayed on a specified display device while the setting value to be used is being set, making it easier to set the setting value to be used.

Feature h13: The display control means includes a means for executing a progress response process to control the progress of a game after the process at the start of the supply of the operating power is completed (a function for executing a first timer interrupt process in the main CPU 63),
the sequential transmission means transmits to the display execution means the display data for causing a corresponding display corresponding to the execution result of the progress corresponding process to be displayed on at least some of the plurality of display means,
The gaming machine according to feature h11 or h12, wherein the predetermined interrupt process is started by interrupting even after the process at the start of the supply of operating power has ended.

According to feature h13, by utilizing a predetermined interrupt process, it is possible to control the display of multiple display means both when processing is being performed at the start of the supply of operating power and after the processing at the start of the supply of operating power has ended.

In addition, with respect to the configuration of features h1 to h13, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature i group>
Feature i1. A first interrupt execution means (a function of executing a first timer interrupt process in the main CPU 63) that interrupts another process and executes a first interrupt process based on the lapse of a first interrupt period while the other process is being executed;
A second interrupt execution means (a function of executing a second timer interrupt process in the main CPU 63) that interrupts the other process and executes a second interrupt process based on the lapse of a second interrupt period while the other process is being executed;
Equipped with
the second interrupt period is shorter than the first interrupt period,
A gaming machine characterized in that processing for controlling the display of predetermined display means (special chart display unit 37a, special chart reserve display unit 37b, regular chart display unit 38a, regular chart reserve display unit 38b, first to fourth notification display devices 201 to 204) is executed by the second interrupt processing.

According to feature i1, processing for display control of a predetermined display means is executed in a predetermined interrupt process that has a shorter interrupt period than the interrupt period of the specific interrupt process. This makes it possible to control the display of the predetermined display means in a shorter period than in a configuration in which processing for display control of a predetermined display means is executed in a specific interrupt process.

Feature i2. A gaming machine as described in Feature i1, characterized in that processing for progressing the game is executed in the first interrupt processing.

Feature i2 allows the first interrupt process to be initiated at an appropriate interval for executing the process to progress the game, while still achieving the excellent effects already described.

Feature i3. A gaming machine described in Feature i1 or i2, characterized in that the second interrupt process is initiated even when the first interrupt process is being executed.

According to feature i3, the second interrupt process is initiated by interrupting even when the first interrupt process is being executed, so that even in a configuration in which the first interrupt process is initiated by interrupting, it is possible to control the display of a specified display means at a specified cycle.

Feature i4. A gaming machine described in any one of Features i1 to i3, characterized in that an interrupt by the first interrupt process is prohibited when the second interrupt process is started, and an interrupt by the first interrupt process is permitted when the second interrupt process is ended.

Feature i4 makes it possible to prevent the first interrupt process from being executed while the second interrupt process is being executed. This allows display control of a specified display means to be given priority.

Feature i5. The device is provided with a means for executing processing at the start of supply of operating power when the supply of operating power is started (a function for executing main processing in the main CPU 63),
A gaming machine described in any one of features i1 to i4, characterized in that the second interrupt processing is started by interrupting even when processing is being executed at the start of the supply of operating power.

Feature i5 makes it possible to control the display of a predetermined display means even when processing is being executed at the start of the supply of operating power. Furthermore, because the second interrupt processing is configured to interrupt and start the processing at the start of the supply of operating power, it is possible to control the display of a predetermined display means even when processing is being executed at the start of the supply of operating power, without complicating the processing configuration of the processing at the start of the supply of operating power.

Feature i6. Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level,
a configuration in which, in a state in which the process at the start of supply of the operating power is being executed, a setting possible state can be entered in which the setting value to be used can be changed;
The gaming machine described in feature i5 is characterized in that the second interrupt execution means executes processing in the second interrupt processing to cause the specified display means to display a value corresponding to the current setting value in the settable situation.

Feature i6 allows the current setting value to be displayed on a specified display device while the setting value to be used is being set, making it easier to set the setting value to be used.

Feature i7. The gaming machine described in Feature i5 or i6, wherein the second interrupt execution means executes the second interrupt processing based on the elapse of the second interrupt period even after the processing at the start of the supply of operating power has ended.

Feature i7 uses a specified interrupt process to enable display control of a specified display means both when processing is being performed at the start of supplying operating power and after the processing at the start of supplying operating power has finished.

In addition, with respect to the configuration of features i1 to i7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group h and feature group i can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the display means must be configured appropriately, and there is still room for improvement in this regard.

<Feature j group>
Feature j1. A means for executing processing at the start of supply of operating power based on the start of supply of operating power (in the 33rd embodiment, a function for executing processing of steps S7901 to S7918 in the main CPU 63, in the 35th embodiment, a function for executing processing of steps S8801 to S8819 in the main CPU 63, in the 36th embodiment, a function for executing processing of steps S9401 to S9420 in the main CPU 63, in the 37th embodiment, a function for executing processing of steps S9501 to S9518 in the main CPU 63, and in the 42nd embodiment, a function for executing processing of steps S9901 to S9917 in the main CPU 63);
A predetermined interrupt execution means (a function of executing a first timer interrupt process in the main CPU 63, a function of executing a second timer interrupt process in the main CPU 63) that interrupts the process at the start of the supply of operating power and executes a predetermined interrupt process;
A gaming machine characterized by comprising:

According to feature j1, a predetermined interrupt process is initiated even when a process is being executed when the supply of operating power starts, making it possible to prioritize the execution of the process set as the predetermined interrupt process even immediately after the supply of operating power starts. Furthermore, since there is no need to set the process set as the predetermined interrupt process for the process when the supply of operating power starts, it is possible to prioritize the execution of the process set as the predetermined interrupt process even immediately after the supply of operating power starts, without complicating the processing configuration of the process when the supply of operating power starts. As a result, it is possible to optimally execute the process when the supply of operating power starts.

Feature j2. A gaming machine according to Feature j1, wherein the predetermined interrupt execution means executes processing for controlling the display of predetermined display means (special chart display unit 37a, special chart reserved display unit 37b, regular chart display unit 38a, regular chart reserved display unit 38b, first to fourth notification display devices 201-204) through the predetermined interrupt processing.

Feature j2 makes it possible to display a predetermined message on a predetermined display means even immediately after the supply of operating power begins.

Feature j3. Equipped with a setting means (a function for executing a setting value update process in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a configuration in which, in a state in which the process at the start of supply of the operating power is being executed, a setting possible state can be entered in which the setting value to be used can be changed;
The gaming machine described in feature j1 or j2 is characterized in that the specified interrupt execution means executes processing by the specified interrupt processing so that a display corresponding to the current setting value is displayed on a specified display means (fourth notification display device 204) in the settable situation.

Feature j3 allows the current setting value to be displayed on a specified display device while the setting value to be used is being set, making it easier to set the setting value to be used.

Feature j4. A gaming machine described in any one of Features j1 to j3, wherein the predetermined interrupt execution means executes the predetermined interrupt processing based on the lapse of a predetermined interrupt period, even after the processing at the start of the supply of operating power has ended.

According to feature j4, by using a predetermined interrupt process, it is possible to execute the process set as the predetermined interrupt process both when the process that started the supply of operating power is being executed and after the process that started the supply of operating power has finished.

Feature j5. A gaming machine described in any one of Features j1 to j4, wherein the predetermined interrupt execution means executes a power outage monitoring process (step S8901) for monitoring the occurrence of a power outage in the predetermined interrupt process.

Feature j5 allows power outage monitoring processing to be performed even when processing is being performed at the start of the supply of operating power. This makes it possible to respond appropriately if a power outage occurs while processing is being performed at the start of the supply of operating power.

Feature j6. The predetermined interrupt process includes a progress response process (steps S8907 to S8920 in the main CPU 63) executed to control the progress of the game,
When the predetermined interrupt process is started by interrupting while the process at the start of supplying the operating power is being executed, the power outage monitoring process is executed, but the progress response process is not executed,
A gaming machine described in feature j5, characterized in that when the specified interrupt processing is started in an interrupt manner while the post-termination processing (steps S8822 to S8825 in the main CPU 63) is being executed after the processing at the start of the supply of operating power has been completed, both the power outage monitoring processing and the progress response processing can be executed.

Feature j6 enables a configuration in which a predetermined interrupt process that can be started in an interrupt situation where post-termination processing is being executed is used to periodically monitor for the occurrence of a power outage while processing at the start of the supply of operating power is being executed, so that even if the predetermined interrupt process is started in an interrupt situation where processing at the start of the supply of operating power is being executed, progress response processing for controlling the progress of the game is not executed.

In addition, for the configuration of features j1 to j6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group j can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to perform processing appropriately when the supply of operating power begins, and there is still room for improvement in this regard.

<Feature k group>
Feature k1. When a predetermined event occurs due to the execution of a game, history information of the corresponding game is stored in the history storage means (normal counter area 231) (a function for executing normal ball entry management processing in the main CPU 63);
An information deriving means (a function for executing the processing of step SA201 in the main CPU 63) for deriving mode information (base value) corresponding to the game result using the history information stored in the history storage means;
A status information display control means (a function of executing display processing and second timer interrupt processing in the main CPU 63) that controls the display of information display means (first to fourth notification display devices 201 to 204) so that a display corresponding to the status information derived by the information derivation means is performed;
A predetermined corresponding display control means (a function of executing the processing of step SA320 in the main CPU 63 and the second timer interrupt processing) that causes a predetermined corresponding display (pre-shift display) to be displayed on the information display means before a new display corresponding to the mode information is started based on the occurrence of a predetermined display trigger;
A gaming machine characterized by comprising:

According to feature k1, when a predetermined event occurs, corresponding history information is stored in the history storage means. Storing the history information in the gaming machine itself prevents unauthorized access to or unauthorized modification of the history information. Furthermore, using the history information stored in the history storage means, behavior information corresponding to the game results is derived, and a display corresponding to the derived behavior information is displayed on the information display means. This makes it possible to grasp the results of game history management, such as the frequency of occurrence of a predetermined event. Furthermore, upon the occurrence of a predetermined display trigger, a predetermined corresponding display is displayed on the information display means before a new display corresponding to the behavior information is started. This makes it possible, when a predetermined display trigger occurs, for the information display means to display the corresponding predetermined corresponding display in priority over the display corresponding to the behavior information, and to use the information display means to notify the user that a predetermined display trigger has occurred.

Feature k2: A period lapse determination means (a function for executing the processing of step SA210 in the main CPU 63) is provided to determine that a predetermined period has elapsed from the occurrence of a predetermined period start trigger to the occurrence of a predetermined period end trigger,
The gaming machine described in feature k1 is characterized in that the predetermined response display control means determines that the predetermined display trigger has occurred when the period elapsed determination means determines that the predetermined period has elapsed, and causes the predetermined response display to be displayed on the information display means.

According to feature k2, when a predetermined period of time has elapsed, the information display means displays a predetermined corresponding display, and then the information display means starts a new display corresponding to the mode information. This allows the amusement hall manager to recognize that the mode information displayed on the information display means is from after the predetermined period of time has elapsed.

Feature k3: The information deriving means, based on the determination by the period elapse determination means that the predetermined period has elapsed, derives the behavior information by using the history information corresponding to the predetermined event that occurred after the predetermined period;
The gaming machine described in feature k2 is characterized in that, based on the period elapse determination means determining that the predetermined period has elapsed, the predetermined corresponding display control means causes the information display means to display the predetermined corresponding display before the information display means displays the display corresponding to the status information derived by the information derivation means using the historical information corresponding to the predetermined event that occurred after the predetermined period.

According to feature k3, in a configuration in which new mode information is derived based on the passage of a predetermined period of time, when the predetermined period of time has passed, the information display means displays a predetermined corresponding display, and then displays a display corresponding to the newly derived mode information after the passage of the predetermined period of time. This allows the amusement hall manager to determine whether the display corresponding to the mode information on the information display means corresponds to the newly derived mode information after the passage of the predetermined period of time.

Feature k4. A gaming machine as described in Feature k3, characterized in that it is equipped with a means (a function for executing the processing of step SA217 in the main CPU 63) for erasing the history information stored in the history storage means based on the period elapse determination means determining that the predetermined period has elapsed.

Feature k4 allows the history information stored in the history information storage means to be erased after a predetermined period of time has elapsed, thereby reducing the storage capacity required in the history information storage means.

Feature k5. A storage execution means (a function of executing the processes of steps SA203 and SA216 in the main CPU 63) is provided for storing the behavior information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means as period-corresponding behavior information in the behavior information storage means (the calculation result storage area 234) based on the determination by the period elapse determination means that the predetermined period has elapsed,
the aspect information display control means controls the display of the information display means so that a display corresponding to the period-corresponding aspect information stored in the aspect information storage means is performed,
A gaming machine described in any one of features k2 to k4, characterized in that the predetermined corresponding display control means, based on the period elapse determination means determining that the predetermined period has elapsed, causes the predetermined corresponding display to be displayed on the information display means before the display corresponding to the period corresponding mode information newly stored in the mode information storage means by the memory execution means is displayed on the information display means.

According to feature k5, past behavior information derived in units of a predetermined period is stored as period-corresponding behavior information, and a display corresponding to that period-corresponding behavior information is displayed on the information display means. This allows the amusement hall manager to understand the past period-corresponding behavior information derived in units of a predetermined period by checking the information display means. Furthermore, when the predetermined period has passed, the information display means displays the predetermined corresponding display, and then displays a display corresponding to the period-corresponding behavior information newly derived after the predetermined period has passed. This allows the amusement hall manager to understand whether the display corresponding to the period-corresponding behavior information on the information display means corresponds to the period-corresponding behavior information newly derived based on the passage of the predetermined period.

Feature k6: The mode information storage means is capable of storing a plurality of pieces of period-corresponding mode information corresponding to different predetermined periods,
The gaming machine described in feature k5 is characterized in that the mode information display control means controls the display of the information display means so that a display corresponding to each of the multiple period-corresponding mode information stored in the mode information storage means is displayed.

According to feature k6, multiple pieces of past period correspondence information derived in units of a specified period are stored, and the information display means displays corresponding to these multiple pieces of period correspondence information, making it possible to compare the occurrence frequencies of specified events corresponding to multiple specified periods.

Feature k7. A gaming machine described in any one of Features k1 to k6, characterized in that it is equipped with a means (a function for executing step SA316 in the main CPU 63 and second timer interrupt processing) for causing the information display means to return to a pre-switching state (interval non-display state) before displaying a display corresponding to mode information different from the mode information while the display corresponding to the mode information is being displayed.

According to feature k7, when the mode information to be displayed is switched, the information display means returns to the pre-switch state, allowing the amusement hall manager to clearly understand that the mode information to be displayed has switched. In this case, the configuration of feature k1 above is provided, and a predetermined corresponding display is displayed on the information display means when a predetermined display trigger occurs. This makes it possible to notify that a predetermined display trigger has occurred by using the information display means, which displays a display corresponding to different mode information with the pre-switch state in between.

Feature k8. A gaming machine described in any one of Features k1 to k7, wherein the predetermined corresponding display control means, when the predetermined display trigger occurs, causes the predetermined corresponding display to be initiated by the information display means even if the display duration period of the display corresponding to the mode information has not yet elapsed.

According to feature k8, when a predetermined display trigger occurs, a predetermined corresponding display is initiated even if a display corresponding to the mode information is in progress. This makes it possible to notify the user early on that a predetermined display trigger has occurred.

Feature k9. A gaming machine described in any one of Features k1 to k7, wherein the predetermined corresponding display control means, when the predetermined display trigger occurs during the display duration of the display corresponding to the mode information, causes the predetermined corresponding display to be initiated by the information display means after the display duration has elapsed.

According to feature k9, even if a predetermined display trigger occurs, the predetermined corresponding display begins after the display corresponding to the aspect information currently being displayed is completed. This makes it possible to notify the user that a predetermined display trigger has occurred without interfering with the display corresponding to the aspect information that is already being displayed.

Feature k10: A behavior information storage means (computation result storage area 234) is provided to store the behavior information derived by the information derivation means,
the behavior information storage means includes a plurality of specific storage areas (a current status area 311, a first history area 312, a second history area 313, and a third history area 314) so as to be able to store each of the plurality of behavior information derived at different times by the information derivation means;
A gaming machine described in any one of features k1 to k9, characterized in that the status information display control means controls the information display means so that displays corresponding to each of the multiple status information stored in the multiple specific memory areas are executed sequentially according to a predetermined display order.

According to feature k10, notifications corresponding to each of the multiple pieces of behavior information are executed sequentially, making it possible to individually grasp the frequency of occurrence of a predetermined event over multiple time periods while limiting the number of information display means. Furthermore, displays corresponding to each of the multiple pieces of behavior information stored in multiple specific memory areas are executed sequentially according to a predetermined display order, making it easier for the amusement hall manager to grasp the type of behavior information being displayed.

Feature k11. The gaming machine described in Feature k10, wherein a predetermined display order is determined in association with the plurality of specific storage areas.

According to feature k11, a predetermined display order for the display corresponding to the aspect information is determined in association with multiple specific storage areas, which simplifies the processing configuration for identifying the type of aspect information to be displayed when starting a new display corresponding to one aspect information.

Feature k12. A gaming machine as described in Feature k10 or k11, wherein the mode information display control means, when causing the information display means to display a display corresponding to the mode information after the predetermined corresponding display has been performed by the information display means, causes the display to start with the display corresponding to the mode information that corresponds to the first position in the predetermined display order.

According to feature k12, after a predetermined corresponding display is performed based on the occurrence of a predetermined display trigger, the display starts from the display corresponding to the aspect information that corresponds to the first position in the predetermined display order. This makes it possible to reconfirm the display corresponding to the aspect information from the first position in the predetermined display order when a predetermined display trigger occurs.

Feature k13. A period lapse determination means (a function for executing the processing of step SA210 in the main CPU 63) for determining that a predetermined period has elapsed from the occurrence of a predetermined period start trigger to the occurrence of a predetermined period end trigger;
a storage execution means (a function of executing the processing of steps SA203 and SA216 in the main CPU 63) for storing, in the plurality of specific storage areas, the behavior information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means, based on the determination by the period elapse determination means that the predetermined period has elapsed;
Equipped with
A gaming machine described in any one of features k10 to k12, characterized in that the storage execution means causes the period correspondence pattern information to be stored in the multiple specific storage areas in the order derived by the information derivation means.

Feature k13 makes it possible to check period correspondence information in the order in which it was derived.

Feature k14. A gaming machine described in any one of Features k1 to k13, wherein the information derivation means executes an information derivation process to derive the status information based on the occurrence of a processing execution trigger, and executes the information derivation process multiple times from the start of derivation of the status information to the completion of derivation of the status information.

According to feature k14, the information derivation process is executed multiple times from the start of derivation of the behavior information until the derivation of the behavior information is completed, thereby reducing the processing load for executing the information derivation process compared to a configuration in which the derivation of the behavior information is completed in a single information derivation process.

Feature k15. A period lapse determination means (a function for executing the processing of step SA210 in the main CPU 63) for determining that a predetermined period has elapsed from the occurrence of a predetermined period start trigger to the occurrence of a predetermined period end trigger;
a storage execution means (a function for executing the processing of steps SA203 and SA216 in the main CPU 63) for storing the status information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means as period-corresponding status information in a status information storage means (a calculation result storage area 234) based on the determination by the period elapse determination means that the predetermined period has elapsed;
Equipped with
the aspect information display control means controls the display of the information display means so that a display corresponding to the period-corresponding aspect information stored in the aspect information storage means is performed,
The gaming machine described in feature k14 is characterized in that the predetermined response display control means determines that the predetermined display trigger has occurred when the period elapsed determination means determines that the predetermined period has elapsed, and causes the predetermined response display to be displayed on the information display means.

According to feature k15, past behavior information derived in units of a predetermined period is stored as period-corresponding behavior information, and a display corresponding to the period-corresponding behavior information is displayed on the information display means. This allows the amusement hall manager to understand the past period-corresponding behavior information derived in units of a predetermined period by checking the information display means. Furthermore, when the predetermined period has elapsed, the information display means displays a predetermined corresponding display, and then displays a display corresponding to the period-corresponding behavior information newly derived upon the elapse of the predetermined period. This allows the amusement hall manager to understand whether the display corresponding to the period-corresponding behavior information on the information display means corresponds to the newly derived period-corresponding behavior information based on the elapse of the predetermined period. Furthermore, since the predetermined corresponding display can be displayed during the period in which the period-corresponding behavior information is being derived, it is possible to prevent a display corresponding to the period-corresponding behavior information from being displayed regardless of the fact that the predetermined period has elapsed and the period-corresponding behavior information is still being derived.

Feature k16. The gaming machine described in Feature k15, wherein the predetermined correspondence display control means causes the information display means to display the predetermined correspondence for a period longer than the longest period required for the information derivation means to derive one of the aspect information.

According to feature k16, when a predetermined period has passed and period correspondence information is in the process of being derived, a predetermined correspondence display is displayed on the information display means.

In addition, with respect to the configuration of features k1 to k16, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature group I>
Feature 11. When a predetermined event occurs as a result of a game being played, history information of the game corresponding to the event is stored in the history storage means (normal counter area 231) (a function for executing normal ball entry management processing in the main CPU 63);
An information deriving means (a function for executing the processing of step SA201 in the main CPU 63) for deriving mode information (base value) corresponding to the game result using the history information stored in the history storage means;
a behavior information storage means (a calculation result storage area 234) for storing the behavior information derived by the information derivation means;
A status information display control means (a function of executing display processing and second timer interrupt processing in the main CPU 63) that controls the display of information display means (the first to fourth notification display devices 201 to 204) so that a display corresponding to the status information stored in the status information storage means is performed;
Equipped with
the behavior information storage means includes a plurality of specific storage areas (a current status area 311, a first history area 312, a second history area 313, and a third history area 314) so as to be able to store each of the plurality of behavior information derived at different times by the information derivation means;
A gaming machine characterized in that the status information display control means controls the information display means so that displays corresponding to each of the multiple status information stored in the multiple specific memory areas are executed sequentially in accordance with a predetermined display order.

According to feature 11, when a predetermined event occurs, corresponding history information is stored in the history storage means. By storing the history information in the gaming machine itself, it is possible to prevent unauthorized access to or unauthorized modification of the history information. Furthermore, the history information stored in the history storage means is used to derive behavior information corresponding to the game results, and the information display means displays a display corresponding to the derived behavior information. This makes it possible to grasp the results of game history management, such as the frequency of occurrence of a predetermined event.

In addition, the behavior information storage means stores multiple pieces of behavior information derived at different times, and notifications corresponding to each of these pieces of behavior information are executed sequentially. This makes it possible to individually grasp the frequency of occurrence of predetermined events over multiple time periods while limiting the number of information display means. Furthermore, since displays corresponding to each of the multiple pieces of behavior information stored in multiple specific memory areas are executed sequentially according to a predetermined display order, it becomes easier for the amusement hall manager to grasp the type of behavior information being displayed.

Feature l2. The gaming machine described in Feature l1, wherein a predetermined display order is determined in association with the plurality of specific storage areas.

According to Feature 12, a predetermined display order for the display corresponding to the aspect information is determined in association with multiple specific storage areas, which simplifies the processing configuration for identifying the type of aspect information to be displayed when starting a new display corresponding to one aspect information.

Feature 13. A predetermined corresponding display control means (a function of executing the processing of step SA320 and the second timer interrupt processing in the main CPU 63) is provided, which causes a predetermined corresponding display (pre-shift display) to be displayed on the information display means before a new display corresponding to the mode information is started based on the occurrence of a predetermined display trigger,
The gaming machine described in feature l1 or l2 is characterized in that when the status information display control means causes the information display means to display a display corresponding to the status information after the specified corresponding display has been performed by the information display means, the status information display control means starts with the display corresponding to the status information that corresponds to the first order in the specified display sequence.

According to feature 13, after a predetermined corresponding display is performed based on the occurrence of a predetermined display trigger, the display starts from the aspect corresponding to the first position in the predetermined display order. This makes it possible to reconfirm the display corresponding to the aspect information from the first position in the predetermined display order when a predetermined display trigger occurs.

Feature 14. A period lapse determination means (a function for executing the process of step SA210 in the main CPU 63) for determining that a predetermined period has elapsed from the occurrence of a predetermined period start trigger to the occurrence of a predetermined period end trigger;
a storage execution means (a function of executing the processing of steps SA203 and SA216 in the main CPU 63) for storing, in the plurality of specific storage areas, the behavior information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means, based on the determination by the period elapse determination means that the predetermined period has elapsed;
Equipped with
A gaming machine described in any one of features l1 to l3, characterized in that the storage execution means causes the period correspondence pattern information to be stored in the multiple specific storage areas in the order derived by the information derivation means.

Feature 14 makes it possible to check period correspondence information in the order in which it was derived.

Feature 15. A gaming machine described in any one of Features 11 to 14, characterized in that it is equipped with a means (a function for executing step SA316 processing and second timer interrupt processing in the main CPU 63) that causes the information display means to return to a pre-switching state (interval non-display state) before displaying a display corresponding to mode information different from the mode information while the display corresponding to the mode information is being displayed.

According to feature 15, when the mode information to be displayed is switched, the information display means returns to its pre-switch state, allowing the amusement hall manager to clearly understand that the mode information to be displayed has been switched.

In addition, with respect to the configuration of features l1 to l5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature m group>
Feature m1. When a predetermined event occurs due to the execution of a game, history information of the corresponding game is stored in the history storage means (normal counter area 231) (a function for executing normal ball entry management processing in the main CPU 63);
An information deriving means (a function for executing the processing of step SA201 in the main CPU 63) for deriving mode information (base value) corresponding to the game result using the history information stored in the history storage means;
Equipped with
The information derivation means executes an information derivation process to derive the status information based on the occurrence of a processing execution trigger, and is characterized in that the information derivation process is executed multiple times from the start of derivation of the status information to the completion of derivation of the status information.

According to feature m1, when a predetermined event occurs, corresponding history information is stored in the history storage means. Storing the history information in the gaming machine itself prevents unauthorized access to or unauthorized modification of the history information. Furthermore, by deriving behavior information corresponding to game results over a predetermined period using the history information stored in the history storage means, it becomes possible to ascertain the results of game history management, such as the frequency of occurrence of a predetermined event. Furthermore, because the information derivation process is executed multiple times from the start of derivation of behavior information until the derivation of that behavior information is completed, the processing load for executing the information derivation process can be reduced compared to a configuration in which the derivation of behavior information is completed in a single information derivation process.

Feature m2. A period lapse determination means (a function for executing the processing of step SA210 in the main CPU 63) for determining that a predetermined period has elapsed from the occurrence of a predetermined period start trigger to the occurrence of a predetermined period end trigger;
a storage execution means (a function for executing the processing of steps SA203 and SA216 in the main CPU 63) for storing the status information corresponding to the game results during the predetermined period derived by the information derivation means using the history information stored in the history storage means as period-corresponding status information in a status information storage means (a calculation result storage area 234) based on the determination by the period elapse determination means that the predetermined period has elapsed;
A mode information display control means (a function of executing display processing and second timer interrupt processing in the main CPU 63) that controls the display of information display means (first to fourth notification display devices 201 to 204) so that a display corresponding to the period-corresponding mode information stored in the mode information storage means is performed;
A predetermined correspondence display control means (a function of executing the processing of step SA320 in the main CPU 63 and the second timer interrupt processing) that causes a predetermined correspondence display to be displayed on the information display means based on the fact that the predetermined period has elapsed determined by the period elapse determination means;
The gaming machine according to feature m1 is characterized by comprising:

According to feature m2, past behavior information derived in units of a predetermined period is stored as period-corresponding behavior information, and a display corresponding to the period-corresponding behavior information is displayed on the information display means. This allows the amusement hall manager to understand past period-corresponding behavior information derived in units of a predetermined period by checking the information display means. Furthermore, when a predetermined period has elapsed, the information display means displays a predetermined corresponding display, and then displays a display corresponding to the period-corresponding behavior information newly derived upon the passage of the predetermined period. This allows the amusement hall manager to understand whether the display corresponding to the period-corresponding behavior information on the information display means corresponds to the newly derived period-corresponding behavior information based on the passage of the predetermined period. Furthermore, because it is possible to display a predetermined corresponding display during the period in which the period-corresponding behavior information is being derived, it is possible to prevent a display corresponding to the period-corresponding behavior information from being displayed regardless of the passage of the predetermined period and the period-corresponding behavior information being in the middle of being derived.

Feature m3. The gaming machine described in Feature m2, wherein the predetermined correspondence display control means causes the information display means to display the predetermined correspondence for a period longer than the longest period required for the information derivation means to derive one of the aspect information.

According to feature m3, when a predetermined period has passed and period correspondence information is in the process of being derived, a predetermined correspondence display is displayed on the information display means.

In addition, with respect to the configuration of features m1 to m3, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group k, feature group l, and feature group m can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, pachinko machines are also known that have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above need to be managed appropriately, and there is still room for improvement in this regard.

<n groups of features>
Feature n1. A setting means (a function for executing the processing of step SA709 in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed based on a first setting-related operation (turning on the setting key insertion portion 68a and pressing the reset button 68c) being performed when the supply of operating power is started (in the 45th embodiment, a function for making a positive determination at step SA412 in the main CPU 63 and a function for making a positive determination at step SA417; in the 46th embodiment, a function for making a positive determination at step SA905 and step SA916 in the main CPU 63 and a function for making a positive determination at step SA917);
When the supply of operating power is started, a notification generating means (a function for executing a setting confirmation process in the main CPU 63) is configured to notify the setting value to be used that is set by the setting means based on a second setting-related operation (an ON operation of the setting key insertion portion 68a).
Equipped with
The gaming machine is characterized in that the situation generation means is equipped with a post-start generation means (in the 45th embodiment, a function of making a positive judgment at step SA412 in the main CPU 63, and in the 46th embodiment, a function of making a positive judgment at steps SA905 and SA916 in the main CPU 63) that causes the situation to become settable when the supply of operating power is stopped during the settable situation and the supply of operating power is then started again, even if the second setting-related operation is performed.

According to feature n1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. Furthermore, in order to change the setting value to be used, a first setting-related operation must be performed when the supply of operating power begins, making it more difficult to fraudulently change the setting value to be used. Furthermore, the setting value to be used is notified by performing a second setting-related operation when the supply of operating power begins, so the amusement hall manager can check the setting value to be used as needed.

In addition, if the supply of operating power is stopped while the setting is possible, the setting will still be possible when the supply of operating power is subsequently started, even if a second setting-related operation is performed. This makes it possible to prioritize changing the setting value of the target device over notifying the user of the setting value when the supply of operating power is subsequently resumed if the supply of operating power is stopped while the setting value of the target device is being changed, preventing gameplay from starting even if the change to the setting value of the target device has not actually been completed.

Feature n2. A gaming machine as described in Feature n1, characterized in that it is equipped with a status notification means (a function for executing the processing of steps SA801 to SA803 in the main CPU 63 and a function for executing second timer interrupt processing) that notifies the user of a setting value that is being changed in the setting possible status.

According to feature n2, when a setting is possible, the setting value being changed is notified, making it possible to change the setting value while understanding the current setting value. Furthermore, by notifying the setting value being changed in this way when a setting is possible, even if a second setting-related operation is performed when the supply of operating power begins, the setting is possible, making it possible to essentially check the setting value, even in a configuration in which the setting value change operation takes priority.

Feature n3. A gaming machine as described in Feature n2, characterized in that the status notification means and the notification generation means both display the target setting value on predetermined display means (first to fourth notification display devices 201 to 204).

According to feature n3, the target setting value is displayed on the specified display means whether the setting value is changed or confirmed, making it possible to use the specified display means for both situations. Furthermore, even if the second setting-related operation is performed when the supply of operating power is started and the setting is enabled, the setting value is displayed on the specified display means when the setting is enabled, so the amusement hall manager who performed the second setting-related operation can visually check the setting value by looking at the specified display means.

Feature n4. The gaming machine described in Feature n3, wherein the status notification means displays a display corresponding to the setting value being changed and a display corresponding to the setting being possible on the predetermined display means.

According to feature n4, when a setting is possible, not only is a display corresponding to the setting value being changed displayed on a specified display means, but also a display corresponding to the setting being possible. This makes it easier for the amusement hall manager to understand that a setting is now possible, even if a second setting-related operation is performed, if the supply of operating power is stopped while the setting is possible and then the supply of operating power is started again.

Feature n5. A gaming machine described in any one of Features n1 to n4, wherein the post-start generation means, when the settable state is established, allows the setting value to be changed from the selected setting value if the supply of operating power is stopped during the settable state.

According to feature n5, even if the supply of operating power is stopped during a setting-enabled state, when the supply of operating power is resumed, it is possible to continue changing the setting value from the state immediately before the supply of operating power was stopped.

Feature n6: A setting correspondence storage means (setting reference area 341) for storing setting correspondence information corresponding to the setting value set by the setting means;
a selection correspondence storage means (setting update area 342) for storing selection correspondence information corresponding to the setting value selected in the setting availability situation;
Equipped with
The situation generation means includes a means for changing the selection correspondence information stored in the selection correspondence storage means so that the setting value to be selected is changed when a change trigger occurs in the settable situation (a function for executing the processing of step SA708 in the main CPU 63),
the setting means, when a termination trigger occurs in the setting possible situation, stores information corresponding to the selection correspondence information stored in the selection correspondence storage means as the setting correspondence information in the setting correspondence storage means, thereby setting the setting value that was a selection target in the setting possible situation as a target for use;
A gaming machine described in any one of features n1 to n5, characterized in that when the settable situation is reached, the post-start generation means enables the setting value to be changed from the setting value corresponding to the selection correspondence information stored in the selection correspondence memory means if the supply of operating power is stopped during the settable situation.

Feature n6 provides a setting correspondence storage means for storing setting correspondence information corresponding to the setting value to be used, and a selection correspondence storage means for storing selection correspondence information corresponding to the setting value being changed in the setting-enabled state. This makes it possible to change the setting value in the setting-enabled state while retaining information about the setting value that was set before the setting-enabled state began. In this case, if the supply of operating power is stopped during the setting-enabled state and then resumed, the setting value is changed from the setting value corresponding to the selection correspondence information that was stored in the selection correspondence storage means when the supply of operating power was stopped. This makes it possible to continue changing the setting value from the state it was in immediately before the supply of operating power was stopped, once the supply of operating power is resumed, even if the supply of operating power is stopped during the setting-enabled state.

Feature n7. The gaming machine described in Feature n6 is characterized in that the situation generation means includes means for enabling the setting value to be changed from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means when the first setting-related operation is performed after the supply of operating power has been stopped during the settable situation and the supply of operating power has subsequently been started (a function for making an affirmative determination in step SA417 in the main CPU 63 in the 45th embodiment, and a function for making an affirmative determination in step SA917 in the main CPU 63 in the 46th embodiment).

According to feature n7, if the supply of operating power is stopped during a setting-enabled state and then resumed, and a second setting-related operation is performed, it is possible to resume changing the setting value from the setting value that was being changed before the supply of operating power was stopped. On the other hand, if the supply of operating power is stopped during a setting-enabled state and then resumed, and a second setting-related operation is performed, the setting value is changed from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means. This makes it possible to vary the initial setting value when starting to change the setting value depending on the operation content when the supply of operating power is resumed.

Feature n8. A gaming machine described in any one of Features n1 to n7, wherein the post-start generation means is capable of causing the setting possible state to be established even if neither the first setting-related operation nor the second setting-related operation is performed when the supply of operating power is stopped during the setting possible state and then the supply of operating power is started again.

According to feature n8, if the supply of operating power is stopped while the setting is possible, the setting can be made possible when the supply of operating power is subsequently started even if neither the first setting-related operation nor the second setting-related operation is performed. Therefore, if the supply of operating power is stopped while changing a setting value, it is possible to actively create a situation in which the setting value can be changed when the supply of operating power is subsequently resumed.

Feature n9. The first setting-related operation includes a setting key insertion section (setting key insertion section 68a) being set to a predetermined corresponding state (ON operated state) by a setting key,
A gaming machine described in any one of features n1 to n8, characterized in that the situation generation means is equipped with a means (a function of executing the processing of steps SA709 and SA710 in the main CPU 63) for terminating the settable situation based on determining that the setting key insertion section has been changed from the predetermined corresponding state to a specific corresponding state (a state in which the setting key has been turned OFF) by the setting key.

According to feature n9, since the setting key insertion unit must be placed in a predetermined corresponding state using a setting key to enter the setting possible state, it is possible to make it more difficult to illegally change the setting value to be used. In this case, the setting possible state does not end simply because the setting key insertion unit is in a specific corresponding state, but rather ends when the setting key insertion unit is changed from the predetermined corresponding state to the specific corresponding state. As a result, even if the supply of operating power is stopped during the setting possible state and then the supply of operating power is resumed when the setting key insertion unit is in a specific corresponding state, the setting possible state does not end immediately. Instead, the setting possible state ends when the setting key insertion unit is changed from the specific corresponding state to the predetermined corresponding state and then again from the predetermined corresponding state to the specific corresponding state. This makes it possible to end the setting possible state at a time convenient for the amusement hall manager.

Feature n10. A gaming machine described in any one of Features n1 to n9, wherein the status generating means causes the setting possible status to occur if the supply of operating power is stopped while the notification generating means is notifying the setting value of the target to be used, and the supply of operating power is then started again, and the first setting-related operation is performed.

According to feature n10, even if the supply of operating power is stopped while the setting value of the target device is being notified, the setting becomes possible if the first setting-related operation is performed when the supply of operating power is subsequently started. This makes it possible to prioritize changing the setting value over checking the setting value.

In addition, with respect to the configuration of features n1 to n10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature group o>
Feature o1. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means for executing predetermined setting-related processing related to the setting value (a function for executing setting value update processing in the main CPU 63, a function for executing setting confirmation processing in the main CPU 63);
an intermediate restart means for restarting the predetermined setting-related processing from the middle after the supply of operating power is started after the supply of operating power has been stopped before the completion of the predetermined setting-related processing (in the 45th embodiment, a function of making a positive determination at step SA412 in the main CPU 63 and a function of making a positive determination at step SA414 in the main CPU 63; in the 46th embodiment, a function of making a positive determination at steps SA905 and SA916 in the main CPU 63);
A gaming machine characterized by comprising:

According to feature o1, the setting value to be used is set from multiple setting value stages corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, even if the supply of operating power is stopped before the specified setting-related processing is completed, the specified setting-related processing will be resumed from where it left off when the supply of operating power is resumed. This makes it possible to continue the specified setting-related processing once the supply of operating power is resumed, even if the supply of operating power is stopped in the middle of the specified setting-related processing.

Feature o2: The setting-related execution means executes the predetermined setting-related process based on a predetermined setting-related operation (if the predetermined setting-related process is a setting value update process, an ON operation of the setting key insertion section 68a and a pressing operation of the reset button 68c; if the predetermined setting-related process is a setting confirmation process, an ON operation of the setting key insertion section 68a),
The gaming machine according to feature o1, wherein the restarting means restarts the predetermined setting-related processing from the middle even if the predetermined setting-related operation is not performed.

According to feature o2, if the supply of operating power is stopped before a specified setting-related process is completed, the specified setting-related process will resume from where it left off even if the specified setting-related operation is not performed, making it possible to prioritize resuming the specified setting-related process from where it left off.

Feature o3: The setting-related execution means executes the predetermined setting-related process based on the predetermined setting-related operation being performed when the supply of operating power is started,
the restarting means restarts the predetermined setting-related processing from the midpoint even if the predetermined setting-related operation is not performed when the supply of operating power is started,
A gaming machine described in feature o2, characterized in that if the supply of operating power is stopped before the specified setting-related processing is completed and the supply of operating power is then started and the specified setting-related operation is performed, the specified setting-related processing is not resumed from the middle by the mid-restart means, but the specified setting-related processing is started anew by the setting-related execution means.

According to feature o3, a predetermined setting-related process is executed based on a predetermined setting-related operation being performed when the supply of operating power is started, making it difficult to fraudulently execute the predetermined setting-related process. In this case, if the supply of operating power is stopped during the predetermined setting-related process and then resumed, the predetermined setting-related process will resume from where it left off even if the predetermined setting-related operation is not performed, making it possible to prioritize resuming the predetermined setting-related process. On the other hand, if the supply of operating power is stopped during the predetermined setting-related process and then resumed, and a predetermined setting-related operation is performed, the predetermined setting-related process will be started anew rather than resumed from where it left off. As a result, if the supply of operating power is stopped during the predetermined setting-related process, it is possible to select either starting the predetermined setting-related process anew or resuming the predetermined setting-related process from where it left off, depending on whether a predetermined setting-related operation was performed when the supply of operating power is resumed.

Feature o4. The predetermined setting-related operation includes the setting key insertion section (setting key insertion section 68a) being set to a predetermined corresponding state (ON operated state) by the setting key,
The gaming machine described in feature o2 or o3 is characterized in that the setting-related execution means is equipped with a means (a function to execute the processing of step SA504 in the main CPU 63, and a function to execute the processing of steps SA709 and SA710 in the main CPU 63) to terminate the specified setting-related processing based on determining that the setting key insertion section has been changed from the specified corresponding state to a specific corresponding state (a state in which the setting key has been turned OFF) by the setting key.

According to feature o4, in order to start a predetermined setting-related process, it is necessary to use the setting key to put the setting key insertion unit into a predetermined corresponding state, making it difficult to fraudulently execute the predetermined setting-related process. In this case, the predetermined setting-related process does not end just because the setting key insertion unit is in a specific corresponding state, but ends when the setting key insertion unit is changed from a predetermined corresponding state to a specific corresponding state. As a result, even if the supply of operating power is stopped before the predetermined setting-related process is completed and the supply of operating power is subsequently started while the setting key insertion unit is in a specific corresponding state, the predetermined setting-related process will not end immediately. Instead, the predetermined setting-related process ends when the setting key insertion unit is changed from a specific corresponding state to a predetermined corresponding state and then again from the predetermined corresponding state. This makes it possible to end the predetermined setting-related process at a time convenient for the amusement hall manager.

Feature o5. A gaming machine described in any one of Features o1 to o4, wherein the predetermined setting-related process is a process for changing a setting value to be used.

According to feature o5, even if the supply of operating power is stopped while changing a setting value, once the supply of operating power is resumed, it is possible to resume changing the setting value from the setting value that was in the middle of being changed. As a result, even if the supply of operating power is stopped while changing a setting value, once the supply of operating power is resumed, it is possible to continue changing the setting value.

Feature o6. The predetermined setting-related process is a process for changing a setting value to be used,
a setting correspondence storage means (setting reference area 341) for storing setting correspondence information corresponding to the setting value to be used;
a selection correspondence storage means (setting update area 342) for storing selection correspondence information corresponding to the setting value selected in the predetermined setting-related processing;
Equipped with
The setting-related execution means
As the predetermined setting-related processing, a means for changing the selection correspondence information stored in the selection correspondence storage means so that the setting value to be selected is changed when a change trigger occurs (a function for executing the processing of step SA708 in the main CPU 63);
As the predetermined setting-related processing, when a termination trigger occurs, information corresponding to the selection correspondence information stored in the selection correspondence storage means is stored in the setting correspondence storage means as the setting correspondence information, thereby setting the setting value that was the selection target as the setting value to be used (a function of executing the processing of step SA709 in the main CPU 63);
Equipped with
A gaming machine described in any one of features o1 to o5, characterized in that the mid-restart means enables the setting value to be changed from the setting value corresponding to the selection correspondence information stored in the selection correspondence memory means when the supply of operating power is stopped before the specified setting-related processing is completed.

Feature o6 includes a setting correspondence storage means for storing setting correspondence information corresponding to the setting value to be used, and a selection correspondence storage means for storing selection correspondence information corresponding to the setting value being changed in the setting-enabled state. This makes it possible to change the setting value in the setting-enabled state while retaining information about the setting value that was set before the setting-enabled state began. In this case, if the supply of operating power is stopped while changing the setting value and then the supply of operating power is resumed, the setting value is changed from the setting value corresponding to the selection correspondence information that was stored in the selection correspondence storage means when the supply of operating power was stopped. As a result, even if the supply of operating power is stopped while changing the setting value, once the supply of operating power is resumed, it is possible to continue changing the setting value from the state it was in immediately before the supply of operating power was stopped.

Feature o7: The setting-related execution means executes the predetermined setting-related process based on a predetermined setting-related operation being performed when supply of operating power is started,
the restarting means restarts the predetermined setting-related processing from the midpoint based on the fact that the predetermined setting-related operation has not been performed when the supply of operating power is started,
The gaming machine described in feature o6 is characterized in that the setting-related execution means is equipped with a means (in the 45th embodiment, a function of making a positive judgment at step SA417 in the main CPU 63, and in the 46th embodiment, a function of making a positive judgment at step SA917 in the main CPU 63) that enables the setting value to be changed from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means when the supply of operating power is stopped before the specified setting-related processing is completed and then the supply of operating power is started again and the specified setting-related operation is performed.

According to feature o7, if the supply of operating power is stopped while a setting value is being changed and then resumed, it is possible to resume changing the setting value from the setting value that was being changed before the supply of operating power was stopped, based on the fact that a specific setting-related operation was not performed. On the other hand, if the supply of operating power is stopped while a setting value is being changed and then resumed, and a specific setting-related operation is performed, the setting value is changed from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means. This makes it possible to vary the initial setting value when starting to change the setting value depending on the operation content when the supply of operating power is resumed.

In addition, with respect to the configuration of features o1 to o7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature p group>
Feature p1. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
and a setting-related execution means (a function for executing a setting value update process in the main CPU 63, a function for executing a setting confirmation process in the main CPU 63) for executing a predetermined setting-related process related to the setting value based on a predetermined setting-related operation (an ON operation of the setting key insertion unit 68a and a pressing operation of the reset button 68c if the predetermined setting-related process is a setting value update process, or an ON operation of the setting key insertion unit 68a if the predetermined setting-related process is a setting confirmation process),
The setting-related execution means is a gaming machine characterized by having a post-supply execution means (in the 45th embodiment, a function of making a positive judgment at step SA412 in the main CPU 63 and a function of making a positive judgment at step SA414 in the main CPU 63; in the 46th embodiment, a function of making a positive judgment at steps SA905 and SA916 in the main CPU 63) that executes the specified setting-related processing if the supply of operating power is stopped before the specified setting-related processing is completed, even if the specified setting-related operation is not performed after the supply of operating power is started thereafter.

According to feature p1, the setting value to be used is set from multiple setting value levels corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. It is also possible to execute a specified setting-related process by performing a specified setting-related operation. In this case, even if the supply of operating power is stopped before the specified setting-related process is completed, the specified setting-related process will be executed when the supply of operating power is resumed, even if the specified setting-related operation has not been performed. This makes it possible to prioritize the execution of the specified setting-related process.

Feature p2: The setting-related execution means executes the predetermined setting-related process based on the predetermined setting-related operation being performed when the supply of operating power is started,
The gaming machine described in feature p1 is characterized in that the post-supply execution means executes the specified setting-related processing when the supply of operating power begins even if the specified setting-related operation is not performed.

According to feature p2, when the supply of operating power is started, a predetermined setting-related process is executed based on the performance of a predetermined setting-related operation, making it difficult to fraudulently execute the predetermined setting-related process. In this case, if the supply of operating power is stopped during the predetermined setting-related process and then resumed, the predetermined setting-related process will be executed even if the predetermined setting-related operation was not performed, making it possible to prioritize the execution of the predetermined setting-related process.

Feature p3: The predetermined setting-related operation includes the setting key insertion section (setting key insertion section 68a) being set to a predetermined corresponding state (ON operated state) by the setting key,
The gaming machine described in feature p1 or p2 is characterized in that the setting-related execution means is equipped with a means (a function to execute the processing of step SA504 in the main CPU 63, and a function to execute the processing of steps SA709 and SA710 in the main CPU 63) to terminate the specified setting-related processing based on determining that the setting key insertion section has been changed from the specified corresponding state to a specific corresponding state (a state in which the setting key has been turned OFF) by the setting key.

According to feature p3, in order to start a predetermined setting-related process, it is necessary to use the setting key to put the setting key insertion unit into a predetermined corresponding state, making it difficult to fraudulently execute the predetermined setting-related process. In this case, the predetermined setting-related process does not end just because the setting key insertion unit is in a specific corresponding state, but ends when the setting key insertion unit is changed from a predetermined corresponding state to a specific corresponding state. As a result, even if the supply of operating power is stopped before the predetermined setting-related process is completed and the supply of operating power is subsequently started while the setting key insertion unit is in a specific corresponding state, the predetermined setting-related process will not end immediately. Instead, the predetermined setting-related process ends when the setting key insertion unit is changed from a specific corresponding state to a predetermined corresponding state and then again from the predetermined corresponding state to a specific corresponding state. This makes it possible to end the predetermined setting-related process at a time convenient for the amusement hall manager.

Feature p4. A gaming machine described in any one of Features p1 to p3, wherein the post-supply execution means does not execute the specified setting-related processing if a specific related operation is performed when the supply of operating power is subsequently started, even if the supply of operating power is stopped before the specified setting-related processing is completed.

According to feature p4, even if the supply of operating power is stopped before the completion of a specified setting-related process, if a specific related operation is performed when the supply of operating power is subsequently started, the specified setting-related process will not be executed. This makes it possible to prevent the specified setting-related process from being executed by performing a specific related operation when the supply of operating power is started, even if the supply of operating power is stopped before the completion of the specified setting-related process, if there is no need to execute the specified setting-related process thereafter.

Feature p5. A gaming machine described in any one of Features p1 to p4, wherein the predetermined setting-related process is a process for notifying the setting value to be used.

According to feature p5, if the supply of operating power is stopped while a setting value is being notified, when the supply of operating power is subsequently started again, notification of the setting value will resume even if a specific setting-related operation is not performed. This makes it possible to prioritize notification of the setting value.

Feature p6. A setting means (a function for executing the processing of step SA709 in the main CPU 63) for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level;
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed based on a specific related operation (turning on the setting key insertion section 68a and pressing the reset button 68c) being performed when the supply of operating power is started (in the 45th embodiment, a function for making a positive determination at step SA412 in the main CPU 63 and a function for making a positive determination at step SA417; in the 46th embodiment, a function for making a positive determination at step SA905 and step SA916 in the main CPU 63 and a function for making a positive determination at step SA917);
Equipped with
the post-supply execution means does not execute the predetermined setting-related process if the supply of operating power is stopped before the predetermined setting-related process is completed and the specific related operation is performed when the supply of operating power is started thereafter,
The gaming machine described in feature p5 is characterized in that the situation generation means causes the setting possible situation to occur when the specific related operation is performed when the supply of operating power is subsequently started, even if the supply of operating power is stopped before the specified setting related processing is completed.

According to feature p6, even if the supply of operating power is stopped while a setting value is being notified, if the supply of operating power is subsequently started and a specific related operation is performed, the setting value will not be notified, but will instead be set in a configurable state in which the setting value can be changed. This makes it possible to prioritize the occurrence of a configurable state over a setting value notification when a specific related operation is performed to set the setting in a configurable state in which the setting value can be changed.

Feature p7. A gaming machine described in any one of Features p1 to p6, wherein the predetermined setting-related process is a process for changing the setting value to be used.

According to feature p7, even if the supply of operating power is stopped while changing the setting value, it is possible to change the setting value once the supply of operating power is resumed. As a result, even if the supply of operating power is stopped while changing the setting value, it is possible to continue changing the setting value once the supply of operating power is resumed.

In addition, with respect to the configuration of features p1 to p7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature q group>
Feature q1. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means for executing predetermined setting-related processing related to the setting value (a function for executing setting value update processing in the main CPU 63, a function for executing setting confirmation processing in the main CPU 63);
Equipped with
The setting-related execution means of the gaming machine is characterized in that even if the supply of operating power is stopped before the specified setting-related processing is completed, if a specific related operation (a RAM clear operation or a setting change operation if the specified setting-related processing is a setting confirmation processing, or a RAM clear operation if the specified setting-related processing is a setting value update processing) is performed when the supply of operating power is started thereafter.

According to feature q1, the setting value to be used is set from multiple setting value stages corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, even if the supply of operating power is stopped before the specified setting-related processing is completed, the specified setting-related processing will not be executed if a specific related operation is performed when the supply of operating power is subsequently started, and the specified setting-related processing does not need to be executed afterwards. As a result, even if the supply of operating power is stopped before the specified setting-related processing is completed, if the specified setting-related processing does not need to be executed afterwards, it is possible to prevent the specified setting-related processing from being executed by performing a specific related operation when the supply of operating power is started.

Feature Q2. The gaming machine described in Feature Q1, wherein the predetermined setting-related process is a process for notifying the setting value to be used.

According to feature q2, even if the supply of operating power is stopped while a setting value is being notified, if a specific related operation is performed when the supply of operating power is subsequently started, the notification of the setting value will not resume. As a result, even if the supply of operating power is stopped while a setting value is being notified, if there is no need to subsequently notify the setting value, it is possible to prevent the notification of the setting value by performing a specific related operation when the supply of operating power is started.

Feature Q3. A gaming machine according to Feature Q1 or Q2, wherein the setting-related execution means executes a predetermined setting-related process based on a predetermined setting-related operation (turning on the setting key insertion unit 68a and pressing the reset button 68c if the predetermined setting-related process is a setting value update process, or turning on the setting key insertion unit 68a if the predetermined setting-related process is a setting confirmation process), and wherein even if the supply of operating power is stopped before the predetermined setting-related process is completed, the predetermined setting-related process is not executed if the specific-related operation is performed instead of the predetermined setting-related operation when the supply of operating power is subsequently started.

Feature q3 makes it difficult to fraudulently execute a specified setting-related process because a specified setting-related operation must be performed to execute the specified setting-related process.

Feature q4. The gaming machine described in Feature q3 is characterized in that the setting-related execution means is equipped with a means for executing the predetermined setting-related processing even if the predetermined setting-related operation has not been performed if the supply of operating power is stopped before the predetermined setting-related processing is completed and the supply of operating power is then started again without the specific related operation being performed (in the 45th embodiment, a function for making a positive determination at step SA412 in the main CPU 63 and a function for making a positive determination at step SA414 in the main CPU 63).

According to feature q4, if the supply of operating power is stopped before a specified setting-related process is completed, it is possible to select whether or not to execute the specified setting-related process without performing the specified setting-related operation, depending on whether or not a specific related operation is performed when the supply of operating power is restarted.

Feature Q5: The predetermined setting-related operation includes the setting key insertion section (setting key insertion section 68a) being set to a predetermined corresponding state (ON operated state) by the setting key,
The gaming machine described in feature q4 is characterized in that the setting-related execution means is equipped with a means (a function to execute the processing of step SA504 in the main CPU 63, and a function to execute the processing of steps SA709 and SA710 in the main CPU 63) to terminate the specified setting-related processing based on determining that the setting key insertion section has been changed from the specified corresponding state to a specific corresponding state (a state in which the setting key has been turned OFF) by the setting key.

According to feature q5, in order to start a predetermined setting-related process, it is necessary to use the setting key to put the setting key insertion unit into a predetermined corresponding state, making it difficult to fraudulently execute the predetermined setting-related process. In this case, the predetermined setting-related process does not end just because the setting key insertion unit is in a specific corresponding state, but ends when the setting key insertion unit is changed from a predetermined corresponding state to a specific corresponding state. As a result, even if the supply of operating power is stopped before the predetermined setting-related process is completed and the supply of operating power is then started again while the setting key insertion unit is in a specific corresponding state, the predetermined setting-related process will not end immediately. Instead, the predetermined setting-related process ends when the setting key insertion unit is changed from a specific corresponding state to a predetermined corresponding state and then again from the predetermined corresponding state. This makes it possible to end the predetermined setting-related process at a time convenient for the amusement hall manager.

Feature q6. A gaming machine described in any one of Features q1 to q5, characterized in that it is equipped with separate execution means for executing a process different from the predetermined setting-related process based on the specific related operation being performed when the supply of operating power is started (a function for executing only a RAM clear process in the main CPU 63 and not a setting value update process if the predetermined setting-related process is a setting confirmation process, or a function for executing a RAM clear process and a setting value update process in the main CPU 63; a function for executing only a RAM clear process in the main CPU 63 in the 45th embodiment and not a setting value update process if the predetermined setting-related process is a setting value update process).

Feature q6 makes it possible to use a specific related operation performed to execute another process to prevent a specific setting-related process from being executed if the supply of operating power is stopped before the completion of the specific setting-related process and the supply of operating power is subsequently started.

Feature Q7. The gaming machine described in Feature Q6 is characterized in that the separate execution means executes the separate process based on the specific related operation being performed when the supply of operating power is subsequently started, even if the supply of operating power is stopped before the specified setting-related process is completed.

According to feature q7, even if the supply of operating power is stopped before a specific setting-related process is completed, if the supply of operating power is subsequently started and a specific related operation is performed, it is possible to prioritize the execution of another process over the specific setting-related process.

Feature Q8. A gaming machine according to Feature Q6 or Q7, wherein the predetermined setting-related process is a process for notifying the setting value to be used, and the separate process is a process for changing the setting value to be used.

According to feature q8, even if the supply of operating power is stopped while a setting value is being notified, if a specific related operation is performed when the supply of operating power is subsequently started, the notification of the setting value will not resume. As a result, even if the supply of operating power is stopped while a setting value is being notified, if there is no need to subsequently notify the setting value, it is possible to prevent the notification of the setting value by performing a specific related operation when the supply of operating power is started. Furthermore, as an operation to prevent the notification of the setting value in this way, it is possible to use a specific related operation for executing a process to change the setting value.

In addition, with respect to the configuration of features q1 to q8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature r group>
Feature r1. A setting means (a function for executing the processing of step SA709 in the main CPU 63) for setting a setting value to be used from among multiple setting values corresponding to the player's advantage level;
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed (in the 45th embodiment, a function for making a positive determination in step SA412 in the main CPU 63 and a function for making a positive determination in step SA417; in the 46th embodiment, a function for making a positive determination in step SA905 and step SA916 in the main CPU 63 and a function for making a positive determination in step SA917);
a setting correspondence storage means (setting reference area 341) for storing setting correspondence information corresponding to the setting value set by the setting means;
a selection correspondence storage means (setting update area 342) for storing selection correspondence information corresponding to the setting value selected in the setting availability situation;
Equipped with
The situation generation means includes a means for changing the selection correspondence information stored in the selection correspondence storage means so that the setting value to be selected is changed when a change trigger occurs in the settable situation (a function for executing the processing of step SA708 in the main CPU 63),
The setting means is characterized in that when an end trigger occurs in the settable situation, the setting means stores information corresponding to the selection correspondence information stored in the selection correspondence storage means as the setting correspondence information in the setting correspondence storage means, thereby setting the setting value that was the selection target in the settable situation as the target for use.

According to feature r1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will hope that the more advantageous setting value will be the one to be used. In this case, by providing a setting correspondence storage means that stores setting correspondence information corresponding to the setting value to be used and a selection correspondence storage means that stores selection correspondence information corresponding to the setting value being changed in the setting possible situation, it is possible to change the setting value in the setting possible situation while storing and retaining information about the setting value that was set before the setting possible situation began.

Feature r2. A gaming machine according to Feature r1, wherein the situation generation means is equipped with first change execution means (a function of making a positive determination in step SA701 in the main CPU 63) that enables a change of the setting value corresponding to the selection correspondence information stored in the selection correspondence storage means in the previous setting correspondence information in the ...

Feature r2. When a setting possible situation is started after the setting possible situation has ended before a termination trigger occurs, the setting value is changed from the setting value corresponding to the selection correspondence information stored in the selection correspondence storage means. As a result, even if the setting possible situation has ended before a termination trigger occurs, when the setting possible situation is resumed, it is possible to continue changing the setting value from the setting value last selected in the previous setting possible situation.

Feature r3. A gaming machine according to Feature r2, wherein the situation generation means is equipped with second change execution means (a function of making a negative determination in step SA701 in the main CPU 63) that enables a change of the setting value from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means in the setting correspondence situation that occurs after the setting possible situation has ended before the termination trigger occurs.

Feature r3 not only makes it possible to resume changing the setting value from the setting value last selected in the previous setting situation when a setting situation begins after the setting situation has ended before a termination trigger occurs, but also makes it possible to change the setting value from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means when a setting situation begins after the setting situation has ended before a termination trigger occurs. This makes it possible to vary the initial setting value when starting to change the setting value depending on the situation when the setting situation is resumed.

Feature r4. A gaming machine according to Feature r3, wherein the second change execution means enables the setting value to be changed from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means in the setting possible situation that occurs after the setting possible situation that ended due to the occurrence of the termination trigger.

According to feature r4, in normal setting situations, the setting value will be changed from the currently used setting value.

Feature r5. A gaming machine according to Feature r3 or r4, characterized in that the situation generation means includes means (a function for executing the processing of steps SA405, SA412, and SA417 in the main CPU 63) for causing one of the following situations to occur: a situation in which the setting value can be changed from the setting value corresponding to the selection correspondence information stored in the selection correspondence storage means, and a situation in which the setting value can be changed from the setting value corresponding to the setting correspondence information stored in the setting correspondence storage means, based on a specific related operation being performed when the setting possible situation begins after the setting possible situation has ended before the trigger for ending the setting possible situation occurs.

According to feature r5, when a setting possible situation begins after a setting possible situation has ended before an end trigger occurs, the amusement hall manager can choose whether to resume changing the setting value from the setting value last selected in the previous setting possible situation, or to start changing the setting value from the setting value currently in use.

Feature r6. A gaming machine described in any one of Features r1 to r5, characterized in that it is equipped with a means (a function for executing the processing of steps SA801 to SA803 in the main CPU 63) for causing a display of a setting value corresponding to the selection correspondence information stored in the selection correspondence storage means in the setting possible situation to be displayed on a predetermined display means (first to fourth notification display devices 201 to 204).

Feature r6 makes it possible to change setting values while checking the setting values being changed in a setting-enabled situation.

Feature r7. A gaming machine described in any one of Features r1 to r6, characterized in that it is equipped with a means (a function for executing the processing of steps SA601 to SA603 in the main CPU 63) for causing a setting value corresponding to the setting correspondence information stored in the setting correspondence storage means to be displayed on a predetermined display means (first to fourth notification display devices 201 to 204) when the setting is not possible.

Feature r7 makes it possible to check the current settings of the target device as needed.

In addition, with respect to the configuration of features r1 to r7, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group n, feature group o, feature group p, feature group q, and feature group r can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to optimize the configuration of the setting values that determine the machine's advantageous degree, and there is still room for improvement in this regard.

<Features group>
Feature s1. A predetermined response start means for starting a predetermined response process (setting confirmation process, setting value update process) based on the predetermined key insertion section (setting key insertion section 68a) being set to a predetermined response state (ON operated state) by a predetermined key (in the 45th embodiment, a function for making an affirmative determination in step SA413 in the main CPU 63 and a function for making an affirmative determination in step SA417 in the main CPU 63; in the 46th embodiment, a function for making an affirmative determination in step SA913 in the main CPU 63 and a function for making an affirmative determination in step SA917);
A predetermined response termination means (a function for executing the processes of steps SA709 and SA710 in the main CPU 63) that terminates the predetermined response process based on the determination that the predetermined key insertion unit has been changed from the predetermined response state to a specific response state (a state in which the predetermined key has been turned off) by the predetermined key;
A gaming machine characterized by comprising:

According to feature s1, in order to start the predetermined response process, it is necessary to use a predetermined key to put the predetermined key insertion unit into a predetermined response state, making it difficult to fraudulently start the predetermined response process. In this case, the predetermined response process does not end just because the predetermined key insertion unit is in a specific response state, but rather ends when the predetermined key insertion unit changes from a predetermined response state to a specific response state. As a result, even if the predetermined response process is started when the predetermined key insertion unit is in a specific response state for some reason, the predetermined response process will not end immediately. Instead, the predetermined response process will end when the predetermined key insertion unit is changed from a specific response state to a predetermined response state and then again from the predetermined response state to a specific response state, making it possible for the amusement hall manager to end the predetermined response process at a time convenient for them.

Feature s2. A gaming machine as described in Feature s1, characterized in that it is equipped with separate start means for starting the predetermined response processing when the predetermined key insertion unit is in the specific response state based on the establishment of a specific start condition (in the 45th embodiment, a function for making a positive determination in step SA412 in the main CPU 63 and a function for making a positive determination in step SA414 in the main CPU 63; in the 46th embodiment, a function for making a positive determination in steps SA905 and SA916 in the main CPU 63).

Feature s2 allows the predetermined response process to be initiated even when the predetermined key insertion unit is in a specific response state based on the satisfaction of a specific start condition, thereby diversifying the trigger for initiating the predetermined response process. However, while this configuration initiates the predetermined response process when the predetermined key insertion unit is in a specific response state, with the configuration of feature s1 above, the predetermined response process does not end simply because the predetermined key insertion unit is in a specific response state, but rather ends when the predetermined key insertion unit changes from a specific response state to a specific response state. As a result, even if the predetermined response process is initiated when the predetermined key insertion unit is in a specific response state, it does not end immediately. Instead, the predetermined response process ends when the predetermined key insertion unit is changed from a specific response state to a predetermined response state and then again from the predetermined response state to a specific response state, making it possible for the amusement hall manager to end the predetermined response process at a time convenient for them.

Feature s3: The predetermined response starting means starts the predetermined response process based on whether the predetermined key insertion unit is in the predetermined response state when the supply of operating power is started,
A gaming machine described in feature S2, characterized in that the specific start condition is met when the supply of operating power is stopped while the specified response processing is being executed and then the supply of operating power is resumed.

According to feature s3, when the supply of operating power is started, the predetermined response process is started based on whether the predetermined key insertion unit is in a predetermined response state, making it difficult to fraudulently start the predetermined response process. Furthermore, even if the supply of operating power is stopped while the predetermined response process is being executed, if the specific start condition is met when the supply of operating power is resumed, the predetermined response process will start even if the predetermined key insertion unit is not in a predetermined response state. This makes it possible to prioritize the start of the predetermined response process if the predetermined response process ends prematurely.

Feature s4: A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63) is provided;
A gaming machine according to any one of features s1 to s3, wherein the predetermined corresponding processing is processing related to the set value.

Feature s4 makes it possible to achieve the above-mentioned excellent effects for processing related to set values.

In addition, with respect to the configuration of features s1 to s4, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above group of features can solve the following problems:

Pachinko machines and slot machines are well-known gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed by, for example, a control means to determine whether or not to create a gaming state advantageous to the player.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary for the control means to ensure that processing progresses smoothly, and there is still room for improvement in this regard.

<Feature group>
Feature t1. Setting means for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage (in the first embodiment, a function for executing the processing of steps S205 to S207 in the master CPU 63; in the eleventh embodiment, a function for executing the processing of steps S3106 to S3108 in the master CPU 63; in the twelfth embodiment, a function for executing the processing of steps S3207 to S3209 in the master CPU 63; in the twenty-second embodiment, a function for executing the processing of steps S5605 to S5607 in the master CPU 63; in the forty-ninth embodiment, a function for executing the processing of step SB311 in the master CPU 63; and in the fifty-third embodiment, a function for executing the processing of step SB915 in the master CPU 63);
a situation generating means for bringing about a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed (a function for making a positive determination in step S103 in the main CPU 63 in the first embodiment, a function for making a positive determination in steps S5503 to S5507 in the main CPU 63 in the 22nd embodiment, a function for making a positive determination in step SB113 in the main CPU 63 in the 49th embodiment, and a function for making a positive determination in step SB812 in the main CPU 63 in the 53rd embodiment);
a start response means for changing the setting value from a predetermined start response setting value when the setting possible state is reached (in the first embodiment, a function for executing the processing of step S201 in the main CPU 63; in the eleventh embodiment, a function for executing the processing of step S3102 in the main CPU 63; in the twelfth embodiment, a function for executing the processing of step S3203 in the main CPU 63; in the twenty-second embodiment, a function for executing the processing of step S5601 in the main CPU 63; in the forty-ninth embodiment, a function for executing the processing of step SB304 in the main CPU 63; and in the fifty-third embodiment, a function for executing the processing of step SB905 in the main CPU 63);
A gaming machine characterized by comprising:

According to feature t1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, when a setting-enabled situation occurs, the setting value is changed from a predetermined starting setting value. This makes it possible to change the setting value from a certain starting setting value in a setting-enabled situation, regardless of the setting value to be used before the setting-enabled situation occurs. This makes the operation of changing the setting value easy to understand for the operator.

Feature t2. A gaming machine according to Feature t1, wherein the start-corresponding setting value is the setting value ("Setting 1") with the lowest advantageous degree.

According to feature t2, when a setting-enabled situation occurs, the setting value is changed from the setting value with the lowest advantage. This means that even if the amusement hall manager unintentionally ends the setting-enabled situation immediately after it occurs, the setting value with the lowest advantage will be used, preventing unintended disadvantages to the amusement hall even if games are played in such a situation.

Feature t3: A setting correspondence storage means (setting reference area 341) for storing setting correspondence information corresponding to the setting value set by the setting means;
a selection correspondence storage means (setting update area 342) for storing selection correspondence information corresponding to the setting value selected in the setting availability situation;
Equipped with
The situation generation means includes a means for changing the selection correspondence information stored in the selection correspondence storage means so that the setting value to be selected is changed when a change trigger occurs in the settable situation (a function for executing the processing of steps SB307 and SB310 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of steps SB908 and SB914 in the main CPU 63 in the 53rd embodiment),
the setting means, when a termination trigger occurs in the setting possible situation, stores information corresponding to the selection correspondence information stored in the selection correspondence storage means as the setting correspondence information in the setting correspondence storage means, thereby setting the setting value that was a selection target in the setting possible situation as a target for use;
A gaming machine described in feature t1 or t2, characterized in that the start response means stores the selection response information corresponding to the setting value of the start response in the selection response memory means when the setting possible situation occurs.

Feature t3 includes a setting correspondence storage means for storing setting correspondence information corresponding to the setting value to be used, and a selection correspondence storage means for storing selection correspondence information corresponding to the setting value being changed in the setting-enabled state. This makes it possible to change the setting value in the setting-enabled state while retaining information about the setting value that was set before the setting-enabled state began.

Feature t4. The gaming machine described in Feature t3 is characterized by including a means (a function for executing the processing of steps SA801 to SA803 in the main CPU 63) for causing a display of the setting value corresponding to the selection correspondence information stored in the selection correspondence storage means in the setting possible situation to be performed on a predetermined display means (first to fourth notification display devices 201 to 204).

Feature t4 makes it possible to change setting values while checking the setting values being changed in a setting-enabled situation.

Feature t5. A gaming machine according to feature t3 or t4, characterized in that it is equipped with a means (a function for executing the processing of steps SA601 to SA603 in the main CPU 63) for causing a setting value corresponding to the setting correspondence information stored in the setting correspondence storage means to be displayed on a predetermined display means (first to fourth notification display devices 201 to 204) when the setting is not possible.

Feature t5 makes it possible to check the current settings of the target device as needed.

In addition, for the configuration of features t1 to t5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group t can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to optimize the configuration of the setting values that determine the machine's degree of advantage, and there is still room for improvement in this regard.

<Feature u group>
Feature u1. First control means (MPU 62),
a second control means (acoustic/optical side MPU 352) that executes control corresponding to the information transmitted by the first control means;
In a gaming machine equipped with
The first control means
a first transmitting means (a function for executing the processing of step SB314 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB918 in the main CPU 63 in the 53rd embodiment) for transmitting first start correspondence information (a return command at the time of update) based on the fact that the first start situation has occurred when the supply of operating power has started;
a second transmitting means for transmitting second start response information (a return command at the time of confirmation or a return command at the time of clearing) based on the fact that the second start situation has occurred when the supply of operating power has started (a function for executing the processing of step SB118 or step SB207 in the main CPU 63 in the 49th embodiment, a function for executing the processing of step SB618 in the main CPU 63 in the 51st embodiment, a function for executing the processing of step SB725 in the main CPU 63 in the 52nd embodiment, a function for executing the processing of step SB816 in the main CPU 63 in the 53rd embodiment, and a function for executing the processing of step SC118 in the main CPU 63 in the 54th embodiment);
A gaming machine characterized by comprising:

According to feature u1, in a configuration in which control corresponding to information transmitted by a first control means is executed by a second control means, when the supply of operating power is started, the first control means transmits first start response information based on the first start status, and transmits second start response information based on the second start status. This makes it possible for control corresponding to the type of start status when the supply of operating power is started to be performed not only by the first control means but also by the second control means.

Feature u2. A gaming machine according to Feature u1, characterized in that the first control means is configured such that when the supply of operating power is started, at least some of the processing content of the processing at the start of the supply of operating power (steps SB101 to SB122 in the 49th embodiment, steps SB601 to SB622 in the 51st embodiment, steps SB701 to SB729 in the 52nd embodiment, steps SB801 to SB818 and steps SB823 to SB826 in the 53rd embodiment, and steps SC101 to SC120 and steps SC125 to SC128 in the 54th embodiment) differs depending on whether the supply of operating power is started in the first start status or the second start status.

According to feature u2, when the supply of operating power is started, at least part of the processing performed by the first control means at the start of the supply of operating power differs depending on whether the start status is the first start status or the second start status, making it possible to have the first control means execute processing corresponding to the start status as processing at the start of the supply of operating power.

Feature u3. The second control means
a start response execution means (a function of making a positive determination in step SB405 in the acoustic/optical side CPU 353) that executes a start response process regardless of whether the first start response information or the second start response information is received;
a predetermined response execution means (a function of executing the processes of steps SB407, SB409, and SB411 in the acoustic/optical side CPU 353) that executes a predetermined response process when one of the first start response information and the second start response information is received, and does not execute the predetermined response process when the other of the first start response information and the second start response information is received;
A gaming machine according to feature u1 or u2, characterized by comprising:

According to feature u3, the second control means executes the start response process regardless of whether it receives the first start response information or the second start response information, so it is possible to have the second control means execute the start response process in response to the transmission of either start response information from the first control means. Furthermore, the second control means executes the predetermined response process when it receives either the first start response information or the second start response information, but does not execute the predetermined response process when it receives the other start response information. This makes it possible for control corresponding to the type of start situation when the supply of operating power is started to be performed not only by the first control means but also by the second control means.

Feature u4. One of the first start situation and the second start situation occurs when a predetermined start-responsive operation (RAM clear operation, setting change operation, or setting confirmation operation) is performed when the supply of operating power is started,
A gaming machine described in feature u3, characterized in that the other of the first start situation and the second start situation occurs when the supply of operating power is started and the specified start-response operation is not performed.

Feature u4 makes it possible to vary the content of control executed by not only the first control means but also the second control means depending on whether a predetermined start-responsive operation has been performed when the supply of operating power has started.

Feature u5. The first control means is configured to execute a process (steps S8907 to S8920) for controlling the progress of a game after transmitting any one of a plurality of types of start response information including the first start response information and the second start response information,
The gaming machine described in feature u3 or u4 is characterized in that the second control means is configured to execute processing corresponding to the progress of the game (steps SB412 to SB414) after receiving any of the multiple types of start response information.

According to feature u5, the first control means transmits one of the start response information before starting processing to control the progress of the game, and the second control means executes processing corresponding to the progress of the game after receiving one of the start response information. This makes it possible for the second control means to execute processing corresponding to the progress of the game after the first control means is in a situation where it can execute processing to control the progress of the game. In this case, by having the configuration of feature u3, it becomes possible for the second control means to recognize the trigger for starting processing corresponding to the progress of the game by utilizing multiple pieces of start response information that determine whether or not the second control means executes a predetermined response process.

Feature u6. The first control means
means for executing a common response process when the supply of operating power is started, regardless of whether the first start situation is reached or the second start situation is reached (in the 49th embodiment, a function for executing the processes of steps SB101 to SB103 in the main CPU 63; in the 51st embodiment, a function for executing the processes of steps SB601 to SB603 in the main CPU 63; in the 52nd embodiment, a function for executing the processes of steps SB701 and SB702 in the main CPU 63; in the 53rd embodiment, a function for executing the processes of steps SB801 to SB803 in the main CPU 63; and in the 54th embodiment, a function for executing the processes of steps SC101 to SC103 in the main CPU 63);
means for executing a specific response process when the supply of operating power has started and one of the first and second start situations has occurred, and not executing the specific response process when the supply of operating power has started and the other of the first and second start situations has occurred (in the 49th embodiment, a function for executing the process of step SB112, step SB115, or step SB117 in the main CPU 63; in the 51st embodiment, a function for executing the process of step SB612, step SB615, or step SB617 in the main CPU 63; in the 52nd embodiment, a function for executing the process of step SB711, step SB718, or step SB721 in the main CPU 63; in the 53rd embodiment, a function for executing the process of step SB810, step SB813, or step SB815 in the main CPU 63; and in the 54th embodiment, a function for executing the process of step SC111, step SC115, or step SC117 in the main CPU 63);
A gaming machine according to any one of features u1 to u5, characterized in that it is equipped with:

According to feature u6, the first control means executes a common response process regardless of whether the first start situation or the second start situation is present, and executes a specific response process when the start situation is either the first start situation or the second start situation. This allows the first control means to execute a common response process regardless of the start situation, while allowing the first control means to execute a process corresponding to the type of start situation. In this case, with the configuration of feature u1 above, the first control means transmits first start response information based on the first start situation and transmits second start response information based on the second start situation, so that when the supply of operating power is started, control corresponding to the type of start situation can be performed not only by the first control means but also by the second control means.

Feature u7. The first control means
A setting means for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level (a function for executing the processing of step SB311 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB915 in the main CPU 63 in the 53rd embodiment);
a first response execution means for determining, based on a first setting-related operation (turning on the setting key insertion portion 68a and pressing the reset button 68c) when the supply of operating power is started, that the first start situation is reached, and for bringing about a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed (in the 49th embodiment, a function for making an affirmative determination at step SB114 in the main CPU 63; in the 51st embodiment, a function for making an affirmative determination at step SB614 in the main CPU 63; in the 52nd embodiment, a function for making an affirmative determination at step SB717 in the main CPU 63; in the 53rd embodiment, a function for making an affirmative determination at step SB812 in the main CPU 63; and in the 54th embodiment, a function for making an affirmative determination at step SC113 in the main CPU 63);
A second response execution means (a function for executing a setting confirmation process in the main CPU 63) that, when the supply of operating power is started, is configured to notify the setting value to be used that is set by the setting means based on the second setting-related operation (the ON operation of the setting key insertion portion 68a) being performed, as the second start situation;
A gaming machine described in any one of features u1 to u6, characterized in that it is equipped with:

According to feature u7, the target setting value is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be selected. Furthermore, in order to change the target setting value, a first setting-related operation must be performed when the supply of operating power begins, making it difficult to illegally change the target setting value. Furthermore, the target setting value is notified by performing a second setting-related operation when the supply of operating power begins, allowing the amusement hall manager to check the target setting value as needed. In this case, with the configuration of feature u1, the first control means transmits first start response information based on the first start status and transmits second start response information based on the second start status. This allows the second control means to perform different control depending on whether the setting is available or not and whether the target setting value is notified.

Feature u8. The first control means
A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A first response execution means (a function of executing a setting value update process or a setting confirmation process in the main CPU 63) that executes a predetermined setting-related process regarding the setting value based on the first start situation when the supply of operating power is started;
a second response execution means for executing a response process different from the predetermined setting-related process based on the second start status when the supply of operating power is started (a function for executing the process of step SB117 in the main CPU 63 in the 49th embodiment, a function for executing the process of step SB617 in the main CPU 63 in the 51st embodiment, a function for executing the process of step SB721 in the main CPU 63 in the 53rd embodiment, a function for executing the process of step SB815 in the main CPU 63, and a function for executing the process of step SC117 in the main CPU 63 in the 54th embodiment);
A gaming machine described in any one of features u1 to u7, characterized in that it is equipped with:

According to feature u8, the setting value to be used is set from multiple setting value stages corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. Furthermore, when the supply of operating power is started, a predetermined setting-related process related to the setting value is executed based on the first start status, and a different response process different from the predetermined setting-related process is executed based on the second start status when the supply of operating power is started. This makes it possible to have the predetermined setting-related process executed or not executed depending on the start status when the supply of operating power is started. In this case, with the configuration of feature u1 above, the first control means transmits first start-related information based on the first start status and transmits second start-related information based on the second start status, so it is possible for the second control means to perform different control depending on whether the predetermined setting-related process is executed or not by the first control means.

Feature u9. A gaming machine described in Feature u8, wherein the second response execution means executes processing to initialize a predetermined memory area provided in the first control means as the separate response processing.

Feature u9 makes it possible to execute a specified setting-related process or initialize a specified storage area of the first control means depending on the start status when the supply of operating power is started. In this case, with the configuration of feature u1 described above, the first control means transmits first start-response information based on the first start status and transmits second start-response information based on the second start status. This makes it possible for the second control means to perform different control depending on whether the specified setting-related process is executed by the first control means or the specified storage area is initialized.

Feature u10. The second control means
a means for storing time correspondence information measured by a time measurement means (RTC 356) that enables time measurement in a time correspondence storage means (RTC memory 357) when one of the first start correspondence information and the second start correspondence information is received (a function for executing the processing of step SB407 in the sound-and-light side CPU 353 in the 49th embodiment, and a function for executing the processing of step SB507 in the sound-and-light side CPU 353 in the 50th embodiment);
means for executing time-corresponding processing when the processing execution timing is reached based on the time-corresponding information stored in the time-corresponding storage means (a function for executing the processing of step SB413 in the sound-and-light side CPU 353 in the 49th embodiment, and a function for executing the processing of step SB513 in the sound-and-light side CPU 353 in the 50th embodiment);
A gaming machine described in any one of features u1 to u9, characterized in that it is equipped with:

According to feature u10, the second control means executes time-related processing when the processing execution timing is reached based on the time-related information stored in the time-related storage means, making it possible to execute time-related processing at a predetermined time. In this case, when one of the first start-related information and the second start-related information is received, the time-related information measured by the time measurement means is stored in the time-related storage means. This makes it possible to select between situations in which time-related information is newly stored in the time-related storage means and situations in which it is not newly stored.

In addition, with respect to the configuration of features u1 to u10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature v group>
Feature v1. A time storage execution means (a function for executing the processing of step SB407 in the sound/light side CPU 353 in the 49th embodiment, and a function for executing the processing of step SB507 in the sound/light side CPU 353 in the 50th embodiment) for storing time correspondence information measured by a time measurement means (RTC 356) that enables time measurement in a time correspondence storage means (RTC memory 357);
a time correspondence execution means for executing time correspondence processing when the processing execution timing is reached based on the time correspondence information stored in the time correspondence storage means (a function for executing the processing of step SB413 in the sound/light side CPU 353 in the 49th embodiment, and a function for executing the processing of step SB513 in the sound/light side CPU 353 in the 50th embodiment);
Equipped with
The time memory execution means stores the time correspondence information measured by the time measurement means in the time correspondence storage means based on the fact that a first start situation has occurred when the supply of operating power has started (in the 49th embodiment, when the power to the pachinko machine 10 is turned on when no operation has been performed, and in the 50th embodiment, when the power to the pachinko machine 10 is turned on when a RAM clear operation, a setting change operation, or a setting confirmation operation has been performed), and does not store the time correspondence information measured by the time measurement means in the time correspondence storage means based on the fact that a second start situation has occurred when the supply of operating power has started (in the 49th embodiment, when the power to the pachinko machine 10 is turned on when a RAM clear operation, a setting change operation, or a setting confirmation operation has been performed, and in the 50th embodiment, when the power to the pachinko machine 10 is turned on when no operation has been performed).

According to feature v1, time-related processing is executed when the processing execution timing is reached based on the time-related information stored in the time-related storage means, making it possible to execute time-related processing at a predetermined time. In this case, if the supply of operating power starts and the first start situation occurs, the time-related information measured by the time measurement means is stored in the time-related storage means, and if the supply of operating power starts and the second start situation occurs, the time-related information is not stored in the time-related storage means. This makes it possible to select between situations in which time-related information is newly stored in the time-related storage means and situations in which it is not newly stored.

Feature v2. One of the first start situation and the second start situation occurs when a predetermined start-responsive operation (a RAM clear operation, a setting change operation, or a setting confirmation operation) is performed when the supply of operating power is started,
A gaming machine described in feature v1, characterized in that the other of the first start situation and the second start situation occurs when the supply of operating power is started and the specified start-response operation is not performed.

Feature v2 makes it possible to select between a situation in which time correspondence information is newly stored in the time correspondence storage means and a situation in which it is not newly stored, depending on whether or not a specified start-up correspondence operation is performed when the supply of operating power is started.

Feature v3. The second start situation occurs when a predetermined start-responsive operation (a RAM clear operation, a setting change operation, or a setting confirmation operation) is performed when the supply of operating power is started,
A gaming machine described in feature v1 or v2, characterized in that the first start situation occurs when the supply of operating power is started and the specified start-response operation is not performed.

According to feature v3, if the specified start-related operation is not performed when the supply of operating power is started, time correspondence information is newly stored in the time correspondence storage means, and if the specified start-related operation is performed when the supply of operating power is started, time correspondence information is not stored in the time correspondence storage means. This makes it possible to basically store time correspondence information newly in the time correspondence storage means when the supply of operating power is started, while performing the specified start-related operation as necessary to prevent time correspondence information from being stored in the time correspondence storage means.

Feature v4. A means for executing a specific response process based on whether the supply of operating power has started and one of the first and second start situations has occurred, and not executing the specific response process based on whether the supply of operating power has started and the other of the first and second start situations has occurred (in the 49th embodiment, a function for executing the processing of step SB112, step SB115, or step SB117 in the main CPU 63; in the 51st embodiment, a function for executing step SB612, step SB613, or step SB614 in the main CPU 63) a function to execute processing of step SB615 or step SB617 in the 52nd embodiment, a function to execute processing of step SB711, step SB718 or step SB721 in the main CPU 63 in the 53rd embodiment, a function to execute processing of step SB810, step SB813 or step SB815 in the main CPU 63 in the 54th embodiment, a function to execute processing of step SC111, step SC115 or step SC117 in the main CPU 63.

According to feature v4, specific response processing is executed when the start status is either the first start status or the second start status. In this case, the configuration of feature v1 is provided, and time correspondence information is newly stored in the time correspondence storage means based on the first start status, and time correspondence information is not stored in the time correspondence storage means based on the second start status. This makes it possible to associate whether or not specific response processing is executed with whether or not new time correspondence information is stored.

Feature v5. A gaming machine according to any one of Features v1 to v4, characterized in that it comprises means for executing a specific response process based on the second start status being established when the supply of operating power has started, and for not executing the specific response process based on the first start status being established when the supply of operating power has started (in the 49th embodiment, a function for executing the process of step SB112, step SB115, or step SB117 in the main CPU 63; in the 51st embodiment, a function for executing the process of step SB612, step SB615, or step SB617 in the main CPU 63; in the 52nd embodiment, a function for executing the process of step SB711, step SB718, or step SB721 in the main CPU 63; in the 53rd embodiment, a function for executing the process of step SB810, step SB813, or step SB815 in the main CPU 63; and in the 54th embodiment, a function for executing the process of step SC111, step SC115, or step SC117 in the main CPU 63).

According to feature v5, specific response processing is executed when the second start situation is reached between the first and second start situations. In this case, the configuration of feature v1 is provided, and time correspondence information is newly stored in the time correspondence storage means based on the first start situation, and time correspondence information is not stored in the time correspondence storage means based on the second start situation. This makes it possible to prevent new time correspondence information from being stored in the time correspondence storage means when specific response processing is executed.

Feature v6. A gaming machine according to Feature v4 or v5, characterized in that it is equipped with means for executing common response processing regardless of whether the first start status or the second start status is established when the supply of operating power is started (in the 49th embodiment, a function for executing the processing of steps SB101 to SB103 in the main CPU 63; in the 51st embodiment, a function for executing the processing of steps SB601 to SB603 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of steps SB701 and SB702 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of steps SB801 to SB803 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of steps SC101 to SC103 in the main CPU 63).

According to feature v6, a common response process is executed regardless of whether the first or second start status is met, while a specific response process is executed when the start status is either the first or second start status. This allows the common response process to be executed regardless of the start status, while also allowing the process corresponding to the type of start status to be executed.

Feature v7. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function of executing a setting value update process or a setting confirmation process in the main CPU 63) that executes a predetermined setting-related process related to the setting value when the supply of operating power is started;
Equipped with
A gaming machine described in any one of features v1 to v6, characterized in that the setting-related execution means executes the specified setting-related processing based on whether one of the first start status and the second start status is reached when the supply of operating power is started.

According to feature v7, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. Furthermore, when the supply of operating power begins, a predetermined setting-related process is executed based on whether the start status is one of the first and second start statuses. This makes it possible to associate whether the predetermined setting-related process is executed with whether new time correspondence information is stored.

Feature v8. A gaming machine described in any one of Features v1 to v7, characterized in that it comprises means for initializing a predetermined memory area provided in the control means based on the state of one of the first and second start states being met when the supply of operating power is started (in the 49th embodiment, a function for executing the processing of step SB117 in the main CPU 63; in the 51st embodiment, a function for executing the processing of step SB617 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of step SB721 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of step SB815 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of step SC117 in the main CPU 63).

According to feature v8, when the supply of operating power starts, a predetermined storage area of the first control means is initialized based on whether the first or second start status is met. This makes it possible to associate whether the predetermined storage area has been initialized with whether new time correspondence information has been stored.

In addition, with respect to the configuration of features v1 to v8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group u and feature group v can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to perform processing appropriately when the supply of operating power begins, and there is still room for improvement in this regard.

<Feature w group>
Feature w1. Predetermined display means (first to fourth notification display devices 201 to 204),
A predetermined display control means (a function of executing a second timer interrupt process in the main CPU 63) that controls the display of the predetermined display means;
A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function of executing a setting value update process or a setting confirmation process in the main CPU 63) that executes a predetermined setting-related process related to the setting value when the supply of operating power is started;
Equipped with
The predetermined display control means
A means for causing the predetermined display means to display information related to the setting value when the predetermined setting-related processing is executed (a function for executing the processing of steps S9004 and S9006 in the main CPU 63);
a check control means for causing the predetermined display means to display a check indication to enable confirmation of whether the predetermined display means is normal or not after the predetermined setting-related processing has been executed (a function for executing the processing of step S9519 in the main CPU 63 in the 37th embodiment, a function for executing the processing of step SA419 in the main CPU 63 in the 45th embodiment, a function for executing the processing of step SA919 in the main CPU 63 in the 46th embodiment, a function for executing the processing of step SB123 in the main CPU 63 in the 49th embodiment, a function for executing the processing of step SB623 in the main CPU 63 in the 51st embodiment, a function for executing the processing of steps SB712 and SB719 in the main CPU 63 in the 52nd embodiment, a function for executing the processing of step SB817 in the main CPU 63 in the 53rd embodiment, and a function for executing the processing of step SC119 in the main CPU 63 in the 54th embodiment);
A gaming machine characterized by comprising:

According to feature w1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. Furthermore, when a specified setting-related process is executed, the setting value is displayed on the specified display means, so the amusement hall manager can understand the current setting value by checking the specified display means. Furthermore, a check display is displayed on the specified display means, making it possible to check whether the specified display means is functioning normally.

In this case, when the supply of operating power begins, a predetermined setting-related process is executed, and then a check display is displayed on the predetermined display means. This makes it possible to prioritize the display of setting values when a predetermined setting-related process is executed over the check display, without requiring adjustment processing such as terminating the check display midway when the predetermined setting-related process has started.

Feature w2. A gaming machine according to Feature w1, wherein the check control means causes the predetermined display means to display the check display regardless of whether the supply of operating power is started, the predetermined setting-related processing is executed, or the predetermined setting-related processing is not executed.

According to feature w2, when the supply of operating power begins, a check display is displayed on the specified display means regardless of whether a specified setting-related process is executed. This makes it possible to check whether the specified display means is normal regardless of the situation when the supply of operating power begins.

Feature w3. A common process is set as a process executed when the supply of operating power is started, whether the predetermined setting-related process is executed or not, and is executed later in the order of execution than the predetermined setting-related process when the predetermined setting-related process is executed;
A gaming machine according to feature w1 or w2, characterized in that the common processing is set to cause the predetermined display means to start the check display.

According to feature w3, when the supply of operating power is initiated, a check display is displayed on the specified display means regardless of whether a specified setting-related process is executed. This makes it possible to check whether the specified display means is operating normally regardless of the situation when the supply of operating power is initiated. Furthermore, because the process for causing the specified display means to start the check display is set as a common process, it is possible to achieve the excellent effects already described while simplifying the processing configuration.

Feature w4. The device is provided with a means for executing a process for progressing a game after the supply of operating power is started and the process at the start of supply is completed (a function for executing the processes of steps S8907 to S8920 in the main CPU 63),
A gaming machine described in any one of features w1 to w3, characterized in that processing to progress the game can be started even when the check display is being executed by the specified display means.

Feature w4 allows processing to proceed with the game to be started even when a check display is being displayed on the specified display means, making it possible to prevent a delay in the start of processing to proceed with the game even when a check display is displayed on the specified display means after the specified setting-related processing is executed.

Feature w5. A delay execution means (a function for executing the processing of steps SB715 and SB724 in the main CPU 63) is provided to execute a delay process that enables delaying the start of processing for progressing a game when the supply of operating power is started,
A gaming machine described in any one of features w1 to w4, characterized in that if the specified setting-related processing is not executed when the supply of operating power is started, the check control means causes the specified display means to start the check display before the delay processing is started.

According to feature w5, a delay process is executed that allows the start of processing to progress gameplay when the supply of operating power is initiated, thereby making it possible for the processing to progress gameplay to begin after the initial settings of various devices are completed. In this case, if the specified setting-related processing is not executed when the supply of operating power is initiated, a check display on the specified display means begins before the delay process is initiated. This makes it possible to display the check display during the period during which the start of processing to progress gameplay is delayed.

Feature w6. The gaming machine described in Feature w5, wherein the delay execution means does not execute the delay processing when the predetermined setting-related processing is executed.

According to feature w6, because a predetermined period of time is required to execute a predetermined setting-related process, it is possible to complete the initial settings of various devices before processing to progress the game begins. In this case, by not executing delay processing when a predetermined setting-related process is executed, it is possible to prevent the start of processing to progress the game from being extremely delayed when the predetermined setting-related process has been executed.

Feature w7. The setting-related execution means
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed based on a first setting-related operation (turning on the setting key insertion portion 68a and pressing the reset button 68c) being performed when the supply of operating power is started (a function for making a positive determination at step SB114 in the main CPU 63 in the 49th embodiment; a function for making a positive determination at step SB614 in the main CPU 63 in the 51st embodiment; a function for making a positive determination at step SB717 in the main CPU 63 in the 52nd embodiment; a function for making a positive determination at step SB812 in the main CPU 63 in the 53rd embodiment; and a function for making a positive determination at step SC113 in the main CPU 63 in the 54th embodiment);
When the supply of operating power is started, a notification generating means (a function for executing a setting confirmation process in the main CPU 63) notifies the setting value to be used based on a second setting-related operation (an ON operation of the setting key insertion portion 68a) being performed;
A gaming machine according to any one of features w1 to w6, characterized in that it is provided with:

According to feature w7, in order to change the setting value to be used, it is necessary to perform a first setting-related operation when the supply of operating power begins, making it difficult to illegally change the setting value to be used. Furthermore, since the setting value to be used is notified by performing a second setting-related operation when the supply of operating power begins, the amusement hall manager can check the setting value to be used as needed.

Feature w8. A gaming machine described in any one of Features w1 to w7, wherein the predetermined display control means is equipped with a means for causing the predetermined display means to display information corresponding to the results of game history management (a function for executing the processing of steps S8708, S8709, and S9107 in the main CPU 63).

Feature w8 makes it possible to notify the gaming hall manager of the results of gaming history management. In this case, by having the configuration of feature w1 and displaying a check display on the specified display means, it becomes possible to confirm whether the information corresponding to the results of gaming history management on the specified display means is being displayed accurately.

In addition, with respect to the configuration of features w1 to w8, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature x group>
Feature x1. Predetermined display means (first to fourth notification display devices 201 to 204),
A predetermined display control means (a function of executing a second timer interrupt process in the main CPU 63) that controls the display of the predetermined display means;
A means for executing a process for progressing a game after the supply of operating power has started and the situation after the supply has started has ended (a function for executing the processes of steps S8907 to S8920 in the main CPU 63);
Equipped with
The predetermined display control means includes a check control means (a function of executing the processing of step S9405 in the main CPU 63 in the 36th embodiment, and a function of executing the processing of steps SB713 and SB722 in the main CPU 63 in the 52nd embodiment) that causes the predetermined display means to perform a check display that enables confirmation of whether the predetermined display means is normal in the situation after the supply has started,
A gaming machine characterized by a configuration in which a delay situation can occur (a situation in which a negative judgment is made in step S9406 in the 36th embodiment, and a situation in which the processing of steps SB715 and SB724 is executed by the main CPU 63 in the 52nd embodiment) that makes it possible to delay the start of processing to progress the game when the check display is being displayed on the specified display means.

According to feature x1, when the supply of operating power begins, a check display is displayed on the specified display means, making it possible to check whether the specified display means is operating normally. In this case, while the check display is displayed, a delay situation may occur that makes it possible to delay the start of processing to progress the game. This makes it possible to ensure an opportunity to check the check display on the specified display means before processing to progress the game begins. Furthermore, the occurrence of a delay situation makes it possible to complete the initial settings of various devices before processing to progress the game begins. This delay situation can then be used to cause the specified display means to display a check display.

Feature x2. A gaming machine as described in Feature x1, characterized in that it is equipped with a means for causing the delay state to occur when the check display on the predetermined display means is being displayed (in the 36th embodiment, a function for executing the processing of step S9406 in the main CPU 63, and in the 52nd embodiment, a function for executing the processing of steps SB715 and SB724 in the main CPU 63).

Feature x2 means that a delay occurs when the check display is displayed, so it is possible to prevent processing to progress the game from starting while the check display is displayed.

Feature x3. A gaming machine as described in Feature x1 or x2, characterized in that the delay state occurs when the check display is being displayed on the predetermined display means based on the first start state being reached when the supply of operating power is started, and the delay state does not occur when the check display is being displayed on the predetermined display means based on the second start state being reached when the supply of operating power is started.

According to feature x3, in the first start situation, a delay occurs when a check display is being displayed on the specified display means, making it possible to prevent processing to progress the game from starting while the check display is being displayed; and in the second start situation, a delay does not occur when a check display is being displayed on the specified display means, making it possible to prevent the start timing of processing to progress the game from being extremely delayed.

Feature x4. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function of executing a setting value update process or a setting confirmation process in the main CPU 63) that executes a predetermined setting-related process related to the setting value when the supply of operating power is started;
Equipped with
the first start situation is a situation in which the predetermined setting-related process is not executed in the post-supply start situation,
The gaming machine according to feature x3, wherein the second start situation is a situation in which the predetermined setting-related processing is executed in the post-supply start situation.

According to feature x4, because a predetermined period of time is required when a predetermined setting-related process is executed, it is possible to complete the initial settings of various devices before the process for progressing the game begins. In this case, by preventing a delay when a check display is being displayed on the predetermined display means when the predetermined setting-related process is executed, it is possible to prevent an excessive delay in the start of the process for progressing the game when the predetermined setting-related process has been executed.

Feature x5. The setting-related execution means
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed based on a first setting-related operation (turning on the setting key insertion portion 68a and pressing the reset button 68c) being performed when the supply of operating power is started (a function for making a positive determination at step SB114 in the main CPU 63 in the 49th embodiment; a function for making a positive determination at step SB614 in the main CPU 63 in the 51st embodiment; a function for making a positive determination at step SB717 in the main CPU 63 in the 52nd embodiment; a function for making a positive determination at step SB812 in the main CPU 63 in the 53rd embodiment; and a function for making a positive determination at step SC113 in the main CPU 63 in the 54th embodiment);
When the supply of operating power is started, a notification generating means (a function for executing a setting confirmation process in the main CPU 63) notifies the setting value to be used based on a second setting-related operation (an ON operation of the setting key insertion portion 68a) being performed;
The gaming machine according to feature x4, characterized in that it is provided with:

According to feature x5, in order to change the setting value to be used, it is necessary to perform a first setting-related operation when the supply of operating power begins, making it difficult to attempt to fraudulently change the setting value to be used. Furthermore, since the setting value to be used is notified by performing a second setting-related operation when the supply of operating power begins, the amusement hall manager can check the setting value to be used as needed.

Feature x6. A gaming machine described in any one of Features x1 to x5, wherein the predetermined display control means is equipped with a means for causing the predetermined display means to display information corresponding to the results of game history management (a function for executing the processing of steps S8708, S8709, and S9107 in the main CPU 63).

Feature x6 makes it possible to notify the gaming hall manager of the results of gaming history management. In this case, by having the configuration of feature x1 and displaying a check display on the specified display means, it becomes possible to confirm whether the information corresponding to the results of gaming history management on the specified display means is being displayed accurately.

In addition, for the configuration of features x1 to x6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group w and feature group x can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, gaming machines such as those exemplified above require a configuration that makes it possible to check whether the display on the specified display means is accurate, and there is still room for improvement in this regard.

<Feature y group>
Feature y1. Setting means for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level (in the 49th embodiment, a function for executing the processing of step SB311 in the main CPU 63, and in the 53rd embodiment, a function for executing the processing of step SB915 in the main CPU 63);
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed (a function for making a positive determination at step SB114 in the main CPU 63 in the 49th embodiment, a function for making a positive determination at step SB614 in the main CPU 63 in the 51st embodiment, a function for making a positive determination at step SB717 in the main CPU 63 in the 52nd embodiment, a function for making a positive determination at step SB812 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination at step SC113 in the main CPU 63 in the 54th embodiment);
a setting monitoring means for executing a setting monitoring process to monitor whether the setting value of the target to be used is abnormal (a function for executing the process of step SB106 in the main CPU 63 in the 49th embodiment, a function for executing the process of step SB606 in the main CPU 63 in the 51st embodiment, a function for executing the process of step SB705 in the main CPU 63 in the 52nd embodiment, a function for executing the process of step SB806 in the main CPU 63 in the 53rd embodiment, and a function for executing the process of step SC106 in the main CPU 63 in the 54th embodiment);
Equipped with
A gaming machine characterized in that the setting monitoring process is included in the supply start process that is executed when the supply of operating power to a control means having the setting means is started (steps SB101 to SB122 in the 49th embodiment, steps SB601 to SB622 in the 51st embodiment, steps SB701 to SB729 in the 52nd embodiment, steps SB801 to SB818 and steps SB823 to SB826 in the 53rd embodiment, and steps SC101 to SC120 and steps SC125 to SC128 in the 54th embodiment).

According to feature y1, the setting value to be used is set from multiple levels of setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In addition, a setting monitoring process is executed to monitor whether the setting value to be used is abnormal, so if the setting value to be used is abnormal, it can be addressed. In addition, because the setting monitoring process is included in the process at the start of supply, it is possible to prevent the process to progress the game from being started even if the setting value to be used is abnormal.

Feature y2. A gaming machine as described in Feature y1, wherein the setting monitoring means executes the setting monitoring process each time a monitoring trigger occurs, even after the supply start processing has ended.

According to feature y2, after the processing at the start of supply is completed, the setting monitoring process is executed each time a monitoring trigger occurs, making it easier to identify abnormal settings in the target device.

Feature y3: Equipped with a means for executing a periodically activated interrupt process (a function for executing a first timer interrupt process in the main CPU 63),
A gaming machine described in feature y2, characterized in that the interrupt processing includes the setting monitoring processing.

Feature y3 allows the settings monitoring process to be executed each time the device is periodically started, thereby increasing the frequency with which settings in use are monitored for abnormalities.

Feature y4. A gaming machine according to any one of Features y1 to y3, characterized in that the setting monitoring means includes a restriction means (in the 49th embodiment, a function for executing step SB119 in the master CPU 63; in the 51st embodiment, a function for executing step SB619 in the master CPU 63; in the 52nd embodiment, a function for executing step SB726 in the master CPU 63; in the 53rd embodiment, a function for executing step SB823 in the master CPU 63; and in the 54th embodiment, a function for executing step SC125 in the master CPU 63) that sets the setting monitoring means to a restricted state in which the execution of a predetermined progression process for progressing the game is restricted based on the identification of an abnormal setting value for the target of use in the setting monitoring process.

According to feature y4, if it is determined that the setting value of the target to be used is abnormal, the execution of the predetermined progress process for progressing the game is restricted, making it possible to prevent the game from starting even if the setting value of the target to be used is abnormal.

Feature y5. A gaming machine according to Feature y4, characterized in that it is equipped with means for releasing the restricted state based on the occurrence of the setting-enabled state (a function for executing the processing of step SB303 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB904 in the main CPU 63 in the 53rd embodiment).

Feature y5 makes it possible to set new settings for the target setting when resolving a situation where the target setting value is abnormal.

Feature y6. A gaming machine according to Feature y4 or y5, wherein the regulating means returns the machine to the regulated state when the supply of operating power is resumed, even if the supply of operating power is stopped while the machine is in the regulated state.

Feature y6 makes it possible to prevent the state in which the execution of a predetermined progress process is restricted due to an abnormal setting value of the target device from being released simply by stopping the supply of operating power.

Feature y7. A gaming machine described in any one of Features y4 to y6, characterized in that it is equipped with a means for executing non-restricted processing different from the predetermined progression processing even in the restricted state (a function for executing the processing of steps S8901 to S8905 in the main CPU 63).

Feature y7 makes it possible to execute non-restricted processes even in situations where the execution of a specified progress process is restricted due to an abnormal setting value for the target device. This makes it possible to ensure that necessary processes are executed even in a restricted state.

Feature y8. A gaming machine according to Feature y7, wherein the non-restrictive processing includes a power outage monitoring process (step S8901) for monitoring the occurrence of a power outage.

Feature y8 allows power outage monitoring processing to be performed even in a restricted state, making it possible to respond appropriately if a power outage occurs in a restricted state.

Feature y9. A gaming machine according to any one of Features y1 to y8, characterized in that the setting monitoring means includes means for executing a notification to enable the player to recognize that the setting possible situation should be generated based on the setting monitoring process identifying an abnormality in the setting value of the target to be used (in the 49th embodiment, a function for executing the processing of step SB121 in the main CPU 63; in the 51st embodiment, a function for executing the processing of step SB621 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of step SB728 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of step SB825 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of step SC127 in the main CPU 63).

According to feature y9, if an abnormal setting value for the target is identified, a notification is issued to make the player aware that a setting enablement situation should be created. Therefore, if an abnormal setting value for the target is detected, it is possible to prompt the amusement hall manager to resolve the abnormality.

In addition, with respect to the configuration of features y1 to y9, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature group y can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to properly manage the setting values that determine the machine's advantageous degree, and there is still room for improvement in this regard.

<Feature z group>
Feature z1. A predetermined monitoring means for monitoring whether a predetermined abnormality has occurred in the information stored in a predetermined storage area (work area 221 for specific control) when the supply of operating power is started (a function for executing the processes of steps S7906 and S7909 in the main CPU 63 in the 33rd embodiment, a function for executing the processes of steps S8807 and S8810 in the main CPU 63 in the 35th embodiment, a function for executing the processes of steps S9408 and S9411 in the main CPU 63 in the 36th embodiment, a function for executing the processes of steps S9506 and S9509 in the main CPU 63 in the 37th embodiment, a function for executing the processes of steps S9905 and S9908 in the main CPU 63 in the 42nd embodiment, a function for executing the processes of steps S9906 and S9909 in the main CPU 63 in the 45th embodiment, in the 46th embodiment, a function of executing the processes of steps SA406 and SA409 in the main CPU 63; in the 49th embodiment, a function of executing the processes of steps SB104 to SB106 in the main CPU 63; in the 51st embodiment, a function of executing the processes of steps SB604 to SB606 in the main CPU 63; in the 52nd embodiment, a function of executing the processes of steps SB703 to SB705 in the main CPU 63; in the 53rd embodiment, a function of executing the processes of steps SB804 to SB806 in the main CPU 63; and in the 54th embodiment, a function of executing the processes of steps SC104 to SC106 in the main CPU 63).
a restricting means for restricting the execution of a predetermined progress process for progressing a game based on the occurrence of the predetermined abnormality being identified by the predetermined monitoring means (a function for executing the process of step S7910 in the main CPU 63 in the 33rd embodiment, a function for executing the process of step S8811 in the main CPU 63 in the 35th embodiment, a function for executing the process of step S9412 in the main CPU 63 in the 37th embodiment, a function for executing the process of step S9510 in the main CPU 63 in the 42nd embodiment, a function for executing the process of step S9909 in the main CPU 63 in the 45th embodiment, In the 46th embodiment, a function of executing the process of step SA911 in the main CPU 63, in the 49th embodiment, a function of executing the process of step SB119 in the main CPU 63, in the 51st embodiment, a function of executing the process of step SB619 in the main CPU 63, in the 52nd embodiment, a function of executing the process of step SB726 in the main CPU 63, in the 53rd embodiment, a function of executing the process of step SB823 in the main CPU 63, and in the 54th embodiment, a function of executing the process of step SC125 in the main CPU 63).
A means for executing non-restricted processing different from the predetermined progress processing even in the restricted state (a function for executing the processing of steps S8201 to S8206 in the main CPU 63 in the 33rd embodiment, a function for executing the processing of steps S8901 to S8905 in the main CPU 63 in the 35th embodiment, and a function for executing the processing of steps SA101 to SA106 in the main CPU 63 in the 42nd embodiment);
A gaming machine characterized by comprising:

According to feature z1, if it is determined that a predetermined abnormality has occurred with respect to information stored in a predetermined memory area, the execution of predetermined progression processing to progress the game is restricted, making it possible to prevent the game from starting despite the occurrence of a predetermined abnormality. Furthermore, even in situations where the execution of predetermined progression processing is restricted due to the occurrence of a predetermined abnormality, it is possible to ensure that non-restricted processing is executed. This makes it possible to ensure that necessary processing is executed even in a restricted state.

Feature z2. A gaming machine according to Feature z1, wherein the non-regulated processing includes a power outage monitoring process for monitoring for the occurrence of a power outage (step S8201 in the 33rd embodiment, step S8901 in the 35th embodiment, and step SA102 in the 42nd embodiment).

Feature z2 allows power outage monitoring processing to be performed even in a restricted state, making it possible to respond appropriately if a power outage occurs in a restricted state.

Feature z3. A gaming machine according to Feature z1 or z2, wherein the regulating means is configured to return to the regulated state when the supply of operating power is resumed, even if the supply of operating power is stopped while the gaming machine is in the regulated state.

Feature z3 makes it possible to prevent the state in which the execution of a predetermined progress process is restricted due to the occurrence of a predetermined abnormality from being lifted simply by stopping the supply of operating power.

Feature z4. Setting means for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level (a function for executing the processing of step SB311 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB915 in the main CPU 63 in the 53rd embodiment);
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed (a function for making a positive determination at step SB114 in the main CPU 63 in the 49th embodiment, a function for making a positive determination at step SB614 in the main CPU 63 in the 51st embodiment, a function for making a positive determination at step SB717 in the main CPU 63 in the 52nd embodiment, a function for making a positive determination at step SB812 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination at step SC113 in the main CPU 63 in the 54th embodiment);
A gaming machine according to any one of features z1 to z3, characterized in that it is provided with:

According to feature z4, the setting value to be used is set from multiple levels of setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, if a specified abnormality occurs with the information stored in the specified memory area, there is a possibility that an abnormality has also occurred with the setting value. In contrast, with the configuration of feature z1 above, if it is determined that a specified abnormality has occurred with the information stored in the specified memory area, the execution of the specified progression process to progress the game is restricted, making it possible to prevent gameplay from starting despite the possibility that an abnormality has occurred with the setting value.

Feature z5. A gaming machine according to Feature z4, characterized in that it is equipped with means for executing a notification that enables a player to recognize that the settable situation should occur, based on the occurrence of the predetermined abnormality being identified by the predetermined monitoring means (in the 49th embodiment, a function for executing the processing of step SB121 in the main CPU 63; in the 51st embodiment, a function for executing the processing of step SB621 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of step SB728 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of step SB825 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of step SC127 in the main CPU 63).

According to feature z5, when a specified abnormality is identified, a notification is issued to make the player aware that a setting-enabled situation should occur, making it possible to prompt the amusement hall manager to set the setting value when a specified abnormality occurs.

Feature z6. A gaming machine as described in Feature z4 or z5, characterized in that it is equipped with means for releasing the restricted state based on the occurrence of the setting-enabled state (a function for executing the processing of step SB303 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB904 in the main CPU 63 in the 53rd embodiment).

Feature z6 makes it possible to set new settings for the target settings when a specified abnormality is resolved.

In addition, with respect to the configuration of features z1 to z6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21, One or more of features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5 may be applied. This allows for a synergistic effect to be achieved by combining these features.

<Feature αA group>
Feature αA1. A predetermined monitoring means for monitoring whether a predetermined abnormality has occurred in the information stored in a predetermined storage area (work area 221 for specific control) when the supply of operating power is started (in the 49th embodiment, a function for executing the processing of steps SB104 to SB106 in the main CPU 63; in the 51st embodiment, a function for executing the processing of steps SB604 to SB606 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of steps SB703 to SB705 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of steps SB804 to SB806 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of steps SC104 to SC106 in the main CPU 63);
a regulating means for, when the occurrence of the predetermined abnormality is identified by the predetermined monitoring means, changing the execution content of the processing at the start of supply of operating power to be different from that when the occurrence of the predetermined abnormality is not identified by the predetermined monitoring means (in the 49th embodiment, a function for executing the processing of step SB119 in the main CPU 63; in the 51st embodiment, a function for executing the processing of step SB619 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of step SB726 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of step SB823 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of step SC125 in the main CPU 63);
specific output means for outputting a specific output to the outside of the gaming machine based on the occurrence of the specific abnormality being identified by the specific monitoring means (in the 49th embodiment, a function for executing the processing of step SB122 in the main CPU 63; in the 51st embodiment, a function for executing the processing of step SB622 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of step SB729 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of step SB826 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of step SC128 in the main CPU 63);
A gaming machine characterized by comprising:

According to feature αA1, when it is determined that a specified abnormality has occurred with the information stored in a specified memory area, the processing executed when the supply of operating power begins is different from that executed when no specified abnormality has occurred, making it possible to prevent processing from proceeding normally despite the occurrence of a specified abnormality. In addition, when it is determined that a specified abnormality has occurred, a specific output is sent externally to the gaming machine. This makes it possible to prompt the gaming hall manager to take action to address the occurrence of the specified abnormality.

Feature αA2. A gaming machine as described in Feature αA1, wherein the specific output means also issues the specific output to the outside of the gaming machine when it is determined that an event other than the predetermined abnormality has occurred.

Feature αA2 allows a specific output to be sent to the outside of the gaming machine even when an event other than a specified abnormality occurs. This makes it possible to use the same configuration for sending a specific output.

Feature αA3. A gaming machine described in Feature αA1 or αA2, wherein the specific output means outputs the specific signal to an external device if the specified abnormality occurs when the supply of operating power is resumed, even if the supply of operating power is stopped while the specified abnormality is occurring.

Feature αA3 enables a specific output to be sent externally to the gaming machine whenever the supply of operating power is resumed when a specified abnormality occurs. This makes it easier for the gaming parlor manager to recognize that a specified abnormality has occurred.

Feature αA4. A gaming machine described in any one of Features αA1 to αA3, wherein the regulating means, upon the occurrence of the predetermined abnormality being identified by the predetermined monitoring means, enters a regulated state in which the execution of a predetermined progression process for progressing the game is restricted.

According to feature αA4, if it is determined that a predetermined abnormality has occurred with the information stored in a predetermined memory area, the execution of a predetermined progression process for progressing the game is restricted, thereby making it possible to prevent the game from starting even when a predetermined abnormality has occurred.

Feature αA5. A gaming machine as described in Feature αA4, characterized in that it is equipped with means for executing non-restricted processing that differs from the predetermined progression processing even in the restricted state (in the 33rd embodiment, a function for executing processing of steps S8201 to S8206 in the main CPU 63; in the 35th embodiment, a function for executing processing of steps S8901 to S8905 in the main CPU 63; and in the 42nd embodiment, a function for executing processing of steps SA101 to SA106 in the main CPU 63).

Feature αA5 makes it possible to execute non-restricted processes even in situations where the execution of a specified progress process is restricted due to the occurrence of a specified abnormality. This makes it possible to ensure that necessary processes are executed even in a restricted state.

Feature αA6. A gaming machine as described in Feature αA5, wherein the non-regulated processing includes a power outage monitoring process for monitoring for the occurrence of a power outage (step S8201 in the 33rd embodiment, step S8901 in the 35th embodiment, and step SA102 in the 42nd embodiment).

Feature αA6 allows power outage monitoring processing to be performed even in a restricted state, making it possible to respond appropriately if a power outage occurs in a restricted state.

Feature αA7. A gaming machine described in any one of Features αA4 to αA6, wherein the regulating means is configured to return to the regulated state when the supply of operating power is resumed, even if the supply of operating power is stopped while the machine is in the regulated state.

Feature αA7 makes it possible to prevent the state in which the execution of a predetermined progress process is restricted due to the occurrence of a predetermined abnormality from being lifted simply by stopping the supply of operating power.

Feature αA8. Setting means for setting a setting value to be used from among a plurality of setting values corresponding to the player's advantage level (a function for executing the processing of step SB311 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB915 in the main CPU 63 in the 53rd embodiment);
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed (a function for making a positive determination at step SB114 in the main CPU 63 in the 49th embodiment, a function for making a positive determination at step SB614 in the main CPU 63 in the 51st embodiment, a function for making a positive determination at step SB717 in the main CPU 63 in the 52nd embodiment, a function for making a positive determination at step SB812 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination at step SC113 in the main CPU 63 in the 54th embodiment);
A gaming machine described in any one of features αA4 to αA7, characterized by comprising:

According to feature αA8, the setting value to be used is set from multiple setting value levels corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, if a specified abnormality occurs with the information stored in the specified memory area, there is a possibility that an abnormality has also occurred with the setting value. In contrast, with the configuration of feature αA1 above, if it is determined that a specified abnormality has occurred with the information stored in the specified memory area, the execution content of the process when the supply of operating power begins is different from that when the specified abnormality has not occurred, making it possible to prevent processing from proceeding as usual despite the possibility that an abnormality has occurred with the setting value. Furthermore, because a specific output is sent externally to the gaming machine based on the determination that a specified abnormality has occurred, it is possible to prompt the gaming hall manager to take action to address the possibility that an abnormality has occurred with the setting value.

Feature αA9. A gaming machine as described in Feature αA8, characterized in that it is equipped with means for executing a notification that enables a player to recognize that the settable situation should occur, based on the occurrence of the predetermined abnormality being identified by the predetermined monitoring means (in the 49th embodiment, a function for executing the processing of step SB121 in the main CPU 63; in the 51st embodiment, a function for executing the processing of step SB621 in the main CPU 63; in the 52nd embodiment, a function for executing the processing of step SB728 in the main CPU 63; in the 53rd embodiment, a function for executing the processing of step SB825 in the main CPU 63; and in the 54th embodiment, a function for executing the processing of step SC127 in the main CPU 63).

According to feature αA9, when a specified abnormality is identified, a notification is issued to make the player aware that a setting-enabled situation should occur, making it possible to prompt the amusement hall manager to set the setting value when a specified abnormality occurs.

Feature αA10. The regulating means, based on the occurrence of the predetermined abnormality identified by the predetermined monitoring means, sets a regulated state in which execution of a predetermined progression process for progressing a game is restricted;
This gaming machine is a gaming machine described in feature αA8 or αA9, characterized in that it is equipped with a means for releasing the restricted state based on the occurrence of the settable situation (in the 49th embodiment, a function for executing the processing of step SB303 in the main CPU 63, and in the 53rd embodiment, a function for executing the processing of step SB904 in the main CPU 63).

Feature αA10 makes it possible to set new settings for the target setting when a specified abnormality is resolved.

In addition, in relation to the configuration of features αA1 to αA10, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21 , features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5. This allows for a synergistic effect to be achieved by combining these features.

<Feature αB group>
Feature αB1. A means for starting processing at the start of supply of operating power when the supply of operating power is started (steps SB101 to SB122 in the 49th embodiment, steps SB601 to SB622 in the 51st embodiment, steps SB701 to SB729 in the 52nd embodiment, steps SB801 to SB818 and steps SB823 to SB826 in the 53rd embodiment, steps SC101 to SC120 and steps SC125 to SC128 in the 54th embodiment),
A means for executing an interrupt process that is periodically started (a function for executing a first timer interrupt process in the main CPU 63);
A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function of executing a setting value update process or a setting confirmation process in the main CPU 63) that executes a predetermined setting-related process related to the setting value as part of the process at the start of the supply of the operating power;
A permission setting means for setting the execution of the interrupt processing from a prohibited state to a permitted state when the predetermined setting-related processing is executed in the processing at the start of the supply of the operating power (a function for executing the processing of step SB201 or step SB301 in the main CPU 63 in the 49th embodiment, and a function for executing the processing of step SB901 in the main CPU 63 in the 53rd embodiment);
A gaming machine characterized by comprising:

According to feature αB1, the setting value to be used is set from multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In addition, because the specified setting-related processing related to the setting value is executed as part of the processing when the supply of operating power begins, it is possible to make it more difficult to fraudulently execute the specified setting-related processing.

In this case, when a specified setting-related process is executed during processing at the start of the supply of operating power, the execution of interrupt processing changes from prohibited to permitted. In other words, while the execution of interrupt processing is generally prohibited during processing at the start of the supply of operating power, interrupt processing can be initiated as an interrupt during specified setting-related processing. By generally prohibiting the execution of interrupt processing during processing at the start of the supply of operating power, it is possible to shorten the time required for processing at the start of the supply of operating power. On the other hand, it is expected that the time required for specified setting-related processing to be completed will be longer because processing related to setting values is executed during this process; therefore, by permitting the execution of interrupt processing when such specified setting-related processing is being executed, it is possible to optimize the execution mode of processing.

Feature αB2. The gaming machine described in Feature αB1, wherein the setting-related execution means terminates the specified setting-related processing when a termination trigger operation is performed during the specified setting-related processing.

According to feature αB2, the specified setting-related processing continues until a termination trigger operation is performed, which can easily result in a long time being required for the processing to be completed. In this case, the configuration of feature αB1 described above allows interrupt processing to be executed while the specified setting-related processing is being executed, making it possible to optimize the execution mode of the processing.

Feature αB3. A gaming machine described in Feature αB1 or αB2, characterized in that it is equipped with a prohibition setting means (a function for executing step SB206 or step SB312 in the main CPU 63 in the 49th embodiment, and a function for executing step SB916 in the main CPU 63 in the 53rd embodiment) that changes the state in which execution of the interrupt process is permitted to a state in which execution of the interrupt process is prohibited when the predetermined setting-related process is completed.

According to feature αB3, when a specified setting-related process ends, execution of interrupt processing is again prohibited. This makes it possible to limit the period during which execution of interrupt processing is permitted when processing is being performed at the start of the supply of operating power to the period during which the specified setting-related process is being performed.

Feature αB4. A gaming machine described in any one of Features αB1 to αB3, wherein the interrupt processing includes a power outage monitoring process (step S8901) for monitoring the occurrence of a power outage.

According to feature αB4, power outage monitoring processing is performed even when a specified setting-related process is being executed. Therefore, even if the configuration is such that it may take a long time for the specified setting-related process to complete, it is possible to appropriately respond if a power outage occurs while the specified setting-related process is being executed.

Feature αB5: The interrupt process includes a progress response process (steps S8907 to S8920 in the main CPU 63) executed to control the progress of the game,
When the interrupt process is started while the predetermined setting-related process is being executed, the power outage monitoring process is executed, but the progress response process is not executed.
A gaming machine described in feature αB4, characterized in that when the interrupt processing is interrupted and started after the processing at the start of the supply of operating power has been completed, both the power outage monitoring processing and the progress response processing can be executed.

Feature αB5 enables a configuration that periodically monitors for power outages while a specific setting-related process is being executed, so that even if an interrupt process is initiated while a specific setting-related process is being executed, progress response processes for controlling game progress are not executed.

Feature αB6: The setting-related execution means
means for executing a changeable process in which the setting value to be used as the predetermined setting-related process can be changed based on a first setting-related operation (turning on the setting key insertion section 68a and pressing the reset button 68c) being performed when the supply of operating power is started (a function for executing a setting value update process in the main CPU 63);
When the supply of operating power is started, a setting notification process is executed to notify the setting value to be used as the predetermined setting-related process based on the second setting-related operation (ON operation of the setting key insertion section 68a) being performed (a function of executing a setting confirmation process in the main CPU 63);
Equipped with
A gaming machine described in any one of features αB1 to αB5, characterized in that the permission setting means sets the execution of the interrupt processing from a state in which execution is prohibited to a state in which execution of the interrupt processing is permitted when the changeable processing is executed in the processing at the start of the supply of operating power, and sets the execution of the interrupt processing from a state in which execution of the interrupt processing is prohibited to a state in which execution of the interrupt processing is permitted when the setting notification processing is executed in the processing at the start of the supply of operating power.

According to feature αB6, in order to change the setting value to be used, it is necessary to perform a first setting-related operation when the supply of operating power begins, making it difficult to attempt to fraudulently change the setting value to be used. Furthermore, since the setting value to be used is notified by performing a second setting-related operation when the supply of operating power begins, the amusement hall manager can check the setting value to be used as needed.

In addition, with respect to the configuration of features αB1 to αB6, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21 , features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above feature z group, feature αA group, and feature αB group can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to perform processing appropriately when the supply of operating power begins, and there is still room for improvement in this regard.

<Feature αC group>
Feature αC1. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function of executing a setting value update process in the main CPU 63) that executes a predetermined setting-related process related to the setting value when the supply of operating power is started;
a restricting means for restricting the execution of a predetermined progress process for progressing a game when the supply of operating power is stopped before the completion of the predetermined setting-related process and then the supply of operating power is started again (a function for making a positive determination in step SB808 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination in steps SC108 and SC116 in the main CPU 63 in the 54th embodiment);
A gaming machine characterized by comprising:

According to feature αC1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, if the supply of operating power is stopped before the specified setting-related processing is completed and then the supply of operating power is resumed, the execution of the specified progression processing to progress the game is restricted. This makes it possible to prevent the specified progression processing to progress the game from being executed even if the specified setting-related processing has not been completed.

Feature αC2. A gaming machine according to Feature αC1, characterized in that the regulating means does not enter the regulated state when the specified setting-related processing is executed, even if the supply of operating power is stopped before the specified setting-related processing is completed and the supply of operating power is subsequently started.

Feature αC2 makes it possible to prevent the execution of predetermined progression processing for progressing the game from being restricted even when predetermined setting-related processing is executed upon resumption of the supply of operating power.

Feature αC3. A gaming machine as described in Feature αC1 or αC2, characterized in that it is equipped with a means for executing non-restricted processing that differs from the predetermined progression processing even in the restricted state (a function for executing the processing of steps S8901 to S8905 in the main CPU 63).

Feature αC3 makes it possible to execute non-restricted processes even when the execution of a specified progress process is restricted. This makes it possible to ensure that necessary processes are executed even in a restricted state.

Feature αC4. A gaming machine according to Feature αC3, wherein the non-restrictive processing includes a power outage monitoring process (step S8901) for monitoring the occurrence of a power outage.

Feature αC4 allows power outage monitoring processing to be performed even in a restricted state, making it possible to respond appropriately if a power outage occurs in a restricted state.

Feature αC5. A gaming machine described in any one of Features αC1 to αC4, wherein the regulating means is configured to return to the regulated state when the supply of operating power is resumed, even if the supply of operating power is stopped while the machine is in the regulated state.

Feature αC5 makes it possible to ensure that the state in which the execution of a predetermined progress process is restricted is not lifted simply by stopping the supply of operating power.

Feature αC6. A gaming machine described in any one of Features αC1 to αC5, characterized in that it is equipped with a means for executing a notification that enables the player to recognize that the situation requires the execution of the predetermined setting-related processing based on the entry of the restricted state (a function for executing the processing of step SB825 in the main CPU 63 in the 53rd embodiment, and a function for executing the processing of step SC127 in the main CPU 63 in the 54th embodiment).

Feature αC6 makes it possible to prompt the amusement hall manager to re-execute a specified setting-related process if the supply of operating power is stopped before the specified setting-related process is completed.

Feature αC7. A gaming machine described in any one of Features αC1 to αC6, wherein the restricting means does not enter the restricted state based on the performance of a specific related operation (turning on the setting key insertion portion 68a and pressing the reset button 68c) even if the supply of operating power is stopped before the specified setting-related processing is completed and then started again.

According to feature αC7, even if the supply of operating power is stopped before the completion of the specified setting-related processing, by performing a specific related operation when the supply of operating power is resumed, it is possible to prevent the execution of the specified progression processing for progressing the game from being restricted.

Feature αC8. The gaming machine described in Feature αC7, wherein the setting-related execution means executes the predetermined setting-related processing based on the specific related operation being performed when the supply of operating power is initiated.

Feature αC8 makes it possible to prevent the execution of predetermined progression processing for progressing the game from being restricted even when predetermined setting-related processing is executed upon resumption of the supply of operating power.

Feature αC9: The specific related operation includes the setting key insertion section (setting key insertion section 68a) being set to a predetermined corresponding state (ON state) by the setting key, and another predetermined operation (pressing operation of the reset button 68c),
The gaming machine described in feature αC8 is characterized in that when the supply of operating power is stopped before the specified setting-related processing is completed and the supply of operating power is then started, the regulating means does not enter the regulated state based on the setting key insertion section being in the specified corresponding state even if the other specified operation is not performed.

According to feature αC9, even if no specific related operation has been performed when the supply of operating power is resumed, the setting key insertion unit is in a predetermined corresponding state, so it is possible to prevent the execution of the predetermined progression process for progressing through the game from being restricted. This makes it possible to prevent the execution of the predetermined progression process from being restricted even if the supply of operating power is stopped during the execution of a predetermined setting-related process and the setting key insertion unit is in a predetermined corresponding state but the power is turned on without performing any other predetermined operation.

Feature αC10. A gaming machine as described in Feature αC9, characterized in that it is equipped with a separate related execution means (a function for executing setting confirmation processing in the main CPU 63) that executes separate related processing related to the setting value based on the setting key insertion section being placed in the specified corresponding state when the supply of operating power is started and the other specified operation is not being performed.

According to feature αC10, even if the supply of operating power is stopped before the completion of a specified setting-related process, by performing an operation to execute another related process when the supply of operating power is resumed, it is possible to prevent the execution of the specified progression process for progressing the game from being restricted.

Feature αC11. A gaming machine as described in Feature αC10, characterized in that if the supply of operating power is stopped before the predetermined setting-related processing is completed, and the supply of operating power is subsequently started, the predetermined setting-related processing is executed without executing the other related processing based on the setting key insertion unit being placed in the predetermined corresponding state in a situation where the other predetermined operation is not being performed.

According to feature αC11, if the supply of operating power is stopped before a specific setting-related process is completed, and an operation to execute another related process is performed when the supply of operating power is resumed, the specific setting-related process is executed instead of the other related process. This makes it possible to prioritize the execution of the specific setting-related process.

Feature αC12. The predetermined setting-related process is a process that enables the setting value to be used to be changed,
The gaming machine described in feature αC11 is characterized in that the other related process is a process for notifying the setting value to be used.

According to feature αC12, if the supply of operating power is stopped while a setting value to be used is being changed, when the supply of operating power is subsequently resumed, it is possible to prioritize the execution of the process to change the setting value to be used over the process to notify the setting value to be used.

Feature αC13. A gaming machine described in any one of Features αC1 to αC12, wherein the predetermined setting-related process is a process that allows the setting value to be changed.

According to feature αC13, if the supply of operating power is stopped during processing to change the setting value to be used, the execution of the predetermined progress processing to continue the game is restricted when the supply of operating power is subsequently resumed. This makes it possible to prevent the execution of the predetermined progress processing to continue the game even when the setting value change has not been completed.

In addition, with respect to the configuration of features αC1 to αC13, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21 , features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5. This allows for a synergistic effect to be achieved by combining these features.

<Feature αD group>
Feature αD1. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function for executing a setting value update process in the main CPU 63) that executes a predetermined setting-related process regarding the setting value based on a specific related operation (turning on the setting key insertion section 68a and pressing the reset button 68c) when the supply of operating power is started;
When the supply of operating power is started, a predetermined related operation (ON operation of the setting key insertion section 68a) is performed, and based on this, a predetermined related process is executed by a separate related execution means (a function of executing a setting value update process in the main CPU 63).
a restricting means for restricting the execution of a predetermined progress process for progressing a game when the supply of operating power is stopped before the completion of the predetermined setting-related process and then the supply of operating power is started again (a function for making a positive determination in step SB808 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination in steps SC108 and SC116 in the main CPU 63 in the 54th embodiment);
Equipped with
The regulating means does not enter the regulated state based on the fact that the specific related operation has been performed when the supply of operating power is started thereafter, even if the supply of operating power is stopped before the completion of the specified setting-related processing, and is characterized in that the regulating means does not enter the regulated state based on the fact that the specific related operation has been performed when the supply of operating power is started thereafter, even if the supply of operating power is stopped before the completion of the specified setting-related processing.

According to feature αD1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, if the supply of operating power is stopped before the specified setting-related processing is completed and then the supply of operating power is resumed, the execution of the specified progression processing to progress the game is restricted. This makes it possible to prevent the specified progression processing to progress the game from being executed even if the specified setting-related processing has not been completed.

In addition, even if the supply of operating power is stopped before the specified setting-related processing is completed, the execution of the specified progression processing will not be restricted if a specific related operation is performed when the supply of operating power is resumed. This makes it possible to prevent the execution of the specified progression processing for progressing the game from being restricted even when the specified setting-related processing is executed when the supply of operating power is resumed.

In addition, even if the supply of operating power is stopped before the specified setting-related processing is completed, the execution of the specified progress processing will not be restricted even if a specified related operation is performed when the supply of operating power is resumed. This makes it possible to prevent the execution of the specified progress processing from being restricted when an operation is performed to execute processing related to setting values.

Feature αD2. A gaming machine as described in Feature αD1, characterized in that if the supply of operating power is stopped before the predetermined setting-related processing is completed, and the supply of operating power is subsequently started, the predetermined setting-related processing is executed without executing the other related processing based on the predetermined related operation being performed.

According to feature αD2, if the supply of operating power is stopped before a specific setting-related process is completed, and an operation to execute another related process is performed when the supply of operating power is resumed, the specific setting-related process is executed instead of the other related process. This makes it possible to prioritize the execution of the specific setting-related process.

Feature αD3: The specific related operation includes the setting key insertion section (setting key insertion section 68a) being set to a predetermined corresponding state (ON state) by the setting key, and another predetermined operation (pressing operation of the reset button 68c),
A gaming machine described in feature αD2, characterized in that the specified related operation includes the setting key insertion section being put into the specified corresponding state by the setting key, but does not include the other specified operation being performed.

According to feature αD3, even if no specific related operation has been performed when the supply of operating power is resumed, the setting key insertion unit is in a predetermined corresponding state, making it possible to prevent the execution of the predetermined progression process for progressing through the game from being restricted. This makes it possible to prevent the execution of the predetermined progression process from being restricted even if the supply of operating power is stopped during the execution of a predetermined setting-related process and the setting key insertion unit is in a predetermined corresponding state but the power is turned on without performing any other predetermined operation.

Feature αD4: The predetermined setting-related process is a process that enables the setting value to be used to be changed,
A gaming machine described in any one of features αD1 to αD3, characterized in that the other related process is a process for notifying the setting value to be used.

According to feature αD4, if the supply of operating power is stopped during processing to change the setting value to be used, the execution of the predetermined progress processing to continue the game is restricted when the supply of operating power is subsequently resumed. This makes it possible to prevent the execution of the predetermined progress processing to continue the game even when the setting value change has not been completed. Furthermore, if the supply of operating power is stopped while the setting value to be used is being changed, when the supply of operating power is resumed, it is possible to prevent the execution of the predetermined progress processing from being restricted not only when an operation is performed to execute processing that allows the setting value to be changed, but also when an operation is performed to execute processing to notify the setting value to be used.

Feature αD5. A gaming machine described in any one of Features αD1 to αD4, characterized in that it is equipped with a means for executing non-restricted processing different from the predetermined progression processing even in the restricted state (a function for executing the processing of steps S8901 to S8905 in the main CPU 63).

Feature αD5 makes it possible to execute non-restricted processes even when the execution of a specified progress process is restricted. This ensures that necessary processes are executed even in a restricted state.

Feature αD6. A gaming machine according to Feature αD5, wherein the non-regulated processing includes a power outage monitoring process (step S8901) for monitoring the occurrence of a power outage.

Feature αD6 allows power outage monitoring processing to be performed even in a restricted state, making it possible to respond appropriately if a power outage occurs in a restricted state.

Feature αD7. A gaming machine described in any one of Features αD1 to αD6, wherein the regulating means returns the machine to the regulated state when the supply of operating power is resumed, even if the supply of operating power is stopped while the machine is in the regulated state.

Feature αD7 makes it possible to ensure that the state in which the execution of a predetermined progress process is restricted is not lifted simply by stopping the supply of operating power.

Feature αD8. A gaming machine described in any one of Features αD1 to αD7, characterized in that it is equipped with a means for executing a notification that enables the player to recognize that the situation requires the execution of the specified setting-related processing based on the entry of the restricted state (in the 53rd embodiment, a function for executing the processing of step SB825 in the main CPU 63, and in the 54th embodiment, a function for executing the processing of step SC127 in the main CPU 63).

Feature αD8 makes it possible to prompt the amusement hall manager to re-execute a specified setting-related process if the supply of operating power is stopped before the specified setting-related process is completed.

Feature αD9. Means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
A setting-related execution means (a function for executing a setting value update process in the main CPU 63) that executes a predetermined setting-related process regarding the setting value based on a specific related operation (turning on the setting key insertion section 68a and pressing the reset button 68c) when the supply of operating power is started;
a restricting means for restricting the execution of a predetermined progress process for progressing a game when the supply of operating power is stopped before the completion of the predetermined setting-related process and then the supply of operating power is started again (a function for making a positive determination in step SB808 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination in steps SC108 and SC116 in the main CPU 63 in the 54th embodiment);
Equipped with
The specific related operations include a first related operation (turning on the setting key insertion section 68a) and a second related operation (pressing the reset button 68c),
The regulating means does not enter the regulated state based on the fact that the specific related operation has been performed when the supply of operating power is started afterwards, even if the supply of operating power is stopped before the specified setting-related processing is completed, and is characterized in that the regulating means does not enter the regulated state based on the fact that the first related operation of the first related operation and the second related operation has been performed when the supply of operating power is started afterwards, even if the supply of operating power is stopped before the specified setting-related processing is completed.

According to feature αD9, the setting value to be used is set from multiple setting value stages corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. In this case, if the supply of operating power is stopped before the specified setting-related processing is completed and then the supply of operating power is resumed, the execution of the specified progression processing to progress the game is restricted. This makes it possible to prevent the specified progression processing to progress the game from being executed even if the specified setting-related processing has not been completed.

In addition, even if the supply of operating power is stopped before the specified setting-related processing is completed, the execution of the specified progression processing will not be restricted if a specific related operation is performed when the supply of operating power is resumed. This makes it possible to prevent the execution of the specified progression processing for progressing the game from being restricted even when the specified setting-related processing is executed when the supply of operating power is resumed.

Furthermore, even if the supply of operating power is stopped before the specified setting-related processing is completed, the execution of the specified progress processing will not be restricted if the first related operation is performed when the supply of operating power is resumed. This makes it possible to prevent the execution of the specified progress processing from being restricted when some operations for executing the specified setting-related processing are performed.

In addition, with respect to the configuration of features αD1 to αD9, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21 , features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5. This allows for a synergistic effect to be achieved by combining these features.

<Feature αE group>
Feature αE1. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed based on the performance of a specific related operation including the operation of a predetermined corresponding operation means when the supply of operating power is started (a function for making a positive determination in step SB812 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination in step SC113 in the main CPU 63 in the 54th embodiment);
An operation identification means (a function for executing the processing of step SB910 in the main CPU 63) for identifying whether the predetermined corresponding operation means is operated or not;
an operation correspondence storage means (OFF confirmation flag 361) in which a storage state becomes a non-operation correspondence state when the operation identification means identifies that the predetermined corresponding operation means has not been operated, and a storage state becomes an operation correspondence state when the operation identification means identifies that the predetermined corresponding operation means has been operated;
A selection object change means (a function for executing the processing of step SB914 in the main CPU 63) that changes the setting value to be selected based on the fact that the operation identification means has identified that the predetermined corresponding operation means has been operated in a situation where the storage state of the operation correspondence storage means is the non-operation corresponding state in the setting possible situation;
Equipped with
When a termination trigger occurs in the setting available state, the setting value to be selected is the setting value to be used,
This gaming machine is characterized by having a state setting means (a function for executing the processing of step SB901 in the main CPU 63 in the 53rd embodiment, and a function for executing the processing of step SC114 in the main CPU 63 in the 54th embodiment) that sets the memory state of the operation-compatible memory means to the operation-compatible state when the settable state is initiated or when the settable state is initiated.

According to feature αE1, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. Furthermore, in order to create a setting-enabled state in which the setting value to be used can be changed, the power must be turned on after a specific related operation, including operation of a predetermined corresponding operation means, has been performed, making it difficult to illegally change the setting value to be used. Furthermore, because the setting value to be selected is changed based on the operation of the predetermined corresponding operation means that is operated to create the setting-enabled state, it is possible to reduce the number of operation means required to change the setting value. Furthermore, in a setting-enabled state, the setting value to be selected is changed based on the identification that the predetermined corresponding operation means has been operated when the memory state of the operation-enabled storage means is in a non-operation-enabled state, making it possible to prevent the setting value to be selected from being changed multiple times in response to a single operation of the predetermined corresponding operation means.

In this case, when the setting possible situation begins or when the setting possible situation has started, the storage state of the operation correspondence storage means is set to the operation possible state. This makes it possible to prevent the setting value to be selected from being changed by the operation of the predetermined corresponding operation means, even if the operation of the predetermined corresponding operation means to create the setting possible situation continues after the setting possible situation has started.

Feature αE2. A gaming machine as described in Feature αE1, wherein the situation generation means determines that the predetermined corresponding operation means is being operated when the detection state of the means for detecting operation of the predetermined corresponding operation means is an operation detection state, regardless of the storage state of the operation correspondence storage means.

According to feature αE2, when determining whether a specific related operation has been performed, the configuration determines whether the specific corresponding operation means has been operated, rather than determining whether the specific corresponding operation means has switched from a non-operated state to an operated state. This simplifies the processing configuration for determining whether a setting possible situation will occur.

Feature αE3: A setting correspondence storage means (setting reference area 341) for storing setting correspondence information corresponding to the setting value to be used;
a selection correspondence storage means (setting update area 342) for storing selection correspondence information corresponding to the setting value to be selected;
Equipped with
the selection target changing means changes the selection correspondence information stored in the selection correspondence storage means so that the setting value that is the selection target is changed, based on the fact that the operation specifying means has specified that the predetermined corresponding operation means has been operated in a situation where the storage state of the operation correspondence storage means is the non-operation corresponding state in the setting possible situation,
The gaming machine described in feature αE1 or αE2 is characterized in that the situation generation means sets the setting value that was the selection target in the setting possible situation as the target for use by storing information corresponding to the selection response information stored in the selection response storage means as the setting response information when the termination trigger occurs in the setting possible situation.

Feature αE3 includes a setting correspondence storage means for storing setting correspondence information corresponding to the setting value to be used, and a selection correspondence storage means for storing selection correspondence information corresponding to the setting value being changed in the setting-enabled state. This makes it possible to change the setting value in the setting-enabled state while retaining information about the setting value that was set before the setting-enabled state began.

Feature αE4. A gaming machine described in any one of Features αE1 to αE3, characterized in that it is equipped with a means (a function for executing the processing of steps SA801 to SA803 in the main CPU 63) for displaying the setting value that is the subject of selection in the setting availability situation on a predetermined display means (first to fourth notification display devices 201 to 204).

Feature αE4 makes it possible to change setting values while checking the setting values being changed in a setting-enabled situation.

Feature αE5. A means for executing a profit awarding process in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing the processes of steps S503 and S504 in the master CPU 63);
a situation generating means for generating a setting possible situation (a situation in which the setting value update process is executed) in which the setting value to be used can be changed based on the performance of a specific related operation including the operation of a predetermined corresponding operation means when the supply of operating power is started (a function for making a positive determination in step SB812 in the main CPU 63 in the 53rd embodiment, and a function for making a positive determination in step SC113 in the main CPU 63 in the 54th embodiment);
An operation identification means (a function for executing the processing of step SB910 in the main CPU 63) for identifying whether the predetermined corresponding operation means is operated or not;
A selection object change means (a function for executing the processing of step SB914 in the main CPU 63) that changes the setting value to be selected based on the fact that the operation identification means has identified that the predetermined corresponding operation means has been operated in the setting possible situation;
Equipped with
When a termination trigger occurs in the setting available state, the setting value to be selected is the setting value to be used,
This gaming machine is characterized by being equipped with a means (in the 53rd embodiment, a function of executing processing of step SB901 in the main CPU 63, and in the 54th embodiment, a function of executing processing of step SC114 in the main CPU 63) that prevents operation of the specified corresponding operating means when the supply of operating power to generate the settable situation is started from being treated as an operation that triggers a change in the setting value to be selected in the settable situation.

According to feature αE5, the setting value to be used is set from among multiple setting values corresponding to the player's level of advantage, so the player will expect the more advantageous setting value to be used. Furthermore, in order to create a setting possible situation in which the setting value to be used can be changed, it is necessary to turn the power on after performing a specific related operation, including operating a predetermined corresponding operating means, making it more difficult to fraudulently change the setting value to be used. Furthermore, because the setting value to be selected is changed based on the operation of the predetermined corresponding operating means that is operated to create the setting possible situation, it is possible to reduce the number of operating means required to change the setting value.

In this case, operation of the predetermined corresponding operating means when the supply of operating power to create the setting possible state begins is not treated as an operation that triggers a change in the setting value that is to be selected in the setting possible state. This makes it possible to prevent the operation of the predetermined corresponding operating means from causing a change in the setting value that is to be selected, even if operation of the predetermined corresponding operating means to create the setting possible state continues after the setting possible state begins.

In addition, with respect to the configuration of features αE1 to αE5, features A1 to A15, features B1 to B7, features C1 to C5, features D1 to D10, features E1 to E6, features F1 to F3, features G1 to G18, features H1 to H7, features I1 to I9, features J1 to J4, features K1 to K7, features L1 to L20, features M1 to M7, features N1 to N6, features O1 to O11, features P1 to P12, features Q1 to Q5, features R1 to R17, features S1 to S8, features T1 to T13, features U1 to U8, features V1 to V6, features W1 to W11, features X1 to X11, features Y1 to Y11, features Z1 to Z10, features a1 to a3, features b1 to b7, features c1 to c21 , features d1 to d10, features e1 to e9, features f1 to f6, features g1 to g6, features h1 to h13, features i1 to i7, features j1 to j6, features k1 to k16, features l1 to l5, features m1 to m3, features n1 to n10, features o1 to o7, features p1 to p7, features q1 to q8, features r1 to r7, features s1 to s4, features t1 to t5, features u1 to u10, features v1 to v8, features w1 to w8, features x1 to x6, features y1 to y9, features z1 to z6, features αA1 to αA10, features αB1 to αB6, features αC1 to αC13, features αD1 to αD9, and features αE1 to αE5. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the above-mentioned feature αC group, feature αD group, and feature αE group can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines have a tray storage section on the front of the machine that stores gaming balls awarded to players. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. In addition, some pachinko machines are known to have a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section.

In addition, in a slot machine, when medals have been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. When the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result of the reels stopping after spinning has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to optimize the configuration of the setting values that determine the machine's advantageous degree, and there is still room for improvement in this regard.

Below is the basic configuration of a gaming machine to which each of the above features can be applied or to which each feature can be applied.

Pachinko gaming machine: A gaming machine that has an operating means operated by the player, a gaming ball launching means that launches gaming balls based on the operation of the operating means, a ball passage that guides the launched gaming balls to a specified gaming area, and various gaming components arranged within the gaming area, and that awards a bonus to the player when the gaming ball passes through a specified passage section of each of the gaming components.

Slot machines and other reel-type gaming machines: A gaming machine equipped with a picture display device that variably displays multiple pictures, in which the variable display of the multiple pictures is initiated by operating a start operating means, and the variable display of the multiple pictures is stopped by operating a stop operating means or after a predetermined time has passed, and a bonus is awarded to the player depending on the picture displayed after the stop.

10... Pachinko machine, 12... Gaming machine main body, 14... Front door frame, 28... Firing operation device, 33... First operating port, 34... Second operating port, 35... Through gate, 49a... Gate detection sensor, 62... MPU, 63... Main CPU, 65... Main RAM, 68a... Setting key insertion section, 68b... Update button, 68c... Reset button, 69a... First notification display device, 69b... Second notification display device, 69c... Third notification display device, 112... Management CPU, 117 ...History memory, 171...Separate storage memory, 181 to 186...History memory for settings 1 to 6, 191...First history memory, 192...Second history memory, 201...First notification display device, 201a to 201g...Display segments, 202...Second notification display device, 202a to 202g...Display segments, 203...Third notification display device, 204...Fourth notification display device, 221...Work area for specific control, 222...Stack for specific control Querier, 223...work area for non-specific control, 224...stack area for non-specific control, 231...normal counter area, 232...counter area for opening/closing execution mode, 233...counter area for high frequency support mode, 234...calculation result storage area, 241...management RAM, 251...reset signal output unit, 252...program monitoring unit, 266...display IC, 311...current state area, 312...first history area, 313...second history Area, 314...Third history area, 321-324...Display segments, 325...Setting correspondence storage area, 325a-325f...First to sixth setting information storage areas, 326...Setting correspondence storage area, 326a-326c...First to third setting information storage areas, 341...Setting reference area, 342...Setting update area, 352...Sound/light side MPU, 353...Sound/light side CPU, 356...RTC, 357...RTC memory, 361...OFF confirmation flag.

Claims (1)

a history storage execution means for storing, when a predetermined event occurs as a result of a game being played, history information of the game corresponding to the event in the history storage means;
information deriving means for deriving behavior information corresponding to a game result by utilizing the history information stored in the history storage means;
a behavior information storage means for storing the behavior information derived by the information derivation means;
a mode information display control means for controlling the display of the mode information stored in the mode information storage means on the information display means;
a predetermined correspondence display control means for controlling the information display means to display a predetermined correspondence display before a new display corresponding to the aspect information is started, based on the occurrence of a predetermined display trigger;
a setting means for setting a set value corresponding to the advantage of a player;
a situation generating means for generating a setting possible situation in which the setting means can set the setting value;
Equipped with
the aspect information storage means includes a plurality of specific storage areas so as to be able to store each of the plurality of aspect information,
the aspect information display control means controls the information display means to sequentially execute displays corresponding to the plurality of aspect information stored in the plurality of specific storage areas in accordance with a predetermined display order, and when the information display means is caused to execute displays corresponding to the aspect information after the predetermined corresponding displays have been executed by the information display means, the information display means starts with a display corresponding to the aspect information corresponding to the first order in the predetermined display order,
When the setting possible state is reached, control can be executed to enable confirmation of the behavior information derived using the history information at that time,
The gaming machine is equipped with a control means for executing various processes,
The control means
an intra-area processing execution means for executing intra-area processing, which is processing using a program stored in a storage area within a predetermined address range in the program storage means;
an out-of-area processing execution means for executing out-of-area processing, which is processing using a program stored in a storage area in an address range outside the predetermined address range in the program storage means;
Equipped with
This gaming machine is
an intra-area corresponding storage area into which information can be written and read when the intra-area process is executed, and into which information can be read but not written when the extra-area process is executed;
an outside-area corresponding storage area into which information can be written and read when the outside-area processing is executed, and into which information can be read but not written when the inside-area processing is executed;
Equipped with
a configuration in which, in a situation where a display corresponding to the mode information is being performed on the information display means, a process for making the setting value set as an object to be used visible can be executed;
The gaming machine is characterized in that the in-area processing execution means is equipped with a means that can execute processing to make the setting value set as the target for use visually confirmable as in-area processing when the processing at the start of the supply of operating power has been completed and game play can begin.