JP7740455B2 - gaming machines - Google Patents

Description

The present invention relates to an amusement machine.

Pachinko machines and slot machines are well-known gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls. The gaming balls stored in the storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Furthermore, when the lottery process is executed, the control means executes rotation start control to start the reels, and if the stop button is operated while the reels are spinning, the control means executes rotation stop control to stop the reels. If the reels stop spinning after stopping, and the result corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player (see, for example, Patent Document 1).

JP 2014-045989 A

Here, in gaming machines such as those exemplified above, processing needs to be executed appropriately, and there is still room for improvement in this regard.

The present invention was made in consideration of the circumstances exemplified above, and aims to provide a gaming machine that allows processing to be executed optimally.

In order to solve the above problem, the present invention provides a predetermined storage area that takes either a first state or a second state depending on the content of an executed command;
a predetermined jump instruction executing means for jumping to a predetermined program address set as a jump destination for the predetermined jump instruction when the predetermined storage area is in the first state and the predetermined jump instruction is an instruction to be executed, and for proceeding to a program address set as a jump destination for the predetermined jump instruction when the predetermined storage area is in the second state and the predetermined jump instruction is an instruction to be executed, without jumping to the predetermined program address set as a jump destination for the predetermined jump instruction;
Equipped with
In the predetermined program in which the predetermined jump instruction is set, a predetermined instruction for executing a predetermined process is set as an instruction to be executed before the predetermined jump instruction,
the predetermined storage area is configured to be in the first state when the predetermined command is executed,
the predetermined program address is a program address at which an instruction to be executed prior to the predetermined jump instruction is set when the predetermined program is executed from the first program address in the predetermined program,
an instruction set between the predetermined program address and the program address where the predetermined jump instruction is set is repeatedly executed until the supply of operating power is stopped;
In the predetermined jump instruction, the predetermined program address is not set as information on a jump destination by the predetermined jump instruction, but information corresponding to an address difference between a program address at which the predetermined jump instruction is set and the predetermined program address is set,
The gaming machine is provided with a specific jump instruction execution means for making it possible to jump to a specific program address when a specific jump instruction is an instruction to be executed,
In the specific jump instruction, the specific program address is not set as information on the jump destination of the specific jump instruction, but information corresponding to the address difference between the program address at which the specific jump instruction is set and the specific program address is set,
The information corresponding to the address difference set in the predetermined jump instruction is characterized in that the amount of information is smaller than the information of the address difference set in the specific jump instruction.

The present invention makes it possible to ensure that processing is performed optimally.

FIG. 1 is a front view of a slot machine according to a first embodiment. 1 is a perspective view of the slot machine with the front door open. FIG. FIG. FIG. 10 is a diagram showing the arrangement of symbols on each reel. 10 is an explanatory diagram showing the relationship between the symbols visible through the display window and the combination lines. FIG. FIG. 10 is an explanatory diagram showing the relationship between winning modes and the benefits to be awarded. FIG. 10A is a front view of the common display area, and FIG. 10B is an explanatory diagram for explaining the display contents of the stop order corresponding display executed on the common display section. 10A and 10B are explanatory diagrams for explaining the relationship between the notification content of the stop order notification executed by the image display device and the display content of the stop order corresponding display executed by the dual-purpose display unit. FIG. 2 is an electrical configuration diagram of the slot machine. 10 is a flowchart showing a main process executed by a main MPU. 10 is a flowchart showing a timer interrupt process executed by the main MPU. 10 is a flowchart showing a process executed by the main MPU during a power outage. 10 is a flowchart showing normal processing executed by a main MPU. FIG. 2 is an explanatory diagram for explaining the configuration of a main RAM. 10 is a flowchart showing a start waiting process executed by the main MPU. 10 is a flowchart showing a bet response process executed by the main MPU. 10A is a flowchart showing the bed status management process executed by the main MPU, and FIG. 10B is a flowchart showing the setting process at the start executed by the main MPU. 10 is a flowchart showing the lottery process for determining a role executed by the main MPU. FIG. 10 is an explanatory diagram for explaining a role lottery table when three coins are bet. FIG. 10 is an explanatory diagram for explaining a role lottery table when two coins are bet. FIG. 10 is an explanatory diagram for explaining the relationship between the order in which the reels stop and the winning patterns that are achieved. 10 is a flowchart showing a reel control process executed by the main MPU. 1 is an explanatory diagram for explaining the game states and game zones that exist in a slot machine. FIG. (a) An explanatory diagram for explaining the conditions under which the stop order corresponding display is executed on the dual-purpose display unit, the conditions under which the ratio display is executed, and the conditions under which the number of awards display is executed; (b) An explanatory diagram for explaining the relationship between the value of the index value counter, the value of the stop order type counter, and the display content of the stop order corresponding display executed on the dual-purpose display unit; (c) An explanatory diagram for explaining the configuration of the main ROM. 10 is a flowchart showing lottery result response processing executed by the main MPU. 10 is a flowchart showing the winning determination process executed by the main MPU. 10 is a flowchart showing a management process executed by a main MPU. 10 is a flowchart showing a port output process executed by the main MPU; (a) to (i) are time charts showing how stop order display and number of awards display are executed on the dual-purpose display unit. (a) to (f) are time charts showing how the ratio display and the number of awards display are executed on the dual-purpose display unit. FIG. 1A is an explanatory diagram for explaining the configuration of a game section area, and FIG. 1B is an explanatory diagram for explaining the configuration of a game status area. 10 is a flowchart showing the response process executed by the main MPU when a game ends. 10 is a flowchart showing a CB process executed by the main MPU. A flowchart showing the first control processing of the game area executed by the main MPU. (a) An explanatory diagram for explaining the contents of the release game number lottery table, and (b) a flowchart showing the release game number lottery process executed by the main MPU. A flowchart showing the second control processing of the game area executed by the main MPU. 10 is a flowchart showing an ending handling process executed by the main MPU. 10 is a flowchart showing advantageous lottery processing executed by the main MPU at the start of a game. 10 is a flowchart showing a normal process executed by the main MPU. 10 is a flowchart showing the advantageous state processing executed by the main MPU at the start of the game. A flowchart showing the pseudo bonus processing executed by the main MPU. 10 is a flowchart showing an AT process executed by a main MPU. (a) An explanatory diagram for explaining the contents of the first add-on lottery table, (b) An explanatory diagram for explaining the contents of the second add-on lottery table, and (c) A flowchart showing the start-up add-on processing executed by the main MPU. 10 is a flowchart showing a command output process executed by a main MPU. An explanatory diagram to explain the electrical configuration of the main control board and performance control board for sending commands from the main MPU to the performance MPU. (a) An explanatory diagram for explaining the data structure of the header, (b) An explanatory diagram for explaining the data structure of the footer, and (c) An explanatory diagram for explaining the setting mode in the main RAM of the memory area set for the start command, the end command, and the power recovery command. (a) An explanatory diagram for explaining the data structure of the start command and the end command, (b) An explanatory diagram for explaining the data structure of the converted start command, and (c) An explanatory diagram for explaining the data structure of the converted end command. 1A is an explanatory diagram for explaining a conversion mode of a start command, and FIG. 1B is an explanatory diagram for explaining a conversion mode of an end command. (a) An explanatory diagram for explaining the content that the production side MPU grasps based on the post-conversion start command, and (b) an explanatory diagram for explaining the content that the production side MPU grasps based on the post-conversion end command. 10 is a flowchart showing a common command transmission process executed by the main MPU. 10 is a flowchart showing a top-level aggregation process executed by the main MPU. 10 is a flowchart showing the command reception response processing executed by the production side MPU. 10 is a flowchart showing the highest level setting process executed by the production side MPU. 10 is a flowchart showing a command conversion process executed by the production side MPU. 10 is a flowchart showing the start-up reception response processing executed by the production side MPU. 10 is a flowchart showing the winning result reception response process executed by the production side MPU. 10 is a flowchart showing the end-time reception response processing executed by the production side MPU. 10 is a flowchart showing the second section corresponding processing executed by the production side MPU. A flowchart showing the pseudo-bonus state response processing executed by the production side MPU. A flowchart showing the AT state response processing executed by the production side MPU. FIG. 2A is an explanatory diagram for explaining the configuration of the main MPU, and FIG. 2B is an explanatory diagram for explaining the setting mode of data and programs in the main ROM. (a) An explanatory diagram for explaining the types of jump commands, (b) An explanatory diagram for explaining the program contents of the power-off standby processing executed by the main MPU, and (c) An explanatory diagram for explaining the state of the jump flag when the OUT command with line number "1001" is executed. (a) An explanatory diagram for explaining the configuration for externally outputting a signal from a slot machine to a hall computer, (b) a flowchart showing the external output setting process executed by the main MPU, and (c) an explanatory diagram for explaining the relationship between the value of the AT status flag and the value of the AT status signal counter and the AT status signal. (a) is an explanatory diagram for explaining the program contents of the AT status signal setting process executed by the main MPU, and (b) and (c) are explanatory diagrams for explaining the jump command set to jump from a program address "ADR112" to a program address "ADR114" in the AT status signal setting process and a comparison example of the AT status signal setting process. FIG. 10 is an explanatory diagram for explaining the relationship between the value of the A register before adding "246" and the value of the A register and the value of the carry flag CF after adding "246". An explanatory diagram for explaining the program contents of the lottery result response processing executed by the main MPU. (a) An explanatory diagram for explaining the program contents of the first comparative example of lottery result response processing, and (b) an explanatory diagram for explaining the instructions set to execute the process of setting a stop order type number in the stop order type counter on the condition that an index value of "1" to "9" is won. (a) and (b) are explanatory diagrams for explaining the jump instructions set to jump from the program address "ADR122" and the program address "ADR125" to the program address "ADR126" in the lottery result response processing and the second comparative example of the lottery result response processing. (a) An explanatory diagram to explain the relationship between the value of the A register before subtracting "11", the value of the A register after subtracting "11", and the value of the carry flag after subtracting "11", and (b) an explanatory diagram to explain the program contents of the start-up addition processing executed by the main MPU. (a) An explanatory diagram for explaining the program contents of the first comparative example of the start-up surcharge processing, and (b) an explanatory diagram for explaining the commands set for selecting the first surcharge lottery table and the commands set for selecting the second surcharge lottery table in the start-up surcharge processing and the first comparative example of the start-up surcharge processing. (a) and (b) are explanatory diagrams for explaining the jump instructions set to jump from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" in the start-up addition process and the second comparison example of the start-up addition process. FIG. 10A is an explanatory diagram for explaining the configuration of a main RAM 74 in the second embodiment, and FIG. 10B is a flowchart showing a common command transmission process executed by a main MPU. 10 is a flowchart showing a top-level aggregation process executed by the main MPU. FIG. 11A is an explanatory diagram for explaining the configuration of a main RAM in the third embodiment, and FIG. 11B is a flowchart showing a common command transmission process executed by a main MPU. 10 is a flowchart showing a top-level aggregation process executed by the main MPU. FIG. 13A is an explanatory diagram for explaining the data configuration of a common data table in the fourth embodiment, and FIG. 13B is an explanatory diagram for explaining the configuration of a main RAM. 10 is a flowchart showing a common command transmission process executed by the main MPU. 10 is a flowchart showing a top-level aggregation process executed by the main MPU. (a) An explanatory diagram for explaining the address range in which the address of the memory area of the main RAM in which the data to be set in the start command is stored is set, and the address range in which the address of the memory area of the main RAM in which the data to be set in the end command is stored is set, among the address range in which the common data table of the main ROM in the fifth embodiment is set; (b) An explanatory diagram for explaining the data structure of the start command; (c) An explanatory diagram for explaining the data structure of the end command. (a) An explanatory diagram for explaining the electrical configuration of the main control board and the performance control board for sending commands from the main MPU to the performance MPU, and (b) an explanatory diagram for explaining the configuration of the highest setting area. 10 is a flowchart showing a common command transmission process executed by the main MPU. 10 is a flowchart showing the command reception response processing executed by the production side MPU. 10 is a flowchart showing the highest level setting process executed by the production side MPU. FIG. 13A is an explanatory diagram illustrating the configuration of a common data table in the sixth embodiment, FIG. 13B is an explanatory diagram illustrating the data configuration of a start command, and FIG. 13C is an explanatory diagram illustrating the data configuration of an end command. FIG. 2 is an explanatory diagram for explaining the configuration of a main RAM. 10 is a flowchart showing a common command transmission process executed by the main MPU. 10 is a flowchart showing a top-level aggregation process executed by the main MPU. 10 is a flowchart showing the highest level setting process executed by the production side MPU. (a) An explanatory diagram for explaining the conditions under which the dual-purpose display unit in the seventh embodiment is fully turned off, the conditions under which the stop order corresponding display is executed on the dual-purpose display unit, the conditions under which the ratio display is executed, and the conditions under which the number of awards display is executed; (b) An explanatory diagram for explaining the configuration of the main RAM; (c) A flowchart showing the start-up setting process executed by the main MPU. 10 is a flowchart showing a reel control process executed by the main MPU. 10 is a flowchart showing a port output process executed by the main MPU; 10A to 10K are time charts showing the state in which the dual-purpose display section is turned off in a game in which stop order corresponding display is performed on the dual-purpose display section. 10A to 10I are time charts showing the state in which the dual-purpose display section is turned off in a game in which stop order corresponding display is not performed on the dual-purpose display section. FIG. 13A is an explanatory diagram for explaining the configuration of the main RAM in the eighth embodiment, and FIG. 13B is a flowchart showing the lottery result response processing executed by the main MPU. 10 is a flowchart showing a timer subtraction process executed by the main MPU. 10A to 10J are time charts showing the state in which the dual-purpose display section is turned off in a game in which stop order corresponding display is not performed on the dual-purpose display section. (a) An explanatory diagram for explaining the display mode of the non-inductive display executed by the dual-purpose display unit in the ninth embodiment; (b) An explanatory diagram for explaining the conditions under which the non-inductive display is executed by the dual-purpose display unit, the conditions under which the stop order corresponding display is executed, the conditions under which the ratio display is executed, and the conditions under which the number of awards display is executed; and (c) A flowchart for explaining the lottery result corresponding processing executed by the main MPU. 10 is a flowchart showing a port output process executed by the main MPU; 10A to 10H are time charts showing how non-guiding display is performed on the dual-purpose display unit. (a) An explanatory diagram for explaining the program contents of the start-up top-up processing executed by the main MPU in the 10th embodiment, and (b) and (c) explanatory diagrams for explaining the jump commands set to jump from the program addresses "ADR141" and "ADR142" to the program address "ADR133" in the start-up top-up processing and the third comparative example of the start-up top-up processing. (a) An explanatory diagram for explaining the execution circuit of the jump command provided in the main MPU in the 11th embodiment; (b) An explanatory diagram for explaining the configuration of the main ROM for executing the additional lottery; (c) An explanatory diagram for explaining the contents of the third additional lottery table; (d) An explanatory diagram for explaining the relationship between the value of the index value counter and the values of the zero flag and carry flag after executing the operation to subtract "2". (a) An explanatory diagram for explaining the program contents of the start-up surcharge processing executed by the main MPU, (b) An explanatory diagram for explaining the program contents of the fourth comparative example of the start-up surcharge processing, and (c) An explanatory diagram for explaining the commands set to select the first to third surcharge lottery tables in the start-up surcharge processing and the fourth comparative example of the start-up surcharge processing. (a) An explanatory diagram for explaining the configuration of the main ROM for executing the additional lottery in the 12th embodiment, (b) An explanatory diagram for explaining the configuration of the main RAM for executing the lottery performance, and (c) A flowchart showing the AT processing executed by the main MPU. 10 is a flowchart showing a start-up addition process executed by the main MPU. (a) and (b) are explanatory diagrams for explaining the jump instructions set to jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" in the start-up addition processing and the fifth comparison example of the start-up addition processing. (a) An explanatory diagram for explaining the program contents of the start-up surcharge processing in the 13th embodiment, and (b) and (c) explanatory diagrams for explaining the commands set to call the lottery execution processing in the start-up surcharge processing and the 6th comparison example of the start-up surcharge processing.

First Embodiment
A first embodiment of the present invention applied to a slot machine 10, which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a front view of the slot machine 10, Fig. 2 is a perspective view of the slot machine 10 with the front door 12 open, and Fig. 3 is a front view of the cabinet 11.

As shown in Figures 2 and 3, the slot machine 10 has a housing 11 that forms its outer shell. The housing 11 is formed by fixing multiple wooden panels together, giving it an overall box-like shape that is open to the front.

As shown in Figures 1 and 2, a front door 12 is attached to the front side of the housing 11. The front door 12 is supported by the housing 11 around a pivot 15 on the left side of the housing 11, allowing the interior space of the housing 11 to be opened and closed. The front door 12 is locked so that it cannot be opened by a locking device 13 on the back side of the front door 12, and this locked state can be released by unlocking the key cylinder 14 with a specified key.

As shown in Figure 1, a gaming panel 20 is provided near the upper center of the front door 12. The gaming panel 20 has three vertically elongated display windows 21L, 21M, and 21R arranged side by side. The display windows 21L, 21M, and 21R are made of a transparent or translucent material, and the interior of the slot machine 10 can be seen through each of the display windows 21L, 21M, and 21R.

As shown in Figures 2 and 3, the interior of the housing 11 is divided into two sections, upper and lower, by a partition plate 11a, and a reel unit 31 is attached to the top of the partition plate 11a. The reel unit 31 includes a cylindrical left reel 32L, a center reel 32M, and a right reel 32R. Each reel 32L, 32M, and 32R is rotatably supported so that its central axis coincides with the axis of rotation of the corresponding reel 32L, 32M, and 32R. The axes of rotation of each reel 32L, 32M, and 32R are arranged on the same axis extending approximately horizontally, and each reel 32L, 32M, and 32R corresponds one-to-one with each display window 21L, 21M, and 21R. Therefore, a portion of the surface of each reel 32L, 32M, and 32R is visible through the corresponding display window 21L, 21M, and 21R. Furthermore, when reels 32L, 32M, and 32R rotate forward, the surfaces of reels 32L, 32M, and 32R are displayed through display windows 21L, 21M, and 21R as if they are moving from top to bottom.

As shown in Figure 1, a start lever 41 is provided on the lower left side of the gaming panel 20, which is operated to start the rotation of each of the reels 32L, 32M, and 32R. When this start lever 41 is operated when a predetermined number or more of gaming media (or gaming value), which are either medals or virtual medals, have been bet, each of the reels 32L, 32M, and 32R begins to spin simultaneously.

Stop buttons 42, 43, and 44 are provided to the right of the start lever 41 and can be operated to individually stop each of the spinning reels 32L, 32M, and 32R. Each stop button 42, 43, and 44 is located directly below the display window 21L, 21M, and 21R corresponding to the reel 32L, 32M, and 32R to be stopped. Each stop button 42, 43, and 44 becomes capable of stopping the left reel 32L once a predetermined time has elapsed since the reel began spinning.

One game (play) is played from the time when the start lever 41 is operated to start the rotation of each reel 32L, 32M, 32R, until the time when the rotation of each reel 32L, 32M, 32R is stopped by the operation of each stop button 42, 43, 44, and the time when various processes such as the awarding of gaming media and management of the game status are completed.

A medal insertion slot 45 for inserting medals is provided below and to the right of the display windows 21L, 21M, and 21R. As shown in FIG. 2, medals inserted through the medal insertion slot 45 are guided by a selector 52 provided on the back of the front door 12 to a hopper device 53 if reception is permitted, or to a medal receiving tray 59 through a medal ejection slot 58 provided at the bottom front of the front door 12 if reception is prohibited (see FIG. 1). The hopper device 53 has the function of dispensing medals stored in a storage tank through the medal ejection slot 58 to the medal receiving tray 59 if a winning combination corresponding to the awarding of game media is achieved on the main line ML (described below). As shown in FIG. 1, a return button 46 is provided below the medal insertion slot 45, which is pressed when a medal inserted into the medal insertion slot 45 becomes stuck in the selector 52.

On the lower left side of the display windows 21L, 21M, and 21R, there are provided a first credit insertion button 47 for inserting the maximum number of credited virtual medals that can be bet at one time, and a second credit insertion button 48 for inserting two virtual medals at a time. In this slot machine 10, there are two situations in which the number of gaming media (medals or virtual medals) that can be bet (i.e., bet setting) at one time is "3" and "2".

When the first credit insertion button 47 is operated in a situation where the number of bets allowed at one time is "3," the current number of bets is "0," and three or more virtual medals are stored and stored, the number of bets will decrease by three virtual medals and become "3." When the first credit insertion button 47 is operated in a situation where the number of bets allowed at one time is "3," the current number of bets is "1," and two or more virtual medals are stored and stored, the number of bets will decrease by two virtual medals and become "3." When the first credit insertion button 47 is operated in a situation where the number of bets allowed at one time is "3," the current number of bets is "2," and one or more virtual medals are stored and stored, the number of bets will decrease by one virtual medal and become "3." When the first credit insertion button 47 is operated in a situation where the number of bets allowed at one time is "2," the current number of bets is "0," and two or more virtual medals are stored and stored, the number of bets will decrease by two virtual medals and become "2." When the number of bets that can be made at one time is "2", the current number of bets is "1", and one or more virtual medals are stored and stored, if the first credit insertion button 47 is operated, one virtual medal will be deducted and the number of bets will become "2".

If the first credit insertion button 47 is operated when the number of stored virtual medals is less than the difference between the number of available bets and the current number of bets, the number of bets will increase by the number of virtual medals, and the number of virtual medals will become 0.

When the second credit insert button 48 is operated in a situation where the number of bets that can be made at one time is "3," the current number of bets is "0," and two or more virtual medals are stored and stored, the number of bets will decrease by two virtual medals and become "2." When the second credit insert button 48 is operated in a situation where the number of bets that can be made at one time is "3," the current number of bets is "1," and one or more virtual medals are stored and stored, the number of bets will decrease by one virtual medal and become "2." When the second credit insert button 48 is operated in a situation where the number of bets that can be made at one time is "2," the current number of bets is "0," and two or more virtual medals are stored and stored, the number of bets will decrease by two virtual medals and become "2." When the second credit insert button 48 is operated in a situation where the number of bets that can be made at one time is "2," the current number of bets is "1," and one or more virtual medals are stored and stored, the number of bets will decrease by one virtual medal and become "2."

If the second credit insertion button 48 is operated when the number of stored virtual medals is one and the current number of bets is "0," the number of bets will become "1" and the number of virtual medals will become zero.

The first credit insertion button 47 has a larger pressing surface that is pressed when the player operates the button than the second credit insertion button 48. This improves the operability of the first credit insertion button 47.

A settlement button 51 is provided to the left of the start lever 41. This slot machine 10 has a credit function that stores and stores, as virtual medals, any surplus medals inserted up to a predetermined maximum value (50 medals) and medals paid out when a prize is won. When the settlement button 51 is operated while virtual medals are stored and stored, the virtual medals are paid out from the medal outlet 58 as real medals.

As shown in Figures 2 and 3, a power supply unit 54 is provided inside the cabinet 11 to the left of the hopper unit 53. The power supply unit 54 is provided with a power switch 55 that is operated when powering on or off, a reset button 56 for resetting various states of the slot machine 10, and a setting key insertion hole 57 into which a setting key held by the amusement hall manager is inserted and operated to change the setting value of the slot machine 10 within the range of "1" to "6."

Next, we will explain the symbols on each reel 32L, 32M, and 32R.

Figure 4 shows the arrangement of symbols on the left reel 32L, center reel 32M, and right reel 32R. As shown in the figure, 21 symbols are arranged in a row on each of the reels 32L, 32M, and 32R. Furthermore, numbers ranging from "0" to "20" are assigned to correspond to each of the reels 32L, 32M, and 32R. However, these numbers are used by the main control device 70 (described below) to identify the symbols visible through the display windows 21L, 21M, and 21R, and are not actually assigned to the reels 32L, 32M, and 32R. However, these numbers will be used in the following explanation.

There are seven types of symbols: "Bell" (e.g., position 20 on left reel 32L), "Replay" (e.g., position 19 on left reel 32L), "Watermelon" (e.g., position 18 on left reel 32L), "Red 7" (e.g., position 15 on left reel 32L), "BAR" (e.g., position 10 on left reel 32L), "Cherry" (e.g., position 9 on left reel 32L), and "White 7" (e.g., position 5 on left reel 32L). The number and arrangement order of each symbol differs on each reel 32L, 32M, and 32R.

Figure 5 is a front view of the display windows 21L, 21M, and 21R. Each display window 21L, 21M, and 21R is formed so that of the 21 symbols on the corresponding reel 32L, 32M, and 32R, only three symbols are visible in their entirety. Therefore, when each reel 32L, 32M, and 32R is stopped, 3 x 3 = 9 symbols are visible through the display window 21L, 21M, and 21R.

In this slot machine 10, a single main line ML is set to connect the positions where the symbols on each reel 32L, 32M, and 32R are visible. The main line ML is a line connecting the middle symbols on the left reel 32L, the middle symbols on the middle reel 32M, and the middle symbols on the right reel 32R. When a predetermined number or more gaming media have been bet, the reels 32L, 32M, and 32R begin to spin, and if a winning combination is achieved on the main line ML, the player is awarded one of the following benefits: gaming media, a replay, or a change in gaming state.

In other words, in this slot machine 10, only one main line ML is set as a line on which a win can be achieved. This main line ML is set as a line that extends in a straight line. Therefore, even if a winning combination of symbols is achieved on a line that extends in a straight line, such as subline SL1 connecting the upper symbol on the left reel 32L, the middle symbol on the middle reel 32M, and the lower symbol on the right reel 32R; subline SL2 connecting the upper symbol on the left reel 32L, the upper symbol on the middle reel 32M, and the upper symbol on the right reel 32R; subline SL3 connecting the lower symbol on the left reel 32L, the lower symbol on the middle reel 32M, and the lower symbol on the right reel 32R; and subline SL4 connecting the lower symbol on the left reel 32L, the middle symbol on the middle reel 32M, and the upper symbol on the right reel 32R, no winning combination will be achieved.

Below, we will explain the relationship between winning symbol combinations and the benefits that will be awarded if a prize is won, with reference to Figure 6. Figure 6 is an explanatory diagram that explains the relationship between winning symbol combinations and the benefits that will be awarded if a prize is won.

The minor winning combinations that result in the awarding of gaming media include the 1st supplementary winning combination, the 2nd supplementary winning combination, the 3rd supplementary winning combination, the 4th supplementary winning combination, the 5th supplementary winning combination, the 6th supplementary winning combination, the 7th supplementary winning combination, the 8th supplementary winning combination, the 9th supplementary winning combination, the 1st bell winning combination, the 2nd bell winning combination, the 1st watermelon winning combination, the 2nd watermelon winning combination, and the cherry winning combination. Specifically, if the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "red 7" symbol, then the 1st supplementary winning combination occurs. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the center reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, a second supplementary win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "red 7" symbol, the stopped symbol on the center reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, a third supplementary win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the center reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "BAR" symbol, a fourth supplementary win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, a fifth supplementary win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "BAR" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, a sixth supplementary win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "white 7" symbol, a seventh supplementary win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "white 7" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, then an 8th supplementary win will occur. If the stopped symbol on the left reel 32L on the main line ML is a "white 7" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, then a 9th supplementary win will occur. If any of the 1st to 9th supplementary wins occur, the number of gaming media to be awarded will be "1".

If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, a first bell win will occur. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, a second bell win will occur. If either the first bell win or the second bell win occurs, the number of gaming media to be awarded will be "15".

If the stopped symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "watermelon" symbol, and the stopped symbol on the right reel 32R is a "watermelon" symbol, a first watermelon win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "watermelon" symbol, and the stopped symbol on the right reel 32R is a "BAR" symbol, a second watermelon win will be awarded. If either the first watermelon win or the second watermelon win is awarded, the number of game media to be awarded will be "5". If the stopped symbol on the left reel 32L on the main line ML is a "cherry" symbol, a cherry win will be awarded regardless of the stopped symbol on the middle reel 32M or the right reel 32R. If a cherry wins, the number of gaming media awarded will be "2".

Winnings that grant a replay bonus, which allows you to play the next game without betting gaming media, include the Regular Replay Win, the First Chance Replay Win, and the Second Chance Replay Win. Specifically, if the stopped symbol on the left reel 32L on the main line ML is a "Replay" symbol, the stopped symbol on the center reel 32M is a "Replay" symbol, and the stopped symbol on the right reel 32R is a "Replay" symbol, and if the stopped symbol on the left reel 32L on the main line ML is a "Red 7" symbol, the stopped symbol on the center reel 32M is a "Red 7" symbol, and the stopped symbol on the right reel 32R is a "BAR" symbol, then if the stopped symbol on the left reel 32L on the main line ML is a "Replay" symbol, and the stopped symbol on the center reel 32M is a "BAR" symbol, then If the stopping pattern is a "red 7" and the stopping pattern on the right reel 32R is a "replay" pattern, if the stopping pattern on the left reel 32L on the main line ML is a "replay" pattern, the stopping pattern on the center reel 32M is a "red 7" pattern, and the stopping pattern on the right reel 32R is a "bar" pattern, or if the stopping pattern on the left reel 32L on the main line ML is a "watermelon" pattern, the stopping pattern on the center reel 32M is a "red 7" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern, a regular replay win will be awarded.If the stopping pattern on the left reel 32L on the main line ML is a "replay" pattern, the stopping pattern on the center reel 32M is a "cherry" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern, a first chance replay win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, a second chance replay win will occur.

If any of the above replay wins are achieved, a replay bonus will be awarded, which allows you to play the next game without having to bet any gaming media. Specifically, if any of the replay wins are achieved in a game where you bet gaming media "3," you will be able to start playing the next game with gaming media "3" betted, without having to bet any gaming media. Also, if any of the replay wins are achieved in a game where you bet gaming media "2," you will be able to start playing the next game with gaming media "2" betted, without having to bet any gaming media.

State transition wins that only result in a transition in the game state include the first CB win and the second CB win. Specifically, a first CB win occurs when the stopped symbol on the left reel 32L is a "red 7" symbol, the stopped symbol on the center reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "white 7" symbol on the main line ML. A second CB win occurs when the stopped symbol on the left reel 32L is a "white 7" symbol, the stopped symbol on the center reel 32M is a "white 7" symbol, and the stopped symbol on the right reel 32R is a "red 7" symbol on the main line ML. When a first CB win occurs, the game state transitions to the first CB state ST2, and when a second CB win occurs, the game state transitions to the second CB state ST3 (see Figure 23).

The first CB state ST2 and the second CB state ST3 are game states in which, when a combination of symbols corresponding to a small win stops on the main line ML, a win is achieved and medals are paid out regardless of whether a winning combination is achieved. For example, even if winning data corresponding to a first bell win has not been set, gaming media will be awarded to the player when a combination of symbols corresponding to a first bell win stops on the main line ML. On the other hand, a replay win is achieved only if the corresponding combination has been won in a lottery.

In the first CB state ST2 and the second CB state ST3, reel control is different from that in the non-CB state. In the non-CB state, reel control is performed for each reel 32L, 32M, and 32R, allowing the reels to slide up to four symbols after the stop buttons 42-44 are operated. In other words, in the non-CB state, reel control is performed for each reel 32L, 32M, and 32R, stopping the reels within a specified time (190 milliseconds) after the stop buttons 42-44 are operated. On the other hand, in the first CB state ST2 and the second CB state ST3, the above-mentioned reel control is performed for the center reel 32M and the right reel 32R, i.e., reel control similar to that in the base game, but the above-mentioned reel control is not performed for the left reel 32L. For the left reel 32L, reel control is performed, allowing the reel to slide up to one symbol after the left stop button 42 is operated. In other words, in the first CB state ST2 and the second CB state ST3, reel control is performed on the left reel 32L to stop it within a specified time (75 msec) that is shorter than the specified time after the left stop button 42 is operated.

Note that in the first CB state ST2 and the second CB state ST3, the reel control that only allows a maximum of one symbol to slide is not limited to the left reel 32L; it may also be controlled so that the reel corresponding to the first stop button operated only slides a maximum of one symbol, or it may be controlled so that only predetermined reels slide a maximum of one symbol. Furthermore, it may also be controlled so that the reel corresponding to the stop buttons operated in a certain order only slides a maximum of one symbol, such as the reel corresponding to the second or last stop button operated only slides a maximum of one symbol.

In the first CB state ST2 and the second CB state ST3, if a combination corresponding to a replay win is won, the replay win takes priority, and if a replay win is not possible, a first bell win may occur. Also, a first bell win may occur even if a combination corresponding to a replay win is not won.

Both the first CB state ST2 and the second CB state ST3 are game states that do not increase the number of game media owned by the player. Furthermore, both the first CB state ST2 and the second CB state ST3 are game states that result in the number of game media owned by the player at the end of the game state being less than the number of game media owned by the player at the start of the game state.

Next, we will explain the devices used to perform various notifications and effects.

As shown in FIG. 1, an upper lamp 61 and a speaker 62 are provided at the top of the front door 12, as well as an image display device 63. If an abnormality occurs in the slot machine 10, the upper lamp 61 is controlled to emit light in a manner corresponding to the abnormality, and is also controlled to emit light in a manner corresponding to the winning result. The upper lamp 61 is also controlled to emit light so that a light effect corresponding to the display effect on the image display device 63 is produced. The speakers 62 are provided as a pair on the left and right, and are controlled to output sound or audio corresponding to the abnormality if an abnormality occurs in the slot machine 10, and are also controlled to output sound or audio corresponding to the winning result. The speakers 62 are also controlled to output sound so that a sound effect corresponding to the display effect on the image display device 63 is produced.

The image display device 63 has a display surface and is configured as a liquid crystal display device with a liquid crystal display, but is not limited to a liquid crystal display device and may be another display device with a display surface such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display. If an abnormality occurs in the slot machine 10, the display is controlled so that an image corresponding to the abnormality is displayed on the display surface. The image display device 63 is also controlled so that images corresponding to the winning combination results in the internal lottery and the winning results in each game are displayed on the display surface. In other words, the image display device 63 executes display effects.

The gaming panel 20 on the front door 12 is provided, below the display windows 21L, 21M, and 21R, with a credit display unit 65 that displays the number of stored virtual medals; a dual-purpose display unit 66 that displays the number of gaming media awarded when a small win is achieved and, when the image display device 63 notifies the stopping order of reels 32L, 32M, and 32R, displays a message corresponding to the message; and a zone display unit 67 that displays a message indicating that the gaming zone is the second zone. The credit display unit 65 is made up of a 7-segment display, and each segment uses a single-color LED, such as green.

Figure 7(a) is a front view of the common display area 68, which is provided with a combined display unit 66 and a section display unit 67. The common display area 68 contains the combined display unit 66, which consists of two 7-segment displays 66a, 66b arranged side by side in the horizontal direction, and the section display unit 67, which consists of one light-emitting element, as shown in Figure 7(a).

When any of the small prize winnings (1st to 9th supplementary prize winnings, 1st bell prize winning, 2nd bell prize winning, 1st watermelon prize winning, 2nd watermelon prize winning, or cherry prize winning) corresponding to the awarding of game media is achieved, the number of game media awarded corresponding to that small prize winning is displayed on the dual-purpose display unit 66 at the end of the game in which that small prize winning was achieved. Specifically, when any of the 1st to 9th supplementary prize winnings is achieved in non-CB mode, the left 7-segment display 66a becomes non-displayable and the right 7-segment display 66b displays "1," thereby indicating that "1" game media has been awarded. When either the 1st bell winning or the second bell winning is achieved in non-CB mode, the left 7-segment display 66a displays "1" and the right 7-segment display 66b displays "5," thereby indicating that "15" game media have been awarded. Furthermore, when either the first watermelon win or the second watermelon win is achieved in the non-CB state, the left 7-segment display 66a goes dark and the right 7-segment display 66b displays "5," indicating that "5" gaming media have been awarded. Furthermore, when a cherry win is achieved in the non-CB state, the left 7-segment display 66a goes dark and the right 7-segment display 66b displays "2," indicating that "2" gaming media have been awarded.

In the first CB state ST2 and the second CB state ST3, the number of gaming media awarded when a small win occurs is "1," as will be described in detail below. Therefore, when a small win occurs in the first CB state ST2 or the second CB state ST3, the left 7-segment display 66a becomes invisible and the right 7-segment display 66b displays "1," indicating that "1" gaming media has been awarded.

On the other hand, even if a win that does not award gaming media, such as a replay win or a CB win, is achieved, no display corresponding to that win is made on the dual-purpose display unit 66. In this case, the left 7-segment display 66a and the right 7-segment display 66b will display "0" to indicate that a small win was not achieved. The display of the number of gaming media awarded on the dual-purpose display unit 66 ends when gaming media are bet to start the game following the game for which the display was made, and "0" is displayed on the left 7-segment display 66a and the right 7-segment display 66b at the time of this bet. Gaming media are bet to start a game when "1" or more gaming media are bet by operating the credit insertion buttons 47, 48, or when a medal inserted into the medal insertion slot 45 is detected by the inserted medal detection sensor 45a, described below.

When the stop order of reels 32L, 32M, and 32R is announced on the image display device 63, information corresponding to the announced stop order is displayed on the dual-purpose display unit 66. In this specification, the announcement of the stop order of reels 32L, 32M, and 32R made on the image display device 63 is also referred to as stop order announcement. In addition, the display corresponding to the stop order of reels 32L, 32M, and 32R made on the dual-purpose display unit 66 is also referred to as stop order corresponding display. Figure 7(b) is an explanatory diagram for explaining the display content of the stop order corresponding display executed on the dual-purpose display unit 66. In this slot machine 10, the stop order of the reels 32L, 32M, and 32R notified by the image display device 63 includes a first stop order in which the first stop is on the left reel 32L, the second stop is on the center reel 32M, and the third stop is on the right reel 32R; a second stop order in which the first stop is on the left reel 32L, the second stop is on the right reel 32R, and the third stop is on the center reel 32M; a third stop order in which the first stop is on the center reel 32M, the second stop is on the left reel 32L, and the third stop is on the right reel 32R; and a fourth stop order in which the first stop is on the center reel 32M, the second stop is on the right reel 32R. There is a fourth stop order in which the first stop is on the right reel 32R, the second stop is on the left reel 32L, and the third stop is on the center reel 32M; a fifth stop order in which the first stop is on the right reel 32R, the second stop is on the left reel 32L, and the third stop is on the center reel 32M; a sixth stop order in which the first stop is on the right reel 32R, the second stop is on the center reel 32M, and the third stop is on the left reel 32L; a seventh stop order in which the first stop is on the left reel 32L and the rest is optional; an eighth stop order in which the first stop is on the center reel 32M and the rest is optional; and a ninth stop order in which the first stop is on the right reel 32R and the rest is optional.

The stop order notification on the image display device 63 can be executed when a winning combination that includes both the first bell winning data and any of the first through sixth supplementary winning data is achieved during the lottery process for winning combinations in the non-CB state, or when a winning combination that includes both the second bell winning data and any of the seventh through ninth supplementary winning data is achieved. Specifically, when a winning combination that includes both the first bell winning data and any of the first through sixth supplementary winning data is achieved, the first bell win is achieved if reels 32L, 32M, and 32R stop in the stop order corresponding to the winning combination. If reels 32L, 32M, and 32R do not stop in the stop order corresponding to the winning combination, one of the first through sixth supplementary winning combinations may be achieved. If the first bell win is achieved, the player is awarded 15 gaming media as explained above. If one of the first through sixth supplementary winning combinations is achieved, the player is awarded 1 gaming media as explained above.

If a winning combination includes the second bell winning data and any of the seventh to ninth supplementary winning data, the second bell win will occur if reels 32L, 32M, and 32R stop in the stopping order corresponding to the current winning combination. If reels 32L, 32M, and 32R do not stop in the stopping order corresponding to the current winning combination, any of the seventh to ninth supplementary winning combinations may occur. If the second bell win occurs, the player will be awarded 15 gaming media as already explained, and if any of the seventh to ninth supplementary winning combinations occurs, the player will be awarded 1 gaming media as already explained.

When one of the above stop orders is notified by the image display device 63, the left 7-segment display 66a of the combined display unit 66 remains in a non-display state, while the right 7-segment display 66b displays a display corresponding to the stop order of the notified item (stop order corresponding display). The display content of the stop order corresponding display on the combined display unit 66 is set to correspond one-to-one to the display content of the stop order notification on the image display device 63. Specifically, as shown in FIG. 7(b), when the first stop order is notified by the image display device 63, the combined display unit 66 displays the first stop order corresponding display; when the second stop order is notified by the image display device 63, the combined display unit 66 displays the second stop order corresponding display; when the third stop order is notified by the image display device 63, the combined display unit 66 displays the third stop order corresponding display; when the fourth stop order is notified by the image display device 63, the combined display unit 66 displays the fourth stop order corresponding display; and when the fifth stop order is notified by the image display device 63, the combined display unit 66 displays the fifth stop order corresponding display. When the sixth stop order is notified by the image display device 63, the fifth stop order corresponding display is made on the combined display unit 66, when the sixth stop order is notified by the image display device 63, the sixth stop order corresponding display is made on the combined display unit 66, when the seventh stop order is notified by the image display device 63, the seventh stop order corresponding display is made on the combined display unit 66, when the eighth stop order is notified by the image display device 63, the eighth stop order corresponding display is made on the combined display unit 66, and when the ninth stop order is notified by the image display device 63, the ninth stop order corresponding display is made on the combined display unit 66. Note that a configuration may be adopted in which multiple types of display content on the combined display unit 66 are set to correspond to some or all of the stop order notification content on the image display device 63.

In this specification, the display showing the number of gaming media awarded executed on the dual-purpose display unit 66, as well as the display of "00" when the stop order corresponding display and the ratio display described below are not executed on the dual-purpose display unit 66, are also referred to as the "award number display." The award number display is executed on the dual-purpose display unit 66 based on the value of the award number counter 74e (see FIG. 14) described below. The display content of the stop order corresponding display on the dual-purpose display unit 66 differs from the display content of the award number display on the dual-purpose display unit 66. This makes it easier to distinguish between a state in which the award number display is executed on the dual-purpose display unit 66 and a state in which the stop order corresponding display is executed.

8(a) and 8(b) are explanatory diagrams illustrating the relationship between the notification content of the stop order notification executed by the image display device 63 and the display content of the stop order corresponding display executed by the dual-purpose display unit 66. When the stop order notification of reels 32L, 32M, and 32R is executed by the image display device 63, as shown in FIG. 8(a), the image display device 63 displays unit display images G1-G3 in the same number as the number of stop operations required to end the game, and each unit display image G1-G3 displays an image corresponding to the stop order of reels 32L, 32M, and 32R. Specifically, a left unit display image G1 corresponding to the left reel 32L, a middle unit display image G2 corresponding to the center reel 32M, and a right unit display image G3 corresponding to the right reel 32R are displayed. FIG. 8(a) shows the notification of the stop order (third stop order) when the first stop is on the center reel 32M, the second stop is on the left reel 32L, and the third stop is on the right reel 32R, so the left unit display image G1 displays an image of "2" corresponding to the stop order of the left reel 32L, the middle unit display image G2 displays an image of "1" corresponding to the stop order of the middle reel 32M, and the right unit display image G3 displays an image of "3" corresponding to the stop order of the right reel 32R.

While the image display device 63 displays an image notifying the stop order of reels 32L, 32M, and 32R as described above, the combined display unit 66 displays an "L" corresponding to the stop order of reels 32L, 32M, and 32R (third stop order), as shown in FIG. 8(b). In other words, the image display device 63 displays unit display images G1-G3 corresponding to the number of reels 32L, 32M, and 32R, and displays an image corresponding to the stop order of the corresponding reels 32L, 32M, and 32R in each unit display image G1-G3, whereas the combined display unit 66 displays an image unrelated to the number of reels 32L, 32M, and 32R. This allows the player to focus on the display content on the image display device 63, even if the combined display unit 66 displays a display corresponding to the notification of the stop order of reels 32L, 32M, and 32R.

The display range of the dual-purpose display unit 66 is narrower than that of the image display unit 63. This also makes it possible to reduce the player's attention to the dual-purpose display unit 66 compared to the image display unit 63. Furthermore, the dual-purpose display unit 66 is located on the opposite side of the display windows 21L, 21M, and 21R, which allow the reels 32L, 32M, and 32R to be viewed, from the image display unit 63. This means that the dual-purpose display unit 66 is positioned at a distance from the image display unit 63, which also makes it possible to reduce the player's attention to the dual-purpose display unit 66.

When the stop order of reels 32L, 32M, and 32R is announced, the stop order display for reels 32L, 32M, and 32R on the combined display unit 66 and the stop order announcement for reels 32L, 32M, and 32R on the image display unit 63 begin after the winning combination is drawn and before the stop operation for reels 32L, 32M, and 32R is enabled. In this case, the stop order display for reels 32L, 32M, and 32R on the combined display unit 66 begins simultaneously or approximately simultaneously with the stop order announcement for reels 32L, 32M, and 32R on the image display unit 63. Furthermore, the stop order display on the combined display unit 66 and the stop order announcement on the image display unit 63 end when a stop command is issued for all reels 32L, 32M, and 32R in the game for which the stop order display and stop order announcement were executed. Note that the display of the stop order corresponding to reels 32L, 32M, and 32R on the combined display unit 66 may be configured to start before the notification of the stop order of reels 32L, 32M, and 32R on the image display unit 63, or the notification of the stop order of reels 32L, 32M, and 32R on the image display unit 63 may be configured to start before the display of the stop order corresponding to reels 32L, 32M, and 32R on the combined display unit 66. Also, the display of the stop order corresponding to reels 32L, 32M, and 32R on the combined display unit 66 may be configured to end before the notification of the stop order of reels 32L, 32M, and 32R on the image display unit 63, or the notification of the stop order of reels 32L, 32M, and 32R on the image display unit 63 may be configured to end before the display of the stop order corresponding to reels 32L, 32M, and 32R on the combined display unit 66.

The dual-purpose display unit 66 is located in the center of the common display area 68, while the interval display unit 67 is located in a corner of the common display area 68. The interval display unit 67 is a display unit for notifying that the gaming interval is the second interval SC2 of the first interval SC1 and the second interval SC2 (see FIG. 23). The second interval SC2 is an interval in which a favorable gaming state (specifically, a pseudo-bonus state ST4 or an AT state ST5) can be initiated and maintained, in which the expected number of gaming media to be acquired in one game (the value obtained by subtracting the number of gaming media betted in one game from the expected number of gaming media to be awarded in one game) can be 1 or greater, by notifying the stopping order of reels 32L, 32M, and 32R, which allows for a winning combination advantageous to the player when different winning combinations are achieved depending on the stopping order of reels 32L, 32M, and 32R. On the other hand, the first section SC1 is a section in which the advantageous gaming state does not start and does not continue.

The interval display unit 67 changes from an off state to an on state when the gaming interval transitions from the first interval SC1 to the second interval SC2. Once the interval display unit 67 is on, it remains on until the second interval SC2 ends, and turns off when the second interval SC2 ends and transitions to the first interval SC1. Therefore, even if the pseudo-bonus state ST4 or the AT state ST5 ends and the normal gaming state ST1 is restored, the second interval SC2 may be maintained. In this case, the interval display unit 67 remains on even when the pseudo-bonus state ST4 or the AT state ST5 ends, and turns off when the second interval SC2 ends. The gaming hall manager can determine that the gaming interval is the first interval SC1 by confirming that the interval display unit 67 is off, and can determine that the gaming interval is the second interval by confirming that the interval display unit 67 is on.

Instead of maintaining the lit state of the section display unit 67 during the second section SC2, the section display unit 67 may be configured to flash at a predetermined cycle during the second section SC2. Furthermore, other displays, such as a liquid crystal display device, may be used as the combined display unit 66 and the section display unit 67.

The slot machine 10 is equipped with various control devices. Specifically, as shown in FIG. 3, a main control device 70 is provided above the reel unit 31. The main control device 70 is attached to the back plate 11b, which forms the back surface of the cabinet 11. The main control device 70 is configured by housing a main control board 71 in a board box 81. An MPU 72 is mounted on one of the board surfaces, the device mounting surface, of the main control board 71. The board box 81 is transparent so that the MPU 72 housed therein can be visually observed from outside the board box 81. Note that while the board box 81 is colorless and transparent, it may also be colored and transparent as long as the MPU 72 housed therein can be visually observed from outside the board box 81. The main control device 70 is mounted on the back plate 11b of the cabinet 11 so that the opposing wall portion 82 of the board box 81, which faces the device mounting surface of the main control board 71, faces the front of the slot machine 10. Therefore, by opening the front door 12 toward the front of the slot machine 10 relative to the cabinet 11 and exposing the internal space of the cabinet 11, it becomes possible to visually observe the opposing wall 82 of the circuit board box 81, and also to visually observe the MPU 72 through the opposing wall 82.

The board box 81 is formed by combining multiple case bodies, one behind the other. These multiple case bodies are provided with connecting portions 83 that prevent separation of the case bodies and leave a mark when the case bodies are separated. Multiple connecting portions 83 are arranged side by side along one side of the roughly rectangular board box 81. This allows for separation of the case bodies, even if some connecting portions 83 are used to prevent separation and those connecting portions 83 are destroyed, allowing the case bodies to be separated. Furthermore, since the connecting portions 83 are destroyed when the case bodies are separated, leaving a mark, it is possible to visually check the connecting portions 83 to determine whether the case bodies have been separated fraudulently. Furthermore, a sealing sticker 84 is affixed to another side of the board box 81, other than the side along which the connecting portions 83 are arranged, spanning the boundary between the case bodies. When the sealing sticker 84 is peeled off, an adhesive layer remains on the case body. This makes it possible to leave a trace if the sealing seal 84 is peeled off when the case body is separated.

As shown in FIG. 2, the slot machine 10 is equipped with a performance control device 90 in addition to the main control device 70. The performance control device 90 is placed on the front door 12, stacked behind the image display device 63. The performance control device 90 controls the upper lamp 61, speaker 62, and image display device 63 based on commands received from the main control device 70. Note that, like the main control device 70, the performance control device 90 is configured with a control board housed in a board box.

Next, the electrical configuration of this slot machine 10 will be explained based on the block diagram in Figure 9.

As already explained, the main control board 71 of the main control device 70 is equipped with an MPU 72. The MPU 72 is equipped with a ROM 73 that stores various control programs and fixed value data executed by the MPU 72, a RAM 74 that is memory for temporarily storing various data when executing the control programs stored in the ROM 73, and a random number circuit 75 that sequentially updates a first random number within a predetermined numerical range based on a clock signal output from a clock circuit. The main MPU 72 also has a built-in transmission circuit 85 for sending commands to the performance control device 90. Furthermore, the MPU 72 also has built-in interrupt circuits, data input/output circuits, etc. It is not essential that the ROM 73 and RAM 74 be integrated into a single chip for the MPU 72; they may each be integrated into separate chips.

The MPU 72 is provided with input and output ports. The input side of the MPU 72 is connected to various sensors, including the reel unit 31, a start detection sensor 41a that detects operation of the start lever 41, stop detection sensors 42a, 43a, and 44a that individually detect operation of each stop button 42, 43, and 44, an inserted medal detection sensor 45a that detects medals inserted through the medal insertion slot 45, credit insertion detection sensors 47a and 48a that individually detect operation of each credit insertion button 47 and 48, a settlement detection sensor 51a that detects operation of the settlement button 51, a payout detection sensor for the hopper device 53, a reset detection sensor that detects operation of the reset button 56 provided on the power supply device 54, and a setting key detection sensor that detects insertion of a setting key into the setting key insertion hole 57. Signals from each of these sensors are input to the MPU 72.

The output side of the MPU 72 is connected to the reel unit 31, the selector drive unit 52a provided on the selector 52, the payout motor of the hopper device 53, the credit display unit 65, the dual-purpose display unit 66, the interval display unit 67, the presentation control device 90, and other components. In each game, the MPU 72 controls the rotation and drive of each reel 32L, 32M, and 32R of the reel unit 31. The selector 52 has the function of detecting medals inserted through the medal insertion slot 45 with the inserted medal detection sensor 45a and then guiding them to the hopper device 53 if acceptance is permitted, or discharging them into the medal tray 59 without detection by the inserted medal detection sensor 45a if acceptance is prohibited. The selector drive unit 52a has the function of switching the state of the selector 52 between an acceptance permitted state and an acceptance prohibited state, specifically by operating a path switching piece provided on the selector 52 between an acceptance permitted position and an acceptance prohibited position. The MPU 72 switches the state of the selector 52 between an acceptance permission state and an acceptance prohibition state by switching between the output state and the stop state of the drive signal to the selector drive unit 52a.

When a small winning combination is achieved and medals are paid out, the MPU 72 controls the operation of the hopper device 53. The MPU 72 also controls the display of the credit display unit 65 to display the number of stored virtual medals. The MPU 72 also controls the display of the credit display unit 65 to display the current setting value when a setting value is updated. The MPU 72 also controls the display of the dual-purpose display unit 66 to display the number of gaming media that have been awarded when gaming media are awarded. The MPU 72 also controls the display of the zone display unit 67 to notify the player that the gaming zone has transitioned to the second zone SC2. The MPU 72 also controls the display of the dual-purpose display unit 66 to display a message corresponding to the game management results. The MPU 72 also sends commands to the effect control device 90 at each timing of each game, and when sending a command to the effect control device 90 to cause the image display device 63 to notify the stop order of reels 32L, 32M, and 32R, it controls the display of the combined display unit 66 so that a display corresponding to the content to be notified is displayed. In this case, direct display control of the image display device 63 is performed by the effect control device 90, while direct display control of the combined display unit 66 is performed by the MPU 72. In other words, direct display control is performed by the effect control device 90 for the image display device 63, which is subject to relatively complex display control, and direct display control is performed by the MPU 72 for the combined display unit 66, which is subject to relatively simple display control. This makes it possible to perform both displays that emphasize increasing attention to the effects and displays that emphasize reliability, while reducing the processing load on the MPU 72.

The main control board 71 is equipped with an abnormality monitoring circuit 86 that monitors whether the MPU 72 is operating normally and, if the MPU 72 is not operating normally, outputs a reset signal to the MPU 72 to return the MPU 72 to a normal state. The abnormality monitoring circuit 86 is connected to the input and output sides of the MPU 72. The abnormality monitoring circuit 86 is equipped with a watchdog timer 86a. The watchdog timer 86a is a down counter that is updated by subtracting 1 at a predetermined interval (specifically, once every 10 milliseconds), and the initial value of the watchdog timer 86a is "18H" (24). In this specification, an "H" suffixed to a number indicates that the number is expressed in hexadecimal.

The abnormality monitoring circuit 86 is electrically connected to the power supply 54, and the operating power of the abnormality monitoring circuit 86 is supplied from the power supply 54, similar to the operating power supplied to the MPU 72. The supply of operating power to the abnormality monitoring circuit 86 begins when the supply of operating power to the slot machine 10 begins, similar to the supply of operating power to the MPU 72. The abnormality monitoring circuit 86 includes an initial value setting hardware circuit that sets the watchdog timer 86a to an initial value of "18H" when the supply of operating power to the abnormality monitoring circuit 86 begins, and a subtraction hardware circuit (not shown) that subtracts 1 from the value of the watchdog timer 86a at predetermined intervals (specifically, once every 10 milliseconds) while operating power is being supplied to the abnormality monitoring circuit 86. The calculation to subtract 1 from the value of the watchdog timer 86a is performed by the subtraction hardware circuit without control by the MPU 72. The calculation to subtract 1 from the value of the watchdog timer 86a at a predetermined interval begins when the supply of operating power to the abnormality monitoring circuit 86 begins, and continues until the supply of operating power to the abnormality monitoring circuit 86 ends.

The MPU 72 can set an initial value for the watchdog timer 86a, but cannot stop the watchdog timer 86a. The watchdog timer 86a will underflow if the initial value is not set for 240 milliseconds. The MPU 72 periodically (specifically, every 1.49 milliseconds) sets the watchdog timer 86a to its initial value of "18H" during the timer interrupt process (see Figure 11), described below. Therefore, the watchdog timer 86a will not underflow when the MPU 72 is operating normally. If the watchdog timer 86a underflows, a reset signal is output to the input port of the MPU 72. When this reset signal is received, the MPU 72 initiates a program reset process. This allows the MPU 72 to return to a normal state by resetting its program if an abnormal condition occurs that prevents the MPU 72 from setting the initial value for the watchdog timer 86a.

A power outage monitoring circuit (not shown) provided in the power supply 54 is connected to the input side of the MPU 72. The power supply 54 is equipped with a power supply unit and a power outage monitoring circuit that supply drive power to the main control unit 70 and other electronic devices in the slot machine 10. The power outage monitoring circuit monitors the voltage applied to the power supply unit from an external power source and outputs a power outage signal to the MPU 72 if the voltage drops below a reference voltage. The MPU 72 executes power outage processing upon receiving the power outage signal and enables the system to return to the processing state before the power outage after power is restored. The power supply 54 also has a power outage power supply unit that supplies backup power to the RAM 74 as power during power outage when the supply of operating power from the external power source is cut off. As a result, even when the supply of operating power from the external power source is cut off, data is stored and maintained in the RAM 74 as long as the power outage power supply unit can supply backup power (for example, for one or two days).

The performance control device 90 is equipped with a performance control board 91 for controlling the execution of various notifications and performances. The performance control board 91 is equipped with an MPU 92. The MPU 92 contains a ROM 93 that stores various control programs and fixed value data executed by the MPU 92, and a RAM 94, which is memory for temporarily storing various data when the control programs stored in the ROM 93 are executed. The MPU 92 also contains a receiving circuit 87 for receiving commands sent from the MPU 72 of the main control device 70. The MPU 92 also contains a clock circuit that outputs a rectangular wave of a predetermined frequency, an interrupt circuit, a data input/output circuit, a random number generation circuit, and other circuits.

It is not essential that the ROM 93 and RAM 94 be integrated into a single chip for the MPU 92; they may each be integrated into a separate chip. Furthermore, while backup power is not supplied to the RAM 94 from the power-off power supply unit of the power supply device 54 when the supply of operating power from the external power source is cut off, backup power may be supplied to the RAM 94.

The MPU 92 is provided with an input port and an output port. As already explained, the MPU 72 of the main control unit 70 is connected to the input side of the MPU 92, and various commands are received from the MPU 72. The upper lamp 61, speaker 62, and image display device 63 are connected to the output side of the MPU 92. Based on commands received from the MPU 72 of the main control unit 70, the MPU 92 controls the light emission of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63, thereby enabling various notifications and performances to be performed.

The performance control board 91 is equipped with a video display processor (VDP), character ROM, video RAM, and other components, not shown, in addition to the MPU 92. The VDP is a type of drawing circuit that directly operates an image processing device that serves as an LCD display driver incorporated in the image display device 63. The VDP is involved in the reading and writing of data from the video RAM, and reads image data stored in the video RAM from the character ROM at predetermined times to display on the image display device 63. The character ROM serves as an image data library for storing character data such as designs to be displayed on the image display device 63. This character ROM stores bitmap image data of various display designs, a color palette table that is referenced when determining the color to be displayed for each dot in the bitmap image, and other data. The video RAM is memory for storing display data to be displayed on the image display device 63. When the MPU 92 determines the execution content of the performance based on commands received from the MPU 72 of the main control device 70, it outputs a drawing list to the VDP that specifies the image content corresponding to each update timing in accordance with the determined execution content of the performance. The VDP reads image data from the character ROM in accordance with the drawing list, and creates display data in the video RAM using the read image data. The VDP then outputs an image signal corresponding to the created display data to the image display device 63, causing the image display device 63 to display an image corresponding to the display data.

For the sake of convenience, in the following explanation, the MPU 72, ROM 73, and RAM 74 of the main control device 70 will be referred to as the main MPU 72, main ROM 73, and main RAM 74, respectively, and the MPU 92, ROM 93, and RAM 94 of the performance control device 90 will be referred to as the performance MPU 92, performance ROM 93, and performance RAM 94, respectively.

Next, we will explain the processing executed by the main MPU 72. First, we will explain the main processing executed by the main MPU 72 when the supply of operating power to the main MPU 72 begins, with reference to the flowchart in Figure 10.

The main processing begins with an initial setting process (step S101). This initial setting process performs various initial settings for registers and I/O devices within the main MPU 72. Then, interrupts are permitted by the timer interrupt process (FIG. 11) (step S102). As described above, the timer interrupt process (FIG. 11) involves setting an initial value for the watchdog timer 86a of the abnormality monitoring circuit 86 (step S204). By permitting interrupts by the timer interrupt process in step S102, the process of setting an initial value for the watchdog timer 86a (step S204) can be executed at a predetermined interval (specifically, every 1.49 milliseconds). This prevents the watchdog timer 86a from underflowing when the main MPU 72 is operating normally.

Then, it is determined whether the power is turned on with the setting key inserted into the setting key insertion hole 57 and turned on (step S103). If the power is turned on with the setting key turned on (step S103: YES), and the reset button 56 was not pressed when the power was turned on (step S104: NO), a partial clear process is performed (step S105), and then a setting value update process is performed (step S107). On the other hand, if the reset button 56 was pressed when the power was turned on (step S104: YES), then a full clear process is performed (step S106), and then a setting value update process is performed (step S107).

The partial clear process (step S105) initializes all memory areas in the main RAM 74 except for the memory area in which the second CB winning data is set (the second CB winning data area 74k, described below). The full clear process (step S106) initializes all memory areas in the main RAM 74, including the memory area in which the second CB winning data is set.

In the setting value update process, the current setting value is read and displayed on the credit display unit 65, provided that the setting key is inserted and turned ON. When the setting value update process is executed, either the partial clear process (step S105) or the full clear process (step S106) has been executed beforehand. Therefore, when the setting value update process begins, the credit display unit 65 displays a value corresponding to a setting value of "1." In the setting value update process, the setting value is updated by 1 each time the reset button 56 is operated, and the updated setting value is displayed on the credit display unit 65. Note that if the reset button 56 is operated when the setting value is "6," the setting value is updated to "1." If the setting key is released after the start lever 41 is operated, the setting value selected at that time becomes the setting value set in this setting value update process, and the setting value update process ends. In this case, the display of the setting value on the credit display unit 65 ends. After that, the process transitions to normal processing (step S108). Normal processing will be described in detail later.

If the setting key is not turned ON during the main processing (step S103: NO), the power restoration process from step S109 onward is executed. The power restoration process is a process for restoring the state of the slot machine 10 to the state before the power was shut off. In the power restoration process, the main RAM 74 is checked to determine whether the setting values of the slot machine 10 are normal (step S109). Specifically, a setting value counter stored in the main RAM 74 is determined to be normal if its value is between "1" and "6," and an abnormality is determined if its value is "0" or "7" or greater. The setting value counter is a counter that allows the main MPU 72 to grasp the current setting values of the slot machine 10. The setting value counter consists of one byte. If the setting values are normal, it is determined whether the power outage flag is set to "1" (step S110). The power outage flag is stored in the main RAM 74, and if the supply of operating power to the main MPU 72 is stopped and the predetermined power outage processing is executed normally, the power outage flag is set to "1." If the power outage flag is set to "1", it is checked whether the RAM judgment value is normal (step S111). Specifically, the checksum value of the main RAM 74 is checked to see whether the value is normal.

If the answer is affirmative in all of steps S109 to S111, this means that the power outage processing was executed normally during the previous power outage. In this case, the value of the stack pointer saved in the main RAM 74 is written to the stack pointer of the main MPU 72, and the data saved in the main RAM 74 is restored to the register of the main MPU 72, thereby restoring the state of the register of the main MPU 72 to the state before the power was interrupted (step S112). In addition, the power outage flag in the main RAM 74 is cleared to "0" (step S113).

Then, the power restoration command flag stored in the main RAM 74 is set to "1" (step S114), and the address before power was cut off is returned to (step S115). The power restoration command flag is a flag that allows the main MPU 72 to know that a power restoration command should be sent to the production MPU 92 to make it aware that power restoration processing is being executed. By setting the power restoration command flag to "1" in step S114, processing is executed to send a power restoration command to the production MPU 92 in the command output processing in step S210 of the timer interrupt processing (Figure 11), which will be described later. Details of the power restoration command will be provided later.

On the other hand, if a negative judgment is made in any of steps S109 to S111, an operation prohibition process is executed. In the operation prohibition process, the execution of the next timer interrupt process (Figure 11) is prohibited (step S116), all output ports of the main MPU 72 are cleared to "0" to turn off all actuators connected to those output ports (step S117), and an error notification process is executed to notify the hall manager or other person that an error has occurred (step S118).

Then, a power-off standby process is executed (step S119). During the power-off standby process, the watchdog timer 86a is repeatedly set to its initial value of "18H" ("24") until the supply of operating power to the main MPU 72 is stopped. If the value of the watchdog timer 86a continues to be updated without being initialized while interrupts due to the timer interrupt process (Figure 11) are prohibited, the watchdog timer 86a will underflow and a reset signal will be output. When the reset signal is received, a process to reset the program of the main MPU 72 is initiated, automatically canceling the operation-prohibited state (the state in which the operation-prohibited process is being executed). In contrast, by repeatedly executing a process to set the watchdog timer 86a to its initial value during the power-off standby process in step S119, the watchdog timer 86a can be prevented from underflowing, and the operation-prohibited state can be maintained until the power to the slot machine 10 is shut off by the gaming parlor manager. The operation prohibition state is released by executing the partial clear process (step S105) or the full clear process (step S106). Details of the program contents of the power cutoff standby process (step S119) will be described later.

Next, the timer interrupt processing executed by the main MPU 72 will be explained with reference to the flowchart in Figure 11. Note that the timer interrupt processing is initiated, for example, every 1.49 milliseconds.

In the register save process (step S201), the values of all registers in the main MPU 72 used in the normal process (Figure 13), described below, are saved to the main RAM 74. In step S202, it is checked whether the power outage flag is set to "1." If the power outage flag is set to "1," the process proceeds to step S203, where power outage processing is executed. The power outage flag is set to "1" when a power outage signal is input to the main MPU 72 from the power outage monitoring circuit of the power supply unit 54. Figure 12 is a flowchart showing the power outage processing (step S203) executed by the main MPU 72.

The power outage processing first determines whether command transmission has finished (step S301). If command transmission has not finished (step S301: NO), the power outage processing (Figure 12) ends, and the process returns to the timer interrupt processing (Figure 11) to finish command transmission. If command transmission has finished (step S301: YES), the value of the stack pointer of the main MPU 72 is saved in the main RAM 74 (step S302). The output status of the output port of the main MPU 72 is then cleared (step S303), and all actuators (not shown) are turned off (step S304). A judgment value is then calculated to determine whether the data in the main RAM 74 is normal when the power outage is resolved (step S305), and the calculated judgment value is saved in the main RAM 74 (step S306). Access to the main RAM 74 is then prohibited (step S307).

Then, similar to step S119 of the main processing (Figure 10) already described, power-off standby processing is executed (step S308). In the power-off standby processing, the watchdog timer 86a is repeatedly set to an initial value of "18H" ("24") until the supply of operating power to the main MPU 72 is stopped. In the timer interrupt processing (Figure 11), the watchdog timer 86a is set to an initial value in step S204, which will be described later. However, while the power-off standby processing (step S308) is being executed, the process of step S204 is not executed. If the value of the watchdog timer 86a continues to be updated without the process of step S204, which sets the watchdog timer 86a to an initial value, being executed, the watchdog timer 86a will underflow and a reset signal will be output. When the reset signal is received, the process of resetting the program of the main MPU 72 is initiated, automatically canceling the standby state for a power outage. By repeatedly setting the initial value in the watchdog timer 86a during the power-off standby process in step S308, it is possible to prevent the watchdog timer 86a from underflowing and prevent the program in the main MPU 72 from being reset before the supply of operating power to the main MPU 72 is stopped. Details of the program content of the power-off standby process (step S308) will be described later.

Returning to the explanation of the timer interrupt processing (Figure 11), if the power outage flag is not set to "1" in step S202, various processing is performed from step S204 onwards. In step S204, an initialization process for the watchdog timer 86a is performed, setting the watchdog timer 86a to its initial value of "18H" ("24"). This prevents the watchdog timer 86a from underflowing, and prevents the program of the main MPU 72 from being reset when the main MPU 72 is operating normally.

Then, in step S205, an interrupt end declaration process is performed, which allows the main MPU 72 itself to set the next timer interrupt. In step S206, a stepping motor control process is performed, which drives the stepping motors provided on each of the reels 32L, 32M, and 32R to rotate the reels 32L, 32M, and 32R.

In step S207, the status of various sensors connected to the input ports is read, and sensor monitoring processing is performed to monitor whether the read results are normal. In step S208, timer subtraction processing is performed to subtract values from each counter and timer. In step S209, counter processing is performed to output the results of counting the number of medals bet and the number of medals paid out to the outside. In step S210, command output processing is performed to send various commands to the performance-side MPU 92. In step S211, port output processing is performed to output data corresponding to the I/O device from the input/output port. In step S212, the values of each register saved to the main RAM 74 in the previous step S201 are restored to the corresponding register in the main MPU 72.

In step S213, management processing is performed to manage the game history and display information corresponding to the management results on the dual-purpose display unit 66. The management processing in step S213 involves processing to display on the dual-purpose display unit 66 the ratio of the total number of games played in the second section SC2 to the total number of games played. Hereinafter, the ratio of the total number of games played in the second section SC2 to the total number of games played is also referred to as the "stay ratio in the second section SC2." The stay ratio in the second section SC2 is calculated as a percentage between 0% and 100%. Also, in this specification, the display corresponding to the stay ratio in the second section SC2 executed on the dual-purpose display unit 66 is also referred to as the "ratio display." The ratio display on the dual-purpose display unit 66 is started when a ratio display start operation (described below) is performed while no games are being played, and is ended when a ratio display end operation (described below) is performed. Details of the management processing in step S213 will be described later. Then, in step S214, an interrupt permission process is performed to permit the next timer interrupt, and this series of timer interrupt processing ends.

Next, the normal processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 13. The normal processing is executed in step S108 of the main processing (Figure 10).

In normal processing, first, an interrupt permission process is performed to permit the next timer interrupt (step S401). Then, a start wait process is executed (step S402). Before explaining the start wait process (Figure 15), the configuration of the main RAM 74, which is used by the main MPU 72 to grasp the number of bets, will be explained. Figure 14 is an explanatory diagram for explaining the configuration of the main RAM 74.

As shown in FIG. 14, the main RAM 74 is provided with a bet limit counter 74a, a bet number setting counter 74b, and a bet number history counter 74c. The bet limit counter 74a is a counter that allows the main MPU 72 to grasp the bet limit, which is the upper limit of the number of gaming media that can be bet on in the current game. The bet limit counter 74a is set to "2" or "3." The bet number setting counter 74b is a counter that allows the main MPU 72 to determine the number of bets on the game to be executed. An integer between "1" and "3" is set to the bet number setting counter 74b. The bet number history counter 74c is a counter that allows the main MPU 72 to determine the number of bets on the previous game. The bet number history counter 74c is set to "2" or "3."

Next, the start waiting process executed by the main MPU 72 will be described with reference to the flowchart in Figure 15. The start waiting process is executed in step S402 of the normal process (Figure 13).

The start wait process first determines whether the replay bet setting flag stored in the main RAM 74 is set to "1" (step S501). The replay bet setting flag is a flag that allows the main MPU 72 to determine whether the same number of bets as the previous bet have already been set when a replay win was achieved in the previous game. If a negative determination is made in step S501, the main MPU 72 determines whether a replay win was achieved in the previous game by determining whether the replay win flag stored in the main RAM 74 is set to "1" (step S502). The replay win flag is a flag that allows the main MPU 72 to determine whether a replay win has been achieved. The replay win flag is set to "1" in step S1207 of the win determination process (FIG. 26) described below.

If a positive judgment is made in step S502, the value of the bet number history counter 74c in the main RAM 74 is set to the bet number setting counter 74b in the main RAM 74 (step S503). The bet number history counter 74c stores the number of bets from the previous game, and in step S503, the number of bets from the previous game stored in the bet number history counter 74c is set to the bet number setting counter 74b. In this way, if any replay win is achieved in the previous game, a bet is set equal to the number of bets from the previous game. Thereafter, the bet set flag for the replay is set to "1" (step S504), and the replay win flag in the main RAM 74 is cleared to "0" (step S505).

If a positive judgment is made in step S501, a negative judgment is made in step S502, or the processing of step S505 is executed, bet handling processing is executed (step S506). Figure 16 is a flowchart showing the bet handling processing.

In the bet processing, if the current gaming state is not the second CB state ST3 (step S601: NO), the bet upper limit counter 74a in the main RAM 74 is set to "3" as the bet upper limit, which is the upper limit of gaming media that can be bet in the current game (step S602). If the current gaming state is the second CB state ST3 (step S601: YES), the bet upper limit counter 74a in the main RAM 74 is set to "2" as the bet upper limit, which is the upper limit of gaming media that can be bet in the current game (step S603). In other words, in this slot machine 10, the bet upper limit is set to "2" when the slot machine is in the second CB state ST3, and the bet upper limit is set to "3" when the slot machine is not in the second CB state ST3.

When the processing of step S602 or step S603 is executed, on the condition that the value of the bet number setting counter 74b in the main RAM 74 is not the current bet upper limit (step S604: NO), it is determined whether one or more virtual medals have been stored and a valid bet operation has been performed (step S605). The main RAM 74 is provided with a credit counter 74d (see FIG. 14) as an area for storing the number of stored virtual medals. In step S605, it is determined whether one or more virtual medals have been stored and stored by determining whether the value of the credit counter 74d is one or more. Furthermore, if the first credit insertion button 47 (FIG. 1) has been operated, it is determined that a valid bet operation has been performed. Furthermore, if the second credit insertion button 48 (FIG. 1) has been operated, it is determined that a valid bet operation has been performed on the condition that the value of the bet number setting counter 74b is one or less.

If a positive judgment is made in step S605, a bet setting process is executed (step S606). The main MPU 72 determines the bet upper limit by referring to the bet upper limit counter 74a. In the bet setting process in step S606, when the first credit insertion button 47 is operated, if the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is equal to or greater than the bet upper limit, the value of the bet number setting counter 74b is set to the bet upper limit and the value of the number of virtual medals used in the setting is subtracted from the credit counter 74d. If the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is less than the bet upper limit, the value of the credit counter 74d is added to the bet number setting counter 74b and then the value of the credit counter 74d is cleared to "0." Furthermore, in the bet number setting process, when the second credit insertion button 48 is operated, if the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is 2 or greater, the value of the bet number setting counter 74b is set to "2" and the value of the number of virtual medals used in the setting is subtracted from the credit counter 74d; if the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is less than 2, the value of the credit counter 74d is added to the bet number setting counter 74b and then the value of the credit counter 74d is cleared to "0".

Then, the value of the award number counter 74e (Figure 14) provided in the main RAM 74 is cleared to "0" (step S607). The award number counter 74e is a counter that allows the main MPU 72 to grasp the number of gaming media awarded to a player when a small winning combination is achieved. The award number counter 74e consists of one byte. The award number counter 74e is set to "1", "2", "5", or "15". The value of the award number counter 74e is cleared to "0" when a valid bet operation is performed while one or more virtual medals are stored and stored.

If a positive determination is made in step S604, a negative determination is made in step S605, or the processing of step S607 is executed, it is determined whether one medal has been inserted into the medal insertion slot 45 and detected by the inserted medal detection sensor 45a (step S608). If a positive determination is made in step S608, and the value of the bet number setting counter 74b in the main RAM 74 is less than the upper limit number of bets (step S609: NO), the value of the bet number setting counter 74b is incremented by 1 (step S610), and if the value of the bet number setting counter 74b is equal to or greater than the upper limit number of bets (step S609: YES), the value of the credit counter 74d in the main RAM 74 is incremented by 1 (step S611).

When the processing of step S610 or step S611 is executed, the value of the award number counter 74e is cleared to "0" (step S612). In this way, the value of the award number counter 74e is cleared to "0" when a medal inserted into the medal insertion slot 45 is detected by the inserted medal detection sensor 45a. Furthermore, as described above, the value of the award number counter 74e is also cleared to "0" when a valid bet operation is performed when one or more virtual medals are stored and stored.

After that, if the value of the bet number setting counter 74b is equal to or greater than the upper limit number of bets and the value of the credit counter 74d is equal to or greater than the upper limit number of accumulated memories (specifically, "50") (step S613: YES), the acceptance prohibition process is executed (step S614). By executing the acceptance prohibition process, even if a medal is inserted into the medal insertion slot 45, the medal will be ejected into the medal tray 59 without being detected by the inserted medal detection sensor 45a.

If a negative judgment is made in step S608, if a negative judgment is made in step S613, or if the processing of step S614 is executed, the bet status management processing is executed (step S615), and this bet handling processing ends. Figure 17(a) is a flowchart showing the bet status management processing (step S615).

In the bet state management process, if the current gaming state is the first CB state ST2 (step S701: YES), the bet set flag at time of acceptance stored in the host RAM 74 is set to "1" (step S703) on the condition that the value of the bet number setting counter 74b is "3" (step S702: YES). On the other hand, if the current gaming state is not the first CB state ST2 (step S701: NO), the bet set flag at time of acceptance is set to "1" (step S703) on the condition that the value of the bet number setting counter 74b is 2 or greater (step S704: YES). The bet set flag at time of acceptance is a flag that allows the host MPU 72 to determine whether or not a sufficient number of gaming media have been bet to start one game. When the gaming state is the first CB state ST2, a single game cannot be started unless "3" gaming media have been bet, but a single game can be started only when "3" gaming media have been bet. Also, when the gaming state is not the first CB state ST2, a single game cannot be started unless two or more gaming media have been bet, but a single game can be started only when two or more gaming media have been bet.

Returning to the explanation of the start waiting process (Figure 15), after executing the bet handling process in step S506, it is determined whether the settlement button 51 has been operated (step S507). If the settlement button 51 has been operated (step S507: YES), the settlement process is executed (step S508), and then the bet set flag at the time of acceptance in the main RAM 74 is cleared to "0" (step S509), terminating the start waiting process. In the settlement process of step S508, if the bet set flag at the time of replay in the main RAM 74 is not set to "1," the hopper device 53 is driven and controlled so that the number of medals corresponding to the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d are discharged into the medal tray 59. In this case, the bet number setting counter 74b is cleared to "0," and the credit counter 74d is also cleared to "0." On the other hand, if the replay bet setting flag in the main RAM 74 is set to "1", the hopper device 53 is controlled and driven so that the number of medals corresponding to the value of the credit counter 74d is discharged into the medal tray 59. In this case, the credit counter 74d is cleared to "0".

Returning to the explanation of the normal processing (Figure 13), after the start waiting processing is executed in step S402, it is determined whether either the bet set flag at replay time or the bet set flag at acceptance time in the main RAM 74 has been set to "1" (step S403). As already explained, the bet set flag at replay time is set to "1" in step S504 of the start waiting processing (Figure 15), and the bet set flag at acceptance time is set to "1" in step S703 of the bet status management processing (Figure 17(a)).

If a negative determination is made in step S403, the process returns to step S402. If a positive determination is made in step S403, the process determines whether the start lever 41 has been operated (step S404). If the start lever 41 has not been operated, the process returns to step S402.

If the start lever 41 is operated (step S404: YES), the main line ML is activated and then the acceptance prohibition process is executed (step S405). By executing the acceptance prohibition process, even if a medal is inserted into the medal insertion slot 45, the medal will be ejected into the medal tray 59 without being detected by the inserted medal detection sensor 45a.

Then, in step S406, a start-up setting process is executed to make various settings when the game starts, in step S407 a role lottery process is executed to draw roles for the current game, and in step S408 a reel control process is executed to drive and control each of the reels 32L, 32M, and 32R in a manner corresponding to the results of the current role lottery process. Details of the start-up setting process (step S406), role lottery process (step S407), and reel control process (step S408) will be described later.

Then, the medium dispensing process is executed (step S409). In the medium dispensing process, if a small win has been achieved in the current game, a process is executed to grant the player a number of game media corresponding to the small win. Specifically, when virtual medals are to be awarded, a value corresponding to the current small win is added to the credit counter 74d of the main RAM 74, and if the value of the credit counter 74d has reached the upper limit of the stored memory number, the hopper device 53 is driven and controlled so that the number of medals exceeding the upper limit of the stored memory number are paid out to the medal tray 59.

After that, a response process at the end of play is executed to enable the setting of the game status and play area corresponding to the result of this game (step S410). In addition, an external output setting process is executed to output the status of the slot machine 10 to the gaming hall's management computer (step S411). Details of the response process at the end of play (step S410) and the external output setting process (step S411) will be described later. After that, an acceptance permission process is executed (step S412). By executing the acceptance permission process, medals inserted through the medal insertion slot 45 are detected by the inserted medal detection sensor 45a and then collected by the hopper device 53.

Next, the startup setting process executed in step S406 of the normal process (Figure 13) will be explained with reference to the flowchart in Figure 17(b).

The initial setting process begins by clearing the value of the index value counter 74f stored in the main RAM 74 to "0" (step S801). The index value counter 74f is a counter that allows the main MPU 72 to track the index value IV that was won in the role lottery process (FIG. 18), which will be described later. The index value counter 74f consists of one byte. As will be described in detail later, in the role lottery process (FIG. 18), if any of the index values IVs "1" to "17" is won, the index value counter 74f is set to that index value IV. If no index value IV is won, the index value counter 74f is set to "0." By clearing the value of the index value counter 74f to "0" in step S801, the index value IV data set in the index value counter 74f in the role lottery process (FIG. 18) can be cleared at the start of the game following the game in which the index value IV data was set in the index value counter 74f.

Then, both the bet set flag at replay and the bet set flag at acceptance in the main RAM 74 are cleared to "0" (step S802), and the in-game flag provided in the main RAM 74 is set to "1" (step S803). The in-game flag is a flag that allows the main MPU 72 to know that a game is being executed. The in-game flag is cleared to "0" in step S1510 of the response process at the end of game (Figure 32), which will be described later. The in-game flag is referenced in the management process (see Figure 27), which will be described later.

Then, the value of the bet number setting counter 74b in the main RAM 74 is set to the bet number history counter 74c in the main RAM 74 (step S804), and the initial setting process is terminated. By setting the value of the bet number setting counter 74b to the bet number history counter 74c in step S804, the main MPU 72 can determine the number of bets placed on the currently started game after it has ended. Note that when the current game has ended, the value of the bet number setting counter 74b is cleared to "0" in step S1509 of the game end response process (Figure 32) described below.

Next, the role lottery process executed in step S407 of the normal processing (Figure 13) will be explained with reference to the flowchart in Figure 18.

In step S901, a random number is obtained to be used when determining whether a winning combination has been achieved. In this slot machine 10, when the start lever 41 is operated, the random number at that time is latched from the random number circuit 75. The random number circuit 75 generates a random number between "0" and "65535", and when the main MPU 72 confirms the operation of the start lever 41, it stores the value latched in the random number circuit 75 in the main RAM 74. This configuration makes it possible to quickly obtain a random number when the start lever 41 is operated, thereby avoiding problems such as synchronization. The random number circuit 75 is configured to latch the value of the free-running counter each time the start lever 41 is operated.

After obtaining the random number, a lottery table for determining whether a winning combination will be achieved is read from the main ROM 73 (step S902). This slot machine 10 is pre-set with six setting values, from "1" to "6." By inserting a setting key into the setting key insertion hole 57, turning it ON, and performing a predetermined operation, the player can select the winning probability corresponding to the setting value for the winning combination lottery process. A setting value of "n+1" provides a more favorable winning probability for the player than "n." Specifically, since the winning probability of a given combination is higher for a setting value of "n+1" than for "n," a setting value of "n+1" is more favorable for the player than for "n." Furthermore, even with the same setting value, a bet of "3" gaming media is more favorable for the player than a bet of "2." Furthermore, there are two game states: a first CB state ST2 and a second CB state ST3. In step S902, a lottery table corresponding to the combination of the current setting value, the current number of bets, and the current gaming status is selected.

The lottery table in the non-CB state will be explained using the example where the setting value is "3". Figure 19 is an explanatory diagram for explaining the lottery table for three coins that is selected when the number of bets is "3", and Figure 20 is an explanatory diagram for explaining the lottery table for two coins that is selected when the number of bets is "2". Note that the following explanation will refer to the explanatory diagram in Figure 21 as appropriate.

As shown in Figures 19 and 20, index values IV are set in the winning combination table whether three coins or two coins are bet. Each index value IV is associated with winning data (i.e., a winning combination) that will result in a win, and a point value PV is set. The point value PV determines the winning probability of the corresponding index value IV in relation to the maximum value ("65535") of the random number circuit 75. Furthermore, the number of index values IV is the same when three coins are bet and when two coins are bet, and the type of winning data set for each index value IV is the same when three coins are bet and when two coins are bet, except for index value IV = 17.

Specifically, index values IV = 1-6 are set with the first bell winning data and one of the first through sixth supplementary winning data. When a win occurs with index value IV = 1, if the first stop (the reel on which the stop command was first issued) is the left reel 32L, the second stop (the reel on which the stop command was second issued) is the center reel 32M, and the third stop (the reel on which the stop command was last issued) is the right reel 32R, as shown in FIG. 21 , the first bell winning is guaranteed regardless of the timing of operation of the stop buttons 42-44; otherwise, the first supplementary winning may be achieved. When a win occurs with index value IV = 2, if the first stop (the reel on which the stop command was first issued) is the left reel 32L, the second stop (the reel on which the stop command was second issued) is the center reel 32M, and the third stop (the reel on which the stop command was last issued) is the right reel 32R, the first bell winning is guaranteed regardless of the timing of operation of the stop buttons 42-44; otherwise, the fourth supplementary winning may be achieved. When the index value IV = 3 is a winning combination, if the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, the first bell win is guaranteed regardless of the timing of operation of the stop buttons 42 to 44; otherwise, the third supplementary win may be achieved. When the index value IV = 4 is a winning combination, if the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, the first bell win is guaranteed regardless of the timing of operation of the stop buttons 42 to 44; otherwise, the sixth supplementary win may be achieved. When the index value IV = 5 is a winning combination, if the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the center reel 32M, the first bell win is guaranteed regardless of the timing of operation of the stop buttons 42 to 44; otherwise, the second supplementary win may be achieved. When a win occurs with index value IV = 6, if the first stop is on the right reel 32R, the second stop is on the center reel 32M, and the third stop is on the left reel 32L, the first bell win will be achieved regardless of the operation timing of each stop button 42-44; in all other cases, the fifth supplementary win may be achieved.

As already explained, in the slot machine 10, when in the non-CB state, reel control is performed on each reel 32L, 32M, and 32R, allowing the reels to slide up to four symbols after the stop buttons 42-44 are operated. In other words, reel control is performed on each reel 32L, 32M, and 32R, causing the reels to stop within the specified time (190 milliseconds) after the stop buttons 42-44 are operated. This reel control makes it easier to achieve a winning combination corresponding to a winning role, while also preventing the achievement of a winning combination corresponding to a non-winning role. However, because the amount of spin that reels 32L, 32M, and 32R can slide is limited as described above, if there are five or more symbols among the component symbols that make up the winning combination on one reel 32L, 32M, and 32R, depending on the timing of the operation of the corresponding stop buttons 42-44, it is possible that the component symbols will not stop on the main line ML (this is also known as a "missed win"). The first bell win, second bell win, and various replay wins are winning modes that will not result in a missed win if reels 32L, 32M, and 32R stop in the corresponding order. However, the first through ninth supplementary wins, first watermelon win, second watermelon win, cherry win, first CB win, and second CB win are winning modes that may result in a missed win depending on the timing of the stop buttons 42-44 operation relative to the rotational position of reels 32L, 32M, and 32R.

Index values IV = 7 to 9 are set with the second bell winning data and one of the seventh to ninth supplementary winning data. When a win occurs with index value IV = 7, as shown in FIG. 21, if the first stop is the left reel 32L, the second bell winning is guaranteed to occur regardless of the type of the second and third stop targets (reels 32L, 32M, 32R) or the operation timing of each stop button 42 to 44; otherwise, the seventh supplementary winning may occur. When a win occurs with index value IV = 8, if the first stop is the center reel 32M, the second bell winning is guaranteed to occur regardless of the type of the second and third stop targets (reels 32L, 32M, 32R) or the operation timing of each stop button 42 to 44; otherwise, the ninth supplementary winning may occur. If the index value IV = 9 and a win occurs, and the first stop is the right reel 32R, the second bell win will be achieved regardless of the type of the second and third stop targets (reels 32L, 32M, 32R) or the operation timing of each stop button 42-44; otherwise, the eighth supplementary win may be achieved.

As shown in Figures 19 and 20, first bell winning data is set for index value IV = 10. If a win occurs with index value IV = 10, as shown in Figure 21, the first bell win is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R or the operation timing of each stop button 42-44.

As shown in Figures 19 and 20, only the first watermelon winning data is set for index value IV=11. If a win occurs with index value IV=11, the first watermelon winning can be achieved regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 21. However, depending on the operation timing of each stop button 42-44, there is a possibility that the first watermelon winning will not be achieved. As shown in Figures 19 and 20, only the second watermelon winning data is set for index value IV=12. If a win occurs with index value IV=12, the second watermelon winning can be achieved regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 21. However, depending on the operation timing of each stop button 42-44, there is a possibility that the second watermelon winning will not be achieved.

As shown in Figures 19 and 20, only cherry winning data is set for index value IV = 13. If a win occurs with index value IV = 13, a cherry winning can occur regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 21. However, depending on the timing of operation of the left stop button 42 relative to the spinning position of left reel 32L, a cherry winning may not occur.

As shown in Figures 19 and 20, only the first chance replay winning data is set for index value IV = 14. If a win occurs with index value IV = 14, the first chance replay winning is guaranteed, regardless of the stopping order of reels 32L, 32M, and 32R and the timing of operation of each stop button 42 to 44, as shown in Figure 21. Also, as shown in Figures 19 and 20, only the second chance replay winning data is set for index value IV = 15. If a win occurs with index value IV = 15, the second chance replay winning is guaranteed, regardless of the stopping order of reels 32L, 32M, and 32R and the timing of operation of each stop button 42 to 44, as shown in Figure 21. Also, as shown in Figures 19 and 20, only the normal replay winning data is set for index value IV = 16. If a win occurs with index value IV = 16, as shown in Figure 21, a normal replay win is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R or the operation timing of each stop button 42-44.

For index value IV=17, only the first CB winning data is set as shown in FIG. 19 for the role selection table when three coins are bet, and only the second CB winning data is set as shown in FIG. 20 for the role selection table when two coins are bet. In other words, the first CB winning data is set as a winning role only when the number of gaming media bets is "3," and the first CB winning can only be achieved when the number of gaming media bets is "3." Furthermore, the second CB winning data is set as a winning role only when the number of gaming media bets is "2," and the second CB winning can only be achieved when the number of gaming media bets is "2." When the first CB winning data is set, if the number of gaming media bets is "3," the first CB winning can be achieved regardless of the stopping order of reels 32L, 32M, and 32R, as shown in FIG. 21. However, the first CB winning may not be achieved depending on the operation timing of each stop button 42-44. When the second CB winning data is set, if the number of gaming media bets is "2," the second CB win can be achieved regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 21. However, the second CB win may not be achieved depending on the operation timing of each stop button 42-44.

Here, winning data other than the first CB winning data and second CB winning data is erased in the game in which the winning occurred, regardless of whether the corresponding win is achieved, and is not carried over to games following the game in which the winning occurred. In contrast, the first CB winning data and second CB winning data are stored and retained in the game following the game in which the winning occurred until the corresponding win is achieved, except when the main RAM 74 is cleared (partial clearing process (step S105) or full clearing process (step S106) for the first CB winning data, and full clearing process (step S106) for the second CB winning data). In this case, in a game in which either the first CB winning data or the second CB winning data is carried over, the index values IV corresponding to the first CB winning data and the second CB winning data are excluded from the lottery.

In other words, if a game is played with the number of bets being "3," and the first CB winning data is set in the main RAM 74, but the first CB winning data is carried over because the first CB winning data is not achieved, the index value IV corresponding to the first CB winning data will be excluded from the lottery even if a game is subsequently played with the number of bets being "3," and the index value IV corresponding to the second CB winning data will be excluded from the lottery even if a game is subsequently played with the number of bets being "2." Also, if a game is played with the number of bets being "2," and the second CB winning data is set in the main RAM 74, and the second CB winning data is carried over because the second CB winning data is not achieved, the index value IV corresponding to the first CB winning data will be excluded from the lottery even if a game is subsequently played with the number of bets being "3," and the index value IV corresponding to the second CB winning data will be excluded from the lottery even if a game is subsequently played with the number of bets being "2." This makes it possible to prevent either the first CB winning data or the second CB winning data from being newly stored when either the first CB winning data or the second CB winning data has already been stored, and makes it possible to prevent multiple CB winning data from being accumulated and stored.

When the role selection table for betting three coins in FIG. 19 is selected, the probability of winning when index value IV = 1, the probability of winning when index value IV = 2, the probability of winning when index value IV = 3, the probability of winning when index value IV = 4, the probability of winning when index value IV = 5, and the probability of winning when index value IV = 6 are each approximately 1/21.8. The probability of winning when index value IV = 7, the probability of winning when index value IV = 8, and the probability of winning when index value IV = 9 are each approximately 1/21.8. The probability of winning when index value IV = 10 is approximately 1/9.4. The probability of winning when index value IV = 11 is approximately 1/164. The probability of winning when index value IV = 12 is approximately 1/146. The probability of winning when index value IV = 13 is approximately 1/423. Furthermore, the probability of winning when index value IV = 14 is approximately 1/328. Furthermore, the probability of winning when index value IV = 15 is approximately 1/164. Furthermore, the probability of winning when index value IV = 16 is approximately 1/7.3. Furthermore, the probability of winning when index value IV = 17 is approximately 1/3.3.

On the other hand, when the role selection table for two bets in Figure 20 is selected, the probability of winning for each of the index values IV = 1 to 16 is lower than when the role selection table for three bets is selected. Specifically, when the role selection table for two bets is selected, the probability of winning for each of the index values IV = 1 to 16 is less than two-thirds of the probability when the role selection table for three bets is selected. This makes it possible to increase the probability of a small role win, which involves the award of gaming media, and a replay win, which involves the award of a replay, in a game played when three gaming media are bets, compared to a game played when two gaming media are bets.

However, when the role selection table for two bets is selected, the probability of winning when the index value IV = 17 is approximately 1/2.2. In contrast, when the role selection table for three bets is selected as described above, the probability of winning when the index value IV = 17 is approximately 1/3.3. This makes it possible to increase the probability that second CB winning data is stored in the main RAM 74 in a game executed when two gaming media are bet, compared to the probability that first CB winning data is stored in the main RAM 74 in a game executed when three gaming media are bet.

In addition to the role selection table for betting three coins and the role selection table for betting two coins, the main ROM 73 also stores a CB selection table referenced in the role selection process (Figure 18) for the first CB state ST2 and the second CB state ST3. The CB selection table contains only one index value IV, and that index value IV is set to normal replay winning data. The probability of winning with that index value IV is 3/10. If the left stop button 42 is operated at the specified timing, a normal replay win is achieved regardless of the stopping order of the reels 32L, 32M, and 32R. If the left stop button 42 is not operated at the specified timing, a normal replay win is not achieved even if normal replay winning data is stored. On the other hand, if the index value IV is won but the left stop button 42 is not operated at the specified timing, or if the index value IV is not won, a first bell win may be achieved.

Here, the winning probability is the same for index values IV set to "1" through "6" for values other than index values IV = 12 and 15. This applies whether the number of gaming media bets is "3" or "2." In contrast, the winning probability for index values IV = 12 and 15 varies between the setting values of "1" through "6." Specifically, the winning probability for index value IV = 12 is lowest for a setting value of "1," with the winning probability increasing as the setting value increases and being highest for a setting value of "6." Furthermore, the winning probability for index value IV = 15 is lowest for a setting value of "1," with the winning probability increasing as the setting value increases and being highest for a setting value of "6." This makes it possible to create differences in the degree of advantage between the setting values of "1" through "6."

Returning to the explanation of the role lottery process (Figure 18), after selecting a lottery table in step S902, the index value IV is set to "1" (step S903), and then the judgment value DV used to determine whether the role is a win or a loss is set (step S904). In this judgment value setting process, the point value PV corresponding to the current index value IV is added to the current judgment value DV to set a new judgment value DV. Note that in the first judgment value setting process, the value of the random number obtained in step S901 is set as the current judgment value DV, and the point value PV corresponding to the current index value IV (index value IV = 1) is added to this random number value to set a new judgment value DV.

Then, a win/loss determination is made for the role corresponding to the index value IV (step S905). The win/loss determination for the role is made by determining whether the determination value DV exceeds "65535." If the determination value DV exceeds "65535" (step S905: YES), a setting process for the index value counter 74f provided in the main RAM 74 is executed (step S906). As already explained, the index value counter 74f is a counter that allows the main MPU 72 to grasp the index value IV that was won in the role lottery process (Figure 18). In the setting process for the index value counter 74f in step S906, the index value IV that was won this time, between "1" and "17," is set in the index value counter 74f. This allows the main MPU 72 to grasp the index value IV that was won in the role lottery process (Figure 18).

Then, a winning data acquisition process is executed (step S907). In the winning data acquisition process, winning data corresponding to the currently winning index value IV is set in the main RAM 74. As shown in FIG. 14, the main RAM 74 is provided with a first winning data area 74g, a second winning data area 74h, a first CB winning data area 74j, and a second CB winning data area 74k. The first winning data area 74g and the second winning data area 74h are one-byte storage areas in which winning data for roles corresponding to the winning index value IV in the role lottery process (FIG. 18), excluding the first CB role and the second CB role, is stored. The first CB winning data area 74j is a one-byte storage area for storing first CB winning data indicating that a first CB role has been won, and the second CB winning data area 74k is a one-byte storage area for storing second CB winning data indicating that a second CB role has been won. When the index value IV for which the first CB winning data is set in the lottery process for winning roles (FIG. 18) is won, the first CB winning data is set in the first CB winning data area 74j, and when the first CB winning is achieved, the first CB winning data is cleared from the first CB winning data area 74j. Also, when the index value IV for which the second CB winning data is set in the lottery process for winning roles (FIG. 18) is won, the second CB winning data is set in the second CB winning data area 74k, and when the second CB winning is achieved, the second CB winning data is cleared from the second CB winning data area 74k. A state in which first CB winning data is set in the first CB winning data area 74j is a state in which bit 0, the least significant bit of bits 0 to 7 of the first CB winning data area 74j, is set to "1", and a state in which second CB winning data is set in the second CB winning data area 74k is a state in which bit 0, the least significant bit of bits 0 to 7 of the second CB winning data area 74k, is set to "1".

In the winning data acquisition process in step S907, if the winning combination corresponding to the winning index value IV is a first CB combination, the first CB winning data is set in the first CB winning data area 74j (the 0th bit of the first CB winning data area 74j is set to "1"). Furthermore, if the winning combination corresponding to the winning index value IV is a second CB combination, the second CB winning data is set in the second CB winning data area 74k (the 0th bit of the second CB winning data area 74k is set to "1"). As already explained, in the combination selection table for three coins bet (Figure 19) and the combination selection table for two coins bet (Figure 20), one or two combinations are set for index values IV of "1" to "17." In the winning data acquisition process in step S907, if the combination corresponding to the winning index value IV is a combination other than the first CB combination or the second CB combination, the winning data corresponding to that combination is set in the first winning data area 74g. Furthermore, in the winning data acquisition process in step S907, if the winning combination corresponding to the winning index value IV is two combinations other than the first CB combination and the second CB combination, the two winning data corresponding to those two combinations are set in the first winning data area 74g and the second winning data area 74h.

If the judgment value DV does not exceed "65535" (step S905: NO), this means that the hand corresponding to the index value IV has not been achieved. In such a case, the index value IV is incremented by 1 (step S908), and then a determination is made as to whether or not there is a hand corresponding to the index value IV, i.e., whether or not there is a target for which a win/loss determination must be made (step S909). Specifically, a determination is made as to whether or not the index value IV after incrementing by 1 exceeds "17," the maximum value of the index value IV set in the lottery table. If there is a target for which a win/loss determination must be made, the process returns to step S904, and the determination of the win/loss of the hand continues. At this time, in step S904, the point value PV corresponding to the current index value IV is added to the judgment value DV used to determine the win/loss of the previous hand (i.e., the current judgment value DV) to obtain a new judgment value DV, and in step S905, the win/loss of the hand is determined based on this judgment value DV.

If a negative judgment is made in step S909, i.e., if none of the index values IV from "1" to "17" is selected, the value of the index value counter 74f is cleared to "0" (step S910). This allows the main MPU 72 to understand that the winning combination has been selected in the lottery process (Figure 18).

Execution of the processing of step S907 or step S910 means that the winning/losing role determination has been completed. In this case, a first stop information setting process is performed to set stop information for reel stop control (step S911). Subsequently, a favorable lottery process at the start of the game is performed (step S912), a first control process for the play area is performed (step S913), and a lottery result response process is performed (step S914). The lottery result response process in step S914 includes a process for setting a start command, described below, to be sent to the presentation-side MPU 92. The start command is a command that causes the presentation-side MPU 92 to recognize that a new game has started and is a command that causes the presentation-side MPU 92 to recognize various information determined by the main-side MPU 72. When the presentation-side MPU 92 receives the start command, it obtains various information for the current game from the game start command. The presentation-side MPU 92 then determines the content of the presentation in a manner corresponding to the various information obtained. Then, a data table corresponding to the determined effect content is read from the effect-side ROM 93 to the effect-side RAM 94, and the light emission control of the upper lamp 61, the sound output control of the speaker 62, and the display control of the image display device 63 are executed according to the read data table. Details of the advantageous lottery process at the start of the game (step S912), the first control process for the play area (step S913), and the lottery result response process (step S914) will be described later.

Next, the reel control processing executed in step S408 of the normal processing (Figure 13) will be explained with reference to the flowchart in Figure 22.

The reel control process first performs a rotation start process to start the rotation of each of the reels 32L, 32M, and 32R (step S1001). This process checks whether a predetermined wait time (e.g., 4.1 seconds) has elapsed since the rotation of the reels 32L, 32M, and 32R began in the previous game. If the wait time has not elapsed, the process waits until the wait time has elapsed. If the wait time has elapsed, the wait time for the next game is reset, and rotation start information is set in the motor control storage area in the main RAM 74. By performing this process, the stepping motor acceleration process is initiated in the stepping motor control process of step S206 in the timer interrupt process (Figure 11), and each of the reels 32L, 32M, and 32R begins to rotate.

Then, it is determined whether the acceleration period for reels 32L, 32M, and 32R has ended and each reel 32L, 32M, and 32R is now rotating at a constant predetermined speed (step S1002). If the acceleration period for reels 32L, 32M, and 32R has not ended (step S1002: NO), step S1002 is repeatedly executed until the acceleration period ends. If the acceleration period for reels 32L, 32M, and 32R has ended (step S1002: YES), an operation validation notification process is executed (step S1003). In the operation validation notification process, a lamp (not shown) provided in one-to-one correspondence with each stop button 42-44 is lit to notify the player that a stop command can now be issued. After the operation validation notification process (step S1003) is executed, the processes from step S1004 onwards are executed, which allows the stop buttons 42-44 corresponding to the spinning reels 32L, 32M, and 32R to be operated to issue a stop command. This makes it possible to stop the spinning reels 32L, 32M, and 32R.

Then, it is determined whether any of the stop buttons 42-44 has been operated (step S1004). If none of the stop buttons 42-44 have been operated (step S1004: NO), the process of step S1004 is repeated until one of the stop buttons 42-44 is operated. If it is determined that one of the stop buttons 42-44 has been operated, it is determined whether one of the stop buttons 42-44 corresponding to the spinning reels 32L, 32M, 32R has been operated, i.e., whether a stop command has been issued (step S1005). If a stop command has not been issued, the process returns to step S1004, and steps S1004 and S1005 are repeated until one of the stop buttons 42-44 is operated.

If a stop command is issued (step S1005: YES), an operation invalidation notification process corresponding to the currently operated stop button 42-44 is executed (step S1006). In step S1006, of the lamps (not shown) of each stop button 42-44 that were lit in the operation validation notification process in step S1003, the lamp corresponding to the currently operated stop button 42-44 is switched to an extinguished state. This allows the player to identify the stop buttons 42-44 for which a stop command has already been issued.

Then, a stop command is sent to the production-side MPU 92 (step S1007). The stop command is a command that causes the production-side MPU 92 to recognize which stop button 42-44 was operated to issue the stop command. When a stop command is sent, the stop control process shown in steps S1008-S1014 is performed to stop the spinning reels.

In the stop control process, the symbol number of the reaching symbol that has reached the base position (specifically, the bottom row) at the time the stop buttons 42-44 are operated is confirmed (step S1008). Specifically, the symbol number of the reaching symbol that has reached the base position is confirmed based on the number of excitation pulses output from the time the detection signal of the reel index sensor is input. Then, based on the stop information stored in the main RAM 74, the number of slips of the reels 32L, 32M, and 32R that should be stopped this time is calculated (step S1009).

In this slot machine 10, five stop patterns are available for stopping each reel 32L, 32M, 32R when the stop buttons 42-44 are operated: a stop pattern in which the reaching symbol that has reached the base position is stopped as is; a stop pattern in which the corresponding reel 32L, 32M, 32R slides by one symbol and then stops; a stop pattern in which the reel slides by two symbols and then stops; a stop pattern in which the reel slides by three symbols and then stops; and a stop pattern in which the reel slides by four symbols and then stops. Therefore, in step S1009, the number of slips is calculated as a value between "0" and "4" based on the stop information stored in the main RAM 74.

Then, the calculated slip count is added to the symbol number of the reached symbol to determine the symbol number of the stopped symbol that will actually stop at the base position (step S1010). Then, it is determined whether the symbol number of the reached symbol on reels 32L, 32M, and 32R that should be stopped this time is equal to the symbol number of the stopped symbol (step S1011). If they are equal, a reel stop process is performed to stop the rotation of reels 32L, 32M, and 32R (step S1012). Then, it is determined whether all reels 32L, 32M, and 32R have stopped (step S1013). If all reels 32L, 32M, and 32R have not stopped, a second stop information setting process is performed (step S1014), and the process returns to step S1004.

Here, stop information refers to information that causes the stop patterns of each reel 32L, 32M, and 32R to correspond to the results of the role lottery process (Figure 18). Using this stop information, it is possible to calculate the number of slips (specifically, "0" to "4") for the reaching symbol that reaches the base position when each stop button 42-44 is stopped. This stop information includes slip number data indicating the correspondence between each symbol and the number of slips, which is stored in advance in the main ROM 73 in correspondence with each lottery result and the stop order of each reel 32L, 32M, and 32R. However, this is not limited to this, and the slip number data corresponding to each lottery result and the stop order of each reel 32L, 32M, and 32R may be derived while the reels 32L, 32M, and 32R are spinning, for example.

The processes for setting the stop information include a first stop information setting process executed in step S911 of the winning combination lottery process (FIG. 18), and a second stop information setting process executed in step S1014 of the reel control process (FIG. 22). In the first stop information setting process, stop information is set according to the results of the winning combination lottery process. In the second stop information setting process, the stop information stored in the main RAM 74 in the first stop information setting process or the previous second stop information setting process is changed after the reels have stopped. In the second stop information setting process, the stop information is changed based on the set winning data, the stop order of reels 32L, 32M, and 32R, and the stop results of stopped reels 32L, 32M, and 32R.

If step S1013 determines that all reels 32L, 32M, and 32R are stopped, a win determination process is executed (step S1015). In this win determination process, the type of symbols stopped on the main line ML on each reel 32L, 32M, and 32R is identified. Based on the winning data stored in the main RAM 74, it is then determined whether the combination of symbols stopped on the main line ML on each reel 32L, 32M, and 32R corresponds to a winning combination in the winning combination lottery process. If the combination corresponds to a winning combination, a winning combination is determined to have been achieved. If a winning combination is determined to have been achieved, if the winning combination is a minor combination, information on the number of gaming media to be awarded is set in the main RAM 74 so that gaming media can be awarded in the media awarding process. If the winning combination is a replay combination, a flag is set to enable the replay setting process to be executed in the next start waiting process (FIG. 15). Details of the winning determination process (step S1015) will be described later.

After executing the winning determination process, the winning result command flag stored in the main RAM 74 is set to "1" (step S1016). The winning result command flag is a flag that allows the main MPU 72 to determine that a winning result command should be sent to the production MPU 92. By setting the winning result command flag to "1" in step S1016, a winning result command sending process is executed in step S2705 of the command output process (FIG. 44) described below, in which the winning result command is sent to the production MPU 92. The winning result command is set with data stored in the first CB winning data area 74j and the second CB winning data area 74k in the main RAM 74, as well as data stored in the winning data area 78 stored in the main RAM 74. The winning data area 78 is a memory area in which one byte of data is stored that allows the main MPU 72 to determine the winning combination that resulted in a winning game in this game. The presentation-side MPU 92 determines whether or not a win has been achieved based on the data set in the winning result command, and if a win has been achieved, determines the type of win. It then controls the light emission of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63 so that a presentation corresponding to the information determined from the winning result command is performed.

<About game status and game zone>
Next, the gaming states and gaming intervals will be explained. Figure 23 is an explanatory diagram for explaining the gaming states and gaming intervals that exist in the slot machine 10.

The slot machine 10 has four game states: a normal game state ST1, a first CB state ST2, a second CB state ST3, a pseudo bonus state ST4, an AT state ST5, and an end preparation state ST6. These game states do not overlap with each other.

Normal gaming state ST1 is a gaming state that is entered by executing a partial clear process (step S105) or a full clear process (step S106) of the main RAM 74. Furthermore, when the first CB state ST2 or second CB state ST3 that occurs in normal gaming state ST1 ends, or when the end preparation state ST6 ends, the gaming state becomes normal gaming state ST1. In normal gaming state ST1, one game can be played regardless of whether the number of gaming media bets is "3" or "2."

In normal gaming state ST1, whether three coins or two coins are bet, the expected net increase in gaming media per game (the value obtained by subtracting the number of gaming media bet in one game from the expected number of gaming media awarded in one game) is zero or less. Furthermore, normal gaming state ST1 exists in a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

The first CB state ST2 is a gaming state to which the player enters when a first CB win occurs when the first CB winning data is stored in the main RAM 74. In the first CB state ST2, one game can be played when the number of gaming media bets is "3", but one game cannot be played when the number of gaming media bets is "2". Furthermore, the second CB state ST3 is a gaming state to which the player enters when a second CB win occurs when the second CB winning data is stored in the main RAM 74. In the second CB state ST3, one game can be played when the number of gaming media bets is "2", but because the maximum bet limit is set to "2", it is not possible to bet "3" gaming media.

The first CB state ST2 and the second CB state ST3 are game states in which the number of game media owned by the player does not increase. Furthermore, both the first CB state ST2 and the second CB state ST3 are game states in which the number of game media owned by the player at the end of the game state is less than the number of game media owned by the player at the start of the game state. Details of the first CB state ST2 and the second CB state ST3 will be explained later.

The pseudo bonus state ST4 is a gaming state that is entered when the conditions for entering the pseudo bonus state ST4 are met in the normal gaming state ST1. The pseudo bonus state ST4 ends when the number of remaining games to continue in the pseudo bonus state ST4 becomes "0" or when the ending conditions of the second section SC2 are met. If the pseudo bonus state ST4 ends without the ending conditions of the second section SC2 described below being met and the conditions for entering the AT state ST5 are not met, the state transitions to the end preparation state ST6. Furthermore, if the pseudo bonus state ST4 ends when the ending conditions of the second section SC2 described below are met, the state transitions to the normal gaming state ST1.

In pseudo bonus state ST4, one game can be played regardless of whether the number of gaming media bets is "3" or "2." In pseudo bonus state ST4, there are two states: a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

In pseudo bonus state ST4, if an index value IV of 1 to 6 is achieved, the stopping order of reels 32L, 32M, and 32R that allows for the first bell win is announced. Furthermore, in pseudo bonus state ST4, if an index value IV of 7 to 9 is achieved, the stopping order of reels 32L, 32M, and 32R that allows for the second bell win is announced. If the first bell win or the second bell win is achieved, 15 gaming media are awarded. This makes it possible to increase the expected number of gaming media awarded in one game in pseudo bonus state ST4. In pseudo bonus state ST4, if three coins are bet, the expected net increase in gaming media in one game will be greater than zero. In pseudo bonus state ST4, if two coins are bet, the expected net increase in gaming media in one game will be zero or less.

The AT state ST5 is a gaming state to which a transition to the AT state ST5 occurs when the transition conditions to the AT state ST5 are met in the pseudo bonus state ST4. The AT state ST5 ends when the number of remaining games to be continued in the AT state ST5 becomes "0" or when the ending conditions of the second section SC2 are met. If the AT state ST5 ends without the ending conditions of the second section SC2 described below being met and the second section SC2 ends when transitioning to the normal gaming state ST1, a transition to the end preparation state ST6 occurs. If the AT state ST5 ends without the ending conditions of the second section SC2 described below being met and the second section SC2 does not end when transitioning to the normal gaming state ST1, a transition to the normal gaming state ST1 occurs without transitioning to the end preparation state ST6. Furthermore, if the AT state ST5 ends when the ending conditions of the second section SC2 described below are met, a transition to the normal gaming state ST1 occurs.

In AT state ST5, one game can be played regardless of whether the number of gaming media bets is "3" or "2." AT state ST5 has a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

In AT state ST5, if an index value IV of 1 to 6 is won, the stopping order of reels 32L, 32M, and 32R that will result in a first bell win is announced. Furthermore, in AT state ST5, if an index value IV of 7 to 9 is won, the stopping order of reels 32L, 32M, and 32R that will result in a second bell win is announced. If a first bell win or a second bell win is won, 15 gaming media are awarded. This makes it possible to increase the expected number of gaming media awarded in one game in AT state ST5. When three coins are bet in AT state ST5, the expected net increase in gaming media in one game will be greater than zero, and when two coins are bet in AT state ST5, the expected net increase in gaming media in one game will be less than zero.

The end preparation state ST6 is the gaming state to which the game is transitioned when the pseudo bonus state ST4 ends without the ending conditions of the second section SC2 described below being met and the conditions for transitioning to the AT state ST5 being met. The end preparation state ST6 is also the gaming state to which the game is transitioned when the AT state ST5 ends without the ending conditions of the second section SC2 described below being met, and the second section SC2 ends upon the subsequent transition to the normal gaming state ST1.

The end preparation state ST6 ends when one game has been played. When the end preparation state ST6 ends, the game transitions to the normal game state ST1. In the end preparation state ST6, one game can be played regardless of whether the number of gaming media bets is "3" or "2." The end preparation state ST6 is a game state in which the expected net increase in gaming media in one game is "0" or less, regardless of whether three or two gaming media are bet. The end preparation state ST6 also exists in two states: a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

As described above, in a configuration in which various game states (normal game state ST1, first CB state ST2, second CB state ST3, pseudo bonus state ST4, AT state ST5, and end preparation state ST6) exist, game intervals are set separately from these game states. The game intervals are set as first interval SC1 and second interval SC2. In other words, in this slot machine 10, the factors that determine the game situation are the number of gaming media bets of "2" and "3," the setting values of "1" to "6," the various game states, and the game intervals of first interval SC1 and second interval SC2.

The first section SC1 is a section in which an advantageous gaming state (pseudo-bonus state ST4 and AT state ST5) is not initiated, in which the expected net increase in gaming media in one game (the value obtained by subtracting the number of gaming media bet in one game from the expected number of gaming media awarded in one game) can be greater than zero when the stopping order of reels 32L, 32M, and 32R is notified, and the advantageous gaming state does not continue. When the partial clearing process (step S105) or full clearing process (step S106) of the main RAM 74 is performed, the normal gaming state ST1 is entered, and the first section SC1 is entered. Furthermore, the first section SC1 is entered when the initialization process for second section SC2 is performed in second section SC2. The second section SC2 is a section in which the advantageous gaming state can begin and continue.

As described above, when the partial clear process (step S105) or full clear process (step S106) of the main RAM 74 is executed, the first section SC1 is entered, and when the initialization process for the second section SC2 is executed, the first section SC1 is entered. On the other hand, the second section SC2 is entered from the first section SC1 when a transition trigger to the second section SC2 occurs based on the role lottery process (Figure 18) in the first section SC1. In this case, a transition trigger to the second section SC2 may occur if a game with a bet of "3" is played in the first section SC1, but a transition trigger to the second section SC2 will not occur even if a game with a bet of "2" is played in the first section SC1. Therefore, a player hoping to transition to the second section SC2 in the first section SC1 should play a game with a bet of "3" rather than a game with a bet of "2."

In the first section SC1, the expected net increase in gaming media per game is always zero or less, whereas in the second section SC2, the expected net increase in gaming media per game is not only zero or less, but can also be greater than zero. Therefore, the second section SC2 is a more advantageous situation than the first section SC1. Therefore, players will expect to transition to the second section SC2 in the first section SC1.

The first section SC1 ends when a transition trigger to the second section SC2 occurs, and a transition to the second section SC2 occurs. In contrast, the second section SC2 can end when the pseudo-bonus state ST4, AT state ST5, or termination preparation state ST6 ends and a transition to the normal gaming state ST1 occurs. When the second section SC2 ends, a transition to the first section SC1 occurs. Furthermore, the ending condition for the second section SC2 is set such that either the total number of games played reaches the upper limit number of games (specifically, 1,500 games) as the second section SC2 continues without a transition to the first section SC1, or the limited total net increase in the number of gaming media reaches the upper limit net increase number (specifically, 2,400) as the second section SC2 continues without a transition to the first section SC1. The limited total net increase in gaming media refers to the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined reference value, and the difference is calculated by subtracting the total number of gaming media consumed to play games while the second section SC2 is continuing (0 when no games are being played) from the total number of gaming media awarded through games played while the second section SC2 is continuing (0 when no gaming media are awarded).

In other words, if the limited total net increase in gaming media since the start of second section SC2 reaches the upper limit as a result of the continuation of second section SC2, second section SC2 ends and a transition to first section SC1 occurs. Also, if the number of games played since the start of second section SC2 reaches the upper limit as a result of the continuation of second section SC2, second section SC2 ends and a transition to first section SC1 occurs. If either of these ending conditions is met, even if the game is in the middle of pseudo-bonus state ST4 or AT state ST5, pseudo-bonus state ST4 or AT state ST5 ends in the game where the ending condition was met, and second section SC2 ends, resulting in a transition to first section SC1 and normal game state ST1. This makes it possible to prevent second section SC2 from continuing excessively.

As shown in Figure 23, the normal game state ST1, first CB state ST2, and second CB state ST3 can be entered in either the first section SC1 or the second section SC2. On the other hand, the pseudo bonus state ST4, AT state ST5, and end preparation state ST6 are never entered in the first section SC1, but only in the second section SC2.

As already explained, in the normal game state ST1, pseudo bonus state ST4, AT state ST5, and end preparation state ST6, it is possible to run a game whether the number of gaming media bets is "3" or "2." In the first CB state ST2, it is possible to run a game only when the number of gaming media bets is "3," and in the second CB state ST3, it is possible to run a game only when the number of gaming media bets is "2."

When in the normal gaming state ST1 in the second section SC2, the expected net increase in gaming media is "0" or less whether a game with a bet of "3" is played or a game with a bet of "2" is played. In this case, in the normal gaming state ST1 in the second section SC2, as described below, a lottery process for transitioning to the pseudo-bonus state ST4 may be executed based on the results of the lottery process ( FIG. 18 ) for each game. However, this lottery process is executed for games with a bet of "3" but not for games with a bet of "2." Also, in the normal gaming state ST1 in the second section SC2, as described below, the value of the release game counter stored in the main RAM 74 is decremented by one each time a game is played. If the value of the release game counter after the decrement is "0," transition to the pseudo-bonus state ST4 is confirmed. However, this decrement of the release game counter is executed for games with a bet of "3" but not for games with a bet of "2." Therefore, in the normal gaming state ST1 in the second section SC2, it is more advantageous for the player to have a game with a bet of "3" played than to have a game with a bet of "2". The release game number counter is a counter that allows the main MPU 72 to determine the remaining number of release games, which is the number of games required to transition to the pseudo-bonus state ST4, when none of the first to third transition confirmation flags in the main RAM 74 are set to "1".

In the pseudo bonus state ST4, when a game with a bet of "3" is executed, the expected net increase in gaming media can be greater than "0," whereas when a game with a bet of "2" is executed, the expected net increase in gaming media is less than "0." Therefore, in the pseudo bonus state ST4, it is more advantageous for the player to execute a game with a bet of "3" than to execute a game with a bet of "2." In the pseudo bonus state ST4, as described below, a lottery process for transitioning to the AT state ST5 can be executed based on the results of the lottery process ( FIG. 18 ) for each game. However, this lottery process is executed in games with a bet of "3," but is not executed in games with a bet of "2." Therefore, from this perspective, in the pseudo bonus state ST4, it is more advantageous for the player to execute a game with a bet of "3" than to execute a game with a bet of "2."

In the AT state ST5, if a game with a bet of "3" is executed, the expected net increase in gaming media can be greater than "0," whereas if a game with a bet of "2" is executed, the expected net increase in gaming media is less than "0." Therefore, in the AT state ST5, it is more advantageous for the player to execute a game with a bet of "3" than to execute a game with a bet of "2." In the AT state ST5, as described below, an additional lottery process can be executed to determine whether to increase the remaining number of games to be played in the AT state ST5 based on the results of the lottery process for the winning combination in each game (FIG. 18). However, this additional lottery process is executed in games with a bet of "3," but is not executed in games with a bet of "2." Therefore, from this perspective, in the AT state ST5, it is more advantageous for the player to execute a game with a bet of "3" than to execute a game with a bet of "2."

As described above, even if it is advantageous to execute games with a bet of "3" in the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2, the number of gaming media awarded in games with a bet of "2" in any of the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2 is added to the limited total net increase in gaming media in the second section SC2, and games with a bet of "2" in any of the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2 are added to the total number of games executed as the second section SC2 continues. In other words, even though games with a bet of "2" in any of the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2 are disadvantageous to the player, such games contribute to achieving the ending conditions of the second section SC2. From this perspective, when the player is in the normal game state ST1, pseudo bonus state ST4, or AT state ST5 in the second section SC2, it is more advantageous for the player to have a game with a bet of "3" executed than to have a game with a bet of "2" executed.

Even in the second section SC2, a first CB win and a second CB win are possible, just like in the first section SC1. If a first CB win is achieved in the second section SC2, the first CB state ST2 is entered in the second section SC2, and the second section SC2 is maintained in the first CB state ST2 and after the first CB state ST2 ends. Furthermore, if a second CB win is achieved in the second section SC2, the second CB state ST3 is entered in the second section SC2, and the second section SC2 is maintained in the second CB state ST3 and after the second CB state ST3 ends. As already explained, the first CB state ST2 and the second CB state ST3 are game states in which the number of game media owned by the player at the end of the game state is less than the number of game media owned by the player at the start of the game state. In other words, the first CB state ST2 and the second CB state ST3 are game states that are disadvantageous to the player. On the other hand, games played in either the first CB state ST2 or the second CB state ST3 in the second section SC2 are added to the total number of games played as the second section SC2 continues. In other words, even though games played in the first CB state ST2 and the second CB state ST3 are disadvantageous to the player, those games contribute to achieving the ending conditions of the second section SC2. Therefore, if the first CB state ST2 or the second CB state ST3 occurs in the second section SC2, it will be even more disadvantageous to the player.

In the end preparation state ST6, the expected net increase in gaming media is "0" or less whether a game with a bet of "3" or a game with a bet of "2" is played in the second section SC2. However, the second section SC2 ends with the end of the pseudo bonus state ST4 or AT state ST5, and only one game is played. Therefore, games played in the end preparation state ST6 do not contribute to the limited total net increase in gaming media in the second section SC2, nor do they contribute to the total number of games played in the second section SC2. However, this is not limited to this, and games played in the end preparation state ST6 may contribute to the limited total net increase in gaming media in the second section SC2 and also contribute to the total number of games played in the second section SC2.

<CB states ST2 and ST3>
Next, the first CB state ST2 and the second CB state ST3 will be described in detail. The first CB role can be a winning combination in a game with a bet number of "3," but cannot be a winning combination in a game with a bet number of "2." In a game with a bet number of "3," the first CB role is won with a probability of approximately 1/3.3. However, in the case of a first CB role winning combination (i.e., a state in which the first CB winning data is stored in the main RAM 74), a second CB role winning combination (i.e., a state in which the second CB winning data is stored in the main RAM 74), the first CB state ST2, or the second CB state ST3, the first CB role is excluded from the lottery targets in the role lottery process (FIG. 18).

The second CB role can be won in games with a bet of "2", but cannot be won in games with a bet of "3". In games with a bet of "2", the probability of winning the second CB role is approximately 1/2.2. However, if the first CB role is in a winning state (i.e., the first CB winning data is stored in the main RAM 74), the second CB role is in a winning state (i.e., the second CB winning data is stored in the main RAM 74), or the first CB state ST2 or second CB state ST3 is in effect, the second CB role is excluded from the lottery in the role lottery process (Figure 18).

When the first CB role is in a winning state, the first CB win can be achieved in a game with a bet of "3," but the first CB win cannot be achieved in a game with a bet of "2." Therefore, when a game with a bet of "2" is played in a winning state for the first CB role, even if the lottery process (Figure 18) results in a loss result that does not match any of the index values IV, the first CB win cannot be achieved regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stop operation of stop buttons 42-44. Furthermore, when a game with a bet of "2" is played in a winning state for the first CB role, even if the lottery process (Figure 18) results in a win with an index value IV that could result in a so-called missed win, the first CB win cannot be achieved regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stop operation of stop buttons 42-44. When a game with a bet of "3" is played in the first CB winning state and the first CB win is achieved, the first CB state ST2 is entered.

In the first CB state ST2, it is possible to play a game with a bet of 3, but it is not possible to play a game with a bet of 2 or less. In the first CB state ST2, normal replay winning data is stored in the main RAM 74 with a probability of 3/10 during the lottery process (Figure 18) for each game, and when normal replay winning data is stored, if the left stop button 42 is operated at the specified timing, a normal replay win is achieved regardless of the stopping order of reels 32L, 32M, and 32R. If the left stop button 42 is not operated at the specified timing, a normal replay win is not achieved even if normal replay winning data is stored.

In the first CB state ST2, if the normal replay winning data is not stored in the main RAM 74 during the role selection process (Figure 18), or if the normal replay winning data is stored in the main RAM 74 but the left stop button 42 is not operated at the specified timing, preventing the normal replay winning, the first bell winning may occur. In this case, the first bell winning occurs regardless of the stopping order of the reels 32L, 32M, and 32R, but the first bell winning may not occur depending on the timing of the stop operation of the left stop button 42.

However, this is not limited to this, and if normal replay winning data is stored in the main RAM 74 during the role selection process (Figure 18) in the first CB state ST2, a normal replay winning may be reliably achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each stop button 42-44. Also, if normal replay winning data is not stored in the main RAM 74 during the role selection process (Figure 18) in the first CB state ST2, a first bell winning may be reliably achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each stop button 42-44.

If the first bell win occurs in the first CB state ST2, one gaming medium is awarded. As already explained, in the first CB state ST2, a game can only be played if three gaming media have been bet. In contrast, the number of gaming media awarded in a game in the first CB state ST2 is one. The first CB state ST2 ends when thirty gaming media have been awarded. Therefore, in the first CB state ST2, it is necessary to generate 30 events in which one gaming medium is awarded in a game played by betting three gaming media. In this case, the number of gaming media owned by the player will decrease by at least 60 from the start to the end of the first CB state ST2. Therefore, the first CB state ST2 is a gaming state that is disadvantageous to the player.

Furthermore, in the first CB state ST2, as described above, a normal replay win may occur, but it is also possible that neither a normal replay win nor a first bell win may occur. In this case, if the first CB state ST2 occurs in the second section SC2, the first CB state ST2, which is disadvantageous to the player, will continue for 30 or more games, and the number of games will be added to the total number of games played in the second section SC2.

When the second CB role is in a winning state, the second CB win can be achieved in a game with a bet of "2," but the second CB win cannot be achieved in a game with a bet of "3." Therefore, when a game with a bet of "3" is played in a winning state for the second CB role, even if the lottery process (Figure 18) results in a loss result that does not match any of the index values IV, the second CB win cannot be achieved regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stop operation of stop buttons 42-44. Furthermore, when a game with a bet of "3" is played in a winning state for the second CB role, even if the lottery process (Figure 18) results in a win with an index value IV that could result in a so-called missed win, the second CB win cannot be achieved regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stop operation of stop buttons 42-44. When a game with a bet of "2" is played in the second CB winning state and the second CB win is achieved, the second CB state ST3 is entered.

In the second CB state ST3, a game can be played when the number of bets is "2," and the upper limit for the number of gaming media bets is "2." In the second CB state ST3, normal replay winning data is stored in the main RAM 74 with a probability of 3/10 during the lottery process (FIG. 18) for each game. When normal replay winning data is stored, if the left stop button 42 is operated at the specified timing, a normal replay win is achieved regardless of the stopping order of reels 32L, 32M, and 32R. If the left stop button 42 is not operated at the specified timing, a normal replay win is not achieved even if normal replay winning data is stored.

In the second CB state ST3, if the normal replay winning data is not stored in the main RAM 74 during the role selection process (Figure 18), or if the normal replay winning data is stored in the main RAM 74 but the left stop button 42 is not operated at the specified timing, preventing the normal replay winning, the first bell winning may occur. In this case, the first bell winning occurs regardless of the stopping order of the reels 32L, 32M, and 32R, but the first bell winning may not occur depending on the timing of the stop operation of the left stop button 42.

However, this is not limited to this, and if normal replay winning data is stored in the main RAM 74 during the role selection process (Figure 18) in the second CB state ST3, a normal replay winning may be reliably achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each stop button 42-44. Also, if normal replay winning data is not stored in the main RAM 74 during the role selection process (Figure 18) in the second CB state ST3, a first bell winning may be reliably achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each stop button 42-44.

If the first bell win occurs in the second CB state ST3, one gaming medium is awarded. As already explained, in the second CB state ST3, a game can only be played if two gaming media have been bet. In contrast, the number of gaming media awarded in a game in the second CB state ST3 is one. The second CB state ST3 ends when thirty gaming media have been awarded. Therefore, in the second CB state ST3, it is necessary to have 30 instances of an event in which one gaming medium is awarded in a game played by betting two gaming media. In this case, the number of gaming media owned by the player will decrease by at least 30 from the start to the end of the second CB state ST3. Therefore, the second CB state ST3 is a disadvantageous gaming state for the player. However, this disadvantageous degree in the second CB state ST3 is lower than in the first CB state ST2.

Furthermore, in the second CB state ST3, as described above, a normal replay win may occur, but it is also possible that neither a normal replay win nor a first bell win may occur. In this case, if the second CB state ST3 occurs in the second section SC2, the second CB state ST3, which is disadvantageous to the player, will continue for 30 or more games, and the number of games will be added to the total number of games played in the second section SC2.

In a configuration in which the first CB state ST2 and the second CB state ST3 are set as game states unfavorable to the player as described above, by playing a game with a bet of "2" to enter a winning state for the second CB role and prevent the second CB win from being achieved, and then playing a game with a bet of "3," it becomes possible to play without transitioning to the first CB state ST2 or the second CB state ST3, regardless of the result of the role selection process (Figure 18) for each game, and regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stop operation of each stop button 42-44. In other words, if a winning state for the second CB role is entered by playing a game with a bet of "2," then a second CB win will not be achieved even if the second CB role is in a winning state by subsequently playing a game with a bet of "3." Furthermore, even if a game with a bet number of "3" is played in the winning state of the second CB role, the first CB role is excluded from the lottery in the role selection process (FIG. 18), so the first CB role will not be won. Since the first CB role is not won, the first CB win will not be achieved, and the game state will not transition to the first CB state ST2. This makes it possible to play a game with a bet number of "3" while preventing transitions to the first CB state ST2 and the second CB state ST3. Playing a game with a bet number of "3" can result in a transition to the second section SC2, as already explained, and a transition to the pseudo-bonus state ST4.

The probability of winning the second CB role in a game with a bet of "2" is approximately 1/2.2, while the probability of winning the first CB role in a game with a bet of "3" is approximately 1/3.3. In other words, the probability of winning the second CB role is set higher than the probability of winning the first CB role. This makes it possible to reduce the number of games required to achieve the winning state of the second CB role when a game with a bet of "2" is played at an amusement hall or the like to achieve the winning state of the second CB role. On the other hand, even if a game with a bet of "3" is played before accidentally achieving the winning state of the second CB role, the probability of winning the first CB role is lower than the probability of winning the second CB role, making it more difficult to win the first CB role.

Note that the configuration is not limited to one in which the probability of winning the second CB role is higher than the probability of winning the first CB role; it may be one in which the probability of winning the first CB role is higher than the probability of winning the second CB role, or one in which the probability of winning the first CB role and the probability of winning the second CB role are the same or approximately the same.

<Display Contents on Dual-Purpose Display Unit 66>
Next, we will explain the display contents on the dual-purpose display unit 66. As already explained, the dual-purpose display unit 66 displays a stop order corresponding display that displays information corresponding to the stop order of the reels 32L, 32M, and 32R, a ratio display that displays the stay ratio in the second section SC2, and a number of awards display based on the value of the number of awards counter 74e in the main RAM 74.

As already explained, the main RAM 74 is provided with an award number counter 74e (Figure 14) that enables the main MPU 72 to grasp the number of gaming media awarded to a player when a small winning combination is achieved. The value of the award number counter 74e is cleared to "0" in step S607 when a valid bet operation is performed while one or more virtual medals are stored in the bet processing (Figure 16) already explained, and is also cleared to "0" in step S612 when a medal inserted into the medal insertion slot 45 is detected by the inserted medal detection sensor 45a.

As already explained with reference to Figure 7(b), there are first through ninth stop orders for the reels 32L, 32M, and 32R that are notified by the image display device 63, and there are also first through ninth stop order corresponding displays that are executed by the dual-purpose display unit 66. As shown in Figure 14, the main RAM 74 is provided with a stop order type counter 74m and a ratio display counter 74n. The stop order type counter 74m is a counter that enables the main MPU 72 to grasp the stop order type number that indicates the type of display corresponding to the stop order of the reels 32L, 32M, and 32R that should be displayed on the dual-purpose display unit 66 when the stop order corresponding display is executed. The stop order type counter 74m consists of one byte. A stop order type number from "1" to "9" or "0," which indicates that the stop order corresponding display is not executed on the dual-purpose display unit 66, is set to the stop order type counter 74m.

The ratio display counter 74n is a counter that indicates that a ratio display should be performed on the dual-purpose display unit 66 and allows the main MPU 72 to grasp the calculation result data of the stay ratio for the second section SC2 that is to be displayed in the ratio display. The ratio display counter 74n consists of one byte. The ratio display counter 74n's initial value is "255," a value indicating that a ratio display will not be performed on the dual-purpose display unit 66. If a partial clear process is performed in step S105 of the main process (Figure 10) or a full clear process is performed in step S106, the ratio display counter 74n is set to the initial value ("255"). In the management process in step S213 of the timer interrupt process (Figure 11), if an operation to start the ratio display (described below) is performed while the game is not being executed, a calculation is performed to calculate the stay ratio for the second section SC2 within the range of 0% to 100%, and the calculation result is set in the ratio display counter 74n. The ratio display counter 74n is set with numerical information between "0" and "100" as the calculation result data of the stay ratio for the second section SC2. When the calculation result data between "0" and "100" is set in the ratio display counter 74n, the combined display unit 66 displays the ratio corresponding to that calculation result data. In the management process in step S213 of the timer interrupt process (FIG. 11), if an operation to end the ratio display, which will be described later, is performed, the ratio display counter 74n is set to its initial value of "255". This ends the ratio display on the combined display unit 66. Details of the management process (step S213) will be described later.

Figure 24(a) is an explanatory diagram illustrating the conditions under which the stop order display, ratio display, and award number display are performed on the dual-purpose display unit 66. As shown in Figure 24(a), the stop order display is performed on the dual-purpose display unit 66 on the condition that a stop order type number between "1" and "9" is set in the stop order type counter 74m in the main RAM 74. Furthermore, the ratio display is performed on the dual-purpose display unit 66 on the condition that a calculation result data between "0" and "100" is set in the ratio display counter 74n. Furthermore, the award number display is performed on the dual-purpose display unit 66 on the condition that a stop order type number between "1" and "9" is not set in the stop order type counter 74m and that a calculation result data between "0" and "100" is not set in the ratio display counter 74n. As described above, in this embodiment, the numerical information set in the stop order type counter 74m is either a stop order type number between "1" and "9" or "0." A state in which a stop order type number between "1" and "9" is not set in the stop order type counter 74m specifically refers to a state in which the value of the stop order type counter 74m is "0." Also, as described above, in this embodiment, the numerical information set in the ratio display counter 74n is either calculation result data between "0" and "100" or the initial value "255." A state in which calculation result data between "0" and "100" is not set in the ratio display counter 74n specifically refers to a state in which the ratio display counter 74n is set to "255."

A state in which a stop order type number between "1" and "9" is set in the stop order type counter 74m begins while a game is being played and ends while the game is being played. On the other hand, a state in which calculation result data for the stay ratio for the second section SC2 is set in the dual-purpose display unit 66 begins while a game is not being played and ends while the game is not being played. Furthermore, a game does not start while calculation result data for the stay ratio for the second section SC2 is set in the dual-purpose display unit 66. The period in which a stop order type number between "1" and "9" is set in the stop order type counter 74m does not overlap with the period in which calculation result data between "0" and "100" is set in the ratio display counter 74n. Therefore, the conditions for executing stop order corresponding display and the conditions for executing ratio display on the dual-purpose display unit 66 will not be met simultaneously.

In this way, when a game is being played and a stop order type number between "1" and "9" is set in the stop order type counter 74m, the dual-purpose display unit 66 prioritizes the stop order display over the award number display based on the value of the award number counter 74e. Also, when a game is not being played and calculation result data between "0" and "100" is set in the ratio display counter 74n, the ratio display prioritizes the award number display based on the value of the award number counter 74e.

Figure 24 (b) is an explanatory diagram illustrating the relationship between the value of the index value counter 74f, the value of the stop order type counter 74m, and the display content of the stop order corresponding display executed by the dual-purpose display unit 66. As already explained, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in the index value counter 74f, and if no index value IV is selected in the role selection process (Figure 18), the index value counter 74f is set to "0."

If the game state is pseudo bonus state ST4 or AT state ST5 and the number of bets is "3", and an index value IV of "1" to "9" is won in the lottery process (Figure 18) for the game role, then that index value IV of "1" to "9" is set in the stop order type counter 74m as the stop order type number. As shown in FIG. 24( b), in the dual-purpose display unit 66, when the stop order type counter 74 m is set to “1”, a stop order corresponding display corresponding to the first stop order of “left → center → right” is performed, when the stop order type counter 74 m is set to “2”, a stop order corresponding display corresponding to the second stop order of “left → right → center” is performed, when the stop order type counter 74 m is set to “3”, a stop order corresponding display corresponding to the third stop order of “center → left → right”, when the stop order type counter 74 m is set to “4”, a stop order corresponding display corresponding to the fourth stop order of “center → right → left”, and when the stop order type counter 74 m is set to “5”. When the stop order type counter 74m is set to "6", a stop order corresponding display corresponding to the fifth stop order of "right → left → center" is displayed; when the stop order type counter 74m is set to "6", a stop order corresponding display corresponding to the sixth stop order of "right → center → left" is displayed; when the stop order type counter 74m is set to "7", a stop order corresponding display corresponding to the seventh stop order of "first stop on the left" is displayed; when the stop order type counter 74m is set to "8", an eighth stop order corresponding display corresponding to the stop order of "first stop on the center" is displayed; and when the stop order type counter 74m is set to "9", a stop order corresponding display corresponding to the ninth stop order of "first stop on the right" is displayed.

When the game state is in the pseudo bonus state ST4 or the AT state ST5 and the number of bets is "3," if any of the index values "10" to "17" is selected during the lottery process (FIG. 18) for the game, or if none of the index values IV "1" to "17" is selected, the value of the stop order type counter 74m becomes "0." Furthermore, when the game state is not in the pseudo bonus state ST4 or the AT state ST5 and the number of bets is "2," the stop order type counter 74m is set to "0" regardless of the result of the lottery process (FIG. 18). As shown in FIG. 24(b), a stop order type number of "0" indicates that the stop order display is not performed on the dual-purpose display unit 66. When the value of the stop order type counter 74m is "0," the dual-purpose display unit 66 displays the number of awards based on the value of the award number counter 74e, provided that the value of the ratio display counter 74n is the initial value ("255"). The display of the number of points awarded based on the value of the number of points awarded counter 74e includes displaying a number indicating the number of points awarded when the number of points awarded counter 74e is set to "1," "2," "5," or "15," and displaying "0" when the value of the number of points awarded counter 74e is "0."

As shown in FIG. 14, the main RAM 74 is provided with a left-side dual-purpose display display area 74p and a right-side dual-purpose display display area 74q. The left-side dual-purpose display display area 74p is a storage area in which 1 byte of display data to be output to the left 7-segment display 66a of the dual-purpose display unit 66 is set, and the right-side dual-purpose display display area 74q is a storage area in which 1 byte of display data to be output to the right 7-segment display 66b of the dual-purpose display unit 66 is set.

Figure 24(c) is an explanatory diagram illustrating the configuration of the main ROM 73. As shown in Figure 24(c), the main ROM 73 stores a stop order display data table 73a for displaying stop order correspondence on the dual-purpose display unit 66, and a numeric display data table 73b for displaying ratios and award numbers on the dual-purpose display unit 66. The stop order display data table 73a contains display data for stop order correspondence display corresponding to stop order type numbers "1" through "9." When displaying stop order correspondence on the dual-purpose display unit 66, the main MPU 72 reads the stop order display data table 73a and sets display data corresponding to the stop order number set in the stop order type counter 74m in the right-side dual-purpose display display area 74q. It also sets non-display data in the left-side dual-purpose display display area 74p. As a result, the left 7-segment display 66a of the dual-purpose display unit 66 becomes non-displayed, and the right 7-segment display 66b displays a stop order corresponding display corresponding to one of the first through ninth stop orders.

The numeric display data table 73b contains display data for displaying the numbers "1" through "9" on the left 7-segment display 66a and the right 7-segment display 66b of the dual-purpose display unit 66. When the main MPU 72 displays a ratio on the dual-purpose display unit 66, it reads the numeric display data table 73b and sets the display data corresponding to the tens digit of the calculation result data set in the ratio display counter 74n in the left dual-purpose display display area 74p, and sets the display data corresponding to the ones digit of the calculation result data in the right dual-purpose display display area 74q. This results in a ratio display in which either "0," "01" through "99," or "00" is displayed on the 7-segment displays 66a and 66b of the dual-purpose display unit 66. When displaying a ratio, if the value of the ratio display counter 74n is "0," the left 7-segment display 66a is hidden and the right 7-segment display 66b lights up and displays "0." As a result, "0" is displayed on the dual-purpose display unit 66. Furthermore, when the value of the ratio display counter 74n is "100", "0" is displayed lit on the left seven-segment display 66a and the right seven-segment display 66b. As a result, "00" is displayed on the dual-purpose display unit 66. This makes it easy to distinguish between a display indicating that the stay ratio for the second section SC2 is 0% and a display indicating that the stay ratio is 100%.

When the main MPU 72 displays the number of awards on the dual-purpose display unit 66, it reads the numeric display data table 73b and sets the display data corresponding to the tens digit of the award number set in the award number counter 74e in the left dual-purpose display unit display area 74p, and sets the display data corresponding to the ones digit of the award number in the right dual-purpose display unit display area 74q. This results in the number of awards being displayed as "00", "01", "02", "05", or "15" on the 7-segment displays 66a and 66b of the dual-purpose display unit 66.

As described above, the main MPU 72 determines that the dual-purpose display unit 66 is currently displaying the stop order corresponding display based on the value of the stop order type counter 74m being one of "1" to "9," and determines that the dual-purpose display unit 66 is not currently displaying the stop order corresponding display based on the stop order type counter 74m not being set to a stop order type number between "1" and "9." In a configuration in which the dual-purpose display unit 66 displays the stop order corresponding display based on the value of the stop order type counter 74m or the number of awards displayed based on the value of the award number counter 74e during game execution, the slot machine 10 lacks a flag that enables the main MPU 72 to determine that the dual-purpose display unit 66 is currently displaying the stop order corresponding display and the number of awards displayed. Therefore, compared to a configuration in which such a flag is included, the data capacity of the main RAM 74 required to generate the state in which the dual-purpose display unit 66 is currently displaying the stop order corresponding display and the number of awards displayed during game execution can be reduced.

The main MPU 72 determines that the dual-purpose display unit 66 is currently displaying a ratio based on the ratio display counter 74n being set to a value between "0" and "100," and determines that the dual-purpose display unit 66 is not currently displaying a ratio based on the value of the ratio display counter 74n or the value of the award counter 74e when a game is not being played. In a configuration in which the dual-purpose display unit 66 displays a ratio based on the value of the ratio display counter 74n or a number of awards based on the value of the award counter 74e when a game is not being played, the slot machine 10 lacks a flag that enables the main MPU 72 to determine when the dual-purpose display unit 66 is in a state where a ratio display should be performed or a number of awards display should be performed. Therefore, compared to a configuration in which such a flag is provided, the data capacity of the main RAM 74 required to generate a state in which the dual-purpose display unit 66 is displaying a ratio or a number of awards when a game is not being played can be reduced.

The period during which the stop order type counter 74m is set to a stop order type number between "1" and "9" does not overlap with the period during which the ratio display counter 74n is set to a calculation result data between "0" and "100." Therefore, the conditions for executing the stop order corresponding display on the dual-purpose display unit 66 and the conditions for executing the ratio display are not met simultaneously. This eliminates the need for flags that enable the main MPU 72 to determine when the dual-purpose display unit 66 is in a state where the stop order corresponding display should be executed and when the ratio display should be executed. Compared to a configuration that includes such flags, this reduces the data capacity of the main RAM 74 required to create the state in which the stop order corresponding display and the ratio display are executed on the dual-purpose display unit 66.

Next, the lottery result response processing executed by the main MPU 72 will be explained with reference to the flowchart in Figure 25. The lottery result response processing is executed in step S914 of the role lottery processing (Figure 18).

In the lottery result processing, if the current gaming state is not the pseudo bonus state ST4 (step S1101: NO), it is determined whether the current gaming state is the AT state ST5 (step S1102). If the current gaming state is the pseudo bonus state ST4 (step S1101: YES) or the AT state ST5 (step S1102: YES), it is determined whether the value of the bet number setting counter 74b in the main RAM 74 is "3" (step S1103). If the value of the bet number setting counter 74b is "3" (step S1103: YES), that is, if the number of bets in the current game is "3," it is determined whether the index value IV = 1 to 9 has been selected in the role lottery processing (Figure 18) by referencing the index value counter 74f in the main RAM 74 (step S1104).

If a positive judgment is made in step S1104, the value of the index value counter 74f is set to the stop order type counter 74m in the main RAM 74 (step S1105). In step S1105, the stop order type counter 74m is set to "n" (n is an integer between "1" and "9"), causing the display content of the stop order correspondence display on the dual-purpose display unit 66 to become the nth stop order correspondence display. The processing of step S1105 is a processing to set the stop order type number of one of "1" to "9" in the stop order type counter 74m, and is also a processing to switch the display content on the dual-purpose display unit 66 from the number of awards display to the stop order correspondence display. Therefore, compared to a configuration in which, in addition to the process of step S1105 in which a stop order type number between "1" and "9" is set in the stop order type counter 74m, a separate process is set to switch the display content on the dual-purpose display unit 66 from a number of awards display based on the value of the number of awards counter 74e to a stop order corresponding display, the processing configuration for setting a stop order type number between "1" and "9" in the stop order type counter 74m and switching the display content on the dual-purpose display unit 66 from a number of awards display to a stop order corresponding display can be simplified.

As already explained, the index value IV that is selected in the winning combination lottery process (FIG. 18) is stored in the index value counter 74f. In a game in which the stop order display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 are executed, the index value IV of "1" to "9" stored in the index value counter 74f is directly set as the stop order type number in the stop order type counter 74m. Therefore, the processing configuration for setting the stop order type number in the stop order type counter 74m is simplified compared to a configuration in which the stop order type number data set in the stop order type counter 74m differs from the index value IV data that is selected in the winning combination lottery process (FIG. 18).

If a negative determination is made in step S1102, step S1103, or step S1104, the value of the stop order type counter 74m is cleared to "0" (step S1106). As a result, the current game becomes a game in which the stop order corresponding display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 are not executed.

In this way, if the gaming state is the pseudo bonus state ST4 or the AT state ST5 and the number of bets on this game is "3," and an index value IV of "n" (n is any integer from "1" to "9") is won in the lottery process for the winning combination (FIG. 18) for the game, the stop order type counter 74m is set to "n," and the display content of the stop order corresponding display on the dual-purpose display unit 66 becomes the nth stop order corresponding display. On the other hand, if any of the following conditions is not met: the gaming state is the pseudo bonus state ST4 or the AT state ST5, the number of bets on this game is "3," or an index value IV of "1" to "9" is won in the lottery process for the winning combination (FIG. 18), the value of the stop order type counter 74m is cleared to "0," and the current game becomes a game in which the stop order corresponding display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 are not executed.

If the processing of step S1105 or step S1106 is performed, the start command flag stored in the main RAM 74 is set to "1" (step S1107), and this lottery result response processing is terminated. The start command flag is a flag that enables the main MPU 72 to know that a start command should be sent to the production MPU 92. By setting the start command flag to "1" in step S1107, a common command sending process (Fig. 50) is executed in step S2709 of the command output process (Fig. 44) described below. In the common command sending process (Fig. 50), processing to send the start command is executed on the condition that the start command flag is set to "1". Details of the start command will be described later.

Next, the winning determination process executed by the main MPU 72 will be explained with reference to the flowchart in Figure 26. The winning determination process is executed in step S1015 of the reel control process (Figure 22).

In the winning determination process, the type of symbols stopped on the main line ML on each reel 32L, 32M, and 32R is first determined (step S1201). Then, it is determined whether a winning combination has been achieved (step S1202). In step S1202, the winning combination determined in the winning combination lottery process (Figure 18) is determined by referencing the first winning data area 74g, the second winning data area 74h, the first CB winning data area 74j, and the second CB winning data area 74k in the main RAM 74. Then, it is determined whether the combination of symbols stopped and displayed on the main line ML on each reel 32L, 32M, and 32R corresponds to the winning combination determined in the winning combination lottery process (Figure 18). If the combination corresponds to the winning combination, it is determined that a winning combination has been achieved. If a winning combination is achieved (step S1202: YES), the winning data setting process is executed (step S1203). In the winning data setting process, winning data corresponding to the winning combination is set in the winning data area 78 provided in the main RAM 74. As already explained, the winning data area 78 is a storage area in which one byte of data is set that enables the main MPU 72 to determine the winning combination in the current game.

If the currently achieved winning combination is a small winning combination (step S1204: YES), the number of gaming media awarded corresponding to the winning combination is set in the award number counter 74e (step S1205). In step S1205, if any of the first to ninth compensatory combinations is achieved, the award number counter 74e is set to "1." If a cherry combination is achieved, the award number counter 74e is set to "2." If a first watermelon combination or a second watermelon combination is achieved, the award number counter 74e is set to "5." If a first bell combination or a second bell combination is achieved, the award number counter 74e is set to "15." This allows the main MPU 72 to determine the number of gaming media awarded by referencing the award number counter 74e during the media awarding process in step S409 of the normal processing (FIG. 13).

When a minor winning combination is achieved in a game in which the stop order display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 are not executed, while the dual-purpose display unit 66 is displaying the number of awards as "00" based on the value ("0") of the number of awards counter 74e, the number of awards counter 74e is set to "1," "2," "5," or "15" in step S1205. As a result, the port output process (FIG. 28) is executed in step S211 of the timer interrupt process (FIG. 11), and the display content of the number of awards display on the dual-purpose display unit 66 changes from "00" to "01," "02," "05," or "15."

If the currently established winning is a replay winning (step S1204: NO, step S1206: YES), the replay winning flag in the main RAM 74 is set to "1" (step S1207). As already explained, the replay winning flag is a flag that allows the main MPU 72 to determine whether a replay winning has occurred. By setting the replay winning flag to "1" in step S1207, the main MPU 72 can determine whether any replay winnings have occurred in the currently established game by referring to the replay winning flag during the start waiting process (FIG. 15) after the current game has ended. If the currently established winning is a replay winning (step S1206: YES), or if no winnings have occurred (step S1206: NO), the process of changing the value of the award number counter 74e is not executed.

If a negative determination is made in step S1202, if the processing of step S1205 is performed, if a negative determination is made in step S1206, or if the processing of step S1207 is performed, the stop order type counter 74m is cleared to "0" (step S1208), and the winning determination process is terminated. As already explained, the dual-purpose display unit 66 performs stop order display on the condition that a stop order type number between "1" and "9" is set in the stop order type counter 74m during game execution. In a game in which the stop order display is performed in the dual-purpose display unit 66, the value of the stop order type counter 74m is cleared to "0" in step S1208, and the port output process (FIG. 28) is executed, thereby terminating the stop order display performed in the dual-purpose display unit 66 and starting the display of the number of awards based on the value of the award number counter 74e.

As already explained, when a game is being played, the main MPU 72 determines that the dual-purpose display unit 66 is currently displaying the stop order based on the value of the stop order type counter 74m, based on the value of the stop order type counter 74m being "1" to "9," and determines that the dual-purpose display unit 66 is currently displaying the number of awards based on the value of the award number counter 74e, based on the value of the stop order type counter 74m being "0." The processing of step S1208 clears the value of the stop order type counter 74m to "0," and also performs settings to switch the display content of the dual-purpose display unit 66 from the stop order based on the value of the award number counter 74e. Therefore, compared to a configuration in which, in addition to the process of clearing the value of the stop order type counter 74m to "0," a separate process is set to switch the display content on the dual-purpose display unit 66 from a stop order corresponding display to an award number display based on the value of the award number counter 74e, the processing configuration for clearing the value of the stop order type counter 74m to "0" and switching the display content on the dual-purpose display unit 66 from a stop order corresponding display to an award number display can be simplified.

As described above, if a replay win is achieved or if no win is achieved, the process of changing the value of the award number counter 74e is not executed. In these cases, the value of the award number counter 74e (specifically, "0") is maintained, the value of the stop order type counter 74m is cleared to "0" in step S1208, and the dual-purpose display unit 66 begins displaying the award number corresponding to the value of the award number counter 74e ("0") (displaying "00"). If the stop order corresponding display was being executed in the dual-purpose display unit 66, the value of the stop order type counter 74m is cleared to "0" in step S1208, thereby terminating the stop order corresponding display executed in the dual-purpose display unit 66 and beginning displaying the award number corresponding to the value of the award number counter 74e ("0") (displaying "00"). Furthermore, if the stop order corresponding display has not been performed on the dual-purpose display unit 66, that is, if the combined display unit 66 has been performing a display of the number of awards (displaying "00") corresponding to the value of the award number counter 74e ("0"), the display of "00" will continue even after the value of the stop order type counter 74m is cleared to "0" in step S1208.

As described above, the stop order display in the dual-purpose display unit 66 ends when the stop order type counter 74m is cleared to "0" during the winning determination process (Figure 26) that is executed after all reels 32L, 32M, and 32R have stopped.

In the winning determination process (FIG. 26), when a small win occurs, step S1205, in which the award number corresponding to the small win is set in the award number counter 74e, occurs before step S1208, in which the stop order type counter 74m is cleared to "0." If the stop order type counter 74m is cleared to "0" while the stop order type display is being executed on the dual-purpose display unit 66, the display content of the dual-purpose display unit 66 switches from the stop order type display to the award number display. If the stop order type counter 74m is cleared to "0" before the award number corresponding to the newly established small win is set in the award number counter 74e on the dual-purpose display unit 66, there is a risk that "0" will be displayed between the end of the stop order type display on the dual-purpose display unit 66 and the start of displaying the award number corresponding to the newly established small win. If the display content on the dual-purpose display unit 66 switches twice in a short period of time (for example, approximately 3 milliseconds) in the order of stop order display → "00" → display corresponding to the number of gaming media awarded, this could confuse the gaming parlor manager and players. In contrast, by using a processing configuration that clears the stop order type counter 74m to "0" when the number of gaming media awarded corresponding to the currently established small winning combination is set in the award number counter 74e, the display content on the dual-purpose display unit 66 can be smoothly switched from the stop order display to the award number display.

Next, the management process executed by the main MPU 72 will be described with reference to the flowchart in Figure 27. The management process is executed in step S213 of the timer interrupt process (Figure 11).

The management process first determines whether a ratio display is being performed on the dual-purpose display unit 66 (step S1301). As already explained, when a game is not being played, if the ratio display counter 74n is set to any value between "0" and "100" as the calculation result data for the stay ratio for the second section SC2, the dual-purpose display unit 66 displays the ratio. Furthermore, if the ratio display counter 74n is not set to any value between "0" and "100," the dual-purpose display unit 66 displays the number of awards based on the value of the award number counter 74e. In step S1301, if the ratio display counter 74n is set to any value between "0" and "100," it is determined that a ratio display is being performed (step S1301: YES).

If the ratio display is not being performed on the dual-purpose display unit 66 (step S1301: NO), it is determined whether a game is being performed by determining whether the in-game flag in the main RAM 74 is set to "1" (step S1302). As already explained, the in-game flag is set to "1" in step S803 of the setting process at the start of play (Figure 17(b)), and the in-game flag is cleared to "0" in step S1510 of the response process at the end of play (Figure 32).

If a game is not being executed (step S1302: NO), it is determined whether an operation to start the ratio display has been performed (step S1303). In step S1303, while operating power is being supplied to the slot machine 10 and the setting value update process in step S107 of the main processing (Figure 10) has not been executed, it is determined whether the front door 12 is open and the reset button 56 on the power supply device 54 has been pressed continuously for three seconds or more. As already explained, if the supply of operating power to the slot machine 10 is initiated while the setting key insertion hole 57 is turned ON and the reset button 56 is being pressed, the all clear process in step S106 of the main processing (Figure 10) is executed. Furthermore, during the setting value update process in step S107 of the main processing (Figure 10), the reset button 56 is operated to update the setting values of the slot machine 10. The slot machine 10 is configured to determine that an operation to start ratio display has been performed when the reset button 56 is pressed continuously for three seconds or more while operating power is being supplied and the setting value update process (step S107) is not being executed. This prevents the operation of the reset button 56 to execute the all clear process (step S106) and the operation of the reset button 56 to update the setting values in the setting value update process (step S107) from being mistakenly identified as an operation of the reset button 56 to start ratio display.

When a game is not being played (step S1302: NO) and a ratio display start operation is performed (step S1303: YES), a ratio calculation process is executed (step S1304). In the ratio calculation process, a calculation is performed to calculate the stay ratio for the second section SC2 using the total game number counter and the second section game number counter stored in the main RAM 74. The total game number counter is a counter for measuring the number of games played regardless of the game status or game section. The total game number counter consists of two bytes and can measure the number of games up to an upper limit of "65535." Furthermore, the value of the total game number counter is not cleared to "0" unless the all-clear process of step S106 is executed in the main process (Figure 10). Therefore, it is possible to measure the cumulative number of games played at the amusement hall over multiple business days. The second section game number counter is a counter that allows the main MPU 72 to grasp the cumulative number of games played in the second section SC2. The second-section game number counter is provided in the host RAM 74 separately from the continued game number counter 74r (described later). Even if the value of the continued game number counter 74r is cleared to "0" when the second section SC2 ends, the value of the second-section game number counter is not cleared to "0." Therefore, if the second section SC2 occurs multiple times with the first section SC1 in between, the total number of games played in those multiple second section SC2s can be measured using the second-section game number counter. The second-section game number counter consists of two bytes and can measure the number of games up to a maximum of "65,535." Furthermore, the value of the second-section game number counter is not cleared to "0" unless the all-clear process of step S106 is executed in the main process ( FIG. 10 ). Therefore, it is possible to measure the cumulative number of games played in the second section SC2 over multiple business days at the amusement hall. The value of the total game count counter is updated in step S1511 of the response process at the end of play (FIG. 32) described below, and the value of the second interval game count counter is updated in step S1905 of the second control process for the game interval (FIG. 36) described below. In the ratio calculation process in step S1304, a calculation is performed so that the calculation result = "(value of second interval game count counter) / "value of total game count counter" x 100". As already explained, the stay ratio for the second interval SC2 is between 0% and 100%, and the calculation result data is numerical information between "0" and "100".

Then, the calculation result data from the ratio calculation process (step S1304) is set to the ratio display counter 74n in the main RAM 74 (step S1305), and this management process ends. As already explained, when a game is not being executed, the main MPU 72 determines that the dual-purpose display unit 66 is currently displaying the ratio based on the value of the award number counter 74e, based on the fact that the ratio display counter 74n is not set to a value between "0" and "100." When a game is not being executed, the dual-purpose display unit 66 ends displaying the award number based on the value of the award number counter 74e by setting the ratio display counter 74n to a value between "0" and "100" in step S1305, and the dual-purpose display unit 66 starts displaying the ratio. The processing of step S1305 is a processing for storing calculation result data in the ratio display counter 74n, and a processing for making settings to switch the display content on the dual-purpose display unit 66 from a number of awards display based on the value of the number of awards counter 74e to a ratio display. Therefore, compared to a configuration in which, in addition to the processing for storing calculation result data in the ratio display counter 74n, a processing for making settings to switch the display content on the dual-purpose display unit 66 from a number of awards display based on the value of the number of awards counter 74e to a ratio display is set as a separate processing, the processing configuration for storing calculation result data in the ratio display counter 74n and making settings to switch the display content on the dual-purpose display unit 66 from a number of awards display to a ratio display can be simplified.

If the ratio display is being performed on the dual-purpose display unit 66 (step S1301: YES), it is determined whether an operation to end the ratio display has been performed (step S1306). Specifically, it determines whether an ON signal has been received from any of the start detection sensor 41a, stop detection sensors 42a-44a, inserted medal detection sensor 45a, inserted credit detection sensor 47a, and settlement detection sensor 51a. If it determines that an ON signal has been received from any of the detection sensors 41a-45a, 47a, it determines that an operation to end the ratio display has been performed. In this case, a positive determination is made in step S1306 regardless of whether each ON signal occurred during the valid period. In other words, a positive determination is made in step S1306 regardless of whether the reception of an ON signal from the start detection sensor 41a triggers the start of rotation of reels 32L, 32M, and 32R. Furthermore, a positive determination is made in step S1306 regardless of whether the receipt of an ON signal from the stop detection sensors 42a-44a triggers the rotation of reels 32L, 32M, and 32R to stop. Also, a positive determination is made in step S1306 regardless of whether the receipt of an ON signal from the inserted medal detection sensor 45a triggers a bet setting or credit increase. Also, a positive determination is made in step S1306 regardless of whether the receipt of an ON signal from the credit insertion detection sensor 47a triggers a bet setting. Also, a positive determination is made in step S1306 regardless of whether the receipt of an ON signal from the settlement detection sensor 51a triggers the settlement of credited virtual medals.

If an operation to end the ratio display is performed (step S1306: YES), the ratio display counter 74n is set to its initial value of "255" (step S1307), and this management process is terminated. By setting the initial value to the ratio display counter 74n in step S1307, the ratio display counter 74n is assumed to be in a state in which no calculation result data between "0" and "100" is set, and the display content on the dual-purpose display unit 66 can be switched from a ratio display to a number of awards display. The process of step S1307 is a process for setting the initial value to the ratio display counter 74n, as well as a process for switching the display content on the dual-purpose display unit 66 from a ratio display to a number of awards display based on the value of the number of awards counter 74e. Therefore, compared to a configuration in which, in addition to the process of step S1307 in which an initial value is set in the ratio display counter 74n, a separate process is set to switch the display content on the dual-purpose display unit 66 from ratio display to number of awards display, the process configuration for setting an initial value in the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from ratio display to number of awards display can be simplified.

If a negative judgment is made in step S1306, this management process is terminated. A new game cannot be started while the ratio display is being performed on the dual-purpose display unit 66. Therefore, while the ratio display is being performed, the calculation result data stored in the ratio display counter 74n and the stay ratio for the second section SC2 displayed on the dual-purpose display unit 66 are not updated.

In this way, the calculation result data for the stay ratio for the second section SC2 is set in the ratio display counter 74n when the ratio display start operation is performed while the game is not being executed. If the calculation to calculate the stay ratio for the second section SC2 were performed even when the ratio display is not being executed on the dual-purpose display unit 66 and the calculation result data were stored in the main RAM 74, it would be necessary to provide a counter in the main RAM 74 to store the calculation result data in addition to the ratio display counter 74n. In contrast, by configuring the calculation result data to be set in the ratio display counter 74n only during the period when the ratio display is being executed on the dual-purpose display unit 66, the data capacity of the memory area provided in the main RAM 74 for storing the calculation result data can be reduced.

Next, the port output processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 28. The port output processing is executed in step S211 of the timer interrupt processing (Figure 11).

In the port output process, it is first determined whether a stop order type number between "1" and "9" is set in the stop order type counter 74m of the main RAM 74 (step S1401). As already explained, if the index value IV of "n" (where "n" is an integer between "1" and "9") is won in the lottery process for a game in which the gaming state is the pseudo bonus state ST4 or the AT state ST5 and the number of bets on the current game is "3" (Figure 18), the stop order type counter 74m is set to "n." On the other hand, if the conditions that the gaming state is the pseudo bonus state ST4 or the AT state ST5, the number of bets on the current game is "3," or the index value IV of "1" to "9" is won in the lottery process for a game in which the index value IV is "1" to "9" (Figure 18) are not met, the stop order type counter 74m is set to "0." If a stop order type number between "1" and "9" is set in the stop order type counter 74m (step S1401: YES), the stop order corresponding display data table 73a ( FIG. 24(c) ) stored in the main ROM 73 is read (step S1402). Then, by referencing the stop order corresponding display data table 73a read in step S1402, display data corresponding to the value of the stop order type counter 74m is set in the right-side dual-purpose display display area 74q of the main RAM 74, and non-display data is set in the left-side dual-purpose display display area 74p of the main RAM 74 (step S1403). As a result, the process of step S1409, described below, is executed, and the stop order corresponding display is performed on the dual-purpose display unit 66.

If the value of the stop order type counter 74m is not between "1" and "9" (step S1401: NO), it is determined whether any calculation result data between "0" and "100" is set in the ratio display counter 74n in the main RAM 74 (step S1404). If any calculation result data between "0" and "100" is set in the ratio display counter 74n (step S1404: YES), the numeric display data table 73b (Figure 24(c)) stored in the main ROM 73 is read (step S1405). Then, the numeric display data table 73b read in step S1405 is referenced and the display data corresponding to the value of the ratio display counter 74n is set in the left-side dual-use display area 74p and the right-side dual-use display area 74q (step S1406). In step S1406, if the value of the ratio display counter 74n is "0," non-display data is set in the left-side shared display display area 74p, and display data corresponding to "0" is set in the right-side shared display display area 74q. In step S1406, if the value of the ratio display counter 74n is "1" to "9," display data corresponding to "0" is set in the left-side shared display display area 74p, and display data corresponding to the digit in the units digit ("1" to "9") is set in the right-side shared display display area 74q. In step S1406, if the value of the ratio display counter 74n is "10" to "99," display data corresponding to the digit in the tens digit ("1" to "9") is set in the left-side shared display display area 74p, and display data corresponding to the digit in the units digit ("1" to "9") is set in the right-side shared display display area 74q. In step S1406, if the value of the ratio display counter 74n is "100", display data corresponding to "0" is set in the left-side dual-purpose display display area 74p and the right-side dual-purpose display display area 74q. This causes the processing of step S1409, described below, to be executed, resulting in the ratio display on the dual-purpose display unit 66.

If a stop order type number between "1" and "9" is not set in the stop order type counter 74m (step S1401: NO) and calculation result data between "0" and "100" is not set in the ratio display counter 74n (step S1404: NO), processing is executed to display the number of awards on the dual-purpose display unit 66 (processing of steps S1407 and S1408). Specifically, as in step S1405, the numeric display data table 73b stored in the main ROM 73 is first read (step S1407). Then, the numeric display data table 73b read in step S1407 is referenced and display data corresponding to the value of the award number counter 74e is set in the left-side dual-purpose display display area 74p and the right-side dual-purpose display display area 74q (step S1408). This executes the processing of step S1409, described below, thereby displaying the number of awards on the dual-purpose display unit 66.

When step S1403, step S1406, or step S1408 is performed, the data (display data or non-display data) set in the left-side shared display area 74p and the right-side shared display area 74q is output to the shared display unit 66 (step S1409). As a result, if non-display data is set in the left-side shared display area 74p and display data for stop order corresponding display is set in the right-side shared display area 74q, stop order corresponding display is executed in the shared display unit 66. Furthermore, if non-display data or display data for ratio display is set in the left-side shared display area 74p and display data for ratio display is set in the right-side shared display area 74q, ratio display is executed in the shared display unit 66. Furthermore, if display data for award number display is set in the shared display area 74p, 74q, award number display is executed in the shared display unit 66.

Then, the display control process for the credit display unit 65 is executed (step S1410), which controls the display of the credit display unit 65, and other port output process is executed (step S1411), and this port output process ends. In the other port output process in step S1411, data corresponding to the I/O device is output from the input/output port.

Next, we will explain how the stop order display and the number of awards display are executed on the dual-purpose display unit 66, with reference to the time chart in Figure 29. FIG. 29(a) shows the execution period of the stop order display on the combined display unit 66, FIG. 29(b) shows the execution period of the award number display on the combined display unit 66, FIG. 29(c) shows the period during which a stop order type number between "1" and "9" is set in the stop order type counter 74m, FIG. 29(d) shows the period during which data equal to or greater than "1" is set in the award number counter 74e, FIG. 29(e) shows the timing when a bet operation or the first medal insertion is performed when a game is not being executed, FIG. 29(f) shows the timing when a game starts, FIG. 29(g) shows the timing when operation of the stop buttons 42 to 44 is enabled, FIG. 29(h) shows the timing when the establishment of any small winning combination is identified in the winning determination process (FIG. 26) (the timing when a positive determination is made in step S1204 and the process of step S1205 is executed), and FIG. 29(i) shows the timing when the port output process (FIG. 28) is executed.

When a bet operation or the first medal insertion is performed at timing t1, while the dual-purpose display unit 66 is displaying the number of awards corresponding to the value of the award number counter 74e, as shown in FIG. 29(e), the value of the award number counter 74e is cleared to "0" at timing t1, as shown in FIG. 29(d). Then, when a port output process is executed at timing t2, as shown in FIG. 29(i), the dual-purpose display unit 66 displays the number of awards as "00", as shown in FIG. 29(b). If the number of awards displayed at timing t1 was already "00", the number of awards displayed as "00" will continue. Furthermore, if the number of awards displayed at timing t1 was "01", "02", "05", or "15", the number of awards displayed will switch to "00".

Then, at timing t3, the start lever 41 is operated, and the game begins as shown in Figure 29(f). Then, at timing t4, a stop order type number from "1" to "9" is set in the stop order type counter 74m as shown in Figure 29(c). Then, at timing t5, a port output process is executed as shown in Figure 29(i), and the display content on the combined display unit 66 switches from the number of awards display to the stop order corresponding display as shown in Figures 29(a) and 29(b). Timing t5 occurs before timing t6, when operation of the stop buttons 42 to 44 is enabled. The stop order corresponding display on the combined display unit 66 begins before operation of the stop buttons 42 to 44 is enabled. Then, at timing t6, operation of the stop buttons 42 to 44 is enabled as shown in Figure 29(g).

Then, at timing t7, the winning determination process (FIG. 26) determines whether a small win has been achieved, as shown in FIG. 29(h), and the number of gaming media awarded corresponding to the newly achieved small win ("1," "2," "5," or "15") is set in the award number counter 74e. Then, at timing t8, the value of the stop order type counter 74m is cleared to "0," as shown in FIG. 29(c). Then, at timing t9, the port output process is executed as shown in FIG. 29(i), and the display content on the dual-purpose display unit 66 switches from the stop order corresponding display to the award number display, as shown in FIGS. 29(a) and 29(b).

As already explained, in the winning determination process (FIG. 26), when a small win occurs, step S1205, which sets the number of gaming media awarded corresponding to the small win to the award number counter 74e, is executed at time t7. This time occurs before step S1208, which clears the stop order type counter 74m to "0" (time t8). As already explained, when the stop order type counter 74m is cleared to "0" while the stop order corresponding display is being executed on the dual-purpose display unit 66, the display content of the dual-purpose display unit 66 switches from the stop order corresponding display to the award number display. If the stop order type counter 74m is cleared to "0" before setting the number of gaming media awarded corresponding to the currently established small win to the award number counter 74e, there is a risk that "0" will be displayed on the dual-purpose display unit 66 between the end of the stop order corresponding display and the start of displaying the number of gaming media awarded corresponding to the currently established small win. If the display content on the dual-purpose display unit 66 switches twice in a short period of time (for example, approximately 3 milliseconds) in the order of stop order display → "00" → display corresponding to the number of gaming media awarded, this could confuse the gaming parlor manager and players. In contrast, by using a processing configuration that clears the stop order type counter 74m to "0" when the number of gaming media awarded corresponding to the currently established small winning combination is set in the award number counter 74e, the display content on the dual-purpose display unit 66 can be smoothly switched from the stop order display to the award number display.

Next, the manner in which the ratio display and the number of points awarded are displayed on the dual-purpose display unit 66 will be described with reference to the time chart in Figure 30. Figure 30(a) shows the period during which the ratio display is performed on the dual-purpose display unit 66, Figure 30(b) shows the period during which the number of points awarded is displayed on the dual-purpose display unit 66, Figure 30(c) shows the period during which calculation result data between "0" and "100" is set in the ratio display counter 74n, Figure 30(d) shows the timing when the operation to start the ratio display is performed, Figure 30(e) shows the timing when the operation to end the ratio display is performed, and Figure 30(f) shows the timing when the port output process (Figure 28) is executed.

When the operation to start the ratio display is performed at time t1, when the game is not being played and the dual-purpose display unit 66 is displaying the number of awards based on the value of the award number counter 74e, as shown in Figure 30(d), a calculation is performed to calculate the stay ratio for the second section SC2, as shown in Figure 30(c), and the calculation result data of one of "0" to "100" is set in the ratio display counter 74n. Then, at time t2, a port output process is executed as shown in Figure 30(f), and the display content on the dual-purpose display unit 66 switches from the number of awards display to the ratio display as shown in Figures 30(a) and (b).

After that, when the ratio display is ended at timing t3 as shown in Figure 30(e), the ratio display counter 74n is set to its initial value of "255" as shown in Figure 30(c). Then, at timing t4, the port output process is executed as shown in Figure 30(f), and the display content on the dual-purpose display unit 66 switches from the ratio display to the number of points awarded as shown in Figures 30(a) and (b).

As already explained, when a game is not being played, the dual-purpose display unit 66 displays a ratio if the ratio display counter 74n is set to any calculation result data between "0" and "100," and displays the number of awards if the ratio display counter 74n is set to its initial value of "255." Therefore, when a game is not being played and the dual-purpose display unit 66 is displaying the number of awards, the display content on the dual-purpose display unit 66 can be switched from the number of awards display to a ratio display by setting the ratio display counter 74n to any calculation result data between "0" and "100." Furthermore, when the dual-purpose display unit 66 is displaying a ratio, the display content on the dual-purpose display unit 66 can be switched from a ratio display to a number of awards display by setting the ratio display counter 74n to its initial value of "255." This simplifies the processing configuration for switching the display content on the dual-purpose display unit 66 from the number of awards display to a ratio display and from a ratio display to a number of awards display.

As described above, the main MPU 72 determines that the dual-purpose display unit 66 is currently displaying the stop order corresponding display based on the value of the stop order type counter 74m being one of "1" to "9," and determines that the dual-purpose display unit 66 is not currently displaying the stop order corresponding display based on the stop order type counter 74m not being set to a stop order type number between "1" and "9." In a configuration in which the dual-purpose display unit 66 displays the stop order corresponding display based on the value of the stop order type counter 74m or the number of awards displayed based on the value of the award number counter 74e during game execution, the slot machine 10 lacks a flag that enables the main MPU 72 to determine that the dual-purpose display unit 66 is currently displaying the stop order corresponding display and the number of awards displayed. Therefore, compared to a configuration in which such a flag is included, the data capacity of the main RAM 74 required to generate the state in which the dual-purpose display unit 66 is currently displaying the stop order corresponding display and the number of awards displayed during game execution can be reduced.

In a game in which the stop order display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 are executed, any of the index values IV "1" to "9" that is selected in the winning combination lottery process (FIG. 18) is stored in the index value counter 74f, and any of the index values IV "1" to "9" stored in the index value counter 74f is set directly as the stop order type number in the stop order type counter 74m. Therefore, the processing configuration for setting the stop order type number in the stop order type counter 74m is simplified compared to a configuration in which the stop order type number data set in the stop order type counter 74m differs from the index value IV data that is selected in the winning combination lottery process (FIG. 18).

In the winning determination process (FIG. 26), when a small win occurs, step S1205, in which the award number corresponding to the small win is set in the award number counter 74e, occurs before step S1208, in which the stop order type counter 74m is cleared to "0." If the stop order type counter 74m is cleared to "0" while the stop order type display is being executed on the dual-purpose display unit 66, the display content of the dual-purpose display unit 66 switches from the stop order type display to the award number display. If the stop order type counter 74m is cleared to "0" before the award number corresponding to the newly established small win is set in the award number counter 74e on the dual-purpose display unit 66, there is a risk that "0" will be displayed between the end of the stop order type display on the dual-purpose display unit 66 and the start of displaying the award number corresponding to the newly established small win. If the display content on the dual-purpose display unit 66 switches twice in a short period of time (for example, approximately 3 milliseconds) in the order of stop order display → "00" → display corresponding to the number of gaming media awarded, this could confuse the gaming parlor manager and players. In contrast, by using a processing configuration that clears the stop order type counter 74m to "0" when the number of gaming media awarded corresponding to the currently established small winning combination is set in the award number counter 74e, the display content on the dual-purpose display unit 66 can be smoothly switched from the stop order display to the award number display.

When a game is being played and the dual-purpose display unit 66 is displaying the number of awards based on the value of the award number counter 74e, the display content on the dual-purpose display unit 66 can be switched from the number of awards display to the stop order corresponding display by performing a process of setting the stop order type counter 74m to one of "1" to "9" (the process of step S1105 in the lottery result response process (FIG. 25)). Therefore, compared to a configuration in which, in addition to the process of setting the stop order type counter 74m to one of "1" to "9", a separate process is set to switch the display content on the dual-purpose display unit 66 from the number of awards display based on the value of the award number counter 74e to the stop order corresponding display, the processing configuration for setting the stop order type counter 74m to one of "1" to "9" and switching the display content on the dual-purpose display unit 66 from the number of awards display to the stop order corresponding display can be simplified.

When a game is being played and the stop order display is being performed on the dual-purpose display unit 66, the value of the stop order type counter 74m is cleared to "0" (the processing of step S1208 in the winning determination processing (FIG. 26)), thereby switching the display content on the dual-purpose display unit 66 from a stop order corresponding display to a number of awards based on the value of the award number counter 74e. Therefore, compared to a configuration in which, in addition to the processing of clearing the value of the stop order type counter 74m to "0," a separate processing is set to switch the display content on the dual-purpose display unit 66 from a stop order corresponding display to a number of awards based on the value of the award number counter 74e, the processing configuration for clearing the value of the stop order type counter 74m to "0" and switching the display content on the dual-purpose display unit 66 from a stop order corresponding display to a number of awards can be simplified.

The main MPU 72 determines that the dual-purpose display unit 66 is currently displaying a ratio based on the ratio counter 74n being set to a value between "0" and "100," and determines that the dual-purpose display unit 66 is not currently displaying a ratio based on the value of the ratio counter 74n or the value of the award counter 74e when a game is not being played. In a configuration in which the dual-purpose display unit 66 displays a ratio based on the value of the ratio counter 74n or the number of awards based on the value of the award counter 74e when a game is not being played, the slot machine 10 lacks a flag that enables the main MPU 72 to determine when the dual-purpose display unit 66 should display a ratio or the number of awards. Therefore, compared to a configuration in which such a flag is included, the data capacity of the main RAM 74 required to display a ratio or the number of awards when a game is not being played can be reduced.

When a game is not being played and the dual-purpose display unit 66 is displaying the number of awards based on the value of the award number counter 74e, the display content on the dual-purpose display unit 66 can be switched from displaying the number of awards to displaying the ratio by executing a process (step S1305 in the management process (FIG. 27)) that sets calculation result data between "0" and "100" in the ratio display counter 74n. Therefore, compared to a configuration in which, in addition to the process of storing calculation result data in the ratio display counter 74n, a separate process is set to switch the display content on the dual-purpose display unit 66 from displaying the number of awards based on the value of the award number counter 74e to displaying the ratio, the processing configuration for storing calculation result data in the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from displaying the number of awards to displaying the ratio can be simplified.

When a game is not being played and a ratio display is being performed on the dual-purpose display unit 66, the display content on the dual-purpose display unit 66 can be switched from a ratio display to a number of awards based on the value of the number of awards counter 74e by executing a process to set the ratio display counter 74n to an initial value of "255" (the process of step S1307 in the management process (FIG. 27)). Therefore, compared to a configuration in which, in addition to the process of setting an initial value to the ratio display counter 74n, a separate process is set to switch the display content on the dual-purpose display unit 66 from a ratio display to a number of awards display, the process configuration for setting an initial value to the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from a ratio display to a number of awards display can be simplified.

Calculation result data for the stay ratio for the second section SC2 is set in the ratio display counter 74n when an operation to start the ratio display is performed while the game is not being executed. If the calculation to calculate the stay ratio for the second section SC2 were performed even when the ratio display is not being executed on the dual-purpose display unit 66 and the calculation result data were stored in the main RAM 74, it would be necessary to provide a counter in the main RAM 74 to store the calculation result data in addition to the ratio display counter 74n. In contrast, by configuring the calculation result data to be set in the ratio display counter 74n only during the period when the ratio display is being executed on the dual-purpose display unit 66, the data capacity of the memory area provided in the main RAM 74 for storing the calculation result data can be reduced.

The period during which the stop order type counter 74m is set to a stop order type number between "1" and "9" does not overlap with the period during which the ratio display counter 74n is set to a calculation result data between "0" and "100." Therefore, the conditions for executing the stop order corresponding display on the dual-purpose display unit 66 and the conditions for executing the ratio display are not met simultaneously. This eliminates the need for flags that enable the main MPU 72 to determine when the dual-purpose display unit 66 is in a state where the stop order corresponding display should be executed and when the ratio display should be executed. Compared to a configuration that includes such flags, this reduces the data capacity of the main RAM 74 required to create the state in which the stop order corresponding display and the ratio display are executed on the dual-purpose display unit 66.

Next, before explaining the response process (Figure 32) executed by the main MPU 72 when play ends, we will explain the play area area 76 and play status area 77 (see Figure 14) provided in the main RAM 74. Figure 31(a) is an explanatory diagram for explaining the data structure of the play area area 76, and Figure 31(b) is an explanatory diagram for explaining the data structure of the play status area 77. The data in the play area area 76 and play status area 77 is set in the start command and end command. Details of the start command and end command will be provided later.

As shown in FIG. 31(a), the game zone area 76 is a memory area consisting of one byte. The 0th bit of the game zone area 76 is set to a second zone flag 76a, the 1st bit is set to a first ending flag 76b, and the 2nd bit is set to a second ending flag 76c. Furthermore, the 3rd to 7th bits of the game zone area 76 are unused bits. The second zone flag 76a is a flag used by the main MPU 72 to determine whether the game zone is the second zone SC2. The second zone flag 76a is set to "1" when the game zone transitions to the second zone SC2, and is cleared to "0" when the second zone SC2 ends. The first ending flag 76b is a flag used by the main MPU 72 to determine whether the number of games played in the second zone SC2, measured using the continued game counter 74r described below, is likely to reach the upper limit number of games ("1500"). The second ending flag 76c is a flag that allows the main MPU 72 to determine whether the limited total net increase in the number of gaming media measured using the total acquisition counter 74s (described below) is likely to reach the upper limit of the net increase.

As shown in Figure 31 (b), the game status area 77 is a memory area consisting of 1 byte, and the 0th bit of the game status area 77 is set to the first CB status flag 77a, the 1st bit is set to the second CB status flag 77b, the 2nd bit is set to the pseudo bonus status flag 77c, the 3rd bit is set to the AT status flag 77d, the 4th bit is set to the end preparation status flag 77e, and the 5th bit is set to the AT transition confirmation flag 77f. In addition, the 6th to 7th bits of the game status area 77 are unused bits. The first CB state flag 77a is a flag that enables the main MPU 72 to recognize that the game is in the first CB state ST2, the second CB state flag 77b is a flag that enables the main MPU 72 to recognize that the game is in the second CB state ST3, the pseudo bonus state flag 77c is a flag that enables the main MPU 72 to recognize that the game is in the pseudo bonus state ST4, the AT state flag 77d is a flag that enables the main MPU 72 to recognize that the game is in the AT state ST5, and the end preparation state flag 77e is a flag that enables the main MPU 72 to recognize that the game is in the end preparation state ST6. When the values of the first CB state flag 77a, the second CB state flag 77b, the pseudo bonus state flag 77c, the AT state flag 77d, and the end preparation state flag 77e are "0," the main MPU 72 recognizes that the game is in the normal game state ST1. The AT transition confirmation flag 77f is a flag that allows the main MPU 72 to determine whether the conditions for transitioning to the AT state ST5 have already been met in the pseudo bonus state ST4.

Next, the response process at the end of play, which is executed in step S410 of the normal processing (FIG. 13), will be explained with reference to the flowchart in FIG. 32. Note that, because the processing of step S410 in the normal processing (FIG. 13) is executed after the reel control processing (step S408), the response process at the end of play is executed after all rotations of reels 32L, 32M, and 32R have stopped in one game.

In the response process at the end of game play, first, CB processing is executed to control the transition to the first CB state ST2, control progress in the first CB state ST2, control the transition to the second CB state ST3, and control progress in the second CB state ST3 (step S1501). CB processing will be described in detail later. Then, if the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S1502: NO), a jump is made to a program address where a CALL command is set that calls processing corresponding to the current game state (step S1503). Specifically, if the game state is the normal game state ST1, a jump is made to a program address where a CALL command is set to call normal processing (step S1504), and the normal processing (step S1504) is executed. If the gaming state is pseudo bonus state ST4, a jump is made to a program address where a CALL command for calling pseudo bonus processing (step S1505) is set, and the pseudo bonus processing (step S1505) is executed. If the gaming state is AT state ST5, a jump is made to a program address where a CALL command for calling AT processing (step S1506) is set, and the AT processing (step S1506) is executed. The processing contents of steps S1504 to S1506 will be explained in detail later.

If a positive judgment is made in step S1502, the process proceeds to step S1507. The process also proceeds to step S1507 when the normal processing called in step S1504, the pseudo-bonus processing called in step S1505, or the AT processing called in step S1506 is terminated and the process returns to the end-of-game response processing (Figure 32). In step S1507, the second control processing of the game area is executed. Details of the second control processing of the game area (step S1507) will be described later.

Then, the end command flag stored in the main RAM 74 is set to "1" (step S1508). The end command flag is a flag that allows the main MPU 72 to know that an end command should be sent to the production MPU 92. By setting the end command flag to "1" in step S1508, a common command sending process (Fig. 50) is executed in step S2709 of the command output process (Fig. 44) described below. In the common command sending process (Fig. 50), processing is executed to send the end command based on the fact that the start command flag in the main RAM 74 is not set to "1". Details of the end command will be described later.

Then, the value of the bet number setting counter 74b in the main RAM 74 is cleared to "0" (step S1509), and the game in progress flag in the main RAM 74 is cleared to "0" (step S1510). Then, the value of the total number of games counter in the main RAM 74 is incremented by 1 (step S1511), and the response process at the end of this game is terminated. As already explained, the total number of games counter is a counter for measuring the number of games played regardless of the game status or game period. As already explained, the total number of games counter is a counter referenced in the ratio calculation process in step S1304 of the management process (Figure 27). By updating the total number of games counter in step S1511, the display content of the ratio display can be made accurate when the ratio display is started on the dual-purpose display unit 66.

If the current gaming state is the first CB state ST2 or the second CB state ST3, a positive determination is made in step S1502, and the normal processing in step S1504, the pseudo bonus processing in step S1505, and the AT processing in step S1506 are not executed. Therefore, if the first CB state ST2 or the second CB state ST3 is selected, the processing for progressing to the normal gaming state ST1, the processing for progressing to the pseudo bonus state ST4, and the processing for progressing to the AT state ST5 are not executed. On the other hand, even if the current gaming state is the first CB state ST2 or the second CB state ST3, the processing of steps S1507 to S1511 is executed. Therefore, even if the current gaming state is the first CB state ST2 or the second CB state ST3, the processing for progressing through the second section SC2 is executed, and the processing for sending an end command to the presentation-side MPU 92 is also executed.

Figure 33 is a flowchart showing the CB processing executed by the main MPU 72. The CB processing is executed in step S1501 of the response processing at the end of play (Figure 32). As already explained, the response processing at the end of play (Figure 32) is executed after all rotations of reels 32L, 32M, and 32R have stopped in one game, so the CB processing is also executed after all rotations of reels 32L, 32M, and 32R have stopped in one game.

The CB processing first determines whether the current game state is in either the first CB state ST2 or the second CB state ST3 by determining whether either the first CB state flag 77a or the second CB state flag 77b provided in the game state area 77 of the main RAM 74 is set to "1" (step S1601). As already explained, the first CB state flag 77a is a flag used by the main MPU 72 to determine whether the game state is in the first CB state ST2, and the second CB state flag 77b is a flag used by the main MPU 72 to determine whether the game state is in the second CB state ST3.

If a negative judgment is made in step S1601, it is determined whether a first CB win has been achieved in this game (step S1602). That is, it is determined whether a symbol combination corresponding to a first CB win has stopped on the main line ML when first CB win data is stored in the first CB win data area 74j of the main RAM 74. If a first CB win has been achieved (step S1602: YES), the first CB status flag 77a in the game status area 77 of the main RAM 74 is set to "1" (step S1603). This changes the game status to the first CB status ST2. In the first CB status ST2, as already explained, steps S701 to S703 of the bet status management process (Figure 17(a)) are executed, and the game is played only when "3" gaming media has been bet.

Then, the first CB winning data stored in the first CB winning data area 74j in the main RAM 74 is cleared (step S1604), and this CB processing is terminated. As already explained, the data in the game status area 77 is set to the end command sent to the presentation side MPU 92. The presentation side MPU 92 determines whether or not the transition to the first CB state ST2 has occurred based on the data in the first CB state flag 77a included in the data in the game status area 77 set in the received end command.

If a negative judgment is made in step S1602, it is determined whether a second CB win has been achieved in this game (step S1605). That is, it is determined whether a symbol combination corresponding to a second CB win has stopped on the main line ML when second CB win data is stored in the second CB win data area 74k of the main RAM 74. If a second CB win has been achieved (step S1605: YES), the second CB status flag 77b in the game status area 77 of the main RAM 74 is set to "1" (step S1606). This changes the game status to the second CB status ST3. In the second CB status ST3, as already explained, steps S603 and S609 of the bet response processing (FIG. 16) and steps S703 and S704 of the bet status management processing (FIG. 17(a)) are executed, and the game is executed only when "2" gaming media have been bet.

Then, the second CB winning data stored in the second CB winning data area 74k of the main RAM 74 is cleared (step S1607), and this CB processing is terminated. As already explained, the data in the game status area 77 is set in the end command sent to the presentation side MPU 92. The presentation side MPU 92 determines whether or not the game has transitioned to the second CB status ST3 based on the data in the second CB status flag 77b included in the data in the game status area 77 set in the received end command.

If a positive judgment is made in step S1601, it is determined whether a first bell win has occurred in this game (step S1608). If a first bell win has occurred (step S1608: YES), the value of the total award counter stored in the main RAM 74 is incremented by 1 (step S1609). The total award counter is a counter used by the main MPU 72 to determine the total number of gaming media awarded in the first CB state ST2 or the second CB state ST3, and is cleared to "0" when the first CB state ST2 or the second CB state ST3 is started.

If the value of the total award counter after adding 1 reaches "30," which is the termination reference number for the first CB state ST2 and the second CB state ST3 (step S1610: YES), the CB state flags 77a and 77b corresponding to the current CB states ST2 and ST3 are cleared to "0" (step S1611), and this CB processing ends. As already explained, the data in the game state area 77 is set in the termination command sent to the presentation-side MPU 92. The presentation-side MPU 92 determines whether the CB states ST2 and ST3 have ended based on the data of the first CB state flag 77a and the second CB state flag 77b included in the data in the game state area 77 set in the received termination command.

<About the second section SC2>
Next, the second section SC2 will be described. First, the first control process of the game section executed by the main MPU 72 will be described with reference to the flowchart in Figure 34. The first control process of the game section is executed in step S913, which is a process executed after the winning/losing determination of the winning combination is completed in the winning combination lottery process (Figure 18).

The first control process for the gaming area first determines whether the second area flag 76a in the gaming area area 76 of the main RAM 74 is set to "1" (step S1701). As already explained, the second area flag 76a is a flag that the main MPU 72 uses to determine whether the gaming area is the second area SC2. If the second area flag 76a is set to "1" (step S1701: YES), the processing from step S1702 onwards is not executed. As a result, if the gaming area is the second area SC2, the direct hit lottery process of step S1706 and the release game number lottery process of step S1710 are not executed.

If the second interval flag 76a is not set to "1" (step S1701: NO), it is determined whether the current game state is the first CB state ST2 or the second CB state ST3 (step S1702). As already explained, the main MPU 72 can determine that the game is in the first CB state ST2 when the first CB state flag 77a in the game state area 77 is set to "1," and can determine that the game is in the second CB state ST3 when the second CB state flag 77b is set to "1." If the current game state is the first CB state ST2 or the second CB state ST3 (step S1702: YES), the processing from step S1703 onwards is not executed. As a result, even if the first section SC1 is selected, if the first CB state ST2 or the second CB state ST3 is selected, the process for setting the second section SC2 in step S1705, the direct hit lottery process in step S1706, and the release game number lottery process in step S1710 will not be executed.

If the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S1702: NO), the value of the bet number setting counter 74b in the main RAM 74 is determined to be "3," thereby determining whether the number of bets for the current game is "3" (step S1703). If the number of bets for the current game is "2" (step S1703: NO), the processing from step S1704 onwards is not executed. As a result, in a game where the number of bets is "2" even if it is the first section SC1, the processing for setting the second section SC2 in step S1705, the direct hit lottery processing in step S1706, and the release game number lottery processing in step S1710 are not executed.

If the number of bets on the current game is "3" (step S1703: YES), it is determined whether any index value IV has been won in the current role lottery process (Figure 18) (step S1704). In step S1704, a positive determination is made if any index value IV between "1" and "17" is set in the index value counter 74f of the main RAM 74. If the current role lottery process (Figure 18) is a miss (step S1704: NO), the processes from step S1705 onwards are not executed. As a result, even if the first section is SC1, if the role lottery process (Figure 18) is a miss, the process for setting the second section SC2 in step S1705, the direct hit lottery process in step S1706, and the number of games to be released lottery process in step S1710 are not executed.

If any index value IV is selected in the current role lottery process (Figure 18) (step S1704: YES), the second section flag 76a in the game section area 76 of the main RAM 74 is set to "1", and the continued game number counter 74r (see Figure 14) and total win number counter 74s (see Figure 14) provided in the main RAM 74 are both cleared to "0" (step S1705). Setting the second section flag 76a to "1" results in the second section SC2.

The continued game number counter 74r is a counter that allows the main MPU 72 to determine the number of games played from the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between. If the value of the continued game number counter 74r reaches a value corresponding to the upper limit number of games (specifically, 1,500 games) in the second section SC2, the second section SC2 ends with the game that was reached, even if the pseudo-bonus state ST4 or AT state ST5 is in progress, and the game transitions to the first section SC1 and normal game state ST1. The continued game number counter 74r consists of 2 bytes.

The total acquisition counter 74s is a counter that allows the main MPU 72 to determine the limited total net increase in game media from the start of the second section SC2 when the second section SC2 continues without the first section SC1 in between. As already explained, the limited total net increase in game media is the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined reference value, and the difference is calculated by subtracting the total number of game media consumed to play games while the second section SC2 is continuing (0 when no game media is being played) from the total number of game media awarded through games played while the second section SC2 is continuing (0 when no game media is being awarded). If the value of the total winnings counter 74s in the second section SC2 reaches a value corresponding to the upper limit of net increase in coins (specifically, 2,400 coins), even if the game is in the middle of the pseudo-bonus state ST4 or AT state ST5, the second section SC2 ends in the game in which the value was reached, and the game transitions to the first section SC1 and normal game state ST1. The total winnings counter 74s consists of 2 bytes.

Then, a direct hit lottery process is executed (step S1706). In the direct hit lottery process, a direct hit lottery table provided in the main ROM 73 and a lottery counter periodically updated in the main RAM 74 are used to determine by lottery whether or not a direct hit will result in pseudo bonus state ST4. In the lottery process for the current game (FIG. 18), if an index value IV = 11 is won, there is a 2% chance of a direct hit in pseudo bonus state ST4; if an index value IV = 12 is won, there is a 1% chance of a direct hit in pseudo bonus state ST4; if an index value IV = 13 is won, there is a 10% chance of a direct hit in pseudo bonus state ST4; if an index value IV = 14 is won, there is a 5% chance of a direct hit in pseudo bonus state ST4; and if an index value IV = 15 is won, there is a 2% chance of a direct hit in pseudo bonus state ST4. In this case, the lower the index value IV's probability of winning in the role selection process (FIG. 18), the higher the probability of a direct win in pseudo bonus state ST4. This makes it possible to increase the advantage of winning an index value IV with a low winning probability in the role selection process (FIG. 18).

If the direct hit lottery process results in a direct hit win to pseudo bonus state ST4 (step S1707: YES), the first transition confirmation flag stored in the main RAM 74 is set to "1" (step S1708). The first transition confirmation flag is a flag used by the main MPU 72 to identify that a win to transition to pseudo bonus state ST4 occurred in the direct hit lottery process (step S1706) executed when transitioning to the second section SC2. If the first transition confirmation flag is set to "1", processing is executed to transition the game state to pseudo bonus state ST4 when the current game ends.

Then, the section display unit 67 is turned on (step S1709). In the section display unit 67 turning on process, the section display unit 67 is switched from an off state to an on state. This causes the section display unit 67 to start announcing that it is in the second section SC2.

If the direct hit lottery process does not result in a direct hit to enter pseudo bonus state ST4 (step S1707: NO), the release game number lottery process is executed by calling a subroutine program called the release game number lottery process with a CALL command (step S1710). The release game number is the number of games required until a transition to pseudo bonus state ST4 occurs if a transition to pseudo bonus state ST4 is not won in the transition lottery process (step S2112) described below. When the release game number lottery program is called with a CALL command in step S1710, return address information for returning to the process of step S1711, which is the next process after step S1710, is stored in the stack area of the main RAM 74. In the release game number lottery process in step S1710, the release game number lottery table 73c (see Figure 24(c)) stored in the main ROM 73 is referenced.

Before explaining the release game number lottery process (Figure 35(b)) in step S1710, we will now explain the release game number lottery table 73c. Figure 35(a) is an explanatory diagram for explaining the contents of the release game number lottery table 73c. As shown in Figure 35(a), the release game number lottery table 73c has four release game numbers set for determining whether they are a win or a loss: 50 games, 200 games, 400 games, and 600 games. In the release game number lottery process, one of these four release game numbers is guaranteed to be a win. The probability of selecting 50 games as the release game number, the probability of selecting 200 games as the release game number, the probability of selecting 400 games as the release game number, and the probability of selecting 600 games as the release game number are each 1/4.

Next, the release game number lottery process executed by the main MPU 72 will be explained with reference to the flowchart in Figure 35 (b). As already explained, the release game number lottery process is executed in step S1710 of the first control process (Figure 34) for the playing area. The release game number lottery process is also executed in step S2506 of the AT process (Figure 42) described below.

In the release game number lottery process, first, the release game number lottery table 73c (see Figure 24(c)) stored in the main ROM 73 is set as the lottery table to be referenced in the release game number lottery process (step S1801). Then, the lottery execution process is executed in steps S1802 to S1807. This lottery execution process is also executed if a negative judgment is made in step S2603 of the start-up addition process (Figure 43(c)) described below, or if the processing of step S2604 is performed. Here, we will explain the case where the lottery execution process (steps S1802 to S1807) is executed with the release game number lottery table 73c set as the lottery table to be referenced in step S1801.

In the lottery execution process (steps S1802 to S1807), one byte of lottery numerical information is first obtained from the lottery counter, which is periodically updated in the main RAM 74, and the obtained lottery numerical information is set in a random number setting counter provided in the main RAM 74 (step S1802). The lottery numerical information is numerical information indicating an integer between "0" and "255," and the random number setting counter is a counter to which the lottery numerical information is set.

Then, the determination target counter provided in the main RAM 74 is set to "4" (step S1803). The determination target counter is a counter that allows the main MPU 72 to grasp the current number of games to be determined among the multiple numbers of games to be determined set in the referenced lottery table (number of games to be released lottery table 73c). The determination target counter consists of 1 byte. In the number of games to be released lottery process, if the value of the determination target counter is "4", the number of games to be determined is "50". If the value of the determination target counter is "3", the number of games to be determined is "200". If the value of the determination target counter is "2", the number of games to be determined is "400". If the number of games to be released of "50", "200", or "400" is not won, the number of games to be released of "600" is won.

Then, the determination value set in the referenced lottery table (number of games to be released lottery table 73c) is added to the value of the random number setting counter (step S1804). As shown in FIG. 35(a), the determination value set in the number of games to be released lottery table 73c is "64," and in step S1804, "64" is added to the value of the random number setting counter.

Then, in step S1804, it is determined whether the value of the random number setting counter after adding the judgment value ("64") exceeds "255" (step S1805), and if the value of the random number setting counter does not exceed "255" (step S1805: NO), the value of the counter to be judged is decremented by 1 (step S1806). The processing of steps S1804 to S1807 is repeated until a positive judgment is made in step S1805 or step S1807. The number of games to be released from the judgment target is updated in the order of 50 games → 200 games → 400 games each time the value of the judgment target counter is decremented by 1 in step S1806.

Then, in step S1806, it is determined whether the value of the target counter after decrementing by 1 is "1" (step S1807). If a negative determination is made in step S1807, the process proceeds to step S1804. Then, the processes of steps S1804 to S1807 are repeatedly executed until a positive determination is made in step S1805 or step S1807.

If a positive judgment is made in step S1805 or step S1807, the release game number lottery process, which was called as a subroutine process by executing the command "RET," is terminated. As already explained, the release game number lottery process is called in step S1710 of the first control process (Figure 34) of the playing area. Therefore, when the release game number lottery process is terminated, the process returns to the next step S1711 of step S1710 in the first control process (Figure 34) of the playing area, based on the return address information stored in the stack area of the main RAM 74. If the number of games to be released is "50", the process returns to step S1711 with the value of the counter to be judged being "4", if the number of games to be released is "200", the process returns to step S1711 with the value of the counter to be judged being "3", if the number of games to be released is "400", the process returns to step S1711 with the value of the counter to be judged being "2", and if the number of games to be released is "600", the process returns to step S1711 with the value of the counter to be judged being "1".

Returning to the explanation of the first control process for the gaming area (Figure 34), after the release game number lottery process is executed in step S1710, the release game number counter setting process is executed (step S1711). As already explained, the release game number counter is a counter used by the main MPU 72 to determine the remaining number of release games, which is the number of games required to transition to the pseudo-bonus state ST4 when none of the first to third transition confirmation flags in the main RAM 74 are set to "1". In the release game number counter setting process, the release game number lottery table 73c (Figure 35(a)) is referenced, and the release game number corresponding to the value of the counter to be determined is set in the release game number counter in the main RAM 74. Specifically, if the value of the counter to be determined is "4", the release game number counter is set to "50", if the value of the counter to be determined is "3", the release game number counter is set to "200", if the value of the counter to be determined is "2", the release game number counter is set to "400", and if the value of the counter to be determined is "1", the release game number counter is set to "600". The value of the counter to be determined is then cleared to "0" (step S1712).

Then, the section display unit 67 is turned on (step S1713), and the first control process for this game section is terminated. In the section display unit 67 turning on process in step S1713, the section display unit 67 is switched from an off state to an on state. This causes the section display unit 67 to start announcing that the second section SC2 is being reached.

Next, the second control processing of the play area executed by the main MPU 72 will be described with reference to the flowchart in Figure 36. The second control processing of the play area is executed in step S1507 of the response processing at the end of play (Figure 32). As described above, the response processing at the end of play is executed after all rotations of reels 32L, 32M, and 32R in one game have stopped, and therefore the second control processing of the play area is also executed after all rotations of reels 32L, 32M, and 32R in one game have stopped.

In the second control process for the game zone, if the second zone flag 76a in the game zone area 76 of the main RAM 74 is set to "1" and the current game zone is the second zone SC2 (step S1901: YES), the state of the end preparation state flag 77e in the game state area 77 of the main RAM 74 is checked to determine whether the current game state is the end preparation state ST6 (step S1902). The end preparation state ST6 is the game state entered when the pseudo bonus state ST4 ends without the ending condition of the second zone SC2, described below, being met, and when the second zone SC2 ends upon the subsequent transition to the normal game state ST1.

If the game is in the end preparation state ST6 (step S1902: YES), it is determined whether the end preparation complete flag stored in the main RAM 74 is set to "1" (step S1903). The end preparation complete flag is a flag that the main MPU 72 uses to determine whether one game has been played in the end preparation state ST6. In the pseudo bonus processing (step S1505) of the response processing at the end of play (Figure 32), if it is determined that the number of remaining games in the pseudo bonus state ST4 is 0 and that the second section SC2 will end upon the subsequent transition to the normal game state ST1, the end preparation state flag 77e is set to "1" and the end preparation complete flag is cleared to "0." Furthermore, in the AT processing (step S1506) in the response processing at the end of play (FIG. 32), if it is determined that the number of remaining games to be continued in the AT state ST5 is 0 and that the second section SC2 will end upon the subsequent transition to the normal game state ST1, the end preparation state flag 77e is set to "1" and the end preparation completion flag is cleared to "0".

If the end preparation completion flag is not set to "1" (step S1903: NO), the end preparation completion flag is set to "1" (step S1904), and then processing from step S1905 onwards is executed. If the end preparation completion flag is set to "1" (step S1903: YES), this means that one game has been played in the end preparation state ST6. In this case, processing is executed to end the second section SC2.

Specifically, the initialization process for the second section SC2 is first executed (step S1915). In the initialization process for the second section SC2, the second section flag 76a in the play section area 76 of the main RAM 74 is cleared to "0." This changes the play section to the first section SC1. Furthermore, in the initialization process for the second section SC2, even if the player is in the pseudo bonus state ST4, the game state is transitioned to the normal play state ST1 by clearing various data indicating the pseudo bonus state ST4 (including the pseudo bonus state flag 77c in the play state area 77), including a counter for storing the number of remaining games in the pseudo bonus state ST4. Furthermore, in the initialization process for the second section SC2, even if the player is in the AT state ST5, the game state is transitioned to the normal play state ST1 by clearing various data indicating the AT state ST5 (including the AT state flag 77d in the play state area 77), including a counter for storing the number of remaining games in the AT state ST5. Furthermore, during the initialization process for the second section SC2, the release game number counter in the main RAM 74 is cleared to "0." Therefore, whether the current gaming state is the normal gaming state ST1, the first CB state ST2, or the second CB state ST3, the remaining release game number (i.e., the ceiling game number) at that time is invalidated, and the remaining release game number is reset upon a subsequent transition to the second section SC2. Note that even if the first CB state ST2 or the second CB state ST3 is in the middle of the first CB state ST2 or the second CB state ST3, the initialization process for the second section SC2 is executed, which ends the second section SC2, but the first CB state ST2 and the second CB state ST3 continue without ending.

Then, the section display unit 67 is turned off (step S1916). In this turning-off process, the section display unit 67 is switched from an on state to an off state. This ends the notification on the section display unit 67 that it is in the second section SC2.

If the game is not in the end preparation state ST6 (step S1902: NO), or if the processing of step S1904 has been executed, the value of the second interval game number counter in the main RAM 74 is incremented by 1 (step S1905). As already explained, the second interval game number counter is a counter that allows the main MPU 72 to grasp the cumulative number of games played in the second interval SC2, and is also a counter that is referenced in the ratio calculation processing in step S1304 of the management processing (Figure 27). By updating the second interval game number counter in step S1905, the content of the ratio display can be made accurate when the ratio display is started on the dual-purpose display unit 66.

Then, the value of the continued game counter 74r in the main RAM 74 is incremented by 1 (step S1906). As already explained, the continued game counter 74r is a counter used by the main MPU 72 to determine the number of games played since the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between.

Then, it is determined whether the value of the continued game counter 74r after adding 1 is equal to or greater than 1500, which is the upper limit number of games (step S1907). If the value of the continued game counter 74r is equal to or greater than 1500, this means that the ending conditions for the second section SC2 have been met. In this case, a positive determination is made in step S1907, and processing is executed to end the second section SC2 in steps S1915 to S1916. The processing content of steps S1915 to S1916 has already been explained. As a result, the second section SC2 ends and the first section SC1 begins. If the pseudo-bonus state ST4 was in the middle of the pseudo-bonus state, the pseudo-bonus state ST4 is forcibly ended and the game enters the normal game state ST1. If the AT state ST5 was in the middle of the AT state, the AT state ST5 is forcibly ended and the game enters the normal game state ST1.

If the value of the continued game number counter 74r is less than 1500 (step S1907: NO), it is determined whether any of the following replay wins has occurred in the current game: a first chance replay win, a second chance replay win, or a regular replay win (step S1908). In this case, whether the number of bets in the current game is "2" or "3" is subject to the determination in step S1908, and whether the current game is in the regular game state ST1, the first CB state ST2, the second CB state ST3, the pseudo bonus state ST4, or the AT state ST5 is subject to the determination in step S1908.

If no replay wins have been achieved (step S1908: NO), the number of bets for the current game (i.e., the value of the bet number setting counter 74b) is subtracted from the total wins counter 74s in the main RAM 74 (step S1909). In this case, even if a replay win was achieved in the previous game and the current game is a game that corresponds to a replay due to the achievement of that replay win, the number of bets for the current game (i.e., the value of the bet number setting counter 74b) is subtracted from the total wins counter 74s.

As already explained, the total acquisition counter 74s is a counter used by the main MPU 72 to determine the limited total net increase in gaming media since the start of the second section SC2 when the second section SC2 continues without the first section SC1 in between. As already explained, the limited total net increase in gaming media refers to the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined reference value, and the difference is calculated by subtracting the total number of gaming media consumed to play games while the second section SC2 is continuing (0 when no games are being played) from the total number of gaming media awarded through games played while the second section SC2 is continuing (0 when no gaming media are awarded).

Then, it is determined whether any of the minor winning combinations (1st to 9th supplementary winning combinations, 1st bell winning combination, 2nd bell winning combination, 1st watermelon winning combination, 2nd watermelon winning combination, and cherry winning combination) that result in the awarding of gaming media in the current game has been achieved (step S1910). In this case, whether the number of bets in the current game is "2" or "3," the determination in step S1910 is also subject to determination in step S1910 regardless of whether the current game is in the normal gaming state ST1, the first CB state ST2, the second CB state ST3, the pseudo bonus state ST4, or the AT state ST5. If a positive determination is made in step S1910, the number of gaming media awarded in the current game is added to the total winnings counter 74s in the main RAM 74 (step S1911).

If a negative judgment is made in step S1910, or if the processing of step S1911 is executed, it is determined whether the value of the total acquisition number counter 74s in the main RAM 74 is 0 or greater (step S1912). If the value of the total acquisition number counter 74s is less than 0 (step S1912: NO), the total acquisition number counter 74s is cleared to "0" (step S1913).

As described above, the bet number for the current game is subtracted from the total wins counter 74s in step S1909. Therefore, for example, if no small wins are achieved in a game in normal game state ST1 immediately after transitioning to the second section SC2, the value of the total wins counter 74s will be less than 0. In this case, a negative judgment is made in step S1912, and the total wins counter 74s is cleared to "0" in step S1913. As a result, if the predetermined difference is calculated by subtracting the "total number of gaming media consumed to play games while the second section SC2 is continuing ("0" when no games are being played)" from the "total number of gaming media awarded through games played while the second section SC2 is continuing ("0" when no gaming media are awarded)," the minimum value of the predetermined difference can be used as a predetermined reference value. The total wins counter 74s can then be used to measure the limited total net increase in gaming media, which is the increase in the predetermined difference from the predetermined reference value.

If a positive judgment is made in step S1908, if a positive judgment is made in step S1912, or if the processing of step S1913 is executed, it is determined whether the value of the total winnings counter 74s exceeds the upper limit net increase of 2400 (step S1914). If the value of the total winnings counter 74s exceeds 2400, this means that the ending condition for the second section SC2 has been met. In this case, a positive judgment is made in step S1914, and processing to end the second section SC2 is executed in steps S1915 to S1916. The processing content of steps S1915 to S1916 has already been explained. As a result, the second section SC2 ends and the first section SC1 begins. If the pseudo-bonus state ST4 was in the middle of the pseudo-bonus state, the pseudo-bonus state ST4 is forcibly ended and the normal gaming state ST1 is entered. If the AT state ST5 was in the middle of the AT state, the AT state ST5 is forcibly ended and the normal gaming state ST1 is entered.

If any replay win is achieved, a positive determination is made in step S1908, and steps S1909 to S1913 are not executed. In a game in which a replay win is achieved, the gaming media owned by the player at the start of the game are used to set the bet, but as a benefit from the replay win, the player can replay a new game with the same number of bets as the number of bets made in the game in which the replay win was achieved. In other words, the number of gaming media owned by the player does not change in a game in which a replay win is achieved. In this case, by not executing steps S1909 to S1913 in a game in which a replay win is achieved, it is possible to omit the execution of the process to change the value of the total win counter 74s in games in which the number of gaming media owned by the player does not change, thereby eliminating the execution of unnecessary process.

On the other hand, even in a game in which a replay win is achieved, step S1914 determines whether the value of the total wins counter 74s exceeds the upper limit of net increase of coins, which is "2400." This makes it possible to determine that the value of the total wins counter 74s exceeds the upper limit of net increase of coins, which is "2400," in a game prior to the game in which a replay win is achieved, even if the initialization process for the second section SC2 has not been performed due to noise or other reasons, and the value of the total wins counter 74s exceeds the upper limit of net increase of coins, which is "2400," in the subsequent game in which a replay win is achieved, and enables the initialization process for the second section SC2 to be performed.

If a negative judgment is made in step S1914, ending response processing is executed (step S1917), and the second control processing for this game section is terminated. Figure 37 is a flowchart showing the ending response processing in step S1917.

The ending response process first determines whether the first ending flag 76b in the game section area 76 of the main RAM 74 is set to "1" (step S2001). As already explained, the first ending flag 76b is a flag used by the main MPU 72 to identify whether the number of games played in the second section SC2, measured using the continued game counter 74r, is likely to reach the upper limit number of games.

If the first ending flag 76b is not set to "1" (step S2001: NO), it is determined whether the sum of the value of the continued game number counter 74r in the main RAM 74, the value of the pseudo bonus continuation counter 74t (see FIG. 14) provided in the main RAM 74, and the value of the AT continuation counter 74u (see FIG. 14) provided in the main RAM 74 is greater than or equal to the upper limit number of games for the second section SC2 (step S2002). The pseudo bonus continuation counter 74t is a counter used by the main MPU 72 to determine the remaining number of continued games in the pseudo bonus state ST4. The pseudo bonus continuation counter 74t consists of one byte. The AT continuation counter 74u is a counter used by the main MPU 72 to determine the remaining number of continued games in the AT state ST5. The AT continuation counter 74u consists of two bytes. As already explained, the upper limit number of games for the second section SC2 is set to 1,500 games. Note that the upper limit on the number of games in the second section SC2 is not limited to 1,500 games, and may be less than 1,500 games or more than 1,500 games.

If a positive judgment is made in step S2002, the first ending flag 76b is set to "1" (step S2003). When the first ending flag 76b is set to "1," the transition condition to the AT state ST5 is not met in the pseudo bonus state ST4 (details will be described later), and the remaining number of continued games is not added in the AT state ST5. Furthermore, when the pseudo bonus state ST4 or the AT state ST5 ends and the game transitions to the normal game state ST1, the second section SC2 ends and the game transitions to the first section SC1. This prevents the transition condition to the AT state ST5 from being met in a situation where the ending condition for the second section SC2 is met, and prevents the remaining number of continued games in the AT state ST5 from being added. Note that the situation in which the first ending flag 76b is set to "1" generally occurs in the pseudo bonus state ST4 or the AT state ST5, but can also occur in the first CB state ST2 or the second CB state ST3. Furthermore, even if the first ending flag 76b is set to "1" in the first CB state ST2, the second CB state ST3, or the pseudo bonus state ST4, the game content will not change, and the execution mode of the presentation will not change either.

If a positive judgment is made in step S2001, a negative judgment is made in step S2002, or the processing of step S2003 is executed, it is determined whether the second ending flag 76c provided in the game section area 76 of the main RAM 74 is set to "1" (step S2004). As already explained, the second ending flag 76c is a flag used by the main MPU 72 to identify that there is a high possibility that the limited total net increase in the number of gaming media measured using the total acquisition counter 74s will reach the upper limit net increase.

If the second ending flag 76c is not set to "1" (step S2004: NO), the sum of the value of the pseudo bonus continuation counter 74t and the value of the AT continuation counter 74u is multiplied by the expected value of gaming media to be acquired in the pseudo bonus state ST4 and the AT state ST5, and the result is added to the value of the total acquisition counter 74s. It is determined whether the result is equal to or greater than the upper limit net increase in the number of gaming media for the second section SC2 (step S2005). The expected value of gaming media to be acquired in one game in the pseudo bonus state ST4 and the AT state ST5 is approximately 5. As already explained, the upper limit net increase in the number of gaming media for the second section SC2 is set to 2,400. Note that the upper limit net increase in the number of gaming media for the second section SC2 is not limited to 2,400, and may be less than or greater than 2,400.

If a positive judgment is made in step S2005, the second ending flag 76c is set to "1" (step S2006). When the second ending flag 76c is set to "1," the transition condition to the AT state ST5 is not met in the pseudo bonus state ST4 (details will be described later), and no additional addition to the remaining number of continued games occurs in the AT state ST5. Furthermore, when the pseudo bonus state ST4 or the AT state ST5 ends and a transition to the normal gaming state ST1 occurs, the second section SC2 ends and a transition to the first section SC1 occurs. This prevents the transition condition to the AT state ST5 from being met in a situation where the ending condition for the second section SC2 would be met, and prevents any additional addition to the remaining number of continued games in the AT state ST5. The second ending flag 76c is set to "1" in the pseudo bonus state ST4 or the AT state ST5, but does not occur in the normal game state ST1, the first CB state ST2, or the second CB state ST3. Furthermore, even if the second ending flag 76c is set to "1" in the pseudo bonus state ST4, the game content does not change, and the execution mode of the presentation does not change either.

<Regarding normal gaming state ST1>
Next, the processing contents in the normal game state ST1 will be explained. Fig. 38 is a flowchart showing the advantageous lottery processing at the start of the game executed by the main MPU 72. The advantageous lottery processing at the start of the game is executed in step S912, which is processing executed after the winning/losing judgment of the winning combination has been completed in the winning combination lottery processing (Fig. 18) and before the first control processing of the game section (step S913).

The advantageous lottery process at the start of the game first determines whether the second zone flag 76a in the game zone area 76 of the main RAM 74 is set to "1" (step S2101). If the second zone flag 76a is not set to "1" (step S2101: NO), the processing from step S2102 onwards is not executed. As a result, if the first zone SC1 is reached, the processing from step S2106 onwards to transition the game state to the pseudo-bonus state ST4 is not executed.

If the second interval flag 76a is set to "1" (step S2101: YES), and the current game state is the pseudo-bonus state ST4 or the AT state ST5 (step S2102: YES), processing for the advantageous state at the start of the game is executed (step S2103). The processing for the advantageous state at the start of the game will be explained later.

If the second interval flag 76a is set to "1" (step S2101: YES) and the game state is neither the pseudo bonus state ST4 nor the AT state ST5 (step S2102: NO), the main MPU 72 determines whether the current game state is the first CB state ST2 or the second CB state ST3 (step S2104). As already explained, the main MPU 72 determines that the game state is the first CB state ST2 when the first CB state flag 77a in the game state area 77 is set to "1," and determines that the game state is the second CB state ST3 when the second CB state flag 77b is set to "1." If the current game state is the first CB state ST2 or the second CB state ST3 (step S2104: YES), the processing from step S2105 onwards is not executed. As a result, even if it is the second section SC2, if it is the first CB state ST2 or the second CB state ST3, processing to transition the game state to the pseudo bonus state ST4 from step S2106 onwards will not be executed.

If the current gaming state is neither the first CB state ST2 nor the second CB state ST3 (step S2104: NO), the value of the bet number setting counter 74b in the main RAM 74 is determined to be "3", thereby determining whether the number of bets for the current game is "3" (step S2105). If the number of bets for the current game is "2" (step S2105: NO), processing from step S2106 onwards is not executed. As a result, in a game where the number of bets is "2", even if it is in the second section SC2, processing from step S2106 onwards to transition the gaming state to the pseudo-bonus state ST4 is not executed.

If the number of bets on the current game is "3" (step S2105: YES), the process determines whether the value of the continued game counter 74r is equal to or greater than the reference number of games (step S2106), and determines whether the value of the total win counter 74s is equal to or greater than the reference number of wins (step S2107). As already explained, the continued game counter 74r is a counter used by the master MPU 72 to determine the number of games played since the start of the second section SC2 when the second section SC2 continues without the first section SC1 in between. If the value of the continued game counter 74r during the second section SC2 reaches a value corresponding to the upper limit number of games (specifically, 1,500 games), the second section SC2 ends with the game that reached the upper limit, even if the pseudo-bonus state ST4 is in progress, and the process transitions to the first section SC1 and normal game state ST1. As already explained, the total acquisition counter 74s is a counter for determining the limited total net increase in game media from the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between, in the main MPU 72. As already explained, the limited total net increase in game media is the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined reference value, and the difference is calculated by subtracting the total number of game media consumed to play games when the second section SC2 is continuing (0 when no game is being played) from the total number of game media awarded by games played when the second section SC2 is continuing (0 when no game media is awarded). If the value of the total winnings counter 74s reaches a value corresponding to the upper limit of net increase in coins (specifically, 2,400 coins) in the second section SC2, even if the pseudo-bonus state ST4 is in progress, the second section SC2 ends in the game in which the value is reached, and the game enters the first section SC1 and the normal game state ST1.

The reference number of games is set to a number less than the upper limit of 1,500 games in the second section SC2, specifically 1,450 games. The reference number of coins won is set to a number less than the upper limit of 2,400 net increase coins in the second section SC2, specifically 2,150 coins.

If the value of the continued game number counter 74r is equal to or greater than the reference number of games (step S2106: YES), or if the value of the total wins counter 74s is equal to or greater than the reference number of wins (step S2107: YES), the third transition confirmation flag stored in the main RAM 74 is set to "1" (step S2108). The third transition confirmation flag is a flag used by the main MPU 72 to determine whether a transition to pseudo-bonus state ST4 has been confirmed due to the upper limit number of games played in the second section SC2 being equal to or greater than the reference number of games played, or the limited total net increase in gaming media in the second section SC2 being equal to or greater than the reference number of wins.

When the third transition confirmation flag is set to "1," processing is executed to transition the game state to the pseudo bonus state ST4 when the current game ends. In other words, when the pre-end period, in which the ending conditions of the second section SC2 are close to being met, is reached in the normal game state ST1, the pseudo bonus state ST4 is forcibly entered. This makes it possible to award the benefit of the pseudo bonus state ST4 occurring in response to reaching the pre-end period in the normal game state ST1. The pseudo bonus state ST4, which begins when the third transition confirmation flag is set to "1," has a continuing game count of 50 games set at the start. The continuing game count set at this start is the difference between the upper limit game count of 1,500 games for the second section SC2 and the base game count of 1,450 games. Furthermore, as already explained, the expected number of gaming media to be acquired in one game in pseudo-bonus state ST4 is approximately 5, so the product of the number of continuing games set at the start and this expected number of gaming media to be acquired is the same or approximately the same as the difference between the upper limit net increase of 2,400 in the second section SC2 and the standard number of gaming media to be acquired, 2,150.

After executing the processing of step S2108, various clearing processes are executed (step S2109). In the various clearing processes, the values of the second transition confirmation flag and the transition waiting counter stored in the main RAM 74 are each cleared to "0." The second transition confirmation flag is a flag that is set to "1" when a transition is won in the transition lottery process (step S2112) described below, and the transition waiting counter is a counter that the main MPU 72 uses to determine how many transition waiting games (specifically, five games) have been played since the second transition confirmation flag was set to "1." When a transition is won in the transition lottery process (step S2112), not only is the second transition confirmation flag set to "1," but a value corresponding to the number of transition waiting games is also set in the transition waiting counter, and the value of the transition waiting counter is decremented by one each time one game is played while the second transition confirmation flag is set to "1." Then, when the value of the transition waiting counter becomes "0" while the second transition confirmation flag is set to "1," the gaming state transitions to the pseudo bonus state ST4. Therefore, a transition to the pseudo bonus state ST4 occurs when the number of transition waiting games is consumed after a transition win is achieved in the transition lottery process (step S2112). In this case, if the third transition confirmation flag is set to "1" as described above, even if the second transition confirmation flag was set to "1" at that time, the second transition confirmation flag is cleared to "0." This makes it possible to prioritize the occurrence of the pseudo bonus state ST4 triggered by the third transition confirmation flag being set to "1" over the occurrence of the pseudo bonus state ST4 triggered by the second transition confirmation flag being set to "1."

If the value of the continued game counter 74r is less than the reference number of games played and the value of the total wins counter 74s is less than the reference number of wins (steps S2106 and S2107: NO), provided that the second transition confirmation flag in the main RAM 74 is not set to "1" (step S2110: NO), it is determined whether or not the current role has been selected for index value IV = 11 to 15 in the lottery process (Figure 18) (step S2111). If a positive determination is made in step S2111, the transition lottery process is executed (step S2112). In the transition lottery process, a transition lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74 are used to determine by lottery whether or not to transition to the pseudo-bonus state ST4. In the lottery process for the current game (FIG. 18), if an index value IV = 11 is won, there is a 20% chance of winning and transitioning to the pseudo bonus state ST4; if an index value IV = 12 is won, there is a 10% chance of winning and transitioning to the pseudo bonus state ST4; if an index value IV = 13 is won, there is a 40% chance of winning and transitioning to the pseudo bonus state ST4; if an index value IV = 14 is won, there is a 30% chance of winning and transitioning to the pseudo bonus state ST4; and if an index value IV = 15 is won, there is a 20% chance of winning and transitioning to the pseudo bonus state ST4. In this case, the lower the probability of winning in the lottery process for the role (FIG. 18), the higher the probability of winning and transitioning to the pseudo bonus state ST4. This increases the advantage of winning an index value IV with a low winning probability in the lottery process for the role (FIG. 18).

If the transition lottery process results in a win to transition to pseudo bonus state ST4 (step S2113: YES), bonus type determination processing is executed in steps S2114 to S2115 to determine the type of pseudo bonus state ST4. Pseudo bonus state ST4 is set to a relatively advantageous big bonus and a relatively less advantageous regular bonus. The big bonus is a pseudo bonus state ST4 that continues until 50 games with a bet of "3" have been played, while the regular bonus is a pseudo bonus state ST4 that continues until 20 games with a bet of "3" have been played. Note that the number of games for each of the above is arbitrary, as long as the big bonus is relatively more advantageous than the regular bonus. Furthermore, if the big bonus is relatively more advantageous than the regular bonus, the number of continuing games may be the same for both bonuses, but the expected value of game media acquired in one game may be higher for the big bonus than for the regular bonus, making the big bonus relatively more advantageous than the regular bonus.

The bonus type determination process first executes a bonus type lottery process (step S2114). The bonus type lottery process uses a type lottery table provided in the main ROM 73 and a lottery counter that is regularly updated in the main RAM 74 to determine whether the type of pseudo-bonus state ST4 that has been entered this time will be a big bonus or a regular bonus. The type lottery table is set so that the selection probability of a big bonus and a regular bonus is 50%, regardless of the result of the current role lottery process (FIG. 18). However, this is not limited to this. A big bonus may be selected more frequently than a regular bonus, or a regular bonus may be selected more frequently than a big bonus. The selection ratio of a big bonus and a regular bonus may also be varied depending on the result of the current role lottery process (FIG. 18).

Then, the big win flag setting process is executed (step S2115). In the big win flag setting process, if a big bonus is selected in the bonus type lottery process in step S2114, the big win flag stored in the main RAM 74 is set to "1". The big win flag is a flag used by the main MPU 72 to identify that a big bonus has been selected in the bonus type lottery process. Furthermore, in the big win flag setting process, if a regular bonus is selected in the bonus type lottery process in step S2114, the big win flag stored in the main RAM 74 is cleared to "0".

Then, the second transition confirmation flag stored in the main RAM 74 is set to "1" (step S2116), and the transition waiting counter stored in the main RAM 74 is set to a value corresponding to the number of transition waiting games (specifically, 5 games) (step S2117), terminating the advantageous lottery process at the start of the game. The second transition confirmation flag is a flag that the main MPU 72 uses to determine whether or not a transition has been won in the transition lottery process (step S2112), and the transition waiting counter is a counter that the main MPU 72 uses to determine whether or not a transition has been won in the transition lottery process (step S2112), and the transition waiting counter is a counter that the main MPU 72 uses to determine whether or not the number of transition waiting games (specifically, 5 games) has been played since the second transition confirmation flag was set to "1." Winning a transition in the transition lottery process (step S2112) not only sets the second transition confirmation flag to "1," but also sets the transition waiting counter to a value corresponding to the number of transition waiting games, and the value of the transition waiting counter is decremented by 1 each time a game is played while the second transition confirmation flag is set to "1." Then, when the second transition confirmation flag is set to "1", the value of the transition waiting counter becomes "0", causing the game state to transition to pseudo bonus state ST4. Therefore, a transition to pseudo bonus state ST4 occurs when the number of transition waiting games is consumed after a transition win is achieved in the transition lottery process (step S2112).

Next, the normal processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 39. The normal processing is executed in step S1504 of the end-of-game response processing (Figure 32). As described above, the end-of-game response processing is executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game, and therefore the normal processing is also executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game.

If the second section flag 76a in the play section area 76 of the main RAM 74 is set to "1" and the current play section is the second section SC2 (step S2201: YES), it is determined whether the first transition confirmation flag in the main RAM 74 is set to "1" (step S2202). If a transition to the second section SC2 has occurred at the start of the current game and a direct hit has been won in the direct hit lottery process (step S1706) executed to determine the transition, the first transition confirmation flag is set to "1".

If the first transition confirmation flag is set to "1" (step S2202: YES), the first start setting process is executed (step S2203). In the first start setting process, the pseudo bonus state flag 77c in the game state area 77 of the main RAM 74 is set to "1." The pseudo bonus state flag 77c is a flag that the main MPU 72 uses to determine whether the game state is in the pseudo bonus state ST4. Furthermore, in the first start setting process, the pseudo bonus continuation counter 74t in the main RAM 74 is set to a value corresponding to 50 games, which is the number of games that the big bonus will continue, as the initial number of continuation games in the pseudo bonus state ST4. In other words, in a configuration in which the pseudo bonus state ST4 is configured with a big bonus and a regular bonus, which have relatively high and low advantageous degrees, if a direct hit is won in the direct hit lottery process (step S1706) and a transition to the pseudo bonus state ST4 occurs, a transition to the big bonus will occur. As already explained, the pseudo bonus continuation counter 74t is a counter that allows the main MPU 72 to determine the remaining number of continuation games in the pseudo bonus state ST4.

If the first transition confirmation flag is not set to "1" (step S2202: NO), it is determined whether the third transition confirmation flag in the main RAM 74 is set to "1" (step S2204). As already explained, the third transition confirmation flag is a flag used by the main MPU 72 to determine whether a transition to pseudo-bonus state ST4 has been confirmed due to the number of continued games in the second section SC2 being equal to or greater than the reference number of games, or the limited total net increase in the number of gaming media in the second section SC2 being equal to or greater than the reference number of acquisitions.

If the third transition confirmation flag is set to "1" (step S2204: YES), the second start setting process is executed (step S2205). In the second start setting process, the pseudo bonus state flag 77c in the game state area 77 of the main RAM 74 is set to "1". In addition, in the second start setting process, the pseudo bonus continuation counter 74t in the main RAM 74 is set to a value corresponding to 50 games, which is the number of continuation games for a big bonus, as the initial number of continuation games for the pseudo bonus state ST4. In other words, in a configuration in which the pseudo bonus state ST4 is configured with a big bonus and a regular bonus, which have relatively high and low degrees of advantage, if a transition to the pseudo bonus state ST4 occurs because the number of continuation games in the second section SC2 is equal to or exceeds the reference number of games or the limited total net increase in the number of gaming media in the second section SC2 is equal to or exceeds the reference number of acquisitions, a transition to the big bonus will occur.

If the third transition confirmation flag is not set to "1" (step S2204: NO), the first CB state flag 77a and the second CB state flag 77b are referenced to determine whether the current game state is the first CB state ST2 or the second CB state ST3 (step S2206). If the current game state is the first CB state ST2 or the second CB state ST3 (step S2206: YES), the processing from step S2207 onwards is not executed. In the processing from step S2207 onwards, the number of games required to transition to the pseudo bonus state ST4 is subtracted as one game is played, and if the transition condition to the pseudo bonus state ST4 is met as one game is played, the processing to transition to the pseudo bonus state ST4 is executed. In this case, by not executing the processing from step S2207 onwards when in the first CB state ST2 or the second CB state ST3, even if the game is played in the first CB state ST2 or the second CB state ST3, it is possible to prevent this from becoming a factor that brings the transition to the pseudo bonus state ST4 closer.

If the current gaming state is neither the first CB state ST2 nor the second CB state ST3 (step S2206: NO), the value of the bet number setting counter 74b in the main RAM 74 is determined to be "3," thereby determining whether the number of bets for the current game is "3" (step S2207). If the number of bets for the current game is "2" (step S2207: NO), the processing from step S2208 onwards is not executed. As already explained, the processing from step S2208 onwards executes a process to subtract the number of games required to transition to pseudo bonus state ST4 as each game is played, and if the transition condition to pseudo bonus state ST4 is met as the game is played, a process to transition to that pseudo bonus state ST4 is executed. In this case, by not executing the processing from step S2208 onwards if a game with a bet number of "2" is played, it is possible to prevent the completion of a game with a bet number of "2" from becoming a factor in approaching the transition to pseudo bonus state ST4.

If the number of bets on this game is "3" (step S2207: YES), it is determined whether the second transfer confirmation flag in the master RAM 74 is set to "1" (step S2208). As already explained, the second transfer confirmation flag is a flag used by the master MPU 72 to determine whether a transfer win has been achieved in the transfer lottery process (step S2112).

If the second transition confirmation flag is set to "1" (step S2208: YES), the value of the transition wait counter in the main RAM 74 is decremented by 1 (step S2209). As already explained, the transition wait counter is a counter used by the main MPU 72 to determine how many transition wait games (specifically, 5 games) have been played since the second transition confirmation flag was set to "1". If the value of the transition wait counter after decrementing by 1 is "0" (step S2210: YES), the third start setting process is executed in steps S2213 to S2217. Details will be described later, but the third start setting process executes processing to transition to pseudo bonus state ST4.

If the second transition confirmation flag is not set to "1" (step S2208: NO), the value of the release game number counter in the main RAM 74 is decremented by 1 (step S2211). The release game number counter is a counter used by the main MPU 72 to determine the remaining number of release games, which is the number of games required to transition to the pseudo bonus state ST4 when none of the first to third transition confirmation flags in the main RAM 74 are set to "1." If the game zone transitions from the first zone SC1 to the second zone SC2 and no direct hit is won in the direct hit lottery process (step S1706), the release game number counter is set to the release game number. The release game number counter is also set if the second zone SC2 is maintained after the AT state ST5 ends.

If the value of the release game number counter after subtracting 1 is "0" (step S2212: YES), the third start setting process is executed in steps S2213 to S2217. Details will be described later, but the third start setting process executes processing to transition to pseudo bonus state ST4.

In the third start setting process in steps S2213 to S2217, the pseudo-bonus state flag 77c in the game status area 77 of the main RAM 74 is first set to "1" (step S2213). Then, it is determined whether the big win flag in the main RAM 74 is set to "1" or whether the value of the release game count counter in the main RAM 74 is "0" (step S2214). As already explained, if a transfer win is achieved in the transfer lottery process (step S2112) and a big bonus is selected in the bonus type lottery process (step S2114 of the advantageous lottery process at the start of the game (FIG. 38)), the big win flag is set to "1." Furthermore, as already explained, the release game count counter is a counter used by the main MPU 72 to measure the number of release games. A situation in which the value of the release game count counter is "0" means that the number of release games has reached "0," triggering a transition to the pseudo-bonus state ST4.

If a positive judgment is made in step S2214, the pseudo bonus continuation counter 74t in the main RAM 74 is set to "50" (step S2215). As a result, the pseudo bonus state ST4 that occurs this time becomes a big bonus. Thereafter, regardless of whether the big win flag in the main RAM 74 is set to "1" or not, the big win flag is cleared to "0" (step S2216), and the normal processing ends. On the other hand, if a negative judgment is made in step S2214, the pseudo bonus continuation counter 74t in the main RAM 74 is set to "20" (step S2217), and the normal processing ends. As a result of the pseudo bonus continuation counter 74t being set to "20" in step S2217, the pseudo bonus state ST4 that occurs this time becomes a regular bonus.

<About advantageous game conditions>
Next, the processing contents in the pseudo bonus state ST4 and the AT state ST5 will be explained. Figure 40 is a flowchart showing the processing for the advantageous state at the start of the game executed by the main MPU 72. As already explained, the advantageous lottery processing at the start of the game is executed in step S912, which is processing executed after the judgment of the winning or losing role in the lottery processing for the winning role (Figure 18) is completed and before the first control processing of the game area (step S913). Then, the processing for the advantageous state at the start of the game is executed in step S2103 in the advantageous lottery processing at the start of the game (Figure 38).

In the advantageous state processing at the start of a game, first, it is determined whether the value of the bet number setting counter 74b in the main RAM 74 is "3" to determine whether the number of bets for the current game is "3" (step S2301). If the number of bets for the current game is "2" (step S2301: NO), processing from step S2302 onwards is not executed. As a result, even if the game is in pseudo bonus state ST4 or AT state ST5, processing from step S2302 onwards is not executed in a game where the number of bets is "2".

If the number of bets on this game is "3" (step S2301: YES), the first CB state flag 77a and the second CB state flag 77b are referenced to determine whether the current gaming state is the first CB state ST2 or the second CB state ST3 (step S2302). If the current gaming state is the first CB state ST2 or the second CB state ST3 (step S2302: YES), processing from step S2303 onwards is not executed. As a result, even if the pseudo bonus state flag 77c or the AT state flag 77d in the main RAM 74 is set to "1," if the current gaming state is the first CB state ST2 or the second CB state ST3, processing from step S2303 onwards is not executed.

If the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S2302: NO), the process determines whether either the first ending flag 76b or the second ending flag 76c in the game section area 76 of the main RAM 74 is set to "1" (step S2303). As already explained, the first ending flag 76b is a flag used by the main MPU 72 to determine that the number of games played in the second section SC2, measured using the continued game counter 74r, has reached the upper limit. As already explained, the second ending flag 76c is a flag used by the main MPU 72 to determine that the limited total net increase in game media, measured using the total acquisition counter 74s, is likely to reach the upper limit. If either the first ending flag 76b or the second ending flag 76c is set to "1" (step S2303: YES), the process from step S2304 onward is not executed. As a result, in situations where the number of games played in the second section SC2 reaches the upper limit, or where there is a high possibility that the limited total net increase in the number of gaming media will reach the upper limit, the processes in steps S2304 to S2309 for determining whether to transition to AT state ST5 and the processes in steps S2310 to S2313 for increasing the number of continued games in AT state ST5 will not be executed.

If neither the first ending flag 76b nor the second ending flag 76c is set to "1" (step S2303: NO), the MPU 72 determines whether the current game state is in the pseudo-bonus state ST4 by determining whether the pseudo-bonus state flag 77c in the game state area 77 of the main RAM 74 is set to "1" (step S2304). If the current game state is in the pseudo-bonus state ST4 (step S2304: YES), the MPU 72 determines whether the AT transition confirmation flag 77f in the game state area 77 of the main RAM 74 is set to "1" (step S2305). As already explained, the AT transition confirmation flag 77f is a flag that the main MPU 72 uses to determine whether the transition conditions to the AT state ST5 have already been met in the pseudo-bonus state ST4. If the AT transition confirmation flag 77f is already set to "1" (step S2305: YES), that is, if the conditions for transitioning to AT state ST5 have already been met in the current pseudo bonus state ST4, the process for determining whether to transition to AT state ST5 from step S2306 onwards is not executed.

If the AT transition confirmation flag 77f is not set to "1" (step S2305: NO), the AT transition lottery process is executed (step S2307) on the condition that the index value IV = 11 to 15 is won in the lottery process for the current game (Figure 18) (step S2306: YES). The AT transition lottery process uses the AT transition lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74 to determine by lottery whether to transition to the AT state ST5 after the end of the current pseudo-bonus state ST4. In the lottery process for the current game (FIG. 18), if an index value IV = 11 is selected, there is a 20% chance of winning the AT transition; if an index value IV = 12 is selected, there is a 10% chance of winning; if an index value IV = 13 is selected, there is a 40% chance of winning; if an index value IV = 14 is selected, there is a 30% chance of winning; and if an index value IV = 15 is selected, there is a 20% chance of winning. In this case, the lower the probability of winning the lottery process for the role (FIG. 18), the higher the probability of winning the AT transition. This increases the advantage of selecting an index value IV with a low probability of winning in the lottery process for the role (FIG. 18). Thereafter, if an AT transition is selected (step S2308: YES), the AT transition confirmation flag 77f is set to "1" (step S2309).

As already explained, the advantageous state processing at the start of the game (Figure 40) is executed (step S2103) on the condition that the advantageous lottery processing at the start of the game (Figure 38) is in pseudo-bonus state ST4 or AT state ST5 (step S2102: YES). If the current gaming state is not pseudo-bonus state ST4 (step S2304: NO), i.e., if the current gaming state is AT state ST5, a program for executing the start-up addition processing is called by a CALL command, and the start-up addition processing is executed (step S2310). When a program for executing the start-up addition processing is called by a CALL command in step S2310, return address information for returning to the processing of the next step S2311 after step S2310 is stored in the stack area of the main RAM 74. Steps S2310 to S2313 are processing for adding to the number of continued games in AT state ST5. Details of the processing in steps S2310 to S2313 will be described later.

Next, the pseudo bonus processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 41. The pseudo bonus processing is executed in step S1505 of the end-of-game response processing (Figure 32). As described above, the end-of-game response processing is executed after all rotations of reels 32L, 32M, and 32R in one game have stopped, and therefore the pseudo bonus processing is also executed after all rotations of reels 32L, 32M, and 32R in one game have stopped.

In the pseudo bonus processing, the system first determines whether the number of bets for the current game is "3" by determining whether the value of the bet number setting counter 74b in the main RAM 74 is "3" (step S2401). If the number of bets for the current game is "2" (step S2401: NO), processing from step S2402 onwards is not executed. As a result, even if a game with a bet number of "2" is played in pseudo bonus state ST4, the number of remaining games to continue in pseudo bonus state ST4 is not subtracted.

Note that when in the CB state (first CB state ST2 or second CB state ST3), the pseudo bonus processing (Figure 41) itself is not executed, so even if the CB state is started in the middle of the pseudo bonus state ST4, the number of games played in the CB state is not treated as the number of games played in the pseudo bonus state ST4. Therefore, even if the CB state is entered in the middle of the pseudo bonus state ST4, after the CB state ends, the pseudo bonus state ST4 will resume from the number of remaining games played immediately before the transition to the CB state.

If the number of bets on this game is "3" (step S2401: YES), the value of the pseudo bonus continuation counter 74t in the main RAM 74 is decremented by 1 (step S2402). Then, it is determined whether the value of the pseudo bonus continuation counter 74t is "0" (step S2403). If the value of the pseudo bonus continuation counter 74t is "0" (step S2403: YES), it is determined whether the AT transition confirmation flag 77f in the game status area 77 of the main RAM 74 is set to "1" (step S2404).

If the AT transition confirmation flag 77f is set to "1" (step S2404: YES), this means that the conditions for transitioning to AT state ST5 have been met in the current pseudo-bonus state ST4. In this case, the pseudo-bonus state flag 77c in the main RAM 74 is first cleared to "0" (step S2405). Then, information corresponding to "50," the initial number of continuing games in AT state ST5, is set in the AT state counter provided in the main RAM 74 (step S2406), and the AT state flag 77d in the game state area 77 of the main RAM 74 is set to "1" (step S2407), terminating this pseudo-bonus processing.

If the AT transition confirmation flag 77f is not set to "1" (step S2404: NO), the process for setting the end preparation state ST6 is executed (step S2408). In this setting process, the pseudo bonus state flag 77c in the game status area 77 of the main RAM 74 is cleared to "0." In addition, in this setting process, the end preparation state flag 77e in the game status area 77 of the main RAM 74 is set to "1." As already explained, the end preparation state flag 77e is a flag used by the main MPU 72 to identify the end preparation state ST6. Setting the end preparation state flag 77e to "1" changes the game status to the end preparation state ST6. Thereafter, the end preparation complete flag in the main RAM 74 is cleared to "0" (step S2409), and the pseudo bonus process is terminated. As already explained, the end preparation complete flag is a flag used by the main MPU 72 to identify whether one game has been played in the end preparation state ST6.

As already explained, in the end preparation state ST6, if a positive judgment is made in step S1902 of the second control processing for the game section (Figure 36) and the end preparation complete flag is not set to "1" (step S1903: NO), the end preparation complete flag is set to "1" and processing is executed to determine whether the ending conditions for the second section SC2 have been met, and the second control processing for the game section for the current game (Figure 36) is terminated. On the other hand, if the end preparation complete flag is set to "1" (step S1903: YES), processing is executed to terminate the second section SC2 and transition to the first section SC1 (steps S1915 to S1916). As a result, the second section SC2 ends when the game following the game in which the pseudo bonus state ST4 ended ends.

Next, the AT processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 42. The AT processing is executed in step S1506 of the response processing at the end of play (Figure 32). As already explained, the response processing at the end of play is executed after all rotations of reels 32L, 32M, and 32R in one game have stopped, and therefore the AT processing is also executed after all rotations of reels 32L, 32M, and 32R in one game have stopped.

In the AT processing, first, it is determined whether the value of the bet number setting counter 74b in the main RAM 74 is "3" to determine whether the number of bets for the current game is "3" (step S2501). If the number of bets for the current game is "2" (step S2501: NO), the processing from step S2502 onwards is not executed. As a result, even if a game with a bet number of "2" is played in the AT state ST5, the number of remaining games to be continued in the AT state ST5 is not subtracted.

Note that when in the CB state (first CB state ST2 or second CB state ST3), the AT processing (Figure 42) itself is not executed, so even if the CB state starts in the middle of the AT state ST5, the number of games played in the CB state is not treated as the number of games played in the AT state ST5. Therefore, even if the CB state is transitioned to in the middle of the AT state ST5, after the CB state ends, the AT state ST5 will resume from the state of the remaining number of games continued immediately before transitioning to the CB state.

If the number of bets on this game is "3" (step S2501: YES), the value of the AT continuation counter 74u in the main RAM 74 is decremented by 1 (step S2502), and it is determined whether the value of the AT continuation counter 74u after decrementing by 1 is "0" (step S2503). If the value of the AT continuation counter 74u is "0" (step S2503: YES), it is determined whether either the first ending flag 76b or the second ending flag 76c in the game status area 77 of the main RAM 74 is set to "1" (step S2504). If the values of the first ending flag 76b and the second ending flag 76c are both "0" (step S2504: NO), the AT state flag 77d in the game status area 77 of the main RAM 74 is cleared to "0" (step S2505). This allows the main MPU 72 to determine that the AT state ST5 has ended.

Then, similar to step S1710 of the first control process (FIG. 34) of the game area already described, the release game number lottery process is executed by calling a subroutine program called the release game number lottery process with a CALL command (step S2506). As already described, the release game number is the number of games required until a transition to pseudo bonus state ST4 occurs if the transition to pseudo bonus state ST4 is not won in the transition lottery process (step S2112). When the subroutine program called the release game number lottery process is called with a CALL command in step S2506, return address information for returning to the process of step S2507, which is the next process after step S2506, is stored in the stack area of the main RAM 74. The contents of the release game number lottery process have already been described with reference to the flowchart in FIG. 35(b).

As already explained, in the release game number lottery process (Figure 35(b)), if the value of the counter to be judged is "4", the release game number of "50" is judged; if the value of the counter to be judged is "3", the release game number of "200" is judged; and if the value of the counter to be judged is "2", the release game number of "400" is judged. If the release game numbers of "50", "200", and "400" are not won, the release game number of "600" is won. When the release game number lottery process (Figure 35(b)) called in step S2506 is terminated, the process returns to step S2507, which is the process next to step S2506, based on the return address information stored in the stack area of the main RAM 74. In the release game number lottery process (FIG. 35(b)) in step S2506, if the release game number of "50" is won, the process returns to step S2507 with the value of the counter to be judged being "4", if the release game number of "200" is won, the process returns to step S2507 with the value of the counter to be judged being "3", if the release game number of "400" is won, the process returns to step S2507 with the value of the counter to be judged being "2", and if the release game number of "600" is won, the process returns to step S2507 with the value of the counter to be judged being "1".

After executing the release game number lottery process in step S2506, steps S2507 to S2508 execute the same processes as steps S1711 to S1712 of the first control process (Figure 34) for the game area already described. Specifically, first, the release game number counter setting process is executed (step S2507). As already described, the release game number counter is a counter used by the main MPU 72 to determine the remaining number of release games, which is the number of games required to transition to the pseudo-bonus state ST4 when none of the first to third transition confirmation flags in the main RAM 74 are set to "1." In the release game number counter setting process, the release game number lottery table 73c (Figure 35(a)) is referenced, and the release game number corresponding to the value of the counter to be determined is set in the release game number counter in the main RAM 74. Specifically, if the value of the counter to be determined is "4", the release game number counter is set to "50", if the value of the counter to be determined is "3", the release game number counter is set to "200", if the value of the counter to be determined is "2", the release game number counter is set to "400", and if the value of the counter to be determined is "1", the release game number counter is set to "600". After that, the value of the counter to be determined is cleared to "0" (step S2508), and the AT processing ends.

If either the first ending flag 76b or the second ending flag 76c in the game section area 76 of the main RAM 74 is set to "1" (step S2504: YES), the process for setting the end preparation state ST6 is executed (step S2509). In the process for setting the end preparation state ST6, the AT state flag 77d in the game state area 77 of the main RAM 74 is cleared to "0." In addition, in the process for setting the end preparation state ST6, the end preparation state flag 77e in the game state area 77 of the main RAM 74 is set to "1." The end preparation state flag 77e is a flag used by the main MPU 72 to identify the end preparation state ST6. Setting the end preparation state flag 77e to "1" changes the game state to the end preparation state ST6. Thereafter, the end preparation complete flag in the main RAM 74 is cleared to "0" (step S2510), and the AT process is terminated. As already explained, the end preparation completion flag is a flag that allows the main MPU 72 to determine whether one game has been played in the end preparation state ST6.

As already explained, in the end preparation state ST6, if a positive judgment is made in step S1902 of the second control processing for the game section (Figure 36) and the end preparation complete flag is not set to "1" (step S1903: NO), the end preparation complete flag is set to "1" and processing is executed to determine whether the ending conditions for the second section SC2 have been met, and the second control processing for the game section for the current game (Figure 36) is terminated. On the other hand, if the end preparation complete flag is set to "1" (step S1903: YES), processing is executed to terminate the second section SC2 and transition to the first section SC1 (steps S1915 to S1916). As a result, the second section SC2 will end when the game following the game in which the AT state ST5 ended ends.

Next, before explaining the start-up surcharge processing executed by the main MPU 72, we will explain the first surcharge lottery table 73d and the second surcharge lottery table 73e stored in the main ROM 73. The first surcharge lottery table 73d and the second surcharge lottery table 73e are set as lottery tables to be referenced in the surcharge lottery. Figure 43(a) is an explanatory diagram for explaining the contents of the first surcharge lottery table 73d, and Figure 43(b) is an explanatory diagram for explaining the contents of the second surcharge lottery table 73e.

As shown in Figures 43(a) and (b), the first additional lottery table 73d and the second additional lottery table 73e are set with the numbers of additional games set to 10, 20, and 50. As shown in Figure 43(a), when the additional lottery process is executed using the first additional lottery table 73d as the reference lottery table, 10 games are selected with a probability of 1/16, 20 games are selected with a probability of 1/16, 50 games are selected with a probability of 1/16, and there is a 13/16 probability of a miss. As shown in Figure 43(b), when the additional lottery process is executed using the second additional lottery table 73e as the reference lottery table, 10 games are selected with a probability of 1/8, 20 games are selected with a probability of 1/8, 50 games are selected with a probability of 1/8, and there is a 5/8 probability of a miss. In this way, the probability of winning 10, 20, or 50 additional games on the second additional lottery table 73e is set higher than the probability of winning 10, 20, or 50 additional games on the first additional lottery table 73d. The second additional lottery table 73e is a lottery table that is more advantageous to players than the first additional lottery table 73d.

Next, the start-up bonus processing executed by the main MPU 72 will be explained with reference to the flowchart in Figure 43 (c). As already explained, the start-up bonus processing is executed in step S2310 of the advantageous state processing at the start of the game (Figure 40).

In the start-up bonus process, it is first determined whether or not one of the index values IV = 11 to 15 has been won in the lottery process for the role in the current game (Figure 18) (step S2601). In step S2601, a positive determination is made if the value of the index value counter 74f in the main RAM 74 is any of "11" to "15," and a negative determination is made if the value of the index value counter 74f is any of "0" to "10" or "16" to "17." If a negative determination is made in step S2601, the start-up bonus process is terminated without executing the process for executing the bonus lottery (the process from step S2602 onwards). The bonus lottery is held on the condition that one of the index values IV = 11 to 15 has been won in the lottery process for the role (Figure 18). This start-up bonus processing (FIG. 43(c)) is called in step S2310 of the advantageous state processing at the start of the game (FIG. 40), so when the start-up bonus processing (FIG. 43(c)) is completed, the process returns to step S2311, which is the next step after step S2310. The processing from step S2311 onwards will be described later.

If the index value IV is one of 11 to 15 (step S2601: YES), steps S2602 to S2604 are executed to execute the additional lottery, steps S1802 to S1807 of the cancellation game number lottery process (FIG. 35(b)), and steps S2311 to S2313 of the advantageous state process at the start of the game (FIG. 40) are executed. In the additional lottery, it is determined whether or not to add to the remaining number of continued games in AT state ST5, and if the remaining number of continued games in AT state ST5 is to be added, the number of added games is selected from 10 games, 20 games, and 50 games.

Specifically, the first bonus lottery table 73d stored in the main ROM 73 is first set as the lottery table to be referenced in the bonus lottery (step S2602). Then, it is determined whether the index value IV = 14 or 15 is selected in the lottery process for the current game (Figure 18) (step S2603). If the index value IV = 14 or 15 is selected (step S2603: YES), the lottery table to be referenced in the bonus lottery is changed to the second bonus lottery table 73e stored in the main ROM 73 (step S2604). On the other hand, if the index value IV = 11 to 13 is selected in the lottery process for the current game (Figure 18) (step S2603: NO), the lottery table to be referenced in the bonus lottery is not changed. As already explained, the second bonus lottery table 73e is a lottery table that is more advantageous to the player than the first bonus lottery table 73d. If the index value IV set to the first chance replay (IV=14) or second chance replay (IV=15) is selected in the role lottery process (FIG. 18), a lottery table (second additional lottery table 73e) that is more advantageous to the player than if the index value IV set to the first watermelon (IV=11), second watermelon (IV=12), or cherry (IV=13) is selected is selected.

If a negative judgment is made in step S2603, or if the processing of step S2604 is performed, a jump command is issued to jump to the program address for executing the processing of step S1802 of the release game number lottery processing (Figure 35 (b)), and the lottery execution processing is executed in steps S1802 to S1807. When a jump command is issued to jump to the program address for executing the processing of step S1802, return address information is not stored in the stack area of the main RAM 74. Therefore, a jump is made to the program address for executing the processing of step S1802 with return address information for returning to the processing of step S2311 of the advantageous state processing at the start of the game (Figure 40) stored in the stack area of the main RAM 74.

Next, we will explain the case where the lottery execution process (steps S1802 to S1807) is executed after a negative judgment is made in step S2603 of the start-up addition process (Figure 43 (c)), or after the processing of step S2604 is performed.

In step S1802, one byte of lottery numerical information is obtained from the lottery counter, which is periodically updated in the main RAM 74, and the obtained lottery numerical information is set in the random number setting counter in the main RAM 74. As already explained, the lottery numerical information is numerical information indicating an integer between "0" and "255," and the random number setting counter is a counter in which the lottery numerical information is set, and consists of one byte.

Then, the judgment target counter in the main RAM 74 is set to "4" (step S1803). Then, the judgment value set in the referenced lottery table (first additional lottery table 73d or second additional lottery table 73e) is added to the value of the random number setting counter (step S1804). As shown in Figure 43(a), the first additional lottery table 73d has a judgment value of "16" set. If the referenced lottery table is the first additional lottery table 73d, in step S1804, the judgment value of "16" is added to the value of the random number setting counter. As shown in Figure 43(b), the second additional lottery table 73e has a judgment value of "32". If the referenced lottery table is the second additional lottery table 73e, in step S1804, the judgment value of "32" is added to the value of the random number setting counter.

Then, it is determined whether the value of the random number setting counter after adding the determination value in step S1804 exceeds "255" (step S1805). If the value of the random number setting counter does not exceed "255" (step S1805: NO), the value of the counter to be determined is decremented by 1 (step S1806). As already explained, the processing of steps S1804 to S1807 is repeatedly executed until a positive determination is made in step S1805 or step S1807. The number of additional games to be determined is updated in the order of 10 games → 20 games → 50 games each time the value of the counter to be determined is decremented by 1 in step S1806.

Then, in step S1806, it is determined whether the value of the counter to be determined after decrementing by 1 is "1" (step S1807). If a negative determination is made in step S1807, the process proceeds to step S1804, and steps S1804 to S1807 are repeatedly executed until a positive determination is made in step S1805 or step S1807. If a positive determination is made in step S1805 or step S1807, the process returns to the advantageous state processing at the start of the game (Figure 40) by executing the "RET" command, based on the return address information stored in the stack area of the main RAM 74. Specifically, the process returns to step S2311, which is the processing following step S2310, in which the CALL command is set to call the start-time bonus processing (Figure 40).

In this way, the start-time addition process (FIG. 43(c)) is called in step S2310 of the advantageous state process at the start of the game (FIG. 40), and if a positive judgment is made in step S2601 of the AT state process (FIG. 43(c)), after executing the processing from step S2602 onwards, the process jumps to step S1802 of the release game number lottery process (FIG. 35(b)) without executing a command to return from the subroutine. Therefore, by executing a command to return from the subroutine after a positive judgment is made in step S1805 or step S1807 of the release game number lottery process (FIG. 35(b)), the process returns to processing S2311, which is the next step after step S2310 of the advantageous state process at the start of the game (FIG. 40), in which a CALL command is set to call the start-time addition process (FIG. 43(c)).

If the additional number of games of "10" is won, the processing returns to step S2311 with the value of the counter to be judged being "4"; if the additional number of games of "20" is won, the processing returns to step S2311 with the value of the counter to be judged being "3"; if the additional number of games of "50" is won, the processing returns to step S2311 with the value of the counter to be judged being "2"; if neither additional number of games is won, the processing returns to step S2311 with the value of the counter to be judged being "1". As already explained, even if a positive judgment is made in step S2601 of the processing for additional games at the start (Figure 43(c)), the processing also returns to step S2311 in the processing for advantageous state at the start of the game (Figure 40); in this case, the processing returns to step S2311 with the value of the counter to be judged being "0".

Here, we will explain the processing of steps S2311 to S2313 of the advantageous state processing at the start of the game (Figure 40). In step S2311, it is determined whether the value of the counter to be determined in the main RAM 74 is 1 or greater. If the value of the counter to be determined is "0" (step S2311: NO), that is, if the winning combination lottery processing (Figure 18) did not result in a win with index value IV = 11 to 15, the advantageous state processing at the start of the game is terminated without executing the processing of steps S2312 to S2313.

If the value of the counter to be determined is "1" or greater (step S2311: YES), an addition process for the number of continued games is executed (step S2312). In this addition process for the number of continued games, the number of added games corresponding to the value of the counter to be determined is determined in the referenced lottery table, and the determined number of added games is added to the value of the AT continuation counter 74u in the main RAM 74. In step S2312, whether the first added lottery table 73d or the second added lottery table 73e is selected, if the value of the counter to be determined is "4," "10" is added as the number of added games to the AT continuation counter 74u; if the value of the counter to be determined is "3," "20" is added as the number of added games to the AT continuation counter 74u; and if the value of the counter to be determined is "2," "50" is added as the number of added games to the AT continuation counter 74u. On the other hand, if the value of the counter to be judged is "1", i.e., if the draw for the additional bonus is unsuccessful, the number of additional games is not added to the AT continuation counter 74u. The value of the counter to be judged is then cleared to "0" (step S2313), and the advantageous state processing at the start of this game (FIG. 40) is terminated.

Next, the command output processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 44. The command output processing is executed in step S210 of the timer interrupt processing (Figure 11).

In the command output process, if the power restoration command flag in the main RAM 74 is set to "1" (step S2701: YES), a power restoration command transmission process is executed to send a power restoration command to the production-side MPU 92 (step S2702). The power restoration command is set with data from the first CB winning data area 74j and the second CB winning data area 74k in the main RAM 74. As already explained, the first CB winning data area 74j is an area for storing first CB winning data indicating that a first CB role has been won, and the second CB winning data area 74k is an area for storing second CB winning data. If the power restoration command contains first CB winning data, the production-side MPU 92 determines that the power restoration process was executed with the first CB winning data stored in the main RAM 74. If the power restoration command contains second CB winning data, the production-side MPU 92 determines that the power restoration process was executed with the second CB winning data stored in the main RAM 74. Furthermore, if the power restoration command does not include the first CB winning data or the second CB winning data, it is determined that the power restoration process was executed in a state where the first CB winning data or the second CB winning data was not contained in the main RAM 74. After that, the power restoration command flag is cleared to "0" (step S2703), and this command output process is terminated.

If, after a negative determination in step S2701, the winning result command flag in the main RAM 74 is set to "1" (step S2704: YES), a winning result command transmission process is executed to transmit a winning result command to the presentation MPU 92 (step S2705). As previously explained, the winning result command contains data stored in the first CB winning data area 74j, the second CB winning data area 74k, and the winning data area 78 in the main RAM 74. Based on the data set in the winning result command, the presentation MPU 92 determines whether or not a win has been achieved, and if a win has been achieved, determines the type of win. The presentation MPU 92 then controls the illumination of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63 to produce a presentation corresponding to the information obtained from the winning result command. The winning result command flag is then cleared to "0" (step S2706), and the command output process ends.

If, after a negative determination is made in step S2704, the start command flag in the main RAM 74 is set to "1" (step S2707: YES), or if the end command flag in the main RAM 74 is set to "1" (step S2707: NO, step S2708: YES), a common command transmission process is executed (step S2709), and the command output process is terminated. In the common command transmission process in step S2709, if the start command flag is set to "1", a start command is transmitted to the production side MPU 92, and if the end command is set to "1", a end command is transmitted to the production side MPU 92.

In the command output process (Figure 44), if the power recovery command flag is set to "1", the power recovery command transmission process (step S2702) is executed regardless of the state of other command flags (start command flag, winning result command flag, and end command flag).

In each game, the period from when the start command flag is set to "1" to when the win result command flag is set to "1" is longer than the acceleration period of reels 32L, 32M, and 32R (specifically, approximately 300 milliseconds). Furthermore, the acceleration period of reels 32L, 32M, and 32R is longer than the interrupt cycle (1.49 milliseconds) of the timer interrupt process (Figure 11). Therefore, in each game, the start command is sent before the win result command.

In each game, the end command flag is set to "1" after the winning result command flag is set to "1." If the command output process (Figure 44) is executed between the time the winning result command flag is set to "1" and the time the end command flag is set to "1," the winning result command is sent before the end command. Also, if the command output process is executed while the winning result command flag and the end command flag are set to "1," the winning result command sending process is executed, and the common command sending process is executed in the next command output process executed approximately 1.49 milliseconds later. In this way, in each game, commands are sent to the production side MPU 92 in the following order: start command → winning result command → end command.

<Configuration for sending commands>
Next, the configuration for transmitting various commands from the main MPU 72 to the performance MPU 92 will be described.

Figure 45 is an explanatory diagram illustrating the electrical configuration of the main control board 71 and performance control board 91 for transmitting commands from the main MPU 72 to the performance MPU 92. As already explained, the main control board 71 is provided with a transmission circuit 85, and the performance control board 91 is provided with a reception circuit 87. As shown in Figure 45, the transmission circuit 85 is provided with a transmission standby buffer 112 in which commands to be sent to the performance MPU 92 are set. The transmission standby buffer 112 is a ring buffer consisting of 32 bytes. Of the commands sent from the main MPU 72 to the performance MPU 92, the commands with the largest data volumes are the start command and the end command, and the data volume of the start command and the end command set in the transmission standby buffer 112 is 15 bytes.

When it is time to set a new command while there is a command currently being sent in the transmission standby buffer 112, the new command is set in the transmission standby buffer 112 in an area following the area where the command currently being sent is set, and the transmission standby state is reached. Also, when it is time to set a new command while there are commands currently being sent and commands waiting to be sent in the transmission standby buffer 112, the new command is set in the transmission standby buffer 112 in an area following the area where the command waiting to be sent is set, and the transmission standby state is reached. The transmission circuit 85 transmits the commands set in the transmission standby buffer 112 to the reception circuit 87 in the order in which they were set in the transmission standby buffer 112. The data capacity of the transmission standby buffer 112 is set to be larger than the total data capacity of multiple commands that may be present in the transmission standby buffer 112 at the same time. Therefore, when each command is set in the transmission standby buffer 112, there is enough free space to set that command.

The transmission circuit 85 is provided with a transmission buffer 111 in which data to be sent to the production-side MPU 92 is set. The transmission buffer 111 consists of one byte. Commands set in the transmission standby buffer 112 are set in the transmission buffer 111 one byte at a time and sent to the production-side MPU 92. Hereinafter, in this specification, one byte of data included in a command is also referred to as a frame FRm (where m is an integer between 1 and 15).

When a command is set in the transmission standby buffer 112, the transmission circuit 85 first sets the first byte of data (first frame FR1) of the multiple bytes of data (multiple frames FRm) included in the command in the transmission buffer 111 and transmits this byte of data to the production-side MPU 92. The transmission circuit 85 then sets the next byte of data (second frame FR2) after the first byte of data included in the command in the transmission buffer 111 and transmits this byte of data to the production-side MPU 92. In this way, the transmission circuit 85 repeatedly transmits the byte of data set in the transmission buffer 111 to the production-side MPU 92 while sequentially updating the byte of data (frame FRm) set in the transmission buffer 111 from the multiple bytes of data (multiple frames FRm) included in the command until transmission of the entire command stored in the transmission standby buffer 112 is completed.

As shown in FIG. 45, the receiving circuit 87 is provided with a receiving buffer 121 in which one byte of data received from the transmitting circuit 85 is stored, and a post-receiving standby buffer 122 in which commands received from the main MPU 72 are stored. The post-receiving standby buffer 122 is a ring buffer consisting of 32 bytes, similar to the transmission standby buffer 112 in the transmitting circuit 85 described above. The storage capacity of the post-receiving standby buffer 122 is set to be larger than the total amount of data for multiple commands that may be present in the post-receiving standby buffer 122 at the same time.

The production-side RAM 94 is provided with a command storage buffer 126 in which commands received from the main-side MPU 72 are stored in a state that makes them usable by the production-side MPU 92. The command storage buffer 126 is a 32-byte ring buffer. After receiving a command, the command stored in the standby buffer 122 is transferred to the command storage buffer 126, where it is saved until it is used by the production-side MPU 92. The storage capacity of the command storage buffer 126 is set to be larger than the total amount of data for multiple commands that can exist in the command storage buffer 126 at the same time.

The receiving circuit 87 sets the 1 byte of data (frame FRm) stored in the receiving buffer 121 in the waiting buffer 122 after receiving it, and clears the receiving buffer 121 to "0" to make it ready to receive the next 1 byte of data. It then outputs a ready-to-receive signal to the transmitting circuit 85. When the transmitting circuit 85 receives the ready-to-receive signal and data is set in the transmitting buffer 111, it transmits the 1 byte of data set in the transmitting buffer 111 to the receiving circuit 87.

A header HD is set in the first frame FR1, which is the first frame of a command sent from the master MPU 72 to the production MPU 92, and a footer FT is set in the last frame FRm of the command. Figure 46(a) is an explanatory diagram illustrating the data structure of the header HD, and Figure 46(b) is an explanatory diagram illustrating the data structure of the footer FT.

As shown in Figure 46 (a), the header HD is one byte of data consisting of bits 0 to 7. Bits 0 to 7 of the header HD contain command identification data that allows the type of command to be identified. The production-side MPU 92 identifies the type of command received based on the command identification data.

Of bits 0 through 7 of each frame FRm included in the command, bit 7 is the most significant bit, and bit 0 is the least significant bit. Bit 7, the most significant bit of the header HD (the most significant bit of the command identification data), is the header identification bit that identifies the header HD. Regardless of the command type, the header identification bit is always set to "1." Of the frames FRm (1-byte data) included in the command, only the frame FRm with its most significant bit (bit 7) set to "1" is a header HD. The receiving circuit 87 determines whether a frame FRm stored in the receiving buffer 121 is a header HD by determining whether its most significant bit is set to "1." When the receiving circuit 87 receives multiple commands from the transmitting circuit 85, it can determine the delimiter positions of these commands based on the position of the header HD. It is also possible to configure the header identification bit to be set to "0," and for frames FRm other than the header HD to have their most significant bit (bit 7) set to "1." In this configuration, the receiving circuit 87 can determine whether a frame FRm stored in the receiving buffer 121 is a header HD by determining whether the most significant bit of the frame FRm is set to "0."

As shown in Figure 46(b), the footer FT is one byte of data consisting of bits 0 through 7. The most significant bit of the footer FT is set to "0," making it possible to distinguish between the header HD and the footer FT based on the state of the most significant bit. Bits 0 through 6 of the footer FT contain identification number data for the slot machine 10. The identification number data is numerical information expressed by seven bits other than "0," specifically, any of the values "1" through "127." The receiving circuit 87 determines whether a frame FRm (one byte of data) stored in the receiving buffer 121 is a footer FT by determining whether identification number data is set in the lowest seven bits (bits 0 through 6). The receiving circuit 87 determines the start position of the command by recognizing the header HD, and the end position of the command by recognizing the footer FT. The receiving circuit 87 then recognizes a series of data starting with the header HD and ending with the footer FT as a single command.

The command stored in the transmission standby buffer 112 and the frame FRm (1 byte of data) stored in the transmission buffer 111 are cleared when a partial clear process (step S105) or a full clear process (step S106) is executed in the main process (Figure 10).

As explained above, the most significant bit of the frames FRm other than the header HD included in the command must be set to "0." When the main MPU 72 sends a command (specifically, a start command or end command) containing data whose most significant bit can be set to "1," it sets a top-level aggregated frame SF that aggregates only the most significant bit data of the frames FRm in the command, and sets the most significant bit of those frames to "0." This allows the most significant bit of the frames FRm other than the header HD to have a value of "0," while data whose most significant bit can be set to "1" can be set in the command. The most significant bit of the top-level aggregated frame SF is set to "0," making it possible to distinguish between the header HD and the top-level aggregated frame SF based on the state of the most significant bit.

Figure 46 (c) is an explanatory diagram illustrating the setting in the main RAM 74 of the memory areas set for the start command, end command, and power recovery command. As shown in Figure 46 (c), the main RAM 74 has many 1-byte memory areas, and each 1-byte memory area has a 2-byte address set in one-to-one correspondence. The counter and area in which data is set for the start command are the same as the counter and area in which data is set for the end command. The counter and area in which data is set for the start command and end command are set in the continuous address range of "0001H" to "000DH" in the main RAM 74.

Specifically, the AT continuation counter 74u is set in the memory area corresponding to addresses "0001H" to "0002H." As previously explained, the AT continuation counter 74u is a counter used by the master MPU 72 to determine the remaining number of games to be played in AT state ST5. The AT continuation counter 74u consists of two bytes. The lowermost byte of the AT continuation counter 74u (hereinafter also referred to as the "lower area of the AT continuation counter 74u") is set in the memory area corresponding to address "0001H," while the uppermost byte of the AT continuation counter 74u (hereinafter also referred to as the "upper area of the AT continuation counter 74u") is set in the memory area corresponding to address "0002H." In this specification, a "B" suffixed to a number indicates that the number is expressed in binary. The remaining number of games in AT state ST5 stored in the AT continuation counter 74u may be "128" (binary notation: "0000000010000000B") or greater. For this reason, the value of the most significant bit in the lower area of the AT continuation counter 74u may be "1," and the value of the most significant bit may be "0." For example, if the number of games remaining in AT state ST5 stored in the AT continuation counter 74u is "128," the value of the most significant bit in the lower area of the AT continuation counter 74u will be "1." If the number of games remaining in AT state ST5 stored in the AT continuation counter 74u is "127" (binary notation: "0000000001111111B"), the value of the most significant bit in the lower area of the AT continuation counter 74u will be "0." In this way, the lower area of the AT continuation counter 74u is a storage area in which the most significant bit can be set to "1."

As already explained, if the ending condition is met, that is, the number of games played since the start of the second section SC2 reaches the upper limit of 1,500 games as the second section SC2 continues, the AT state ST5 ends with the game where the ending condition was met, even if the game is in the middle of the AT state ST5, and the second section SC2 ends, transitioning to the first section SC1 and normal game state ST1. Also, as already explained, the number of additional games selected in the additional lottery is 10, 20, or 50. Therefore, the number of remaining games in the AT state ST5 stored in the AT continuation counter 74u will never be 32,768 (1,000,000,000,000,000B in binary notation), i.e., the most significant bit in the upper area of the AT continuation counter 74u will never be set to 1. The value of the most significant bit in the upper area of the AT duration counter 74u is "0", and the upper area of the AT duration counter 74u is an area where the most significant bit is not set to "1".

The continued game counter 74r is set in the memory area corresponding to addresses "0003H" through "0004H." As previously explained, the continued game counter 74r is a counter used by the master MPU 72 to determine the number of games played since the start of the second section SC2 when the second section SC2 is continued without a first section SC1 in between. The continued game counter 74r consists of two bytes. The lowest byte of the continued game counter 74r (hereinafter referred to as the "lower area of the continued game counter 74r") is set in the memory area corresponding to address "0003H," while the highest byte of the continued game counter 74r (hereinafter referred to as the "upper area of the continued game counter 74r") is set in the memory area corresponding to address "0004H." The number of games played stored in the continued game counter 74r may be "128" (binary notation: "0000000010000000B") or more. Therefore, the value of the most significant bit in the lower area of the continued game counter 74r may be "1" and the value of the most significant bit may be "0." For example, if the number of games played since the start of the second section SC2 stored in the continued game counter 74r is "128," the value of the most significant bit in the lower area of the continued game counter 74r will be "1." Conversely, if the number of games played since the start of the second section SC2 stored in the continued game counter 74r is "127" ("0000000001111111B" in binary), the value of the most significant bit in the lower area of the continued game counter 74r will be "0." In this way, the lower area of the continued game counter 74r is a storage area in which the most significant bit can be set to "1."

As described above, if the ending condition is met in which the number of games played since the start of second section SC2 reaches the upper limit of 1500 as the second section SC2 continues, second section SC2 ends with the game for which the ending condition is met, and the first section SC1 begins. Therefore, the number of games played stored in continued game counter 74r will never exceed 32768 (1000000000000000B in binary), meaning that the most significant bit in the upper area of continued game counter 74r will never be set to 1. The value of the most significant bit in the upper area of continued game counter 74r is 0, and the upper area of continued game counter 74r is an area in which the most significant bit is not set to 1.

The total acquisition counter 74s is set in the memory area corresponding to addresses "0005H" to "0006H." As already explained, the total acquisition counter 74s is a counter used by the main MPU 72 to determine the limited total net increase in gaming media from the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between. The total acquisition counter 74s consists of two bytes. The lowest byte of the total acquisition counter 74s (hereinafter referred to as the "lower area of the total acquisition counter 74s") is set in the memory area corresponding to address "0005H," and the highest byte of the total acquisition counter 74s (hereinafter referred to as the "upper area of the total acquisition counter 74s") is set in the memory area corresponding to address "0006H." The limited total net increase in gaming media stored in the total acquisition counter 74s may be "128" ("0000000010000000B" in binary) or greater. Therefore, the most significant bit in the lower area of the total acquisition counter 74s may be "1" and the most significant bit may be "0." For example, if the limited total net increase in gaming media stored in the total acquisition counter 74s is "128," the most significant bit in the lower area of the total acquisition counter 74s will be "1." Furthermore, if the limited total net increase in gaming media stored in the total acquisition counter 74s is "127" ("000000000111111B" in binary), the most significant bit in the lower area of the total acquisition counter 74s will be "0." In this way, the lower area of the total acquisition counter 74s is a storage area in which the most significant bit can be set to "1."

As already explained, if the limited total net increase in gaming media since the start of second section SC2 reaches the upper limit net increase of 2400 as the second section SC2 continues, second section SC2 ends and transitions to first section SC1. Therefore, the number of times the game has been played stored in total wins counter 74s will never exceed 32768 (1000000000000000B in binary), meaning that the most significant bit in the upper area of total wins counter 74s will never be set to 1. The value of the most significant bit in the upper area of total wins counter 74s is 0, and the upper area of total wins counter 74s is an area where the most significant bit is not set to 1.

As described above, the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total acquisition counter 74s are memory areas in which the most significant bit may be "1" or "0" depending on the number of games stored in the AT continuation counter 74u, the number of games stored in the continued game count counter 74r, or the limited total net increase in gaming media stored in the total acquisition counter 74s, and are memory areas in which the most significant bit can be set to "1".

The memory area corresponding to address "0007H" is set to the top-level aggregation area 74v. The top-level aggregation area 74v is a memory area where the data of the top-level aggregation frame set in the start command or end command is set when the main MPU 72 sends the start command or end command to the performance MPU 92. The top-level aggregation area 74v consists of 1 byte. Bits 0 to 5 of the top-level aggregation area 74v aggregate the data "0" or "1" stored in the top bit (bit 7) of the memory area corresponding to addresses "0001H" to "0006H". Specifically, the most significant bit of data in the lower area of the AT continuation counter 74u set to the address "0001H" is set to the 0th bit of the highest aggregation area 74v, the most significant bit of data in the upper area of the AT continuation counter 74u set to the address "0002H" is set to the 1st bit of the highest aggregation area 74v, the most significant bit of data in the lower area of the continuing game number counter 74r set to the address "0003H" is set to the 2nd bit of the highest aggregation area 74v, the most significant bit of data in the upper area of the continuing game number counter 74r set to the address "0004H" is set to the 3rd bit of the highest aggregation area 74v, the most significant bit of data in the lower area of the total winning number counter 74s set to the address "0005H" is set to the 4th bit of the highest aggregation area 74v, and the most significant bit of data in the upper area of the total winning number counter 74s set to the address "0006H" is set to the 5th bit of the highest aggregation area 74v. As a result, the most significant bit data in these six areas is aggregated in the most significant aggregation area 74v. The sixth and seventh bits in the most significant aggregation area 74v are unused bits, and the values of these sixth and seventh bits are "0". The most significant aggregation area 74v is a storage area in which the most significant bit (seventh bit) is not set to "1".

In this way, the "0" or "1" data stored in the most significant bits of the six memory areas set in the contiguous address range of "0001H" to "0006H," including the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total win count counter 74s, where a "1" can be set in the most significant bit, is aggregated into a one-byte memory area (top-level aggregation area 74v). Therefore, compared to a configuration in which two or more bytes of memory area are set in the main RAM 74 to set the "0" or "1" data stored in the most significant bits of these six memory areas, the data capacity of the memory area provided in the main RAM 74 to set the "0" or "1" data stored in the most significant bits of these six memory areas is reduced.

Six memory areas, including the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total win count counter 74s, which can have their most significant bit set to "1," are set in a contiguous address range from "0001H" to "0006H." This simplifies the processing configuration for specifying the address range of the memory area for which the data "0" or "1" stored in the most significant bit is set in the top aggregation area 74v.

As described above, the lower area of the AT continuation counter 74u, the lower area of the continued game counter 74r, and the lower area of the total wins counter 74s are areas where the most significant bit can be set to "1," while the upper area of the AT continuation counter 74u, the upper area of the continued game counter 74r, and the upper area of the total wins counter 74s are areas where the most significant bit cannot be set to "1." In the main RAM 74, the lower and upper areas of the AT continuation counter 74u are set to a continuous address range ("0001H" to "0002H"). Furthermore, the lower and upper areas of the continued game counter 74r are set to a continuous address range ("0003H" to "0004H"), and the lower and upper areas of the total wins counter 74s are set to a continuous address range ("0005H" to "0006H"). The configuration aggregates the "0" or "1" data stored in the most significant bits of six memory areas set in the contiguous address range of "0001H" to "0006H," including the upper area of the AT continuation counter 74u, the upper area of the continued game count counter 74r, and the upper area of the total win counter 74s, into the most significant aggregation area 74v. Therefore, compared to a configuration in which only memory areas where a "1" can be set in the most significant bit are set in a contiguous address range in the main RAM 74, this configuration prevents the processing configuration from becoming complicated for determining the number of games remaining in the AT state ST5, the number of games played since the start of the second interval SC2 when the second interval SC2 is continued without the first interval SC1 in between, and the limited total net increase in gaming media since the start of the second interval SC2 when the second interval SC2 is continued without the first interval SC1 in between.

The bet number setting counter 74b is set in the memory area corresponding to the address "0008H." As already explained, the numerical information set in the bet number setting counter 74b is either "2" or "3." Therefore, the value of the most significant bit of the bet number setting counter 74b is always "0," and the bet number setting counter 74b is a memory area where the most significant bit is not set to "1." The stop order type counter 74m is set in the memory area corresponding to the address "0009H." As already explained, in this embodiment, the numerical information set in the stop order type counter 74m is a stop order type number between "1" and "9" or "0." Therefore, the value of the most significant bit of the stop order type counter 74m is always "0," and the stop order type counter 74m is a memory area where the most significant bit is not set to "1." The game status area 77 is set in the memory area corresponding to the address "000AH." As already explained, the first CB state flag 77a, the second CB state flag 77b, the pseudo bonus state flag 77c, the AT state flag 77d, the end preparation state flag 77e, and the AT transition confirmation flag 77f are set in the 0th to 5th bits of the game status area 77, and the 6th to 7th bits of the game status area 77 are unused bits. The value of the most significant bit of the game status area 77 is always "0," and the game status area 77 is a memory area in which "1" is not set in the most significant bit. The memory area corresponding to the address "000BH" is set to the game section area 76. As already explained, the second section flag 76a, the first ending flag 76b, and the second ending flag 76c are set in the 0th to 2nd bits of the game section area 76, and the 3rd to 7th bits of the game section area 76 are unused bits. The value of the most significant bit in the play interval area 76 is always "0," and the play interval area 76 is a memory area in which the most significant bit is not set to "1." A pseudo bonus continuation counter 74t is set in the memory area corresponding to the address "000CH." As already explained, the pseudo bonus continuation counter 74t is a counter used by the host MPU 72 to determine the remaining number of continued games in the pseudo bonus state ST4. The pseudo bonus continuation counter 74t is set to "50" when the pseudo bonus state ST4 is a big bonus, and is set to "20" when the pseudo bonus state ST4 is a regular bonus. The maximum remaining number of continued games set in the pseudo bonus continuation counter 74t is "50" (binary notation: "00110010B"), and the value of the most significant bit in the pseudo bonus continuation counter 74t is always "0." In this way, the pseudo bonus continuation counter 74t is a memory area in which the most significant bit is not set to "1." The award number counter 74e is set in the memory area corresponding to the address "000DH". As already explained, the number of award game media set in the award number counter 74e is "1", "2", "5", or "15", and the maximum number of award game media set in the award number counter 74e is "15" ("00001111B" in binary). The value of the most significant bit in the award number counter 74e is always "0", and the award number counter 74e is a memory area where "1" is never set in the most significant bit.

In this way, the bet number setting counter 74b, stop order type counter 74m, game status area 77, game interval area 76, pseudo bonus continuation counter 74t, and award number counter 74e, which are set in the address range of "0008H" to "000DH," are memory areas in which "1" is not set in the most significant bit. The main RAM 74 does not have a memory area for aggregating the data in the most significant bit of these bet number setting counter 74b, stop order type counter 74m, game status area 77, game interval area 76, pseudo bonus continuation counter 74t, and award number counter 74e.

Among the memory areas of the main RAM 74 where data is set in the start command and the end command, a top-order aggregation area 74v is provided to aggregate the most significant bit data in areas where the most significant bit (seventh bit) can be set to "1," while no memory area is provided to aggregate the most significant bit data in memory areas of the main RAM 74 where the most significant bit is not set to "1." This configuration limits the number of memory areas (top-order aggregation areas 74v) set in the main RAM 74 for aggregating most significant bit data, while allowing the most significant bit data in areas where the most significant bit can be set to "1" to be set in the start command and the end command.

The memory areas in which data is set for start and end commands are set in the continuous address range of "0001H" to "000DH" in the main RAM 74, which simplifies the processing configuration for specifying the address range of the memory area in which data is set for start commands and the processing configuration for specifying the address range of the memory area in which data is set for end commands.

As shown in FIG. 46(c), of the data set in the start command, the only data used by the presentation side MPU 92 at the start of the game are the AT continuation counter 74u, the top-level aggregation area 74v, the bet number setting counter 74b, the stop order type counter 74m, and the game status area 77. The data for the number of continued games counter 74r, the total number of wins counter 74s, the game section area 76, the pseudo bonus continuation counter 74t, and the number of awarded counter 74e are data that are not used by the presentation side MPU 92 at the start of the game. Furthermore, of the data set in the end command, the only data used by the presentation side MPU 92 at the end of the game are the number of continued games counter 74r, the total number of wins counter 74s, the top-level aggregation area 74v, the game status area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the number of awarded counter 74e. The data for the AT continuation counter 74u, the bet number setting counter 74b, and the stop order type counter 74m are data that are not used by the presentation side MPU 92 at the end of the game.

In this way, only a portion of the memory area of the main RAM 74 (specifically, the top-level aggregation area 74v and the game status area 77) in which data used by the presentation MPU 92 at the start of the game is stored is shared with the memory area of the main RAM 74 in which data used by the presentation MPU 92 at the end of the game is stored. In this configuration, by making the memory areas in which data is set for the start command and end command the memory areas in the main RAM 74 in which data used by the presentation MPU 92 at the start and end of the game are stored, it is possible to set the memory areas in which data is set for the start command and the memory areas in which data is set for the end command in consecutive address ranges of the main RAM 74.

In the main RAM 74, the address range of the memory area where the data set for the start command is stored (address range "0001H" to "000DH") is the same as the address range of the memory area where the data set for the end command is stored (address range "0001H" to "000DH"), so the processing configuration for sending the start command and the processing configuration for sending the end command can be standardized. This allows the data size of the program for sending the start command and the end command in the main ROM 73 to be reduced.

As mentioned above, the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s are counters whose most significant bit in the lower area can be set to "1." The data of the AT continuation counter 74u is data used by the presentation side MPU 92 at the start of the game, but is not data used by the presentation side MPU 92 at the end of the game. Furthermore, the data of the number of continued games counter 74r and the total number of wins counter 74s is data used by the presentation side MPU 92 at the end of the game, but is not data used by the presentation side MPU 92 at the start of the game. If only the data to be used by the presentation-side MPU 92 at the start of the game were set in the start command, and only the data to be used by the presentation-side MPU 92 at the end of the game were set in the end command, it would be necessary to provide a memory area in the main RAM 74 for setting the most significant bit data in the lower and upper areas of the continued game counter 74r and the most significant bit data in the lower and upper areas of the total wins counter 74s, separate from a memory area for setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u. In contrast, by setting the data of the AT continuation counter 74u, the continued game count counter 74r, and the total wins counter 74s in the start command and the end command, it is possible to use only one memory area, the most significant aggregation area 74v, for setting the data of "0" or "1" stored in the most significant bit of the lower and upper areas of the AT continuation counter 74u, the continued game count counter 74r, and the total wins counter 74s. This reduces the data capacity of the main RAM 74 for setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game number counter 74r, and the lower and upper areas of the total win number counter 74s.

As already explained, data stored in the first CB winning data area 74j and the second CB winning data area 74k in the main RAM 74 is set in the power recovery command. As shown in FIG. 46(c), in the main RAM 74, the first CB winning data area 74j is set in the memory area corresponding to the address "000EH," and the second CB winning data area 74k is set in the memory area corresponding to the address "000FH." In this way, the memory areas storing data set in commands other than the start command and the end command are also set in memory areas corresponding to consecutive addresses in the main RAM 74. This simplifies the process of setting the data stored in the first CB winning data area 74j and the second CB winning data area 74k in the power recovery command.

The first CB winning data area 74j and second CB winning data area 74k, where data is set in the power recovery command, are memory areas in which a "1" is never set in the most significant bit. As shown in Figure 46 (c), the main RAM 74 does not have a memory area for aggregating the most significant bit data in the first CB winning data area 74j and second CB winning data area 74k. Therefore, the data capacity of the main RAM 74 is reduced compared to a configuration in which a memory area for aggregating the most significant bit data in the first CB winning data area 74j and second CB winning data area 74k is provided.

Next, we will explain what happens when the receiving circuit 87 receives a start command. Figure 47(a) is an explanatory diagram illustrating the data structure of the start command and end command, Figure 47(b) is an explanatory diagram illustrating the data structure of the converted start command, and Figure 47(c) is an explanatory diagram illustrating the data structure of the converted end command. Also, Figure 48(a) is an explanatory diagram illustrating the conversion mode of the start command, and Figure 48(b) is an explanatory diagram illustrating the conversion mode of the end command.

Commands received by the receiving circuit 87 from the main MPU 72 are stored in the post-reception standby buffer 122. As shown in FIG. 45, the production RAM 94 has a pre-conversion area 124 and a post-conversion area 125. The pre-conversion area 124 is a storage area in which a start command or end command for which the top-level aggregated frame SF is set is stored, and the post-conversion area 125 is a storage area for converting the start command or end command stored in the pre-conversion area 124 into a post-conversion start command or post-conversion end command.

As shown in Figures 48(a) and (b), the pre-conversion area 124 includes the first through fifteenth areas RA1 to RA15, while the post-conversion area 125 includes the first through tenth areas RB1 to RB10. These areas RA1 to RA15 and RB1 to RB10 are storage areas consisting of 1 byte. In the performance-side RAM 94, the first through fifteenth areas RA1 to RA15 of the pre-conversion area 124 are set in the consecutive address range of "α+1" to "α+15," while the first through tenth areas RB1 to RB10 of the post-conversion area 125 are set in the consecutive address range of "β+1" to "β+10" in the performance-side RAM 94.

The total data capacity of the first to fifteenth areas RA1 to RA15 in the pre-conversion area 124 is 15 bytes, and the total data capacity of the first to tenth areas RB1 to RB10 in the post-conversion area 125 is 10 bytes. As already explained, the maximum data capacity of one command received by the receiving circuit 87 from the transmitting circuit 85 is 15 bytes. Furthermore, the data capacity of the post-conversion start command is 7 bytes, and the data capacity of the post-conversion end command is 10 bytes.

The data structure of an end command is the same as that of a start command. Below, the data structure of start and end commands is explained using the start command as an example.

As shown in Figure 47 (a), the first frame FR1 located at the beginning of the start command contains header HD data indicating that it is a start command, bits 0 to 6 of the second frame FR2 contain data from bits 0 to 6 in the lower area of the AT continuation counter 74u, bits 0 to 6 of the third frame FR3 contain data from bits 0 to 6 in the upper area of the AT continuation counter 74u, and bits 0 to 6 of the fourth frame FR4 contain data from bits 0 to 6 in the lower area of the continued game number counter 74r. Six bits of data are set, with bits 0 to 6 of the fifth frame FR5 being set to the data of the 0th to 6th bits of the upper area of the continued game counter 74r, bits 0 to 6 of the sixth frame FR6 being set to the data of the 0th to 6th bits of the lower area of the total wins counter 74s, bits 0 to 6 of the seventh frame FR7 being set to the data of the 0th to 6th bits of the upper area of the total wins counter 74s, and data of the highest aggregation area 74v being set in the eighth frame FR8. As previously explained, the data of the highest aggregation area 74v is data in which the "0" or "1" data stored in the highest bits of the lower area of the AT continuation counter 74u, the upper area of the AT continuation counter 74u, the lower area of the continued game counter 74r, the upper area of the continued game counter 74r, the lower area of the total wins counter 74s, and the upper area of the total wins counter 74s are aggregated in bits 0 to 5 of the highest aggregation area 74v.

The ninth frame FR9 of the start command contains data for the bet number setting counter 74b, the tenth frame FR10 contains data for the stop order type counter 74m, the eleventh frame FR11 contains data for the game status area 77, the twelfth frame FR12 contains data for the game section area 76, the thirteenth frame FR13 contains data for the pseudo bonus continuation counter 74t, the fourteenth frame FR14 contains data for the award number counter 74e, and the fifteenth frame FR15 contains data for the footer FT.

When the production-side MPU 92 converts a start command into a converted start command, it first sets the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) included in the start command to the most significant bits of the second to seventh frames FR2 to FR7 corresponding to those bits 0 to 5. It then generates the converted start command by excluding frames 1 to 15 included in the start command that contain data not used at the start of the game, from among frames FR1 to FR15, and the eighth frame FR8, which contains data from the top-level aggregated area 74v. Specifically, the following are excluded: the fourth and fifth frames FR4-FR5, in which data for the continued game counter 74r is set; the sixth and seventh frames FR6-FR7, in which data for the total wins counter 74s is set; the eighth frame FR8, in which data for the top-level aggregation area 74v is set; the twelfth frame FR12, in which data for the play section area 76 is set; the thirteenth frame FR13, in which data for the pseudo bonus continuation counter 74t is set; and the fourteenth frame FR14, in which data for the awards counter 74e is set.

As shown in Figure 47 (b), the converted start command contains data from the header HD, data from the lower area of the AT continuation counter 74u, data from the upper area of the AT continuation counter 74u, data from the bet number setting counter 74b, data from the stop order type counter 74m, data from the game status area 77, and data from the footer FT. The data from the lower area of the AT continuation counter 74u set in the converted start command is data from bits 0 to 7, including the most significant bit of the lower area of the AT continuation counter 74u, and the data from the upper area of the AT continuation counter 74u set in the converted start command is data from bits 0 to 7, including the most significant bit of the upper area of the AT continuation counter 74u.

When converting an end command into a converted end command, the production-side MPU 92 first sets the "0" or "1" data set in bits 0 through 5 of the top-level aggregate frame SF (eighth frame FR8) included in the end command to the most significant bits of the second through seventh frames FR2 through FR7 corresponding to those bits 0 through 5. The production-side MPU 92 then generates the converted end command by excluding frames 1 through 15 included in the end command that contain data that will not be used at the end of the game, as well as the eighth frame FR8, which contains data for the top-level aggregate area 74v. Specifically, the production-side MPU 92 excludes the second and third frames FR2 through FR3, which contain data for the AT continuation counter 74u; the eighth frame FR8, which contains data for the top-level aggregate area 74v; the ninth frame FR9, which contains data for the bet number setting counter 74b; and the tenth frame FR10, which contains data for the stop order type counter 74m.

As shown in Figure 47 (c), the converted end command includes data for the header HD, data for the lower area of the continued game count counter 74r, data for the upper area of the continued game count counter 74r, data for the lower area of the total number of wins counter 74s, data for the upper area of the total number of wins counter 74s, data for the game status area 77, data for the game section area 76, data for the pseudo bonus continuation counter 74t, data for the number of awards counter 74e, and data for the footer FT. The data for the lower area of the continued game count counter 74r set in the converted end command is data from bits 0 to 7, including the most significant bit, of the lower area of the continued game count counter 74r, and the data for the upper area of the continued game count counter 74r set in the converted end command is data from bits 0 to 7, including the most significant bit, of the upper area of the continued game count counter 74r. In addition, the data in the lower area of the total acquisition number counter 74s set in the post-conversion end command is data from bits 0 to 7, including the most significant bit, in the lower area of the total acquisition number counter 74s, and the data in the upper area of the total acquisition number counter 74s set in the post-conversion end command is data from bits 0 to 7, including the most significant bit, in the upper area of the total acquisition number counter 74s.

The production-side ROM 93 stores a start conversion table that is referenced when converting a start command into a converted start command, and an end conversion table that is referenced when converting an end command into a converted end command. The start conversion table contains information about frames to exclude when converting a start command into a converted start command. The end conversion table contains information about frames to exclude when converting an end command into a converted end command. The production-side MPU 92 converts start commands into converted start commands based on the start conversion table, and converts end commands into converted end commands based on the end conversion table.

The production-side MPU 92 sets the start command or end command stored in the post-reception standby buffer 122 to the first through fifteenth areas RA1 through RA15 of the pre-conversion area 124. As a result, as shown in Figures 48(a) and (b), the top-level aggregated frame SF is set to the eighth area RA8 of the pre-conversion area 124. The data "0" or "1" set in the 0th through 5th bits of the top-level aggregated frame SF is then set to the most significant bit (7th bit) of the 2nd through 7th areas RA2 through RA7 in the pre-conversion area 124, in which the 2nd through 7th frames FR2 through FR7 corresponding to the 0th through 5th bits are set. Specifically, the 0th bit of data in the 8th area RA8 is set to the most significant bit of the second area RA2, the 1st bit of data in the 8th area RA8 is set to the most significant bit of the third area RA3, the 2nd bit of data in the 8th area RA8 is set to the most significant bit of the fourth area RA4, the 3rd bit of data in the 8th area RA8 is set to the most significant bit of the fifth area RA5, the 4th bit of data in the 8th area RA8 is set to the most significant bit of the sixth area RA6, and the 5th bit of data in the 8th area RA8 is set to the most significant bit of the seventh area RA7.

In a start command or end command, the frames in which the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) is set as the most significant bit are the consecutive second to seventh frames FR2 to FR7. This simplifies the processing configuration for the production-side MPU 92 to specify the frames in which the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF is set as the most significant bit.

After that, if a start command is set in the pre-conversion area 124, the first through fifteenth frames FR1 through FR15 set in the first through fifteenth areas RA1 through RA15 of the pre-conversion area 124, excluding the frames to be excluded, are transferred to the first through seventh areas RA1 through RA7 of the post-conversion area 125 based on the start conversion table. Specifically, as shown in FIG. 48(a), data from the first area RA1, second area RA2, third area RA3, ninth area RA9, tenth area RA10, eleventh area RA11, and fifteenth area RA15 of the pre-conversion area 124 is transferred to the first area RB1, second area RB2, third area RA3, fourth area RB4, fifth area RB5, sixth area RB6, and seventh area RB7 of the post-conversion area 125. This allows the start command to be converted into a post-conversion start command.

If an end command is set in the pre-conversion area 124, based on the end conversion table, frames other than the frames to be excluded among the first to fifteenth frames FR1 to FR15 set in the first to fifteenth areas RA1 to RA15 of the pre-conversion area 124 are transferred to the first to tenth areas RA1 to RA10 of the post-conversion area 125. Specifically, as shown in FIG. 48(b), data from the first area RA1, fourth area RA4, fifth area RA5, sixth area RA6, seventh area RA7, eleventh area RA11, twelfth area RA12, thirteenth area RA13, fourteenth area RA14, and fifteenth area RA15 of the pre-conversion area 124 is transferred to the first area RB1, second area RB2, third area RB3, fourth area RB4, fifth area RB5, sixth area RB6, seventh area RB7, eighth area RB8, ninth area RB9, and tenth area RB10 of the post-conversion area 125. This allows the end command to be converted into a converted end command.

The production-side MPU 92 stores the post-conversion start command or post-conversion end command in the command storage buffer 126. This makes the post-conversion start command or post-conversion end command available to the production-side MPU 92. The post-conversion start command and post-conversion end command are commands for which the most significant bit of the frame FRm other than the header HD can also be set to "1". The production-side MPU 92 executes the performance based on the commands stored in the command storage buffer 126.

In this way, the production side MPU 92 converts the start command received from the main side MPU 72 into a converted start command, and converts the end command received from the main side MPU 72 into a converted end command. When converting a start command or end command received from the main side MPU 72 into a converted start command or a converted end command, the production side MPU 92 sets the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) to the most significant bit in the second to seventh frames FR2 to FR7 corresponding to those bits 0 to 5. This allows the production side MPU 92 to use a converted start command or a converted end command in which the most significant bit in frames other than the header HD can also be set to "1," while the most significant bit in frames other than the header HD included in the start command or end command sent from the main side MPU 72 to the production side MPU 92 is set to "0."

Only a portion of the first through fifteenth frames FR1 through FR15 included in the start command are set in the converted start command. This allows the master MPU 72 to send a start command that includes data other than that used by the production MPU 92 at the start of the game, while reducing the data size of the converted start command stored in the command storage buffer 126 and used by the production MPU 92. Furthermore, only a portion of the first through fifteenth frames FR1 through FR15 included in the end command are set in the converted end command. This allows the master MPU 72 to send a end command that includes data other than that used by the production MPU 92 at the end of the game, while reducing the data size of the converted end command stored in the command storage buffer 126 and used by the production MPU 92. This reduces the data size of the command storage buffer 126.

Of the first to fifteenth frames FR1 to FR15 included in the start command, the frames that the production side MPU 92 sets in the converted start command are different from the frames of the first to fifteenth frames FR1 to FR15 included in the end command that the production side MPU 92 sets in the converted end command. Therefore, in a configuration in which the address range of the memory area of the main RAM 74 storing the data set in the start command sent from the main MPU 72 to the production MPU 92 at the start of the game is the same as the address range of the memory area of the main RAM 74 storing the data set in the end command sent from the main MPU 72 to the production MPU 92 at the end of the game, the production MPU 92 can use the converted start command at the start of the game, in which only the data required by the production MPU 92 at the start of the game is set between the header HD and footer FT, and at the end of the game, the production MPU 92 can use the converted end command in which only the data required by the production MPU 92 at the end of the game is set between the header HD and footer FT.

When the main MPU 72 sends a command that contains only data whose most significant bit is never set to "1" (for example, a power restoration command or a winning result command), it does not aggregate the most significant bit data in the frame FRm included in that command. As already explained, the power restoration command sets data from the first CB winning data area 74j and the second CB winning data area 74k. These first CB winning data area 74j and second CB winning data area 74k are memory areas whose most significant bit is never set to "1". The main RAM 74 does not have a memory area for aggregating the most significant bit data of the first CB winning data area 74j and the second CB winning data area 74k, and the main MPU 72 does not perform processing to aggregate the most significant bit data of the first CB winning data area 74j and the second CB winning data area 74k when sending a power restoration command.

In this way, when sending a command that contains only data that will never have a "1" set in the most significant bit, the data in the most significant bit of the frame included in that command is not aggregated. Therefore, compared to a configuration that generates a top-level aggregated frame SF even for commands that do not contain data that can have a "1" set in the most significant bit, the processing configuration for sending that command in the main MPU 72 can be simplified, and the processing load on the main MPU 72 for sending that command can be reduced.

If the production-side MPU 92 determines that the highest-level aggregated frame SF is not set for a command stored in the post-reception standby buffer 122, it transfers the command as is to the command storage buffer 126. Specifically, if a power-recovery command is stored in the post-reception standby buffer 122, it transfers the power-recovery command as is to the command storage buffer 126, and if a winning result command is stored in the post-reception standby buffer 122, it transfers the winning result command as is to the command storage buffer 126. Therefore, compared to a configuration in which the highest-level aggregated frame SF is generated even for commands that only have a frame FRm set, which does not have the highest bit set to "1", it is possible to eliminate the need for processing to convert the command after it is received, thereby reducing the processing load on the production-side MPU 92.

As shown in FIG. 45, the receiving circuit 87 is provided with a first write pointer 127 and a read pointer 128. The first write pointer 127 and read pointer 128 consist of one byte, and store integers between "0" and "31" in them. The first write pointer 127 is used by the receiving circuit 87 to determine the write destination area in the post-reception standby buffer 122. When one byte of data is stored in the receiving buffer 121, the receiving circuit 87 determines the write destination area in the post-reception standby buffer 122 based on the value of the first write pointer 127, and writes the one byte of data stored in the receiving buffer 121 to the determined area. The receiving circuit 87 then increments the value of the first write pointer 127 by one. If the value of the first write pointer 127 after the increment exceeds the maximum value of "31," the value of the first write pointer 127 is cleared to "0." The receiving buffer 121 is then cleared to "0."

The read pointer 128 is used by the production side MPU 92 to determine the beginning of a command stored in the post-reception standby buffer 122. When one or more commands are stored in the post-reception standby buffer 122, the production side MPU 92 determines the beginning of the command based on the value of the read pointer 128, and determines the end of that command based on the footer FT data of that command. When multiple commands are stored in the post-reception standby buffer 122, the beginning of the command that was first stored in the post-reception standby buffer 122 is determined based on the value of the read pointer 128, and the end of that command is determined based on the footer FT data of that command.

If the command whose beginning and end are identified based on the value of the read pointer 128 is a start command or an end command, the production-side MPU 92 sets the start command or end command in the pre-conversion area 124 of the production-side RAM 94. The production-side MPU 92 then clears to "0" the area in the post-reception standby buffer 122 where the start command or end command was stored, and updates the value of the read pointer 128 to a value corresponding to the area next to the area where the end of the start command or end command (footer FT data) was stored. Furthermore, if the production-side MPU 92 determines that the start and end command is a command other than a start command or end command (e.g., a winning result command or a return command), it stores the command in the command storage buffer 126 of the production-side RAM 94. The production-side MPU 92 then clears to "0" the area in the post-reception standby buffer 122 where the command was stored, and updates the value of the read pointer 128 to a value corresponding to the area next to the area where the end of the command (footer FT data) was stored. This allows commands received from the main MPU 72 to be made available to the production MPU 92 in the order they were stored in the reception standby buffer 122, i.e., in the order they were received from the main MPU 72.

Figure 49(a) is an explanatory diagram illustrating the content that the production-side MPU 92 grasps based on the converted start command, and Figure 49(b) is an explanatory diagram illustrating the content that the production-side MPU 92 grasps based on the converted end command.

As shown in Figure 49 (a), the presentation side MPU 92 determines that it is time to start a game based on the header HD data set in the received command indicating that it is a start command. Based on the data in the bet number setting counter 74b set in the start command, the presentation side MPU 92 determines whether the number of bets in the currently started game is "3" or "2." Based on the data in the stop order type counter 74m set in the start command, the presentation side MPU 92 determines whether or not the image display device 63 is notifying the stop order of reels 32L, 32M, and 32R, and, if notifying the stop order of reels 32L, 32M, and 32R, determines the type of stop order to be notified. Based on the data in the AT transition confirmation flag 77f included in the data in the game status area 77 set in the start command, the presentation side MPU 92 determines that an AT state win has occurred. Based on the data of the AT continuation counter 74u set in the start command, the presentation side MPU 92 determines whether or not an addition has been made to the remaining number of continued games in the AT state ST5, and determines the number of added games if such an addition has occurred.

As shown in FIG. 49(b), the presentation side MPU 92 determines that a transition to the first CB state ST2 has occurred and that the first CB state ST2 has ended based on the data of the first CB state flag 77a included in the data of the game status area 77 set in the end command. The presentation side MPU 92 determines that a transition to the second CB state ST3 has occurred and that the second CB state ST3 has ended based on the data of the second CB state flag 77b included in the data of the game status area 77 set in the end command. The presentation side MPU 92 determines that the pseudo bonus state ST4 has started and that the pseudo bonus state ST4 has ended based on the data of the pseudo bonus state flag 77c included in the data of the game status area 77 set in the end command. The presentation side MPU 92 determines that a transition to the AT state ST5 has occurred and that the AT state ST5 has ended based on the data of the AT state flag 77d included in the data of the game status area 77 set in the end command. The presentation-side MPU 92 determines whether the second section SC2 has started and ended based on the data of the second section flag 76a included in the data of the play section area 76 set in the end command. The presentation-side MPU 92 determines whether or not to start the presentation of the ending period based on the data of the first ending flag 76b included in the data of the play section area 76 set in the end command, and if the presentation of the ending period is to start, determines the number of games remaining until the ending condition is met based on the data of the continued game number counter 74r set in the end command. The presentation-side MPU 92 determines whether or not to start the presentation of the ending period based on the data of the second ending flag 76c included in the data of the play section area 76 set in the end command, and if the presentation of the ending period is to start, determines the limited total net increase in the number of game media remaining until the ending condition is met based on the data of the total acquisition number counter 74s set in the end command. The production side MPU 92 determines whether or not gaming media were awarded in the currently completed game based on the data of the award number counter 74e set in the end command, and if gaming media were awarded in the currently completed game, determines the number of gaming media awarded.

Next, the common command transmission process executed by the main MPU 72 will be described with reference to the flowchart in Figure 50. As already explained, the common command transmission process is executed in step S2709 when the start command flag in the main RAM 74 is set to "1" (step S2707: YES) or when the end command flag in the main RAM 74 is set to "1" (step S2708: YES) during the command output process (Figure 44). As already explained, the start command flag is set to "1" in step S1107 of the lottery result response process (Figure 25) when a game starts, and the end command flag is set to "1" in step S1508 of the game end response process (Figure 32) when the game ends.

The common command transmission process first performs the top-level aggregation process (step S2801). In the top-level aggregation process, data of "1" or "0" stored in the most significant bit (bit 7) of the memory area set at addresses "0001H" to "0006H" in the main RAM 74 is transferred to bits 0 to 5 of the top-level aggregation area 74v. The address range of the memory area in the main RAM 74 that is the transfer source in the top-level aggregation process (step S2801) is the consecutive address range of "0001H" to "0006H". The top-level aggregation process targets the storage areas set at addresses "0001H" through "0006H" as the transfer range. The process of transferring "0" or "1" stored in the most significant bit of the source storage area to the destination bit, updating the source storage area, and updating the destination bit is repeated until the "0" or "1" stored in the most significant bit of all storage areas included in the transfer range is set to bits 0 through 5 of the top-level aggregation area 74v. The address of the source storage area is updated in the order "0001H" → "0002H" → ... → "0005H" → "0006H," and the destination bits in the top-level aggregation area 74v are updated in the order of bit 0 → bit 1 → ... → bit 4 → bit 5.

Figure 51 is a flowchart showing the top-level aggregation process (step S2801) executed by the main MPU 72.

In the top-level aggregation process, the address of the top-level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 provided in the main RAM 74 (step S2901). The transfer destination counter 115 is a counter that allows the main MPU 72 to grasp the data transfer destination. The transfer destination counter 115 is set with the address (2 bytes) of the storage area to which the data is to be transferred. By setting the address of the top-level aggregation area 74v in the transfer destination counter 115 in step S2901, the top-level aggregation area 74v can be set as the storage area to which the data is to be transferred.

Then, the top-level aggregation area 74v is cleared to "0" (step S2902), and the value of the bit designation counter 117 provided in the main RAM 74 is cleared to "0" (step S2903). The bit designation counter 117 is a counter that allows the main MPU 72 to grasp the destination bit in the destination storage area (top-level aggregation area 74v). Numerical information between "0" and "5" is set in the bit designation counter 117. By clearing the value of the bit designation counter 117 to "0" in step S2903, the 0th bit of the top-level aggregation area 74v can be set as the destination bit.

Then, "0001H," the start address of the address range from "0001H" to "0006H," which is the transfer target range for the top-level aggregation process, is set in the transfer source counter 116 provided in the main RAM 74 (step S2904). The transfer source counter 116 is a counter that allows the main MPU 72 to grasp the address (2 bytes) of the transfer source memory area. By setting "0001H" in the transfer source counter 116 in step S2904, the lower area of the AT continuation counter 74u, which is set to the address "0001H," can be set as the transfer source memory area. Then, "6" is set as the number of data transfers in the transfer count counter 114 (see Figure 45) provided in the main RAM 74 (step S2905). This "6" is the number of memory areas present in the transfer target range. The transfer count counter 114 is a counter that allows the main MPU 72 to keep track of the number of times data stored in a memory area included in the transfer range in the common command transmission process is transferred to the transmission standby buffer 112, and the number of times data stored in the most significant bit of a memory area included in the transfer range in the top-level aggregation process is transferred to the top-level aggregation area 74v. The transfer count counter 114 consists of 1 byte.

Then, the most significant bit of data in the source storage area is transferred to the destination bit (step S2906). As already explained, the main MPU 72 identifies the source storage area based on the address stored in the source counter 116, and identifies the destination bit based on the address stored in the destination counter 115 and the value of the bit designation counter 117. Then, the value of the transfer count counter 114 is decremented by 1 (step S2907), and it is determined whether the value of the transfer count counter 114 after decrementing by 1 is "0" (step S2908).

If a negative determination is made in step S2908, the value of the transfer source counter 116 in the main RAM 74 is incremented by 1 to update the address of the transfer source storage area (step S2909). Steps S2906 to S2910 are repeated until a positive determination is made in step S2908, and in step S2909, the address of the transfer source storage area is updated in the order of "0001H" → "0002H" → ... → "0005H" → "0006H". Then, the value of the bit designation counter 117 in the main RAM 74 is incremented by 1 to update the transfer destination bit in the top-level aggregation area 74v (step S2910). In step S2910, the transfer destination bit in the top-level aggregation area 74v is updated in the order of bit 0 → bit 1 → ... → bit 4 → bit 5.

Then, proceed to step S2906, and repeat steps S2906 to S2910 until a positive determination is made in step S2908. This allows the data "0" or "1" stored in the most significant bits of all storage areas included in the transfer target range to be set to bits 0 to 5 of the top-level aggregation area 74v. If a positive determination is made in step S2908, this top-level aggregation process ends.

In this way, the transfer target range in the top-level aggregation process (Figure 51) is the consecutive address range of "0001H" to "0006H" in the main RAM 74. By repeatedly executing the process of incrementing the value of the transfer source counter 116 in the main RAM 74 by 1 (processing of step S2909), the transfer source memory area can be updated sequentially. This simplifies the processing configuration for sequentially updating the transfer source memory area.

Since the transfer target range in the top-level aggregation process (Figure 51) is the consecutive address range from "0001H" to "0006H" in the main RAM 74, the transfer target range can be specified by setting the start address of the transfer target range, "0001H," in the transfer source counter 116 in step S2904, and setting the number of transfers, "6," in the transfer count counter 114 in step S2905. This simplifies the processing configuration for specifying the transfer target range.

Returning to the explanation of the common command transmission process (Figure 50), after the top-level aggregation process (Figure 51) is executed in step S2801, the area in the transmission standby buffer 112 to which data is to be written is determined by determining the value of the write pointer 113 (see Figure 45) provided in the transmission circuit 85 (step S2802). Data is set in the write pointer 113 to identify the area in the transmission standby buffer 112 to which data is to be written. Specifically, one of numerical values "0" to "31" is set in the write pointer 113.

Then, it is determined whether the start command flag in the main RAM 74 is set to "1" (step S2803). If the start command flag is set to "1" (step S2803: YES), i.e., if it is the start of the game, the data in the header HD corresponding to the start command stored in the main ROM 73 is set to the write destination area in the transmission standby buffer 112 identified in step S2802 (step S2804), and the start command flag is cleared to "0" (step S2805). On the other hand, if the start command flag is not set to "1" (step S2803: NO), i.e., if it is the end of the game, the data in the header HD corresponding to the end command stored in the main ROM 73 is set to the write destination area in the transmission standby buffer 112 identified in step S2802 (step S2806), and the end command flag in the main RAM 74 is cleared to "0" (step S2807).

If the processing of step S2805 or step S2807 is performed, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S2808). In step S2808, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

Then, in the main RAM 74, the start address of the transfer target range for transferring data to the transmission standby buffer 112 when sending a start command or an end command is set in the transfer source counter 116 of the main RAM 74 (step S2809). The transfer target range in the common command transmission process (Figure 50) is the address range of "0001H" to "000DH". By setting the address of "0001H" in the transfer source counter 116 in step S2809, the lower area of the AT continuation counter 74u can be set as the transfer source memory area. Then, "13" is set in the transfer count counter 114 of the main RAM 74 (step S2810). This "13" is the number of 1-byte memory areas included in the address range of "0001H" to "000DH", which is the transfer target range.

Then, the destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 is identified, and the source memory area is identified based on the address set in the source counter 116, and the data from the source memory area is transferred to the destination area (step S2811). Then, the most significant bit (bit 7) of the destination area is set to "0" (step S2812). This sets the most significant bit of the second through fourteenth frames FR2 through FR14 to "0," and makes it possible to distinguish between the header HD and the second through fourteenth frames FR2 through FR14 based on the value of the most significant bit.

Then, as in step S2808, the value of the write pointer 113 is updated (step S2813). Specifically, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31," the write pointer 113 is cleared to "0." The value of the transfer count counter 114 in the primary RAM 74 is then decremented by 1 (step S2814), and it is determined whether the value of the transfer count counter 114 after the decrement is "0" (step S2815).

If a negative determination is made in step S2815, i.e., if the transfer of data stored in the 1-byte storage area included in the transfer target range to the transmission standby buffer 112 has not been completed, the value of the transfer source counter 116 is incremented by 1 to update the address of the storage area of the transfer source (step S2816). The processing of steps S2811 to S2816 is repeated until a positive determination is made in step S2815, and in step S2816, the address of the storage area that will be the transfer source area is updated in the following order: "0001H" → "0002H" → "0003H" → ... → "000CH" → "000DH".

Then, proceed to step S2811, and repeat steps S2811 through S2816 until a positive determination is made in step S2815. This allows data stored in all 1-byte storage areas included in the transfer target range (address range "0001H" to "000DH") to be set in the transmission standby buffer 112. If a positive determination is made in step S2815, the footer FT data stored in the main ROM 73 is set to the write destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S2817). Then, as in steps S2808 and S2813, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S2818), and the common command transmission process ends. In step S2818, the value of the write pointer 113 is incremented by 1. If the value of the write pointer 113 after the increment exceeds the maximum value of "31," the write pointer 113 is cleared to "0."

In this way, the transfer target range in the common command transmission process (Figure 50) is the consecutive address range of "0001H" to "000DH" in the main RAM 74. By repeatedly executing the process of incrementing the value of the transfer source counter 116 in the main RAM 74 by 1 (processing of step S2816), the transfer source memory area can be updated sequentially. This simplifies the processing configuration for sequentially updating the transfer source memory area.

Since the transfer target range in the common command transmission process (Figure 50) is the consecutive address range from "0001H" to "000DH" in the main RAM 74, the transfer target range can be specified by setting the start address of the transfer target range, "0001H," in the transfer source counter 116 in step S2809, and setting the number of transfers, "13," in the transfer count counter 114 in step S2810. This simplifies the processing configuration for specifying the transfer target range.

Next, the command reception response processing executed by the production-side MPU 92 will be described with reference to the flowchart in Figure 52. The command reception response processing is repeatedly executed by the production-side MPU 92 at relatively short intervals (for example, every 4 milliseconds).

The command reception response process first determines whether header HD data is set in the post-reception standby buffer 122 in the receiving circuit 87 (step S3001). As already explained, of the frames FRm (1 byte of data) included in the various commands received by the production side MPU 92 from the master side MPU 72, the only frame FRm with a "1" set in the most significant bit (seventh bit) is the first frame FR1 in which header HD data is set. In step S3001, a positive determination is made if a frame FRm with a "1" set in the most significant bit exists.

If header HD data has been set in the post-reception standby buffer 122 (step S3001: YES), it is determined whether footer FT data has been set in the post-reception standby buffer 122, thereby determining whether reception of one or more commands has finished (step S3002). If a negative determination is made in step S3002, this means that a command is being received, and the command reception response process is terminated without executing the processes from step S3003 onwards.

If footer FT data is present in the post-reception standby buffer 122 (step S3002: YES), the start and end of the command to be moved from the post-reception standby buffer 122 to the pre-conversion area 124 of the production-side RAM 94 or the command storage buffer 126 (hereinafter also referred to as the "command to be moved") are identified (step S3003). In step S3003, the start of the command to be moved is identified based on the value of the read pointer 128 in the post-reception standby buffer 122, and the end of the command to be moved is identified based on the footer FT data of the command to be moved. If multiple commands are stored in the post-reception standby buffer 122, the first of the multiple commands stored in the post-reception standby buffer 122 is the command to be moved based on the value of the read pointer 128.

Then, it is determined whether start command header HD data is set for the command to be moved identified in step S3003 (step S3004). If start command header HD data is set (step S3004: YES), this means that the command to be moved is a start command, and the start reception correspondence table is read from the production-side ROM 93 (step S3005). On the other hand, if start command header HD data is not set (step S3004: NO), it is determined whether end command header HD data is set for the command to be moved identified in step S3003 (step S3006). If end command header HD data is set (step S3006: YES), this means that the command to be moved is an end command, and the end reception correspondence table is read from the production-side ROM 93 (step S3007).

If step S3005 or step S3007 has been performed, the highest-level setting process is executed (step S3008). In this highest-level setting process, the "0" or "1" data set in bits 0 to 5 of the highest-level aggregated frame SF (eighth frame FR8) contained in the received start command or end command is set to the highest-level bits of the second to seventh frames FR2 to FR7 corresponding to those bits 0 to 5. Figure 53 is a flowchart showing the highest-level setting process (step S3008).

In the top-level setting process, the first through fifteenth frames FR1 through FR15 of the start command or end command to be moved in the post-reception standby buffer 122 are first set to the first through fifteenth areas RA1 through RA15 of the pre-conversion area 124 in the production-side RAM 94 (step S3101). As a result, whether a start command is set in the pre-conversion area 124 or an end command is set in the pre-conversion area 124, the top-level aggregated frame SF is set to the eighth area RA8.

Then, a process for clearing the post-reception standby buffer 122 is executed (step S3102). In this process, the area in the post-reception standby buffer 122 in which the start command or end command, which is the command to be moved, was stored is cleared to "0". This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. The value of the read pointer 128 in the post-reception standby buffer 122 is then updated to a value corresponding to the storage area next to the storage area in which the end of the start command or end command (footer FT data) was stored (step S3103).

Then, the address (2 bytes) of the eighth area RA8 of the pre-conversion area 124 is set in the production side transfer source counter provided in the production side RAM 94 (step S3104). The production side transfer source counter is a counter that allows the production side MPU 92 to grasp the memory area from which data is being transferred. The production side transfer source counter consists of 2 bytes. By setting the address of the eighth area RA8 in the production side transfer source counter in step S3104, the eighth area RA8 in which the top-level aggregated frame SF is set can be used as the memory area from which data is being transferred.

Then, the value of the presentation-side bit designation counter provided in the presentation-side RAM 94 is cleared to "0" (step S3105). The presentation-side bit designation counter is a counter that allows the presentation-side MPU 92 to grasp the source bit in the source memory area. The presentation-side bit designation counter consists of 1 byte. By clearing the value of the presentation-side bit designation counter to "0" in step S3105, the 0th bit in the 8th area RA8 of the pre-conversion area 124 can be set as the source bit.

Then, the address (2 bytes) of the second area RA2 in the pre-conversion area 124 is set in the production side transfer destination counter provided in the production side RAM 94 (step S3106). The production side transfer destination counter is a counter that allows the production side MPU 92 to grasp the transfer destination memory area. The production side transfer destination counter consists of 1 byte. By setting the address of the second area RA2 in the production side transfer destination counter in step S3106, the second area RA2 can be used as the transfer destination memory area.

Then, the "0" or "1" data stored in the source bit is transferred to the most significant bit in the destination storage area (step S3107). As already explained, the production side MPU 92 identifies the source storage area based on the address stored in the production side source counter, and identifies the source bit in the source storage area based on the value of the production side bit designation counter. The production side MPU 92 also identifies the destination storage area based on the address stored in the production side destination counter.

Then, by determining whether the value of the production-side bit designation counter is "5," it is determined whether the data transfer in step S3107 was performed with the source bit being the 5th bit of the 8th area RA8 in the pre-conversion area 124 (step S3108). If a negative determination is made in step S3108, the value of the production-side bit designation counter is incremented by 1 to update the source bit in the 8th area RA8 in the pre-conversion area 124 (step S3109). The processes of steps S3107 to S3110 are repeated until a positive determination is made in step S3108, and in step S3109, the source bit in the 8th area RA8 is updated in the order of bit 0 → bit 1 → ... → bit 4 → bit 5.

Then, the address of the destination memory area in the pre-conversion area 124 is updated by adding 1 to the value of the director's transfer destination counter (step S3110). In step S3110, the destination memory areas in the pre-conversion area 124 are updated in the following order: second area RA2 → third area RA3 → fourth area RA4 → fifth area RA5 → sixth area RA6 → seventh area RA7.

If the source bit and destination memory area have been updated in steps S3109 and S3110, proceed to step S3107, and repeat steps S3107 through S3110 until a positive determination is made in step S3108. This allows the main MPU 72 to restore the data aggregated in bits 0 through 5 of the top-level aggregated frame SF before sending the start or end command to the top-level bits of the corresponding second through seventh frames FR2 through FR7. If a positive determination is made in step S3108, this top-level setting process ends.

In this way, the addresses of areas RA2 to RA7, whose most significant bits are set to "0" or "1" data stored in bits 0 to 5 of the most significant aggregated frame SF during the top-level setting process (Figure 53), are in the consecutive address range of "α+2" to "α+7." The destination memory areas can be updated sequentially by repeatedly executing the process of incrementing the value of the director's destination counter by 1 (step S3110). This simplifies the processing configuration for sequentially updating the destination memory areas.

The value of the production-side bit designation counter in the production-side RAM 94 is incremented by 1 each time the process of transferring "0" or "1" data stored in any of bits 0 through 5 of the most significant aggregated frame SF to the most significant bit in the destination memory area (processing in step S3107) is executed. Therefore, by referencing the value of the production-side bit designation counter, it is possible to determine the number of times that "0" or "1" data set in any of bits 0 through 5 of the most significant aggregated frame SF has been transferred to the second through seventh frames FR2 through FR7 corresponding to that bit. This simplifies the processing configuration for determining the number of transfers in the production-side MPU 92.

Returning to the explanation of the command reception response process (Figure 52), after the top-level setting process is executed in step S3008, a command conversion process is executed (step S3009). If the currently received command is a start command, the command conversion process in step S3009 extracts the header HD data, footer FT data, and data used by the production-side MPU 92 at the start of the game from the data stored in the pre-conversion area 124 and transfers them to the first through seventh areas RB1 through RB7 of the post-conversion area 125, thereby setting the post-conversion start command in the post-conversion area 125. On the other hand, if the currently received command is an end command, the command conversion process in step S3009 extracts the header HD data, footer FT data, and data used by the production-side MPU 92 at the end of the game from the data stored in the pre-conversion area 124 and transfers them to the post-conversion area 125, thereby setting the post-conversion end command in the post-conversion area 125. Figure 54 is a flowchart showing the command conversion process (step S3009) executed by the production-side MPU 92.

In the command conversion process, the address of the first area RA1 in the pre-conversion area 124 ("α + 1") is first set in the director's transfer source counter (step S3201). This allows the first area RA1 in the pre-conversion area 124 to be the source memory area. Then, the address of the first area RB1 in the post-conversion area 125 ("β + 1") is set in the director's transfer destination counter (step S3202). This allows the first area RB1 in the post-conversion area 125 to be the source memory area. Then, the data stored in the source memory area is transferred to the destination memory area (step S3203). As already explained, the director's MPU 92 can identify the source memory area based on the address stored in the director's transfer source counter, and can identify the destination memory area based on the address stored in the director's transfer destination counter.

Then, it is determined whether the source memory area is the 15th area RA15 in the pre-conversion area 124 (step S3204). In step S3204, a positive determination is made if the address of the 15th area RA15 in the pre-conversion area 124 ("α+15") is stored in the director's source counter. The 15th area RA15 is the area in which the footer FT data is set, both when the command set in the pre-conversion area 124 is a start command and when the command set in the pre-conversion area 124 is an end command.

If a negative judgment is made in step S3204, i.e., if command conversion is not complete, the value of the director's transfer source counter is incremented by 1 to update the address of the transfer source memory area (step S3205). The processing of steps S3205 to S3206 is repeated until a negative judgment is made in step S3206, and in step S3205, the address of the transfer source memory area is updated in the order of "α+1" → "α+2" → ... → "α+14" → "α+15". As a result, the transfer source memory areas in the pre-conversion area 124 are updated in the order of first area RA1 → second area RA2 → fourteenth area RA14 → fifteenth area RA15.

Then, the read start reception correspondence table or end reception correspondence table is referenced to determine whether the source storage area updated in step S3205 is an area to be excluded (step S3206). As already explained, the start reception correspondence table lists the following areas to be excluded: the fourth to seventh areas RA4 to RA7, in which the third to sixth frames FR3 to FR6 are stored; the eighth area RA8, in which the top-level aggregated frame SF is stored; and the twelfth to fourteenth areas RA12 to RA14, in which the tenth to twelfth frames FR10 to FR12 are stored. Furthermore, the end reception correspondence table lists the following areas to be excluded: the second to third areas RA2 to RA3, in which the first and second frames FR1 to FR2 are stored; the eighth area RA8, in which the top-level aggregated frame SF is stored; and the ninth to tenth areas RA9 to RA10, in which the seventh and eighth frames FR7 to FR8 are stored.

If a positive determination is made in step S3206, the process proceeds to step S3205, and steps S3205 to S3206 are repeatedly executed until a negative determination is made in step S3206. This prevents data stored in consecutive areas to be excluded from being transferred to the post-conversion area 125, even if there are consecutive areas to be excluded in the pre-conversion area 124.

If a negative judgment is made in step S3206, the value of the director's transfer destination counter is incremented by 1 to update the address of the transfer destination storage area (step S3207). Steps S3203 to S3207 are repeatedly executed until a positive judgment is made in step S3204, and in step S3207, the address of the transfer source storage area is updated in the order of "β+1" → "β+2" → ... → "β+9" → "β+10". As a result, in the converted area 125, the transfer destination storage areas are updated in the order of first area RB1 → second area RB2 → ... → ninth area RB9 → tenth area RB10. Then, proceed to step S3203, and repeatedly execute steps S3203 to S3207 until a positive judgment is made in step S3204. As a result, data set in the pre-conversion area 124 that is not subject to exclusion can be transferred to the post-conversion area 125, and the post-conversion area 125 can be set to a state in which a post-conversion start command or post-conversion end command is set. If a positive determination is made in step S3204, i.e., if command conversion is complete, this command conversion process ends.

In this way, the source memory area in the pre-conversion area 124 is updated in a manner that excludes areas that are subject to exclusion. On the other hand, the destination memory area in the post-conversion area 125 is updated in a manner that the memory area set next to the current destination memory area in the post-conversion area 125 becomes the destination memory area after the update. As a result, when a start command is received, data to be used by the production side MPU 92 at the start of the game can be extracted from the start command and set as the converted start command, and when an end command is received, data to be used by the production side MPU 92 at the end of the game can be extracted from the end command and set as the converted end command.

Returning to the explanation of the command reception response process (Figure 52), after the command conversion process is executed in step S3009, the area in the command storage buffer 126 to which the data is to be written is determined by determining the value of the second write pointer 129 (see Figure 45) provided in the production-side RAM 94 (step S3010). The second write pointer 129 is set with data that identifies the area in the command storage buffer 126 to which the data is to be written. Specifically, the second write pointer 129 is set with numerical information ranging from "0" to "31."

Then, the post-conversion start command or post-conversion end command stored in the post-conversion area 125 is set to the write destination area in the command storage buffer 126 identified in step S3010 (step S3011). This allows the post-conversion start command or post-conversion end command to be stored in the command storage buffer 126 and made available to the production-side MPU 92.

Then, the value of the second write pointer 129 is updated (step S3012). In step S3012, if the data of the post-conversion start command was written to the command storage buffer 126 in step S3011, "7", which is the data size of the post-conversion start command, is added to the value of the second write pointer 129. If the data of the post-conversion end command was written to the command storage buffer 126 in step S3011, "10", which is the data size of the post-conversion end command, is added to the value of the second write pointer 129. In step S3012, if the result of the operation to add "7" or "10" exceeds the maximum value of "63", the second write pointer 129 is set to a value that is "64" less than the result of the operation. For example, if the result of the operation to add "7" or "10" is "64", which exceeds the maximum value of "63", the second write pointer 129 is set to "0", which is "64" less than the result of the operation ("64").

After that, if the command stored in the command storage buffer 126 in step S3011 is a converted start command (step S3013: YES), the start reception flag provided in the production-side RAM 94 is set to "1" (step S3014). The start reception flag is a flag that allows the production-side MPU 92 to know that a start command has been received from the main-side MPU 72. By setting the start reception flag to "1" in step S3014, steps S3302 and subsequent steps will be executed in the start reception response processing (Figure 55) described below.

If the command stored in the command storage buffer 126 in step S3011 is not a post-conversion start command (step S3013: NO), that is, if the command stored in the command storage buffer 126 in step S3011 is a post-conversion end command, the end reception flag provided in the production-side RAM 94 is set to "1" (step S3015). The end reception flag is a flag that allows the production-side MPU 92 to know that an end command has been received from the main-side MPU 72. By setting the end reception flag to "1" in step S3015, steps S3502 and subsequent steps will be executed in the end reception handling process (Figure 57) described below. If the processing of step S3014 or step S3015 has been performed, the pre-conversion area 124 and post-conversion area 125 are cleared to "0" (step S3016), and this command reception handling process ends.

If the command identified as the command to be moved in step S3003 is neither a start command nor an end command (step S3004: NO, step S3006: NO), it is determined whether the command to be moved has header HD data indicating that it is a winning result command (step S3017). If the command to be moved has header HD data indicating that it is a winning result command (step S3017: YES), the value of the second write pointer 129 in the production-side RAM 94 is determined to be the write destination area in the command storage buffer 126 (step S3018), and the winning result command stored in the post-reception standby buffer 122 is set to the write destination area in the command storage buffer 126 identified in step S3018 (step S3019). This allows the winning result command to be stored in the command storage buffer 126 and made available to the production-side MPU 92.

Then, the value of the second write pointer 129 is updated (step S3020). In step S3020, "5", which is the data capacity of the winning result command written to the command storage buffer 126 in step S3019, is added to the value of the second write pointer 129. In step S3020, if the result of the operation to add "5" exceeds the maximum value of "63", the second write pointer 129 is set to a value "64" smaller than the result of the operation. For example, if the result of the operation to add "5" is "64", which exceeds the maximum value of "63", the second write pointer 129 is set to "0", which is "64" smaller than the result of the operation ("64").

Then, a process for clearing the post-reception standby buffer 122 is executed (step S3021). In the process for clearing the post-reception standby buffer 122 in step S3021, the area in the post-reception standby buffer 122 where the winning result command was stored is cleared to "0". This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. Then, the value of the read pointer 128 in the post-reception standby buffer 122 is updated to a value corresponding to the area next to the area where the end of the winning result command (footer FT data) was stored (step S3022).

Then, the winning result reception flag stored in the production side RAM 94 is set to "1" (step S3023), and this command reception response process is terminated. The winning result reception flag is a flag that allows the production side MPU 92 to know that a winning result command has been received. By setting the winning result reception flag to "1" in step S3023, steps S3402 and beyond will be executed in the winning result reception response process (Figure 56) described below.

If a negative determination is made in step S3017, processing for receiving other commands is executed (step S3024), and this command reception processing ends. In the processing for receiving other commands in step S3024, the value of the second write pointer 129 in the production-side RAM 94 is first determined to determine the write destination area in the command storage buffer 126, and the command determined in step S3003 as the command to be moved (e.g., a power recovery command) is set in this determined area. Thereafter, as in steps S3012 and S3020, the value of the second write pointer 129 is updated. Then, the area in the post-reception standby buffer 122 where the command to be moved was stored is cleared to "0." This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. Then, the value of the read pointer 128 in the post-reception standby buffer 122 is updated to a value corresponding to the area following the area where the end of the command to be moved (footer FT data) was stored.

Next, the start-up reception response processing executed by the production-side MPU 92 will be explained with reference to the flowchart in Figure 55. The start-up reception response processing is repeatedly executed by the production-side MPU 92 at relatively short intervals (for example, every 4 milliseconds).

In the start reception processing, if the start reception flag in the presentation side RAM 94 is set to "1" (step S3301: YES), the data of the bet number setting counter 74b set in the converted start command stored in the command storage buffer 126 is set in the presentation side bet number counter provided in the presentation side RAM 94 (step S3302). The presentation side bet number counter is a counter that allows the presentation side MPU 92 to determine the number of bets for the current game ("2" or "3"). By setting the data of the bet number setting counter 74b set in the converted start command in the presentation side bet number counter in step S3302, the number of bets for the current game can be determined by the presentation side MPU 92.

Then, the current game state is determined (step S3303). The presentation side RAM 94 is provided with a presentation side first CB state flag, a presentation side second CB state flag, a presentation side pseudo bonus state flag, a presentation side AT state flag, a presentation side end preparation state flag, a first CB internal state flag, and a second CB internal state flag. The presentation side first CB state flag is a flag that enables the presentation side MPU 92 to determine that the game state is the first CB state ST2, the presentation side second CB state flag is a flag that enables the presentation side MPU 92 to determine that the game state is the second CB state ST3, the presentation side pseudo bonus state flag is a flag that enables the presentation side MPU 92 to determine that the game state is the pseudo bonus state ST4, and the presentation side AT state flag is a flag that enables the presentation side MPU 92 to determine that the game state is the AT state ST5. The flags are the presentation side end preparation state flag, which allows the presentation side MPU 92 to understand that the game state is in the end preparation state ST6, the first CB internal state flag, which allows the presentation side MPU 92 to understand that after a first CB win occurs, the first CB internal state is a state in which the corresponding first CB winning has not been achieved, and the second CB internal state flag, which allows the presentation side MPU 92 to understand that after a second CB win occurs, the second CB internal state is a state in which the corresponding second CB winning has not been achieved. In step S3303, if the presentation side first CB state flag is set to "1", it is determined that the state is the first CB state ST2; if the presentation side second CB state flag is set to "1", it is determined that the state is the second CB state ST3; if the presentation side pseudo-bonus state flag is set to "1", it is determined that the state is the pseudo-bonus state ST4; if the presentation side AT state flag is set to "1", it is determined that the state is the AT state ST5; and if the presentation side end preparation state flag is set to "1", it is determined that the state is the end preparation state ST6. Furthermore, if the values of these five flags are all "0", it is determined that the state is the normal game state ST1. Furthermore, if the first CB internal state flag is set to "1", it is determined that the state is the first CB internal state, and if the second CB internal state flag is set to "1", it is determined that the state is the second CB internal state.

Then, the effect start process is executed (step S3304). In the effect start process, an effect data table is read from the effect side ROM 93 to execute an effect in the upper lamp 61, speaker 62, and image display device 63 corresponding to the game status determined in step S3303 and the number of bets set in the effect side bet number counter in step S3302. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are initiated according to the read effect data table. In the effect start process in step S3304, if the ending period flag provided in the effect side RAM 94 is set to "1," an effect data table to execute an effect corresponding to the ending period is read from the effect side ROM 93. The ending period flag is a flag that enables the effect side MPU 92 to determine that the ending effect of the second section SC2 is being executed. The ending period flag is set to "1" in step S3608 of the second section corresponding process (FIG. 58) described below.

In the presentation start processing in step S3304, if the game state is the pseudo bonus state ST4, the presentation side pseudo bonus state counter in the presentation side RAM 94 is referenced to determine the number of remaining games to be continued in the pseudo bonus state ST4, provided that the value of the number of continued games non-display flag in the presentation side RAM 94 is "0," and display data for displaying the determined number of remaining games to be continued on the image display device 63 is output to the image display device 63. The number of continued games non-display flag is a flag that allows the presentation side MPU 92 to determine that a display indicating the number of remaining games to be continued in the pseudo bonus state ST4 will not be executed. The number of continued games non-display flag is set to "1" in step S3707 of the pseudo bonus state response processing (Figure 59) described below when the pseudo bonus state ST4 is initiated with either the ending flag 76b or 76c in the main side RAM 74 set to "1." The presentation side pseudo bonus continuation counter is a counter that allows the presentation side MPU 92 to determine the number of remaining games to be continued in the pseudo bonus state ST4. The pseudo bonus continuation counter on the presentation side is set with the data of the pseudo bonus continuation counter 74t set in the post-conversion end command in steps S3704 and S3709 of the pseudo bonus state response process (FIG. 59) described later. When the transition to the pseudo bonus state ST4 occurs because the number of continued games in the second section SC2 is equal to or greater than the reference number of games (specifically, "1450") or the limited total net increase in the number of gaming media in the second section SC2 is equal to or greater than the reference acquisition number (specifically, "2150"), the pseudo bonus state ST4 may end with the end of the second section SC2 if the number of continued games in the second section SC2 reaches the upper limit number of games (specifically, "1500") or the limited total net increase in the number of gaming media in the second section SC2 reaches the upper limit net increase number (specifically, "2400") before the remaining number of continued games in the pseudo bonus state ST4 becomes "0". In this case, by not displaying the remaining number of games to be played in pseudo bonus state ST4, it is possible to prevent the player from feeling uncomfortable about the fact that pseudo bonus state ST4 has ended when the ending conditions for the second section SC2 are met.

In the presentation start processing in step S3304, if the game state is AT state ST5, the number of remaining games to be played in AT state ST5 is determined by referencing the presentation side AT continuation counter provided in the presentation side RAM 94, and display data for displaying the determined number of remaining games to be played on the image display device 63 is output to the image display device 63. The presentation side AT continuation counter is a counter that allows the presentation side MPU 92 to determine the number of remaining games to be played in AT state ST5. The presentation side AT continuation counter is set with the data of the AT continuation counter 74u set in the post-conversion end command in steps S3807 and S3812 of the AT state response processing (Figure 60) described below.

Then, by referencing the presentation side AT state flag, it is determined whether the game state is AT state ST5 (step S3305). If the game state is AT state ST5 (step S3305: YES), the value of the presentation side AT continuation counter in the presentation side RAM 94 is determined (step S3306). Then, based on the data of the AT continuation counter 74u set in the post-conversion start command, the value of the AT continuation counter 74u is determined (step S3307). Then, it is determined whether an addition to the remaining number of continued games in AT state ST5 has occurred (step S3308). In step S3308, an operation is performed to subtract the value of the presentation side AT continuation counter determined in step S3306 from the value of the AT continuation counter 74u determined in step S3307, and if the result of this operation is 1 or greater, it is determined that an addition has occurred (step S3308: YES). As already explained, the numbers of games that can be added in the lottery for adding the remaining number of continued games in AT state ST5 are "10," "20," and "50."

If an additional bonus has been awarded (step S3308: YES), the number of additional bonus games for the current bonus win is determined based on the calculation result of step S3308 (step S3309). Then, the additional bonus effect setting process is executed (step S3310). In the additional bonus effect setting process, a performance data table is read from the performance-side ROM 93 to execute an additional bonus effect on the image display device 63 corresponding to the number of additional bonus games determined in step S3309. Then, display control of the image display device 63 is executed in accordance with the read performance data table. If an additional bonus effect is executed, a cut-in image corresponding to the number of additional bonus games is displayed on the image display device 63 during the execution of the effect started in the performance start process in step S3304. This notifies the player of the number of additional bonus games.

If a negative judgment is made in step S3308, or if the processing of step S3310 is performed, the data of the AT continuation counter 74u set in the post-conversion start command is set to the presentation-side AT continuation counter (step S3311). This allows the presentation-side MPU 92 to grasp the remaining number of continued games in AT state ST5.

If the gaming state is not AT state ST5 (step S3305: NO), the effect side pseudo bonus state flag is referenced to determine whether the gaming state is in pseudo bonus state ST4 (step S3312). If the gaming state is in pseudo bonus state ST4 (step S3312: YES), it is determined whether the effect execution flag provided in the effect side RAM 94 is set to "1" (step S3313). The effect execution flag is a flag that allows the effect side MPU 92 to determine whether an AT transition confirmation effect has already been executed in the current pseudo bonus state ST4. When the pseudo bonus state ST4 ends, the effect execution flag is cleared to "0" in step S3715 of the pseudo bonus state response processing (FIG. 59) described below.

If the effect execution flag is not set to "1" (step S3313: NO), a determination is made as to whether the transition to AT state ST5 has been confirmed based on the data of the AT transition confirmation flag 77f included in the data in the game state area 77 set in the post-conversion start command (step S3314). If the transition to AT state ST5 has been confirmed (step S3314: YES), the setting process for the AT transition confirmation effect is executed (step S3315). In the setting process for the AT transition confirmation effect, a presentation data table for executing the AT transition confirmation effect that notifies the player that the transition to AT state ST5 has been confirmed is read from the presentation-side ROM 93. Then, display control of the image display device 63 is initiated according to the read presentation data table. If the AT transition confirmation effect is executed, a cut-in image notifying the player that the transition to AT state ST5 has been confirmed is displayed on the image display device 63 during the execution of the effect started in step S3304. This notifies the player that the transition to AT state ST5 has been confirmed. After that, the effect execution flag in the effect side RAM 94 is set to "1" (step S3316). This prevents the AT transition confirmation effect from being executed more than once before the current pseudo bonus state ST4 ends.

If the processing of step S3311 is executed, if a positive determination is made in step S3313, if a negative determination is made in step S3314, or if the processing of step S3316 is executed, it is determined whether the game involves stop order notification, which notifies the stop order of reels 32L, 32M, and 32R, on the image display device 63 (step S3317). In step S3317, the value of the stop order type counter 74m is determined based on the data of the stop order type counter 74m set in the converted start command, and if the value of the stop order type counter 74m is any one of "1" to "9," it is determined that the game involves stop order notification (step S3317: YES). As already explained, in a game in which stop order notification is made on the image display device 63, a stop order type number of any one of "1" to "9" is set in the stop order type counter 74m, and in a game in which stop order notification is not made on the image display device 63, the value of the stop order type counter 74m is "0."

If the game is one in which stop order notifications are executed on the image display device 63 (step S3317: YES), the type of stop order notification to be executed on the image display device 63 is determined based on the value of the stop order type counter 74m determined in step S3317 (step S3318), and stop order notification start processing is executed (step S3319). In the stop order notification start processing, a notification data table for executing the type of stop order notification determined in step S3318 on the image display device 63 is read from the presentation-side ROM 93. Then, display control of the image display device 63 is started in accordance with the read notification data table.

If a negative judgment is made in step S3312, if a negative judgment is made in step S3317, or if the processing of step S3319 is performed, the start-up reception flag in the production-side RAM 94 is cleared to "0" (step S3320), and this start-up reception response processing ends.

In this way, the presentation-side MPU 92 converts the start command received from the main MPU 72 into a converted start command and executes processing to execute the presentation of the currently started game based on the converted start command. As already explained with reference to FIG. 47(b), the converted start command contains data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 in the main RAM 74. Because this configuration makes the data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 available when a start command is received, the number of times commands need to be sent from the main MPU 72 to the presentation-side MPU 92 can be reduced compared to a configuration in which the data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 is received in two or more commands. This reduces the processing load when the main MPU 72 sends commands to the production MPU 92, and also reduces the processing load when the production MPU 92 executes processing corresponding to commands received from the main MPU 72.

Next, the winning result reception response process executed by the production side MPU 92 will be described with reference to the flowchart in Figure 56. The winning result reception response process is repeatedly executed by the production side MPU 92 at relatively short intervals (for example, every 4 milliseconds).

In the winning result reception process, if the winning result reception flag in the presentation RAM 94 is set to "1" (step S3401: YES), the presentation MPU 92 determines whether first CB winning data is set in the main RAM 74 based on the data in the first CB winning data area 74j set in the winning result command stored in the command storage buffer 126 (step S3402). If first CB winning data is set (step S3402: YES), the presentation MPU 92 determines whether a first CB winning event corresponding to the first CB winning data has occurred based on the data in the winning data area 78 in the main RAM 74 set in the winning result command (step S3403). If a first CB winning event has not occurred (step S3403: NO), the presentation MPU 92 sets the first CB internal state flag in the presentation RAM 94 to "1" (step S3404). This allows the presentation MPU 92 to determine the first CB internal state. On the other hand, if a first CB win is achieved (step S3403: YES), the first CB internal state flag in the presentation side RAM 94 is cleared to "0" (step S3405). This allows the presentation side MPU 92 to know that the first CB internal state has ended.

If a negative determination is made in step S3402, the controller 126 determines whether second CB winning data is set in the main RAM 74 based on the data in the second CB winning data area 74k set in the winning result command stored in the command storage buffer 126 (step S3406). If second CB winning data is set (step S3406: YES), the controller 126 determines whether a second CB winning event corresponding to the second CB winning data has occurred based on the data in the winning data area 78 in the main RAM 74 set in the winning result command (step S3407). If a second CB winning event has not occurred (step S3407: NO), the controller 126 sets the second CB internal state flag in the presentation RAM 94 to "1" (step S3408). This allows the presentation MPU 92 to determine whether the second CB internal state is correct. On the other hand, if a second CB win is achieved (step S3407: YES), the second CB internal state flag in the presentation side RAM 94 is cleared to "0" (step S3409). This allows the presentation side MPU 92 to know that the second CB internal state has ended.

If step S3404 is performed, step S3405 is performed, a negative judgment is made in step S3406, step S3408 is performed, or step S3409 is performed, the winning result reception flag in the presentation side RAM 94 is cleared to "0" (step S3410), and this winning result reception response process is terminated.

Next, the end-of-period reception response processing executed by the production-side MPU 92 will be explained with reference to the flowchart in Figure 57. The end-of-period reception response processing is repeatedly executed by the production-side MPU 92 at relatively short intervals (for example, every 4 milliseconds).

During the end-time reception process, if the end-time reception flag in the production-side RAM 94 is set to "1" (step S3501: YES), the second-section response process is executed (step S3502). Figure 58 is a flowchart showing the second-section response process (step S3502).

In the second section processing, it is determined whether the presentation-side second section flag stored in the presentation-side RAM 94 is set to "1" (step S3601). The presentation-side second section flag is a flag that allows the presentation-side MPU 92 to determine that the play section is the second section SC2. If the presentation-side second section flag is not set to "1" (step S3601: NO), it is determined whether the play section is the second section SC2 based on the data of the second section flag 76a included in the data of the play section area 76 set in the post-conversion end command stored in the command storage buffer 126 (step S3602). If the presentation-side second section flag is not set to "1" and the second section flag 76a in the main RAM 74 is set to "1" (step S3601: NO, step S3602: YES), this indicates the start timing of the second section SC2, and the presentation-side second section flag is set to "1" (step S3603). This allows the presentation side MPU 92 to understand that the game zone is the second zone SC2.

If a positive determination is made in step S3601, similar to step S3602, it is determined whether the game zone is the second zone SC2 based on the data of the second zone flag 76a included in the data of the game zone area 76 set in the post-conversion end command (step S3604). If a positive determination is made in step S3604, that is, if the current game is executed in a state where the game zone is the second zone SC2 and the second zone SC2 will continue after the current game ends, it is determined whether the ending period flag in the presentation-side RAM 94 is set to "1" (step S3605). As already explained, the ending period flag is a flag that enables the presentation-side MPU 92 to determine that the period in which the ending presentation of the second zone SC2 is being executed is being performed.

If a negative judgment is made in step S3605, it is determined whether either of the ending flags 76b, 76c in the main RAM 74 is set to "1" based on the data of the first ending flag 76b and the second ending flag 76c contained in the data of the game section area 76 set in the post-conversion end command (step S3606). If either of the ending flags 76b, 76c is set to "1" (step S3606: YES), it is determined whether the game is in AT state ST5 based on the data of the AT state flag 77d contained in the data of the game section area 77 set in the post-conversion end command (step S3607). If the game is in AT state ST5 (step S3607: YES), the ending period flag in the presentation RAM 94 is set to "1" (step S3608), and the second section response processing is terminated. By setting the ending period flag to "1", it is possible to start the ending period effect in the effect start processing in step S3304 of the start-time reception corresponding processing (FIG. 55) already explained. On the other hand, if the AT state is not ST5 (step S3607: NO), the ending wait flag provided in the performance side RAM 94 is set to "1" (step S3609), and this second section corresponding processing ends. The ending wait flag is a flag that allows the performance side MPU 92 to know that the ending period effect should start at the timing of transition to AT state ST5. If the ending wait flag is set to "1" in step S3609, the ending period effect will start at the timing of transition to AT state ST5.

If the presentation side second section flag is set to "1" and the second section flag 76a is not set to "1" (step S3601: YES, step S3604: NO), this means that it is time for the second section SC2 to end, and so the second section initialization effect setting process is executed (step S3610). In the second section initialization effect setting process, display data for displaying a message corresponding to the initialization of the second section SC2 on the image display device 63 is output to the image display device 63. The presentation side second section flag is then cleared to "0" (step S3611). This allows the presentation side MPU 92 to understand that the play section has become the first section SC1. The ending period flag in the presentation side RAM 94 is then cleared to "0" (step S3612), and the second section response process is terminated. Clearing the ending period flag to "0" in step S3612 prevents the ending period effect from being executed.

Returning to the explanation of the end-of-game reception response process (Figure 57), after the second section response process is executed in step S3502, the pseudo-bonus state response process is executed (step S3503). Figure 59 is a flowchart showing the pseudo-bonus state response process.

In the pseudo-bonus state response process, if the pseudo-bonus state flag in the presentation RAM 94 is not set to "1" (step S3701: NO), the system determines whether the game is in pseudo-bonus state ST4 based on the pseudo-bonus state flag 77c included in the game state area 77 data set in the post-conversion end command (step S3702). If the pseudo-bonus state flag is not set to "1" and the pseudo-bonus state flag 77c in the main RAM 74 is set to "1" (step S3701: NO, step S3702: YES), this indicates that it is time to transition to pseudo-bonus state ST4, and the system executes pseudo-bonus state start effect setting process (step S3703). In the pseudo-bonus state start effect setting process, the system reads from the presentation ROM 93 an effect data table for executing a pseudo-bonus state start effect, indicating a transition to pseudo-bonus state ST4, using the upper lamp 61, speaker 62, and image display device 63. Then, in accordance with the read performance data table, the system starts controlling the light emission of the upper lamp 61, controlling the sound output of the speaker 62, and controlling the display of the image display device 63.

Then, the data of the pseudo bonus continuation counter 74t set in the converted end command is set in the presentation-side pseudo bonus continuation counter provided in the presentation-side RAM 94 (step S3704). As already explained, the presentation-side pseudo bonus continuation counter is a counter that allows the presentation-side MPU 92 to grasp the remaining number of continued games in pseudo bonus state ST4. The presentation-side pseudo bonus continuation counter is referenced when executing processing to display the remaining number of continued games in pseudo bonus state ST4 on the image display device 63 during the presentation start processing in step S3304 of the start-time reception response processing (FIG. 55) already explained. Then, the presentation-side pseudo bonus state flag in the presentation-side RAM 94 is set to "1" (step S3705). This allows the presentation-side MPU 92 to grasp that the game state is pseudo bonus state ST4 and that the game section is in pseudo bonus state ST4.

Then, based on the data for the first ending flag 76b and the second ending flag 76c included in the data for the play interval area 76 set in the converted end command, it is determined whether either of the ending flags 76b and 76c is set to "1" (step S3706). If at least one of the first ending flag 76b and the second ending flag 76c in the host RAM 74 is set to "1" (step S3706: YES), the number of games to be continued flag in the presentation RAM 94 is set to "1" (step S3707). As previously explained, the number of games to be continued flag is a flag that allows the presentation MPU 92 to determine that a display indicating the number of games remaining to be played in the pseudo bonus state ST4 will not be executed. In a game in the pseudo bonus state ST4, if the value of the number of games to be continued flag is "0," a display indicating the number of games remaining to be played in the pseudo bonus state ST4 and a display indicating the number of gaming media acquired in the pseudo bonus state ST4 are displayed on the image display device 63. Furthermore, in a game in pseudo bonus state ST4, if the continued game count non-display flag is set to "1", the image display device 63 will display the number of gaming media acquired in pseudo bonus state ST4, but will not display the remaining number of continued games in pseudo bonus state ST4.

If the presentation-side pseudo-bonus state flag is set to "1" and the pseudo-bonus state flag 77c in the main RAM 74 is set to "1" (step S3701: YES, step S3708: YES), i.e., if the current game is being played in pseudo-bonus state ST4 and pseudo-bonus state ST4 continues after the current game ends, the value of the presentation-side pseudo-bonus continuation counter is updated by setting the data of the pseudo-bonus continuation counter 74t set in the post-conversion end command to the presentation-side pseudo-bonus continuation counter (step S3709). Then, an update process is executed for the pseudo-bonus award number counter provided in the presentation-side RAM 94 (step S3710). The pseudo-bonus award number counter is a counter that allows the presentation-side MPU 92 to track the number of gaming media acquired in pseudo-bonus state ST4. In the pseudo bonus award number counter update process in step S3710, the number of gaming media awarded in the current game is determined based on the data in the award number counter 74e set in the post-conversion end command, and the determined number of gaming media awarded is added to the pseudo bonus award number counter in the presentation-side RAM 94. This allows the presentation-side MPU 92 to determine the number of gaming media acquired in pseudo bonus state ST4. Then, the display showing the number of gaming media acquired in pseudo bonus state ST4, displayed on the image display device 63, is updated (step S3711). In step S3711, display data corresponding to the value of the pseudo bonus award number counter after being updated in step S3710 is output to the image display device 63.

If the presentation-side pseudo bonus state flag is set to "1" and the pseudo bonus state flag 77c in the main RAM 74 is not set to "1" (step S3701: YES, step S3708: NO), this means that the pseudo bonus state ST4 has ended, so the pseudo bonus state end effect setting process is executed (step S3712). In the pseudo bonus state end effect setting process, a presentation data table is read from the presentation-side ROM 93 to execute a pseudo bonus state end effect indicating the end of the pseudo bonus state ST4 using the upper lamp 61, speaker 62, and image display device 63. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are initiated according to the read presentation data table.

Then, the presentation side pseudo bonus state flag is cleared to "0" (step S3713). This allows the presentation side MPU 92 to know that the pseudo bonus state ST4 has ended. The presentation side pseudo bonus continuation counter value is then cleared to "0" (step S3714), and the presentation execution completion flag in the presentation side RAM 94 is cleared to "0" (step S3715). The presentation side RAM 94's non-display flag for the number of continued games is then cleared to "0" (step S3716), and the presentation side RAM 94's pseudo bonus award count counter is cleared to "0" (step S3717).

Then, based on the data of the end preparation state flag 77e included in the data of the game state area 77 set in the converted end command, it is determined whether or not the game is in the end preparation state ST6 (step S3718). If the game is in the end preparation state ST6 (step S3718: YES), the presentation side end preparation state flag in the presentation side RAM 94 is set to "1" (step S3719). This allows the presentation side MPU 92 to know that the game state is in the end preparation state.

If a negative judgment is made in step S3706, if processing of step S3707 is performed, if processing of step S3711 is performed, if a negative judgment is made in step S3718, or if processing of step S3719 is performed, the process proceeds to step S3521 of the end-of-game reception handling process (Figure 57). On the other hand, if a negative judgment is made in step S3701 or step S3702, the pseudo-bonus state handling process is terminated, and the process proceeds to step S3504 of the end-of-game reception handling process (Figure 57).

Returning to the explanation of the end-of-service reception handling process (Figure 57), in step S3504, the AT status handling process is executed. Figure 60 is a flowchart showing the AT status handling process.

In the AT state response processing, if the presentation-side AT state flag in the presentation-side RAM 94 is not set to "1" (step S3801: NO), it is determined whether the game is in AT state ST5 based on the data of the AT state flag 77d contained in the data of the game state area 77 set in the post-conversion end command (step S3802). If the presentation-side AT state flag is not set to "1" and the AT state flag 77d in the main RAM 74 is set to "1" (step S3801: NO, step S3802: YES), this means it is time to transition to AT state ST5, so steps S3803 to S3808 are executed. Specifically, it is determined whether the ending wait flag in the presentation RAM 94 is set to "1" (step S3803). If the ending wait flag is set to "1" (step S3803: YES), the ending period flag in the presentation RAM 94 is set to "1" (step S3804). This allows the ending period effect to be executed. In this way, if the first ending flag 76b or the second ending flag 76c in the main RAM 74 is set to "1" when an ending effect is not being executed and the game state is not in the AT state ST5, the ending effect will begin when the game subsequently transitions to the AT state ST5. Then, the ending wait flag in the presentation RAM 94 is cleared to "0" (step S3805).

If a negative judgment is made in step S3803, or if the processing of step S3805 is performed, the AT state start effect setting process is executed (step S3806). In the AT state start effect setting process, an effect data table for executing the AT state start effect indicating that the AT state ST5 has started on the upper lamp 61, speaker 62, and image display device 63 is read from the effect-side ROM 93. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read effect data table.

Then, the data of the AT continuation counter 74u set in the converted end command is set to the presentation-side AT continuation counter in the presentation-side RAM 94 (step S3807). As already explained, the presentation-side AT continuation counter is a counter that allows the presentation-side MPU 92 to grasp the remaining number of continuing games in AT state ST5. The presentation-side AT continuation counter is referenced when processing is performed to display the remaining number of continuing games in AT state ST5 on the image display device 63 during the presentation start processing in step S3304 of the start-time reception corresponding processing (Figure 55) already explained. Then, the presentation-side AT state flag is set to "1" (step S3808). This allows the presentation-side MPU 92 to grasp that the game state is in AT state ST5.

If the presentation-side AT state flag is set to "1" and the AT state flag 77d in the main RAM 74 is set to "1" (step S3801: YES, step S3809: YES), i.e., the current game is being played in AT state ST5 and AT state ST5 will continue after the current game ends, the number of game media awarded for the game to be ended is determined based on the data in the award number counter 74e set in the converted end command (step S3810), and a process for setting the award number display is executed (step S3811). In the process for setting the award number display, if the number of game media awarded determined in step S3810 is one or more, a data table for displaying the number of game media awarded on the image display device 63 is read from the presentation-side ROM 93. Then, display control of the image display device 63 is initiated according to the read presentation data table. Then, the value of the AT continuation counter on the production side is updated by setting the data of the AT continuation counter 74u set in the converted end command to the AT continuation counter on the production side (step S3812).

If the presentation-side AT state flag in the presentation-side RAM 94 is set to "1" and the AT state flag 77d in the main RAM 74 is not set to "1" (step S3801: YES, step S3809: NO), this means that AT state ST5 has ended, and the AT state end effect setting process is executed (step S3813). In the AT state end effect setting process, the presentation data table for executing the AT state end effect indicating that AT state ST5 has ended using the upper lamp 61, speaker 62, and image display device 63 is read from the presentation-side ROM 93. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are initiated according to the read presentation data table. Then, the presentation-side AT state flag is cleared to "0" (step S3814). This allows the presentation-side MPU 92 to determine that AT state ST5 has ended. Then, the value of the presentation-side AT continuation counter is cleared to "0" (step S3815).

Then, based on the data of the end preparation state flag 77e included in the data of the game state area 77 set in the converted end command, it is determined whether or not the game is in the end preparation state ST6 (step S3816). If the game is in the end preparation state ST6 (step S3816: YES), the presentation side end preparation state flag in the presentation side RAM 94 is set to "1" (step S3817). This allows the presentation side MPU 92 to determine that the game state is in the end preparation state ST6.

If step S3808 is performed, step S3812 is performed, a negative determination is made in step S3816, or step S3817 is performed, the process proceeds to step S3521 of the end-of-state reception handling process (Figure 57). On the other hand, if a negative determination is made in steps S3801 and S3802, the AT state handling process is terminated and the process proceeds to step S3505 of the end-of-state reception handling process (Figure 57).

Returning to the explanation of the end-time reception response processing (Figure 57), in steps S3505 to S3511, the first CB state response processing is executed. In the first CB state response processing (steps S3505 to S3511), it is first determined whether the presentation-side first CB state flag in the presentation-side RAM 94 is set to "1" (step S3505). If the presentation-side first CB state flag is not set to "1" (step S3505: NO), it is determined whether the first CB state is ST2 based on the data of the first CB state flag 77a included in the data in the game state area 77 set in the converted end-time command (step S3506). If the presentation-side AT state flag in the presentation-side RAM 94 is not set to "1" and the first CB state flag 77a in the main RAM 74 is set to "1" (step S3505: NO, step S3506: YES), this indicates that it is time to transition to the first CB state ST2, and a setting process for the first CB state start effect is executed (step S3507). In the setting process for the first CB state start effect, a presentation data table for executing a first CB state start effect indicating that the first CB state ST2 has started on the upper lamp 61, speaker 62, and image display device 63 is read from the presentation-side ROM 93. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read presentation data table. Then, the presentation-side first CB state flag is set to "1" (step S3508). This allows the presentation side MPU 92 to understand that the game state is the first CB state ST2.

If the presentation-side first CB state flag in the presentation-side RAM 94 is set to "1" and the first CB state flag 77a in the main RAM 74 is not set to "1" (step S3505: YES, step S3509: NO), this means that the first CB state ST2 has ended, and the first CB state end effect setting process is executed (step S3510). In the first CB state end effect setting process, an effect data table is read from the presentation-side ROM 93 to execute a first CB state end effect indicating that the first CB state ST2 has ended using the upper lamp 61, speaker 62, and image display device 63. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are initiated according to the read effect data table. Then, the presentation-side first CB state flag is cleared to "0" (step S3511). This allows the presentation-side MPU 92 to determine that the first CB state ST2 has ended.

If a negative judgment is made in steps S3505 and S3506, the second CB state response processing is executed in steps S3512 to S3518. In the second CB state response processing (steps S3512 to S3518), it is first determined whether the presentation side second CB state flag in the presentation side RAM 94 is set to "1" (step S3512). If the presentation side second CB state flag is not set to "1" (step S3512: NO), it is determined whether the second CB state ST3 is in place based on the data of the second CB state flag 77b included in the data in the game state area 77 set in the post-conversion end command (step S3513). If the presentation-side second CB state flag in the presentation-side RAM 94 is not set to "1" and the second CB state flag 77b in the main RAM 74 is set to "1" (step S3512: NO, step S3513: YES), this indicates that it is time to transition to the second CB state ST3, and a setting process for the second CB state start effect is executed (step S3514). In the setting process for the second CB state start effect, a presentation data table for executing a second CB state start effect indicating that the second CB state ST3 has started on the upper lamp 61, speaker 62, and image display device 63 is read from the presentation-side ROM 93. Then, the illumination control of the upper lamp 61, the sound output control of the speaker 62, and the display control of the image display device 63 are started according to the read presentation data table. Then, the presentation-side second CB state flag is set to "1" (step S3515). This allows the presentation side MPU 92 to understand that the game state is the second CB state ST3.

If the presentation-side second CB state flag in the presentation-side RAM 94 is set to "1" and the second CB state flag 77b in the main RAM 74 is not set to "1" (step S3512: YES, step S3516: NO), this means that the second CB state ST3 has ended, and the second CB state end effect setting process is executed (step S3517). In the second CB state end effect setting process, an effect data table is read from the presentation-side ROM 93 to execute a second CB state end effect indicating that the second CB state ST3 has ended using the upper lamp 61, speaker 62, and image display device 63. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are initiated according to the read effect data table. Then, the presentation-side second CB state flag is cleared to "0" (step S3518). This allows the presentation-side MPU 92 to determine that the second CB state ST3 has ended.

If a negative judgment is made in steps S3512 and S3513, it is determined whether the presentation side end preparation state flag in the presentation side RAM 94 is set to "1" (step S3519). As already explained, the end preparation state ST6 ends when one game has been played. If the presentation side end preparation state flag is set to "1" (step S3519: YES), that is, if the current game has been played in the end preparation state ST6, the end preparation state ST6 will end after the current game ends, and the presentation side end preparation state flag is cleared to "0" (step S3520). This allows the presentation side MPU 92 to know that the end preparation state ST6 has ended.

If step S3508 is processed, if a positive judgment is made in step S3509, if step S3511 is processed, if step S3515 is processed, if a positive judgment is made in step S3516, if step S3518 is processed, if a negative judgment is made in step S3519, or if step S3520 is processed, the process proceeds to step S3521. Also, as already explained, if a negative judgment is made in step S3706 of the pseudo-bonus state response processing (Figure 59), if step S3707 is processed, if step S3711 is processed, if a negative judgment is made in step S3718, or if step S3719 is processed, the process also proceeds to step S3521 of the end-of-reception response processing (Figure 57). Furthermore, as already explained, if step S3808 of the AT state response processing (Fig. 60) is performed, if step S3812 is performed, if a negative determination is made in step S3816, or if step S3817 is performed, the process proceeds to step S3521 of the end-of-game reception response processing (Fig. 57). In step S3521, the end-of-game reception flag in the performance-side RAM 94 is cleared to "0," and the end-of-game reception response processing ends.

In this way, the presentation-side MPU 92 converts the end command received from the main-side MPU 72 into a converted end command and executes processing to execute the presentation based on the converted end command. As already explained with reference to Figure 47 (c), the converted end command contains data for the number of continued games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and award number counter 74e in the main-side RAM 74. Because the data for the continued games counter 74r, total wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and awarded number counter 74e becomes available when an end command is received, the number of commands sent from the main MPU 72 to the presentation MPU 92 can be reduced compared to a configuration in which the data for the continued games counter 74r, total wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and awarded number counter 74e is received using two or more commands. This reduces the processing load on the main MPU 72 when sending commands to the presentation MPU 92, and also reduces the processing load on the presentation MPU 92 when executing processing corresponding to commands received from the main MPU 72.

As described above, the "0" or "1" data stored in the most significant bits of the six memory areas set in the contiguous address range of "0001H" to "0006H," including the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total win count counter 74s, whose most significant bits can be set to "1," is aggregated into a one-byte memory area (top-level aggregation area 74v). Therefore, compared to a configuration in which two or more bytes of memory area are set in the main RAM 74 to set the "0" or "1" data stored in the most significant bits of these six memory areas, the data capacity of the memory area provided in the main RAM 74 to set the "0" or "1" data stored in the most significant bits of these six memory areas is reduced.

Six memory areas, including the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total win count counter 74s, which can have their most significant bit set to "1," are set in a contiguous address range from "0001H" to "0006H." This simplifies the processing configuration for specifying the address range of the memory area for which the data "0" or "1" stored in the most significant bit is set in the top aggregation area 74v.

The memory areas set in the address range of "0008H" to "000DH" (bet number setting counter 74b, stop order type counter 74m, game status area 77, game interval area 76, pseudo bonus continuation counter 74t, and award number counter 74e) are memory areas in which "1" is not set in the most significant bit. Among the memory areas set in the address range of "0001H" to "000DH" where data is set for start commands and end commands, in a configuration in which a top-level aggregation area 74v is provided to aggregate data of "0" or "1" stored in the most significant bit of memory areas corresponding to addresses "0001H" to "0006H," no memory area is provided in which data of "0" stored in the most significant bit of memory areas corresponding to addresses "0008H" to "000DH" is set. This allows the most significant bit of data in a storage area where a "1" can be set to the most significant bit to be set in the start command and end command, while limiting the number of storage areas (most significant aggregation areas 74v) set in the main RAM 74 for aggregating the most significant bit of data.

The memory areas in which data is set for start and end commands are set in the continuous address range of "0001H" to "000DH" in the main RAM 74, which simplifies the processing configuration for specifying the address range of the memory area in which data is set for start commands and the processing configuration for specifying the address range of the memory area in which data is set for end commands.

Only a portion of the memory area of the main RAM 74 (specifically, the top-level aggregation area 74v and the game status area 77) in which data used by the presentation MPU 92 at the start of the game is stored is shared with the memory area of the main RAM 74 in which data used by the presentation MPU 92 at the end of the game is stored. In this configuration, by setting the memory areas in which data is set for start commands and end commands as memory areas in the main RAM 74 in which data used by the presentation MPU 92 at the start and end of the game is stored, it is possible to set the memory areas in which data is set for start commands and memory areas in which data is set for end commands in consecutive address ranges in the main RAM 74.

In the main RAM 74, the address range of the memory area where the data set for the start command is stored (address range "0001H" to "000DH") is the same as the address range of the memory area where the data set for the end command is stored (address range "0001H" to "000DH"), so the processing configuration for sending the start command and the processing configuration for sending the end command can be standardized. This allows the data size of the program for sending the start command and the end command in the main ROM 73 to be reduced.

Counters for which a "1" can be set in the most significant bit of the lower area include the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s. The data of the AT continuation counter 74u is used by the presentation MPU 92 at the start of the game, but is not used by the presentation MPU 92 at the end of the game. Furthermore, the data of the number of continued games counter 74r and the total number of wins counter 74s is used by the presentation MPU 92 at the end of the game, but is not used by the presentation MPU 92 at the start of the game. If only the data used by the presentation MPU 92 at the start of the game were set as the start command and only the data used by the presentation MPU 92 at the end of the game were set as the end command, it would be necessary to provide a memory area in the main RAM 74 for setting the most significant bit data in the lower and upper areas of the number of continued games counter 74r and the most significant bit data in the lower and upper areas of the total number of wins counter 74s, separate from the memory area for setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u. In contrast, by configuring the start command and end command to set data for the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s, it is possible to use only one memory area, the top-level aggregation area 74v, for setting the "0" or "1" data stored in the most significant bit of the lower and upper areas of the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s. This reduces the data capacity of the main RAM 74 for setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the number of continued games counter 74r, and the lower and upper areas of the total number of wins counter 74s.

The production side MPU 92 converts start commands received from the main side MPU 72 into converted start commands, and converts end commands received from the main side MPU 72 into converted end commands. When converting a start command or end command received from the main side MPU 72 into a converted start command or converted end command, the production side MPU 92 sets the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) to the most significant bit in the second to seventh frames FR2 to FR7 corresponding to those bits 0 to 5. This allows the production side MPU 92 to use a converted start command or converted end command in which the most significant bit in frames other than the header HD can also be set to "1," while the most significant bit in frames other than the header HD included in the start command or end command sent from the main side MPU 72 to the production side MPU 92 is set to "0."

In a start command or end command, the frames in which the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) is set as the most significant bit are the consecutive second to seventh frames FR2 to FR7. This simplifies the processing configuration for the production-side MPU 92 to specify the frames in which the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF is set as the most significant bit.

Only a portion of the first through fifteenth frames FR1 through FR15 included in the start command are set in the converted start command. This allows the master MPU 72 to send a start command that includes data other than that used by the production MPU 92 at the start of the game, while reducing the data size of the converted start command stored in the command storage buffer 126 and used by the production MPU 92. Furthermore, only a portion of the first through fifteenth frames FR1 through FR15 included in the end command are set in the converted end command. This allows the master MPU 72 to send a end command that includes data other than that used by the production MPU 92 at the end of the game, while reducing the data size of the converted end command stored in the command storage buffer 126 and used by the production MPU 92. This reduces the data size of the command storage buffer 126.

Of the first to fifteenth frames FR1 to FR15 included in the start command, the frames that the production side MPU 92 sets in the converted start command are different from the frames of the first to fifteenth frames FR1 to FR15 included in the end command that the production side MPU 92 sets in the converted end command. Therefore, in a configuration in which the address range of the memory area of the main RAM 74 storing the data set in the start command sent from the main MPU 72 to the production MPU 92 at the start of the game is the same as the address range of the memory area of the main RAM 74 storing the data set in the end command sent from the main MPU 72 to the production MPU 92 at the end of the game, the production MPU 92 can use the converted start command at the start of the game, in which only the data required by the production MPU 92 at the start of the game is set between the header HD and footer FT, and at the end of the game, the production MPU 92 can use the converted end command in which only the data required by the production MPU 92 at the end of the game is set between the header HD and footer FT.

The transfer target range in the top-level aggregation process (Figure 51) is the consecutive address range from "0001H" to "0006H" in the main RAM 74. The source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source counter 116 in the main RAM 74 by 1 (processing in step S2909). This simplifies the processing configuration for sequentially updating the source memory area.

Since the transfer target range in the top-level aggregation process (Figure 51) is the consecutive address range from "0001H" to "0006H" in the main RAM 74, the transfer target range can be specified by setting the start address of the transfer target range, "0001H," in the transfer source counter 116 in step S2904, and setting the number of transfers, "6," in the transfer count counter 114 in step S2905. This simplifies the processing configuration for specifying the transfer target range.

The transfer target range in the common command transmission process (Figure 50) is the consecutive address range from "0001H" to "000DH" in the main RAM 74. The source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source counter 116 in the main RAM 74 by 1 (processing in step S2816). This simplifies the processing configuration for sequentially updating the source memory area.

Since the transfer target range in the common command transmission process (Figure 50) is the consecutive address range from "0001H" to "000DH" in the main RAM 74, the transfer target range can be specified by setting the start address of the transfer target range, "0001H," in the transfer source counter 116 in step S2809, and setting the number of transfers, "13," in the transfer count counter 114 in step S2810. This simplifies the processing configuration for specifying the transfer target range.

During the top-level setting process (Figure 53), the addresses of areas RA2 to RA7, whose most significant bits are set to the data "0" or "1" stored in bits 0 to 5 of the top-level aggregated frame SF, are in the consecutive address range of "α+2" to "α+7." The destination memory areas can be updated sequentially by repeatedly adding 1 to the value of the director's destination counter (step S3110). This simplifies the processing configuration for sequentially updating the destination memory areas.

The value of the production-side bit designation counter in the production-side RAM 94 is incremented by 1 each time the process of transferring "0" or "1" data stored in any of bits 0 through 5 of the most significant aggregated frame SF to the most significant bit in the destination memory area (processing in step S3107) is executed. Therefore, by referencing the value of the production-side bit designation counter, it is possible to determine the number of times that "0" or "1" data set in any of bits 0 through 5 of the most significant aggregated frame SF has been transferred to the second through seventh frames FR2 through FR7 corresponding to that bit. This simplifies the processing configuration for determining the number of transfers in the production-side MPU 92.

When converting a start command or end command set in the pre-conversion area 124 into a converted start command or a converted end command by transferring data for some of the first through fifteenth frames FR1 through FR15 contained in the start command or end command set in the pre-conversion area 124 to the converted area 125, the source memory area in the pre-conversion area 124 is updated in a manner that excludes areas that are subject to exclusion. On the other hand, the destination memory area in the converted area 125 is updated in a manner that the memory area set next to the current destination memory area in the converted area 125 becomes the updated destination memory area. As a result, when a start command is received, data to be used by the production side MPU 92 at the start of the game can be extracted from the start command and set as the converted start command. Also, when an end command is received, data to be used by the production side MPU 92 at the end of the game can be extracted from the end command and set as the converted end command.

The presentation-side MPU 92 converts the start command received from the main MPU 72 into a converted start command and executes processing to execute the presentation of the currently started game based on the converted start command. The converted start command contains data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 in the main RAM 74. Because the data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 is available when a start command is received, the number of commands sent from the main MPU 72 to the presentation-side MPU 92 can be reduced compared to a configuration in which the data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 is received in two or more commands. This reduces the processing load when the main MPU 72 sends commands to the production MPU 92, and also reduces the processing load when the production MPU 92 executes processing corresponding to commands received from the main MPU 72.

The presentation-side MPU 92 converts the end command received from the main MPU 72 into a converted end command and executes processing to execute the presentation based on the converted end command. The converted end command contains data for the number of continuing games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and number of awarded bonuses counter 74e stored in the main RAM 74. This configuration makes the data for the number of continuing games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and number of awarded bonuses counter 74e available when the end command is received. This reduces the number of commands sent from the main MPU 72 to the presentation-side MPU 92 compared to a configuration in which the data for the number of continuing games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and number of awarded bonuses counter 74e is received using two or more commands. This reduces the processing load when the main MPU 72 sends commands to the production MPU 92, and also reduces the processing load when the production MPU 92 executes processing corresponding to commands received from the main MPU 72.

<Configuration of main MPU 72>
Next, we will explain the configuration of the main MPU 72. Figure 61(a) is an explanatory diagram for explaining the configuration of the main MPU 72.

As shown in FIG. 61(a), the main MPU 72 has the following general-purpose registers: W register 101a, A register 101b, B register 102a, C register 102b, D register 103a, E register 103b, H register 104a, and L register 104b. These eight general-purpose registers are 1-byte registers. These general-purpose registers can also be used as pair registers by combining two corresponding general-purpose registers. Specifically, the W register 101a and the A register 101b can be combined to form the 2-byte WA register 101, and the B register 102a and the C register 102b can be combined to form the 2-byte BC register 102. Furthermore, the D register 103a and the E register 103b can be combined to form the 2-byte DE register 103, and the H register 104a and the L register 104b can be combined to form the 2-byte HL register 104.

The main MPU 72 is equipped with a program counter PC. The program counter PC stores the storage address of the next instruction to be fetched by the main MPU 72, and its value is incremented by 1 each time one byte of instruction is fetched. Except when a jump or call instruction is executed, the main MPU 72 processes instructions stored in the main ROM 73 in order from low addresses (smaller program addresses) to high addresses (larger program addresses).

As shown in FIG. 61(a), the main MPU 72 has a zero flag ZF, a carry flag CF, and a jump flag JF. The zero flag ZF consists of one bit. The zero flag ZF is a flag that is set to "1" when the register content after an operation is "0" and set to "0" when the register content after an operation is not "0." The carry flag CF consists of one bit. The carry flag CF is set to "1" when a carry occurs from the most significant bit (the seventh bit of the 0th to 7th bits) during execution of an 8-bit arithmetic instruction, an ADD instruction (addition instruction), and is set to "0" when no carry occurs from the most significant bit (the seventh bit). The carry flag CF is set to "1" when a borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) during execution of an 8-bit arithmetic instruction, a SUB instruction (subtraction instruction), and is set to "0" when no borrow occurs to the most significant bit (the seventh bit). The jump flag JF is a flag that takes on the same value as the zero flag ZF or the carry flag CF, depending on the executed instruction. The jump flag JF consists of one bit. When the OUT instruction, which is an output instruction, the XOR instruction, which is an instruction that calculates an exclusive OR, or the LD instruction, which is a transfer instruction, is executed, the jump flag JF takes on the same value as the zero flag ZF. Specifically, the jump flag JF takes on the same value as the carry flag CF when the CP instruction, which is a comparison instruction, or the SUB instruction, which is a subtraction instruction, is executed ...CF instruction is 1 when the carry flag CF is 0 when the carry flag CF is 0 when the carry flag CF is 1 when the carry flag CF is 0 when the carry flag CF is 1 when the carry flag CF is 0 when the jump flag JF is 1 when the carry flag CF is 0 when the carry flag CF is 1 when the carry flag CF is 0 when the jump flag JF is 1 when the carry flag CF is 0 when the carry flag CF is 1 when the carry flag CF is 0 when the jump flag JF is 1 when the carry flag CF is 0 when the carry flag CF is 1 when the carry flag CF is 0 when the carry flag CF is 1 when the carry flag CF is 0 when the jump flag JF is referenced by the JRS instruction, which will be described later.

Figure 61(b) is an explanatory diagram illustrating how data and programs are set in the main ROM 73. As shown in Figure 61(b), addresses from "9000H" to "9EFFH" are assigned to the main ROM 73. The main ROM 73 has many 1-byte areas, and a 2-byte address is set for each of these 1-byte areas.

In the main ROM 73, data used to execute various processes is stored in a consolidated manner in consecutive address areas in the address range of "9000H" to "98FFH." The address range of "9900H" to "9902H," which is consecutive to the address range of "9000H" to "98FFH," is an unused area where no data is stored, followed by consecutive address areas in the address range of "9903H" to "9EFFH," where programs for executing various processes are stored in a consolidated manner. The address range of "9F00H" to "9F02H," which is consecutive to the address range of "9903H" to "9EFFH," is an unused area where no data is stored. The relationship between the data and programs and addresses described above is set both in physical addresses in the main ROM 73 and in logical addresses on the memory map recognized by the main MPU 72.

In the main ROM 73, data and programs are stored in areas with different address ranges, regardless of the order in which they are executed, which allows for efficient work when checking data and programs separately. Furthermore, an address range for an unused area in which no data is stored is set between the address range of the area in which data is stored and the address range of the area in which programs are stored, making it easier to grasp the boundary between the address range of data and the address range of programs when checking.

Next, before explaining the contents of the power-off standby processing program executed by the main MPU 72 (Figure 62 (b)), we will explain the jump instructions, including the JRS instruction, set in the power-off standby processing program.

Figure 62(a) is an explanatory diagram illustrating the types of jump instructions executed by the main MPU 72. As shown in Figure 62(a), the jump instructions executed by the main MPU 72 include the JP instruction, the JR instruction, and the JRS instruction. As shown in Figure 61(a), the main MPU 72 is equipped with a JP execution circuit 105, a JR execution circuit 106, and a JRS execution circuit 107. The JP execution circuit 105 is a dedicated circuit for executing the JP instruction, the JR execution circuit 106 is a dedicated circuit for executing the JR instruction, and the JRS execution circuit 107 is a dedicated circuit for executing the JRS instruction.

As shown in Figure 62 (a), the JP instruction is an instruction that specifies the entire 2-byte program address (absolute address) that is the jump destination, and jumps to that jump destination program address. The word length (machine language data capacity) of the JP instruction is 3 bytes, and the machine language of the JP instruction contains the entire 2-byte program address that specifies the jump destination. By using the JP instruction, it is possible to jump to any address included in the address range ("9903H" to "9EFFH") in which programs are stored in the main ROM 73, regardless of the program address for which the JP instruction is set.

The JR and JRS instructions use differential information from the program address where the JR or JRS instruction is set to specify a two-byte program address as the jump destination, and then jump to the specified jump destination program address. The word length (machine language data capacity) of a JR instruction is two bytes, and the machine language of the JR instruction contains one byte of data specifying part of the jump destination program address. The JR instruction contains eight bits, including one code bit and seven numeric bits, that specify the differential information from the program address where the JR instruction is set. The JR instruction relatively specifies the jump destination program address (two bytes) based on the program address where the JR instruction is set and the differential information (eight bits) set in the JR instruction. In this way, the data capacity of the information (difference information) set in the JR instruction to specify the two-byte jump destination program address is limited to eight bits, thereby reducing the data capacity of the machine language of the JR instruction. Therefore, by using a two-byte JR instruction, the machine language data capacity of the jump instruction for jumping to the jump destination program address can be reduced compared to using a three-byte JP instruction. The range that can be jumped with the JR instruction is from "(the program address where the JR instruction is set) +2 - 128" to "(the program address where the JR instruction is set) +2 + 127". Of this, "+2" corresponds to the word length (2 bytes) of the JR instruction itself, and "-128 to 127" is a numerical range that can be specified using a total of 8 bits: 1 bit for the code and 7 bits for the value.

The JRS instruction contains five bits, including one sign bit and four numeric bits, that specify the difference from the program address where the JRS instruction is set. The JRS instruction relatively identifies the jump destination program address (two bytes) based on the program address where the JRS instruction is set and the five-bit difference information set in the JRS instruction. In this way, the data size of the information (difference information) set in the JRS instruction to specify the two-byte jump destination program address is limited to five bits, reducing the machine code data size of the JRS instruction. Therefore, by using a one-byte JRS instruction, the machine code data size of the jump instruction for jumping to the jump destination program address can be reduced compared to using a three-byte JP instruction or a two-byte JR instruction. The range that can be jumped with the JRS instruction is between "(the program address where the JRS instruction is set) + 1 - 16" and "(the program address where the JRS instruction is set) + 1 + 15." Of these, "+1" corresponds to the word length (1 byte) of the JRS instruction itself, and "-16 to 15" is a numerical range that can be specified using a total of 5 bits: 1 bit for the code and 4 bits for the value.

The JP and JR instructions include conditional jumps, which jump if the referenced flag is in a specified state, and unconditional jumps, which jump unconditionally without reference to the state of the flag. The JP and JR instructions reference the zero flag ZF or the carry flag CF. The main MPU 72 can execute a JP instruction that jumps if the zero flag ZF has a value of "1," a JP instruction that jumps if the zero flag ZF has a value of "0," a JP instruction that jumps if the carry flag CF has a value of "1," and a JP instruction that jumps if the carry flag CF has a value of "0." The main MPU 72 can also execute a JR instruction that jumps if the zero flag ZF has a value of "1," a JR instruction that jumps if the zero flag ZF has a value of "0," a JR instruction that jumps if the carry flag CF has a value of "1," and a JR instruction that jumps if the carry flag CF has a value of "0."

The word length of a JRS instruction (1 byte) is shorter than the word length of a JP instruction (3 bytes) and the word length of a JR instruction (2 bytes). To enable the word length to be shortened, the JRS instruction only provides conditional jumps that jump when the referenced flag is in a specified state; it does not provide unconditional jumps that jump unconditionally without reference to the state of the flag. Also, to enable the word length to be shortened, the flag that is referenced in a JRS instruction is limited to the jump flag JF. The main MPU 72 can execute a JRS instruction that jumps when the value of the jump flag JF is "1", and a JRS instruction that jumps when the value of the jump flag JF is "0".

The value of the jump flag JF is maintained even when a JRS instruction is executed. The value of the jump flag JF does not change before or after the JRS instruction is executed. Therefore, a jump can be made to the program address of the jump destination set in the JRS instruction while maintaining the value of the jump flag JF before the JRS instruction is executed, and the instruction set in the program address of the jump destination can be executed based on the value of the jump flag JF before the JRS instruction is executed.

Next, the contents of the power-off standby processing program executed by the main MPU 72 will be explained with reference to the explanatory diagram in Figure 62 (b). As already explained, the power-off standby processing is executed in step S119 of the main processing (Figure 10), and also in step S308 of the power outage processing (Figure 12). As shown in Figure 62 (b), this program has line numbers "1001" to "1002". Program instructions are executed in order from lowest to highest line number, except when a call or jump instruction is executed.

As shown in Figure 62(b), the instruction "OUT (WDTCLR0), 18H" is set in line number "1001." "OUT" is an output instruction. "WDTCLR0" is a one-byte port number used to output initial value data from the main MPU 72 to the watchdog timer 86a, and "18H" is one-byte numerical information indicating the initial value ("24") to be set in the watchdog timer 86a. Executing the instruction "OUT (WDTCLR0), 18H" in line number "1001" sets the watchdog timer 86a to the initial value "18H" ("24"). This initializes the watchdog timer 86a, restoring it to a state in which the time required for the watchdog timer 86a to underflow is 240 milliseconds.

As already explained, the watchdog timer 86a is a down counter that is updated by subtracting 1 at a predetermined interval (specifically, once every 10 milliseconds). The watchdog timer 86a underflows if an initial value is not set for 240 milliseconds. When the watchdog timer 86a underflows, a reset signal is output to the input port of the MPU 72. When this reset signal is received, the MPU 72 initiates processing to reset the program.

The instruction "JRS 0, ADR101" is set in line number "1002." "JRS" is a conditional jump instruction with a word length of 1 byte. "0" sets the condition for jumping to the destination program address: the value of the jump flag JF must be "0." "ADR101" specifies the program address where the instruction "OUT (WDTCLR0), 18H" is set in line number "1001" as the destination program address. The instruction in line number "1002" is set to program address "ADR102." As already explained, the range that can be jumped with the JRS instruction is from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in Figure 62(b), an OUT instruction with a word length of 3 bytes is set in line number "1001." "ADR101" is "(ADR102) + 1 - 4", and is a program address within the range that can be specified as the jump destination program address for the JRS instruction, based on the program address (ADR102) where the JRS instruction on line number "1002" is set. On line number "1002", if the jump flag JF is set to "0", a jump will be made to the program address on line number "1001", where the instruction "OUT (WDTCLR0), 18H" is set.

Figure 62(c) is an explanatory diagram illustrating the state of the jump flag JF after the instruction "OUT (WDTCLR0), 18H" is executed on line number "1001." As already explained, the jump flag JF after the OUT instruction is executed takes the same value as the zero flag ZF. When the OUT instruction "OUT (WDTCLR0), 18H" is executed on line number "1001," the value of the zero flag ZF becomes "0." Therefore, the state of the jump flag JF after the OUT instruction is executed becomes "0," the same as the value of the zero flag ZF, and a jump to line number "1001" is performed by executing the JRS instruction "JRS 0, ADR101" on line number "1002." The instructions on lines "1001" to "1002" are then repeatedly executed until the supply of operating power to the primary MPU 72 is stopped. This allows the process of setting the watchdog timer 86a to an initial value to be repeatedly executed. The interval at which the watchdog timer 86a is set to an initial value during the power-off standby process is shorter than the time (specifically, 240 milliseconds) required for the value of the watchdog timer 86a to underflow after the initial value is set to the watchdog timer 86a. This prevents the value of the watchdog timer 86a from underflowing, which would otherwise trigger the process to reset the program of the main MPU 72.

A JRS instruction with a word length of 1 byte is set as the instruction to jump from the program address ("ADR102") of line number "1002" to the program address ("ADR101") of line number "1001". This reduces the data size of the power cutoff standby processing program compared to a configuration in which a JR instruction with a word length of 2 bytes or a JP instruction with a word length of 3 bytes is set as the instruction to jump from the program address of line number "1002" to the program address of line number "1001".

As already explained, the JRS instruction only provides a conditional jump that jumps when the referenced flag is in a specific state; it does not provide an unconditional jump that jumps unconditionally without referencing the state of the flag. The JRS instruction set on line number "1002" is a conditional jump instruction that jumps to the program address on line number "1001" when the value of jump flag JF is "0." However, during power-off standby processing, the state of jump flag JF always becomes "0" after the OUT instruction on line number "1001" is executed. Therefore, while using the JRS instruction, which is a conditional jump instruction with a short word length, the instructions set on lines "1001" to "1002" can be repeatedly executed.

<Configuration for externally outputting AT status signal>
Next, a configuration for externally outputting the AT status signal will be described. The slot machine 10 outputs various signals including the AT status signal (specifically, the AT status signal, the pseudo bonus status signal, the number of inserted coins signal, and the number of paid out coins signal) to a hall computer HC located outside the slot machine 10. The hall computer HC is a management computer installed in the gaming hall. The AT status signal is a signal that enables the hall computer HC to determine that the current gaming status of the slot machine 10 is the AT status ST5. The main MPU 72 raises the AT status signal from the LOW status to the HIGH status when the gaming status transitions to the AT status ST5, and lowers the AT status signal from the HIGH status to the LOW status when the AT status ST5 ends.

Figure 63(a) is an explanatory diagram illustrating the configuration for external output from the slot machine 10 to the hall computer HC. As shown in Figure 63(a), the main MPU 72 has an output port 108. The slot machine 10 has an external terminal board 109 for externally outputting various signals. The external terminal board 109 is provided with an AT status signal terminal 109a for externally outputting an AT status signal. The output port 108 is electrically connected to the AT status signal terminal 109a. The main MPU 72 outputs the AT status signal to the hall computer HC via the AT status signal terminal 109a.

The hall computer HC determines that the AT state ST5 has started when it detects a rise from a LOW state to a HIGH state in the AT state signal input from the slot machine 10, and determines that the AT state ST5 has ended when it detects a fall from a HIGH state to a LOW state in the AT state signal. The hall computer HC may also be configured to determine that the gaming state is in the AT state ST5 when the AT state signal input from the slot machine 10 is in the HIGH state, and to determine that the gaming state is not in the AT state ST5 when the AT state signal is in the LOW state.

The hall computer HC transmits information to a data counter DC installed in the gaming hall based on signals received from the slot machines 10. The data counter DC is mounted above the corresponding slot machine 10, and displays the number of games that have been played since the non-AT state began. The non-AT state ends when the gaming state transitions to AT state ST5, and begins when the AT state ST5 ends. Note that the AT state signal terminal 109a may be electrically connected to the data counter DC, and the main MPU 72 may externally output an AT state signal to the data counter DC.

Next, the external output setting process executed by the main MPU 72 will be described with reference to the flowchart in Figure 63 (b). The external output setting process is executed in step S411 of the normal process (Figure 13).

In the external output setting process, an AT status signal setting process is executed to set the state of the AT status signal (step S3901). Figure 63 (c) is an explanatory diagram illustrating the relationship between the value of the AT status flag 77d and the value of the AT status signal counter 74w and the AT status signal. In the AT status signal setting process in step S3901 of the external output setting process (Figure 63 (b)), if the AT status flag 77d in the main RAM 74 is set to "1" and the value of the AT status signal counter 74w is "0," i.e., if the AT status signal start-up process has not been performed since the game state transitioned to AT status ST5, the AT status signal is raised from the LOW state to the HIGH state by executing the AT status signal start-up process. The AT status signal counter 74w is then set to "1." This allows the main MPU 72 to determine that the AT status signal is in the HIGH state. The state in which the AT state flag 77d is set to "1" and the value of the AT state signal counter 74w is "0" is a state that occurs when AT state ST5 starts. In the AT state signal setting process in step S3901, if the AT state flag 77d and the AT state signal counter 74w in the main RAM 74 are set to "1", no process is performed to change the state of the AT state signal. This maintains the HI state of the AT state signal. The state in which the AT state flag 77d and the AT state signal counter 74w are set to "1" is a state that occurs when AT state ST5 continues.

In the AT status signal setting process in step S3901, if the value of the AT status flag 77d in the main RAM 74 is "0" and the value of the AT status signal counter 74w is "1," i.e., if the AT status signal has not been turned off since AT status ST5 ended, the AT status signal is turned off, causing the AT status signal to rise from a HIGH state to a LOW state. The value of the AT status signal counter 74w is then cleared to "0." This allows the main MPU 72 to determine that the AT status signal is in a LOW state. The state in which the value of the AT status flag 77d is "0" and the value of the AT status signal counter 74w is "1" occurs when AT status ST5 ends. In the AT status signal setting process in step S3901, if the values of the AT status flag 77d and the AT status signal counter 74w in the main RAM 74 are "0," no processing is performed to change the state of the AT status signal. This maintains the LOW state of the AT status signal. The state in which the values of the AT state flag 77d and the AT state signal counter 74w are "0" occurs when the gaming state continues to be in a state other than the AT state ST5 (non-AT state).

Returning to the explanation of the external output setting process (Figure 63 (b)), after executing the AT state signal setting process in step S3901, other signal setting process is executed (step S3902), and this external output setting process is terminated. In the other signal setting process in step S3902, a process is executed to set the state of the pseudo bonus state signal output to the hall computer HC via the external terminal board 109. The pseudo bonus state signal is a signal that allows the hall computer HC to determine whether the gaming state is in the pseudo bonus state ST4. When the pseudo bonus state ST4 starts, the main MPU 72 raises the pseudo bonus state signal from the LOW state to the HIGH state, and when the pseudo bonus state ST4 ends, the main MPU 72 lowers the pseudo bonus state signal from the HIGH state to the LOW state.

Next, the program contents of the AT status signal setting process executed by the main MPU 72 will be explained with reference to the explanatory diagram in Figure 64 (a). The AT status signal setting process is executed in step S3901 of the external output setting process (Figure 63 (b)). As shown in Figure 64 (a), this program has line numbers "1101" to "1117". Program instructions are executed in order from lowest to highest line number, except when a call instruction or jump instruction is executed.

As shown in Figure 64 (a), the instruction "LD A, (YGJTAR)" is set in line number "1101." "LD" is the LD instruction as an 8-bit transfer instruction, and "A" specifies the A register 101b as the transfer destination. "YGJTAR" is the address (2 bytes) of the game status area 77 in the main RAM 74. "(YGJTAR)" specifies the game status area 77 as the transfer source. When the instruction "LD A, (YGJTAR)" is executed in line number "1101," the data in the game status area 77 is transferred to A register 101b.

The instruction "AND A, 08H" is set in line number "1102." "AND" is an AND instruction that calculates the logical product of 8-bit data, and "A" is the A register 101b. As mentioned above, the data in the game status area 77 is set in A register 101b when the LD instruction in line number "1101" is executed. As already explained with reference to Figure 31(b), the AT status flag 77d is set in the third bit of the game status area 77. "08H" is mask data "00001000B" that masks all bits of the data stored in A register 101b with "0" except for the third bit, which is set by the data in the AT status flag 77d. Execution of the instruction "AND A, 08H" in line number "1102" performs a logical product operation between the data stored in A register 101b and the mask data, and the result of this operation is stored in A register 101b. The value of A register 101b is "08H" if the AT status flag 77d is set to "1", and is "00H" if the value of the AT status flag 77d is set to "0".

The instruction "CP A, 08H" is set on line number "1103." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "08H" is one byte of numerical information. Executing the instruction "CP A, 08H" on line number "1103" subtracts "08H" from the value of the A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. As described above, after the instruction "AND A, 08H" on line number "1102" is executed, the value of the A register 101b is "08H" if the AT status flag 77d is set to "1", and is "00H" if the value of the AT status flag 77d is "0". When the AT status flag 77d is set to "1", the instruction "CP A, 08H" on line number "1103" is executed, and an operation is performed to subtract "08H" from "08H" stored in the A register 101b, so no borrow to the most significant bit occurs, and the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, if the value of AT status flag 77d is "0", the instruction "CP A, 08H" is executed on line number "1103", which causes an operation to subtract "08H" from "00H" stored in A register 101b, resulting in a borrow to the most significant bit, causing the value of carry flag CF to become "1", and the value of jump flag JF to become "1". The result of the operation to subtract "08H" from the value of A register 101b is not written to A register 101b. The value of A register 101b does not change even when the instruction "CP A, 08H" is executed.

The instruction "JRS 0, ADR113" is set on line number "1104." "JRS" is a conditional jump instruction with a word length of 1 byte. "0" sets the jump condition to a value of "0" for the jump flag JF. "ADR113" specifies "ADR113," the program address where the LD instruction on line number "1111" is set, as the jump destination program address. The JRS instruction on line number "1104" is set to the program address "ADR111." The JRS instruction on line number "1104" relatively identifies the 2-byte jump destination program address (ADR113) based on the program address (ADR111) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. Because the jump to the destination program address is performed using a 1-byte JRS instruction, the machine code data size of the jump instruction for jumping to the destination program address is reduced compared to a configuration using a 3-byte JP instruction or a 2-byte JR instruction. As already explained, the range that can be jumped to using the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in FIG. 64(a), the total word length of the instructions set at the program addresses between the program addresses "ADR111" and "ADR113" (the LD instruction at line number "1105," the CP instruction at line number "1106," the RET instruction at line number "1107," the CALL instruction at line number "1108," the XOR instruction at line number "1109," and the JRS instruction at line number "1110") is 11 bytes. "ADR113" is "(ADR111) + 1 + 11", and is a program address that can be specified as the program address of the jump destination in the JRS instruction based on the program address (ADR111) where the JRS instruction on line number "1104" is set. When the instruction "JRS 0, ADR113" is executed on line number "1104", a jump is made to the program address "ADR113" on line number "1111", provided that the value of the jump flag JF is "0". Specifically, when "1" is set in the AT status flag 77d, a jump is made to the program address "ADR113" on line number "1111" by executing the instruction "JRS 0, ADR113" on line number "1104". On the other hand, if the value of the AT status flag 77d is "0", even if the instruction "JRS 0, ADR 113" is set in line number "1104", the program address will not jump and will proceed to the next line number "1105".

The instructions set in line numbers "1105" to "1110" are instructions that are executed when the game state is not AT state ST5 (non-AT state). The instruction "LD A, (AJSGCNT)" is set in line number "1105." "LD" is an LD instruction as an 8-bit transfer instruction, and "A" specifies A register 101b as the transfer destination. "AJSGCNT" is the address (2 bytes) of the AT state signal counter 74w in the main RAM 74. "(AJSGCNT)" specifies the AT state signal counter 74w as the transfer source. When the instruction "LD A, (AJSGCNT)" is executed in line number "1105," the data of the AT state signal counter 74w is transferred to A register 101b. As already explained, the value of the AT status signal counter 74w is "1" when the AT status signal is in the HI state, and is "0" when the AT status signal is in the LOW state.

The instruction "CP A, 01H" is set on line number "1106." "CP" is a CP instruction for comparing 8-bit data, "A" is the A register 101b, and "01H" is one byte of numerical information. Execution of the "CP A, 01H" instruction on line number "1106" subtracts "01H" from the value of the A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the carry flag CF is set to "1." If no borrow to the most significant bit occurs during this operation, the carry flag CF is set to "0." As mentioned above, after execution of the instruction "LD A, (AJSGCNT)" on line number "1105," the data of the AT status signal counter 74w ("00H" or "01H") is set in the A register 101b. When the value of the AT status signal counter 74w is "1", the instruction "CP A, 01H" is executed on line number "1106", which causes an operation to subtract "01H" from the "01H" stored in the A register 101b, so no borrow occurs to the most significant bit and the value of the carry flag CF becomes "0". On the other hand, when the value of the AT status flag 77d is "0", the instruction "CP A, 01H" is executed on line number "1106", which causes an operation to subtract "01H" from the "00H" stored in the A register 101b, so a borrow occurs to the most significant bit and the value of the carry flag CF becomes "1".

The instruction "RET C" is set on line number "1107." "RET" is an instruction to return from a subroutine, and "C" sets the condition for returning from a subroutine: the value of the carry flag CF must be "1." As described above, if the value of the AT status signal counter 74w is "0," the instruction "CP A, 01H" is executed on line number "1106," causing the value of the carry flag CF to become "1." Therefore, if the value of the AT status signal counter 74w is "0," the instruction "RET C" is executed on line number "1107," terminating the AT status signal setting process called in step S1411 of the port output process (Figure 28) and returning to the process of step S1411 set next to the AT status signal setting process. In this way, if the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "0", it means that the gaming state will continue to be a state other than the AT state ST5 (non-AT state), so the AT state signal setting process is terminated without changing the state in which the AT state signal is in the LOW state. On the other hand, as described above, if the value of the AT state signal counter 74w is "1", the instruction "CP A, 01H" is executed in line number "1106", causing the value of the carry flag CF to be "0". Therefore, even if the instruction "RET C" is set in line number "1107", the subroutine will not be returned to and the next line number "1108" will be proceeded to. In this way, when the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "1," this means that the process of lowering the AT state signal after AT state ST5 ends (the process of line number "1108" described below) has not yet been executed, so the process proceeds to line number "1108" and lowers the AT state signal. The state in which the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "1" is the state that occurs when AT state ST5 ends.

The command "CALL AJSGTSSR" is set in line number "1108." "AJSGTSSR" is the process for lowering the AT status signal, and "CALL" is a CALL command that calls the subroutine for the process for lowering the AT status signal. The command "CALL AJSGTSSR" is executed in line number "1108" to execute the process for lowering the AT status signal. In the process for lowering the AT status signal, processing is executed to change the AT status signal from HI to LOW. When the process for lowering the AT status signal is completed, the process proceeds to line number "1109," which is set next to line number "1108," which called the process for lowering the AT status signal.

The instruction "XOR A,A" is set in line number "1109." "XOR" is an exclusive OR instruction called an XOR instruction, and the "A" before and after the comma specify A register 101b. When "XOR A,A" is executed in line number "1109," the result of the exclusive OR operation between the value of A register 101b and the value of A register 101b is set in A register 101b specified by the "A" before the comma. Specifically, regardless of the value of A register 101b, "00H" is set in A register 101b. In other words, A register 101b is cleared to "0." In the AT status signal setting process, the data in A register 101b is set in the AT status signal counter 74w in the main RAM 74 in line number "1116," which will be described later. The A register 101b is a register in which the data to be set in the AT status signal counter 74w is set, and the instruction "XOR A, A" is an instruction to clear the A register 101b to "0". As mentioned above, the result of the operation performed by the instruction "XOR A, A" is "0". Also, as already explained, the jump flag JF takes on the same value as the zero flag ZF when the XOR instruction is executed. Therefore, when the instruction "XOR A, A" is executed on line number "1109", the value of the zero flag ZF becomes "1" and the value of the jump flag JF becomes "1".

The instruction "JRS 1, ADR114" is set on line number "1110." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" sets the jump condition to the value of the jump flag JF being "1," and "ADR114" specifies the program address "ADR114" at line number "1116" as the jump destination. The instruction "JRS 1, ADR114" on line number "1110" is set to the program address "ADR112." As already explained, the range that can be jumped with the JRS instruction is from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in FIG. 64(a), the total word length of the instructions set at the program addresses between program addresses "ADR112" and "ADR114" (the LD instruction at line number "1111", the CP instruction at line number "1112", the RET instruction at line number "1113", the CALL instruction at line number "1114", and the LD instruction at line number "1115") is 11 bytes. "ADR114" is "(ADR112) + 1 + 11", and is a program address that can be specified as the program address to jump to in the JRS instruction based on the program address (ADR112) at which the JRS instruction at line number "1110" is set. As described above, when the instruction "XOR A, A" is executed at line number "1109", the value of the zero flag ZF becomes "1" and the value of the jump flag JF also becomes "1". Therefore, by executing the instruction "XOR A, A" on line number "1109" and then the instruction "JRS 1, ADR114" on line number "1110", it is possible to always jump from the program address "ADR112" on line number "1110" to the program address "ADR114" on line number "1116".

As explained above, the 1-byte JRS instruction only provides a conditional jump instruction that jumps to a destination program address when the jump flag JF is set to either "1" or "0." By executing the "XOR A, A" instruction on line "1109" and setting the jump flag JF to "1," and then executing the "JRS 1, ADR114" instruction on line "1110," a jump from line "1110" to line "1116" can be reliably performed. As mentioned above, the "XOR A, A" instruction set on line "1109" is an instruction to clear the data in the A register 101b to "0," which is set in the AT status signal counter 74w on line "1116," as described below. The instruction "XOR A, A" set on line number "1109" is also an instruction that makes it possible to reliably jump to the program address "ADR114" on line number "1116" using the 1-byte JRS instruction on line number "1110." By combining these two roles into the XOR instruction on line number "1109," the data size of the program for executing the AT status signal setting process is reduced.

The instruction set in line number "1111" is executed when there is a jump from line number "1104" to line number "1111." As already explained, if AT state flag 77d is set to "1," the instruction "JRS 0, ADR113" is executed in line number "1104," causing a jump to the program address "ADR113" at line number "1111." The instructions set in line numbers "1111" to "1115" are instructions executed in AT state ST5.

In line number "1111," the instruction "LD A, (AJSGCNT)" is set, just like in line number "1105." By executing the instruction "LD A, (AJSGCNT)" in line number "1111," the data in the AT status signal counter 74w is transferred to the A register 101b. As already explained, the value of the AT status signal counter 74w is "1" when the AT status signal is in the HI state, and "0" when the AT status signal is in the LOW state.

The instruction "CP A, 01H" is set for line number "1112," just like line number "1106." Executing the instruction "CP A, 01H" on line number "1112" performs an operation to subtract "1" from the value of A register 101b. If the value of A register 101b before the subtraction is "0," i.e., if the value of AT status signal counter 74w is "0," a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs in the operation, and the value of carry flag CF becomes "1." On the other hand, if the value of A register 101b before the subtraction is "1" or greater, i.e., if the value of AT status signal counter 74w is "1," no borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs in the operation, and the value of carry flag CF becomes "0." The result of the operation to subtract "1" from the value of A register 101b is not written to A register 101b, and the value of A register 101b does not change even when the instruction "CP A,01H" is executed.

The instruction "RET NC" is set in line number "1113." "RET" is a subroutine return instruction, and "NC" sets the condition for returning from a subroutine: the carry flag CF must be set to "0." As described above, if the AT status signal counter 74w has a value of "1," the instruction "CP A, 01H" is executed in line number "1112," setting the carry flag CF to "0." Therefore, if the AT status signal counter 74w has a value of "1," the instruction "RET NC" is executed in line number "1113," terminating the currently called subroutine and returning to the process set next to the process that called the subroutine. Specifically, the process returns to step S3902, which is the process following step S3901 in the external output setting process (FIG. 63(b)). Thus, when the value of the AT state flag 77d is "1" and the value of the AT state signal counter 74w is "1," this means that the AT state ST5 continues, and the AT state signal setting process is terminated without changing the HI state of the AT state signal. On the other hand, as described above, when the value of the AT state signal counter 74w is "0," the instruction "CP A, 01H" is executed in line number "1112," causing the value of the carry flag CF to become "1." Therefore, even if the instruction "RET NC" is set in line number "1113," the subroutine is not returned to, and the process proceeds to the next line number "1114." Thus, when the value of the AT state flag 77d is "1" and the value of the AT state signal counter 74w is "0," this means that the process of raising the AT state signal after the game state transitions to AT state ST5 (the process of line number "1114" described below) has not yet been executed, so the process proceeds to line number "1114" and raises the AT state signal. The state in which the value of the AT state flag 77d is "1" and the value of the AT state signal counter 74w is "0" occurs at the start of AT state ST5.

The instruction "CALL AJSGTASR" is set in line number "1114." "AJSGTASR" is the AT status signal rise process, and "CALL" is a CALL instruction that calls the subroutine for the AT status signal rise process. The AT status signal rise process is executed by executing the instruction "CALL AJSGTASR" in line number "1114." In the AT status signal rise process, processing is executed to change the AT status signal from a LOW state to a HIGH state. When the AT status signal rise process is completed, the process proceeds to line number "1115," the next line after line number "1114," which called the AT status signal rise process.

The instruction "LD A, 01H" is set on line number "1115." "LD" is an 8-bit transfer instruction, "A" specifies the A register 101b as the transfer destination, and "01H" is 1 byte of numerical information indicating "1." Executing the instruction "LD A, 01H" on line number "1115" sets "01H" in A register 101b.

The instruction set in line number "1116" is executed when a jump is made from the program address ("ADR112") in line number "1110" to the program address ("ADR114") in line number "1116", or when the LD instruction is executed in line number "1115". The instruction "LD (AJSGCNT), A" is set in line number "1116". "LD" is the LD instruction as an 8-bit transfer instruction, "(AJSGCNT)" specifies the AT status signal counter 74w as the transfer destination, and "A" specifies the A register 101b as the transfer source. When a jump is made from the program address of line number "1110" to the program address of line number "1116," that is, when AT state ST5 ends, the A register 101b is cleared to "0" at line number "1109," so the instruction "LD (AJSGCNT), A" is executed at line number "1116," and the AT state signal counter 74w in the main RAM 74 is set to "0." This allows the main MPU 72 to grasp that the AT state signal is in a LOW state. On the other hand, when the instruction of line number "1115" is executed, that is, when AT state ST5 begins, the A register 101b is set to "1" at line number "1115," so the instruction "LD (AJSGCNT), A" is executed at line number "1116," and the AT state signal counter 74w is set to "1." This allows the main MPU 72 to determine that the AT status signal is in the HI state.

The command "RET" is set on line number "1117." "RET" is a command to return from a subroutine. Executing the command "RET" on line number "1117" ends the currently called subroutine and returns to the process set up after the process that called the subroutine. Specifically, it returns to the process of step S3902, which is set up after the process of step S3901 in the external output setting process (Figure 63 (b)).

Figure 64(b) is an explanatory diagram illustrating a jump command set to jump from the program address "ADR112" with line number "1110" to the program address "ADR114" with line number "1116" in the AT status signal setting process (Figure 64(a)), and Figure 64(c) is an explanatory diagram illustrating a jump command set to jump from the program address "ADR112" with line number "1110" to the program address "ADR114" with line number "1116" in a comparative example of AT status signal setting process.

As already explained, the JRS instruction only provides a conditional jump, which jumps when the referenced flag is in a specified state (either when the jump flag JF is set to "1" or when the jump flag JF is set to "0"); it does not provide an unconditional jump, which jumps unconditionally without referencing the state of the flag. As mentioned above, the instruction "JRS 1, ADR114" set on line number "1110" jumps to the program address "ADR114" on line number "1116" on the condition that the jump flag JF is set to "1." If the jump flag JF is set to "0," the jump condition is not met even though the instruction "JRS 1, ADR114" is set on line number "1110," so the program will proceed to the next line number "1111" without jumping to the program address "ADR114." In the AT status signal setting process in this embodiment (FIG. 64(a)), the instruction "XOR A, A" is executed on line number "1109," setting the value of the jump flag JF to "1," and the instruction "JRS 1, ADR114" on line number "1110" is executed while the value of the jump flag JF is "1." This makes it possible to always jump from the program address "ADR112" on line number "1110" to the program address "ADR114" on line number "1116" by using the JRS instruction, which is a conditional jump instruction set on line number "1110."

To ensure a jump from the program address at line number "1110" to the program address at line number "1116," it is possible to set an unconditional jump instruction, JR or JP, at line number "1110." However, if the JR instruction "JR ADR114" is set at line number "1110," as shown in Figure 64(c), the word length of the jump instruction set at line number "1110" will be 2 bytes. Furthermore, although not shown, if the JP instruction "JP ADR114" is set at line number "1110," the word length of the jump instruction set at line number "1110" will be 3 bytes. The instruction "XOR A, A" set on line number "1109" is an instruction to create one byte of data "00H" to be set in the AT status signal counter 74w on line number "1116", and is a necessary instruction regardless of whether the jump instruction set on line number "1110" is a JRS instruction (word length 1 byte), a JR instruction (word length 2 bytes), or a JP instruction (word length 3 bytes). In the AT status signal setting process (FIG. 64(a)), the instructions "XOR A, A" and "JRS 1, ADR 114" are set in consecutive line numbers "1109" and "1110." This allows the word length of the jump instruction set in line number "1110" to be kept to 1 byte, while the instruction "XOR A, A," which is required regardless of which jump instruction is set in line number "1110," is used to ensure a jump from the program address of line number "1110" to the program address of line number "1116." This reduces the data size of the program (FIG. 64(a)) used to execute the AT status signal setting process.

<Program content for processing lottery results>
Next, prior to describing the program contents (see FIG. 66) of the lottery result response processing (FIG. 25) executed by the main MPU 72, we will describe the processing contents for determining whether or not the value of the index value counter 74f in the main RAM 74 in the lottery result response processing is within the numerical range of "1" to "9." As already described, the lottery result response processing is executed in step S914 of the role lottery processing (FIG. 18).

Hereinafter, the numerical range of "1" to "9" that is the subject of judgment when determining whether the value of the index value counter 74f is within this range is also referred to as the "target range of judgment." As already explained, in a game in which the pseudo bonus state ST4 or AT state ST5 is active and the number of bets is "3," a stop order type number of "1" to "9" is set in the stop order type counter 74m, provided that an index value IV of "1" to "9" is selected in the role lottery process (FIG. 18). Then, based on the stop order type number of "1" to "9" being set in the stop order type counter 74m, the dual-purpose display unit 66 displays the stop order of reels 32L, 32M, and 32R, and the image display device 63 notifies the player of the stop order of reels 32L, 32M, and 32R. The determination range ("1" to "9") is the range of index values IV that are the target for the stop order display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 when the game is in pseudo bonus state ST4 or AT state ST5 and the number of bets on the current game is "3".

The main MPU 72 first transfers the data in the index value counter 74f in the main RAM 74 to the A register 101b. Then, by executing the instruction "ADD A, F6H" on line number "1213" of the lottery result response processing (Figure 66) described below, an operation is performed to add "246" to the value of the A register 101b. The A register 101b is a 1-byte register, and the maximum value of the numerical information stored in the A register 101b is "255." The "246" added to the value of the A register 101b is the numerical information obtained by subtracting "9," the maximum value in the judgment range ("1" to "9"), from "255," the maximum value of the 1-byte numerical information stored in the A register 101b.

Figure 65 is an explanatory diagram illustrating the relationship between the value of A register 101b before adding "246", the value of A register 101b after adding "246", and the value of carry flag CF. As shown in Figure 65, if the value of A register 101b before adding "246" is any value between "0" and "9", that is, if the value of A register 101b before adding "246" is less than or equal to "9", the maximum value in the range to be judged ("1" to "9"), no carry occurs from the most significant bit (bit 7) during the operation to add "246" to A register 101b. Therefore, the value of carry flag CF after adding "246" will be "0". The one-byte numerical information ("246" to "255") stored in the A register 101b before the operation to add "246" is performed is greater than the one-byte numerical information ("0" to "9") stored in the A register 101b before the operation to add "246" is performed.

If the value of A register 101b before adding "246" is between "10" and "17," that is, if the value of A register 101b before adding "246" is greater than "9," the maximum value in the range to be judged ("1" to "9"), a carry occurs from the most significant bit (bit 7) of A register 101b during the operation to add "246" to A register 101b. As a result, the value of the carry flag CF after adding "246" becomes "1." The one-byte of numerical information ("0" to "7") stored in A register 101b before the operation to add "246" is smaller than the one-byte of numerical information ("10" to "17") stored in A register 101b before the operation to add "246" is executed.

If the value of A register 101b before adding "246" is within the range of "1" to "9" to be judged, the one-byte of numerical information stored in A register 101b after the operation to add "246" is completed will be any of "247" to "255." Thus, if the value of A register 101b before adding "246" is within the range of "1" to "9" to be judged, the one-byte of numerical information stored in A register 101b after the operation to add "246" is completed will be a value greater than or equal to "247."

If the value of A register 101b before adding "246" is "0," which is not included in the judgment target judgment ("1" to "9"), the one-byte of numerical information stored in A register 101b after the calculation to add "246" is completed will be "246." Also, if the value of A register 101b before adding "246" is any of "10" to "17," which are not included in the judgment target judgment ("1" to "9"), the one-byte of numerical information stored in A register 101b after the calculation to add "246" is completed will be any of "0" to "7." Thus, if the value of A register 101b before adding "246" is "0" or any of "10" to "17," which are not included in the judgment target judgment ("1" to "9"), the one-byte of numerical information stored in A register 101b after the calculation to add "246" is completed will be a value less than "247."

As described above, the one-byte numerical information stored in A register 101b after the operation to add "246" is performed will be a value of "247" or greater if the one-byte numerical information stored in A register 101b before the operation to add "246" is any of "1" to "9" which is included in the judgment range, and will be a value less than "247" if the one-byte numerical information stored in A register 101b before the operation to add "246" is any of "0" or "10" to "17" which is not included in the judgment range. Therefore, by determining whether the value of A register 101b is "247" or greater after the operation to add "246" is performed, it is possible to determine whether the value of index value counter 74f is within the judgment range of "1" to "9" while limiting the number of judgments to one.

Next, the program contents of the lottery result response processing (Figure 25) executed by the main MPU 72 will be explained with reference to the explanatory diagram in Figure 66. As already explained, the lottery result response processing is executed in step S914 of the role lottery processing (Figure 18). The processing contents of the lottery result response processing have been explained with reference to the flowchart in Figure 25. As shown in Figure 66, this program has line numbers set to "1201" to "1219". Program commands are executed in order from lowest to highest line number, except when a call command or jump command is executed.

In line number "1201," the instruction "LD A, (YGJTAR)" is set, just like in line number "1101" of the AT status signal setting process (Figure 64 (a)) already explained. "LD" is the LD instruction as an 8-bit transfer instruction, and "A" specifies the A register 101b as the transfer destination. "YGJTAR" is the address (2 bytes) of the game status area 77 in the main RAM 74, and "(YGJTAR)" specifies the game status area 77 as the transfer source. When the instruction "LD A, (YGJTAR)" is executed in line number "1201," the data in the game status area 77 is transferred to the A register 101b.

The instruction "AND A, 04H" is set in line number "1202." "AND" is an AND instruction that calculates the logical product of 8-bit data, and "A" is the A register 101b. As mentioned above, the data in the game status area 77 is set in the A register 101b by executing the LD instruction in line number "1201." As already explained with reference to Figure 31(b), the second bit of the game status area 77 is set to the pseudo bonus status flag 77c. "04H" is mask data "00000100B" that masks all bits of the data stored in the A register 101b with "0" except for the second bit, which is set to the data in the pseudo bonus status flag 77c. Executing the instruction "AND A, 04H" in line number "1202" performs a logical product operation between the data stored in the A register 101b and the mask data, and the result of this operation is stored in the A register 101b. The value of A register 101b is "04H" if the pseudo bonus state flag 77c is set to "1", and is "00H" if the value of the pseudo bonus state flag 77c is set to "0".

The instruction "CP A, 04H" is set on line number "1203." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "04H" is one byte of numeric information representing "4." Executing the instruction "CP A, 04H" on line number "1203" subtracts "04H" from the value of the A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. When the pseudo bonus state flag 77c is set to "1", an operation is performed to subtract "04H" from "04H" stored in the A register 101b, so no borrowing to the most significant bit occurs, the value of the carry flag CF becomes "0", and the value of the jump flag JF also becomes "0". On the other hand, when the value of the pseudo bonus state flag 77c is "0", an operation is performed to subtract "04H" from "00H" stored in the A register 101b, so a borrowing to the most significant bit occurs, the value of the carry flag CF becomes "1", and the value of the jump flag JF also becomes "1".

The instruction "JRS 0, ADR123" is set on line number "1204." "JRS" is a conditional jump instruction with a word length of 1 byte, "0" sets the jump condition to a value of "0" for the jump flag JF, and "ADR123" specifies "ADR123," the program address where the LD instruction on line number "1209" is set, as the jump destination program address. The instruction on line number "1204" is set to the program address "ADR121." The JRS instruction on line number "1204" relatively identifies the 2-byte jump destination program address (ADR123) based on the program address (ADR121) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. Because the jump to the destination program address is performed using a 1-byte JRS instruction, the data size of the machine code for the jump instruction to jump to the destination program address is reduced compared to a configuration using a 3-byte JP instruction or a 2-byte JR instruction. As already explained, the range that can be jumped to using the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in FIG. 66 , the total word length of the instructions set at the program addresses between the program addresses "ADR121" and "ADR123" (the LD instruction at line number "1205," the AND instruction at line number "1206," the CP instruction at line number "1207," and the JRS instruction at line number "1208") is 8 bytes. "ADR123" is "(ADR121) + 1 + 8," and is a program address that can be specified as the jump destination program address of the JRS instruction based on the program address (ADR121) where the JRS instruction at line number "1204" is set. When the instruction "JRS 0, ADR123" is executed at line number "1204," a jump occurs to the program address at line number "1209," provided that the value of the jump flag JF is "0." As described above, when the pseudo bonus state flag 77c is set to "1," the value of the jump flag JF becomes "0" when the instruction at line number "1203" is executed. Therefore, when the instruction "JRS 0, ADR123" is executed at line number "1204," a jump occurs to the program address "ADR123" at line number "1209." On the other hand, as mentioned above, if the value of the pseudo bonus state flag 77c is "0", the command on line number "1203" is executed, causing the value of the jump flag JF to be "1". Therefore, even if the command "JRS 0, ADR 123" is set on line number "1204", the program address will not jump and will proceed to the next line number "1205".

The commands on lines 1205 through 1208 are executed when the gaming state is not in pseudo-bonus state ST4. Lines 1205 through 1207 contain the same commands as lines 1101 through 1103 in the AT state signal setting process (Figure 64(a)) described above. Specifically, line 1205 contains the command "LD A, (YGJTAR)." "LD" is an 8-bit transfer command, "A" specifies the A register 101b as the transfer destination, and "(YGJTAR)" specifies the gaming state area 77 as the transfer source. Executing the command "LD A, (YGJTAR)" on line 1205 transfers the data in the gaming state area 77 to the A register 101b.

The instruction "AND A, 08H" is set in line number "1206." "AND" is an AND instruction that calculates the logical product of 8-bit data, and "A" is the A register 101b. As mentioned above, the data in the game status area 77 is set in A register 101b by executing the LD instruction in line number "1205." As already explained with reference to Figure 31(b), the AT status flag 77d is set in the third bit of the game status area 77. "08H" is mask data "00001000B" that masks all bits in the data stored in A register 101b other than the third bit, where the data in the AT status flag 77d is set, with "0." Executing the instruction "AND A, 08H" in line number "1206" performs a logical product operation between the data stored in A register 101b and the mask data, and the result of this operation is stored in A register 101b. The value of A register 101b is "08H" if the AT status flag 77d is set to "1", and is "00H" if the value of the AT status flag 77d is set to "0".

The instruction "CP A, 08H" is set on line number "1207." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "08H" is one byte of numerical information. Executing the instruction "CP A, 08H" on line number "1207" subtracts "08H" from the value of the A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. When the AT status flag 77d is set to "1", an operation is performed to subtract "08H" from "08H" stored in the A register 101b, so no borrowing to the most significant bit occurs, the value of the carry flag CF becomes "0", and the value of the jump flag JF also becomes "0". On the other hand, when the value of the AT status flag 77d is "0", an operation is performed to subtract "08H" from "00H" stored in the A register 101b, so a borrowing to the most significant bit occurs, the value of the carry flag CF becomes "1", and the value of the jump flag JF also becomes "1".

The instruction "JRS 1, ADR125" is set on line number "1208." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" sets the jump condition to a value of "1" for the jump flag JF, and "ADR125" specifies "ADR125," the program address where the JRS instruction on line number "1215" is set, as the jump destination program address. The instruction on line number "1208" is set to the program address "ADR122." The JRS instruction on line number "1208" relatively identifies the 2-byte jump destination program address (ADR125) based on the program address (ADR122) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. Because the jump to the destination program address is performed using a 1-byte JRS instruction, the machine code data size of the jump instruction for jumping to the destination program address is reduced compared to a configuration using a 3-byte JP instruction or a 2-byte JR instruction. As already explained, the range that can be jumped to using the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in FIG. 66 , the total word length of the instructions set at program addresses between program addresses "ADR122" and "ADR125" (the LD instruction at line number "1209," the CP instruction at line number "1210," the JRS instruction at line number "1211," the LD at line number "1212," the ADD instruction at line number "1213," and the CP instruction at line number "1214") is 13 bytes. "ADR125" is "(ADR122) + 1 + 13," and is a program address that can be specified as the program address of the jump destination in the JRS instruction based on the program address (ADR122) where the JRS instruction on line number "1208" is set. When the instruction "JRS 1, ADR125" is executed on line number "1208," a jump to line number "1215" occurs, provided that the value of the jump flag JF is "1." As described above, when the value of the AT status flag 77d is "0," the value of the jump flag JF becomes "1" when the instruction on line number "1207" is executed. Therefore, when the instruction "JRS 1, ADR125" is executed on line number "1208," a jump to the program address "ADR125" on line number "1215" occurs. On the other hand, as mentioned above, if the AT status flag 77d is set to "1", the instruction on line number "1207" is executed, causing the value of the jump flag JF to be set to "0". Therefore, even if the instruction "JRS 1, ADR 125" is set on line number "1208", the program address will not jump and will proceed to the next line number "1209".

The command set in line number "1209" is executed when a jump to line number "1209" is made by the JRS command in line number "1204," or when the game proceeds to the next line number "1209" without jumping at line number "1208" where the JRS command is set. Specifically, the command set in line number "1209" is executed in pseudo bonus state ST4 where the pseudo bonus state flag 77c is set to "1," or in AT state ST5 where the AT state flag 77d is set to "1."

The command "LD A, (BTSSCNT)" is set in line number "1209." "LD" is the LD command as an 8-bit data transfer command, and "A" is the A register 101b. "BTSSCNT" is the address (2 bytes) of the bet number setting counter 74b in the main RAM 74, and "(BTSSCNT)" specifies the bet number setting counter 74b as the transfer source. Executing the command "LD A, (BTSSCNT)" in line number "1209" transfers the data stored in the bet number setting counter 74b to A register 101b. As a result, if the number of bets in the current game is "3," "03H" is set in A register 101b, and if the number of bets in the current game is "2," "02H" is set in A register 101b.

The instruction "CP A, 03H" is set on line number "1210." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "03H" is one byte of numeric information representing "3." Executing the instruction "CP A, 03H" on line number "1210" subtracts "03H" from the value of the A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. If the number of bets on the current game is "3", an operation is performed to subtract "03H" from "03H" stored in the A register 101b, so no borrow occurs to the most significant bit, the value of the carry flag CF becomes "0", and the value of the jump flag JF also becomes "0". On the other hand, if the number of bets on the current game is "2", an operation is performed to subtract "03H" from "02H" stored in the A register 101b, so a borrow occurs to the most significant bit, the value of the carry flag CF becomes "1", and the value of the jump flag JF also becomes "1". The result of the operation to subtract "03H" from the value of the A register 101b is not written to the A register 101b. The value of the A register 101b does not change even when the instruction "CP A, 03H" is executed.

The instruction "JRS 1, ADR126" is set on line number "1211." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" sets the jump condition to a value of "1" for the jump flag JF, and "ADR126" specifies "ADR126," the program address where the LD instruction on line number "1218" is set, as the jump destination program address. The instruction on line number "1211" is set to the program address "ADR124." The JRS instruction on line number "1211" relatively identifies the 2-byte jump destination program address (ADR126) based on the program address (ADR124) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. Because the jump to the destination program address is performed using a 1-byte JRS instruction, the machine code data size of the jump instruction for jumping to the destination program address is reduced compared to a configuration using a 3-byte JP instruction or a 2-byte JR instruction. As already explained, the range that can be jumped to using the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in FIG. 66 , the total word length of the instructions set at program addresses between program addresses "ADR124" and "ADR126" (the LD instruction at line number "1212," the ADD instruction at line number "1213," the CP instruction at line number "1214," the JRS instruction at line number "1215," the LD instruction at line number "1216," and the LD instruction at line number "1217") is 14 bytes. "ADR126" is "(ADR124) + 1 + 14," and is a program address that can be specified as the jump destination program address of the JRS instruction based on the program address (ADR124) where the JRS instruction at line number "1211" is set. When the instruction "JRS 1, ADR126" is executed at line number "1211," a jump to line number "1218" occurs, provided that the value of the jump flag JF is "1." As described above, when the number of bets in the current game is "2," the value of the jump flag JF is set to "1" by executing the instruction at line number "1210." Therefore, when the instruction "JRS 1, ADR126" is executed at line number "1211," a jump to the program address "ADR126" at line number "1218" occurs. On the other hand, as mentioned above, if the number of bets in this game is "3", the command on line number "1210" is executed, causing the value of the jump flag JF to be "0". Therefore, even if the command "JRS 1, ADR126" is set on line number "1211", the program address will not jump and will proceed to the next line number "1212".

The command at line number "1212" is executed when the game is in pseudo bonus state ST4 or AT state ST5 and the number of bets in the current game is "3". The command "LD A, (INDXCNT)" is set in line number "1212". "LD" is the LD command as an 8-bit data transfer command, and "A" is the A register 101b. "INDXCNT" is the address (2 bytes) of the index value counter 74f in the main RAM 74, and "(INDXCNT)" specifies the index value counter 74f as the transfer source. When the command "LD A, (INDXCNT)" is executed in line number "1209", the data in the index value counter 74f is transferred to the A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in A register 101b, and if no index value IV is selected in the role selection process (Figure 18), "0" is set in A register 101b.

The instruction "ADD A, F6H" is set on line number "1213." "ADD" is an ADD instruction that adds 8-bit data, "A" is the A register 101b, and "F6H" is one byte of numeric data representing "246." As explained above, "246" is the value obtained by subtracting "9," the maximum value in the range to be judged ("1" to "9"), from "255," the maximum value for one byte of numeric information. When the instruction "ADD A, F6H" is executed on line number "1213," an operation is performed to add "246" to the value in A register 101b, and the result of this operation is written to A register 101b. If a carry from the most significant bit (the seventh bit) occurs in the operation, the carry flag CF is set to "1," and if a carry from the most significant bit (the seventh bit) does not occur in the operation, the value of the carry flag CF becomes "0." As already explained with reference to Figure 65, by executing the instruction "ADD A, F6H" on line number "1213," if the value of the index value counter 74f is "0," the value of the A register 101b becomes "246," if the value of the index value counter 74f is any one of "1" to "9," which is the range to be determined, the value of the A register 101b becomes any one of "247" to "255," and if the value of the index value counter 74f is any one of "10" to "17," which is the range to be determined, the value of the A register 101b becomes any one of "0" to "7." In this way, if the value of the index value counter 74f is within the judgment range of "1" to "9," the value of the A register 101b will be greater than or equal to "247," and if the value of the index value counter 74f is "0" or any of "10" to "17," which are not within the judgment range, the value of the A register 101b will be less than "247."

The instruction "CP A, F7H" is set on line number "1214." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "F7H" is one byte of numeric information representing "247." Executing the instruction "CP A, F7H" on line number "1214" subtracts "F7H" from the value of A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. When the value of index value counter 74f is within the range to be determined, between "1" and "9," an operation is performed to subtract "247" from a value greater than or equal to "247," so no borrow occurs to the most significant bit, and the value of carry flag CF becomes "0," and the value of jump flag JF also becomes "0." On the other hand, when the value of index value counter 74f is "0" or any of the values between "10" and "17," which are not within the range to be determined, an operation is performed to subtract "247" from a value less than "247," so a borrow occurs to the most significant bit, and the value of carry flag CF becomes "1," and the value of jump flag JF also becomes "1."

The instruction set on line number "1215" is executed when a jump to line number "1215" is made by the JRS instruction on line number "1208," or when the CP instruction on line number "1214" is executed to proceed to line number "1215." First, we will explain what happens when the instruction on line number "1215" is executed after the CP instruction on line number "1214" is executed.

The instruction "JRS 1, ADR126" is set for line number "1215," just like line number "1211." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" sets the jump condition to a value of "1" for the jump flag JF, and "ADR126" specifies "ADR126," the program address where the LD instruction on line number "1218" is set, as the jump destination program address. As mentioned above, the instruction on line number "1215" is set to the program address "ADR125." The JRS instruction on line number "1215" relatively identifies the 2-byte jump destination program address (ADR126) based on the program address (ADR125) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. Because the configuration uses a 1-byte JRS instruction to jump to a destination program address, the machine language data size of the jump instruction for jumping to the destination program address is reduced compared to configurations using a 3-byte JP instruction or a 2-byte JR instruction. As already explained, the range that can be jumped to with the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in Figure 66, the total word length of the instructions set at program addresses between program addresses "ADR125" and "ADR126" (LD instructions at line numbers "1216" and "1217") is 6 bytes. "ADR126" is "(ADR125) + 1 + 6," and is a program address that can be specified as the jump destination program address for the JRS instruction based on the program address (ADR125) where the JRS instruction at line number "1215" is set. When the instruction "JRS 1, ADR126" is executed at line number "1215," a jump to line number "1218" occurs, provided that the value of the jump flag JF is "1." As described above, if the value of the index value counter 74f is "0" or any of "10" to "17," which are not included in the judgment range ("1" to "9"), the value of the jump flag JF becomes "1" when the instruction at line number "1214" is executed. Therefore, when the instruction "JRS 1, ADR126" is executed at line number "1215," a jump to the program address "ADR126" at line number "1218" occurs. On the other hand, as mentioned above, if the value of the index value counter 74f is within the judgment range of "1" to "9", the instruction at line number "1214" is executed, causing the value of the jump flag JF to be set to "0". Therefore, even if the instruction "JRS 1, ADR126" is set at line number "1215", the program address does not jump and proceeds to the next line number "1216".

Next, we will explain the case where the JRS instruction on line number "1208" causes a jump to line number "1215" and then the instruction on line number "1215" is executed. As already explained, the instruction "JRS 1, ADR125" is set on line number "1208," and a jump to the program address on line number "1215" occurs if the value of jump flag JF is "1." Specifically, if the value of pseudo-bonus state flag 77c is "0," the instructions on lines "1205" to "1208" are executed, and if the value of AT state flag 77d is "0," a jump occurs from the program address on line number "1208" (ADR122) to the program address on line number "1215" (ADR125). As already explained, the state of jump flag JF does not change when the JRS instruction is executed. Therefore, when the JRS instruction on line number "1208" jumps to line number "1215" and then the instruction on line number "1215" is executed, the value of the jump flag JF is always "1", and the instruction "JRS 1, ADR126" is executed on line number "1215", resulting in a jump to the program address on line number "1218".

In this way, when the game state is neither the pseudo-bonus state ST4 nor the AT state ST5, the command "JRS 1, ADR125" is executed on line number "1208", causing a jump to the program address "ADR125" on line number "1215", and the command "JRS 1, ADR126" is executed on line number "1215", causing a jump to the program address "ADR126" on line number "1218". The JRS command in line number "1215" is a command to jump to the program address in line number "1218" if the index value IV of "1" to "9" is not won in the role lottery process (Figure 18) in a game in which the game is in pseudo bonus state ST4 or AT state ST5 and the number of bets is "3", and it is also a command to always jump to the program address in line number "1218" when jumping from line number "1208" to the program address in line number "1215", provided that the value of the jump flag JF is "1". For this reason, in a game in which the pseudo bonus state ST4 or AT state ST5 and the number of bets is "3", the data capacity of the program stored in the main ROM 73 for executing the lottery result response process (FIG. 66) is reduced compared to a configuration in which, as a separate command from the command for jumping to the program address of line number "1218" if the index value IV of "1" to "9" is not won in the role lottery process (FIG. 18), an command is set to always jump to the program address of line number "1218" when jumping from line number "1208" on the condition that the value of the jump flag JF is "1".

The command in line number "1216" is executed when the value of the index value counter 74f is within the judgment range of "1" to "9" in a game in which the game is in pseudo bonus state ST4 or AT state ST5 and the number of bets is "3." Similar to line number "1212," line number "1216" has the command "LD A, (INDXCNT)." "LD" is the LD command as an 8-bit transfer command, "A" is the A register 101b, and "(INDXCNT)" specifies the index value counter 74f as the transfer source. By executing the command "LD A, (INDXCNT)" in line number "1216," the data in the index value counter 74f is transferred to the A register 101b. The instruction on line number "1216" is executed when the value of the index value counter 74f is within the range of "1" to "9" that is the target of judgment, so the A register 101b is set to one of "1" to "9."

The instruction "LD (TJSBCNT), A" is set on line number "1217." "LD" is the LD instruction as an 8-bit transfer instruction, and "A" is the A register 101b. "TJSBCNT" is the address (2 bytes) of the stop order type counter 74m in the main RAM 74, and "(TJSBCNT)" specifies the stop order type counter 74m as the transfer destination. By executing the instruction "LD (TJSBCNT), A" on line number "1217," the data in the A register 101b is transferred to the stop order type counter 74m. This allows the stop order type counter 74m to be set to a stop order type number between "1" and "9."

In this way, in a game in which the pseudo bonus state ST4 or AT state ST5 is active and the bet amount is "3," a stop order type number between "1" and "9" is set in the stop order type counter 74m, provided that an index value IV between "1" and "9" is selected in the winning combination lottery process (FIG. 18). As already explained, based on the stop order type number between "1" and "9" being set in the stop order type counter 74m, the dual-purpose display unit 66 displays the stop order of reels 32L, 32M, and 32R, and the image display device 63 notifies the player of the stop order of reels 32L, 32M, and 32R.

The command set in line number "1218" is executed when the JRS command in line number "1211" jumps to the program address (ADR126) in line number "1218," when the JRS command in line number "1215" jumps to the program address (ADR126) in line number "1218," or when the LD command in line number "1217" is executed to proceed to line number "1218." Specifically, if the game state is neither pseudo-bonus state ST4 nor AT state ST5, the JRS command in line number "1208" jumps to the program address (ADR125) in line number "1215," and the JRS command in line number "1215" always jumps to the program address (ADR126) in line number "1218." If the system is in pseudo bonus state ST4 or AT state ST5 and the number of bets on the current game is "2," the JRS command in line number "1211" jumps to the program address (ADR126) in line number "1218." If the system is in pseudo bonus state ST4 or AT state ST5, the number of bets on the current game is "3," and the index value IV of "1" to "9" has not been won in the role lottery process (FIG. 18), the JRS command in line number "1215" jumps to the program address (ADR126) in line number "1218." If the system is in pseudo bonus state ST4 or AT state ST5, the number of bets on the current game is "3," and the index value IV of "1" to "9" has been won in the role lottery process (FIG. 18), the system sets the stop order type number to one of "1" to "9" in the stop order type counter 74m and then proceeds to line number "1218."

The instruction "LD (KSJCAR), 01H" is set on line number "1218." "LD" is the LD instruction as an 8-bit transfer instruction, and "01H" is one byte of numerical information, "1." "KSJCAR" is the address (2 bytes) of the start command area provided in the main RAM 74. The start command area is a one-byte memory area in which the start command flag is set, and the start command flag is set in the least significant bit (bit 0) of the start command area. Bits 1 through 7 of the start command area are unused. "(KSJCAR)" specifies the start command area of the main RAM 74 as the transfer destination. Execution of the instruction "LD (KSJCAR), 01H" on line number "1218" sets "01H" in the start command area of the main RAM 74. This allows the start command flag in the main RAM 74 to be set to "1." As already explained, setting the start command flag to "1" causes the common command transmission process (FIG. 50) to be executed, transmitting the start command to the production MPU 92.

The command "RET" is set in line number "1219." "RET" is a command to return from a subroutine. Executing the command "RET" in line number "1219" terminates the lottery result response process (Figure 66) called in step S914 of the role selection process (Figure 18). As already explained, in the role selection process (Figure 18), if the lottery result response process is executed in step S914, the role selection process (Figure 18) is terminated and processing proceeds to the reel control process in step S408 of the normal process (Figure 13).

Figure 67(a) is an explanatory diagram illustrating the program contents of a first comparative example of lottery result response processing. As shown in Figure 67(a), this program has line numbers "8001" to "8020" set. Program instructions are executed in order from lowest to highest line number, except when a call instruction or jump instruction is executed.

The first comparative example of lottery result processing is configured to execute the following processing: to set the data of index value counter 74f in A register 101b to determine whether the value of index value counter 74f is within the determination range of "1" to "9"; to determine whether the value of A register 101b is equal to or greater than "1," the minimum value of the determination range; and, if it is determined that the value of A register 101b is equal to or greater than "1," to determine whether the value of A register 101b is equal to or less than "9," the maximum value of the determination range.

As shown in Figure 67 (a), line numbers "8001" to "8011" in the first comparative example of lottery result response processing have the same instructions as line numbers "1201" to "1211" in the lottery result response processing (Figure 66) already described. Line number "8012" in the first comparative example of lottery result response processing has the same instruction "LD A, (INDXCNT)" as line number "1212" in the lottery result response processing (Figure 66). Execution of the instruction "LD A, (INDXCNT)" in line number "8012" sets the data in index value counter 74f in A register 101b.

The instruction "CP A, 01H" is set on line number "8013." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "01H" is a 1-byte value representing "1," the minimum value in the range to be judged ("1" to "9"). Executing the instruction "CP A, 01H" on line number "8013" subtracts "01H" from the value in A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. When the value of index value counter 74f is "1" or greater, an operation is performed to subtract "1" from the value "1" or greater, so no borrow occurs to the most significant bit, and the value of carry flag CF becomes "0" and the value of jump flag JF also becomes "0." On the other hand, when the value of index value counter 74f is "0," an operation is performed to subtract "1" from "0," so a borrow occurs to the most significant bit, so the value of carry flag CF becomes "1," and the value of jump flag JF also becomes "1." The result of the operation to subtract "01H" from the value of A register 101b is not written to A register 101b. The value of A register 101b does not change even when the instruction "CP A, 01H" is executed.

The instruction "JRS 1, ADR807" is set on line number "8014." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" sets the jump condition to a value of "1" for the jump flag JF, and "ADR807" specifies "ADR807," the program address where the LD instruction on line number "8019" is set, as the jump destination program address. The instruction on line number "8014" is set to program address "ADR805." The JRS instruction on line number "8014" relatively identifies the 2-byte jump destination program address (ADR807) based on the program address (ADR805) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. ADR807 is "(ADR805) + 1 + 9," and is a program address that can be specified as the program address of the jump destination of the JRS instruction based on the program address (ADR805) where the JRS instruction at line number "8014" is set. When the instruction "JRS 1, ADR807" is executed at line number "8014," a jump to line number "8019" occurs on the condition that the value of the jump flag JF is "1." Specifically, when the value of the index value counter 74f is "0," that is, when the value of the index value counter 74f is smaller than "1," which is the minimum value in the judgment range ("1" to "9"), the instruction "JRS 1, ADR807" is executed at line number "8014," a jump to the program address "ADR807" at line number "8019" occurs. On the other hand, if the value of the index value counter 74f is equal to or greater than "1," which is the minimum value in the judgment range ("1" to "9"), the program address will not jump and will proceed to the next line number, "8015," even if the instruction "JRS 1, ADR807" is set in line number "8014."

The instruction "CP A, 0AH" is set on line number "8015." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "0AH" is a 1-byte value representing "10," which is one greater than the maximum value of "9" in the range to be judged ("1" to "9"). Executing the instruction "CP A, 0AH" on line number "8015" subtracts "0AH" from the value of the A register 101b. If a borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs during this operation, the value of the carry flag CF becomes "1." If no borrow to the most significant bit occurs during this operation, the value of the carry flag CF becomes "0." As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. If the value of index value counter 74f is "10" or greater, an operation is performed to subtract "10" from the value "10" or greater, so no borrowing occurs to the most significant bit, the value of carry flag CF becomes "0", and the value of jump flag JF also becomes "0". On the other hand, if the value of index value counter 74f is less than "10", that is, if the value of index value counter 74f is less than or equal to "9", the maximum value in the range to be judged, an operation is performed to subtract "10" from a value less than "10", so a borrowing occurs to the most significant bit, the value of carry flag CF becomes "1", and the value of jump flag JF also becomes "1".

The instruction "JRS 0, ADR807" is set in the line number "8016.""JRS" is a conditional jump instruction with a word length of 1 byte, "0" sets the jump condition that the value of the jump flag JF is "0," and "ADR807" specifies "ADR807," the program address where the LD instruction in line number "8019" is set, as the jump destination program address. The instruction in line number "8016" is set to the program address "ADR806." The JRS instruction in line number "8016" relatively identifies the 2-byte jump destination program address (ADR807) based on the program address (ADR806) where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. ADR807 is "(ADR806)+1+6", and is a program address that can be specified as the jump destination program address for the JRS instruction on line number "8016", based on the program address (ADR806) where the JRS instruction on line number "8016" is set. When the instruction "JRS 0, ADR807" is executed on line number "8016", a jump to line number "8019" is performed on the condition that the value of the jump flag JF is "0". Specifically, when the value of the index value counter 74f is "10" or greater, that is, when the value of the index value counter 74f is greater than "9", which is the maximum value in the judgment range ("1" to "9"), "JRS 0, ADR807" is executed on line number "8016", and the jump destination program address for the JRS instruction on line number "8016" is specified as "0".
Execution of the instruction "JRS 0, ADR807" causes a jump to the program address "ADR807" at line number "8019." On the other hand, if the value of the index value counter 74f is less than "10," that is, if the value of the index value counter 74f is equal to or less than "9," which is the maximum value in the judgment range ("1" to "9"), the program address does not jump and proceeds to the next line number "8017" even if the instruction "JRS 0, ADR807" is set in line number "8016."

Line numbers "8017" through "8020" contain the same commands as line numbers "1216" through "1219" in the lottery result response processing (Figure 66). The commands set in line numbers "8017" through "8018" are executed when the value of the index value counter 74f is within the judgment range of "1" through "9." By executing the command "LD A, (INDXCNT)" in line number "8017," the data in the index value counter 74f (numeric information between "1" and "9") is transferred to the A register 101b. By executing the command "LD (TJSBCNT), A" in line number "8018," the data in the A register 101b is set in the stop order type counter 74m. As a result, the stop order type counter 74m is set to one of the stop order type numbers between "1" and "9." By executing the command "LD (KSJCAR), 01H" on line number "8019", "01H" is transferred to the start command area of the main RAM 74, and the start command flag of the main RAM 74 is set to "1". By executing the command "RET" on line number "8020", the first comparative example of the lottery result response processing (Figure 67(a)) is completed.

Figure 67 (b) is an explanatory diagram for explaining the commands set to execute the process of setting a stop order type number in the stop order type counter 74m on the condition that the index value IV in the judgment range ("1" to "9") is selected in the lottery result response process ( Figure 66 ) and the first comparative example of the lottery result response process ( Figure 67 (a) ).

In the lottery result response processing (Figure 66), instructions for executing the process of setting a stop order type number in the stop order type counter 74m on the condition that the index value IV in the judgment range is selected are set in line numbers "1212" to "1217." In the first comparative example of the lottery result response processing (Figure 67(a)), instructions for executing the process of setting a stop order type number in the stop order type counter 74m on the condition that the index value IV in the judgment range is selected are set in line numbers "8012" to "8018." In the first comparative example of the lottery result response processing (Figure 67(a)), three 3-byte LD instructions, two 2-byte CP instructions, and two 1-byte JRS instructions are set in line numbers "8012" to "8018." The total word length of the instructions set in line numbers "8012" to "8018" is 15 bytes. In contrast, lines "1212" to "1217" of the lottery result response processing (Figure 66) contain three 3-byte LD instructions, one 2-byte ADD instruction, one 2-byte CP instruction, and one 1-byte JRS instruction. The total word length of the instructions set on lines "1212" to "1217" is 14 bytes.

As already explained, the lottery result response processing (Figure 66) is configured to perform the following processing: adding "246", a value calculated by subtracting "9", the maximum value in the judgment range ("1" to "9"), from "255", the maximum value in 1-byte numerical information, to the value of A register 101b in which the data of index value counter 74f is set; and determining whether the 1-byte numerical information stored in A register 101b after adding "246" is greater than or equal to "247", a value calculated by adding "246" to "1", the minimum value in the judgment range. This reduces the total word length of the instructions set in the program for determining whether the value of the index value counter 74f is within the determination range ("1" to "9"), compared to a processing configuration like the first comparative example of lottery result response processing (FIG. 67(a)) that performs processing to determine whether the value of the A register 101b, to which the data of the index value counter 74f is set, is greater than or equal to "1," the minimum value of the determination range ("1" to "9"), and processing to determine whether the value of the A register 101b is less than or equal to "9," the maximum value of the determination range. Therefore, the data size of the program stored in the main ROM 73 for executing the lottery result response processing (FIG. 66) can be reduced.

The number of jump instructions (JRS instructions) set in line numbers "1212" to "1217" of the lottery result response processing (Figure 66) is fewer than the number of jump instructions (JRS instructions) set in line numbers "8012" to "8018" of the first comparative example of lottery result response processing (Figure 67(a)). By reducing the number of jump instructions, the risk of unused programs can be reduced.

Figure 68 (a) is an explanatory diagram illustrating the jump instructions set to jump from program addresses "ADR122" and "ADR125" to program address "ADR126" in the lottery result response processing (Figure 66). As already explained, the range that can be jumped to with a JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in Figure 66, "ADR126" is "(ADR122) + 1 + 20," and is a program address that cannot be specified as a jump destination program address with the JRS instruction based on the program address (ADR122) where the JRS instruction at line number "1208" is set.

In the lottery result response processing (Figure 66), JRS instructions are set to program addresses "ADR122" and "ADR125" to jump on the condition that the value of the jump flag JF is "1." Taking advantage of the fact that the state of the jump flag JF does not change even when the JRS instruction is executed, the lottery result response processing (Figure 66) jumps to "ADR125," a program address that can be specified as the jump destination program address for the JRS instruction, based on the program address (ADR122) where the JRS instruction at line number "1208" is set, and then jumps to program address "ADR126" using the JRS instruction set for the program address of "ADR125."

As already explained, the JRS command in line number "1215" is a command to jump to the program address in line number "1218" when an index value IV of "1" to "9" is not won in the role lottery process (Figure 18) in a game in which the pseudo bonus state ST4 or AT state ST5 and the number of bets is "3." It is also a command to always jump to the program address in line number "1218" when jumping from line number "1208" to the program address in line number "1215" on the condition that the value of the jump flag JF is "1."

Figure 68(b) is an explanatory diagram illustrating jump instructions set to jump from program addresses "ADR122" and "ADR125" to program address "ADR126" in a second comparative example of lottery result response processing. As already explained, the range that can be jumped with a JR instruction is the range from "(the program address where the JR instruction is set) + 2 - 128" to "(the program address where the JR instruction is set) + 2 + 127." As mentioned above, "ADR126" is "(ADR122) + 1 + 20," and is a program address that can be specified as the jump destination program address with a JR instruction based on ADR122. In the second comparative example of lottery result response processing (Figure 68(b)), the instruction "JR C, ADR126" is set to program address "ADR122." "JR" is a jump instruction with a word length of 2 bytes, "C" sets the jump condition that the carry flag CF is set to "1", and "ADR126" specifies the program address "ADR126" as the jump destination program address. As already explained, the JR instruction relatively specifies the 2-byte jump destination program address (ADR126) based on the program address (ADR122) where the JR instruction is set and the difference information (8 bits) set in the JR instruction. Also, as already explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. In the second comparative example of lottery result processing (Figure 68 (b)), the instruction "JR C, ADR126" is set to program address "ADR122", so if the carry flag CF is set to "1", a direct jump is made to program address "ADR126" without passing through program address "ADR125".

As mentioned above, the JRS command in line number "1215" is a command to jump to the program address in line number "1218" when the index value IV of "1" to "9" is not won in the role lottery process (Figure 18) in a game in which the pseudo bonus state ST4 or AT state ST5 and the number of bets is "3". Therefore, even in a configuration where a direct jump is made from line number "1208" to the program address in line number "1218", the JRS command in line number "1215" cannot be omitted.

As shown in Figure 68(b), in the second comparative example of lottery result response processing (Figure 68(b)), the total word length of the jump instructions set to jump from the program addresses "ADR122" and "ADR125" to the program address "ADR126" is 3 bytes. In contrast, as shown in Figure 68(a), in the lottery result response processing (Figure 66), the total word length of the jump instructions set to jump from the program addresses "ADR122" and "ADR125" to the program address "ADR126" is 2 bytes.

As described above, the lottery result response processing (Figure 66) sets a JRS instruction to jump to program addresses "ADR122" and "ADR125" on the condition that the value of the jump flag JF is "1", and taking advantage of the fact that the state of the jump flag JF does not change even when the JRS instruction is executed, jumps to the program address of line number "1215" using a JRS instruction with a word length of 1 byte on the condition that the value of the jump flag JF is "1" at line number "1208", and then reliably jumps to the program address of line number "1218" using a JRS instruction with a word length of 1 byte set at the jump destination line number "1215". This reduces the word length of the jump instructions set to jump from program address "ADR122" and program address "ADR125" to program address "ADR126," compared to the processing configuration in the second comparative example of lottery result response processing (FIG. 68(b)), which jumps directly to line number "1218" using a 2-byte JR instruction on the condition that the carry flag CF is set to "1" at line number "1208." This reduces the data size of the program stored in main ROM 73 to execute lottery result response processing (FIG. 66).

<Program contents for start-up top-up processing>
Next, before explaining the program contents (see Figure 69 (b)) of the start-up top-up process (Figure 43 (c)) executed by the main MPU 72, we will explain the processing contents for determining whether the value of the index value counter 74f of the main RAM 74 in the start-up top-up process is any of "11" to "15".

Hereinafter, the numerical range of "11" to "15" that is the subject of judgment when determining whether the value of the index value counter 74f is within this range is also referred to as the "first lottery target range." Furthermore, the numerical range of "14" to "15" that is the subject of judgment when determining whether the value of the index value counter 74f is within this range is also referred to as the "second lottery target range." As already explained, the start-time addition processing is executed in AT state ST5. Furthermore, as already explained, in the initial addition processing, if the index value IV of the first lottery target range ("11" to "15") is selected in the lottery processing for the winning combination (FIG. 18), the first addition lottery table 73d (FIG. 43(a)) is first selected as the lottery table to be referenced, and if the index value IV of the second lottery target range ("14" to "15") is selected in the lottery processing for the winning combination (FIG. 18), the lottery table to be referenced is changed to the second addition lottery table 73e (FIG. 43(b)), which is more advantageous to the player than the first addition lottery table 73d. Then, if the index value IV of any of "11" to "13", which is in the first lottery target range but not in the second lottery target range, is selected in the lottery processing for the winning combination (FIG. 18), the addition lottery is executed based on the first addition lottery table 73d. Furthermore, if the index value IV of "14" or "15", which is in the first lottery range and also in the second lottery range, is selected in the role lottery process (Figure 18), an additional lottery is executed based on the second additional lottery table 73e.

The master MPU 72 first transfers the data in the index value counter 74f in the master RAM 74 to the A register 101b. Then, by executing the instruction "SUB A, 0BH" at line number "1302" of the start-time addition process (Figure 69(b)) described below, an operation is performed to subtract "11" from the value in the A register 101b. The "11" subtracted from the value in the A register 101b is the minimum value in the first lottery target range ("11" to "15"). The operation to subtract "11" is an operation that changes the minimum value ("11") in the first lottery target range ("11" to "15") to the minimum value ("0") in the numerical range that can be represented in 8 bits ("0" to "255"). This operation shifts the first lottery target range downward by "11." By subtracting "11", the maximum value of the first lottery range ("15") shifts downward by "11" to become "4". Details of the SUB command on line number "1302" will be explained later.

Figure 69(a) is an explanatory diagram illustrating the relationship between the value of A register 101b before subtracting "11," the value of A register 101b after subtracting "11," and the value of carry flag CF after subtracting "11." As shown in Figure 69(a), if the value of A register 101b before subtracting "11" is between "11" and "17," that is, if the value of A register 101b before subtracting "11" is equal to or greater than "11," the minimum value in the first lottery range ("11" to "15"), no borrow occurs to the most significant bit of A register 101b (the seventh bit of bits 0 to 7) during the operation to subtract "11" from the value of A register 101b. Therefore, the value of carry flag CF after subtracting "11" becomes "0." After the operation to subtract "11" is completed, the one-byte of numerical information ("0" to "6") stored in the A register 101b will be smaller than the one-byte of numerical information ("11" to "17") stored in the A register 101b before the operation to subtract "11" is performed.

If the value of A register 101b before subtracting "11" is between "0" and "10," that is, if the value of A register 101b before subtracting "11" is a value smaller than "11," the minimum value in the first lottery range (a value equal to or smaller than "10"), a borrow occurs to the most significant bit of A register 101b (the seventh bit of bits 0 to 7) during the operation to subtract "11" from the value of A register 101b. As a result, the value of the carry flag CF after subtracting "11" becomes "1." Then, the one-byte of numerical information ("245" to "255") stored in A register 101b after the operation to subtract "11" is completed will be greater than the one-byte of numerical information ("0" to "10") stored in A register 101b before the operation to subtract "11" was performed.

If the value of A register 101b before subtracting "11" is within the first lottery range of "11" to "15," the 1-byte of numerical information stored in A register 101b after the calculation to subtract "11" is completed will be any of "0" to "4." Thus, if the value of A register 101b before subtracting "11" is within the first lottery range, the 1-byte of numerical information stored in A register 101b after the calculation to subtract "11" is completed will be a value less than "5."

If the value of A register 101b before subtracting "11" is either "0" or "10," which is not included in the first lottery target range ("11" to "15"), the one-byte of numerical information stored in A register 101b after the calculation to subtract "11" is either "245" or "255." Furthermore, if the value of A register 101b before subtracting "11" is either "16" or "17," which are not included in the first lottery target range, the one-byte of numerical information stored in A register 101b after the calculation to subtract "11" is either "5" or "6." Thus, if the value of A register 101b before subtracting "11" is either "0" to "10" or "16" to "17," which are not included in the first lottery target range, the one-byte of numerical information stored in A register 101b after the calculation to subtract "11" is a value greater than or equal to "5."

As described above, the one-byte numerical information stored in A register 101b after the calculation to subtract "11" is completed will be a value less than "5" if the value in A register 101b before the subtraction of "11" is within the first lottery target range, and will be a value greater than or equal to "5" if the value in A register 101b before the subtraction of "11" is any of "0" to "10" or "16" to "17", which are not within the first lottery target range. Therefore, by determining whether the one-byte numerical information stored in A register 101b after the calculation to subtract "11" is completed is less than "5", it is possible to determine whether the value of index value counter 74f is within the first lottery target range of "11" to "15", while limiting the number of determinations to one.

As shown in FIG. 69(a), if the value of the index value counter 74f is any of "11" to "13", which is included in the first lottery target range ("11" to "15") but not included in the second lottery target range ("14" to "15"), the 1-byte numerical information stored in the A register 101b after the calculation to subtract "11" will be any of "0" to "2" (a value less than "3"). On the other hand, if the value of the index value counter 74f is "14" or "15", which is included in the first lottery target range ("11" to "15") and also included in the second lottery target range, the 1-byte numerical information stored in the A register 101b after the calculation to subtract "11" will be "3" or "4" (a value greater than or equal to "3"). Therefore, after determining that the value of the index value counter 74f is within the first lottery range of "11" to "15," it is possible to determine whether the value of the index value counter 74f is within the second lottery range of "14" to "15" while limiting the number of determinations to one by determining whether the 1-byte numerical information stored in the A register 101b is less than "3."

Considering a configuration in which, in order to determine whether the index value IV is within the second lottery target range ("14" to "15"), a determination is made as to whether the index value IV before subtracting "11" is equal to or greater than "14," the minimum value of the second lottery target range, the boundary value when determining whether the index value IV is within the second lottery target range ("14" to "15") is "14." In contrast, by performing an operation to shift the first lottery target range ("11" to "15") downward by "11" (an operation to subtract "11") and then determining whether the value after the operation is equal to or greater than "3," which is the value obtained by shifting the minimum value ("14") of the second lottery target range ("14" to "15") downward by "11," the boundary value when determining whether the index value IV is within the second lottery target range ("14" to "15") can be set to "3," a value smaller than "14." The number of bits required to represent the boundary value ("3") when determining whether the value obtained by shifting the index value IV downward by "11" is equal to or greater than "3" is "2," which is smaller than the number of bits ("4") required to represent the boundary value ("14") when determining whether the pre-shift index value IV is equal to or greater than "14," the minimum value of the second selection range. In this configuration, in which a calculation is performed to subtract "11" from the index value IV to determine whether the index value IV is within the first selection range, the number of bits required to represent the boundary value used in this determination can be reduced by using the value obtained by shifting the index value IV downward by "11." This reduces the data capacity required to store the boundary value.

Next, the program contents of the start-time addition process (Figure 43(c)) executed by the main MPU 72 will be explained with reference to the explanatory diagram in Figure 69(b). As already explained, the start-time addition process is executed in step S2310 of the advantageous state process at the start of the game (Figure 40). The processing contents of the start-time addition process have already been explained with reference to the flowchart in Figure 43(c). As shown in Figure 69(b), this program has line numbers set to "1301" to "1309". Program instructions are executed in order from lowest to highest line number, except when a call or jump instruction is executed.

Line number "1301" contains the command "LD A, (INDXCNT)," similar to line number "1212" in the lottery result processing (Figure 66). "LD" is the LD command as a transfer command for 8-bit data, "A" is the A register 101b, and "(INDXCNT)" specifies the index value counter 74f in the main RAM 74 as the transfer source. By executing the command "LD A, (INDXCNT)" in line number "1301," the data in the index value counter 74f is transferred to the A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the winning combination lottery processing (Figure 18), that index value IV is set in the A register 101b. If no index value IV is selected in the winning combination lottery processing (Figure 18), "0" is set in the A register 101b.

The instruction "SUB A, 0BH" is set in line number "1302." "SUB" is a SUB instruction that subtracts 8-bit data, "A" is the A register 101b, and "0BH" is one byte of numerical information indicating "11," the minimum value in the first lottery range ("11" to "15"). By executing the instruction "SUB A, 0BH" in line number "1302," an operation is performed to subtract "11" from the value in A register 101b, and the result of this operation is written to A register 101b. If a borrow to the most significant bit (the seventh bit) occurs in this operation, the carry flag CF is set to "1." If a borrow to the most significant bit (the seventh bit) does not occur in this operation, the value of the carry flag CF is set to "0." As already explained with reference to Figure 69 (a), if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), the value of the A register 101b will be less than "5", and if the value of the index value counter 74f is any of "0" to "10" or "16" to "17", which are not within the first lottery target range ("11" to "15"), the value of the A register 101b will be "5" or greater. Furthermore, as already explained with reference to FIG. 69(a), if the value of the index value counter 74f is any of "11" to "13", which is included in the first lottery target range ("11" to "15") but not included in the second lottery target range ("14" to "15"), the value of the A register 101b will be less than "3", and if the value of the index value counter 74f is "14" or "15", which is included in the first lottery target range ("11" to "15") and also included in the second lottery target range, the value of the A register 101b will be a value of "3" or greater.

The instruction "CP A, 05H" is set on line number "1303." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "05H" is one byte of numerical information indicating a value ("5") that is "1" greater than "4," which is the value calculated by subtracting "11" from "15," the maximum value in the first lottery target range ("11" to "15"). Executing the instruction "CP A, 05H" on line number "1303" performs an operation to subtract "5" from the value in A register 101b. If the value of the A register 101b before the subtraction of "5" is less than "5," i.e., if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), a borrow occurs to the most significant bit (the seventh bit of the zeroth to seventh bits) in the operation, and the value of the carry flag CF becomes "1." On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or greater, i.e., if the value of the index value counter 74f is one of "0" to "10" or "16" to "17," which are not within the first lottery target range ("11" to "15"), a borrow does not occur to the most significant bit (the seventh bit of the zeroth to seventh bits) in the operation, and the value of the carry flag CF becomes "0." The result of the operation of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even when the instruction "CP A, 05H" is executed, the value of A register 101b does not change. Therefore, the operation to subtract "11" is performed on line number "1302", and the data stored in A register 101b can also be used on line number "1306", which will be described later.

The instruction "RET NC" is set in line number "1304." "RET" is a RET instruction to return from a subroutine, and "NC" sets the condition for returning from a subroutine, that is, the value of the carry flag CF be "0." Execution of the instruction "RET NC" in line number "1304" terminates the start-time bonus processing called in step S2310 of the advantageous state processing at the start of the game (FIG. 40), provided that the value of the carry flag CF is "0," and returns to step S2311, the next step after step S2310. As described above, if the value of the index value counter 74f is "0" to "10" or "16" to "17," which are not included in the first lottery target range ("11" to "15"), the instruction in line number "1303" is executed, and the value of the carry flag CF becomes "0." Therefore, by executing the command "RET NC" in line number "1304", the start-time addition process ends and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). On the other hand, as described above, if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), the command in line number "1303" is executed and the value of the carry flag CF becomes "1". Therefore, even if the command "RET NC" is set in line number "1304", the start-time addition process does not end and the process proceeds to the next line number "1305".

The command in line number "1305" is executed when the AT state is ST5 and the index value IV in the first lottery target range ("11" to "15") is selected in the role lottery process (Figure 18). The command "LD HL, KSADD01" is set in line number "1305." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first add-on lottery table 73d in the main ROM 73. By executing the command "LD HL, KSADD01" in line number "1305," the start address of the first add-on lottery table 73d is transferred to HL register 104. This allows the first add-on lottery table 73d to be set as the lottery table to be referenced in the add-on lottery. In this way, when the AT state ST5 is active and the index value IV in the first selection range ("11" to "15") is selected in the role selection process (Figure 18), the first additional selection table 73d is set as the selection table to be referenced.

The instruction "CP A, 03H" is set in row number "1306." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is A register 101b, and "03H" is one byte of numerical information indicating the value ("3") calculated by subtracting "11" from "14," the minimum value in the second lottery target range ("14" to "15"). As described above, A register 101b stores one byte of numerical information calculated by subtracting "11" in row number "1302." The instruction in row number "1306" is executed when the index value IV in the first lottery target range ("11" to "15") is selected in the role selection process (Figure 18), and therefore the value in A register 101b is either "0" to "4." Execution of the instruction "CP A, 03H" on line number "1306" performs an operation to subtract "3" from the value of the A register 101b. As already explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. If the value of the A register 101b before the subtraction of "3" is less than "3," that is, if the value of the index value counter 74f is one of "11" to "13," which is not included in the second lottery target range ("14" to "15"), a borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) in the operation, causing the value of the carry flag CF to become "1," and the value of the jump flag JF also to become "1." On the other hand, if the value of the A register 101b before the subtraction of "3" is "3" or greater, i.e., if the value of the index value counter 74f is "14" or "15," which is within the second selection range, no borrow to the most significant bit (the seventh bit of bits 0 to 7) occurs in the calculation, so the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0." As described above, by using the value after shifting the index value IV downward by "11" to determine whether the index value before the shift is within the second selection range ("14" to "15"), the number of bits required to represent the boundary value ("3") in this determination can be reduced. This reduces the data capacity required to store this boundary value.

The instruction "JRS 1, ADR132" is set on line number "1307." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" specifies that the jump condition is that the jump flag JF value is "1," and "ADR132" specifies the program address "ADR132" on line number "1309" as the jump destination. The instruction on line number "1307" is set to program address "ADR131." As previously explained, the range that can be jumped with the JRS instruction is from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in Figure 69(b), the word length of the instruction (the LD instruction on line number "1308") set at a program address between program addresses "ADR131" and "ADR132" is 3 bytes. "ADR132" is "(ADR131) + 1 + 3", and is a program address that can be specified as the jump destination program address for the JRS instruction, based on the program address (ADR131) where the JRS instruction at line number "1307" is set.

As described above, if the value of the index value counter 74f is any of "11" to "13," which is within the first lottery target range ("11" to "15") but not within the second lottery target range ("14" to "15"), the instruction at line number "1306" is executed, causing the value of the jump flag JF to be set to "1." Therefore, the instruction "JRS 1, ADR132" is executed at line number "1307," causing a jump to the program address "ADR132" at line number "1309." On the other hand, as described above, if the value of the index value counter 74f is "14" or "15," which is within the first lottery target range ("11" to "15") and also within the second lottery target range ("14" to "15"), the instruction at line number "1306" is executed, causing the value of the jump flag JF to be set to "0." Therefore, even if the instruction "JRS 1, ADR132" is set on line number "1307", the program address will not jump and will proceed to the next line number "1308".

The command at line number "1308" is executed when the AT state is ST5 and the index value IV in the second lottery target range ("14" to "15") is selected in the role lottery process (Figure 18). The command "LD HL, KSADD02" is set in line number "1308." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second additional lottery table 73e (Figure 43 (b)) in the main ROM 73. When the command "LD HL, KSADD02" is executed in line number "1308," the start address of the second additional lottery table 73e is transferred to the HL register 104. This allows the reference lottery table to be changed from the first add-on lottery table 73d to the second add-on lottery table 73e, which is more advantageous to the player than the first add-on lottery table 73d. In this way, when the AT state ST5 is reached and the index value IV in the second lottery target range ("14" to "15") is won in the role lottery process (Figure 18), the second add-on lottery table 73e is set as the reference lottery table in the add-on lottery.

The command set in line number "1309" is executed when a jump to line number "1309" is made by the JRS command in line number "1307," or when the LD command in line number "1308" is executed and the program proceeds to line number "1309." Specifically, in AT state ST5, if the role selection process (Figure 18) selects an index value IV that is included in the first selection target range ("11" to "15") but not included in the second selection target range ("14" to "15"), the JRS command in line number "1307" jumps to the program address of line number "1309," and the command in line number "1309" is executed. Also, in AT state ST5, if the index value IV is selected in the role selection process (Figure 18) and is included in both the first selection target range ("11" to "15") and the second selection target range ("14" to "15"), the LD command in line number "1308" is executed, and then the command in line number "1309" is executed.

The instruction "JP ADR133" is set in line number "1309." "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is a program address (2 bytes) in which an instruction to execute the processing of step S1802 in the release game number lottery processing (Figure 35 (b)) is set. Executing the instruction "JP ADR133" in line number "1309" causes a jump to the program address "ADR133." Then, executing the processing of steps S1802 to S1807 in the release game number lottery processing (Figure 35 (b)) executes a lottery to add on the remaining number of continued games in AT state ST5. As already explained, when the player is in the AT state ST5 and has won an index value IV that is included in the first lottery target range ("11" to "15") but not included in the second lottery target range ("14" to "15") in the role lottery process (FIG. 18), an additional lottery is executed with the first additional lottery table 73d set as the reference lottery table. Also, when the player is in the AT state ST5 and has won an index value IV that is included in the first lottery target range ("11" to "15") and also included in the second lottery target range ("14" to "15") in the role lottery process (FIG. 18), an additional lottery is executed with the second additional lottery table 73e set as the reference lottery table.

The JP command on line number "1309" is a command to jump to the program address "ADR133" after changing the referenced lottery table to the second top-up lottery table 73e on line number "1308," and is also a command that ensures a jump to the program address "ADR133" when a jump to the program address on line number "1309" is made with the JRS command on line number "1307." Therefore, compared to a configuration in which a command to ensure a jump to the program address "ADR133" when a jump is made with the JRS command on line number "1307" is set as a separate command from the command to jump to the program address "ADR133" after changing the referenced lottery table to the second top-up lottery table 73e on line number "1308," the data size of the program stored in the main ROM 73 for executing the start-up top-up processing can be reduced.

As already explained, in the release game number lottery processing (Figure 35), after setting the release game number lottery table 73c as the reference lottery table in step S1801, the lottery execution processing of steps S1802 to S1807 is executed without calling a subroutine program. The lottery execution processing (steps S1802 to S1807) is executed after executing the processing of step S1801 in the release game number lottery processing (Figure 35), and is also executed when a jump is made by the JP command at line number "1309" in the start-time addition processing (Figure 69 (b)). If the lottery execution process (steps S1802 to S1807) is configured as a common subroutine called in the release game number lottery process (FIG. 35) and the start-up addition process (FIG. 69(b)), it will be necessary to set a CALL command (3 bytes) that calls the lottery execution process after the command to execute the process of step S1801 in the release game number lottery process (FIG. 35). In this configuration, a CALL command is set instead of a JP command at line number "1309" of the start-up addition process (FIG. 69(b)), but the word length of the CALL command (3 bytes) is the same as the word length of the JP command (3 bytes). For this reason, if a common subroutine called the lottery execution process is called in the release game number lottery process (FIG. 35) and the start-up additional process (FIG. 69(b)), the data capacity of the program stored in the main ROM 73 for executing the release game number lottery process (FIG. 35) and the start-up additional process (FIG. 69(b)) will increase by the amount of the CALL command set in the release game number lottery process (FIG. 35).

In this embodiment, the JP command "JP ADR133" is executed at line number "1309" of the start-time surcharge processing (FIG. 69(b)), thereby jumping to the program address (ADR133) where an instruction to execute the processing of step S1802 of the release game number lottery processing (FIG. 35(b)) is set. Furthermore, when the processing of step S1801 is executed in the release game number lottery processing (FIG. 35(b)), the processing of step S1802 is executed without calling a subroutine program. Therefore, compared to a configuration in which a common subroutine called the lottery execution processing is called in the release game number lottery processing (FIG. 35) and the start-time surcharge processing (FIG. 69(b)), the data capacity of the program stored in the main ROM 73 for executing the release game number lottery processing (FIG. 35) and the start-time surcharge processing (FIG. 69(b)) can be reduced.

Figure 70(a) is an explanatory diagram illustrating the program contents in a first comparative example of start-time addition processing. As shown in Figure 70(a), this program has line numbers "8101" to "8110". Program instructions are executed in order from lowest to highest line number, except when a call or jump instruction is executed.

The first comparative example of the start-up addition process is configured to execute the following process: setting the data of the index value counter 74f in the A register 101b to determine whether the value of the index value counter 74f is within the first lottery range ("11" to "15"); determining whether the value of the A register 101b is equal to or greater than "11," the minimum value of the first lottery range; and, if it is determined that the value of the A register 101b is equal to or greater than "11," determining whether the value of the A register 101b is equal to or less than "15," the maximum value of the first lottery range. Furthermore, the first comparative example of the start-up addition process is configured to execute, when the value of the index value counter 74f is within the first lottery range, determining whether the value of the index value counter 74f is equal to or greater than "14," the minimum value of the second lottery range, to determine whether the value of the index value counter 74f is within the second lottery range ("14" to "15").

As shown in Figure 70 (a), the command "LD A, (INDXCNT)" is set in line number "8101" in the first comparative example of the start-up addition process, just like line number "1301" in the start-up addition process (Figure 69 (b)). By executing the command "LD A, (INDXCNT)" in line number "8101", the data in index value counter 74f is transferred to A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in A register 101b, and if no index value IV is selected in the role selection process (Figure 18), "0" is set in A register 101b.

The instruction "CP A, 0BH" is set in line number "8102." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is A register 101b, and "0BH" is 1 byte of numerical information indicating "11," the minimum value in the first lottery target range ("11" to "15"). When the instruction "CP A, 0BH" is executed in line number "8102," an operation is performed to subtract "11" from the value in A register 101b. As already explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. If the value of the A register 101b before the subtraction of "11" is between "0" and "10," i.e., if the value of the index value counter 74f is less than "11," which is the minimum value of the first lottery target range ("11" to "15"), a borrow to the most significant bit (the seventh bit of the zeroth to seventh bits) occurs in the operation, causing the carry flag CF to have a value of "1," and the jump flag JF to have a value of "1." On the other hand, if the value of the A register 101b before the subtraction of "11" is between "11" and "17," i.e., if the value of the index value counter 74f is "11" or greater, no borrow to the most significant bit (the seventh bit of the zeroth to seventh bits) occurs in the operation, causing the carry flag CF to have a value of "0," and the jump flag JF to have a value of "0." The result of the operation of subtracting "11" from the value of the A register 101b is not written to the A register 101b. Even when the instruction "CP A, 0BH" is executed, the value of A register 101b does not change. The data transferred from index value counter 74f to A register 101b on line number "8101" is also used on line number "8104" described below.

The instruction "RET C" is set on line number "8103." "RET" is a RET instruction to return from a subroutine, and "C" sets the condition for returning from a subroutine: the carry flag CF must be set to "1." By executing the instruction "RET C" on line number "8103," the first comparative example of the start-up addition process ends, provided that the carry flag CF is set to "1." Specifically, if the value of the index value counter 74f is between "0" and "10," the carry flag CF is set to "1," and the first comparative example of the start-up addition process ends. On the other hand, if the value of the index value counter 74f is between "11" and "17," the value of the carry flag CF is "0," and the first comparative example of the start-up addition process does not end, and the program proceeds to the next line number "8104."

The instruction "CP A, 10H" is set in line number "8104." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "10H" is one byte of numerical information indicating "16," which is one greater than the maximum value of "15" in the first lottery target range ("11" to "15"). As described above, the A register 101b stores the data transferred to the A register 101b from the index value counter 74f at line number "8101." Execution of the instruction "CP A, 10H" at line number "8104" subtracts "16" from the value in A register 101b. As previously explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. Furthermore, the instruction at line number "8104" is executed on the condition that the value of the index value counter 74f is any one of "11" to "17." If the value of the A register 101b before the subtraction of "16" is less than "16," i.e., if the value of the index value counter 74f is any one of "11" to "15," which is the first lottery target range, a borrow to the most significant bit (the seventh bit of the zeroth to seventh bits) occurs in the calculation, the value of the carry flag CF becomes "1," and the value of the jump flag JF also becomes "1." On the other hand, if the value of the A register 101b before the subtraction of "16" is "16" or greater, i.e., if the value of the index value counter 74f is "16" or "17," which are not included in the first lottery target determination, a borrow to the most significant bit (the seventh bit of the zeroth to seventh bits) does not occur in the calculation, so the value of the carry flag CF becomes "0," and the value of the jump flag JF also becomes "0." The result of the operation to subtract "16" from the value of A register 101b is not written to A register 101b. Even when the instruction "CP A, 10H" is executed, the value of A register 101b does not change. The data transferred from index value counter 74f to A register 101b on line number "8101" is also used on line number "8107" described below.

The instruction "RET NC" is set in line number "8105." "RET" is a RET instruction to return from a subroutine, and "NC" sets the condition for returning from a subroutine, that the value of the carry flag CF be "0." By executing the instruction "RET NC" in line number "8105," the start-up addition process ends, provided that the value of the carry flag CF is "0." Specifically, if the value of the index value counter 74f is "16" or "17," the value of the carry flag CF is "0," and the start-up addition process ends. On the other hand, if the value of the index value counter 74f is within the first lottery range of "11" to "15," the value of the carry flag CF is "1," and the process proceeds to the next line number "8106" without returning from the subroutine.

The command "LD HL, KSADD01" is set in line number "8106," just like line number "1305" in the start-up add-on process (Figure 69 (b)). By executing the command "LD HL, KSADD01" in line number "8106," the start address of the first add-on lottery table 73d is transferred to the HL register 104. This sets the first add-on lottery table 73d as the lottery table to be referenced.

The instruction "CP A, 0EH" is set in line number "8107." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is A register 101b, and "0EH" is one byte of numerical information indicating "14," the minimum value in the second lottery target range ("14" to "15"). As described above, A register 101b stores the data transferred to A register 101b from index value counter 74f at line number "8101." By executing the instruction "CP A, 0EH" in line number "8107," an operation is performed to subtract "14" from the value in A register 101b. As previously explained, when the CP instruction is executed, the value of jump flag JF becomes the same as the value of carry flag CF. Furthermore, the instruction on line number "8107" is executed on the condition that the value of the index value counter 74f is one of the first lottery target ranges, "11" to "15." If the value of the A register 101b before the subtraction of "14" is less than "14," that is, if the value of the index value counter 74f is one of "11" to "13," which is included in the first lottery target range ("11" to "15") but not included in the second lottery target range ("14" to "15"), a borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) in the calculation, and the value of the carry flag CF becomes "1," and the value of the jump flag JF also becomes "1." On the other hand, if the value of the A register 101b before the subtraction of "14" is "14" or greater, that is, if the value of the index value counter 74f is within the second lottery range ("14" or "15"), no borrow occurs to the most significant bit (the seventh bit of bits 0 to 7) in the calculation, so the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0".

Line numbers "8108" through "8110" contain the same instructions as lines "1307" through "1309" in the start-up addition process (Figure 69(b)). As described above, if the value of the index value counter 74f is any of "11" through "13," which is within the first lottery target range but not within the second lottery target range, the instruction on line number "8107" is executed, setting the value of the jump flag JF to "1." Therefore, the instruction "JRS 1, ADR812" is executed on line number "8108," causing a jump from the program address "ADR811" on line number "8108" to the program address "ADR812" on line number "8110." On the other hand, as described above, if the value of the index value counter 74f is "14" or "15," which is included in the second lottery target range, the instruction at line number "8107" is executed, and the value of the jump flag JF is set to "0." Therefore, even if the instruction "JRS 1, ADR812" is set at line number "8108," the program address does not jump, and proceeds to the next line number "8109." By executing the instruction "LD HL, KSADD02" at line number "8109," the start address of the second add-on lottery table 73e is transferred to the HL register 104. As a result, the lottery table to be referenced in the add-on lottery is changed to the second add-on lottery table 73e. In this way, when the AT state ST5 is active and the index value IV in the second selection range ("14" to "15") is selected in the role selection process (Figure 18), the second additional selection table 73e is set as the selection table to be referenced in the additional selection. Executing the command "JP ADR133" on line number "8110" causes a jump to the program address "ADR133".

Figure 70 (b) is an explanatory diagram illustrating the commands set for selecting the first add-on lottery table 73d and the commands set for selecting the second add-on lottery table 73e in the start-up add-on process and the first comparative example of the start-up add-on process. In the start-up add-on process (Figure 69 (b)), the commands for selecting the first add-on lottery table 73d on the condition that the index value IV of the first lottery target range is selected are set in row numbers "1301" to "1305." Also, in the first comparative example of the start-up add-on process (Figure 70 (a)), the commands for selecting the first add-on lottery table 73d on the condition that the index value IV of the first lottery target range is selected are set in row numbers "8101" to "8106."

As shown in Figure 70(b), in the first comparative example of start-up addition processing (Figure 70(a)), lines "8101" to "8106" have two 3-byte LD instructions, two 2-byte CP instructions, and two 1-byte RET instructions. The total word length of the instructions set in lines "8101" to "8106" is 12 bytes. In contrast, lines "1301" to "1305" in the start-up addition processing (Figure 69(b)) have two 3-byte LD instructions, one 2-byte SUB instruction, one 2-byte CP instruction, and one 1-byte RET instruction. The total word length of the instructions set in lines "1301" to "1305" is 11 bytes.

As already explained, the start-up addition process (Figure 69 (b)) is configured to perform the following processing: subtracting "11", the minimum value of the first lottery target range ("11" to "15"), from the value of A register 101b in which the data of index value counter 74f is set; and determining whether the value of A register 101b after subtracting "11" is less than "5", which is a value "1" greater than the value calculated by subtracting "11" from "15", the maximum value of the first lottery target range. This reduces the total word length of the instructions set in the program to determine whether the value of the index value counter 74f is within the first lottery range, compared to the processing configuration of the first comparative example of the start-up addition process (FIG. 70(a)), which determines whether the value of the A register 101b, to which the data of the index value counter 74f is set, is greater than or equal to "11," the minimum value of the first lottery range, and determines whether the value of the A register 101b is less than or equal to "15," the maximum value of the first lottery range. Therefore, the data size of the program stored in the main ROM 73 to execute the start-up addition process (FIG. 69(b)) can be reduced.

In the start-up addition process (Figure 69(b)), the instructions for setting the first addition lottery table as the reference lottery table when the value of the index value counter 74f is any of "11" to "13" and for setting the second addition lottery table as the reference lottery table when the value of the index value counter 74f is "14" or "15" are set in line numbers "1301" to "1308." In the first comparative example of the start-up addition process (Figure 70(a)), the instructions for setting the first addition lottery table as the reference lottery table when the value of the index value counter 74f is any of "11" to "13" and for setting the second addition lottery table as the reference lottery table when the value of the index value counter 74f is "14" or "15" are set in line numbers "8101" to "8109." In the first comparative example of the start-time addition processing (FIG. 70(a)), three 3-byte LD instructions, three 2-byte CP instructions, two 1-byte RET instructions, and one 1-byte JRS instruction are set in line numbers "8101" to "8109". The total word length of the instructions set in line numbers "8101" to "8109" is 18 bytes. In contrast, in the start-time addition processing (FIG. 69(b)), three 3-byte LD instructions, one 2-byte SUB instruction, two 2-byte CP instructions, one 1-byte RET instruction, and one 1-byte JRS instruction are set in line numbers "1301" to "1308". The total word length of the instructions set on lines 1301 to 1308 is 17 bytes.

As already explained, the start-up addition process (Figure 69 (b)) is configured to perform the following processes: subtracting "11", the minimum value of the first lottery target range ("11" to "15"), from the value of A register 101b in which the data of index value counter 74f is set; determining whether the value of A register 101b after subtracting "11" is less than "5", which is a value "1" greater than the value calculated by subtracting "11" from "15", the maximum value of the first lottery target range; and determining whether the value of A register 101b after subtracting "11" is greater than or equal to "3", the value calculated by subtracting "11" from "14", the minimum value of the second lottery target range ("14" to "15"). This makes it possible to reduce the total word length of the instructions set in the program to set the first add-on lottery table as the reference lottery table when the value of the index value counter 74f is either "11" to "13", and to set the second add-on lottery table as the reference lottery table when the value of the index value counter 74f is "14" or "15", compared to a processing configuration that performs the following, as in the first comparative example of the start-up add-on processing (Figure 70 (a)), which performs the following: determining whether the value of the A register 101b, to which the data of the index value counter 74f is set, is greater than or equal to "11", the minimum value of the first lottery target range ("11" to "15"); determining whether the value of the A register 101b is less than or equal to "15", the maximum value of the first lottery target range; and determining whether the value of the A register 101b is greater than or equal to "14", the minimum value of the second lottery target range ("14" to "15"). This reduces the data size of the program stored in the main ROM 73 to execute the start-up top-up process (Figure 69 (b)).

Figure 71 (a) is an explanatory diagram illustrating the jump instructions set to jump from program addresses "ADR131" and "ADR132" to program address "ADR133" in the start-up addition process ( Figure 69 (b)). As already explained, the range that can be jumped to with the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." "ADR133" is the program address where an instruction to execute the processing of step S1802 of the release game number lottery process ( Figure 35 (b)) is set, and is a program address that cannot be specified as a jump destination program address with the JRS instruction based on the program address (ADR131) where the JRS instruction at line number "1307" is set. Furthermore, "ADR133" is a program address that cannot be specified as a jump destination program address in a JRS instruction based on the program address (ADR132) at line number "1309".

As already explained, the range that can be jumped to with the JR instruction is from "(the program address where the JR instruction is set) + 2 - 128" to "(the program address where the JR instruction is set) + 2 + 127." "ADR133" is a program address that cannot be specified as a jump destination program address with a JR instruction based on the program address (ADR131) of line number "1307," and it is also a program address that cannot be specified as a jump destination program address with a JR instruction based on the program address (ADR132) of line number "1309."

In the start-time addback process (Figure 69(b)), the instruction "JP ADR133" is set on line number "1309." As already explained, the JP instruction is a three-byte jump instruction that specifies the entire program address (two bytes) of the jump destination. Therefore, by using the JP instruction, it is possible to jump from the program address "ADR132" where the JP instruction on line number "1309" is set to the program address "ADR133." In the start-time addback process (Figure 69(b)), a one-byte JRS instruction is set on line number "1307," and, on the condition that the value of the jump flag JF is "1," a jump is made from line number "1307" to the program address (ADR132) of line number "1309," and then the JP instruction set on the jump destination program address is used to jump to the program address "ADR133."

Figure 71(b) is an explanatory diagram illustrating jump instructions set to jump from program addresses "ADR131" and "ADR132" to program address "ADR133" in a second comparative example of start-up addition processing. In the second comparative example of start-up addition processing (Figure 71(b)), the instruction "JP C, ADR133" is set to program address "ADR131." "JP" is a jump instruction with a word length of 3 bytes, "C" specifies the jump condition, that is, the carry flag CF is set to "1," and "ADR133" specifies the program address "ADR133" as the jump destination program address. As already explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. In the second comparative example of start-up addition processing (Figure 71 (b)), the instruction "JR C, ADR133" is set to program address "ADR131", so if the carry flag CF is set to "1", it jumps directly to program address "ADR133" without passing through program address "ADR132".

As mentioned above, the JP command at line number "1309" is a command to jump to the program address "ADR133" after changing the reference lottery table in the additional lottery at line number "1308" to the second additional lottery table 73e, on the condition that the AT state is ST5 and the index value IV included in the second lottery target range ("14" to "15") has been won in the role lottery process (Figure 18). For this reason, even in a configuration where a direct jump is made from line number "1307" to program address "ADR133," the JP command at line number "1309" cannot be omitted.

As shown in Figure 71(b), in the second comparative example of start-up addition processing (Figure 71(b)), the total word length of the jump instructions set to jump from program addresses "ADR131" and "ADR132" to program address "ADR133" is 6 bytes. In contrast, as shown in Figure 71(a), in the start-up addition processing (Figure 69(b)), the total word length of the jump instructions set to jump from program addresses "ADR131" and "ADR132" to program address "ADR133" is 4 bytes.

As described above, the start-up processing (Fig. 69(b)) is configured to jump to line number "1309" using a 1-byte JRS instruction on the condition that the jump flag JF is set to "1" at line number "1307," and then jump to program address "ADR133" using the JP instruction set at the jump destination line number "1309." This reduces the total word length of the jump instructions set to jump from program addresses "ADR131" and "ADR132" to program address "ADR133," compared to the second comparative example of start-up processing (Fig. 71(b)), which uses a 3-byte JP instruction to jump directly to program address "ADR133" on the condition that the carry flag CF is set to "1" at line number "1307." This reduces the data size of the program stored in the main ROM 73 to execute the start-up top-up process (Figure 69 (b)).

The present embodiment described above provides the following excellent effects:

The main MPU 72 determines that the dual-purpose display unit 66 is currently displaying the stop order corresponding display based on the value of the stop order type counter 74m being one of "1" to "9," and determines that the dual-purpose display unit 66 is not currently displaying the stop order corresponding display based on the stop order type counter 74m not being set to a stop order type number between "1" and "9." In a configuration in which the dual-purpose display unit 66 displays the stop order corresponding display based on the value of the stop order type counter 74m or the number of awards displayed based on the value of the award number counter 74e during game execution, the slot machine 10 lacks a flag that enables the main MPU 72 to determine that the dual-purpose display unit 66 is currently displaying the stop order corresponding display and the number of awards displayed. Therefore, compared to a configuration in which such a flag is included, the data capacity of the main RAM 74 required to display the dual-purpose display unit 66 while the game is being executed can be reduced.

In a game in which the stop order display on the dual-purpose display unit 66 and the stop order notification on the image display device 63 are executed, any of the index values IV "1" to "9" that is selected in the winning combination lottery process (FIG. 18) is stored in the index value counter 74f, and any of the index values IV "1" to "9" stored in the index value counter 74f is set directly as the stop order type number in the stop order type counter 74m. Therefore, the processing configuration for setting the stop order type number in the stop order type counter 74m is simplified compared to a configuration in which the stop order type number data set in the stop order type counter 74m differs from the index value IV data that is selected in the winning combination lottery process (FIG. 18).

In the winning determination process (FIG. 26), when a small win occurs, step S1205, in which the award number corresponding to the small win is set in the award number counter 74e, occurs before step S1208, in which the stop order type counter 74m is cleared to "0." If the stop order type counter 74m is cleared to "0" while the stop order type display is being executed on the dual-purpose display unit 66, the display content of the dual-purpose display unit 66 switches from the stop order type display to the award number display. If the stop order type counter 74m is cleared to "0" before the award number corresponding to the newly established small win is set in the award number counter 74e on the dual-purpose display unit 66, there is a risk that "0" will be displayed between the end of the stop order type display on the dual-purpose display unit 66 and the start of displaying the award number corresponding to the newly established small win. If the display content on the dual-purpose display unit 66 switches twice in a short period of time (for example, approximately 3 milliseconds) in the order of stop order display → "00" → display corresponding to the number of gaming media awarded, this could confuse the gaming parlor manager and players. In contrast, by using a processing configuration that clears the stop order type counter 74m to "0" when the number of gaming media awarded corresponding to the currently established small winning combination is set in the award number counter 74e, the display content on the dual-purpose display unit 66 can be smoothly switched from the stop order display to the award number display.

When a game is being played and the dual-purpose display unit 66 is displaying the number of awards based on the value of the award number counter 74e, the display content on the dual-purpose display unit 66 can be switched from the number of awards display to the stop order corresponding display by performing a process of setting the stop order type counter 74m to one of "1" to "9" (the process of step S1105 in the lottery result response process (FIG. 25)). Therefore, compared to a configuration in which, in addition to the process of setting the stop order type counter 74m to one of "1" to "9", a separate process is set to switch the display content on the dual-purpose display unit 66 from the number of awards display based on the value of the award number counter 74e to the stop order corresponding display, the processing configuration for setting the stop order type counter 74m to one of "1" to "9" and switching the display content on the dual-purpose display unit 66 from the number of awards display to the stop order corresponding display can be simplified.

When a game is being played and the stop order display is being performed on the dual-purpose display unit 66, the value of the stop order type counter 74m is cleared to "0" (the processing of step S1208 in the winning determination processing (FIG. 26)), thereby switching the display content on the dual-purpose display unit 66 from a stop order corresponding display to a number of awards based on the value of the award number counter 74e. Therefore, compared to a configuration in which, in addition to the processing of clearing the value of the stop order type counter 74m to "0," a separate processing is set to switch the display content on the dual-purpose display unit 66 from a stop order corresponding display to a number of awards based on the value of the award number counter 74e, the processing configuration for clearing the value of the stop order type counter 74m to "0" and switching the display content on the dual-purpose display unit 66 from a stop order corresponding display to a number of awards can be simplified.

The main MPU 72 determines that the dual-purpose display unit 66 is currently displaying a ratio based on the ratio display counter 74n being set to a value between "0" and "100," and determines that the dual-purpose display unit 66 is not currently displaying a ratio based on the value of the ratio display counter 74n or the value of the award counter 74e when a game is not being played. In a configuration in which the dual-purpose display unit 66 displays a ratio based on the value of the ratio display counter 74n or a number of awards based on the value of the award counter 74e when a game is not being played, the slot machine 10 lacks a flag that enables the main MPU 72 to determine when the dual-purpose display unit 66 is in a state where a ratio display should be performed or a number of awards display should be performed. Therefore, compared to a configuration in which such a flag is provided, the data capacity of the main RAM 74 required to generate a state in which the dual-purpose display unit 66 is displaying a ratio or a number of awards when a game is not being played can be reduced.

When a game is not being played and the dual-purpose display unit 66 is displaying the number of awards based on the value of the award number counter 74e, the display content on the dual-purpose display unit 66 can be switched from displaying the number of awards to displaying the ratio by executing a process (step S1305 in the management process (FIG. 27)) that sets calculation result data between "0" and "100" in the ratio display counter 74n. Therefore, compared to a configuration in which, in addition to the process of storing calculation result data in the ratio display counter 74n, a separate process is set to switch the display content on the dual-purpose display unit 66 from displaying the number of awards based on the value of the award number counter 74e to displaying the ratio, the processing configuration for storing calculation result data in the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from displaying the number of awards to displaying the ratio can be simplified.

When a game is not being played and a ratio display is being performed on the dual-purpose display unit 66, the display content on the dual-purpose display unit 66 can be switched from a ratio display to a number of awards based on the value of the number of awards counter 74e by executing a process to set the ratio display counter 74n to an initial value of "255" (the process of step S1307 in the management process (FIG. 27)). Therefore, compared to a configuration in which, in addition to the process of setting an initial value to the ratio display counter 74n, a separate process is set to switch the display content on the dual-purpose display unit 66 from a ratio display to a number of awards display, the process configuration for setting an initial value to the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from a ratio display to a number of awards display can be simplified.

Calculation result data for the stay ratio for the second section SC2 is set in the ratio display counter 74n when an operation to start the ratio display is performed while the game is not being executed. If the calculation to calculate the stay ratio for the second section SC2 were performed even when the ratio display is not being executed on the dual-purpose display unit 66 and the calculation result data were stored in the main RAM 74, it would be necessary to provide a counter in the main RAM 74 to store the calculation result data in addition to the ratio display counter 74n. In contrast, by configuring the calculation result data to be set in the ratio display counter 74n only during the period when the ratio display is being executed on the dual-purpose display unit 66, the data capacity of the memory area provided in the main RAM 74 for storing the calculation result data can be reduced.

The period during which the stop order type counter 74m is set to a stop order type number between "1" and "9" does not overlap with the period during which the ratio display counter 74n is set to a calculation result data between "0" and "100." Therefore, the conditions for executing the stop order corresponding display on the dual-purpose display unit 66 and the conditions for executing the ratio display are not met simultaneously. This eliminates the need for flags that enable the main MPU 72 to determine when the dual-purpose display unit 66 is in a state where the stop order corresponding display should be executed and when the ratio display should be executed. Compared to a configuration that includes such flags, this reduces the data capacity of the main RAM 74 required to create the state in which the stop order corresponding display and the ratio display are executed on the dual-purpose display unit 66.

The "0" or "1" data stored in the most significant bits of six memory areas set in the contiguous address range of "0001H" to "0006H," including the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total win count counter 74s, whose most significant bits can be set to "1," is aggregated into a one-byte memory area (top-level aggregation area 74v). Therefore, compared to a configuration in which two or more bytes of memory area are set in the main RAM 74 to set the "0" or "1" data stored in the most significant bits of these six memory areas, the data capacity of the memory area provided in the main RAM 74 to set the "0" or "1" data stored in the most significant bits of these six memory areas is reduced.

Six memory areas, including the lower area of the AT continuation counter 74u, the lower area of the continued game count counter 74r, and the lower area of the total win count counter 74s, which can have their most significant bit set to "1," are set in a contiguous address range from "0001H" to "0006H." This simplifies the processing configuration for specifying the address range of the memory area for which the data "0" or "1" stored in the most significant bit is set in the top aggregation area 74v.

The memory areas set in the address range of "0008H" to "000DH" (bet number setting counter 74b, stop order type counter 74m, game status area 77, game interval area 76, pseudo bonus continuation counter 74t, and award number counter 74e) are memory areas in which "1" is not set in the most significant bit. Among the memory areas set in the address range of "0001H" to "000DH" where data is set for start commands and end commands, in a configuration in which a top-level aggregation area 74v is provided to aggregate data of "0" or "1" stored in the most significant bit of memory areas corresponding to addresses "0001H" to "0006H," no memory area is provided in which data of "0" stored in the most significant bit of memory areas corresponding to addresses "0008H" to "000DH" is set. This allows the most significant bit of data in a storage area where a "1" can be set to the most significant bit to be set in the start command and end command, while limiting the number of storage areas (most significant aggregation areas 74v) set in the main RAM 74 for aggregating the most significant bit of data.

The memory areas in which data is set for start and end commands are set in the continuous address range of "0001H" to "000DH" in the main RAM 74, which simplifies the processing configuration for specifying the address range of the memory area in which data is set for start commands and the processing configuration for specifying the address range of the memory area in which data is set for end commands.

Only a portion of the memory area of the main RAM 74 (specifically, the top-level aggregation area 74v and the game status area 77) in which data used by the presentation MPU 92 at the start of the game is stored is shared with the memory area of the main RAM 74 in which data used by the presentation MPU 92 at the end of the game is stored. In this configuration, by setting the memory areas in which data is set for the start command and the end command as memory areas in the main RAM 74 in which data used by the presentation MPU 92 at the start and end of the game is stored, it is possible to set the memory areas in which data is set for the start command and the memory areas in which data is set for the end command in consecutive address ranges in the main RAM 74.

In the main RAM 74, the address range of the memory area where the data set for the start command is stored (address range "0001H" to "000DH") is the same as the address range of the memory area where the data set for the end command is stored (address range "0001H" to "000DH"), so the processing configuration for sending the start command and the processing configuration for sending the end command can be standardized. This allows the data size of the program for sending the start command and the end command in the main ROM 73 to be reduced.

Counters for which a "1" can be set in the most significant bit of the lower area include the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s. The data of the AT continuation counter 74u is used by the presentation MPU 92 at the start of the game, but is not used by the presentation MPU 92 at the end of the game. Furthermore, the data of the number of continued games counter 74r and the total number of wins counter 74s is used by the presentation MPU 92 at the end of the game, but is not used by the presentation MPU 92 at the start of the game. If only the data used by the presentation MPU 92 at the start of the game were set as the start command and only the data used by the presentation MPU 92 at the end of the game were set as the end command, it would be necessary to provide a memory area in the main RAM 74 for setting the most significant bit data in the lower and upper areas of the number of continued games counter 74r and the most significant bit data in the lower and upper areas of the total number of wins counter 74s, separate from the memory area for setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u. In contrast, by configuring the start command and end command to set data for the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s, it is possible to use only one memory area, the top-level aggregation area 74v, for setting the "0" or "1" data stored in the most significant bit of the lower and upper areas of the AT continuation counter 74u, the number of continued games counter 74r, and the total number of wins counter 74s. This reduces the data capacity of the main RAM 74 for setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the number of continued games counter 74r, and the lower and upper areas of the total number of wins counter 74s.

The production side MPU 92 converts start commands received from the main side MPU 72 into converted start commands, and converts end commands received from the main side MPU 72 into converted end commands. When converting a start command or end command received from the main side MPU 72 into a converted start command or converted end command, the production side MPU 92 sets the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) to the most significant bit in the second to seventh frames FR2 to FR7 corresponding to those bits 0 to 5. This allows the production side MPU 92 to use a converted start command or converted end command in which the most significant bit in frames other than the header HD can also be set to "1," while the most significant bit in frames other than the header HD included in the start command or end command sent from the main side MPU 72 to the production side MPU 92 is set to "0."

In a start command or end command, the frames in which the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF (eighth frame FR8) is set as the most significant bit are the consecutive second to seventh frames FR2 to FR7. This simplifies the processing configuration for the production-side MPU 92 to specify the frames in which the "0" or "1" data set in bits 0 to 5 of the top-level aggregated frame SF is set as the most significant bit.

Only a portion of the first through fifteenth frames FR1 through FR15 included in the start command are set in the converted start command. This allows the master MPU 72 to send a start command that includes data other than that used by the production MPU 92 at the start of the game, while reducing the data size of the converted start command stored in the command storage buffer 126 and used by the production MPU 92. Furthermore, only a portion of the first through fifteenth frames FR1 through FR15 included in the end command are set in the converted end command. This allows the master MPU 72 to send a end command that includes data other than that used by the production MPU 92 at the end of the game, while reducing the data size of the converted end command stored in the command storage buffer 126 and used by the production MPU 92. This reduces the data size of the command storage buffer 126.

Of the first to fifteenth frames FR1 to FR15 included in the start command, the frames that the production side MPU 92 sets in the converted start command are different from the frames of the first to fifteenth frames FR1 to FR15 included in the end command that the production side MPU 92 sets in the converted end command. Therefore, in a configuration in which the address range of the memory area of the main RAM 74 storing the data set in the start command sent from the main MPU 72 to the production MPU 92 at the start of the game is the same as the address range of the memory area of the main RAM 74 storing the data set in the end command sent from the main MPU 72 to the production MPU 92 at the end of the game, the production MPU 92 can use the converted start command at the start of the game, in which only the data required by the production MPU 92 at the start of the game is set between the header HD and footer FT, and at the end of the game, the production MPU 92 can use the converted end command in which only the data required by the production MPU 92 at the end of the game is set between the header HD and footer FT.

The transfer target range in the top-level aggregation process (Figure 51) is the consecutive address range from "0001H" to "0006H" in the main RAM 74. The source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source counter 116 in the main RAM 74 by 1 (processing in step S2909). This simplifies the processing configuration for sequentially updating the source memory area.

Since the transfer target range in the top-level aggregation process (Figure 51) is the consecutive address range from "0001H" to "0006H" in the main RAM 74, the transfer target range can be specified by setting the start address of the transfer target range, "0001H," in the transfer source counter 116 in step S2904, and setting the number of transfers, "6," in the transfer count counter 114 in step S2905. This simplifies the processing configuration for specifying the transfer target range.

The transfer target range in the common command transmission process (Figure 50) is the consecutive address range from "0001H" to "000DH" in the main RAM 74. The source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source counter 116 in the main RAM 74 by 1 (processing in step S2816). This simplifies the processing configuration for sequentially updating the source memory area.

Since the transfer target range in the common command transmission process (Figure 50) is the consecutive address range from "0001H" to "000DH" in the main RAM 74, the transfer target range can be specified by setting the start address of the transfer target range, "0001H," in the transfer source counter 116 in step S2809, and setting the number of transfers, "13," in the transfer count counter 114 in step S2810. This simplifies the processing configuration for specifying the transfer target range.

During the top-level setting process (Figure 53), the addresses of areas RA2 to RA7, whose most significant bits are set to the data "0" or "1" stored in bits 0 to 5 of the top-level aggregated frame SF, are in the consecutive address range of "α+2" to "α+7." The destination memory areas can be updated sequentially by repeatedly adding 1 to the value of the director's destination counter (step S3110). This simplifies the processing configuration for sequentially updating the destination memory areas.

The value of the production-side bit designation counter in the production-side RAM 94 is incremented by 1 each time the process of transferring "0" or "1" data stored in any of bits 0 through 5 of the most significant aggregated frame SF to the most significant bit in the destination memory area (processing in step S3109) is executed. Therefore, by referencing the value of the production-side bit designation counter, it is possible to determine the number of times that "0" or "1" data set in any of bits 0 through 5 of the most significant aggregated frame SF has been transferred to the second through seventh frames FR2 through FR7 corresponding to that bit. This simplifies the processing configuration for determining the number of transfers in the production-side MPU 92.

When converting a start command or end command set in the pre-conversion area 124 into a converted start command or a converted end command by transferring data for some of the first through fifteenth frames FR1 to FR15 contained in the start command or end command set in the pre-conversion area 124 to the converted area 125, the source memory area in the pre-conversion area 124 is updated in a manner that excludes areas to be excluded. On the other hand, the destination memory area in the converted area 125 is updated in a manner that the memory area set next to the current destination memory area in the converted area 125 becomes the updated destination memory area. As a result, when a start command is received, data to be used by the production side MPU 92 at the start of the game can be extracted from the start command and set as the converted start command. Also, when an end command is received, data to be used by the production side MPU 92 at the end of the game can be extracted from the end command and set as the converted end command.

The presentation-side MPU 92 converts the start command received from the main MPU 72 into a converted start command and executes processing to execute the presentation of the currently started game based on the converted start command. The converted start command contains data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 in the main RAM 74. Because the data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 is available when a start command is received, the number of commands sent from the main MPU 72 to the presentation-side MPU 92 can be reduced compared to a configuration in which the data for the AT continuation counter 74u, bet number setting counter 74b, stop order type counter 74m, and game status area 77 is received in two or more commands. This reduces the processing load when the main MPU 72 sends commands to the production MPU 92, and also reduces the processing load when the production MPU 92 executes processing corresponding to commands received from the main MPU 72.

The presentation-side MPU 92 converts the end command received from the main MPU 72 into a converted end command and executes processing to execute the presentation based on the converted end command. The converted end command contains data for the number of continuing games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and number of awarded bonuses counter 74e stored in the main RAM 74. This configuration makes the data for the number of continuing games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and number of awarded bonuses counter 74e available when the end command is received. This reduces the number of commands sent from the main MPU 72 to the presentation-side MPU 92 compared to a configuration in which the data for the number of continuing games counter 74r, total number of wins counter 74s, game status area 77, game section area 76, pseudo bonus continuation counter 74t, and number of awarded bonuses counter 74e is received using two or more commands. This reduces the processing load when the main MPU 72 sends commands to the production MPU 92, and also reduces the processing load when the production MPU 92 executes processing corresponding to commands received from the main MPU 72.

The JRS instruction only provides a conditional jump that jumps when the referenced flag is in a specified state (the jump flag JF is either "1" or "0"); it does not provide an unconditional jump that jumps unconditionally without referencing the flag state. The JRS instruction set on line number "1002" in the power-off standby processing (Figure 62 (b)) is a conditional jump instruction that jumps to the program address on line number "1001" when the jump flag JF is "0." However, in the power-off standby processing, the value of the jump flag JF always becomes "0" after the OUT instruction "OUT (WDTCLR0), 18H" on line number "1001" is executed. Therefore, while using the JRS instruction, which is a conditional jump instruction with a short word length, the instructions set on lines "1001" to "1002" can be repeatedly executed.

In the power-off standby processing (Figure 62 (b)), a JRS instruction with a word length of 1 byte is set as the instruction to jump from the program address ("ADR102") of line number "1002" to the program address ("ADR101") of line number "1001". Therefore, the data size of the program for the power-off standby processing can be reduced compared to a configuration in which a JR instruction with a word length of 2 bytes or a JP instruction with a word length of 3 bytes is set as the instruction to jump from the program address of line number "1002" to the program address of line number "1001".

The 1-byte JRS instruction only provides a conditional jump instruction that jumps to a destination program address when the jump flag JF is set to either "1" or "0." In the AT status signal setting process (Figure 64(a)), the instruction "XOR A, A" is executed on line "1109," setting the zero flag ZF to "1" and the jump flag JF to "1." Then, with the jump flag JF set to "1," the instruction "JRS 1, ADR114" is executed on line "1110," the line immediately following line "1109." This ensures a jump from line "1110" to the program address "ADR114" on line "1116." The instruction "XOR A, A" set on line number "1109" is an instruction to clear to "0" the data in A register 101b that is set in the AT status signal counter 74w at the jump destination line number "1116." The instruction "XOR A, A" set on line number "1109" is also an instruction that enables a reliable jump to the program address "ADR114" on line number "1116" using the 1-byte JRS instruction on line number "1110." By combining these two roles into the XOR instruction on line number "1109," the data size of the program for executing the AT status signal setting process is reduced.

To ensure a jump from the program address at line number "1110" to the program address at line number "1116," it is possible to set an unconditional jump instruction, JR or JP, at line number "1110." However, setting a JR instruction with a word length of 2 bytes or a JP instruction with a word length of 3 bytes at line number "1110" would increase the word length of the jump instruction for jumping from line number "1110" to line number "1116." In the AT status signal setting process (Figure 64(a)), the instructions "XOR A, A" and "JRS 1, ADR114" are set at consecutive line numbers "1109" and "1110." This makes it possible to ensure a jump from the program address at line number "1110" to the program address at line number "1116" while keeping the word length of the jump instruction set at line number "1110" to 1 byte.

The lottery result response processing (Figure 66) is configured to perform the following processing: adding "246", a value calculated by subtracting "9", the maximum value in the judgment range ("1" to "9"), from "255", the maximum value in 1-byte numerical information, to the value of A register 101b in which the data of index value counter 74f is set; and determining whether the 1-byte numerical information stored in A register 101b after adding "246" is greater than or equal to "247", a value calculated by adding "246" to "1", the minimum value in the judgment range. This reduces the total word length of the instructions set in the program for determining whether the value of the index value counter 74f is within the determination range ("1" to "9"), compared to a processing configuration like the first comparative example of lottery result response processing (FIG. 67(a)) that performs processing to determine whether the value of the A register 101b, to which the data of the index value counter 74f is set, is greater than or equal to "1," the minimum value of the determination range ("1" to "9"), and processing to determine whether the value of the A register 101b is less than or equal to "9," the maximum value of the determination range. Therefore, the data size of the program stored in the main ROM 73 for executing the lottery result response processing (FIG. 66) can be reduced.

By configuring the processing to add "246", a value calculated by subtracting "9", the maximum value in the judgment range ("1" to "9"), from "255", the maximum value for 1 byte of numerical information, to the value of A register 101b where the data of index value counter 74f is set, and then determining whether the 1 byte of numerical information stored in A register 101b after adding "246" is greater than or equal to "247", a value calculated by adding "246" to "1", the minimum value in the judgment range. This reduces the number of jump instructions (JRS instructions) compared to the processing configuration, as in the first comparative example of lottery result processing (Figure 67(a)), which determines whether the value of A register 101b where the data of index value counter 74f is set is greater than or equal to "1", the minimum value in the judgment range ("1" to "9"), and determines whether the value of A register 101b is less than or equal to "9", the maximum value in the judgment range. This reduces the risk of unused programs.

The lottery result response processing (Figure 66) sets a JRS instruction to jump to program addresses "ADR122" and "ADR125" on the condition that the value of the jump flag JF is "1", and taking advantage of the fact that the state of the jump flag JF does not change even when the JRS instruction is executed, jumps to the program address of line number "1215" using a JRS instruction with a word length of 1 byte on the condition that the value of the jump flag JF is "1" at line number "1208", and then jumps reliably to the program address of line number "1218" using a JRS instruction with a word length of 1 byte set at the jump destination line number "1215". This reduces the word length of the jump instructions set to jump from program address "ADR122" and program address "ADR125" to program address "ADR126," compared to the processing configuration in the second comparative example of lottery result response processing (FIG. 68(b)), which jumps directly to line number "1218" using a 2-byte JR instruction on the condition that the carry flag CF is set to "1" at line number "1208." This reduces the data size of the program stored in main ROM 73 to execute lottery result response processing (FIG. 66).

The initial addition process (Figure 69 (b)) is configured to perform the following processing: subtracting "11", the minimum value of the first lottery target range ("11" to "15"), from the value of A register 101b in which the data of index value counter 74f is set; and determining whether the value of A register 101b after subtracting "11" is less than "5", which is a value "1" greater than the value calculated by subtracting "11" from "15", the maximum value of the first lottery target range. This reduces the total word length of the instructions set in the program to determine whether the value of the index value counter 74f is within the first lottery range, compared to the processing configuration of the first comparative example of the start-up addition process (FIG. 70(a)), which determines whether the value of the A register 101b, to which the data of the index value counter 74f is set, is greater than or equal to "11," the minimum value of the first lottery range, and determines whether the value of the A register 101b is less than or equal to "15," the maximum value of the first lottery range. Therefore, the data size of the program stored in the main ROM 73 to execute the start-up addition process (FIG. 69(b)) can be reduced.

The start-up addition process (Figure 69 (b)) is configured to perform the following processes: subtracting "11", the minimum value of the first lottery target range ("11" to "15"), from the value of A register 101b in which the data of index value counter 74f is set; determining whether the value of A register 101b after subtracting "11" is less than "5", which is a value "1" greater than the value calculated by subtracting "11" from "15", the maximum value of the first lottery target range; and determining whether the value of A register 101b after subtracting "11" is greater than or equal to "3", the value calculated by subtracting "11" from "14", the minimum value of the second lottery target range ("14" to "15"). This makes it possible to reduce the total word length of the instructions set in the program to set the first add-on lottery table as the reference lottery table when the value of the index value counter 74f is either "11" to "13", and to set the second add-on lottery table as the reference lottery table when the value of the index value counter 74f is "14" or "15", compared to a processing configuration that performs the following, as in the first comparative example of the start-up add-on processing (Figure 70 (a)), which performs the following: determining whether the value of the A register 101b, to which the data of the index value counter 74f is set, is greater than or equal to "11", the minimum value of the first lottery target range ("11" to "15"); determining whether the value of the A register 101b is less than or equal to "15", the maximum value of the first lottery target range; and determining whether the value of the A register 101b is greater than or equal to "14", the minimum value of the second lottery target range ("14" to "15"). This reduces the data size of the program stored in the main ROM 73 to execute the start-up top-up process (Figure 69 (b)).

In a configuration in which an operation to subtract 11 from the index value IV is performed to determine whether the index value IV is within the first lottery range, the value obtained by shifting the index value IV downward by 11 is used to determine whether the index value before the shift is within the second lottery range. After performing an operation to shift the first lottery range (11 to 15) downward by 11 (a calculation to subtract 11), a determination is made as to whether the value obtained by the operation is equal to or greater than 3, which is the value obtained by shifting the minimum value (14) of the second lottery range (14 to 15) downward by 11. This allows the boundary value used to determine whether the index value IV is within the second lottery range (14 to 15) to be set to 3, which is smaller than the minimum value (14) of the second lottery range. The number of bits required to represent the boundary value ("3") when determining whether the value obtained by shifting the index value IV downward by "11" is "3" or greater is "2," which is smaller than the number of bits ("4") required to represent the boundary value ("14") when determining whether the index value IV before the shift is "14" or greater, the minimum value of the second selection range. This reduces the number of bits required to represent the boundary value used to determine whether the index value IV is within the second selection range. This reduces the data capacity required to store the boundary value.

The start-time increment process (Fig. 69(b)) is configured to jump to line number "1309" using a 1-byte JRS instruction on the condition that the jump flag JF is set to "1" at line number "1307," and then jump to program address "ADR133" using the JP instruction set at the jump destination line number "1309." This reduces the total word length of the jump instructions set to jump from program addresses "ADR131" and "ADR132" to program address "ADR133," compared to the second comparative example of start-time increment process (Fig. 71(b)), which jumps directly to program address "ADR133" using a 3-byte JP instruction on the condition that the carry flag CF is set to "1" at line number "1307." This reduces the data size of the program stored in the main ROM 73 to execute the start-up top-up process (Figure 69 (b)).

By executing the JP command "JP ADR133" at line number "1309" in the start-time surcharge processing (FIG. 69(b)), a jump is made to the program address (ADR133) where an instruction for executing step S1802 of the release game number lottery processing (FIG. 35(b)) is set, and when step S1801 is executed in the release game number lottery processing (FIG. 35(b)), step S1802 is executed without calling a subroutine program. Therefore, compared to a configuration in which a common subroutine called the lottery execution processing is called in the release game number lottery processing (FIG. 35) and the start-time surcharge processing (FIG. 69(b)), the data size of the program stored in the main ROM 73 for executing the release game number lottery processing (FIG. 35) and the start-time surcharge processing (FIG. 69(b)) can be reduced.

Second Embodiment
This embodiment differs from the first embodiment in that when the primary MPU 72 sets a start command or an end command in the transmission standby buffer 112, the primary MPU 72 transfers data by specifying the start address and end address of the transfer target range in the primary RAM 74. The following describes the configuration that differs from the first embodiment. Note that a description of the same configuration as the first embodiment will generally be omitted.

Figure 72 (a) is an explanatory diagram illustrating the configuration of the main RAM 74 in this embodiment. As shown in Figure 72 (a), the main RAM 74 is provided with an end position counter 131. The end position counter 131 is a counter that allows the main MPU 72 to grasp the end address (2 bytes) of the transfer range in the common command transmission process (Figure 72 (b)) and top-level aggregation process (Figure 73) described below. The end position counter 131 consists of 2 bytes.

Similar to the first embodiment described above, the transfer target range in the common command transmission process (Figure 72(b)) is the consecutive address range of "0001H" to "000DH" in the main RAM 74, and the transfer target range in the top-level consolidation process (Figure 73) is the consecutive address range of "0001H" to "0006H" in the main RAM 74. The end address of the transfer target range in the common command transmission process (Figure 72(b)) is "000DH", and the end address of the transfer target range in the top-level consolidation process (Figure 73) is "0006H".

Figure 72 (b) is a flowchart showing the common command transmission process executed by the main MPU 72. As already explained in the first embodiment above, the common command transmission process is executed in step S2709 when the start command flag in the main RAM 74 is set to "1" (step S2707: YES) or when the end command flag in the main RAM 74 is set to "1" (step S2708: YES) in the command output process (Figure 44). As already explained, the start command flag is set to "1" in step S1107 of the lottery result response process (Figure 25) when a game starts, and the end command flag is set to "1" in step S1508 of the game end response process (Figure 32) when the game ends.

The common command transmission process first executes the top-level aggregation process (step S4001). Figure 73 is a flowchart showing the top-level aggregation process.

In the top-level aggregation process, steps S4101 to S4104 are performed in the same manner as steps S2901 to S2904 in the top-level aggregation process (Figure 51) in the first embodiment. Specifically, the address of the top-level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 of the main RAM 74 (step S4101). This allows the top-level aggregation area 74v to be set as the destination storage area. The top-level aggregation area 74v is then cleared to "0" (step S4102), and the value of the bit designation counter 117 in the main RAM 74 is cleared to "0" (step S4103). This allows the 0th bit of the top-level aggregation area 74v to be set as the destination bit. Then, "0001H", which is the start address of the transfer target range ("0001H" to "0006H") in the top-level aggregation process (FIG. 73), is set in the transfer source counter 116 in the main RAM 74 (step S4104). This makes it possible to set the lower area of the AT continuation counter 74u, which is set at address "0001H", as the transfer source storage area.

Then, "0006H", which is the end address of the transfer target range ("0001H" to "0006H") in the top-level aggregation process (Figure 73), is set in the end position counter 131 in the main RAM 74 (step S4105). This makes it possible for the main MPU 72 to grasp the end address. Then, the most significant bit of data in the source memory area is transferred to the destination bit (step S4106). As already explained in the first embodiment above, the main MPU 72 identifies the source memory area based on the address stored in the source counter 116, and identifies the destination bit based on the address stored in the destination counter 115 and the value of the bit designation counter 117.

Then, it is determined whether the address set in the transfer source counter 116 is the end address ("0006H") set in the end position counter 131 in step S4105 (step S4107). If the address set in the transfer source counter 116 is not the end address ("0006H") (step S4107: NO), the value of the transfer source counter 116 is incremented by 1 to update the transfer source storage area (step S4108). The processes of steps S4106 to S4109 are repeated until a positive determination is made in step S4107, and in step S4108 the address of the transfer source storage area is updated in the following order: "0001H" → "0002H" → "0003H" → "0004H" → "0005H" → "0006H".

Then, the value of the bit designation counter 117 is incremented by 1 to update the destination bit (step S4109). In step S4109, the destination bits are updated in the order of bit 0 → bit 1 → bit 2 → bit 3 → bit 4 → bit 5 in the most significant aggregation area 74v. Then, proceed to step S4106, and repeat steps S4106 to S4109 until a positive determination is made in step S4107. This allows the most significant bit data in the storage area included in the transfer target range ("0001H" to "0006H") to be set to bits 0 to 5 in the most significant aggregation area 74v.

In this way, the top-level aggregation process (Figure 73) sets the start address ("0001H") and end address ("0006H") of the transfer range ("0001H" to "0006H"), and repeatedly executes the following processes until the address of the source memory area reaches the end address: transferring the most significant bit of data in the source memory area to the destination bit (processing in step S4106), updating the address of the source memory area (processing in step S4108), and updating the destination bit (processing in step S4109). This simplifies the processing configuration for setting the most significant bit of data in the memory area of the transfer range in the top-level aggregation area 74v.

Returning to the explanation of the common command transmission process (Figure 72(b)), after executing the top-level aggregation process (Figure 73) in step S4001, steps S4002 to S4009 execute the same processing as steps S2802 to S2809 of the common command transmission process (Figure 50) in the first embodiment described above. Specifically, the value of the write pointer 113 (Figure 45) in the transmission circuit 85 is first determined to identify the write destination area in the transmission standby buffer 112 (step S4002). Thereafter, if the start command flag in the main RAM 74 is set to "1" (step S4003: YES), i.e., if it is the start of the game, the data in the header HD corresponding to the start command stored in the main ROM 73 is set to the write destination area determined in step S4002 (step S4004), and the start command flag is cleared to "0" (step S4005). On the other hand, if the start command flag is not set to "1" (step S4003: NO), i.e., if the game is ending, the header HD data corresponding to the end command stored in the main ROM 73 is set to the write destination area identified in step S4002 (step S4006), and the end command flag in the main RAM 74 is cleared to "0" (step S4007).

If step S4005 or step S4007 is performed, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4008). In step S4008, the value of the write pointer 113 is incremented by 1. If the value of the write pointer 113 after incrementing by 1 exceeds the maximum value of "31," the write pointer 113 is cleared to "0." Then, in the main RAM 74, the start address of the transfer target range for transferring data to the transmission standby buffer 112 when transmitting a start command or an end command is set in the transfer source counter 116 of the main RAM 74 (step S4009). As already explained, the transfer target range in the common command transmission process (Figure 50) is the address range from "0001H" to "000DH." By setting the address "0001H" in the transfer source counter 116 in step S4009, the lower area of the AT continuation counter 74u can be set as the transfer source memory area. Then, the end address "000DH" is set in the end position counter 131 in the main RAM 74 (step S4010). "000DH" is the final address of the transfer range from "0001H" to "000DH".

Then, the data stored in the source memory area is transferred to the destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S4011). As already explained in the first embodiment, the main MPU 72 identifies the source memory area based on the address stored in the source counter 116. Then, the most significant bit (seventh bit) of the destination area is set to "0" (step S4012). This sets the most significant bit of the second to fourteenth frames FR2 to FR14 in the start command or end command to "0," and makes it possible to distinguish between the first frame FR1, in which data in the header HD is set, and the second to fourteenth frames FR2 to FR14.

Then, as in step S4008, the value of the write pointer 113 is updated (step S4013). Then, it is determined whether the data in the source counter 116 is the end address ("000DH") set in the end position counter 131 in step S4010 (step S4014). If the data in the source counter 116 is not the end address (step S4014: NO), the source memory area is updated by adding 1 to the value of the source counter 116 (step S4015). Steps S4011 to S4015 are repeated until a positive determination is made in step S4014. In step S4015, the address of the memory area that will become the source area is updated in the following order: "0001H" → "0002H" → "0003H" → ... → "000CH" → "000DH".

Then, proceed to step S4011, and repeat steps S4011 to S4015 until a positive determination is made in step S4014. This allows data from the storage area included in the transfer target range ("0001H" to "000DH") to be set in the transmission standby buffer 112. If a positive determination is made in step S4014, that is, when the transfer of data stored in the storage area included in the transfer target range to the transmission standby buffer 112 is completed, the footer FT data stored in the main ROM 73 is set in the write destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S4016). Then, as in steps S4008 and S4013, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4017), and this common command transmission process ends.

In this way, in the common command transmission process (Figure 72 (b)), the start address ("0001H") and end address ("000DH") of the transfer range ("0001H" to "000DH") are set in the main RAM 74, and the following processes are repeatedly executed: transferring data stored in the source memory area to the destination area in the transmission standby buffer 112 (processing in step S4011), updating the destination area (processing in step S4013), and updating the address of the source memory area (processing in step S4015) until the address of the source memory area reaches the end address. This simplifies the processing configuration for setting data stored in the memory area of the transfer range in the transmission standby buffer 112.

The present embodiment described above provides the following excellent effects:

The transfer range in the top-level aggregation process (Figure 73) is set to consecutive addresses (addresses "0001H" to "0006H") in the main RAM 74. In the top-level aggregation process (Figure 73), the start address ("0001H") and end address ("0006H") of the transfer range ("0001H" to "0006H") are set, and the following processes are repeatedly executed until the address of the source memory area reaches the end address: transferring the most significant bit of data in the source memory area to the destination bit (processing in step S4106), updating the address of the source memory area (processing in step S4108), and updating the destination bit (processing in step S4109). This simplifies the processing configuration for setting the most significant bit of data in the memory area of the transfer range in the top-level aggregation area 74v.

The transfer range in the common command transmission process (Figure 72 (b)) is set to consecutive addresses (addresses "0001H" to "000DH") in the main RAM 74. In the common command transmission process (Figure 72 (b)), the start address ("0001H") and end address ("000DH") of the transfer range ("0001H" to "000DH") are set in the main RAM 74, and the following processes are repeatedly executed until the address of the source memory area reaches the end address: transferring data stored in the source memory area to the destination area in the transmission standby buffer 112 (processing in step S4011), updating the destination area (processing in step S4013), and updating the address of the source memory area (processing in step S4015). This simplifies the processing configuration for setting data stored in the memory area of the transfer range in the transmission standby buffer 112.

Third Embodiment
This embodiment differs from the first embodiment in that, in addition to the start command and the end command, a BB transition command exists as a command in which data stored in the most significant bit is aggregated. The following describes the configuration that differs from the first embodiment. Note that a description of the same configuration as the first embodiment will be omitted.

In addition to the normal game state ST1, first CB state ST2, second CB state ST3, pseudo bonus state ST4, AT state ST5, and end preparation state ST6 already described in the first embodiment, there are also the first BB state and the second BB state. As already described in the first embodiment, the main ROM 73 stores a role selection table for when three coins are bet (Figure 19) and a role selection table for when two coins are bet (Figure 20). In this embodiment, the role selection table for when three coins are bet and the role selection table for when two coins are bet have an index value IV of "18" in which the first BB winning data is set and an index value IV of "19" in which the second BB winning data is set, in addition to the index values IV of "1" to "17" already described in the first embodiment. The probability of winning the first BB and the probability of winning the second BB on the winning combination table when three coins are bet are each approximately 1/437, and the probability of winning the first BB and the probability of winning the second BB on the winning combination table when two coins are bet are each approximately 1/437.

If the index value IV ("18") to which the first BB winning data is set is won in the role lottery process (Figure 18), the first BB winning data is set in the main RAM 74, and if the index value IV ("19") to which the second BB winning data is set is won, the second BB winning data is set in the main RAM 74. When the first BB winning data is set in the main RAM 74 and a first BB win is achieved, the game state transitions to the first BB state, and when the second BB winning data is set in the main RAM 74 and a second BB win is achieved, the game state transitions to the second BB state. If first BB winning data is set in the main RAM 74 and the game ends without a first BB win, the first BB winning data is carried over to the next game or thereafter. If second BB winning data is set in the main RAM 74 and the game ends without a second BB win, the second BB winning data is carried over to the next game or thereafter. The first BB winning data set in the main RAM 74 is cleared to "0" when a first BB win is achieved or when the all-clear process (step S106) is executed in the main processing (FIG. 10). The second BB winning data set in the main RAM 74 is cleared to "0" when a second BB win is achieved or when the all-clear process (step S106) is executed in the main processing (FIG. 10).

In the first BB state or the second BB state, one game can be played when the number of gaming media bets is "3." In the first BB state or the second BB state, the expected net increase in gaming media in one game is greater than "0." The first BB state ends when the total number of gaming media paid out in the first BB state reaches the termination threshold number of "300," and the second BB state ends when the total number of gaming media paid out in the second BB state reaches the termination threshold number of "150."

As already explained in the first embodiment with reference to Figure 31 (b), the main RAM 74 has a game status area 77. In this embodiment, a BB status flag is provided in the sixth bit of the game status area 77. The BB status flag is a flag that enables the main MPU 72 to determine whether the game status is the first BB status or the second BB status. The BB status flag is set to "1" when transitioning to the first BB status or the second BB status, and the BB status flag is cleared to "0" when the first BB status or the second BB status ends. The main MPU 72 determines whether the game status is the first BB status or the second BB status based on the BB status flag being set to "1". As already explained in the first embodiment, the data stored in the game status area 77 is set to the start command and the end command. The presentation side MPU 92 determines whether the game state is the first BB state or the second BB state based on the data in the game state area 77 set in the start command and end command.

Figure 74(a) is an explanatory diagram illustrating the configuration of the main RAM 74 in this embodiment. As shown in Figure 74(a), the main RAM 74 is provided with a coin limit counter 74x, an interval game counter 74y, a replay occurrence counter 74z, a cherry occurrence counter 74α, and a BB highest level aggregation area 74β. These coin limit counter 74x, interval game counter 74y, replay occurrence counter 74z, cherry occurrence counter 74α, and BB highest level aggregation area 74β are memory areas in which data is set in the BB transition command sent from the main MPU 72 to the presentation MPU 92 when a first BB win or a second BB win is achieved. The BB transition command will be described in detail later.

The limit number counter 74x is a counter that allows the main MPU 72 to determine whether the total number of gaming media paid out in the first BB state or the second BB state has reached the termination reference number (300 in the first BB state, 150 in the second BB state). If a first BB win is achieved, the limit number counter 74x is set to 300, and if a second BB win is achieved, the limit number counter 74x is set to 150. The limit number counter 74x consists of two bytes. As shown in Figure 74(a), the lower area (the area of the lower byte) of the limit number counter 74x is set to address "0021H" in the main RAM 74, and the upper area (the area of the upper byte) of the limit number counter 74x is set to address "0022H." When limit number counter 74x is set to "300" ("0000000100101100B" in binary), the value of the most significant bit in the lower and upper areas of limit number counter 74x will be "0." Furthermore, when limit number counter 74x is set to "150" ("0000000010010110B" in binary), the value of the most significant bit in the lower area of limit number counter 74x will be "1," and the value of the most significant bit in the upper area of limit number counter 74x will be "0." The lower area of limit number counter 74x is a storage area where the most significant bit can be set to "1," while the upper area of limit number counter 74x is a storage area where the most significant bit cannot be set to "1."

The interval game counter 74y is a counter that allows the main MPU 72 to keep track of the number of games played while a state other than the BB state (first BB state or second BB state) continues. The interval game counter 74y consists of two bytes. A value between "0" and "65535" is set in the interval game counter 74y. The main MPU 72 clears the value of the interval game counter 74y to "0" upon the end of the first BB state or second BB state, and increments the value of the interval game counter 74y by 1 upon the execution of a game in a gaming state other than the first BB state or the second BB state. However, if a game is executed in a gaming state other than the first BB state or the second BB state and the interval game counter 74y has its maximum value set to "65535," the interval game counter 74y will remain set to the maximum value ("65535"). The interval game number counter 74y counts the number of games within a numerical range of "0" to "65535" ("1111111111111111B" in binary notation), so the lower and upper areas of the interval game number counter 74y are storage areas in which a "1" can be set in the most significant bit.

The replay success counter 74z is a counter that allows the main MPU 72 to keep track of the number of replay wins that have occurred when a state other than the BB state (first BB state or second BB state) continues. The replay success counter 74z consists of two bytes. Numerical information between "0" and "65535" is set in the replay success counter 74z. The main MPU 72 clears the value of the replay success counter 74z to "0" upon the end of the first BB state or the second BB state, and increments the value of the replay success counter 74z by one upon the occurrence of a normal replay win, a first chance replay win, or a second chance replay win in a game state other than the first BB state or the second BB state. However, if a normal replay win, a first chance replay win, or a second chance replay win occurs when the game state is neither the first BB state nor the second BB state and the replay win counter 74z is set to its maximum value of "65535," the replay win counter 74z will maintain its maximum value ("65535"). Because the replay win counter 74z counts the number of replay wins within the range of "0" to "65535" ("111111111111111B" in binary), the lower and upper areas of the replay win counter 74z are storage areas in which the most significant bit can be set to "1."

The cherry formation counter 74α is a counter that allows the main MPU 72 to keep track of the number of cherry formations that occur when a state other than the BB state (first BB state or second BB state) continues. The cherry formation counter 74α consists of one byte. Numerical information between "0" and "255" is set in the cherry formation counter 74α. The main MPU 72 clears the value of the cherry formation counter 74α to "0" when the first BB state or the second BB state ends, and increments the value of the cherry formation counter 74α by one when a cherry formation occurs in a game state other than the first BB state or the second BB state. However, if a cherry win occurs when the game is in neither the first BB state nor the second BB state and the cherry formation counter 74α is set to its maximum value of 255, the cherry formation counter 74α will maintain its maximum value (255). Because the value of the cherry formation counter 74α can reach or exceed 128 (0000000010000000B in binary), the cherry formation counter 74α is a storage area in which a 1 can be set in its most significant bit.

The BB highest-level aggregation area 74β is a memory area that aggregates the "0" or "1" data stored in the lower and upper areas of the limit number counter 74x, the lower and upper areas of the interval game counter 74y, the lower and upper areas of the replay completion counter 74z, and the most significant bit (the 7th bit of the 0th to 7th bits) of the cherry completion counter 74α, all of which are set in the consecutive address range of "0021H" to "0027H." The BB highest-level aggregation area 74β consists of 1 byte. The most significant bit of data in the lower area of the limited number of coins counter 74x is set to the 0th bit of the BB highest aggregation area 74β, the most significant bit of data in the upper area of the limited number of coins counter 74x is set to the 1st bit of the BB highest aggregation area 74β, the most significant bit of data in the lower area of the interval game number counter 74y is set to the 2nd bit of the BB highest aggregation area 74β, the most significant bit of data in the upper area of the interval game number counter 74y is set to the 3rd bit of the BB highest aggregation area 74β, the most significant bit of data in the lower area of the replay occurrence counter 74z is set to the 4th bit of the BB highest aggregation area 74β, the most significant bit of data in the upper area of the replay occurrence counter 74z is set to the 5th bit of the BB highest aggregation area 74β, and the most significant bit of the cherry occurrence counter 74α is set to the 6th bit of the BB highest aggregation area 74β. The value of the most significant bit (7th bit) of the BB most significant aggregation area 74β is always "0", and the BB most significant aggregation area 74β is a storage area in which the most significant bit is never set to "1".

The BB top-level aggregation area 74β is set to address "0028H," which is contiguous with the address range "0021H" to "0027H." Because the memory areas in the main RAM 74 where data is set in the BB transition command are set in the contiguous address range "0021H" to "0028H," it is possible to simplify the processing configuration for setting data stored in the memory areas of the main RAM 74 in the BB transition command.

As described above, when a first BB win or a second BB win is achieved, the main MPU 72 sends a BB transition command to the production MPU 92. The BB transition command is a command that causes the production MPU 92 to understand that the first BB state or the second BB state has begun. As described above, the BB transition command contains data stored in the limit number counter 74x, interval game number counter 74y, replay count counter 74z, cherry count counter 74α, and BB top-level aggregation area 74β. When the effect-side MPU 92 determines that the value of the limit number counter 74x is "300" based on the BB transition command received from the main MPU 72, it controls the light emission of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63 so that the start effect of the first BB state is executed. When the effect-side MPU 92 determines that the value of the limit number counter 74x is "150" based on the BB transition command received from the main MPU 72, it controls the light emission of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63 so that the start effect of the second BB state is executed.

The presentation-side ROM 93 stores two light-emitting data tables for controlling the light emission of the upper lamp 61 during the start presentation of the first BB state, two sound data tables for controlling the sound output of the speaker 62 during the start presentation of the first BB state, and two image data tables for controlling the display of the image display device 63 during the start presentation of the first BB state. When executing the start presentation of the first BB state, the presentation-side MPU 92 selects a light-emitting data table using data from the interval game counter 74y set in the BB transition command, selects a sound data table using data from the replay completion counter 74z set in the BB transition command, and selects an image data table using data from the cherry completion counter 74α set in the BB transition command. Based on the selected light-emitting data table, sound data table, and image data table, the presentation-side MPU 92 executes the start presentation of the first BB state using the upper lamp 61, speaker 62, and image display device 63. This allows the start effect of the first BB state to be executed in a manner corresponding to the value of the interval game counter 74y, the value of the replay occurrence counter 74z, and the value of the cherry occurrence counter 74α.

The presentation-side ROM 93 stores two light-emitting data tables for controlling the light emission of the upper lamp 61 during the start presentation of the second BB state, two sound data tables for controlling the sound output of the speaker 62 during the start presentation of the second BB state, and two image data tables for controlling the display of the image display device 63 during the start presentation of the second BB state. When executing the start presentation of the second BB state, the presentation-side MPU 92 selects a light-emitting data table using data from the interval game counter 74y set in the BB transition command, selects a sound data table using data from the replay completion counter 74z set in the BB transition command, and selects an image data table using data from the cherry completion counter 74α set in the BB transition command. The presentation-side MPU 92 then executes the start presentation of the second BB state using the upper lamp 61, speaker 62, and image display device 63 based on the selected light-emitting data table, sound data table, and image data table. This allows the start of the second BB state to be executed in a manner corresponding to the value of the interval game counter 74y, the value of the replay formation count counter 74z, and the value of the cherry formation count counter 74α.

When a BB transition command is sent, the data stored in the most significant bit of the memory area in the main RAM 74, which is set in the address range of "0021H" to "0027H," is set to the BB most significant aggregation area 74β, and the data stored in the memory area in the main RAM 74, which is set in the address range of "0021H" to "0028H," is set to the transmission standby buffer 112. Furthermore, as already explained in the first embodiment above, when a start command or an end command is sent, the data stored in the most significant bit of the memory area in the main RAM 74, which is set in the address range of "0001H" to "0006H," is set to the most significant aggregation area 74v, and the data stored in the memory area in the main RAM 74, which is set in the address range of "0001H" to "000DH," is set to the transmission standby buffer 112.

The start command, end command, and BB transition command are sent to the production-side MPU 92 by executing the common command transmission process (Figure 74 (b)) described below. The common command transmission process is executed when the start command flag in the main RAM 74 is set to "1", the end command flag in the main RAM 74 is set to "1", or the BB transition command flag provided in the main RAM 74 is set to "1" during the command output process in step S211 of the timer interrupt process (Figure 11). The BB transition command flag is a flag that allows the main MPU 72 to know that a transition to the first BB state or the second BB state has occurred. The BB transition command flag is set to "1" when the condition for transitioning to the first BB state or the second BB state is met.

In a game in which a first BB win or a second BB win is achieved, the period from when the start command flag is set to "1" to when the BB transition command flag is set to "1" is longer than the acceleration period of reels 32L, 32M, and 32R (specifically, 0.3 seconds). Furthermore, the acceleration period of reels 32L, 32M, and 32R is longer than the interrupt cycle (1.49 milliseconds) of the timer interrupt process (Figure 11). In this game, the BB transition command flag is set to "1" after the process for sending the start command is executed in the common command send process, so the common command send process is not executed with both the start command flag and the BB transition command flag set to "1."

In the common command transmission process, the main MPU 72 determines that a start command will be sent if the start command flag is set to "1," and that a BB transition command will be sent if the BB transition command flag is set to "1." The main MPU 72 also determines that a BB transition command will be sent if the BB transition command flag is set to "0" and the end command flag is set to "1." When the common command transmission process is executed with the BB transition command flag and the end command flag set to "1," processing to send the BB transition command is executed, and processing to send the end command is executed in the next common command transmission process, which is executed approximately 1.49 milliseconds later. In this way, in a game in which a first BB win or a second BB win is achieved, commands are sent to the production MPU 92 in the following order: start command → BB transition command → end command.

Next, the common command transmission process executed by the main MPU 72 will be explained with reference to the flowchart in Figure 74 (b).

In the common command transmission process, steps S4201 and S4202 are executed in the same manner as steps S2801 and S2802 in the common command transmission process (Figure 50) in the first embodiment. Specifically, the top-level aggregation process is executed first (step S4201). Figure 75 is a flowchart showing the top-level aggregation process.

In the top-level aggregation process, a transfer destination setting process is executed (step S4301). In the transfer destination setting process, when a start command or an end command is sent, the address of the top-level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 of the main RAM 74. This allows the top-level aggregation area 74v to be set as the storage area for the transfer destination. In addition, when a BB transition command is sent, the address of the BB top-level aggregation area 74β in the main RAM 74 is set in the transfer destination counter 115. This allows the BB top-level aggregation area 74β to be set as the storage area for the transfer destination. As described above, the main MPU 72 determines that a start command will be sent if the start command flag is set to "1", and determines that a BB transition command will be sent if the BB transition command flag is set to "1". In addition, the main MPU 72 determines that a BB transition command will be sent if the value of the BB transition command flag is set to "0" and the value of the end command flag is set to "1".

Then, the destination storage area is cleared to "0" (step S4302). In step S4302, if the top-level aggregation area 74v was set as the destination storage area in step S4301, the top-level aggregation area 74v is cleared to "0." Also, if the BB top-level aggregation area 74β was set as the destination storage area in step S4301, the BB top-level aggregation area 74β is cleared to "0." Then, similar to step S2903 of the top-level aggregation process (FIG. 51) in the first embodiment, the value of the bit designation counter 117 in the primary RAM 74 is cleared to "0" (step S4303). This allows the 0th bit of the top-level aggregation area 74v to be set as the destination bit when sending a start command or end command, and the 0th bit of the BB top-level aggregation area 74β to be set as the destination bit when sending a BB transition command.

Then, the start address setting process for the top-level aggregation is executed (step S4304). In the start address setting process for the top-level aggregation, the start address of the transfer target range for the top-level aggregation process is set in the transfer source counter 116 of the main RAM 74. Specifically, when a start command or end command is sent, the transfer target range for the top-level aggregation process is the address range "0001H" to "0006H", and the start address of this transfer target range, "0001H", is set in the transfer source counter 116. Also, when a BB transition command is sent, the transfer target range for the top-level aggregation process is the address range "0021H" to "0027H", and the start address of this transfer target range, "0021H", is set in the transfer source counter 116.

Then, the transfer count setting process for the top-level aggregation is executed (step S4305). In the transfer count setting process for the top-level aggregation, when a start command or end command is sent, the transfer count counter 114 is set to "6", which is the number of storage areas included in the transfer target range ("0001H" to "0006H") in the top-level aggregation process. Also, when a BB transition command is sent, the transfer count counter 114 is set to "7", which is the number of storage areas included in the transfer target range ("0021H" to "0027H") in the top-level aggregation process.

Then, in steps S4306 to S4310, the same processing as steps S2906 to S2910 of the top-level aggregation process (Figure 51) in the first embodiment is executed. Specifically, the most significant bit of data in the source storage area is transferred to the destination bit (step S4306). The main MPU 72 identifies the source storage area based on the address stored in the source counter 116, and identifies the destination bit based on the address stored in the destination counter 115 and the value of the bit designation counter 117. The main MPU 72 then subtracts 1 from the value of the transfer count counter 114 (step S4307), and determines whether the value of the transfer count counter 114 after the subtraction is "0" (step S4308).

If a negative determination is made in step S4308, the value of the transfer source counter 116 is incremented by 1 to update the address of the transfer source storage area (step S4309). The processes of steps S4306 to S4310 are repeated until a positive determination is made in step S4308. In step S4309, when a start command or an end command is sent, the address of the transfer source storage area is updated in the following order: "0001H" → "0002H" → ... → "0005H" → "0006H". Furthermore, when a BB transition command is sent, the address of the transfer source storage area is updated in the following order: "0021H" → "0022H" → ... → "0026H" → "0027H".

Then, the value of the bit designation counter 117 in the main RAM 74 is incremented by 1 to update the destination bit in the destination storage area (step S4310). In step S4310, when a start command or end command is sent, the destination bit in the top-level aggregation area 74v is updated in the order of bit 0 → bit 1 → ... → bit 4 → bit 5. Also, when a BB transition command is sent, the destination bit in the BB top-level aggregation area 74β is updated in the order of bit 0 → bit 1 → ... → bit 5 → bit 6.

Then, proceed to step S4306, and repeat steps S4306 to S4310 until a positive determination is made in step S4308. As a result, when sending a start command or an end command, the data stored in the most significant bits of the six memory areas included in the address range of "0001H" to "0006H" can be set to bits 0 to 5 of the top-level aggregation area 74v, and when sending a BB transition command, the data stored in the most significant bits of the seven memory areas included in the address range of "0021H" to "0027H" can be set to bits 0 to 6 of the BB top-level aggregation area 74β. If a positive determination is made in step S4308, this top-level aggregation process ends.

In this way, in a configuration where the commands for consolidating data stored in the most significant bits are a start command, an end command, and a BB transition command, which has a different address range (transfer range in the top-level consolidation process) for consolidating data stored in the most significant bits than the start command and end command, by varying the start address of the transfer range in the top-level consolidation process and the number of transfers depending on the type of command to be sent, a common top-level consolidation process can be used to consolidate data stored in the most significant bits of the memory area set in the address range of "0001H" to "0006H" in the top-level consolidation area 74v when sending a start command or an end command, and data stored in the most significant bits of the memory area set in the address range of "0021H" to "0027H" can be consolidated in the BB top-level consolidation area 74β when sending a BB transition command. Therefore, compared to a configuration in which a process for aggregating data stored in the most significant bit when a BB transition command is sent is provided as a separate process from the process for aggregating data stored in the most significant bit when a start command or end command is sent, the data capacity of the program stored in the main ROM 73 for executing the process for aggregating data stored in the most significant bit can be reduced.

When a start command or end command is sent, the transfer target range in the top-level aggregation process is the consecutive address range of "0001H" to "0006H" in the main RAM 74. Furthermore, when a BB transition command is sent, the transfer target range in the top-level aggregation process is the consecutive address range of "0021H" to "0027H" in the main RAM 74. The source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source counter 116 in the main RAM 74 by 1 (processing in step S4309). This simplifies the processing configuration for sequentially updating the source memory area.

Since the transfer range in the top-level aggregation process is a continuous address range in the main RAM 74, the transfer range can be specified by setting the start address of the transfer range in the transfer source counter 116 in step S4304 and setting the number of transfers in the transfer count counter 114 in step S4305. This simplifies the processing configuration for specifying the transfer range in the top-level aggregation process.

Returning to the explanation of the common command transmission process (FIG. 74(b)), after executing the top-level aggregation process in step S4201, the value of the write pointer 113 in the transmission circuit 85 is obtained to determine the write destination area in the transmission standby buffer 112 (step S4202), and header setting process is executed (step S4203). In the header setting process, if the start command flag is set to "1," the header HD data corresponding to the start command stored in the main ROM 73 is set to the write destination area determined in step S4202. Also, if the BB transition command flag is set to "1," the header HD data corresponding to the BB transition command stored in the main ROM 73 is set to the write destination area determined in step S4202. Furthermore, if the BB transition command flag is set to "0" and the end command flag is set to "1," the header HD data corresponding to the end command stored in the main ROM 73 is set to the write destination area determined in step S4202.

Then, similar to step S2808 of the common command transmission process (FIG. 50) in the first embodiment, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4204). In step S4204, step S4209 (described later), and step S4214 (described later), the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31," the write pointer 113 is cleared to "0."

Then, the start address setting process is executed (step S4205). In the start address setting process, when a start command or an end command is sent, the transfer source counter 116 of the primary RAM 74 is set to "0001H", which is the start address of the transfer range ("0001H" to "000DH") in the common command sending process, and when a BB transition command is sent, the transfer source counter 116 of the primary RAM 74 is set to "0021H", which is the start address of the transfer range ("0021H" to "0028H") in the common command sending process.

Then, the transfer count setting process is executed (step S4206). In the transfer count setting process, when a start command or an end command is sent, the transfer count counter 114 in the main RAM 74 is set to "13", which is the number of memory areas included in the transfer target range ("0001H" to "000DH") in the common command sending process, and when a BB transition command is sent, the transfer count counter 114 is set to "8", which is the number of memory areas included in the transfer target range ("0021H" to "0028H") in the common command sending process.

Then, in steps S4207 through S4214, the same processing as steps S2811 through S2818 of the common command transmission process (Figure 50) in the first embodiment is executed. Specifically, the destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 is identified, and the source memory area is identified based on the address set in the source counter 116, and the data from the source memory area is transferred to the destination area (step S4207). Then, the most significant bit (the seventh bit) of the destination area is set to "0" (step S4208). This allows the most significant bit of the second through fourteenth frames FR2 through FR14 of the start or end command to be set to "0" when transmitting the start or end command, and also makes it possible to distinguish the header HD from the second through fourteenth frames FR2 through FR14 based on the value of the most significant bit. Furthermore, when a BB transition command is sent, the most significant bit value in the second to ninth frames FR2 to FR9 of the BB transition command can be set to "0," and the header HD can be distinguished from the second to ninth frames FR2 to FR9 based on the value of the most significant bit.

Then, as in step S4204, the value of the write pointer 113 is updated (step S4209), and the value of the transfer count counter 114 is decremented by 1 (step S4210). It is then determined whether the value of the transfer count counter 114 after decrementing by 1 is "0" (step S4211). If a negative determination is made in step S4211, that is, if the transfer of data stored in the 1-byte storage area included in the transfer target range to the transmission standby buffer 112 has not been completed, the value of the transfer source counter 116 is incremented by 1, thereby updating the address of the source storage area (step S4212). The processing of steps S4207 to S4212 is repeated until a positive determination is made in step S4211. In step S4212, when sending a start command or an end command, the address of the storage area that will be the source area is updated in the order of "0001H" → "0002H" → "0003H" → ... → "000CH" → "000DH", and when sending a BB transition command, the address of the storage area that will be the source area is updated in the order of "0021H" → "0022H" → "0023H" → ... → "0027H" → "0028H".

Then, proceed to step S4207, and repeatedly execute steps S4207 to S4212 until a positive determination is made in step S4211. As a result, when sending a start command or an end command, data stored in 14 memory areas included in the address range of "0001H" to "000DH" can be set in the send standby buffer 112, and when sending a BB transition command, data stored in 8 memory areas included in the address range of "0021H" to "0028H" can be set in the send standby buffer 112.

If a positive judgment is made in step S4211, the footer FT data stored in the main ROM 73 is set to the write destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S4213), and the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113, as in steps S4204 and S4209 (step S4214).

Then, the command flag is cleared (step S4215), and this common command transmission process ends. In the command flag clearing process in step S4215, if the start command flag is set to "1", the start command flag is cleared to "0". Furthermore, if the BB transition command flag is set to "1", the BB transition command flag is cleared to "0". Furthermore, if the value of the BB transition command is "0" and the end command flag is set to "1", the end command flag is cleared to "0". In the command flag clearing process (step S4215), if the BB transition command flag and the end command flag are set to "1", only the BB transition command flag is cleared to "0", and the end command flag remains set to "1". This allows the process to send the end command in the next common command transmission process, which will be executed approximately 1.49 milliseconds later.

In this way, in a configuration in which there are start commands, end commands, and BB transition commands in which the address range (transfer target range in the common command transmission process) for setting data in the command in the main RAM 74 differs from that of the start and end commands, by varying the information on the start address of the transfer target range and the number of transfers in the common command transmission process depending on the type of command to be transmitted, it is possible to use the common common command transmission process to set data stored in a memory area set in the address range of "0001H" to "000DH" in the transmission standby buffer 112 when transmitting a start command or end command, and to set data stored in a memory area set in the address range of "0021H" to "0028H" in the transmission standby buffer 112 when transmitting a BB transition command. Therefore, compared to a configuration in which a process for setting data from the main RAM 74 in the transmission standby buffer 112 when a BB transition command is sent is provided as a separate process from the process for setting data from the main RAM 74 in the transmission standby buffer 112 when a start command or an end command is sent, the data capacity of the program stored in the main ROM 73 for executing the process for setting data from the main RAM 74 in the transmission standby buffer 112 can be reduced.

When sending a start command or an end command, the transfer target range in the common command transmission process is the consecutive address range of "0001H" to "000DH" in the main RAM 74. Furthermore, when sending a BB transition command, the transfer target range in the common command transmission process is the consecutive address range of "0021H" to "0028H" in the main RAM 74. Because the transfer target range in the common command transmission process is a consecutive address range in the main RAM 74, the transfer source memory area can be sequentially updated by repeatedly executing the process of incrementing the value of the transfer source counter 116 in the main RAM 74 by 1 (processing of step S4212). This simplifies the processing configuration for sequentially updating the transfer source memory area.

Since the transfer range in the common command transmission process is a continuous address range in the main RAM 74, the transfer range can be specified by setting the start address of the transfer range in the transfer source counter 116 in step S4205 and setting the number of transfers in the transfer count counter 114 in step S4206. This simplifies the processing configuration for specifying the transfer range in the common command transmission process.

The present embodiment described above provides the following excellent effects:

In a configuration where the commands that aggregate the data stored in the most significant bits are a start command, an end command, and a BB transition command, which has a different address range (transfer range in the top-level aggregation process) for which the data stored in the most significant bits is aggregated from the start command and end command, by varying the start address of the transfer range in the top-level aggregation process and the number of transfers depending on the type of command to be sent, a common top-level aggregation process can be used to aggregate the data stored in the most significant bits of the memory area set in the address range of "0001H" to "0006H" in the top-level aggregation area 74v when sending a start command or an end command, and aggregate the data stored in the most significant bits of the memory area set in the address range of "0021H" to "0027H" in the BB top-level aggregation area 74β when sending a BB transition command. Therefore, compared to a configuration in which a process for aggregating data stored in the most significant bit when a BB transition command is sent is provided as a separate process from the process for aggregating data stored in the most significant bit when a start command or end command is sent, the data capacity of the program stored in the main ROM 73 for executing the process for aggregating data stored in the most significant bit can be reduced.

In a configuration where there are start commands, end commands, and BB transition commands in which the address range (transfer range in the common command transmission process) for setting data in the command in the main RAM 74 differs from that of the start and end commands, by varying the start address of the transfer range and the number of transfers in the common command transmission process depending on the type of command to be transmitted, it is possible to use the common common command transmission process to set data stored in a memory area set in the address range of "0001H" to "000DH" in the transmission standby buffer 112 when transmitting a start command or end command, and to set data stored in a memory area set in the address range of "0021H" to "0028H" in the transmission standby buffer 112 when transmitting a BB transition command. Therefore, compared to a configuration in which a process for setting data from the main RAM 74 in the transmission standby buffer 112 when a BB transition command is sent is provided as a separate process from the process for setting data from the main RAM 74 in the transmission standby buffer 112 when a start command or an end command is sent, the data capacity of the program stored in the main ROM 73 for executing the process for setting data from the main RAM 74 in the transmission standby buffer 112 can be reduced.

<Fourth embodiment>
This embodiment differs from the first embodiment in that the storage areas of the primary RAM 74 in which data is set for the start command and the end command are identified using a data table (common data table 73f, described later) stored in the primary ROM 73. The following describes the configurations that differ from the first embodiment. Note that descriptions of the same configurations as the first embodiment will generally be omitted.

As already explained in the first embodiment above, data stored in multiple memory areas in the main RAM 74 is set in the start command and end command. In this embodiment, at least some of the memory areas in which data is set in the start command and end command are not set in a contiguous address range in the main RAM 74. Figure 76 is an explanatory diagram for explaining the common data table 73f stored in the main ROM 73 in this embodiment. The common data table 73f is a data table that allows the main MPU 72 to determine the addresses of the memory areas in the main RAM 74 in which data is set in the start command and end command. The common data table 73f is referenced when sending the start command and end command.

As shown in Figure 76 (a), the common data table 73f is set in the continuous address range of "9101H" to "911AH" in the main ROM 73. The main ROM 73 has many 1-byte storage areas, and each 1-byte storage area has a 2-byte address set in one-to-one correspondence. Each 1-byte storage area in the main ROM 73 is specified by a 2-byte address. As already explained in the first embodiment above, the main RAM 74 has many 1-byte storage areas, and each 1-byte storage area has a 2-byte address set in one-to-one correspondence. Each 1-byte storage area in the main RAM 74 is specified by a 2-byte address.

The 2-byte memory area corresponding to addresses "9101H" to "9102H" is set to the address of the lower area of the AT continuation counter 74u, the 2-byte memory area corresponding to addresses "9103H" to "9104H" is set to the address of the upper area of the AT continuation counter 74u, the 2-byte memory area corresponding to addresses "9105H" to "9106H" is set to the address of the lower area of the continued game number counter 74r, the 2-byte memory area corresponding to addresses "9107H" to "9108H" is set to the address of the upper area of the continued game number counter 74r, the 2-byte memory area corresponding to addresses "9109H" to "910AH" is set to the address of the lower area of the total winning number counter 74s, the 2-byte memory area corresponding to addresses "910BH" to "910CH" is set to the address of the upper area of the total winning number counter 74s, and the 2-byte memory area corresponding to addresses "910DH" to "91 The address of the top-level aggregation area 74v is set in a 2-byte memory area corresponding to addresses "910FH" to "9110H," the address of the bet number setting counter 74b is set in a 2-byte memory area corresponding to addresses "9111H" to "9112H," the address of the stop order type counter 74m is set in a 2-byte memory area corresponding to addresses "9113H" to "9114H," the address of the game status area 77 is set in a 2-byte memory area corresponding to addresses "9115H" to "9116H," the address of the game section area 76 is set in a 2-byte memory area corresponding to addresses "9117H" to "9118H," the address of the pseudo bonus continuation counter 74t is set in a 2-byte memory area corresponding to addresses "9119H" to "911AH," and the address of the award number counter 74e is set in a 2-byte memory area corresponding to addresses "9119H" to "911AH."

In the main ROM 73, the addresses of the memory areas where data is set for the start command and end command are set in the consecutive address range of "9101H" to "911AH." This simplifies the processing configuration for identifying the addresses of these memory areas when setting the data in these memory areas in the transmission standby buffer 112.

As in the first embodiment described above, the most significant bit of data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game counter 74r, and the lower and upper areas of the total wins counter 74s is aggregated in bits 0 to 5 of the most significant aggregation area 74v in the main RAM 74. In the main ROM 73, the addresses of the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game counter 74r, and the lower and upper areas of the total wins counter 74s, whose most significant bit of data is aggregated in the most significant aggregation area 74v, are set in the consecutive address range of "9101H" to "910CH." This simplifies the processing configuration for identifying the addresses of these lower and upper areas when setting the most significant bit of data in these lower and upper areas to bits 0 to 5 of the most significant aggregation area 74v.

In a configuration in which data is set in the start command and the end command while referencing a data table (common data table 73f) stored in the main ROM 73, the data table referenced when setting data in the start command and the data table referenced when setting data in the end command are the same. This makes it possible to reduce the data volume of the data tables stored in the main ROM 73 for the process of setting data in the start command and the end command.

The memory area of the main RAM 74 where data is set for the start command is the same as the memory area of the main RAM 74 where data is set for the end command. This allows the data table referenced when setting data for the start command and the data table referenced when setting data for the end command to be a common data table (common data table 73f).

Figure 76 (b) is an explanatory diagram illustrating the configuration of the main RAM 74. As shown in Figure 76 (b), the main RAM 74 is provided with a source address counter 132 and an end address counter 133. The source address counter 132 is a counter that allows the main MPU 72 to grasp the address in the main ROM 73 where the address of the source storage area in the main RAM 74 is set. The source address counter 132 consists of 2 bytes.

The end address counter 133 is a counter that allows the main MPU 72 to grasp the end address of the transfer target range in the common command transmission process (Figure 77) and top-level aggregation process (Figure 78) described below. The transfer target range in the common command transmission process (Figure 77) is the address range from "9101H" to "911AH" in the common data table 73f, and the end address of this transfer target range is "9119H". As described above, the grant number counter 74e is set at the end of this transfer target range, and "9119H" is the first address in the address range from "9119H" to "911AH" in which the address of the grant number counter 74e is set. The transfer target range in the top-level aggregation process (Figure 78) is the address range from "9101H" to "910CH" in the common data table 73f, and the end address of this transfer target range is "910BH". As mentioned above, the upper area of the total acquisition counter 74s is set at the end of the transfer range, and "910BH" is the first address in the address range from "910BH" to "910CH", where the addresses of the upper area of the total acquisition counter 74s are set.

Next, the common command transmission process executed by the main MPU 72 will be described with reference to the flowchart in FIG. 77. As already explained in the first embodiment above, the common command transmission process is executed in step S2709 when the start command flag in the main RAM 74 is set to "1" (step S2707: YES) or when the end command flag in the main RAM 74 is set to "1" (step S2708: YES) in the command output process (FIG. 44). As already explained, the start command flag is set to "1" in step S1107 of the lottery result response process (FIG. 25) when a game starts, and the end command flag is set to "1" in step S1508 of the game end response process (FIG. 32) when the game ends.

The common command transmission process first reads the common data table 73f stored in the main ROM 73 (step S4401). Then, the top-level aggregation process is executed (step S4402). Figure 78 is a flowchart showing the top-level aggregation process executed by the main MPU 72.

In the top-level aggregation process, the address of the top-level aggregation area 74v of the main RAM 74 is first set in the transfer destination counter 115 of the main RAM 74 (step S4501). This allows the top-level aggregation area 74v to be set as the destination storage area. The top-level aggregation area 74v is then cleared to "0" (step S4502), and the value of the bit designation counter 117 in the main RAM 74 is cleared to "0" (step S4503). This allows the 0th bit of the top-level aggregation area 74v to be set as the destination bit.

Then, "9101H," which is the start address of the transfer target range ("9101H" to "910CH") of the top-level aggregation process (Figure 78), is set in the transfer source address counter 132 (step S4504). This makes it possible to grasp the lower area of the AT continuation counter 74u as the transfer source storage area based on the addresses set in the addresses of "9101H" to "9102H" in the common data table 73f. Then, "910BH," which is the end address of the transfer target range ("9101H" to "910CH") of the top-level aggregation process (Figure 78), is set in the end address counter 133 of the main RAM 74 (step S4505).

Then, the most significant bit of data in the source memory area is transferred to the destination bit (step S4506). In step S4506, the address of the source memory area in the main RAM 74 is identified based on the data in the memory area corresponding to the address set in the source address counter 132 in the common data table 73f, and the destination bit is identified based on the data in the destination counter 115 and the value of the bit designation counter 117. Then, it is determined whether the data in the source address counter 132 is the end address set in the end address counter 133 in step S4505 (step S4507).

If the data in the source address counter 132 is not the end address (step S4507: NO), the source storage area is updated by incrementing the value of the source address counter 132 by 2 (step S4508). Steps S4506 to S4509 are repeated until a positive determination is made in step S4507. In step S4508, the addresses stored in the source address counter 132 are updated in the following order: "9101H" → "9103H" → "9105H" → ... → "9109H" → "910BH". The value of the bit designation counter 117 is then incremented by 1 to update the destination bit in the top-level aggregation area 74v (step S4509). In step S4509, the destination bits in the top-level aggregation area 74v are updated in the following order: 0th bit → 1st bit → ... → 4th bit → 5th bit.

Then, proceed to step S4506, and repeat steps S4506 to S4509 until a positive determination is made in step S4507. This allows the most significant bit data in the storage area determined based on the address set in the address range of "9101H" to "910CH" in the common data table 73f to be set to bits 0 to 5 of the most significant aggregation area 74v. If a positive determination is made in step S4507, this most significant aggregation process ends.

As already explained, in the main ROM 73, the addresses of the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game number counter 74r, and the lower and upper areas of the total winning number counter 74s, whose most significant bit data is aggregated in the most significant aggregation area 74v, are set in the consecutive address range of "9101H" to "910CH". Therefore, after setting the start address ("9101H") of the transfer range ("9101H" to "910CH") of the top-level aggregation process (FIG. 78) in the source address counter 132, the process of transferring the most significant bit of data in the source memory area to the destination bit (processing of step S4506), the process of updating the source memory area by adding 2 to the value of the source address counter 132 (processing of step S4508), and the process of updating the destination bit by adding 1 to the value of the bit designation counter 117 (processing of step S4509) are repeatedly executed, so that the most significant bit of data in the memory area of the main RAM 74 identified by the address set in the transfer range can be aggregated in the top-level aggregation area 74v. This simplifies the processing configuration for aggregating the most significant bit of data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game counter 74r, and the lower and upper areas of the total win counter 74s in the top-level aggregation area 74v.

Returning to the explanation of the common command transmission process (Figure 77), after executing the top-level aggregation process in step S4402, steps S4403 to S4409 execute the same processes as steps S2802 to S2808 of the common command transmission process (Figure 50) in the first embodiment described above. Specifically, the value of the write pointer 113 (Figure 45) in the transmission circuit 85 is determined to determine the write destination area in the transmission standby buffer 112 (step S4403). Thereafter, if the start command flag in the main RAM 74 is set to "1" (step S4404: YES), i.e., if it is the start of the game, the data in the header HD corresponding to the start command stored in the main ROM 73 is set to the write destination area determined in step S4403 (step S4405), and the start command flag is cleared to "0" (step S4406). On the other hand, if the start command flag is not set to "1" (step S4404: NO), i.e., if the game is ending, the header HD data corresponding to the end command stored in the main ROM 73 is set to the write destination area identified in step S4403 (step S4407), and the end command flag in the main RAM 74 is cleared to "0" (step S4408).

If the processing of step S4406 or step S4408 is performed, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4409). In step S4409, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

Then, "9101H," which is the start address of the transfer target range ("9101H" to "911AH") in the common command transmission process (FIG. 77), is set in the transfer source address counter 132 (step S4410). This makes it possible to grasp the lower area of the AT continuation counter 74u as the transfer source memory area based on the addresses set in the address range of "9101H" to "9102H" in the common data table 73f. Then, "9119H," which is the end address of the transfer target range ("9101H" to "911AH") in the common command transmission process (FIG. 77), is set in the end address counter 133 (step S4411).

Then, the data stored in the source memory area is transferred to the destination area in the transmission standby buffer 112 (step S4412). In step S4412, the address of the source memory area in the main RAM 74 is identified based on the data in the memory area corresponding to the address set in the source address counter 132 in the common data table 73f. Then, the most significant bit (bit 7) of the destination area is set to "0" (step S4413). This sets the most significant bit of the second to fourteenth frames FR2 to FR14 to "0," and makes it possible to distinguish between the header HD and the second to fourteenth frames FR2 to FR14 based on the value of the most significant bit.

Then, as in step S4409, the value of the write pointer 113 is updated (step S4414). Specifically, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31", the write pointer 113 is cleared to "0". Then, it is determined whether the data in the source address counter 132 is the end address ("9119H") set in the end address counter 133 in step S4411 (step S4415).

If the data in the source address counter 132 is not the end address (step S4415: NO), the value of the source address counter 132 is incremented by 2 to update the address referenced to determine the source storage area in the common data table 73f (step S4416). This allows the source storage area in the main RAM 74 to be updated. Steps S4412 to S4416 are repeated until a positive determination is made in step S4415. In step S4416, the addresses stored in the source address counter 132 are updated in the following order: "9101H" → "9103H" → "9105H" → ... → "9117H" → "9119H".

Then, the process proceeds to step S4412, and steps S4412 to S4416 are repeatedly executed until a positive determination is made in step S4415. This allows the data stored in the memory area of the main RAM 74 corresponding to the address set in the address range "9101H" to "911AH" in the common data table 73f to be set in the transmission standby buffer 112.

If a positive determination is made in step S4415, steps S4417 and S4418 execute the same processing as steps S2817 and S2818 of the common command transmission process (Figure 50) in the first embodiment described above. Specifically, the footer FT data stored in the main ROM 73 is set in the write destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S4417). Thereafter, as in steps S4409 and S4414, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4418), and the common command transmission process terminates.

As explained above, the addresses of the storage areas in the main RAM 74 where data is set in the start and end commands are set in the common data table 73f in the consecutive address range of "9101H" to "911AH." Therefore, after setting the start address ("9101H") of the transfer range ("9101H" to "911AH") in the common command transmission process (FIG. 77) in the transfer source address counter 132, the following steps are repeatedly executed: transferring the data from the source storage area to the destination area in the transmission standby buffer 112 (step S4412), updating the destination area (step S4414), and updating the source storage area by incrementing the value of the transfer source address counter 132 by 2. This simplifies the processing required to set data stored in the storage area of the main RAM 74 in the transmission standby buffer 112.

The present embodiment described above provides the following excellent effects:

In a configuration in which data is set in the start command and the end command while referencing a data table (common data table 73f) stored in the main ROM 73, the data table referenced when setting data in the start command and the data table referenced when setting data in the end command are the same. This makes it possible to reduce the data volume of the data tables stored in the main ROM 73 for the process of setting data in the start command and the end command.

The memory area of the main RAM 74 where data is set for the start command is the same as the memory area of the main RAM 74 where data is set for the end command. This allows the data table referenced when setting data for the start command and the data table referenced when setting data for the end command to be a common data table (common data table 73f).

In the main ROM 73, the addresses of the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game number counter 74r, and the lower and upper areas of the total winning number counter 74s, whose most significant bit data is aggregated in the most significant aggregation area 74v, are set in the consecutive address range of "9101H" to "910CH". Therefore, after setting the start address ("9101H") of the transfer range ("9101H" to "910CH") of the top-level aggregation process (FIG. 78) in the source address counter 132, the process of transferring the most significant bit of data in the source memory area to the destination bit (processing of step S4506), the process of updating the source memory area by adding 2 to the value of the source address counter 132 (processing of step S4508), and the process of updating the destination bit by adding 1 to the value of the bit designation counter 117 (processing of step S4509) are repeatedly executed, so that the most significant bit of data in the memory area of the main RAM 74 identified by the address set in the transfer range can be aggregated in the top-level aggregation area 74v. This simplifies the processing configuration for aggregating the most significant bit of data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game counter 74r, and the lower and upper areas of the total win counter 74s in the top-level aggregation area 74v.

The addresses of the storage areas in the main RAM 74 where data is set in the start and end commands are set in the consecutive address range of "9101H" to "911AH" in the common data table 73f. Therefore, after setting the start address ("9101H") of the transfer range ("9101H" to "911AH") in the common command transmission process (FIG. 77) in the transfer source address counter 132, the process of transferring the data in the source storage area to the destination area in the transmission standby buffer 112 (processing in step S4412), updating the destination area (processing in step S4414), and updating the source storage area by incrementing the value of the transfer source address counter 132 by 2 are repeatedly executed. This allows the data stored in the storage area in the main RAM 74 identified by the addresses set in the transfer range to be set in the transmission standby buffer 112. This simplifies the processing configuration for setting data stored in the storage areas in the main RAM 74 in the start and end commands.

Fifth Embodiment
This embodiment differs from the fourth embodiment in that, of the data stored in the memory area of the main RAM 74 ascertained based on the common data table 73f, only the data required by the presentation MPU 92 at the start of the game is set as the start command, and, of the data stored in the memory area of the main RAM 74 ascertained based on the common data table 73f, only the data required by the presentation MPU 92 at the end of the game is set as the end command. The following describes the configuration that differs from the fourth embodiment. Note that a description of the same configuration as the fourth embodiment will generally be omitted.

Figure 79(a) is an explanatory diagram illustrating the address range in which the address of the memory area of the main RAM 74 in which the data to be set in the start command is stored is set, and the address range in which the address of the memory area of the main RAM 74 in which the data to be set in the end command is stored, within the address range in which the common data table 73f of the main ROM 73 is set; Figure 79(b) is an explanatory diagram illustrating the data structure of the start command; and Figure 79(c) is an explanatory diagram illustrating the data structure of the end command.

As shown in FIG. 79(a), the common data table 73f has a first setting range and a second setting range, as well as a first exclusion range and a second exclusion range. The first setting range and the second setting range are address ranges in which addresses of the memory area of the main RAM 74 in which data to be set in the start command is stored are set. The first setting range is the address range of "9101H" to "9104H", and the second setting range is the address range of "910DH" to "9114H". The first exclusion range and the second exclusion range are address ranges in which addresses of the memory area of the main RAM 74 in which data is not set in the start command are set. The first exclusion range is the address range of "9105H" to "910CH", and the second exclusion range is the address range of "9115H" to "911AH".

As shown in Figure 79 (b), the start command contains data for the lower area of the AT continuation counter 74u, the upper area of the AT continuation counter 74u, the top aggregation area 74v, the bet number setting counter 74b, the stop order type counter 74m, and the game status area 77, which are determined based on the addresses set in the first setting range ("9101H" to "9104H") and the second setting range ("910DH" to "9114H"). This data is required by the presentation side MPU 92 when the game starts.

In this way, by configuring the start command so that only the data required by the production side MPU 92 at the start of the game is set, the data volume of the start command sent from the main side MPU 72 to the production side MPU 92 can be reduced. Furthermore, when the production side MPU 92 receives a start command, it is not necessary to extract only the data required by the production side MPU 92 at the start of the game from the data set in the start command. This reduces the processing load on the production side MPU 92 when it receives a start command.

As shown in FIG. 79(a), the common data table 73f has a third set range and a fourth set range set, as well as a third exclusion range and a fourth exclusion range set. The third set range and the fourth set range are address ranges in which addresses of the storage area of the main RAM 74 in which data to be set in the termination command is stored are set. The third set range is the address range of "9105H" to "910EH", and the fourth set range is the address range of "9113H" to "911AH". The third exclusion range and the fourth exclusion range are address ranges in which addresses of the storage area of the main RAM 74 in which data is not set in the termination command are set. The third exclusion range is the address range of "9101H" to "9104H", and the fourth exclusion range is the address range of "910FH" to "9112H".

As shown in Figure 79 (c), the end command contains data for the lower area of the continued game counter 74r, the upper area of the continued game counter 74r, the lower area of the total wins counter 74s, the upper area of the total wins counter 74s, the top aggregation area 74v, the game status area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the awarded number counter 74e, which are grasped based on the addresses set in the third setting range ("9105H" to "910EH") and the fourth setting range ("9113H" to "911AH"). This data is required by the presentation side MPU 92 when the game ends.

In this way, by configuring the end command so that only the data required by the production side MPU 92 at the end of the game is set, the data volume of the end command sent from the main MPU 72 to the production side MPU 92 can be reduced. Furthermore, when the production side MPU 92 receives the end command, it is no longer necessary to extract only the data required by the production side MPU 92 at the end of the game from the data set in the end command. This reduces the processing load on the production side MPU 92 when it receives the end command.

Figure 80(a) is an explanatory diagram illustrating the electrical configuration of the main control board 71 and performance control board 91 used to send commands from the main MPU 72 to the performance MPU 92. As shown in Figure 80(a), the performance RAM 94 has a top-level setting area 134. The top-level setting area 134 is a memory area used when executing a process to set the data from bits 0 to 5 in the top-level aggregated frame SF set in the start command or end command to the frame corresponding to those bits 0 to 5.

Figure 80(b) is an explanatory diagram illustrating the configuration of the highest setting area 134. As shown in Figure 80(b), the highest setting area 134 is provided with first to eleventh areas RC1 to RC11. The first to eleventh areas RC1 to RC11 are storage areas consisting of 1 byte. The total data capacity of the first to eleventh areas RC1 to RCA11 in the highest setting area 134 is 11 bytes. In the production-side RAM 94, the first to eleventh areas RC1 to RC11 of the highest setting area 134 are set in the consecutive address range of "γ+1" to "γ+11".

As shown in Figure 79 (b), the start command consists of eight frames (first to eighth frames FR1 to FR8). The production side MPU 92 sets the first to eighth frames FR1 to FR8 of the received start command to the first to eighth areas RC1 to RC8 of the top setting area 134. The second frame FR2, in which the data of the lower area of the AT continuation counter 74u in the main RAM 74 is set, is set to the second area RC2, the third frame FR3, in which the data of the upper area of the AT continuation counter 74u is set, is set to the third area RC3, and the top aggregation frame SF (fourth frame FR4), in which the data of the top aggregation area 74v is set, is set to the fourth area RC4. As already explained in the first embodiment, the "0" or "1" data stored in the most significant bit (bit 7) of the lower area of the AT duration counter 74u in the main RAM 74 is set to bit 0 of the highest aggregated frame SF, and the "0" data stored in the most significant bit of the upper area of the AT duration counter 74u is set to bit 1 of the highest aggregated frame SF. The production-side MPU 92 generates a post-conversion start command by setting the data of bit 0 in the fourth area RC4 to the most significant bit of the second area RC2 and setting the data of bit 1 in the fourth area RC4 to the most significant bit of the third area RC3. The production-side MPU 92 then stores the generated post-conversion start command in the command storage buffer 126. This allows the production-side MPU 92 to use the post-conversion start command.

As shown in Figure 79 (c), the end command consists of 11 frames (1st to 11th frames FR1 to FR11). The production side MPU 92 sets the 1st to 11th frames FR1 to FR11 of the received end command to the 1st to 11th areas RC1 to RC11 of the top setting area 134. The second frame FR2 in the main RAM 74, in which the data of the lower area of the continued game number counter 74r is set, is set to the second area RC2, the third frame FR3 in which the data of the upper area of the continued game number counter 74r is set, is set to the third area RC3, the fourth frame FR4 in which the data of the lower area of the total winning number counter 74s is set, is set to the fourth area RC4, the fifth frame FR5 in which the data of the upper area of the total winning number counter 74s is set, is set to the fifth area RC5, and the top aggregation frame SF (sixth frame FR6) in which the data of the top aggregation area 74v is set, is set to the sixth area RC6. As already explained in the first embodiment above, the data of "0" or "1" stored in the most significant bit (seventh bit) of the lower area of the continued game count counter 74r in the main RAM 74 is set to the second bit of the highest aggregated frame SF, the data of "0" stored in the most significant bit of the upper area of the continued game count counter 74r is set to the third bit of the highest aggregated frame SF, the data of "0" or "1" stored in the most significant bit of the lower area of the total winnings counter 74s is set to the fourth bit of the highest aggregated frame SF, and the data of "0" stored in the most significant bit of the upper area of the total winnings counter 74s is set to the fifth bit of the highest aggregated frame SF. The production side MPU 92 generates a post-conversion end command by setting the second bit of data in the sixth area RC6 to the most significant bit of the second area RC2, the third bit of data in the sixth area RC6 to the most significant bit of the third area RC3, the fourth bit of data in the sixth area RC6 to the most significant bit of the fourth area RC4, and the fifth bit of data in the sixth area RC6 to the most significant bit of the fifth area RC5. The production side MPU 92 then stores the generated post-conversion end command in the command storage buffer 126. This makes the post-conversion end command available to the production side MPU 92.

Next, the common command transmission process executed by the main MPU 72 will be described with reference to the flowchart in FIG. 81. As already explained in the first embodiment above, the common command transmission process is executed in step S2709 when the start command flag in the main RAM 74 is set to "1" (step S2707: YES) or when the end command flag in the main RAM 74 is set to "1" (step S2708: YES) in the command output process (FIG. 44). As already explained, the start command flag is set to "1" in step S1107 of the lottery result response process (FIG. 25) when a game starts, and the end command flag is set to "1" in step S1508 of the game end response process (FIG. 32) when the game ends.

In the common command transmission process, steps S4601 to S4605 are performed in the same manner as steps S4401 to S4405 in the common command transmission process (Figure 77) in the fourth embodiment. Specifically, first, the common data table 73f stored in the main ROM 73 is read (step S4601), and then the top-level aggregation process is performed (step S4602). In the top-level aggregation process, as already explained in the fourth embodiment with reference to the flowchart in Figure 78, the most significant bit data in the storage area of the main RAM 74, as determined based on the address set in the address range "9101H" to "910CH" in the common data table 73f, is set to bits 0 to 5 of the top-level aggregation area 74v. This top-level aggregation process (step S4602) is performed both when a start command and when an end command are transmitted.

As already explained, in the main RAM 74, the memory areas in which the most significant bit data is set in the top-level aggregation area 74v include the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game count counter 74r, and the lower and upper areas of the total wins counter 74s. Of these six memory areas, the memory areas in which data is set for the start command are the lower and upper areas of the AT continuation counter 74u, and the memory areas in which data is set for the end command are the lower and upper areas of the continued game count counter 74r, and the lower and upper areas of the total wins counter 74s. In this configuration, among the six storage areas whose most significant bit data is aggregated in the top-level aggregation area 74v, the storage areas in which data is set in the start command are different from the storage areas in which data is set in the end command. In both cases, the process of aggregating the most significant bit data from the six storage areas in the top-level aggregation area 74v (the top-level aggregation process of step S4602) is executed when the start command is sent and when the end command is sent. Therefore, compared to a configuration in which the process of setting the most significant bit data in the top-level aggregation area 74v is executed when the start command is sent, and the process of setting the most significant bit data in the top-level aggregation area 74v is executed when the end command is sent, the process of setting the most significant bit data in the top-level aggregation area 74v is executed only for the storage areas in which data is set in the end command.

Then, the value of the write pointer 113 (Figure 45) in the transmission circuit 85 is determined to determine the write destination area in the transmission standby buffer 112 (step S4603). If the start command flag in the main RAM 74 is set to "1" (step S4604: YES), i.e., if it is the start of the game, the header HD data indicating a start command stored in the main ROM 73 is set to the write destination area determined in step S4603 (step S4605). Then, the transfer source address counter 132 in the main RAM 74 is set to "9101H," which is the top address of the first setting range ("9101H" to "9104H") (step S4606). This allows the lower area of the AT continuation counter 74u in the main RAM 74 to be set as the transfer source storage area.

If the start command flag is not set to "1" (step S4604: NO), the header HD data stored in the main ROM 73 indicating that it is an end command is set to the write destination area identified in step S4603 (step S4607). Then, the source address counter 132 in the main RAM 74 is set to "9105H," which is the top address of the third setting range ("9105H" to "910EH") (step S4608). This allows the lower area of the continued game count counter 74r in the main RAM 74 to be set as the source memory area.

If step S4606 or step S4608 is performed, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4609), similar to step S4409 in the common command transmission process (FIG. 77) in the fourth embodiment. In step S4609, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

Then, in steps S4610 to S4612, the same processing as steps S4012 to S4014 of the common command transmission process (FIG. 77) in the fourth embodiment is performed. Specifically, data from the source memory area is first transferred to the destination area in the transmission standby buffer 112 (step S4610). In step S4610, the address of the source memory area in the main RAM 74 is identified based on the data in the memory area corresponding to the address set in the source address counter 132 in the common data table 73f. Then, the most significant bit (the seventh bit) of the destination area is set to "0" (step S4611). This allows the most significant bit of the second to seventh frames FR2 to FR7 of the start command to be set to "0" when transmitting the start command, and also makes it possible to distinguish the header HD from the second to seventh frames FR2 to FR7 based on the value of the most significant bit. Furthermore, when an end command is sent, the most significant bit of the second to tenth frames FR2 to FR10 of the end command can be set to "0," and the header HD can be distinguished from the second to tenth frames FR2 to FR10 based on the value of the most significant bit.

Then, as in step S4609, the value of the write pointer 113 is updated (step S4612). Specifically, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment exceeds the maximum value of "31", the write pointer 113 is cleared to "0". The value of the source address counter 132 is then incremented by "2" to update the address referenced to identify the source memory area in the common data table 73f (step S4613). This allows the source memory area in the main RAM 74 to be updated.

If the start command flag in the primary RAM 74 is set to "1" (step S4614: YES), it is determined whether the data in the source address counter 132 is "9105H," the starting address of the first exclusion range ("9105H" to "910CH") (step S4615). If the data in the source address counter 132 is "9105H" (step S4615: YES), the source address counter 132 is set to "910DH," the starting address of the second set range ("910DH" to "9114H") (step S4616). This allows the source storage area to be updated to the top-level aggregation area 74v. This also prevents data stored in the storage area of the primary RAM 74, which is determined based on the address set in the first exclusion range of the common data table 73f, from being set as the start command. If the data in the source address counter 132 is not "9105H" (step S4615: NO), it is determined whether the data in the source address counter 132 is "9115H", which is the starting address of the second exclusion range ("9115H" to "911AH") (step S4617).

If step S4616 is processed, or if a negative determination is made in step S4617, the process proceeds to step S4610, and steps S4610 to S4617 are repeatedly executed until a positive determination is made in step S4617. This allows data stored in a memory area of the main RAM 74 identified based on the addresses set in the first and second setting ranges of the common data table 73f to be set in the transmission standby buffer 112. Therefore, only the data required by the production MPU 92 at the start of the game can be set in the transmission standby buffer 112.

If a positive judgment is made in step S4617, i.e., if the process of setting the data stored in the memory area of the main RAM 74 identified based on the addresses set in the first and second setting ranges to the transmission standby buffer 112 is completed, the start command flag of the main RAM 74 is cleared to "0" (step S4618).

If the start command flag in the main RAM 74 is not set to "1" (step S4614: NO), it is determined whether the data in the source address counter 132 is "910FH," the starting address of the fourth exclusion range (910FH to 9112H) (step S4619). If the data in the source address counter 132 is "910FH" (step S4619: YES), the source address counter 132 is set to "9113H," the starting address of the fourth set range (9113H to 911AH) (step S4620). This allows the source memory area to be updated to the game status area 77. This also prevents data stored in the memory area of the main RAM 74, which is determined based on the address set in the fourth exclusion range of the common data table 73f, from being set as the end command. If the data in the source address counter 132 is not "910FH" (step S4619: NO), it is determined whether the data in the source address counter 132 is "911BH" (step S4621). "911BH" is the address next to "911AH", which is the last address in the fourth setting range ("9113H" to "911AH").

If step S4620 is performed, or if a negative determination is made in step S4621, the process proceeds to step S4610, and steps S4610 through S4614 and steps S4619 through S4621 are repeatedly executed until a positive determination is made in step S4621. This allows data stored in a memory area of the main RAM 74 identified based on the addresses set in the third and fourth setting ranges of the common data table 73f to be set in the transmission standby buffer 112. Therefore, only data required by the production MPU 92 at the end of the game can be set in the transmission standby buffer 112.

If a positive judgment is made in step S4621, i.e., if the process of setting the data stored in the memory area of the main RAM 74 identified based on the addresses set in the third and fourth setting ranges to the transmission standby buffer 112 is completed, the end command flag of the main RAM 74 is cleared to "0" (step S4622).

If step S4618 or step S4622 has been performed, steps S4623 and S4624 execute the same processing as steps S4417 and S4418 of the common command transmission process (FIG. 77) in the fourth embodiment. Specifically, the footer FT data stored in the main ROM 73 is set in the write destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S4623). Thereafter, as in steps S4609 and S4612, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4624), and the common command transmission process terminates.

In this way, when sending a start command or an end command, first the data of the most significant bit in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game number counter 74r, and the lower and upper areas of the total winnings counter 74s is set to bits 0 to 5 of the most significant aggregation area 74v (top-level aggregation process in step S4602), and then, if a start command is being sent, the data required by the presentation side MPU 92 at the start of the game is set in the transmission standby buffer 112, and if an end command is being sent, the data required by the presentation side MPU 92 at the end of the game is set in the transmission standby buffer 112. In a configuration in which only a portion of the memory area in the main RAM 74 where data is set for start commands is shared with the memory area where data is set for end commands, the process of setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game count counter 74r, and the lower and upper areas of the total win count counter 74s to bits 0 through 5 of the top-level aggregation area 74v (top-level aggregation process in step S4602) is executed using the same subroutine program. This reduces the data capacity of the program stored in the main ROM 73 for executing this process.

Next, the command reception response processing executed by the production-side MPU 92 will be explained with reference to the flowchart in Figure 82. As already explained in the first embodiment above, the command reception response processing is repeatedly executed by the production-side MPU 92 at relatively short intervals (for example, every 4 milliseconds).

In the command reception response processing, steps S4701 to S4707 are performed in the same manner as steps S3001 to S3007 in the command reception response processing (Figure 52) in the first embodiment described above. Specifically, if header HD data and footer FT data are set in the post-reception standby buffer 122 of the receiving circuit 87 (step S4701: YES, step S4702: YES), the start and end of the command to be moved from the post-reception standby buffer 122 to the top setting area 134 of the performance-side RAM 94 or the command storage buffer 126 (the command to be moved) are determined (step S4703). In step S4703, the start of the command to be moved is determined based on the value of the read pointer 128 in the post-reception standby buffer 122, and the end of the command to be moved is determined based on the footer FT data of the command to be moved. If multiple commands are stored in the post-reception standby buffer 122, the first of the multiple commands stored in the post-reception standby buffer 122 is determined to be the command to be moved, based on the value of the read pointer 128. Thereafter, if the command to be moved identified in step S4703 has start command header HD data set (step S4704: YES), this means that the command to be moved is a start command, and so the start reception correspondence table is read from the production-side ROM 93 (step S4705). On the other hand, if the command to be moved identified in step S4703 has end command header HD data set (step S4704: NO, step S4706: YES), this means that the command to be moved is an end command, and so the end reception correspondence table is read from the production-side ROM 93 (step S4707).

If step S4705 or step S4707 is performed, the highest level setting process is executed (step S4708). Figure 83 is a flowchart showing the highest level setting process (step S4708) executed by the production-side MPU 92.

In the top-level setting process, the start command or end command stored in the post-reception standby buffer 122 is first set in the top-level setting area 134 in the production-side RAM 94 (step S4801). In step S4801, if a start command is stored in the post-reception standby buffer 122, the first through eighth frames FR1 through FR8 of that start command are set in the first through eighth areas RC1 through RC8 of the top-level setting area 134, and if an end command is stored in the post-reception standby buffer 122, the first through eleventh frames FR1 through FR11 of that end command are set in the first through eleventh areas RC1 through RC11 of the top-level setting area 134.

Then, a clearing process is performed on the post-reception standby buffer 122 (step S4802). In this clearing process, the area in the post-reception standby buffer 122 where the start command or end command was stored is cleared to "0". This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. The value of the read pointer 128 in the post-reception standby buffer 122 is then updated to a value corresponding to the storage area next to the storage area where the end of the start command or end command (footer FT data) was stored (step S4803).

If the command set in the top setting area 134 in step S4801 is a start command (step S4804: YES), the address of the fourth area RC4 in that top setting area 134 is set in the production side transfer source counter in the production side RAM 94 (step S4805). As already explained, the fourth area RC4 is the area in which the top aggregate frame SF of the start command is set. As already explained in the first embodiment above, the production side transfer source counter is a counter that allows the production side MPU 92 to grasp the memory area from which data is being transferred. By setting the address of the fourth area RC4 in the production side transfer source counter in step S4805, the fourth area RC4 can be set as the memory area from which data is being transferred.

Then, the presentation-side bit designation counter in the presentation-side RAM 94 is cleared to "0" (step S4806). As already explained in the first embodiment above, the presentation-side bit designation counter is a counter that allows the presentation-side MPU 92 to grasp the source bit in the source memory area. By clearing the value of the presentation-side bit designation counter to "0" in step S4806, the 0th bit in the fourth area RC4 can be set as the source bit.

As described above, the top-level setting process is executed when a start command or end command is set in the top-level setting area 134. If a negative determination is made in step S4804, this means that the command set in the top-level setting area 134 in step S4801 is an end command, and the address of the sixth area RC6 in that top-level setting area 134 ("γ+6") is set in the production-side transfer source counter in the production-side RAM 94 (step S4807). This makes the sixth area RC6 the transfer source memory area. As already explained, the sixth area RC6 is the area where the top-level aggregate frame SF (sixth frame FR6) of the end command is set. Then, the production-side bit designation counter in the production-side RAM 94 is set to "2" (step S4808). This allows the second bit of the sixth area RC6 to be set as the transfer source bit.

After processing step S4806 or step S4808, the address of second area RC2 in the top setting area 134 is set in the director's transfer destination counter in the director's RAM 94 (step S4809). As already explained in the first embodiment above, the director's transfer destination counter is a counter that allows the director's MPU 92 to grasp the destination storage area. By setting the address of second area RC2 in the director's transfer destination counter in step S4809, the second area RC2 can be used as the destination storage area.

Then, the data "0" or "1" stored in the source bit is set to the most significant bit in the destination memory area (step S4810). Then, based on the value of the production-side bit designation counter, it is determined whether the process of setting the data aggregated in the highest aggregated frame SF to the most significant bit of the corresponding frame has been completed (step S4811). In step S4811, if a start command is set in the highest setting area 134, a positive determination is made if the value of the production-side bit designation counter is "1", and if an end command is set in the highest setting area 134, a positive determination is made if the value of the production-side bit designation counter is "5".

If a negative determination is made in step S4811, the value of the production-side bit designation counter is incremented by 1, thereby updating the source bit in the source memory area (fourth area RC4 or sixth area RC6) (step S4812). The processes of steps S4810 to S4813 are repeated until a positive determination is made in step S4811. In step S4812, if a start command is set in the highest setting area 134, the source bits in the fourth area RC4 are updated in the order of bit 0 → bit 1, and if an end command is set in the highest setting area 134, the source bits in the sixth area RC6 are updated in the order of bit 2 → bit 3 → bit 4 → bit 5.

Then, the destination memory area is updated by adding 1 to the value of the director's destination counter (step S4813). In step S4813, if a start command is set in the top-level setting area 134, the destination memory areas in the top-level setting area 134 are updated in the order of second area RC2 → third area RC3, and if an end command is set in the top-level setting area 134, the destination memory areas in the top-level setting area 134 are updated in the order of second area RC2 → third area RC3 → fourth area RC4 → fifth area RC5.

Then, proceed to step S4810, and repeat steps S4810 to S4813 until a positive determination is made in step S4811. As a result, if the command set in the top-level setting area 134 in step S4801 is a start command, the converted start command can be set in the top-level setting area 134, and if the command set in the top-level setting area 134 in step S4801 is an end command, the converted end command can be set in the top-level setting area 134. If a positive determination is made in step S4811, this top-level setting process is terminated.

As described above, the data stored in the lower and upper areas of the AT continuation counter 74u is set in the second to third consecutive frames FR2 to FR3 in the start command. Therefore, by repeatedly incrementing the value of the presentation-side transfer destination counter (step S4813), the transfer destination memory area where the data aggregated in the top aggregated frame SF is set can be sequentially updated. This simplifies the processing configuration for the presentation-side MPU 92 to set the data aggregated in the 0th to 1st bits in the top aggregated frame SF of the start command to the most significant bit of the second to third frames FR2 to FR3 corresponding to those 0th to 1st bits. Furthermore, the data stored in the lower and upper areas of the continued game counter 74r and the lower and upper areas of the total win counter 74s are set in the second to fifth consecutive frames FR2 to FR5 in the end command. Therefore, by repeatedly incrementing the value of the production-side transfer destination counter by 1 (step S4813), the transfer destination memory area where the data aggregated in the highest aggregated frame SF is set can be sequentially updated. This simplifies the processing structure for the production-side MPU 92 to set the data aggregated in the second through fifth bits of the highest aggregated frame SF of the termination command to the highest bits of the second through fifth frames FR2 through FR5 that correspond to those second through fifth bits.

Returning to the explanation of the command reception response processing (Figure 82), after the highest-level setting processing is performed in step S4708, steps S4709 to S4714 perform processing similar to steps S3010 to S3015 of the command reception response processing (Figure 52) in the first embodiment described above. Specifically, the value of the second write pointer 129 (Figure 80(a)) in the production-side RAM 94 is determined to determine the write destination area in the command storage buffer 126 (step S4709). Then, the converted start command or converted end command stored in the highest-level setting area 134 is set to the write destination area determined in step S4709 (step S4710). This allows the converted start command or converted end command to be stored in the command storage buffer 126, making it possible for the converted start command or converted end command to be available for use by the production-side MPU 92.

Then, the value of the second write pointer 129 is updated (step S4711). In step S4711, if the data of the post-conversion start command was written to the command storage buffer 126 in step S4710, "8", which is the data size of the post-conversion start command, is added to the value of the second write pointer 129. If the data of the post-conversion end command was written to the command storage buffer 126 in step S4710, "11", which is the data size of the post-conversion end command, is added to the value of the second write pointer 129. In step S4711, if the result of the operation to add "8" or "11" exceeds the maximum value of "63", the second write pointer 129 is set to a value that is "64" less than the result of the operation. For example, if the result of the operation to add "8" or "11" is "64", which exceeds the maximum value of "63", the second write pointer 129 is set to "0", which is "64" less than the result of the operation ("64").

Thereafter, if the command stored in the command storage buffer 126 in step S4710 is a post-conversion start command (step S4712: YES), the start reception flag in the production-side RAM 94 is set to "1" (step S4713). This allows the production-side MPU 92 to recognize that a start command has been received. On the other hand, if the command stored in the command storage buffer 126 in step S4710 is not a post-conversion start command (step S4712: NO), that is, if the command stored in the command storage buffer 126 in step S4710 is a post-conversion end command, the end reception flag in the production-side RAM 94 is set to "1" (step S4714). This allows the production-side MPU 92 to recognize that an end command has been received. If step S4713 or step S4714 is performed, the first to eleventh areas RC1 to RC11 of the top-level setting area 134 are cleared to "0" (step S4715), and this command reception response process ends.

If a negative determination is made in step S4706, steps S4716 to S4723 execute the same processing as steps S3017 to S3024 of the command reception response processing (FIG. 52) in the first embodiment described above. Specifically, if header HD data indicating a winning result command is stored in the post-reception standby buffer 122 (step S4716: YES), the value of the second write pointer 129 in the presentation-side RAM 94 is determined to determine the write destination area in the command storage buffer 126 (step S4717), and the winning result command stored in the post-reception standby buffer 122 is set to the write destination area determined in step S4717 (step S4718). This allows the winning result command to be stored in the command storage buffer 126 and made available to the presentation-side MPU 92.

Then, the value of the second write pointer 129 is updated (step S4719). In step S4719, "5", which is the data capacity of the winning result command written to the command storage buffer 126 in step S4718, is added to the value of the second write pointer 129. In step S4719, if the result of the operation to add "5" exceeds the maximum value of "63", the second write pointer 129 is set to a value "64" smaller than the result of the operation. For example, if the result of the operation to add "5" is "64", which exceeds the maximum value of "63", the second write pointer 129 is set to "0", which is "64" smaller than the result of the operation ("64").

Then, a process for clearing the post-reception standby buffer 122 is executed (step S4720). In the process of clearing the post-reception standby buffer 122 in step S4720, the area in the post-reception standby buffer 122 where the winning result command was stored is cleared to "0". This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. The value of the read pointer 128 in the post-reception standby buffer 122 is then updated to a value corresponding to the area following the area where the end of the winning result command (footer FT data) was stored (step S4721), the winning result reception flag in the presentation-side RAM 94 is set to "1" (step S4722), and this command reception response process is terminated. By setting the winning result reception flag to "1" in step S4722, the process from step S3402 onwards is executed in the winning result reception response process (Figure 56).

If a negative determination is made in step S4716, processing for receiving other commands is executed (step S4723), and this command reception processing ends. In the processing for receiving other commands in step S4723, the value of the second write pointer 129 in the production-side RAM 94 is first determined to determine the write destination area in the command storage buffer 126, and the command determined in step S4703 as the command to be moved (e.g., a power recovery command) is set in the determined write destination area. Thereafter, as in steps S4711 and S4719, the value of the second write pointer 129 is updated. Then, the area in the post-reception standby buffer 122 where the command to be moved was stored is cleared to "0." This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. Then, the value of the read pointer 128 in the post-reception standby buffer 122 is updated to a value corresponding to the area following the area where the end of the command to be moved (footer FT data) was stored.

The present embodiment described above provides the following excellent effects:

The common data table 73f has a first set range and a second set range set, as well as a first exclusion range and a second exclusion range set. Data stored in a memory area determined based on the addresses set in the first set range and the second set range is set as the start command, while data stored in a memory area determined based on the addresses set in the first exclusion range and the second exclusion range is not set. This allows only the data required by the production side MPU 92 at the start of the game to be set as the start command.

By configuring the start command so that only the data required by the production side MPU 92 at the start of the game is set, the data volume of the start command sent from the main side MPU 72 to the production side MPU 92 can be reduced. Furthermore, when the production side MPU 92 receives a start command, it is no longer necessary to extract only the data required by the production side MPU 92 at the start of the game from the data set in the start command. This reduces the processing load on the production side MPU 92 when it receives a start command.

The common data table 73f has a third set range and a fourth set range set, as well as a third excluded range and a fourth excluded range set. Data stored in a memory area determined based on the addresses set in the third set range and the fourth set range is set as the end command, while data stored in a memory area determined based on the addresses set in the third excluded range and the fourth excluded range is not set. This allows only the data required by the production side MPU 92 at the end of the game to be set as the end command.

By configuring the end command so that only the data required by the production side MPU 92 at the end of the game is set, the data volume of the end command sent from the main MPU 72 to the production side MPU 92 can be reduced. Furthermore, when the production side MPU 92 receives the end command, it is no longer necessary to extract only the data required by the production side MPU 92 at the end of the game from the data set in the end command. This reduces the processing load on the production side MPU 92 when it receives the end command.

In the main RAM 74, the memory areas in which the most significant bit of data is set in the top-level aggregation area 74v include the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the number of continued games counter 74r, and the lower and upper areas of the total number of wins counter 74s. Of these six memory areas, the memory areas in which data is set for the start command are the lower and upper areas of the AT continuation counter 74u, and the memory areas in which data is set for the end command are the lower and upper areas of the number of continued games counter 74r and the lower and upper areas of the total number of wins counter 74s. Thus, in a configuration in which the memory area in which data is set for the start command and the memory area in which data is set for the end command are different among the six memory areas in which the most significant bit of data is aggregated in the top-level aggregation area 74v, a process of aggregating the most significant bit of data from these six memory areas into the top-level aggregation area 74v (the top-level aggregation process of step S4602) is executed whether a start command or an end command is sent. Therefore, compared to a configuration in which, when a start command is sent, processing is performed to set the most significant bit of data in the top-level aggregation area 74v for only those storage areas of the six storage areas for which data is set in the start command, and, when an end command is sent, processing is performed to set the most significant bit of data in the top-level aggregation area 74v for only those storage areas of the six storage areas for which data is set in the end command, the processing configuration for setting the most significant bit of data in the top-level aggregation area 74v can be simplified.

When sending a start command or an end command, first the data of the most significant bit in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game count counter 74r, and the lower and upper areas of the total winning count counter 74s is set to bits 0 to 5 of the most significant aggregation area 74v (top-level aggregation process in step S4602), and then, if a start command is being sent, the data required by the production side MPU 92 at the start of the game is set in the transmission standby buffer 112, and if an end command is being sent, the data required by the production side MPU 92 at the end of the game is set in the transmission standby buffer 112. In a configuration in which only a portion of the memory area in the main RAM 74 where data is set for start commands is shared with the memory area where data is set for end commands, the process of setting the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continued game count counter 74r, and the lower and upper areas of the total win count counter 74s to bits 0 through 5 of the top-level aggregation area 74v (top-level aggregation process in step S4602) is executed using the same subroutine program. This reduces the data capacity of the program stored in the main ROM 73 for executing this process.

The data stored in the lower and upper areas of the AT continuation counter 74u is set in the second to third consecutive frames FR2 to FR3 in the start command. Therefore, by repeatedly incrementing the value of the presentation-side transfer destination counter (step S4813), the transfer destination memory area where the data aggregated in the top aggregated frame SF is set can be sequentially updated. This simplifies the processing configuration for the presentation-side MPU 92 to set the data aggregated in bits 0 to 1 in the top aggregated frame SF of the start command to the most significant bit of the second to third frames FR2 to FR3 corresponding to those bits 0 to 1. Furthermore, the data stored in the lower and upper areas of the continued game counter 74r and the lower and upper areas of the total win counter 74s are set in the second to fifth consecutive frames FR2 to FR5 in the end command. Therefore, by repeatedly incrementing the value of the production-side transfer destination counter by 1 (step S4813), the transfer destination memory area where the data aggregated in the highest aggregated frame SF is set can be sequentially updated. This simplifies the processing structure for the production-side MPU 92 to set the data aggregated in the second through fifth bits of the highest aggregated frame SF of the termination command to the highest bits of the second through fifth frames FR2 through FR5 that correspond to those second through fifth bits.

Sixth Embodiment
In this embodiment, the configuration of the common data table 73g that is referenced when sending start commands and end commands differs from that of the fifth embodiment. The following describes the configuration that differs from the fifth embodiment. Note that a description of the configuration that is the same as that of the fifth embodiment will basically be omitted.

The common data table 73g is stored in the main ROM 73. Figure 84(a) is an explanatory diagram illustrating the configuration of the common data table 73g. As shown in Figure 84(a), the common data table 73g is set in the consecutive address range of "9101H" to "911AH" in the main ROM 73.

In the common data table 73g, an eleventh setting range is set in the consecutive address range of "9101H" to "910CH," and a twelfth setting range is set in the consecutive address range of "9109H" to "911AH." The eleventh setting range contains the addresses of multiple (specifically, six) memory areas in which data is set for start commands among the many one-byte memory areas provided in the main RAM 74, and the twelfth setting range contains the addresses of multiple (specifically, nine) memory areas in which data is set for end commands among the many one-byte memory areas provided in the main RAM 74.

As in the first embodiment, the memory areas in the main RAM 74 where data is set for the start command are the lower and upper areas of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, the game status area 77, and the top-level aggregation area 74v, and addresses for identifying these six memory areas are set in the 11th setting range. Hereinafter, these six memory areas are also referred to as "memory areas of the main RAM 74 included in the 11th setting range."

As in the first embodiment, the memory areas in the main RAM 74 where data is set for the end command are the game status area 77, the top-level aggregation area 74v, the lower and upper areas of the continued game count counter 74r, the lower and upper areas of the total win count counter 74s, the game interval area 76, the pseudo bonus continuation counter 74t, and the award count counter 74e, and addresses for identifying these nine memory areas are set in the 12th setting range. Hereinafter, these nine memory areas are also referred to as "memory areas of the main RAM 74 included in the 12th setting range."

Of the six memory areas in the main RAM 74 where data is set for start commands, the game status area 77 and the top-level aggregation area 74v are also memory areas where data is set for end commands. In this way, in the main RAM 74, only some of the multiple memory areas where data is set for start commands overlap with the multiple memory areas where data is set for end commands.

As already explained in the first embodiment above, the lower area of the AT continuation counter 74u, the lower area of the number of continued games counter 74r, and the lower area of the total number of wins counter 74s are storage areas in which a "1" can be set in the most significant bit (the seventh bit of the 0th to 7th bits). As shown in FIG. 84(a), a first aggregation range is set in the consecutive address range of "9101H" to "9104H" in the 11th setting range of the common data table 73g. The first aggregation range includes the addresses of the lower and upper areas of the AT continuation counter 74u, among the six storage areas in which data is set in the start command in the main RAM 74, where the data stored in the most significant bit is aggregated in the most significant aggregation area 74v. The most significant bit data in the lower area of the AT continuation counter 74u is set to the 0th bit of the most significant aggregation area 74v, and the most significant bit data in the upper area of the AT continuation counter 74u is set to the 1st bit of the most significant aggregation area 74v. Hereinafter, the lower and upper areas of the AT continuation counter 74u identified based on the address of the main RAM 74 set in the first aggregation range will also be referred to as "storage areas of the main RAM 74 included in the first aggregation range."

A second aggregation range is set in the consecutive address range "910DH" to "9114H" in the 12th setting range of the common data table 73g. The second aggregation range includes the addresses of the lower and upper areas of the continued games counter 74r and the lower and upper areas of the total wins counter 74s, among the nine memory areas in the main RAM 74 where data is set in the termination command. The data stored in the most significant bit in the lower area of the continued games counter 74r is set to the 0th bit of the most significant aggregation area 74v, and the data in the most significant bit in the upper area of the continued games counter 74r is set to the 1st bit of the most significant aggregation area 74v. Furthermore, the data in the most significant bit in the lower area of the total wins counter 74s is set to the 2nd bit of the most significant aggregation area 74v, and the data in the most significant bit in the upper area of the total wins counter 74s is set to the 3rd bit of the most significant aggregation area 74v. Hereinafter, the lower and upper areas of the continued game counter 74r and the lower and upper areas of the total win counter 74s identified based on the address of the main RAM 74 set in the second aggregation range will also be referred to as "storage areas of the main RAM 74 included in the second aggregation range."

Figure 84(b) is an explanatory diagram illustrating the data structure of a start command, and Figure 84(c) is an explanatory diagram illustrating the data structure of an end command. As shown in Figure 84(b), the start command contains data for the lower area of the AT continuation counter 74u, the upper area of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, the game status area 77, and the top-level aggregation area 74v, which are determined based on the addresses set in the 11th setting range ("9101H" to "910CH"). This data is required by the presentation-side MPU 92 at the start of the game. By configuring the start command in this way so that only the data required by the presentation-side MPU 92 at the start of the game is set, the data volume of the start command transmitted from the main-side MPU 72 to the presentation-side MPU 92 can be reduced. Furthermore, this eliminates the need for the presentation-side MPU 92, upon receiving the start command, to extract only the data required by the presentation-side MPU 92 at the start of the game from the data set in the start command. This reduces the processing load on the production side MPU 92 when a start command is received.

As shown in FIG. 84(c), the end command contains data for the game status area 77, the top-level aggregation area 74v, the lower area of the continued game counter 74r, the upper area of the continued game counter 74r, the lower area of the total win counter 74s, the upper area of the total win counter 74s, the game section area 76, the pseudo bonus continuation counter 74t, and the awarded number counter 74e, which are determined based on the addresses set in the 12th setting range ("9109H" to "911AH"). This data is required by the presentation MPU 92 at the end of the game. By configuring the end command in this way so that only the data required by the presentation MPU 92 at the end of the game is set, the data volume of the end command transmitted from the main MPU 72 to the presentation MPU 92 can be reduced. Furthermore, the presentation MPU 92 that receives the end command does not need to extract only the data required by the presentation MPU 92 at the end of the game from the data set in the end command. This reduces the processing load on the production side MPU 92 when an end command is received.

As with the fifth embodiment above, the start command consists of eight frames (first to eighth frames FR1 to FR8). The production-side MPU 92 sets the first to eighth frames FR1 to FR8 of the received start command to the first to eighth areas RC1 to RC8 of the top setting area 134 in the production-side RAM 94. As shown in Figure 84 (b), the second frame FR2 in which the data of the lower area of the AT continuation counter 74u in the main RAM 74 is set is set to the second area RC2, the third frame FR3 in which the data of the upper area of the AT continuation counter 74u is set is set to the third area RC3, and the top-level aggregation frame SF (seventh frame FR7) in which the data of the top-level aggregation area 74v is set is set to the seventh area RC7. As described above, the data stored in the most significant bit of the lower area of the AT duration counter 74u in the main RAM 74 is set to bit 0 of the highest aggregated frame SF, and the data stored in the most significant bit of the upper area of the AT duration counter 74u is set to bit 1 of the highest aggregated frame SF. The production side MPU 92 generates a post-conversion start command by setting the data in bit 0 of the seventh area RC7 to the most significant bit of the second area RC2 and setting the data in bit 1 of the seventh area RC7 to the most significant bit of the third area RC3. The production side MPU 92 then stores the generated post-conversion start command in the command storage buffer 126. This makes the post-conversion start command available to the production side MPU 92.

As in the fifth embodiment above, the end command consists of 11 frames (first to eleventh frames FR1 to FR11). The production-side MPU 92 sets the first to eleventh frames FR1 to FR11 of the received end command to the first to eleventh areas RC1 to RC11 of the top-level setting area 134. As shown in Figure 84 (c), the top aggregation frame SF (third frame FR3) in which the data of the top aggregation area 74v in the main RAM 74 is set is set to the third area RC3, the fourth frame FR4 in which the data of the lower area of the continued game number counter 74r is set is set to the fourth area RC4, the fifth frame FR5 in which the data of the upper area of the continued game number counter 74r is set is set to the fifth area RC5, the sixth frame FR6 in which the data of the lower area of the total winning number counter 74s is set is set to the sixth area RC6, and the seventh frame FR7 in which the data of the upper area of the total winning number counter 74s is set is set to the seventh area RC7. As described above, the data stored in the most significant bit of the lower area of the continued game counter 74r is set to bit 0 of the highest aggregated frame SF, the data stored in the most significant bit of the upper area of the continued game counter 74r is set to bit 1 of the highest aggregated frame SF, the data stored in the most significant bit of the lower area of the total wins counter 74s is set to bit 2 of the highest aggregated frame SF, and the data stored in the most significant bit of the upper area of the total wins counter 74s is set to bit 3 of the highest aggregated frame SF. The production-side MPU 92 generates a post-conversion end command by setting the data of bit 0 in the third area RC3 to the most significant bit of the fourth area RC4, setting the data of bit 1 in the third area RC3 to the most significant bit of the fifth area RC5, setting the data of bit 2 in the third area RC3 to the most significant bit of the sixth area RC6, and setting the data of bit 3 in the third area RC3 to the most significant bit of the seventh area RC7. The generated post-conversion end command is then stored in the command storage buffer 126. This allows the production-side MPU 92 to make the post-conversion end command available for use.

Figure 85 is an explanatory diagram illustrating the configuration of the main RAM 74. The main RAM 74 is provided with a transfer destination counter 115, a bit designation counter 117, and a transfer source address counter 132, as in the fifth embodiment, and also with a transfer count counter 114, as in the first embodiment. As already explained in the first embodiment, the transfer count counter 114 is a one-byte counter that enables the main MPU 72 to grasp the number of times data stored in a memory area included in the transfer target range in the common command transmission process is transferred to the transmission standby buffer 112, and the number of times data stored in the most significant bit of a memory area included in the transfer target range in the most significant aggregation process is transferred to the most significant aggregation area 74v.

In this embodiment, when a start command is sent, the transfer target range in the common command sending process is the 11th set range, and the transfer target range in the top-level consolidation process is the first consolidation range. Furthermore, when an end command is sent, the transfer target range in the common command sending process is the 12th set range, and the transfer target range in the top-level consolidation process is the second consolidation range.

Next, the common command transmission process executed by the main MPU 72 will be described with reference to the flowchart in Figure 86. As already explained in the first embodiment above, the common command transmission process is executed in step S2709 when the start command flag in the main RAM 74 is set to "1" in the command output process (Figure 44) (step S2707: YES) or when the end command flag in the main RAM 74 is set to "1" (step S2708: YES).

The common command transmission process first reads the common data table 73g stored in the main ROM 73 (step S4901), and then executes the top-level aggregation process (step S4902). Figure 87 is a flowchart showing the top-level aggregation process.

In the top-level aggregation process, steps S5001 to S5003 are performed in the same manner as steps S4501 to S4503 in the top-level aggregation process (Figure 78) in the fourth embodiment. Specifically, the address of the top-level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 of the main RAM 74 (step S5001). This allows the top-level aggregation area 74v to be set as the transfer destination storage area. The top-level aggregation area 74v is then cleared to "0" (step S5002), and the value of the bit designation counter 117 in the main RAM 74 is cleared to "0" (step S5003). This allows the 0th bit of the top-level aggregation area 74v to be set as the transfer destination bit.

After that, if the start command flag in the main RAM 74 is set to "1" (step S5004: YES), i.e., if a start command is to be sent, "9101H," the start address of the first aggregation range ("9101H" to "9104H"), is set in the transfer source address counter 132 (step S5005). This makes it possible to grasp the lower area of the AT continuation counter 74u as the transfer source memory area based on the addresses set in the address range of "9101H" to "9102H" in the common data table 73g. Then, "2," the number of memory areas in the main RAM 74 included in the first aggregation range, is set as the number of transfers in the transfer count counter 114 of the main RAM 74 (step S5006).

On the other hand, if the start command flag in the main RAM 74 is not set to "1" (step S5004: NO), i.e., if an end command is to be sent, "910DH," the start address of the second aggregation range ("910DH" to "9114H"), is set in the transfer source address counter 132 (step S5007). This makes it possible to identify the lower area of the continued game count counter 74r as the transfer source memory area based on the addresses set in the address range of "910DH" to "910EH" in the common data table 73g. Then, "4," the number of memory areas in the main RAM 74 included in the second aggregation range, is set in the transfer count counter 114 as the number of transfers (step S5008).

After performing step S5006 or step S5008, the most significant bit of data in the source storage area is transferred to the destination bit (step S5009), similar to step S4506 in the top-level aggregation process (Figure 78) in the fourth embodiment. In step S5009, the address of the source storage area in the main RAM 74 is identified based on the data in the storage area corresponding to the address set in the source address counter 132 in the common data table 73g, and the destination bit is identified based on the data in the destination counter 115 and the value of the bit designation counter 117. Then, the value of the transfer count counter 114 is decremented by 1 (step S5010), and it is determined whether the value of the transfer count counter 114 after the decrement is "0" (step S5011).

If a negative determination is made in step S5011, the source storage area is updated by incrementing the value of the source address counter 132 by 2 (step S5012). Steps S5009 to S5013 are repeated until a positive determination is made in step S5011. In step S5012, when a start command is sent, the addresses stored in the source address counter 132 are updated in the order of "9101H" → "9103H", and when an end command is sent, the addresses stored in the source address counter 132 are updated in the order of "910DH" → "910FH" → "9111H" → "9113H".

Then, the value of the bit designation counter 117 is incremented by 1 to update the destination bit in the top-level aggregation area 74v (step S5013). In step S5013, when a start command is sent, the destination bit in the top-level aggregation area 74v is updated in the order of bit 0 → bit 1, and when an end command is sent, the destination bit in the top-level aggregation area 74v is updated in the order of bit 0 → bit 1 → bit 2 → bit 3.

Then, proceed to step S5009, and repeat steps S5009 to S5013 until a positive determination is made in step S5011. As a result, when a start command is sent, the data stored in the most significant bit of the memory area of the main RAM 74 included in the first aggregation range can be set to bits 0 to 1 of the top-level aggregation area 74v, and when an end command is sent, the data stored in the most significant bit of the memory area of the main RAM 74 included in the second aggregation range can be set to bits 0 to 3 of the top-level aggregation area 74v. If a positive determination is made in step S5011, this top-level aggregation process is terminated.

As described above, in the common data table 73g, the first aggregation range is set to the consecutive address range of "9101H" to "9104H." Therefore, the source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source address counter 132 by 2 (processing of step S5012). Furthermore, the second aggregation range is set to the consecutive address range of "910DH" to "9114H." Therefore, the source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source address counter 132 by 2 (processing of step S5012). This simplifies the processing configuration for sequentially updating the source memory area.

Because the first aggregation range is a contiguous address range, the first aggregation range can be specified by setting the start address of the first aggregation range ("9101H") in the transfer source address counter 132 in step S5005 and setting the number of storage areas in the main RAM 74 included in the first aggregation range ("2") in the transfer count counter 114 in step S5006. This simplifies the processing configuration for specifying the first aggregation range. Because the second aggregation range is a contiguous address range, the start address of the second aggregation range ("910DH") in the transfer source address counter 132 in step S5007 and setting the number of storage areas in the main RAM 74 included in the second aggregation range ("4") in the transfer count counter 114 in step S5008 can be specified. This simplifies the processing configuration for specifying the second aggregation range.

Commands that aggregate data stored in the most significant bits include start commands and end commands, which aggregate data stored in the most significant bits in a different storage area of the main RAM 74 than the start commands. By varying the start address and transfer count information for the transfer range (first aggregation range or second aggregation range) in the top-level aggregation process depending on the type of command being sent, a common top-level aggregation process can be used to aggregate data stored in the most significant bits of the storage area of the main RAM 74 included in the first aggregation range in the top-level aggregation area 74v when a start command is sent, and aggregate data stored in the most significant bits of the storage area of the main RAM 74 included in the second aggregation range in the top-level aggregation area 74v when an end command is sent. Therefore, compared to a configuration in which a process for aggregating data stored in the most significant bits when an end command is sent is provided as a separate process from a process for aggregating data stored in the most significant bits when a start command is sent, the data volume of the program stored in the main ROM 73 for executing the process for aggregating data stored in the most significant bits can be reduced.

Returning to the explanation of the common command transmission process (FIG. 86), after executing the top-level aggregation process in step S4902, steps S4903 to S4905 are performed similarly to steps S4603 to S4605 of the common command transmission process (FIG. 81) in the fifth embodiment. Specifically, the value of the write pointer 113 in the transmission circuit 85 is determined to determine the write destination area in the transmission standby buffer 112 (step S4903). Thereafter, if the start command flag in the main RAM 74 is set to "1" (step S4904: YES), i.e., if a start command is to be sent, the header HD data stored in the main ROM 73 indicating that this is a start command is set to the write destination area determined in step S4903 (step S4905). Thereafter, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4906). In step S4906, and steps S4911, S4917, and S4922 described below, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after incrementing by 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

Then, "9101H," the start address of the eleventh setting range ("9101H" to "910CH"), is set in the transfer source address counter 132 of the main RAM 74 (step S4907). This makes it possible to grasp the lower area of the AT continuation counter 74u as the transfer source memory area based on the addresses set in the address range of "9101H" to "9102H" in the common data table 73g. Then, "6," the number of memory areas in the main RAM 74 included in the eleventh setting range, is set in the transfer count counter 114 as the number of transfers (step S4908), and the start command flag is cleared to "0" (step S4909).

On the other hand, if the start command flag is not set to "1" (step S4904: NO), i.e., if an end command is to be sent, the header HD data stored in the main ROM 73 indicating that it is an end command is set to the write destination area identified in step S4903 (step S4910). Then, as in step S4906 described above, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4911).

Then, "9109H," the start address of the twelfth setting range ("9109H" to "911AH"), is set in the transfer source address counter 132 of the main RAM 74 (step S4912). This makes it possible to identify the game status area 77 as the transfer source memory area based on the addresses set in the address range of "9109H" to "910AH" in the common data table 73g. Then, "9," the number of memory areas in the main RAM 74 included in the twelfth setting range, is set in the transfer count counter 114 as the number of transfers (step S4913), and the end command flag is cleared to "0" (step S4914).

After performing step S4909 or step S4914, steps S4915 through S4917 are similar to steps S4610 through S4612 of the common command transmission process (FIG. 81) in the fifth embodiment. Specifically, data from the source memory area is transferred to the destination area in the transmission standby buffer 112 (step S4915). In step S4915, the address of the source memory area in the main RAM 74 is identified based on the data in the memory area corresponding to the address set in the source address counter 132 in the common data table 73g. Then, the most significant bit (the seventh bit) of the destination area is set to "0" (step S4916). This allows the most significant bit of the second through seventh frames FR2 through FR7 of the start command to be set to "0" when transmitting the start command, and also makes it possible to distinguish the header HD from the second through seventh frames FR2 through FR7 based on the value of the most significant bit. Furthermore, when an end command is sent, the most significant bit of the second to tenth frames FR2 to FR10 of the end command can be set to "0," and the header HD can be distinguished from the second to tenth frames FR2 to FR10 based on the value of the most significant bit.

Then, similar to steps S4906 and S4911 described above, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4917). Then, the value of the transfer count counter 114 is decremented by 1 (step S4918), and it is determined whether the value of the transfer count counter 114 after the decrement is "0" (step S4919).

If a negative determination is made in step S4919, the source storage area is updated by incrementing the value of the source address counter 132 by 2 (step S4920). Steps S4915 to S4920 are repeated until a positive determination is made in step S4919. In step S4920, when a start command is sent, the addresses stored in the source address counter 132 are updated in the order "9101H" → "9103H" → ... → "9109H" → "910BH", and when an end command is sent, the addresses stored in the source address counter 132 are updated in the order "9109H" → "910BH" → ... → "9117H" → "9119H".

Then, proceed to step S4915, and repeat steps S4915 to S4919 until a positive determination is made in step S4919. As a result, when sending a start command, data stored in the memory area of the main RAM 74 included in the 11th setting range can be set in the transmission standby buffer 112, and when sending an end command, data stored in the memory area of the main RAM 74 included in the 12th setting range can be set in the transmission standby buffer 112.

After a positive determination is made in step S4919, steps S4921 and S4922 execute the same processing as steps S4623 and S4624 of the common command transmission process (FIG. 81) in the fifth embodiment. Specifically, the footer FT data stored in the main ROM 73 is set in the write destination area in the transmission standby buffer 112 corresponding to the value of the write pointer 113 (step S4921). Thereafter, as in steps S4906, S4911, and S4917 described above, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4922), and the common command transmission process terminates.

As described above, in a configuration in which only some of the multiple storage areas in the main RAM 74 where data is set for the start command overlap with the multiple storage areas where data is set for the end command, the 11th setting range in the common data table 73g is set to the consecutive address range of "9101H" to "910CH." Therefore, the source storage area can be sequentially updated by repeatedly executing the process of incrementing the value of the source address counter 132 by 2 (step S4920). This simplifies the processing configuration for transferring data stored in the storage areas of the main RAM 74 included in the 11th setting range to the transmission standby buffer 112. Furthermore, the 12th setting range in the common data table 73g is set to the consecutive address range of "9109H" to "911AH." Therefore, the source storage area can be sequentially updated by repeatedly executing the process of incrementing the value of the source address counter 132 by 2 (step S4920). This simplifies the processing configuration for transferring data stored in the storage area of the main RAM 74 included in the 12th setting range to the transmission standby buffer 112.

The main MPU 72 uses the common data table 73g to identify the storage area in the main RAM 74 where data is set for the start command, and to identify the storage area in the main RAM 74 where data is set for the end command. Therefore, compared to a configuration in which the main ROM 73 stores a data table referenced to identify the storage area in the main RAM 74 where data is set for the end command as a separate data table from the data table referenced to identify the storage area in the main RAM 74 where data is set for the start command, the data capacity of the data tables used to identify the storage area in the main RAM 74 where data is set for the start command and the storage area in the main RAM 74 where data is set for the end command can be reduced. This reduces the data capacity of the main ROM 73 for storing these data tables.

Because the 11th setting range is a contiguous address range, the starting address of the 11th setting range ("9101H") is set in the transfer source address counter 132 in step S4908, and the number of storage areas in the main RAM 74 included in the 11th setting range ("6") is set in the transfer count counter 114 in step S4909, thereby specifying the 11th setting range. This simplifies the processing configuration for specifying the 11th setting range. Because the 12th setting range is a contiguous address range, the starting address of the 12th setting range ("9109H") is set in the transfer source address counter 132 in step S4912, and the number of storage areas in the main RAM 74 included in the 12th setting range ("9") is set in the transfer count counter 114 in step S4913, thereby specifying the 12th setting range. This simplifies the processing configuration for specifying the 12th setting range.

By varying the start address and transfer count information for the transfer range (11th set range or 12th set range) in the common command transmission process depending on the type of command to be transmitted, the common common command transmission process can be used to set data stored in the memory area of the main RAM 74 included in the 11th set range in the transmission standby buffer 112 when transmitting a start command, and to set data stored in the memory area of the main RAM 74 included in the 12th set range in the transmission standby buffer 112 when transmitting an end command. Therefore, compared to a configuration in which a process is provided in which data from the main RAM 74 is transferred to the transmission standby buffer 112 when transmitting an end command as a separate process from the process in which data from the main RAM 74 is transferred to the transmission standby buffer 112 when transmitting a start command, the data volume of the program stored in the main ROM 73 for executing the process of transferring data from the main RAM 74 to the transmission standby buffer 112 can be reduced.

Next, the highest-level setting process executed by the production-side MPU 92 will be explained with reference to the flowchart in Figure 88. As already explained in the fifth embodiment above, the highest-level setting process is executed in step S4708 of the command reception response process (Figure 82).

In the top-level setting process, steps S5101 to S5103 are executed in the same manner as steps S4801 to S4803 in the top-level setting process (Figure 83) in the fifth embodiment. Specifically, first, the start command or end command stored in the post-reception standby buffer 122 is set in the top-level setting area 134 of the production-side RAM 94 (step S5101). In step S5101, if a start command is stored in the post-reception standby buffer 122, the first to eighth frames FR1 to FR8 of the start command are set in the first to eighth areas RC1 to RC8 of the top-level setting area 134. Also, if an end command is stored in the post-reception standby buffer 122, the first to eleventh frames FR1 to FR11 of the end command are set in the first to eleventh areas RC1 to RC11 of the top-level setting area 134.

Then, a clearing process is executed on the post-reception standby buffer 122 (step S5102). In this clearing process, the area in the post-reception standby buffer 122 where the start command or end command was stored is cleared to "0". This ensures that free space is available in the post-reception standby buffer 122 for storing the next command. Then, the value of the read pointer 128 in the post-reception standby buffer 122 is updated to a value corresponding to the storage area next to the storage area where the end of the start command or end command (footer FT data) was stored (step S5103).

Then, the value of the presentation-side bit designation counter in the presentation-side RAM 94 is cleared to "0" (step S5104). As already explained in the first embodiment above, the presentation-side bit designation counter is a counter that allows the presentation-side MPU 92 to grasp the source bit in the source memory area.

If the command set in the top-level setting area 134 in step S5101 is a start command (step S5105: YES), the address of the seventh area RC7 in the top-level setting area 134 is set in the production-side transfer source counter in the production-side RAM 94 (step S5106). As already explained, the seventh area RC7 is the area in which the top-level aggregate frame SF of the start command is set. As already explained in the first embodiment above, the production-side transfer source counter is a counter that allows the production-side MPU 92 to determine the source memory area of data transfer. By setting the address of the seventh area RC7 in the production-side transfer source counter in step S5106, the seventh area RC7 can be set as the source memory area. As mentioned above, because the value of the production-side bit designation counter was cleared to "0" in step S5104, the 0th bit in the seventh area RC7 can be set as the source bit.

Then, the address of the second area RC2 in the top setting area 134 is set in the director's transfer destination counter in the director's RAM 94 (step S5107). As already explained in the first embodiment above, the director's transfer destination counter is a counter that allows the director's MPU 92 to grasp the destination storage area. By setting the address of the second area RC2 in the director's transfer destination counter in step S5107, the second area RC2 can be used as the destination storage area.

On the other hand, if the command set in the top-level setting area 134 in step S5101 is not a start command but an end command (step S5105: NO), the address of the third area RC3 in the top-level setting area 134 is set to the production-side transfer source counter in the production-side RAM 94 (step S5108). As already explained, the third area RC3 is the area where the top-level aggregate frame SF of the start command is set. By setting the address of the third area RC3 in the production-side transfer source counter in step S5108, the third area RC3 can be set as the transfer source memory area. As mentioned above, because the value of the production-side bit designation counter was cleared to "0" in step S5104, the 0th bit in the third area RC3 can be set as the transfer source bit. Then, the address of the fourth area RC4 in the top-level setting area 134 is set to the production-side transfer destination counter in the production-side RAM 94 (step S5109). This allows the fourth area RC4 to be used as the transfer destination memory area.

After processing step S5107 or step S5109, the data "0" or "1" stored in the source bit is set to the most significant bit in the destination memory area (step S5110), similar to step S4810 of the highest-level setting process (FIG. 83) in the fifth embodiment. Then, based on the value of the production-side bit designation counter, it is determined whether the process of setting the data aggregated in the highest-level aggregated frame SF to the most significant bit of the corresponding frame has been completed (step S5111). In step S5111, if the command set in the highest-level setting area 134 is a start command, a positive determination is made if the value of the production-side bit designation counter is "1," and if the command set in the highest-level setting area 134 is an end command, a positive determination is made if the value of the production-side bit designation counter is "3."

If a negative judgment is made in step S5111, the value of the production-side bit designation counter is incremented by 1, thereby updating the source bit in the area (seventh area RC7 or third area RC3) in which the highest aggregated frame SF is set in the highest setting area 134 (step S5112). The processes of steps S5110 to S5113 are repeatedly executed until a positive judgment is made in step S5111. In step S5112, if a start command is set in the highest setting area 134, the source bit in the seventh area RC7 is updated in the order of bit 0 → bit 1, and if an end command is set in the highest setting area 134, the source bit in the third area RC3 is updated in the order of bit 0 → bit 1 → bit 2 → bit 3.

Then, the value of the director's transfer destination counter is incremented by 1 to update the transfer destination memory area (step S5113). As a result, if a start command is set in the top-level setting area 134, the transfer destination memory areas in the top-level setting area 134 are updated in the order of second area RC2 → third area RC3, and if an end command is set in the top-level setting area 134, the transfer destination areas in the top-level setting area 134 are updated in the order of fourth area RC4 → fifth area RC5 → sixth area RC6 → seventh area RC7.

After processing step S5113, proceed to step S5110, and repeat steps S5110 through S5113 until a positive determination is made in step S5111. As a result, if a start command is set in the top-level setting area 134, the data aggregated in bits 0 through 1 of the top-level aggregated frame SF can be set to the most significant bits of the second through third frames FR2 through FR3 corresponding to those bits. Also, if an end command is set in the top-level setting area 134, the data aggregated in bits 0 through 3 of the top-level aggregated frame SF can be set to the most significant bits of the fourth through seventh frames FR4 through FR7 corresponding to those bits. If a positive determination is made in step S5111, this top-level setting process ends.

As described above, the data stored in the lower and upper areas of the AT continuation counter 74u is set in the consecutive second and third frames FR2-FR3 in the start command. Therefore, by repeatedly incrementing the value of the presentation-side transfer destination counter (step S5113), the transfer destination memory area where the data aggregated in the top aggregated frame SF is set can be sequentially updated. This simplifies the processing configuration for the presentation-side MPU 92 to set the data aggregated in bits 0-1 in the top aggregated frame SF of the start command to the most significant bit of the second and third frames FR2-FR3 corresponding to those bits 0-1. Furthermore, the data stored in the lower and upper areas of the continued game counter 74r and the lower and upper areas of the total win counter 74s are set in the consecutive fourth to seventh frames FR4-FR7 in the end command. Therefore, by repeatedly incrementing the value of the production-side transfer destination counter by 1 (step S5113), the transfer destination memory area where the data aggregated in the highest aggregated frame SF is set can be sequentially updated. This simplifies the processing structure for the production-side MPU 92 to set the data aggregated in bits 0 to 3 in the highest aggregated frame SF of the termination command to the highest bits of the fourth to seventh frames FR4 to FR7 corresponding to those bits 0 to 3.

The present embodiment described above provides the following excellent effects:

In a configuration in which only some of the multiple storage areas in the main RAM 74 where data is set for the start command overlap with the multiple storage areas where data is set for the end command, the 11th setting range in the common data table 73g is set to the consecutive address range of "9101H" to "910CH." Therefore, the source storage areas can be sequentially updated by repeatedly incrementing the value of the source address counter 132 by 2 (step S4920). This simplifies the processing configuration for transferring data stored in the storage areas of the main RAM 74 included in the 11th setting range to the transmission standby buffer 112. Furthermore, the 12th setting range in the common data table 73g is set to the consecutive address range of "9109H" to "911AH." Therefore, the source storage areas can be sequentially updated by repeatedly incrementing the value of the source address counter 132 by 2 (step S4920). This simplifies the processing configuration for transferring data stored in the storage area of the main RAM 74 included in the 12th setting range to the transmission standby buffer 112.

The main MPU 72 uses the common data table 73g to identify the storage area in the main RAM 74 where data is set for the start command, and to identify the storage area in the main RAM 74 where data is set for the end command. Therefore, compared to a configuration in which the main ROM 73 stores a data table referenced to identify the storage area in the main RAM 74 where data is set for the end command as a separate data table from the data table referenced to identify the storage area in the main RAM 74 where data is set for the start command, the data capacity of the data tables used to identify the storage area in the main RAM 74 where data is set for the start command and the storage area in the main RAM 74 where data is set for the end command can be reduced. This reduces the data capacity of the main ROM 73 for storing these data tables.

Because the 11th setting range is a contiguous address range, the starting address of the 11th setting range ("9101H") is set in the transfer source address counter 132 in step S4908, and the number of storage areas in the main RAM 74 included in the 11th setting range ("6") is set in the transfer count counter 114 in step S4909, thereby specifying the 11th setting range. This simplifies the processing configuration for specifying the 11th setting range. Because the 12th setting range is a contiguous address range, the starting address of the 12th setting range ("9109H") is set in the transfer source address counter 132 in step S4912, and the number of storage areas in the main RAM 74 included in the 12th setting range ("9") is set in the transfer count counter 114 in step S4913, thereby specifying the 12th setting range. This simplifies the processing configuration for specifying the 12th setting range.

By varying the start address and transfer count information for the transfer range (11th set range or 12th set range) in the common command transmission process depending on the type of command to be transmitted, the common common command transmission process can be used to set data stored in the memory area of the main RAM 74 included in the 11th set range in the transmission standby buffer 112 when transmitting a start command, and to set data stored in the memory area of the main RAM 74 included in the 12th set range in the transmission standby buffer 112 when transmitting an end command. Therefore, compared to a configuration in which a process is provided in which data from the main RAM 74 is transferred to the transmission standby buffer 112 when transmitting an end command as a separate process from the process in which data from the main RAM 74 is transferred to the transmission standby buffer 112 when transmitting a start command, the data volume of the program stored in the main ROM 73 for executing the process of transferring data from the main RAM 74 to the transmission standby buffer 112 can be reduced.

In the common data table 73g, the first aggregation range is set to the consecutive address range of "9101H" to "9104H." Therefore, the source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source address counter 132 by 2 (processing of step S5012). Furthermore, the second aggregation range is set to the consecutive address range of "910DH" to "9114H." Therefore, the source memory area can be updated sequentially by repeatedly executing the process of incrementing the value of the source address counter 132 by 2 (processing of step S5012). This simplifies the processing configuration for sequentially updating the source memory area.

Because the first aggregation range is a contiguous address range, the first aggregation range can be specified by setting the start address of the first aggregation range ("9101H") in the transfer source address counter 132 in step S5005 and setting the number of storage areas in the main RAM 74 included in the first aggregation range ("2") in the transfer count counter 114 in step S5006. This simplifies the processing configuration for specifying the first aggregation range. Because the second aggregation range is a contiguous address range, the start address of the second aggregation range ("910DH") in the transfer source address counter 132 in step S5007 and setting the number of storage areas in the main RAM 74 included in the second aggregation range ("4") in the transfer count counter 114 in step S5008 can be specified. This simplifies the processing configuration for specifying the second aggregation range.

Commands that aggregate data stored in the most significant bits include start commands and end commands, which aggregate data stored in the most significant bits in a different storage area of the main RAM 74 than the start commands. By varying the start address and transfer count information for the transfer range (first aggregation range or second aggregation range) in the top-level aggregation process depending on the type of command being sent, a common top-level aggregation process can be used to aggregate data stored in the most significant bits of the storage area of the main RAM 74 included in the first aggregation range in the top-level aggregation area 74v when a start command is sent, and aggregate data stored in the most significant bits of the storage area of the main RAM 74 included in the second aggregation range in the top-level aggregation area 74v when an end command is sent. Therefore, compared to a configuration in which a process for aggregating data stored in the most significant bits when an end command is sent is provided as a separate process from a process for aggregating data stored in the most significant bits when a start command is sent, the data volume of the program stored in the main ROM 73 for executing the process for aggregating data stored in the most significant bits can be reduced.

The data stored in the lower and upper areas of the AT continuation counter 74u is set in the consecutive second and third frames FR2-FR3 in the start command. Therefore, by repeatedly incrementing the value of the presentation-side transfer destination counter (step S5113), the transfer destination memory area where the data aggregated in the top aggregated frame SF is set can be sequentially updated. This simplifies the processing configuration for the presentation-side MPU 92 to set the data aggregated in bits 0-1 in the top aggregated frame SF of the start command to the most significant bit of the second and third frames FR2-FR3 corresponding to those bits 0-1. Furthermore, the data stored in the lower and upper areas of the continued game counter 74r and the lower and upper areas of the total win counter 74s are set in the consecutive fourth to seventh frames FR4-FR7 in the end command. Therefore, by repeatedly incrementing the value of the production-side transfer destination counter by 1 (step S5113), the transfer destination memory area where the data aggregated in the highest aggregated frame SF is set can be sequentially updated. This simplifies the processing structure for the production-side MPU 92 to set the data aggregated in bits 0 to 3 in the highest aggregated frame SF of the termination command to the highest bits of the fourth to seventh frames FR4 to FR7 corresponding to those bits 0 to 3.

Seventh Embodiment
This embodiment differs from the first embodiment in that when the start lever 41 is operated to start the game, the combined display unit 66 enters an all-off state in which the left 7-segment display 66a and the right 7-segment display 66b of the combined display unit 66 are not displayed. Below, the configurations that differ from the first embodiment will be described. Note that a description of the same configurations as the first embodiment will basically be omitted.

Figure 89(a) is an explanatory diagram illustrating the conditions under which the dual-purpose display unit 66 is in a fully unlit state, the conditions under which the stop order corresponding display is executed on the dual-purpose display unit 66, the conditions under which the ratio display is executed, and the conditions under which the number of awards display is executed. As shown in Figure 89(a), the dual-purpose display unit 66 is in one of the following states during a period in which a game is being executed: a fully unlit state, a state in which the stop order corresponding display is executed, or a state in which the number of awards display is executed; and during a period in which a game is not being executed, a state in which the ratio display is executed or the number of awards display is executed. Here, a period in which a game is being executed is a period in which the in-game flag in the main RAM 74 is set to "1," and a period in which a game is not being executed is a period in which the value of the in-game flag is "0."

While the game is being played, the dual-purpose display unit 66 will be fully turned off, provided that the off data "255" is set in the award number counter 74e of the main RAM 74. Furthermore, the dual-purpose display unit 66 will display the stop order information, provided that the off data ("255") is not set in the award number counter 74e and a stop order type number between "1" and "9" is set in the stop order type counter 74m of the main RAM 74.

When a game is not being played, the ratio display is executed on the dual-purpose display unit 66 on the condition that calculation result data of any one of "0" to "100" is set in the ratio display counter 74n. Whether a game is being played or not, the number of awards displayed on the dual-purpose display unit 66 is executed on the condition that the extinguishing data ("255") is not set in the award number counter 74e, the stop order type number of "1" to "9" is not set in the stop order type counter 74m, and the calculation result data of "0" to "100" is not set in the ratio display counter 74n.

The period during which the award number counter 74e is set to light-off data ("255") and the period during which the stop order type counter 74m is set to any of the stop order type numbers "1" to "9" occur and end while the game is being played. On the other hand, as already explained in the first embodiment above, calculation result data of "0" to "100" is set to the ratio display counter 74n when the ratio display start operation is performed while the game is not being played. Therefore, the state in which the award number counter 74e is set to light-off data ("255") and the state in which the ratio display counter 74n is set to calculation result data of "0" to "100" do not overlap. Furthermore, the state in which the stop order type counter 74m is set to any of the stop order type numbers "1" to "9" and the state in which the ratio display counter 74n is set to calculation result data of "0" to "100" do not overlap.

The light-off data is set in the award number counter 74e when the start lever 41 is operated to start the game. The light-off data set in the award number counter 74e is cleared when the first acceleration period for reels 32L, 32M, and 32R ends in the reel control process (see Figure 90) described below. Acceleration control of reels 32L, 32M, and 32R is executed during the first acceleration period and the second acceleration period. The first acceleration period lasts approximately 290 milliseconds from the start of acceleration control of reels 32L, 32M, and 32R. The second acceleration period lasts approximately 10 milliseconds following the first acceleration period.

Figure 89(b) is an explanatory diagram for explaining the configuration of the main RAM 74. As shown in Figure 89(b), the main RAM 74 is provided with an acceleration period counter 74γ. The acceleration period counter 74γ is a timer counter that allows the main MPU 72 to determine when the first and second acceleration periods of the reels 32L, 32M, and 32R have ended. The value of the acceleration period counter 74γ is updated by subtracting 1 in the timer subtraction process of step S208 in the timer interrupt process (Figure 11). When the main MPU 72 starts acceleration control of the reels 32L, 32M, and 32R, it sets "195" to the acceleration period counter 74γ as information corresponding to the first acceleration period. The value of the acceleration period counter 74γ becomes "0" approximately 290 milliseconds after acceleration control of the reels 32L, 32M, and 32R has started. This allows the main MPU 72 to determine when the first acceleration period has ended. When the first acceleration period ends, the main MPU 72 sets "7" in the acceleration period counter 74γ as information corresponding to the second acceleration period. The value of the acceleration period counter 74γ becomes "0" approximately 10 milliseconds after the second acceleration period of the reels 32L, 32M, and 32R begins. This allows the main MPU 72 to know that the second acceleration period has ended.

As described above, when the start lever 41 is operated to start a new game, the dual-purpose display unit 66 temporarily goes into a fully unlit state. If the previous game ends without a small win, the value of the award number counter 74e becomes "0" and the dual-purpose display unit 66 displays the award number of "00" corresponding to the value of the award number counter 74e. Thereafter, even if a bet operation or medal insertion is performed to start the game, the value of the award number counter 74e remains "0", and the dual-purpose display unit 66 continues to display the award number of "00" corresponding to the value of the award number counter 74e. In a game in which stop order corresponding display is not executed on the combined display unit 66, if the display mode of the combined display unit 66 is not changed during the period from the start of the game to the winning determination process (step S5319 of the reel control process (FIG. 90) described later), when a small winning combination is not achieved in the game, the value of the award number counter 74e continues to be "0", and the combined display unit 66 continues to display the number of awards of "00" corresponding to the value of the award number counter 74e. In this way, in a game in which stop order corresponding display is not executed on the combined display unit 66, if the display mode of the combined display unit 66 is not changed during the period from the start of the game to the winning determination process (step S5319), the combined display unit 66 continues to display "00" throughout the period from before the game starts to the end of the game, and there are cases in which it is not possible to know that the game has started based on the display on the combined display unit 66. In contrast, by configuring the dual-purpose display unit 66 to be temporarily turned off at the start of the game, it is possible to prevent the state in which "00" is displayed on the dual-purpose display unit 66 from continuing before and after the game is executed, and it is also possible to prevent the state in which "00" is displayed on the dual-purpose display unit 66 from continuing before and after the start of the game. This allows the display mode of the dual-purpose display unit 66 at the start of the game to be a display mode that corresponds to the start of the game. By changing the display mode of the dual-purpose display unit 66 at the start of the game, it is possible to know that the game has started based on the display mode of the dual-purpose display unit 66.

As already explained in the first embodiment, the stop order display is executed on the condition that an index value IV of "1" to "9" is won in the lottery process (FIG. 18) for a game in which the gaming state is the pseudo bonus state ST4 or the AT state ST5 and the bet amount is "3." In a game in which the stop order display is executed on the dual-purpose display unit 66, as in the first embodiment, a stop order type number of "1" to "9" is set in the stop order type counter 74m before acceleration control of the reels 32L, 32M, and 32R begins. Then, with the stop order type number set in the stop order type counter 74m, the award number counter 74e is cleared to "0" at the end of the first acceleration period. The port output process (FIG. 91), described later, is then executed, thereby switching the display content on the dual-purpose display unit 66 from the award number display to the stop order display. The timer interrupt process (FIG. 11), including the port output process, is executed at a cycle of 1.49 milliseconds, as in the first embodiment. Because the second acceleration period (approximately 10 milliseconds) is longer than the 1.49 milliseconds, after the award number counter 74e is cleared to "0" at the end of the first acceleration period, the port output process is always executed between the end of the second acceleration period and the activation of the stop buttons 42-44. Therefore, in games in which stop order corresponding display is executed, the stop order corresponding display can be reliably started on the dual-purpose display unit 66 at a timing before the activation of the stop buttons 42-44.

In both games in which stop order corresponding display is executed on the dual-purpose display unit 66 and games in which stop order corresponding display is not executed, the dual-purpose display unit 66 is temporarily put into a fully off state at the start of the game. Processing to put the dual-purpose display unit 66 into a fully off state is executed regardless of the results of the winning combination lottery process (Figure 18). Therefore, when a game starts based on the operation of the start lever 41, processing to put the dual-purpose display unit 66 into a fully off state can be executed prior to the timing at which the winning combination lottery process (Figure 18) is executed. This ensures a long duration for the fully off state in a configuration in which the dual-purpose display unit 66 ends its fully off state prior to the timing at which the operation of the stop buttons 42-44 is enabled.

As described above, the main MPU 72 turns the dual-purpose display unit 66 to a fully off state on the condition that off data ("255") is set in the award count counter 74e. The award count counter 74e is a counter in which information about the number of awards of gaming media is set, and in which off data for turning the dual-purpose display unit 66 to a fully off state is set. Therefore, compared to a configuration in which, in addition to the award count counter 74e in which information about the number of awards of gaming media is set, a flag or the like is set in the main RAM 74 to set information indicating the timing for turning the dual-purpose display unit 66 to a fully off state, the data capacity of the storage area provided in the main RAM 74 can be reduced to enable the main MPU 72 to grasp the number of awards of gaming media and the timing for turning the dual-purpose display unit 66 to a fully off state.

Next, the start-up setting process executed by the main MPU 72 will be explained with reference to the flowchart in Figure 89 (c). As already explained in the first embodiment above, the start-up setting process is executed in step S406, which is the step immediately before step S407 in which the role selection process (Figure 18) is executed in the normal process (Figure 13).

During the start-up setup process, the payout counter 74e in the master RAM 74 is set to "255," which is the off data (step S5201). This allows the master MPU 72 to execute the process for turning off all of the dual-purpose display units 66 during the next port output process (Figure 91). Subsequently, in steps S5202 through S5205, the same processes as steps S801 through S804 of the start-up setup process (Figure 17(b)) in the first embodiment are executed. Specifically, the value of the index value counter 74f in the master RAM 74 is cleared to "0" (step S5202), and both the replay bet set flag and the acceptance bet set flag in the master RAM 74 are cleared to "0" (step S5203). Subsequently, the game-in-progress flag in the master RAM 74 is set to "1" (step S5204). This allows the master MPU 72 to recognize that a game is currently being played. Thereafter, the value of the bet number setting counter 74b in the master RAM 74 is set to the bet number history counter 74c in the master RAM 74 (step S5205), and the initial setting process is terminated. By setting the value of the bet number setting counter 74b to the bet number history counter 74c in step S5205, the master MPU 72 can determine the number of bets on the game that has just started after the game has ended.

Next, the reel control processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 90. As already explained in the first embodiment above, the reel control processing is executed in step S408 of the normal processing (Figure 13).

In the reel control process, a spin start process is executed (step S5301), similar to step S1001 in the reel control process (FIG. 22) in the first embodiment described above. In the spin start process, a check is made to see if a predetermined wait time (e.g., 4.1 seconds) has elapsed since the start of spinning of reels 32L, 32M, and 32R in the previous game. If the wait time has not elapsed, the process waits until the wait time has elapsed. If the wait time has elapsed, the process resets the wait time for the next game and sets spin start information in the motor control storage area in main RAM 74. By performing this process, the stepping motor acceleration process is initiated in the stepping motor control process of step S206 in the timer interrupt process (FIG. 11), and each of reels 32L, 32M, and 32R begins spinning.

Then, a first acceleration period setting process is executed (step S5302). In the first acceleration period setting process, the numerical information "195", which corresponds to the first acceleration period (approximately 290 milliseconds) of reels 32L, 32M, and 32R, is set to the acceleration period counter 74γ in the main RAM 74. As described above, the value of the acceleration period counter 74γ is updated by subtracting 1 in the timer subtraction process in step S208 of the timer interrupt process (FIG. 11). It then becomes "0" after approximately 290 milliseconds have elapsed. Then, a determination is made as to whether the first acceleration period of reels 32L, 32M, and 32R has ended (step S5303). If the first acceleration period has not ended, the process in step S5303 is repeatedly executed until the first acceleration period ends. In step S5303, a positive determination is made if the value of the acceleration period timer counter in the main RAM 74 is "0".

If a positive determination is made in step S5303, the value of the award number counter 74e in the main RAM 74 is cleared to "0" (step S5304). This terminates the state in which the award number counter 74e has been set to off data ("255"), and enables the state to be changed so that processing is executed to execute stop order corresponding display or award number display on the dual-purpose display unit 66 in the next port output process (FIG. 91). In a game in which stop order corresponding display is executed, processing to execute stop order corresponding display is executed in the next port output process, thereby switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the dual-purpose display unit 66 is executing stop order corresponding display. Furthermore, in a game in which stop order display is not executed, processing to execute award number display is executed in the next port output process, thereby switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the dual-purpose display unit 66 is executing award number display.

Then, a second acceleration period setting process is executed (step S5305). In the second acceleration period setting process, the acceleration period counter 74γ is set to the numerical value "7," which corresponds to the second acceleration period (approximately 10 milliseconds) for reels 32L, 32M, and 32R. As described above, the value of the acceleration period counter 74γ is updated by subtracting 1 in the timer subtraction process of step S208 in the timer interrupt process (FIG. 11). The counter then becomes "0" after approximately 10 milliseconds have elapsed. It is then determined whether the second acceleration period for reels 32L, 32M, and 32R has ended (step S5306). If the second acceleration period has not ended, the process of step S5306 is repeatedly executed until the second acceleration period ends. In step S5306, a positive determination is made if the value of the acceleration period timer counter in the main RAM 74 is "0."

If a positive determination is made in step S5306, steps S5307 through S5320 execute the same processing as steps S1003 through S1016 of the reel control processing (FIG. 22) in the first embodiment described above. Specifically, an operation validation notification process is first executed (step S5307). In the operation validation notification process, lamps (not shown) corresponding to each stop button 42 through 44 are lit to notify the player that it is now possible to issue a stop command. It is then determined whether any of the stop buttons 42 through 44 has been operated (step S5308). If none of the stop buttons 42 through 44 have been operated (step S5308: NO), the process of step S5308 is repeatedly executed until any of the stop buttons 42 through 44 is operated. If it is determined that one of the stop buttons 42-44 has been operated (step S5308: YES), it is determined whether or not the stop button 42-44 corresponding to the spinning reels 32L, 32M, 32R has been operated, i.e., whether or not a stop command has been issued (step S5309). If a stop command has not been issued, the process returns to step S5308, and steps S5308-S5309 are repeatedly executed until one of the stop buttons 42-44 is operated.

If a stop command is issued (step S5309: YES), an operation invalidation notification process corresponding to the currently operated stop button 42-44 is executed (step S5310), and a stop command command is sent to the production-side MPU 92 (step S5311). Subsequently, if a stop command command is sent, the stop control process shown in steps S5312 to S5318 is performed to stop the spinning reels. In the stop control process, the symbol number of the reaching symbol that reached the base position (specifically, the lower row) at the time the stop button 42-44 was operated is confirmed (step S5312), and the slip count (a value between "0" and "4") of the reels 32L, 32M, and 32R that should be stopped this time is calculated based on the stop information stored in the main RAM 74 (step S5313). The calculated slip count is then added to the symbol number of the reaching symbol to determine the symbol number of the stop symbol that will actually stop at the base position (step S5314). Next, it is determined whether the symbol number of the reaching symbol on reels 32L, 32M, and 32R that should be stopped this time is equal to the symbol number of the stopped symbol (step S5315). If they are equal (step S5315: YES), a reel stop process is performed to stop the rotation of reels 32L, 32M, and 32R (step S5316). If all reels 32L, 32M, and 32R have not stopped (step S5317: NO), a second stop information setting process is performed (step S5318), and the process returns to step S5308. The processes of steps S5308 to S5318 are then repeated until a positive determination is made in step S5317.

If it is determined in step S5317 that all reels 32L, 32M, and 32R are stopped, a winning determination process is executed (step S5319). In this winning determination process, the type of symbols stopped on the main line ML on each reel 32L, 32M, and 32R is identified. Then, based on the contents of the winning data stored in the main RAM 74, it is determined whether the combination of symbols stopped and displayed on the main line ML on each reel 32L, 32M, and 32R corresponds to a winning combination in the winning combination lottery process. If the combination of symbols corresponds to a winning combination, it is determined that a winning combination has been achieved. As already explained in the first embodiment, in the winning determination process (step S5319), if it is determined that any of the small winning combinations has been achieved, the information on the number of awards corresponding to the achieved small winning combination ("1," "2," "5," or "15") is set in the award number counter 74e of the main RAM 74, and the value of the stop order type counter 74m in the main RAM 74 is cleared to "0." Also, in the winning determination process (step S5319), if it is determined that any of the replay winning combinations has been achieved, a flag is set so that the replay setting process is executed in the next start waiting process (FIG. 15), and the value of the stop order type counter 74m is cleared to "0." Furthermore, in the winning determination process (step S5319), if it is determined that no winning combination has been achieved, the value of the stop order type counter 74m is cleared to "0." By clearing the value of the stop order type counter 74m to "0", the state is set so that processing for displaying the number of awards on the combined display unit 66 is executed in the next port output processing (FIG. 28). In a game in which the stop order corresponding display is executed on the combined display unit 66, processing for displaying the number of awards on the combined display unit 66 is executed in the next port output processing (FIG. 28), thereby switching from a state in which the stop order corresponding display is executed on the combined display unit 66 to a state in which the number of awards is displayed on the combined display unit 66. If no small winning combination is achieved in a game in which the stop order corresponding display is not executed on the combined display unit 66, even if processing for displaying the number of awards on the combined display unit 66 is executed in the next port output processing (FIG. 28), the state in which the combined display unit 66 is displaying the number of awards of "00" continues. If the achievement of any minor winning combination is identified in a game in which the stop order display is not executed on the dual-purpose display unit 66, the process for displaying the number of awards executed on the dual-purpose display unit 66 is executed in the next port output process (FIG. 28), and the display content of the number of awards executed on the dual-purpose display unit 66 changes from "00" to "01," "02," "05," or "15." After that, the winning result command flag in the main RAM 74 is set to "1" (step S5320), and the reel control process ends.

As described above, in a game in which stop order corresponding display is executed on the dual-purpose display unit 66, by executing a process to clear the award number counter 74e to "0" (processing of step S5304) when the dual-purpose display unit 66 is in a fully unlit state, it is possible to end the state in which the unlit data is set in the award number counter 74e and to execute a process to execute stop order corresponding display on the dual-purpose display unit 66 in the next port output process (Figure 91). By executing the process to execute stop order corresponding display in the next port output process, the dual-purpose display unit 66 switches from a fully unlit state to a state in which stop order corresponding display is being executed on the dual-purpose display unit 66. Therefore, compared to a configuration in which a process is set to set the dual-purpose display unit 66 in a state where a process for executing a stop order corresponding display is executed in the next port output process as a separate process from the process for clearing to "0" the value of the number of indications counter 74e for which the light-off data is set (processing of step S5304), the process configuration for switching from a state in which the dual-purpose display unit 66 is in an all-off state to a state in which a stop order corresponding display is executed in the dual-purpose display unit 66 can be simplified.

In games in which stop order display is not performed on the dual-purpose display unit 66, by executing a process to clear the award number counter 74e to "0" (processing of step S5304) while the dual-purpose display unit 66 is in a fully unlit state, it is possible to end the state in which the unlit data is set in the award number counter 74e and to execute a process to display the award number (display "00") on the dual-purpose display unit 66 in the next port output process (Figure 91). By executing the process to display the award number in the next port output process, the dual-purpose display unit 66 switches from a fully unlit state to a state in which the dual-purpose display unit 66 is displaying the award number. Therefore, compared to a configuration in which a process is set to execute a process to display the number of awards on the dual-purpose display unit 66 during the next port output process as a separate process from the process to clear the value of the award number counter 74e, for which the off data is set, to "0" (the process of step S5304), the process configuration for switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the number of awards is being displayed on the dual-purpose display unit 66 can be simplified.

Next, the port output processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 91. As already explained in the first embodiment, the port output processing is executed in step S211 of the timer interrupt processing (Figure 11). As mentioned above, the timer interrupt processing (Figure 11) is executed at a cycle of 1.49 milliseconds.

In the port output process, it is first determined whether the off data "255" is set in the grant number counter 74e of the main RAM 74 (step S5401). If off data is set in the grant number counter 74e (step S5401: YES), non-display data is set in the left-side dual-purpose display display area 74p and the right-side dual-purpose display display area 74q in the main RAM 74 (step S5402). This non-display data set in the dual-purpose display display areas 74p and 74q is output to the dual-purpose display unit 66 in step S5411 (described below), thereby enabling the dual-purpose display unit 66 to be fully off.

If a negative determination is made in step S5401, steps S5403 to S5413 execute the same processing as steps S1401 to S1411 of the port output processing (Figure 28) in the first embodiment. Specifically, it determines whether a stop order type number between "1" and "9" is set in the stop order type counter 74m in the main RAM 74 (step S5403). If a stop order type number between "1" and "9" is set in the stop order type counter 74m (step S5403: YES), the stop order correspondence display data table 73a stored in the main ROM 73 is read (step S5404). The read stop order correspondence display data table 73a is referenced, and display data corresponding to the value of the stop order type counter 74m is set in the right-side dual-use display area 74q, and non-display data is set in the left-side dual-use display area 74p (step S5405). This display data and non-display data set in the dual-purpose display display areas 74p and 74q are output to the dual-purpose display unit 66 in step S5411, which will be described later, allowing the dual-purpose display unit 66 to perform stop order-based display.

If, after a negative determination is made in step S5403, calculation result data between "0" and "100" is set in the ratio display counter 74n of the main RAM 74 (step S5406: YES), the numeric display data table 73b stored in the main ROM 73 is read (step S5407), and the read numeric display data table 73b is referenced to set display data corresponding to the value of the ratio display counter 74n in the left-side dual-purpose display display area 74p and the right-side dual-purpose display display area 74q (step S5408). This display data set in the dual-purpose display display areas 74p and 74q is output to the dual-purpose display unit 66 in step S5411, described below, allowing the dual-purpose display unit 66 to display the ratio.

If a stop order type number between "1" and "9" is not set in the stop order type counter 74m (step S5403: NO) and calculation result data between "0" and "100" is not set in the ratio display counter 74n (step S5406: NO), processing is performed to display the number of awards on the dual-purpose display unit 66 (processing of steps S5409 to S5410). Specifically, as in step S5407, the numeric display data table 73b stored in the main ROM 73 is read (step S5409), and the read numeric display data table 73b is referenced to set display data corresponding to the value of the number of awards counter 74e in the left-side dual-purpose display unit display area 74p and the right-side dual-purpose display unit display area 74q (step S5410). This display data set in the dual-purpose display area 74p, 74q is output to the dual-purpose display unit 66 in step S5411, which will be described later, allowing the number of points awarded to be displayed on the dual-purpose display unit 66.

When step S5402, step S5405, step S5408, or step S5410 is performed, the data (display data or non-display data) set in the left-side shared display display area 74p and the right-side shared display display area 74q is output to the shared display unit 66 (step S5411). As a result, if non-display data is set in the shared display display areas 74p and 74q, the shared display unit 66 is fully turned off. Furthermore, if non-display data is set in the left-side shared display display area 74p and display data for stop order corresponding display is set in the right-side shared display display area 74q, stop order corresponding display is executed in the shared display unit 66. Furthermore, if non-display data or display data for ratio display is set in the left-side shared display display area 74p and display data for ratio display is set in the right-side shared display display area 74q, ratio display is executed in the shared display unit 66. In addition, if display data for displaying the number of points awarded is set in the dual-purpose display area 74p, 74q, the number of points awarded will be displayed on the dual-purpose display 66.

Then, display control processing of the credit display unit 65 is executed (step S5412), other port output processing is executed (step S5413), and this port output processing ends. In the other port output processing in step S5413, data corresponding to the I/O device is output from the input/output port.

Next, the manner in which the dual-purpose display unit 66 is in a fully unlit state in a game in which stop order corresponding display is performed on the dual-purpose display unit 66 will be described with reference to the time chart in Figure 92. Figure 92(a) shows the period during which the dual-purpose display unit 66 is in a fully unlit state, Figure 92(b) shows the period during which the dual-purpose display unit 66 displays the number of awards "00", Figure 92(c) shows the period during which the dual-purpose display unit 66 displays the number of awards, Figure 92(d) shows the period during which the unlit data "255" is set in the number of awards counter 74e, Figure 92(e) shows the period during which the stop order type number of any of "1" to "9" is set in the stop order type counter 74m, and Figure 92(f) shows the period during which the reels 32L, 32M , 32R, Figure 92(g) shows the timing when a bet operation or the first medal insertion is performed when no game is being played, Figure 92(h) shows the timing when the game starts, Figure 92(i) shows the timing when operation of stop buttons 42 to 44 is validated, Figure 92(j) shows the timing when the winning determination process (step S5319 of the reel control process (Figure 90)) is executed, and Figure 92(k) shows the timing when the port output process (Figure 91) is executed.

When the value of the award number counter 74e is "0" and the combined display unit 66 is displaying the number of awards "00," a bet operation or the first medal insertion is performed as shown in FIG. 92(g), causing the value of the award number counter 74e to remain at "0." Then, when a port output process is executed at time t2 as shown in FIG. 92(k), the combined display unit 66 continues to display the number of awards "00," as shown in FIG. 92(c). Then, when a game starts at time t3 as shown in FIG. 92(h), extinguishing data ("255") is set in the award number counter 74e as shown in FIG. 92(d). Then, when a port output process is executed at time t4 as shown in FIG. 92(k), the combined display unit 66 stops displaying the number of awards and turns off the combined display unit 66, as shown in FIGS. 92(a) and (c).

Then, at timing t5, a stop order type number between "1" and "9" is set in the stop order type counter 74m, as shown in FIG. 92(e). Then, at timing t6, a first acceleration period for reels 32L, 32M, and 32R begins, as shown in FIG. 92(f), and ends at timing t7. At timing t7, when the first acceleration period ends, the award number counter 74e is cleared to "0," as shown in FIG. 92(d), thereby ending the state in which the award number counter 74e had its lights-off data set. Then, as shown in FIG. 92(k), when port output processing is executed at timing t8, the combined display unit 66 ends its fully turned-off state, as shown in FIGS. 92(a) and (b), and the combined display unit 66 begins displaying the stop order. Then, at timing t9, operation of the stop buttons 42 to 44 is enabled, as shown in FIG. 92(j).

Then, at timing t10, the winning determination process is executed as shown in Figure 92 (j), and if it is determined in the winning determination process that no small winning combinations have been achieved, the value of the award number counter 74e remains at "0". Also, at timing t10, the value of the stop order type counter 74m is cleared to "0" as shown in Figure 92 (e). Then, when the port output process is executed at timing t11 as shown in Figure 92 (k), the display content on the dual-purpose display unit 66 switches from the stop order corresponding display to the award number display (displaying "00") as shown in Figures 92 (b) and (c).

As described above, by configuring the dual-purpose display unit 66 to temporarily be fully unlit when the game starts, it is possible to prevent the dual-purpose display unit 66 from continuing to display the number of points awarded as "00" before and after the game starts. By changing the display mode of the dual-purpose display unit 66 when the game starts, it is possible to know that the game has started based on the display mode of the dual-purpose display unit 66.

In a configuration in which the dual-purpose display unit 66 ends its fully-off state at t8, which is before t9 when operation of the stop buttons 42-44 is enabled, processing is executed to put the dual-purpose display unit 66 into a fully-off state, regardless of the results of the role selection process (Figure 18). Therefore, processing to put the dual-purpose display unit 66 into a fully-off state (processing to set the off data in the award number counter 74e) can be executed at t3, which is before the role selection process (Figure 18) is executed. This ensures that the fully-off state lasts for a long time.

Next, we will explain, with reference to the time chart in Figure 93, how the dual-purpose display unit 66 becomes fully unlit in a game in which the dual-purpose display unit 66 does not display the stop order. FIG. 93(a) shows the period during which the dual-purpose display unit 66 is in a fully unlit state, FIG. 93(b) shows the period during which the award number display of "00" is executed on the dual-purpose display unit 66, FIG. 93(c) shows the period during which the award number counter 74e is set to the unlit data "255", FIG. 93(d) shows the first acceleration period of reels 32L, 32M, 32R, FIG. 93(e) shows the timing when a bet operation or the first medal insertion is performed when no game is being played, FIG. 93(f) shows the timing when the game starts, FIG. 93(g) shows the timing when operation of stop buttons 42-44 is enabled, FIG. 93(h) shows the timing when the establishment of any small winning combination is identified in the winning determination process (step S5319 of the reel control process (FIG. 90)), and FIG. 93(i) shows the timing when the port output process (FIG. 91) is executed.

When a bet operation or the first medal insertion is performed at timing t1, when the value of the award number counter 74e is "0" and the combined display unit 66 is displaying the award number of "00," as shown in FIG. 93(e), the value of the award number counter 74e remains at "0." Then, when a port output process is performed at timing t2, as shown in FIG. 93(i), the combined display unit 66 continues to display the award number of "00," as shown in FIG. 93(b). Then, when a game starts at timing t3, as shown in FIG. 93(f), the award number counter 74e is set to off data ("255") as shown in FIG. 93(c). Then, when a port output process is performed at timing t4, as shown in FIG. 93(i), the combined display unit 66 stops displaying the award number and becomes completely off, as shown in FIGS. 93(a) and (b).

Then, as shown in FIG. 93(d), the first acceleration period for reels 32L, 32M, and 32R begins at time t5 and ends at time t6. At time t6, when the first acceleration period ends, the award number counter 74e is cleared to "0" as shown in FIG. 93(c). Then, as shown in FIG. 93(i), the port output process is executed at time t7, and the dual-purpose display unit 66 ends its fully illuminated state and begins displaying the award number as shown in FIGS. 93(a) and (b). Then, at time t8, operation of stop buttons 42-44 is enabled. Then, as shown in FIG. 93(h), the winning determination process is executed at time t9. If it is determined that no small winning combinations have been achieved in the winning determination process, the value of the award number counter 74e remains at "0." Thereafter, even if the port output process is executed at timing t10 as shown in Figure 93(i), the status in which the added number display of "00" is executed on the dual-purpose display unit 66 as shown in Figure 93(b) continues.

As described above, in a game in which the stop order display is not performed on the dual-purpose display unit 66, when a bet operation or medal insertion is performed, the dual-purpose display unit 66 displays the number of awards as "00", and the winning determination process (step S5319) is executed while the dual-purpose display unit 66 displays the number of awards as "00". By temporarily turning off the dual-purpose display unit 66 at the start of the game, it is possible to prevent the dual-purpose display unit 66 from continuing to display the number of awards as "00" for the period from before the start of the game until the end of the game. By changing the display mode of the dual-purpose display unit 66 at the start of the game, it is possible to know that the game has started based on the display mode of the dual-purpose display unit 66.

In a configuration in which the dual-purpose display unit 66 ends its fully-off state at t7, which is before t8 when operation of the stop buttons 42-44 is enabled, processing is executed to put the dual-purpose display unit 66 into a fully-off state, regardless of the results of the role selection process (Figure 18). Therefore, processing to put the dual-purpose display unit 66 into a fully-off state (processing to set the off data in the award number counter 74e) can be executed at t3, which is before the role selection process (Figure 18) is executed. This ensures that the fully-off state lasts for a long time.

The present embodiment described above provides the following excellent effects:

The main MPU 72 turns the dual-purpose display unit 66 to a fully off state on the condition that off data ("255") is set in the award number counter 74e. The award number counter 74e is a counter in which information on the number of awards of gaming media is set, and is also a counter in which off data for turning the dual-purpose display unit 66 to a fully off state is set. Therefore, compared to a configuration in which, in addition to the award number counter 74e in which information on the number of awards of gaming media is set, a flag or the like is set in the main RAM 74 to indicate the timing for turning the dual-purpose display unit 66 to a fully off state, the data capacity of the storage area provided in the main RAM 74 can be reduced to enable the main MPU 72 to grasp the number of awards of gaming media and the timing for turning the dual-purpose display unit 66 to a fully off state.

In a game in which stop order corresponding display is executed on the dual-purpose display unit 66, by executing a process of clearing the award number counter 74e to "0" (processing of step S5304) while the dual-purpose display unit 66 is in a fully turned-off state, it is possible to end the state in which turn-off data is set in the award number counter 74e, and to enter a state in which a process for executing stop order corresponding display is executed on the dual-purpose display unit 66 in the next port output process (FIG. 91). By executing the process for executing stop order corresponding display in the next port output process, the state in which the dual-purpose display unit 66 is in a fully turned-off state is switched to a state in which stop order corresponding display is executed on the dual-purpose display unit 66. Therefore, compared to a configuration in which a process is set to set the state in which the process for executing the stop order corresponding display on the dual-purpose display unit 66 in the next port output process to be executed as a separate process from the process of clearing the value of the grant number counter 74e in which the light-off data is set to "0" (processing of step S5304), the processing configuration for switching from a state in which the dual-purpose display unit 66 is in a fully turned-off state to a state in which the stop order corresponding display is being executed on the dual-purpose display unit 66 can be simplified.

In games in which stop order display is not performed on the dual-purpose display unit 66, by executing a process to clear the award number counter 74e to "0" (processing of step S5304) while the dual-purpose display unit 66 is in a fully unlit state, it is possible to end the state in which the unlit data is set in the award number counter 74e and to execute a process to display the award number (display "00") on the dual-purpose display unit 66 in the next port output process (Figure 91). By executing the process to display the award number in the next port output process, the dual-purpose display unit 66 switches from a fully unlit state to a state in which the dual-purpose display unit 66 is displaying the award number. Therefore, compared to a configuration in which a process is set to execute a process to display the number of awards on the dual-purpose display unit 66 during the next port output process as a separate process from the process to clear the value of the award number counter 74e, for which the off data is set, to "0" (the process of step S5304), the process configuration for switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the number of awards is being displayed on the dual-purpose display unit 66 can be simplified.

By configuring the dual-purpose display unit 66 to temporarily be fully unlit at the start of a game, it is possible to prevent the dual-purpose display unit 66 from continuing to display the number of points awarded as "00" before and after the start of a game. By changing the display mode of the dual-purpose display unit 66 at the start of a game, it is possible to know that the game has started based on the display mode of the dual-purpose display unit 66.

In games in which the stop order display is not performed on the dual-purpose display unit 66, when a bet operation or medal insertion is performed, the dual-purpose display unit 66 displays the number of awards as "00", and the winning determination process (step S5319) is executed while the dual-purpose display unit 66 displays the number of awards as "00". By temporarily turning off the dual-purpose display unit 66 at the start of the game, it is possible to prevent the dual-purpose display unit 66 from continuing to display the number of awards as "00" from before the game starts until the game ends.

In a configuration in which the dual-purpose display unit 66 ends its fully-off state before the operation of the stop buttons 42-44 is enabled, processing is executed to put the dual-purpose display unit 66 into a fully-off state regardless of the results of the winning combination lottery process (Figure 18). Therefore, processing to put the dual-purpose display unit 66 into a fully-off state can be executed before the winning combination lottery process (Figure 18) is executed. This ensures that the fully-off state lasts for a long time.

Eighth Embodiment
This embodiment differs from the seventh embodiment in that, provided that the game is one in which stop order corresponding display is not executed on the dual-purpose display unit 66, the dual-purpose display unit 66 is temporarily turned off when acceleration control of the reels 32L, 32M, and 32R begins. The following describes the configuration that differs from the seventh embodiment. Note that a description of the same configuration as the seventh embodiment will be omitted.

As already explained in the seventh embodiment above, the condition for the stop order corresponding display to be executed on the combined display unit 66 is that an index value IV of any one of "1" to "9" is won in the lottery process (FIG. 18) for a game in which the gaming state is the pseudo bonus state ST4 or the AT state ST5 and the number of bets is "3." In the all-lights-off state, as in the seventh embodiment above, the left 7-segment display 66a and the right 7-segment display 66b on the combined display unit 66 are not displayed. As already explained in the first embodiment above, in a game in which the stop order corresponding display is executed on the combined display unit 66, a stop order notification is executed on the image display device 63.

As already explained in the seventh embodiment above, the condition for the dual-purpose display unit 66 to be in the fully off state is that the off data "255" is set in the award number counter 74e of the main RAM 74. The dual-purpose display unit 66 is in the fully off state only while a game is being played. When the dual-purpose display unit 66 is to be in the fully off state, as in the seventh embodiment above, the main MPU 72 sets the off data "255" in the award number counter 74e of the main RAM 74. This enables the process for setting the dual-purpose display unit 66 to the fully off state (the processes of steps S5401, S5402, and S5411) to be executed in the next port output process (FIG. 91).

As described above, if the conditions for executing the stop order display on the combined display unit 66 are not met, the combined display unit 66 temporarily goes into a fully unlit state when acceleration control of reels 32L, 32M, and 32R begins. As with the seventh embodiment, if the previous game ends without a small win, the value of the award counter 74e becomes "0," and the combined display unit 66 displays the number of awards of "00," which corresponds to the value of the award counter 74e. Thereafter, even if a bet operation or medal insertion is performed to start the game, the value of the award counter 74e remains "0," and the combined display unit 66 continues to display the number of awards of "00," which corresponds to the value of the award counter 74e. As with the first embodiment, in a game in which the stop order display is not executed on the combined display unit 66, the winning determination process (FIG. 26) is executed in step S1015 of the reel control process (FIG. 22) with the number of awards displayed as "00" on the combined display unit 66. In a game in which stop order corresponding display is not executed, if the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), when a small winning combination is not achieved in the game, the value of the award number counter 74e continues to be "0", and the award number display of "00" corresponding to the value of the award number counter 74e continues on the dual-purpose display unit 66. In this way, in a game in which stop order corresponding display is not executed on the dual-purpose display unit 66, if the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), the state in which "00" is displayed on the dual-purpose display unit 66 continues from before the game starts to the end of the game, and there are cases in which it is not possible to know that the game has started based on the display on the dual-purpose display unit 66. In contrast, if the conditions for executing the stop order corresponding display on the dual-purpose display unit 66 are not met, the dual-purpose display unit 66 can be configured to temporarily turn off completely when acceleration control of reels 32L, 32M, and 32R begins. This prevents the dual-purpose display unit 66 from continuing to display "00" for the period from when a bet is made or a medal is inserted until the win determination process (FIG. 26) is executed. This allows the display mode of the dual-purpose display unit 66 to change in a mode corresponding to the start of a game in which the stop order corresponding display on the dual-purpose display unit 66 is not executed.

Figure 94(a) is an explanatory diagram for explaining the configuration of the main RAM 74. As shown in Figure 94(a), the main RAM 74 is provided with an off-time counter 74δ. The off-time counter 74δ is a counter that allows the main MPU 72 to grasp the timing when the all-off state in the dual-purpose display unit 66 ends. The off-time counter 74δ consists of one byte. When the main MPU 72 sets the off data "255" in the number-of-events counter 74e, it sets "221" in the off-time counter 74δ as information on the duration of the all-off state. "221" is numerical information for setting the all-off state to approximately 330 milliseconds. As already explained in the first embodiment above, the timer interrupt process (Figure 11) is executed at a cycle of 1.49 milliseconds, and the timer subtraction process is executed in step S208 of the timer interrupt process. Details of the timer subtraction process (Figure 95) in this embodiment will be described later, but the value of the extinguishing time counter 74δ is updated by subtracting 1 during the timer subtraction process, and becomes "0" approximately 330 milliseconds after the extinguishing data is set in the number of times the timer is applied counter 74e.

As already explained in the first embodiment, the reel control process (FIG. 22) is executed in step S408 of the normal process (FIG. 13). In this embodiment, the acceleration period during which acceleration control of reels 32L, 32M, and 32R is executed is approximately 300 milliseconds. As already explained in the first embodiment, in the reel control process (FIG. 22), when the acceleration period for reels 32L, 32M, and 32R ends (step S1002: YES), operation of stop buttons 42-44 is enabled. Also, as already explained in the first embodiment, in the reel control process (FIG. 22), if a stop command is issued for any of reels 32L, 32M, and 32R, a reel stop process (step S1012) is executed to stop the rotation of reels 32L, 32M, and 32R when the symbol number of the arrival symbol on reels 32L, 32M, and 32R to be stopped is equal to the symbol number of the stop symbol. In this reel stop process, a stopping excitation pulse is output to the reels 32L, 32M, and 32R that are to be stopped. Specifically, in a configuration in which one-phase excitation and two-phase excitation pulses are output during acceleration control and constant speed rotation control of reels 32L, 32M, and 32R, in the reel stop process (step S1012), a four-phase excitation pulse with weaker excitation force than the one-phase excitation and two-phase excitation is output as the stopping excitation pulse. The state in which the stopping excitation pulse is output continues for 100 interrupts (approximately 149 milliseconds) of the timer interrupt process (FIG. 11).

As already explained in the first embodiment, in the winning determination process (FIG. 26) executed in step S1015 of the reel control process (FIG. 22), if any of the small winning combinations is achieved (step S1204: YES), the information on the number of awards corresponding to that small winning combination is set in the award number counter 74e of the main RAM 74 (step S1205). When the information on the number of awards is set in the award number counter 74e, the port output process (FIG. 91) is executed, and the display of that number of awards begins on the combined display unit 66. When any of the small winning combinations is achieved in a game in which the combined display unit 66 does not perform stop order display, the display state of the combined display unit 66 changes in the following order: the combined display unit 66 displays the number of awards "00" → the combined display unit 66 is completely turned off → the combined display unit 66 displays the number of awards "00" → the combined display unit 66 displays the number of awards corresponding to the achieved small winning combination. Furthermore, in the winning determination process (FIG. 26), if no small win is achieved in a game in which the stop order corresponding display is not executed, the value of the award number counter 74e remains at "0", and the state in which the award number display of "00" is executed on the combined display unit 66 is maintained. In this way, if no small win is achieved in a game in which the stop order corresponding display is not executed on the combined display unit 66, the display state of the combined display unit 66 changes in the following order: a state in which the award number display of "00" is executed on the combined display unit 66 → a state in which the combined display unit 66 is fully turned off → a state in which the award number display of "00" is executed on the combined display unit 66.

Next, the lottery result response processing executed by the main MPU 72 will be explained with reference to the flowchart in Figure 94 (b). As already explained in the first embodiment above, the lottery result response processing is executed in step S914 of the role lottery processing (Figure 18).

In the lottery result processing, steps S5501 to S5506 are executed in the same manner as steps S1101 to S1106 in the lottery result processing in the first embodiment (FIG. 25). Specifically, if the current gaming state is the pseudo-bonus state ST4 (step S5501: YES) or the AT state ST5 (step S5502: YES), it is determined whether the value of the bet number setting counter 74b in the main RAM 74 is "3" (step S5503). If the value of the bet number setting counter 74b is "3" (step S5503: YES), i.e., if the number of bets in the current game is "3," it is determined whether any of the index values IV of "1" to "9" has been selected in the winning combination lottery processing (FIG. 18) by referencing the index value counter 74f in the main RAM 74 (step S5504).

If a positive judgment is made in step S5504, the value of the index value counter 74f is set to the stop order type counter 74m in the main RAM 74 (step S5505). By setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m in step S5505, the process for executing the stop order corresponding display on the dual-purpose display unit 66 in the next port output process (Figure 91) (the processes of steps S5403 to S5405 and step S5411) can be executed. By executing the process for executing the stop order corresponding display in the next port output process, the display content on the dual-purpose display unit 66 switches from the number display of "00" to the stop order corresponding display corresponding to one of the stop order type numbers "1" to "9" set in the stop order type counter 74m. The processing of step S5505 is processing for setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m and for switching from a state in which the number of awards is displayed on the dual-purpose display unit 66 to a state in which the stop order corresponding display is being displayed. Therefore, compared to a configuration in which, in addition to the processing of step S5505 for setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m, a separate processing is set for switching from a state in which the number of awards is displayed on the dual-purpose display unit 66 to a state in which the stop order corresponding display is being displayed, the processing configuration for setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m and for switching from a state in which the number of awards is displayed on the dual-purpose display unit 66 to a state in which the stop order corresponding display is being displayed can be simplified.

If a negative determination is made in step S5502, step S5503, or step S5504, i.e., if it is determined that stop order corresponding display will not be executed on the dual-purpose display unit 66, the value of the stop order type counter 74m is cleared to "0" (step S5506). As a result, the current game becomes a game in which stop order corresponding display on the dual-purpose display unit 66 and stop order notification on the image display device 63 are not executed.

Then, the award number counter 74e is set to the off data "255" (step S5507). This allows the process to be executed (steps S5401, S5402, and S5411) to turn the dual-purpose display unit 66 completely off during the next port output process (Figure 91). By executing the process to turn the dual-purpose display unit 66 completely off during the next port output process, the dual-purpose display unit 66 switches from a state in which the dual-purpose display unit 66 displays the award number "00" to a state in which the dual-purpose display unit 66 is completely off. The process of step S5507 sets the off data ("255") to the award number counter 74e and also switches from a state in which the dual-purpose display unit 66 displays the award number "00" to a state in which the dual-purpose display unit 66 is completely off. Therefore, compared to a configuration in which, in addition to the process of step S5507 in which the off data is set in the award count counter 74e, a separate process is set to switch from a state in which the dual-purpose display unit 66 is displaying the award count of "00" to a state in which the dual-purpose display unit 66 is completely off, the process configuration for setting the off data in the award count counter 74e and switching from a state in which the dual-purpose display unit 66 is displaying the award count of "00" to a state in which the dual-purpose display unit 66 is completely off can be simplified.

Then, the numerical information "221", which corresponds to the duration of the all-off state (approximately 330 milliseconds), is set in the off-time counter 74δ in the main RAM 74 (step S5508). This allows approximately 330 milliseconds to be set as the duration of the all-off time in the dual-purpose display unit 66. As described above, the value of the off-time counter 74δ is updated by subtracting 1 in the timer subtraction process (FIG. 95) described below, and becomes "0" approximately 330 milliseconds after the off data is set in the award number counter 74e. If the processing of step S5505 or step S5508 is performed, the start command flag provided in the main RAM 74 is set to "1" (step S5509), and this lottery result response process ends.

In this way, if the execution condition for the stop order corresponding display on the combined display unit 66 is not met (if a negative judgment is made in step S5502, step S5503, or step S5504), processing is executed to turn off all lights on the combined display unit 66 (processing of step S5507). On the other hand, if the execution condition for the stop order corresponding display on the combined display unit 66 is met (step S5501 or step S5502: YES, step S5503: YES, step S5504: YES), processing is not executed to turn off all lights on the combined display unit 66 (processing of step S5507), and processing is executed to execute the stop order corresponding display on the combined display unit 66 (processing of step S5505).

This configuration causes the combined display unit 66 to go into a fully extinguished state when the conditions for executing the stop order corresponding display on the combined display unit 66 are not met. As already explained, in the reel control process (Figure 22), operation of the stop buttons 42-44 is enabled based on the end of the acceleration period of the reels 32L, 32M, and 32R. If the combined display unit 66 were configured to go into a fully extinguished state regardless of whether or not the stop order corresponding display on the combined display unit 66 is displayed, and if the stop order corresponding display were to start at or before the timing at which operation of the stop buttons 42-44 is enabled, it would be necessary to end the fully extinguished state at or before the timing at which operation of the stop buttons 42-44 is enabled. In contrast, by configuring the dual-purpose display unit 66 to be fully unlit when the conditions for executing the stop order corresponding display on the dual-purpose display unit 66 are not met, it is possible to set the timing for ending the fully unlit state on the dual-purpose display unit 66 regardless of when the acceleration period of the reels 32L, 32M, and 32R ends and the operation of the stop buttons 42-44 becomes effective.

If the conditions for executing the stop order corresponding display are met (step S5501 or step S5502: YES, step S5503: YES, step S5504: YES), a stop order type number from "1" to "9" is set in the stop order type counter 74m (step S5505), and the process for executing the stop order corresponding display on the dual-purpose display unit 66 is executed during the next port output process (Figure 91). Then, when the next port output process is executed, the dual-purpose display unit 66 switches from a fully unlit state to a state in which the stop order corresponding display is being executed on the dual-purpose display unit 66. Therefore, in a game in which stop order-based display is executed on the dual-purpose display unit 66, even if the process for turning off all lights on the dual-purpose display unit 66 is not executed when acceleration control of reels 32L, 32M, and 32R begins, it is possible to prevent the dual-purpose display unit 66 from continuing to display "00" for the period from when a bet operation is performed or a medal is inserted until the win determination process (FIG. 26) is executed. This allows the display mode of the dual-purpose display unit 66 to change in a mode corresponding to the start of a game on the dual-purpose display unit 66.

Next, the timer decrement process executed by the main MPU 72 will be explained with reference to the flowchart in Figure 95. As already explained, the timer decrement process is executed in step S208 of the timer interrupt process (Figure 11).

In the timer subtraction process, if the value of the off-time counter 74δ (Figure 94(a)) in the main RAM 74 is "1" or greater (step S5601: YES), the value of the off-time counter 74δ is subtracted by 1 (step S5602), and it is determined whether the value of the off-time counter 74δ after the subtraction of 1 is "0" (step S5603).

If a positive judgment is made in step S5603, i.e., if the duration of the all-off state in the dual-purpose display unit 66 has ended, the value of the award number counter 74e is cleared to "0" (step S5604). As already explained, in the lottery result response processing (FIG. 94(b)), if it is determined that stop order corresponding display will not be executed in the dual-purpose display unit 66 (if a negative judgment is made in step S5502, step S5503, or step S5504), off data is set in the award number counter 74e (step S5507), and numerical information of "221", which corresponds to the duration of the all-off state, is set in the off time counter 74δ (step S5508). Therefore, the state in which a positive judgment is made in step S5601 is the state in which off data is set in the award number counter 74e. The processing of step S5604 is processing executed when the off data is set in the award number counter 74e. By clearing the value of the award number counter 74e to "0" in step S5604, the state in which the off data is set in the award number counter 74e can be ended, and the processing for executing the processing for displaying the award number of "00" on the dual-purpose display unit 66 (processing of steps S5409 to S5411) can be executed in the next port output processing (FIG. 91). By executing the processing for displaying the award number of "00" in the next port output processing, the dual-purpose display unit 66 switches from a state in which the dual-purpose display unit 66 is fully off to a state in which the dual-purpose display unit 66 is displaying the award number of "00". The processing of step S5604 is processing for clearing the off data set in the award number counter 74e, and processing for switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the dual-purpose display unit 66 is displaying the award number of "00". Therefore, compared to a configuration in which, in addition to the process of step S5604 for clearing the off data set in the award number counter 74e, a separate process is set for switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the award number display is being executed on the dual-purpose display unit 66, the process configuration for clearing the off data set in the award number counter 74e and switching from a state in which the dual-purpose display unit 66 is fully off to a state in which the award number display is being executed on the dual-purpose display unit 66 can be simplified. On the other hand, in a game in which stop order corresponding display is executed on the dual-purpose display unit 66, even if the value of the award number counter 74e is cleared to "0" in step S5604, the stop order type counter 74m remains set to one of "1" to "9," and therefore the state in which the stop order corresponding process is being executed on the dual-purpose display unit 66 continues.

If a negative judgment is made in step S5601, if a negative judgment is made in step S5603, or if the processing of step S5604 is performed, other timer decrement processing is performed (step S5605), and this timer decrement processing ends. In the other timer decrement processing (step S5605), the values of each counter and timer other than the light-off time counter are decremented.

In this way, in a game in which stop order corresponding display is not performed on the dual-purpose display unit 66, the light-off data set in the award number counter 74e is cleared when the value of the light-off time counter 74δ in the main RAM 74 becomes "0". Then, when the port output process (Figure 91) is executed with the light-off data set in the award number counter 74e cleared, the dual-purpose display unit 66 switches from a fully lighted state to a state in which the dual-purpose display unit 66 is displaying the award number of "00".

While the timing of the initial (first) stop command varies depending on the timing of the player's operation of the stop buttons 42-44, the timing of the end of the all-lights-out state is not affected by the timing of the first stop command. Therefore, the duration of the all-lights-out state can be fixed at approximately 330 milliseconds in all cases: when the first stop command is generated before approximately 330 milliseconds have elapsed since the numerical information ("221") corresponding to the duration of the all-lights-out state (approximately 330 milliseconds) is set in the off-time counter 74δ; when the first stop command is generated after approximately 330 milliseconds have elapsed since the numerical information corresponding to the duration of the all-lights-out state is set in the off-time counter 74δ; or when the first stop command is generated after approximately 330 milliseconds have elapsed since the numerical information corresponding to the duration of the all-lights-out state is set in the off-time counter 74δ. This prevents the duration of the all-lights-off state from being shortened due to the timing of the first stop command, and in either case, the dual-purpose display unit 66 can be turned off in a manner that can be recognized by players and amusement hall managers.

Next, we will explain, with reference to the time chart in Figure 96, how the dual-purpose display unit 66 becomes fully unlit in a game in which the dual-purpose display unit 66 does not display the stop order. Figure 96(a) shows the period during which the dual-purpose display unit 66 is in a fully off state, Figure 96(b) shows the period during which the award number display on the dual-purpose display unit 66 is being executed, Figure 96(c) shows the period during which the award number counter 74e is set to the off data "255", Figure 96(d) shows the acceleration period of reels 32L, 32M, and 32R, Figure 96(e) shows the timing when a bet operation or the first medal insertion is performed when a game is not being executed, Figure 96(f) shows the timing when the lottery result response processing (Figure 94(b)) is executed, Figure 96(g) shows the timing when operation of stop buttons 42 to 44 is enabled, Figure 96(h) shows the timing when stop control of the first reel ends, Figure 96(i) shows the timing when the prize determination processing (Figure 26) is executed at step S1015 of the reel control processing (Figure 22), and Figure 96(j) shows the timing when the port output processing (Figure 91) is executed. In this specification, stop control of the first reel refers to stop control of the reel for which the first (first) stop command is issued among the left reel 32L, center reel 32M, and right reel 32R.

When the value of the award number counter 74e is "0" and the combined display unit 66 is displaying the award number of "00", if a bet operation or the first medal is inserted as shown in Figure 96(e), the value of the award number counter 74e will remain at "0". Then, when the port output process is executed at the time of t2 as shown in Figure 96(j), the combined display unit 66 will continue to display the award number of "00" as shown in Figure 96(b).

Then, the game starts, and when the lottery result processing is executed at timing t3 as shown in Figure 96(f), light-off data ("255") is set in the award number counter 74e as shown in Figure 96(c). Then, as shown in Figure 96(d), an acceleration period for reels 32L, 32M, and 32R begins at timing t4. Then, when the port output processing is executed at timing t5 as shown in Figure 96(j), the state in which the award number display (displaying "00") is being executed on the dual-purpose display unit 66 switches to a state in which the dual-purpose display unit 66 is fully turned off as shown in Figures 96(a) and (b).

Then, at timing t6, the acceleration period of reels 32L, 32M, and 32R ends as shown in Figure 96(d), and operation of stop buttons 42-44 is enabled as shown in Figure 96(g). Then, at timing t7, when the duration of the fully unlit state of the dual-purpose display unit 66 (approximately 330 milliseconds) has elapsed, the value of the award number counter 74e is cleared to "0" as shown in Figure 96(c). This results in a state in which no unlit data is set in the award number counter 74e. Then, at timing t8, when the port output process is executed as shown in Figure 96(j), the dual-purpose display unit 66 switches from a fully unlit state to a state in which the dual-purpose display unit 66 is displaying the award number (displaying "00") as shown in Figures 96(a) and (b). The period during which the light-off data is set in the award number counter 74e (approximately 330 milliseconds) is approximately 30 milliseconds longer than the acceleration period (approximately 300 milliseconds) of the reels 32L, 32M, and 32R. Although the process of setting the light-off data in the award number counter 74e (the process of step S5507 in the lottery result response process (FIG. 94(b))) is executed followed by the process of executing acceleration control of the reels 32L, 32M, and 32R (the process of step S1001 in the reel control process (FIG. 22)), the difference (approximately 30 milliseconds) between the period during which the light-off data is set in the award number counter 74e and the acceleration period of the reels 32L, 32M, and 32R is longer than the period from the timing t3 when the process of setting the light-off data in the award number counter 74e is executed to the timing t4 when the acceleration control of the reels 32L, 32M, and 32R is started. Therefore, after the acceleration control of reels 32L, 32M, and 32R ends, the state in which the light-off data is set in the award number counter 74e ends.

Then, as shown in Figure 96(h), the stop control of the first reel ends at t9. As previously explained, the stop control of each reel 32L, 32M, and 32R requires at least approximately 149 milliseconds (the period during which four-phase excitation pulses are output). The total period (at least approximately 449 milliseconds) of the acceleration period of reels 32L, 32M, and 32R (approximately 300 milliseconds) and the period required for the stop control of the first reel (at least approximately 149 milliseconds) is longer than the total period (maximum approximately 331.5 milliseconds) during which the light-off data is set in the award number counter 74e and the period from the end of that period until the port output process is executed (maximum approximately 1.49 milliseconds). Furthermore, the timing of t4, when the acceleration control of reels 32L, 32M, and 32R begins, is later than the timing of t3, when the light-off data is set in the award number counter 74e. Therefore, the timing t8 when the fully unlit state of the dual-purpose display unit 66 ends occurs before the timing t9 when the stop control of the first reel ends.

Then, as shown in FIG. 96(i), the winning determination process (FIG. 26) is executed at timing t10. As described above, the stop control of the first reel ends at timing t8, when the dual-purpose display unit 66 finishes its fully turned-off state and starts displaying the number of winnings "00" on the dual-purpose display unit 66. Then, between timing t9, when the stop control of the first reel ends, and timing t10, when the winning determination process determines whether a small winning combination has been achieved, stop control of the second and third reels is executed. In this specification, stop control of the second reel refers to stop control of the reel among the left reel 32L, center reel 32M, and right reel 32R for which the second stop command has been issued, and stop control of the third reel refers to stop control of the reel among the left reel 32L, center reel 32M, and right reel 32R for which the last (third) stop command has been issued. The total period during which stop control is executed for the second reel (approximately 149 milliseconds) and the period during which stop control is executed for the third reel (approximately 149 milliseconds) is approximately 298 milliseconds. Therefore, the time during which the number of awards displayed on the dual-purpose display unit 66 to display "00" after the all-lights-out state ends can be at least the total period (approximately 298 milliseconds) during which stop control is executed for the second reel (approximately 149 milliseconds) and the period during which stop control is executed for the third reel (approximately 149 milliseconds). This makes it easier for players and amusement hall managers to understand the number of awards displayed to display "00".

As shown in Figure 96(i), if the winning determination process executed at timing t10 determines that no small winning combinations have been achieved, the value of the award number counter 74e will remain at "0". Even if the port output process is then executed at timing t11 as shown in Figure 96(j), the award number display of "00" will continue to be executed on the dual-purpose display unit 66 as shown in Figure 96(b).

As described above, from the time a bet is made or a medal is inserted until the lottery result processing (Figure 94 (b)) is executed (from timing t1 to timing t3), the dual-purpose display unit 66 displays the number of awards "00." If the stop order corresponding display is not executed, the dual-purpose display unit 66 temporarily goes into a fully unlit state when the acceleration control of reels 32L, 32M, and 32R begins. From the time this fully unlit state ends until the winning determination processing (Figure 26) is executed (from timing t8 to timing t10), the dual-purpose display unit 66 displays the number of awards "00." In this way, if no small winning combination is achieved in a game in which the stop order corresponding display is not executed on the dual-purpose display unit 66, the display state of the dual-purpose display unit 66 changes in the following order: a state in which the dual-purpose display unit 66 displays the number of awards "00" → a state in which the dual-purpose display unit 66 is fully unlit → a state in which the dual-purpose display unit 66 displays the number of awards "00." In a configuration in which the dual-purpose display unit 66 displays the number of awards "00" upon a bet operation or medal insertion, and the win determination process (FIG. 26) is executed with the dual-purpose display unit 66 displaying the number of awards "00," by temporarily turning off the dual-purpose display unit 66 when acceleration control of reels 32L, 32M, and 32R begins, it is possible to prevent the dual-purpose display unit 66 from continuing to display the number of awards "00" for the period from when a bet operation or medal insertion is performed until the win determination process (FIG. 26) is executed. This allows the display mode of the dual-purpose display unit 66 to change in a mode corresponding to the start of a game even in which the dual-purpose display unit 66 does not display a stop order corresponding to the game.

The time t8, when the combined display unit 66 ends its fully off state, is later than the time t6, when the acceleration period of the reels 32L, 32M, and 32R ends and the operation of the stop buttons 42-44 becomes valid. Therefore, the period during which the combined display unit 66 remains fully off can be set longer, compared to a configuration in which the combined display unit 66 ends its fully off state at or before the time the operation of the stop buttons 42-44 becomes valid. This makes it easier for players and amusement hall managers to understand the fully off state of the combined display unit 66.

In a configuration in which the all-lights-off state of the dual-purpose display unit 66 ends at a timing (t8) later than the timing (t6) when the operation of the stop buttons 42-44 is enabled, the all-lights-off state ends at a timing (t8) earlier than the timing (t9) when the stop control of the first reel ends. Therefore, the time for which the combined display unit 66 displays the number of awards "00" after the all-lights-off state ends can be at least the total period (approximately 298 milliseconds) during which the stop control of the second reel is executed (approximately 149 milliseconds) and the stop control of the third reel is executed (approximately 149 milliseconds). This makes it easier for players and amusement hall managers to understand the number of awards "00" displayed.

The fully off state of the dual-purpose display unit 66 ends after the operation of the stop buttons 42-44 is enabled and before the stop control of the first reel ends. Therefore, in a game in which the dual-purpose display unit 66 does not perform stop order display, the dual-purpose display unit 66 can be made to be in a fully off state, and the dual-purpose display unit 66 can be made to display the number of awards as "00" from the time the fully off state ends until the winning determination process (Figure 26) is performed, in a manner that is recognizable to players and amusement hall managers.

The present embodiment described above provides the following excellent effects:

In a game in which the dual-purpose display unit 66 does not display the number of awards corresponding to the stop order, the dual-purpose display unit 66 displays "00" when a bet is made or a medal is inserted, and the winning determination process (FIG. 26) is executed with the number of awards displayed as "00" on the dual-purpose display unit 66. By temporarily turning off the dual-purpose display unit 66 when acceleration control of reels 32L, 32M, and 32R begins, it is possible to prevent the dual-purpose display unit 66 from continuing to display "00" for the period from when a bet is made or a medal is inserted until the winning determination process (FIG. 26) is executed. This allows the display mode of the dual-purpose display unit 66 to change in a manner corresponding to the start of the game in a game in which the dual-purpose display unit 66 does not display the number of awards corresponding to the stop order.

The process for temporarily turning the dual-purpose display unit 66 off (the process of step S5507) is executed when it is determined that the stop order display is not being executed on the dual-purpose display unit 66. Therefore, the timing for ending the off-state can be set independently of the timing at which the acceleration period of the reels 32L, 32M, and 32R ends and the operation of the stop buttons 42-44 is enabled. By configuring the dual-purpose display unit 66 to end its off-state after the operation of the stop buttons 42-44 is enabled, the period during which the dual-purpose display unit 66 remains off can be set longer than when the dual-purpose display unit 66 ends its off-state before the operation of the stop buttons 42-44 is enabled. This makes it easier for players and amusement hall managers to understand the off-state of the dual-purpose display unit 66.

In a configuration in which the all-lights-off state of the dual-purpose display unit 66 ends after the operation of the stop buttons 42-44 is enabled, the all-lights-off state ends before the stop control of the first reel ends. Therefore, the time during which the combined display unit 66 displays the number of awards "00" after the all-lights-off state ends can be at least the total period (approximately 298 milliseconds) during which the stop control of the second reel is executed (approximately 149 milliseconds) and the stop control of the third reel is executed (approximately 149 milliseconds). This makes it easier for players and amusement hall managers to understand the "00" display of the number of awards.

The fully off state of the dual-purpose display unit 66 ends after the operation of the stop buttons 42-44 is enabled and before the stop control of the first reel ends. Therefore, in a game in which the dual-purpose display unit 66 does not perform stop order display, the dual-purpose display unit 66 can be made to be in a fully off state, and the dual-purpose display unit 66 can be made to display the number of awards as "00" from the time the fully off state ends until the winning determination process (Figure 26) is performed, in a manner that is recognizable to players and amusement hall managers.

The process for turning off the dual-purpose display unit 66 when acceleration control of reels 32L, 32M, and 32R begins (the process of step S5507) is executed in games in which stop order display is not executed on the dual-purpose display unit 66, but is not executed in games in which stop order display is executed. In games in which stop order display is executed, a stop order type number between "1" and "9" is set in the stop order type counter 74m based on the results of the role lottery process (Figure 18) and a port output process (Figure 28) is executed prior to the activation of stop buttons 42-44. This switches the dual-purpose display unit 66 from displaying the number of awards "00" to displaying the stop order type number corresponding to that stop order type number on the dual-purpose display unit 66. Therefore, in a game in which stop order-based display is executed, even if the process for turning off the dual-purpose display unit 66 is not executed when acceleration control of reels 32L, 32M, and 32R begins, it is possible to prevent the dual-purpose display unit 66 from continuing to display "00" for the period from when a bet operation is performed or a medal is inserted until the win determination process (FIG. 26) is executed. This makes it possible to change the display mode of the dual-purpose display unit 66 at the start of the game in a mode that corresponds to the start of the game.

Ninth Embodiment
This embodiment differs from the first embodiment in that in a game in which the stop order corresponding display is not performed, the dual-purpose display unit 66 displays a non-guiding display indicating that the stop order corresponding display is not performed. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 97(a) is an explanatory diagram illustrating the display mode of the non-guiding display on the combined display unit 66. As shown in Figure 97(a), in the non-guiding display, the right-hand seven-segment display 66b displays a display indicating that the game does not perform stop order corresponding display, and the left-hand seven-segment display 66a is in a non-display state. In this way, by configuring the combined display unit 66 to display a non-guiding display for a game in which stop order corresponding display is not performed on the combined display unit 66, it is possible to easily identify that the game does not perform stop order corresponding display based on the display on the combined display unit 66.

As already explained in the first embodiment above, the main ROM 73 stores a stop order corresponding display data table 73a, which contains display data for stop order corresponding display corresponding to the stop order type numbers "1" through "9." In this embodiment, the stop order corresponding display data table 73a also contains display data for non-guiding display corresponding to the non-guiding data of "10." When the main MPU 72 performs a non-guiding display on the dual-purpose display unit 66, it reads the stop order corresponding display data table 73a, sets the display data for non-guiding display in the right-side dual-purpose display display area 74q, and sets non-display data in the left-side dual-purpose display display area 74p. The display data and non-display data set in the dual-purpose display display areas 74p and 74q are output to the dual-purpose display unit 66, thereby performing a non-guiding display on the dual-purpose display unit 66.

Figure 97(b) is an explanatory diagram illustrating the conditions under which the dual-purpose display unit 66 executes the non-guiding display, the stop order display, the ratio display, and the number of awards display. As shown in Figure 97(b), while a game is being played, the dual-purpose display unit 66 is in one of the following states: non-guiding display, stop order display, and number of awards display; and while a game is not being played, it is in the ratio display or number of awards display. Here, a period during which a game is being played is a period during which the in-game flag in the main RAM 74 is set to "1," and a period during which a game is not being played is a period during which the value of the in-game flag is "0."

While a game is being played, non-guiding display is performed on the dual-purpose display unit 66, provided that the non-guiding data "10" is set in the stop order type counter 74m in the main RAM 74. The non-guiding data is set in the stop order type counter 74m when it is determined in the lottery result response process (FIG. 97(c)) described below that the game is one in which stop order corresponding display is not performed on the dual-purpose display unit 66. While a game is being played, stop order corresponding display is performed on the dual-purpose display unit 66, provided that a stop order type number between "1" and "9" is set in the stop order type counter 74m in the main RAM 74. As already explained in the first embodiment above, the stop order type counter 74m is cleared to "0" in step S1208 of the prize determination process (FIG. 26). As a result, if a non-guiding display was being executed on the dual-purpose display unit 66, the non-guiding display will end and the display of the number of awards will begin, and if a stop order corresponding display was being executed on the dual-purpose display unit 66, the stop order corresponding display will end and the display of the number of awards will begin.

When a game is not being played, the ratio display is executed on the dual-purpose display unit 66, provided that the ratio display counter 74n is set to any calculation result data between "0" and "100." Whether a game is being played or not, the number of awards is displayed on the dual-purpose display unit 66, provided that the stop order type counter 74m is not set to a stop order type number between "1" and "9" and the non-guiding data of "10" is not set, and the ratio display counter 74n is not set to any calculation result data between "0" and "100."

The period during which the stop order type counter 74m is set to a stop order type number between "1" and "9" or non-guidance data of "10" occurs and ends while the game is being played. On the other hand, as already explained in the first embodiment above, the ratio display counter 74n is set to calculation result data between "0" and "100" when the ratio display start operation is performed while the game is not being played. Therefore, there is no overlap between a state in which the stop order type counter 74m is set to a stop order type number between "1" and "9" or non-guidance data of "10" and a state in which the ratio display counter 74n is set to calculation result data between "0" and "100".

As described above, the main MPU 72 causes the combined display unit 66 to display the stop order corresponding display when a stop order type number between "1" and "9" is set in the stop order type counter 74m, and causes the combined display unit 66 to display the non-guiding data when the non-guiding data "10" is set in the stop order type counter 74m. The stop order type counter 74m is a counter into which a stop order type number between "1" and "9" is set, and into which non-guiding data ("10") for executing the non-guiding display on the combined display unit 66 is set. Therefore, compared to a configuration in which the main RAM 74 includes a flag or the like in the main RAM 74 that enables the main MPU 72 to determine when the combined display unit 66 should display the non-guiding display in addition to the stop order type counter 74m in which the stop order type number is set, the data capacity of the storage area provided in the main RAM 74 for executing the non-guiding display on the combined display unit 66 can be reduced.

As described above, if the conditions for executing the stop order display on the dual-purpose display unit 66 are not met, a non-guiding display is executed on the dual-purpose display unit 66 when acceleration control of reels 32L, 32M, and 32R begins. As with the seventh embodiment above, if the previous game ends without a small winning combination being achieved, the value of the award number counter 74e becomes "0" and the dual-purpose display unit 66 displays the award number of "00" corresponding to the value of the award number counter 74e. Thereafter, even if a bet operation or medal insertion is performed to start the game, the value of the award number counter 74e remains "0", and the dual-purpose display unit 66 continues to display the award number of "00" corresponding to the value of the award number counter 74e. In a game in which the stop order corresponding display is not executed on the combined display unit 66, if the display mode of the combined display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), when a small winning combination is not achieved in the game, the value of the award number counter 74e continues to be "0", and the award number display of "00" corresponding to the value of the award number counter 74e continues on the combined display unit 66. In this way, in a game in which the stop order corresponding display is not executed on the combined display unit 66, if the display mode of the combined display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), the state in which "00" is displayed on the combined display unit 66 continues from before the game starts to the end of the game, and there are cases in which it is not possible to know that the game has started based on the display on the combined display unit 66. In contrast, if the conditions for executing the stop order corresponding display on the dual-purpose display unit 66 are not met, the dual-purpose display unit 66 is configured to execute a non-guiding display when acceleration control of reels 32L, 32M, and 32R begins. This prevents the dual-purpose display unit 66 from continuing to display "00" for the period from when a bet operation is performed or a medal is inserted until the win determination process (FIG. 26) is executed. This makes it possible to know that a game has started based on the display mode of the dual-purpose display unit 66, even in games where the stop order corresponding display on the dual-purpose display unit 66 is not executed.

As already explained in the first embodiment above, in a game in which a stop order corresponding display is executed, the stop order corresponding display is executed on the dual-purpose display unit 66 at a timing before the acceleration control of reels 32L, 32M, and 32R is initiated. As a result, the display content on the dual-purpose display unit 66 switches from the award number display of "00" to a stop order corresponding display corresponding to one of the stop order type numbers "1" to "9" set in the stop order type counter 74m. Therefore, in a game in which a stop order corresponding display is executed on the dual-purpose display unit 66, it is possible to prevent the dual-purpose display unit 66 from continuing to display "00" for the period from when a bet operation or medal insertion is performed until the execution of the win determination process (Figure 26). This makes it possible to know that a game has started based on the display mode of the dual-purpose display unit 66.

Figure 97 (c) is a flowchart showing the lottery result response processing executed by the main MPU 72. As already explained in the first embodiment above, the lottery result response processing is executed in step S914 of the role lottery processing (Figure 18).

In the lottery result processing, steps S5701 to S5705 are executed in the same manner as steps S1101 to S1105 of the lottery result processing in the first embodiment (FIG. 25). Specifically, if the current gaming state is the pseudo-bonus state ST4 (step S5701: YES) or the AT state ST5 (step S5702: YES), it is determined whether the value of the bet number setting counter 74b in the main RAM 74 is "3" (step S5703). If the value of the bet number setting counter 74b is "3" (step S5703: YES), i.e., if the number of bets in the current game is "3," it is determined whether any of the index values IV of "1" to "9" has been selected in the winning combination lottery processing (FIG. 18) by referencing the index value counter 74f in the main RAM 74 (step S5704).

If a positive judgment is made in step S5704, the value of the index value counter 74f is set to the stop order type counter 74m in the main RAM 74 (step S5705). This enables the dual-purpose display unit 66 to be in a state where processing for displaying the stop order correspondence is executed in the next port output process (Figure 98). By executing processing for displaying the stop order correspondence in the next port output process, the dual-purpose display unit 66 switches from displaying the number of awards "00" to displaying the stop order correspondence. The processing in step S5705 sets the stop order type counter 74m to one of "1" to "9" as a stop order type number, and also switches the dual-purpose display unit 66 from displaying the number of awards to displaying the stop order correspondence. Therefore, compared to a configuration in which, in addition to the process of step S5705, setting a stop order type number from "1" to "9" in the stop order type counter 74m, a separate process is set for switching the combined display unit 66 from a state in which the number of awards is displayed to a state in which the stop order correspondence display is displayed, the process configuration for setting a stop order type number from "1" to "9" in the stop order type counter 74m and switching the combined display unit 66 from a state in which the number of awards is displayed to a state in which the stop order correspondence display is displayed can be simplified. As already explained with reference to FIG. 24(b) in the first embodiment above, when the index value IV of "n" (where "n" is an integer from "1" to "9") is won in the lottery process (FIG. 18) for a game in which the pseudo bonus state ST4 or the AT state ST5 and the bet amount is "3," "n" is set in the stop order type counter 74m. As a result, the display content of the stop order correspondence display in the combined display unit 66 becomes the nth stop order correspondence display.

If a negative judgment is made in step S5702, step S5703, or step S5704, the stop order type counter 74m is set to "10," which is non-indicative data for displaying a non-indicative display on the combined display unit 66 (step S5706). This allows the combined display unit 66 to be placed in a state where processing for displaying a non-indicative display is executed in the next port output process (Figure 98). By executing processing for displaying a non-indicative display in the next port output process, the combined display unit 66 can be switched from a state in which the number of awards displayed as "00" is being displayed to a state in which a non-indicative display is being executed. The processing of step S5706 sets the non-indicative data of "10" to the stop order type counter 74m and also switches the combined display unit 66 from a state in which the number of awards displayed is being displayed to a state in which a non-indicative display is being executed. Therefore, compared to a configuration in which, in addition to the process of step S5706 in which non-guiding data "10" is set in the stop order type counter 74m, a separate process is set to switch the combined display unit 66 from a state in which the number of awards is displayed to a state in which the non-guiding display is displayed, the process configuration for setting non-guiding data in the stop order type counter 74m and switching the combined display unit 66 from a state in which the number of awards is displayed to a state in which the non-guiding display is displayed can be simplified.

If step S5705 or step S5706 is performed, the start command flag in the main RAM 74 is set to "1" (step S5707), similar to step S1107 of the lottery result response processing (Figure 25) in the first embodiment described above, and the lottery result response processing is terminated.

In this way, in a game in which the stop order corresponding display is executed on the combined display unit 66, a stop order type number between "1" and "9" is set in the stop order type counter 74m before the acceleration control of reels 32L, 32M, and 32R begins, thereby causing the combined display unit 66 to be in a state where processing is executed to execute the stop order corresponding display in the next port output process. In addition, in a game in which the stop order corresponding display is not executed on the combined display unit 66, non-guiding data of "10" is set in the stop order type counter 74m before the acceleration control of reels 32L, 32M, and 32R begins, thereby causing the combined display unit 66 to be in a state where processing is executed to execute the non-guiding display in the next port output process.

In a game in which a stop order corresponding display is executed, the stop order corresponding display is executed on the dual-purpose display unit 66 based on the stop order type number being set in the stop order type counter 74m, and a process of clearing the value of the stop order type counter 74m to "0" (the process of step S1208 in the prize determination process (FIG. 26)) is executed to end the stop order corresponding display. In a game in which a stop order corresponding display is executed, the non-guiding display is executed on the dual-purpose display unit 66 based on the non-guiding data being set in the stop order type counter 74m, and a process of clearing the value of the stop order type counter 74m to "0" (the process of step S1208 in the prize determination process (FIG. 26)) is executed to end the non-guiding display. The process of step S1208 in the prize determination process (FIG. 26) is executed to end the stop order corresponding display in a game in which a stop order corresponding display is executed, and is executed to end the non-guiding display in a game in which a stop order corresponding display is not executed. This simplifies the processing configuration for ending the stop order corresponding display and the non-guiding display compared to a configuration in which the processing for ending the non-guiding display is set as a separate processing from the processing for ending the stop order corresponding display.

Next, the port output processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 98. As already explained in the first embodiment above, the port output processing is executed in step S211 of the timer interrupt processing (Figure 11).

In the port output process, similar to step S1401 in the port output process (Figure 28) in the first embodiment described above, it is first determined whether a stop order type number between "1" and "9" is set in the stop order type counter 74m in the main RAM 74 (step S5801). If a stop order type number between "1" and "9" is not set in the stop order type counter 74m (step S5801: NO), it is determined whether the non-guidance data "10" is set in the stop order type counter 74m in the main RAM 74 (step S5802).

If a stop order type number between "1" and "9" is set in the stop order type counter 74m (step S5801: YES), or if non-guidance data is set in the stop order type counter 74m (step S5802: YES), the stop order display data table 73a stored in the main ROM 73 is read (step S5803), and the read stop order display data table 73a is referenced to set the display data corresponding to the value of the stop order type counter 74m in the dual-purpose display area 74p, 74q (step S5804). In step S5804, if a stop order type number between "1" and "9" is set in the stop order type counter 74m, the display data corresponding to the value of the stop order type counter 74m is set in the right-side dual-purpose display area 74q, and non-display data is set in the left-side dual-purpose display area 74p. The display data and non-display data set in the combined display area 74p, 74q are output to the combined display unit 66 in step S5810, which will be described later, thereby enabling the combined display unit 66 to perform stop order corresponding display. Furthermore, if the non-guiding data "10" is set in the stop order type counter 74m, display data for non-guiding display is set in the right combined display area 74q, and non-display data is set in the left combined display area 74p. The display data and non-display data set in the combined display area 74p, 74q are output to the combined display unit 66 in step S5810, which will be described later, thereby enabling the combined display unit 66 to perform non-guiding display.

Steps S5805 through S5812 are similar to steps S1404 through S1411 of the port output process ( FIG. 28 ) in the first embodiment. Specifically, after a negative determination is made in step S5802, if calculation result data between "0" and "100" is set in the ratio display counter 74n (step S5805: YES), the numeric display data table 73b stored in the main ROM 73 is read (step S5806). Then, by referencing the numeric display data table 73b read in step S5806, display data corresponding to the value of the ratio display counter 74n is set in the left-side dual-purpose display display area 74p and the right-side dual-purpose display display area 74q (step S5807). The display data set in the dual-purpose display display areas 74p and 74q is output to the dual-purpose display unit 66 in step S5810, described below, allowing the dual-purpose display unit 66 to display the ratio.

If the stop order type counter 74m is not set to a stop order type number between "1" and "9" and the non-guidance data is not set (step S5801: NO, step S5802: NO), and the ratio display counter 74n is not set to a calculation result data between "0" and "100" (step S5805: NO), processing is performed to display the number of awards on the dual-purpose display unit 66 (processing of steps S5808 to S5809). Specifically, as in step S5806, the numeric display data table 73b stored in the main ROM 73 is read (step S5808), and the read numeric display data table 73b is referenced to set the display data corresponding to the value of the number of awards counter 74e in the left-side dual-purpose display unit display area 74p and the right-side dual-purpose display unit display area 74q (step S5809). This display data set in the dual-purpose display area 74p, 74q is output to the dual-purpose display unit 66 in step S5810, which will be described later, allowing the number of points awarded to be displayed on the dual-purpose display unit 66.

If step S5804, step S5807, or step S5809 is performed, the data (display data or non-display data) set in the left-side shared display area 74p and the right-side shared display area 74q is output to the shared display unit 66 (step S5810). As a result, if non-display data is set in the left-side shared display area 74p and display data for stop order corresponding display is set in the right-side shared display area 74q, stop order corresponding display is executed in the shared display unit 66. Furthermore, if non-display data is set in the left-side shared display area 74p and display data for non-guiding display is set in the right-side shared display area 74q, non-guiding display is executed in the shared display unit 66. Furthermore, if non-display data or display data for ratio display is set in the left-side shared display area 74p and display data for ratio display is set in the right-side shared display area 74q, ratio display is executed in the shared display unit 66. In addition, if display data for displaying the number of points awarded is set in the dual-purpose display area 74p, 74q, the number of points awarded will be displayed on the dual-purpose display 66.

Then, display control processing of the credit display unit 65 is executed (step S5811), other port output processing is executed (step S5812), and this port output processing ends. In the other port output processing in step S5812, data corresponding to the I/O device is output from the input/output port.

Next, the manner in which non-guiding displays are executed on the dual-purpose display unit 66 will be described with reference to the time chart in Figure 99. Figure 99(a) shows the period during which non-guiding displays are executed on the dual-purpose display unit 66, Figure 99(b) shows the period during which the awarded number display of "00" is executed on the dual-purpose display unit 66, Figure 99(c) shows the period during which the non-guiding data "10" is set in the stop order type counter 74m, Figure 99(d) shows the timing when a bet operation or the first medal insertion is performed when no game is being played, Figure 99(e) shows the timing when a game starts, Figure 99(f) shows the timing when operation of the stop buttons 42 to 44 is enabled, Figure 99(g) shows the timing when the winning determination process (Figure 26) is executed, and Figure 99(h) shows the timing when the port output process (Figure 98) is executed.

When the value of the award number counter 74e is "0" and the combined display unit 66 is displaying the award number of "00", if a bet operation or the first medal is inserted as shown in Figure 99(d), the value of the award number counter 74e will remain at "0". Then, when the port output process is executed at the time of t2 as shown in Figure 99(h), the combined display unit 66 will continue to display the award number of "00" as shown in Figure 99(b).

Then, as shown in Figure 99(e), the game starts at timing t3. Then, as shown in Figure 99(c), the non-guiding data "10" is set in the stop order type counter 74m at timing t4. Then, as shown in Figure 99(h), the port output process is executed at timing t5, and the display content of the dual-purpose display unit 66 changes from the awarded number display of "00" to a non-guiding display as shown in Figures 99(a) and (b). Then, at timing t6, operation of the stop buttons 42 to 44 is enabled as shown in Figure 99(f).

Then, at timing t7, the winning determination process (FIG. 26) is executed as shown in FIG. 99(g), and if it is determined in the winning determination process that no small winning combinations have been achieved, the value of the award number counter 74e remains at "0". Also, at timing t7, as shown in FIG. 99(c), step S1208 of the winning determination process (FIG. 26) is executed, clearing the value of the stop order type counter 74m to "0". Then, at timing t8, the port output process is executed as shown in FIG. 99(h), and the display content on the dual-purpose display unit 66 switches from the non-guiding display to the award number display of "00" as shown in FIGS. 99(a) and (b).

As described above, the dual-purpose display unit 66 displays the number of awards "00" in response to a bet operation or medal insertion, and the win determination process (FIG. 26) is executed while the dual-purpose display unit 66 displays the number of awards "00." In a game in which the dual-purpose display unit 66 does not display the stop order corresponding display, a process for displaying a non-guiding display on the dual-purpose display unit 66 (a process for setting non-guiding data in the stop order type counter 74m) is executed at timing t4, which is before the acceleration control of reels 32L, 32M, and 32R is initiated. This prevents the dual-purpose display unit 66 from continuing to display the number of awards "00" for the period from when the bet operation or medal insertion is performed until the win determination process (FIG. 26) is executed. Therefore, even in a game in which the dual-purpose display unit 66 does not display the stop order corresponding display, it is possible to know that the game has started based on the display mode of the dual-purpose display unit 66.

The present embodiment described above provides the following excellent effects:

In a configuration in which the combined display unit 66 displays the number of awards "00" based on a bet operation or medal insertion, and the win determination process (FIG. 26) is executed while the combined display unit 66 displays the number of awards "00," in games in which the combined display unit 66 does not display the stop order corresponding to the reels, a non-guiding display is executed on the combined display unit 66 when acceleration control of the reels 32L, 32M, and 32R begins. This prevents the combined display unit 66 from continuing to display the number of awards "00" for the period from when the bet operation or medal insertion is performed until the win determination process (FIG. 26) is executed. Therefore, even in games in which the combined display unit 66 does not display the stop order corresponding to the reels, it is possible to know that the game has started based on the display mode of the combined display unit 66.

When a stop order type number between "1" and "9" is set in the stop order type counter 74m, the main MPU 72 causes the combined display unit 66 to display the corresponding stop order. Also, when the non-guiding data "10" is set in the stop order type counter 74m, the main MPU 72 causes the combined display unit 66 to display the non-guiding order. The stop order type counter 74m is a counter into which a stop order type number between "1" and "9" is set, and into which non-guiding data for displaying the non-guiding order on the combined display unit 66 is set. Therefore, compared to a configuration in which the main RAM 74 includes a flag or the like in the main RAM 74 that enables the main MPU 72 to determine when the non-guiding order should be displayed on the combined display unit 66, in addition to the stop order type counter 74m into which the stop order type number is set, the data capacity of the storage area provided in the main RAM 74 for displaying the non-guiding order on the combined display unit 66 can be reduced.

In a game in which a stop order corresponding display is executed, the stop order corresponding display is executed on the dual-purpose display unit 66 based on the stop order type number being set in the stop order type counter 74m, and a process of clearing the value of the stop order type counter 74m to "0" (the process of step S1208 in the prize determination process (FIG. 26)) is executed to end the stop order corresponding display. In a game in which a stop order corresponding display is executed, the non-guiding display is executed on the dual-purpose display unit 66 based on the non-guiding data being set in the stop order type counter 74m, and a process of clearing the value of the stop order type counter 74m to "0" (the process of step S1208 in the prize determination process (FIG. 26)) is executed to end the non-guiding display. The process of step S1208 in the prize determination process (FIG. 26) is executed to end the stop order corresponding display in a game in which a stop order corresponding display is executed, and is executed to end the non-guiding display in a game in which a stop order corresponding display is not executed. This simplifies the processing configuration for ending the stop order corresponding display and the non-guiding display compared to a configuration in which the processing for ending the non-guiding display is set as a separate processing from the processing for ending the stop order corresponding display.

For games in which stop order corresponding display is not performed on the dual-purpose display unit 66, the dual-purpose display unit 66 is configured to display non-guiding information, making it easier to identify that the game does not display stop order corresponding display based on the display on the dual-purpose display unit 66.

Tenth Embodiment
In this embodiment, the processing content of the start-time addition process and the program content for executing the start-time addition process differ from those of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

As already explained in the first embodiment above, the main MPU 72 executes the start-time addition process in step S2310 in the advantageous state process at the start of the game (Figure 40). As in the first embodiment above, the start-time addition process is executed in AT state ST5. In the start-time addition process in this embodiment, if the index value IV ("11") in which the first watermelon winning data is set, the index value IV ("12") in which the second watermelon winning data is set, the index value IV ("14") in which the first chance replay winning data is set, or the index value IV ("15") in which the second chance replay winning data is set is selected in the role lottery process (Figure 18), the first add-on lottery table 73d (Figure 43(a)) is selected as the lottery table to be referenced in the add-on lottery. Furthermore, if the index value IV ("13") for which cherry winning data is set is won in the role lottery process (Figure 18), the second additional lottery table 73e (Figure 43(b)), which is more advantageous to the player than the first additional lottery table 73d, is selected as the lottery table to be referenced in the additional lottery.

Figure 100 is an explanatory diagram of the program contents of the start-up bonus processing executed by the main MPU 72. As already explained in the first embodiment above, the start-up bonus processing is executed in step S2310 of the advantageous state processing at the start of the game (Figure 40). As shown in Figure 100, this program has line numbers "1401" to "1409" set. Program commands are executed in order from lowest to highest line number, except when a call command or jump command is executed.

Lines "1401" to "1405" contain the same instructions as lines "1301" to "1305" in the program for the start-up addition processing in the first embodiment (Figure 69(b)). Specifically, line "1401" contains the instruction "LD A, (INDXCNT)." "LD" is the LD instruction as an instruction to transfer 8-bit data, "A" is the A register 101b, and "(INDXCNT)" specifies the index value counter 74f in the main RAM 74 as the transfer source. Execution of the instruction "LD A, (INDXCNT)" on line "1401" transfers the data in the index value counter 74f to the A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in A register 101b, and if no index value IV is selected in the role selection process (Figure 18), "0" is set in A register 101b.

The instruction "SUB A, 0BH" is set in line number "1402." "SUB" is a SUB instruction that subtracts 8-bit data, "A" is the A register 101b, and "0BH" is one byte of numerical information representing "11." As previously explained, "11" is the minimum value of the first lottery target range, "11" to "15." By executing the instruction "SUB A, 0BH" in line number "1402," an operation is performed to subtract "11" from the value in A register 101b, and the result of this operation is written to A register 101b. If a borrow to the most significant bit (the seventh bit) occurs in this operation, the carry flag CF is set to "1." If a borrow to the most significant bit (the seventh bit) does not occur in this operation, the value of the carry flag CF is set to "0." As already explained in the first embodiment with reference to Figure 69 (a), if the value of the index value counter 74f is within the first lottery target range of "11" to "15", the value of the A register 101b will be less than "5", and if the value of the index value counter 74f is not within the first lottery target range of "11" to "15", the value of the A register 101b will be greater than or equal to "5".

The instruction "CP A, 05H" is set in line number "1403." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "05H" is one byte of numerical information representing "5." Execution of the instruction "CP A, 05H" in line number "1403" results in an operation to subtract "5" from the value of A register 101b. As already explained in the first embodiment above, when the CP instruction is executed, the value of the jump flag JF becomes equal to the value of the carry flag CF. If the value of A register 101b before the subtraction of "5" is less than "5," i.e., if the value of index value counter 74f is within the first lottery target range ("11" to "15"), a carry is carried to the most significant bit (the seventh bit of bits 0 to 7) in the operation, causing the value of the carry flag CF to become "1," and the value of the jump flag JF to also become "1." On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or greater, i.e., if the value of the index value counter 74f is "0" to "10" or "16" to "17," which are not included in the first lottery range, no borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) in the operation, so the carry flag CF becomes "0" and the jump flag JF also becomes "0." The result of the operation to subtract "5" from the value of the A register 101b is not written to the A register 101b. Execution of the instruction "CP A, 05H" does not change the value of the A register 101b. Therefore, the data stored in the A register 101b by executing the operation to subtract "11" on line number "1402" can also be used in line number "1406," which will be described later.

The instruction "RET NC" is set in line number "1404." "RET" is a RET instruction to return from a subroutine, and "NC" sets the condition for returning from a subroutine, that is, the value of the carry flag CF be "0." By executing the instruction "RET NC" in line number "1404," the start-time bonus processing called in step S2310 of the advantageous state processing at the start of the game (FIG. 40) is terminated, provided that the value of the carry flag CF is "0," and the process returns to step S2311, the next step after step S2310. As described above, if the value of the index value counter 74f is "0" to "10" or "16" to "17," which are not included in the first lottery target range ("11" to "15"), the instruction in line number "1403" is executed, and the value of the carry flag CF becomes "0." Therefore, by executing the command "RET NC" in line number "1404", the start-time addition process ends and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). On the other hand, as described above, if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), the command in line number "1403" is executed and the value of the carry flag CF becomes "1". Therefore, even if the command "RET NC" is set in line number "1404", the start-time addition process does not end and the process proceeds to the next line number "1405".

The command "LD HL, KSADD01" is set in line number "1405." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first add-on lottery table 73d in the main ROM 73. By executing the command "LD HL, KSADD01" in line number "1405," the start address of the first add-on lottery table 73d is transferred to the HL register 104. This allows the first add-on lottery table 73d to be set as the lottery table to be referenced in the add-on lottery. In this way, when the AT state is ST5 and the index value IV in the first lottery target range ("11" to "15") is selected in the role lottery process (Figure 18), the first add-on lottery table 73d is set as the lottery table to be referenced.

The instruction "CP A, 02H" is set on line number "1406." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "02H" is one byte of numerical information representing "2." As described above, the A register 101b stores one byte of numerical information calculated by subtracting "11" on line number "1402." Specifically, when the value of the index value counter 74f is "13," the value of the A register 101b is "2." Furthermore, when the value of the index value counter 74f is "11," "12," "14," or "15," the value of the A register 101b is "0," "1," "3," or "4." Execution of the instruction "CP A, 02H" on line number "1406" subtracts "2" from the value of the A register 101b. If the value of the A register 101b before the subtraction of "2" is "2", i.e., if the value of the index value counter 74f is "13", the result of the operation will be "0" and the zero flag ZF will be set to "1". On the other hand, if the value of the A register 101b before the subtraction of "2" is not "2", i.e., if the value of the index value counter 74f is "11", "12", "14", or "15", the result of the operation will not be "0", and the value of the zero flag ZF will be "0".

The instruction "JR NZ, ADR142" is set on line number "1407." "JR" is a conditional jump instruction with a word length of 2 bytes, "NZ" specifies that the jump condition is that the value of the zero flag ZF is "0," and "ADR142" specifies the program address "ADR142" on line number "1409" as the program address to jump to. The instruction on line number "1407" is set to program address "ADR141." The JR instruction on line number "1407" relatively identifies the 2-byte program address to jump to (ADR142) based on the program address (ADR141) where the JR instruction is set and the difference information (8 bits) set in the JR instruction. Because the configuration uses a JR instruction with a word length of 2 bytes to jump to a jump destination program address, the machine language data size of the jump instruction for jumping to the jump destination program address is reduced compared to the configuration using a JP instruction with a word length of 3 bytes. As described above, when the value of the index value counter 74f is "11," "12," "14," or "15," the value of the zero flag ZF is set to "0" when the instruction at line number "1406" is executed. Therefore, when the instruction "JR NZ, ADR142" is executed at line number "1407," a jump to the program address "ADR142" at line number "1409" is performed. On the other hand, as described above, when the value of the index value counter 74f is "13," the zero flag ZF is set to "1" when the instruction at line number "1406" is executed. Therefore, even if the instruction "JR NZ, ADR142" is set on line number "1407", the program address will not jump and will proceed to the next line number "1408".

The command in line number "1408" is executed when the AT state is ST5 and the index value IV of "13" is won in the role lottery process (Figure 18). The command "LD HL, KSADD02" is set in line number "1408." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second add-on lottery table 73e in the main ROM 73. By executing the command "LD HL, KSADD02" in line number "1408," the start address of the second add-on lottery table 73e is transferred to HL register 104. This allows the lottery table referenced in the add-on lottery to be changed to the second add-on lottery table 73e. In this way, when the player is in AT state ST5 and has won the index value IV of "13" in the role lottery process (Figure 18), the lottery table to be referenced is changed from the first additional lottery table 73d to the second additional lottery table 73e, which is more advantageous to the player than the first additional lottery table 73d.

The command set in line number "1409" is executed when a jump is made from line number "1407" to the program address of line number "1409," or when the command in line number "1408" is executed to proceed to line number "1409." Specifically, in AT state ST5, if the index value IV included in the first lottery target range ("11" to "15") and not "13" is selected in the role selection process (Figure 18), the JR command in line number "1407" jumps to the program address of line number "1409" and the command in line number "1409" is executed. Also, in AT state ST5, if the index value IV of "13" included in the first lottery target range ("11" to "15") is selected in the role selection process (Figure 18), the LD command in line number "1408" is executed, and then the command in line number "1409" is executed.

The instruction "JP ADR133" is set in line number "1409." "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is a program address (2 bytes) in which an instruction to execute the processing of step S1802 in the release game number lottery processing (Figure 35 (b)) is set. Execution of the instruction "JP ADR133" in line number "1409" causes a jump to the program address "ADR133." Then, execution of the processing (lottery execution processing) of steps S1802 to S1807 in the release game number lottery processing (Figure 35 (b)) executes a lottery to add to the remaining number of continued games in AT state ST5. As already explained, if the player is in the AT state ST5 and has won an index value IV that is included in the first lottery target range ("11" to "15") and is not "13" in the role lottery process (Figure 18), the bonus lottery is executed with the first bonus lottery table 73d set as the reference lottery table. Also, if the player is in the AT state ST5 and has won an index value IV of "13" that is included in the first lottery target range ("11" to "15") in the role lottery process (Figure 18), the bonus lottery is executed with the second bonus lottery table 73e set as the reference lottery table.

The JP command at line number "1409" is a command to jump to the program address "ADR133" after changing the referenced lottery table to the second top-up lottery table 73e at line number "1408," and is also a command that ensures a jump to the program address "ADR133" when a jump to the program address at line number "1409" is made with the JR command at line number "1407." Therefore, compared to a configuration in which a command to ensure a jump to the program address "ADR133" when a jump is made with the JR command at line number "1407" is set as a separate command from the command to jump to the program address "ADR133" after changing the referenced lottery table to the second top-up lottery table 73e at line number "1408," the data size of the program stored in the main ROM 73 for executing the start-up top-up processing can be reduced.

As already explained, in the release game number lottery process (Figure 35), after setting the release game number lottery table 73c as the reference lottery table in step S1801, the lottery execution process of steps S1802 to S1807 is executed without calling a subroutine program. The lottery execution process (steps S1802 to S1807) is executed after executing the process of step S1801 in the release game number lottery process (Figure 35), and is also executed when a jump is made by the JP command at line number "1409" in the start-time addition process (Figure 100(a)). If the lottery execution process (steps S1802 to S1807) is configured as a common subroutine called in the release game number lottery process (FIG. 35) and the start-up addition process (FIG. 100(a)), it will be necessary to set a CALL command (3 bytes) that calls the lottery execution process after the command to execute the process of step S1801 in the release game number lottery process (FIG. 35). In this configuration, a CALL command is set instead of a JP command at line number "1409" of the start-up addition process (FIG. 100(a)), but the word length of the CALL command (3 bytes) is the same as the word length of the JP command (3 bytes). For this reason, if the release game number lottery process (FIG. 35) and the start-up additional processing (FIG. 100(a)) are configured to call a common subroutine called the lottery execution processing, the data capacity of the program stored in the main ROM 73 for executing the release game number lottery process (FIG. 35) and the start-up additional processing (FIG. 100(a)) will increase by the amount of the CALL command set in the release game number lottery process (FIG. 35).

In this embodiment, the processing is configured to jump to the program address (ADR133) where an instruction to execute the processing of step S1802 of the release game number lottery processing (FIG. 35(b)) is set by executing the JP command "JP ADR133" at line number "1409" of the start-time surcharge processing (FIG. 100(a)), and when the processing of step S1801 is executed in the release game number lottery processing (FIG. 35(b)), the processing of step S1802 is executed without calling a subroutine program. Therefore, compared to a configuration in which a common subroutine called the lottery execution processing is called in the release game number lottery processing (FIG. 35) and the start-time surcharge processing (FIG. 100(a)), the data capacity of the program stored in the main ROM 73 for executing the release game number lottery processing (FIG. 35) and the start-time surcharge processing (FIG. 100(a)) can be reduced.

Figure 100(b) is an explanatory diagram illustrating the jump instructions set in the program for start-up addition processing (Figure 100(a)) to jump from program addresses "ADR141" and "ADR142" to program address "ADR133." In the program for start-up addition processing (Figure 100(a)), the instruction "JP ADR133" is set at line number "1409." As already explained, the JP instruction is a jump instruction with a word length of 3 bytes that specifies the entire program address (2 bytes) of the jump destination. Therefore, by using the JP instruction, it is possible to jump from the program address "ADR142" where the JP instruction at line number "1409" is set to the program address "ADR133." The program for start-up addition processing (Figure 100(a)) sets a JR instruction with a word length of 2 bytes on line number "1407", jumps from line number "1407" to line number "1409", and then jumps to program address "ADR133" using the JP instruction set in the program address (ADR142) of the jump destination.

Figure 100(c) is an explanatory diagram illustrating jump instructions set to jump from program addresses "ADR141" and "ADR142" to program address "ADR133" in a third comparative example of start-up addition processing. In the third comparative example of start-up addition processing (Figure 100(c)), the instruction "JP NZ, ADR133" is set to program address "ADR141." "JP" is a conditional jump instruction with a word length of 3 bytes, "NZ" specifies that the jump condition is that the value of the zero flag ZF is "0," and "ADR133" specifies the program address "ADR133" as the jump destination program address. As already explained, by executing the instruction "CP A, 02H" on line number "1406," if the value of the index value counter 74f is "13," the zero flag ZF is set to "1." On the other hand, if the value of the index value counter 74f is "11," "12," "14," or "15," the value of the zero flag ZF becomes "0." If the value of the index value counter 74f is "11," "12," "14," or "15," the instruction "JP NZ, ADR133" is executed on line number "1407," resulting in a direct jump to the program address "ADR133." On the other hand, if the value of the index value counter 74f is "13," the program proceeds to the next line number "1408" without jumping.

As mentioned above, the JP command on line number "1409" is a command to jump to the program address "ADR133" after changing the referenced lottery table to the second additional lottery table 73e on line number "1408." Therefore, even in a configuration where a direct jump is made from line number "1407" to program address "ADR133," the JP command on line number "1409" cannot be omitted.

As shown in Figure 100(c), in the third comparative example of start-up addition processing (Figure 100(c)), the total word length of the jump instructions set to jump from program addresses "ADR141" and "ADR142" to program address "ADR133" is 6 bytes. In contrast, as shown in Figure 100(b), in the program for start-up addition processing (Figure 100(a)), the total word length of the jump instructions set to jump from program addresses "ADR141" and "ADR142" to program address "ADR133" is 5 bytes.

As described above, the program for start-up top-up processing (Fig. 100(a)) is configured to jump to line number "1409" using a two-byte JR instruction on the condition that the value of the zero flag ZF is "0" at line number "1407," and then jump to program address "ADR133" using a JP instruction set at the jump destination line number "1409." This reduces the total word length of the jump instructions set to jump from program address "ADR141" to program address "ADR133," compared to the processing configuration of the third comparative example for start-up top-up processing (Fig. 100(c)), which jumps directly to program address "ADR133" using a three-byte JP instruction on the condition that the value of the zero flag ZF is "0" at line number "1407." This reduces the data capacity of the program (Fig. 100(a)) stored in main ROM 73 to execute start-up top-up processing.

The present embodiment described above provides the following excellent effects:

The program for start-up top-up processing (Fig. 100(a)) is configured to jump to line number "1409" using a two-byte JR instruction on the condition that the value of the zero flag ZF is "0" at line number "1407," and then jump to program address "ADR133" using a JP instruction set at the jump destination line number "1409." This reduces the total word length of the jump instructions set to jump from program address "ADR141" to program address "ADR133," compared to the processing configuration of the third comparative example for start-up top-up processing (Fig. 100(c)), which jumps directly to program address "ADR133" using a three-byte JP instruction on the condition that the value of the zero flag ZF is "0" at line number "1407." This reduces the data capacity of the program (Fig. 100(a)) stored in main ROM 73 to execute start-up top-up processing.

Eleventh Embodiment
In this embodiment, the processing content of the start-time addition process and the program content for executing the start-time addition process differ from those of the first embodiment. The following describes the configurations that differ from the first embodiment. Note that the description of the same configurations as the first embodiment will basically be omitted.

Figure 101(a) is an explanatory diagram illustrating the jump instruction execution circuit provided in the main MPU 72 in this embodiment. As shown in Figure 101(a), the main MPU 72 is provided with the JP execution circuit 105 and JR execution circuit 106 already described with reference to Figure 61(a) in the first embodiment above. The main MPU 72 is capable of executing the JP instruction and the JR instruction as jump instructions. The main MPU 72 does not have the JRS execution circuit 107 in the first embodiment above.

In this embodiment, the value of the carry flag CF does not change even when the JR instruction, a conditional jump instruction with a word length of 2 bytes, is executed. When the jump condition set in the JR instruction is met and a jump is made to the jump destination program address, the instruction set in the jump destination program address can be executed while maintaining the value of the carry flag CF before the jump. Also, when the jump condition set in the JR instruction is not met and the instruction set after the JR instruction is proceeded to, the instruction set after the JR instruction can be executed while maintaining the value of the carry flag CF.

The value of the carry flag CF does not change even when the LD instruction is executed as a 16-bit transfer instruction. When an LD instruction (16-bit transfer instruction) is executed and the instruction set after that LD instruction is proceeded to, the value of the carry flag CF before the LD instruction was executed remains the same, and the instruction set after that LD instruction can be executed.

As already explained in the first embodiment above, the start-up addition processing is executed in step S2310 of the advantageous state processing at the start of the game (FIG. 40). The start-up addition processing is executed in the AT state ST5. In this embodiment, the first addition lottery is executed when the index value IV ("14" or "15") in which the first chance replay winning data or the second chance replay winning data is set is won in the role lottery processing (FIG. 18) in the game executed in the AT state ST5. The second addition lottery is executed when the index value IV ("11" or "12") in which the first watermelon winning data or the second watermelon winning data is set is won in the role lottery processing (FIG. 18) in the game executed in the AT state ST5. The third addition lottery is executed when the index value IV ("13") in which the cherry winning data is set is won in the role lottery processing (FIG. 18) in the game executed in the AT state ST5.

Figure 101(b) is an explanatory diagram illustrating the configuration of the main ROM 73 for executing the add-on lottery. As shown in Figure 101(b), the main ROM 73 stores a first add-on lottery table 73d, which is selected as the lottery table to be referenced in the first add-on lottery, a second add-on lottery table 73e, which is selected as the lottery table to be referenced in the second add-on lottery, and a third add-on lottery table 73h, which is selected as the lottery table to be referenced in the third add-on lottery.

As already explained in the first embodiment with reference to Figures 43(a) and (b), the first additional lottery table 73d and the second additional lottery table 73e are set with the number of additional games set to 10, 20, and 50. Furthermore, the first additional lottery table 73d has a judgment value of "16" set, and the second additional lottery table 73e has a judgment value of "32." As in the first embodiment, when the first additional lottery is executed using the first additional lottery table 73d as the reference lottery table, 10 games are selected with a probability of 1/16, 20 games are selected with a probability of 1/16, 50 games are selected with a probability of 1/16, and there is a 13/16 probability of a miss. Also, as in the first embodiment above, when a second additional lottery is executed using the second additional lottery table 73e as the reference lottery table, 10 games are selected with a 1/8 probability, 20 games are selected with a 1/8 probability, 50 games are selected with a 1/8 probability, and there is a 5/8 probability of a loss. As in the first embodiment above, the probability of winning 10, 20, or 50 additional games in the second additional lottery table 73e is set higher than the probability of winning 10, 20, or 50 additional games in the first additional lottery table 73d. The second additional lottery table 73e is a lottery table that is more advantageous to players than the first additional lottery table 73d.

Figure 101(c) is an explanatory diagram for explaining the contents of the third additional lottery table 73h. As shown in Figure 101(c), the third additional lottery table 73h has the additional game numbers set to 20, 40, and 80, and the judgment value set to "32." When the third additional lottery is performed using the third additional lottery table 73h as the reference lottery table, 20 games are selected with a 1/8 probability, 40 games are selected with a 1/8 probability, 80 games are selected with a 1/8 probability, and there is a 5/8 probability of a loss. The probability of winning the additional game number of 20, 40, or 80 games in the third additional lottery table 73h is the same as the probability of winning the additional game number of 10, 20, or 50 games in the second additional lottery table 73e. As mentioned above, the second additional lottery table 73e is a lottery table that is more advantageous to players than the first additional lottery table 73d, but the third additional lottery table 73h is a lottery table that is even more advantageous to players than the second additional lottery table 73e.

Prior to explaining the start-up addition process (Figure 102(a)), we will explain the process for selecting the addition lottery to be executed from the first to third addition lotteries. In the start-up addition process (Figure 102(a)) in this embodiment, if the value of the index value counter 74f is any of "11" to "15," the first addition lottery table 73d is first selected as the lottery table to be referenced. Thereafter, if it is determined that the value of the index value counter 74f is "11" or "12," the lottery table to be referenced is changed to the second addition lottery table 73e. This allows the second addition lottery to be executed in steps S1802 to S1807 (lottery execution process) of the release game number lottery process (Figure 35(b)) already described in the first embodiment above. Furthermore, if it is determined that the value of the index value counter 74f is "13," the lottery table to be referenced is changed to the third addition lottery table 73h. This allows the third additional lottery to be executed in steps S1802 to S1807 (lottery execution processing) of the release game number lottery processing (Figure 35 (b)). Furthermore, if the value of the index value counter 74f is "14" or "15", the first additional lottery table 73d remains selected as the lottery table to be referenced. This allows the first additional lottery to be executed in steps S1802 to S1807 (lottery execution processing) of the release game number lottery processing (Figure 35 (b)).

As already explained in the first embodiment with reference to FIG. 69(a), when an operation is performed to subtract "11" from the value of A register 101b after transferring the data of index value counter 74f to A register 101b, if the winning index value IV is within the numerical range of "11" to "15," the index value IV is shifted downward by "11" and stored in A register 101b. After the operation to subtract "11" is performed, the 1-byte of numerical information stored in A register 101b is "0" if the value of index value counter 74f is "11," "1" if the value of index value counter 74f is "12," "2" if the value of index value counter 74f is "13," "3" if the value of index value counter 74f is "14," and "4" if the value of index value counter 74f is "15." In the start-up addition process (FIG. 102(a)) in this embodiment, after the calculation to subtract "11" is performed, the instruction "CP A,02H" is executed on line number "1506" (described below) to perform a calculation to subtract "2" from the value of A register 101b ("0" to "4"). This "2" is a value other than the minimum value ("0") and maximum value ("4") in the range of "0" to "4", which is obtained by shifting the range of "11" to "15" downward by "11".

Figure 101(d) is an explanatory diagram illustrating the relationship between the value of the index value counter 74f and the values of the zero flag ZF and carry flag CF after execution of an operation to subtract "2." As shown in Figure 101(d), in row number "1506," if the index value IV to which the first or second watermelon winning data is set in the winning combination lottery process (Figure 18) is a winning combination, i.e., if the value of the index value counter 74f is "11" or "12," an operation is executed to subtract "2" from the "0" or "1" stored in the A register 101b. During this operation, a carry is carried to the most significant bit (the seventh bit of bits 0 to 7). Therefore, after execution of this operation, the value of the zero flag ZF becomes "0" and the value of the carry flag CF becomes "1." The main MPU 72 changes the lottery table to be referenced to the second add-on lottery table 73e based on the fact that the value of the zero flag ZF is "0" and the value of the carry flag CF is "1." This makes it possible to execute the second add-on lottery.

In line number "1506," if the index value IV for which cherry winning data is set in the role lottery process (Figure 18) is a win, i.e., if the value of the index value counter 74f is "13," an operation is performed to subtract "2" from the "2" stored in the A register 101b. The result of this operation is "0," and no borrow to the most significant bit (seventh bit) occurs during the execution of this operation. Therefore, after the execution of this operation, the value of the zero flag ZF becomes "1" and the value of the carry flag CF becomes "0." Based on the fact that the value of the zero flag ZF is "1," the main MPU 72 changes the referenced lottery table to the third add-on lottery table 73h. This makes it possible to execute the third add-on lottery.

In line number "1506," if the first chance replay winning data or second chance replay winning data is set to the index value IV in the winning combination lottery process (FIG. 18), i.e., if the value of the index value counter 74f is "14" or "15," an operation is performed to subtract "2" from the "3" or "4" stored in the A register 101b. The result of this operation is "1" or "2," and no borrowing to the most significant bit (seventh bit) occurs during the execution of this operation. Therefore, after the execution of this operation, the value of the zero flag ZF and the value of the carry flag CF become "0." When the value of the zero flag ZF and the value of the carry flag CF are "0," the main MPU 72 maintains the first add-on lottery table 73d selected as the lottery table to be referenced. This makes it possible to execute the first add-on lottery.

In order to determine whether the winning index value IV is between "11" and "12," the winning index value IV is "13," or the winning index value IV is between "14" and "15," if an operation is performed to subtract "13" from the index value IV before subtracting "11," the value subtracted will be "13." In contrast, by performing an operation to shift the numerical range of "11" to "15" downward by "11" (an operation to subtract "11"), and then subtracting "2," the value obtained by shifting "13" downward by "11," from the value after that operation, the value subtracted can be set to "2," a value smaller than "13." In order to determine whether the winning index value IV is "11" to "12", "13", or "14" to "15", the number of bits required to represent the value "2" subtracted from the value obtained by shifting the index value IV downward by "11" is "2", which is smaller than the number of bits ("4") required to represent the value "13" subtracted from the index value IV before the shift. In this way, in a configuration in which an operation is performed to subtract "11" from the index value IV to determine whether the index value IV is within the range of "11" to "15," the value after changing the index value IV downward by "11" is used to determine whether the pre-change index value IV is between "11" and "12," whether the pre-change index value IV is "13," or whether the pre-change index value IV is between "14" and "15." This reduces the number of bits required to represent the value subtracted in the operation to make this determination, thereby reducing the data capacity required to store this value.

Next, the contents of the program for the start-up bonus processing executed by the main MPU 72 will be explained with reference to the explanatory diagram in Figure 102(a). As already explained, the start-up bonus processing is executed in step S2310 of the advantageous state processing at the start of the game (Figure 40). As shown in Figure 102(a), this program has line numbers set to "1501" to "1511". Program commands are executed in order from lowest to highest line number, except when a call command or jump command is executed.

Line numbers "1501" to "1505" contain the same instructions as line numbers "1301" to "1305" in the start-up addition process (Figure 69 (b)) in the first embodiment described above. Specifically, line number "1501" contains the instruction "LD A, (INDXCNT)." "LD" is the LD instruction as an 8-bit data transfer instruction, "A" is the A register 101b, and "(INDXCNT)" specifies the index value counter 74f in the main RAM 74 as the transfer source. Execution of the instruction "LD A, (INDXCNT)" in line number "1501" transfers the data in the index value counter 74f to the A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in A register 101b, and if no index value IV is selected in the role selection process (Figure 18), "0" is set in A register 101b.

The instruction "SUB A, 0BH" is set in line number "1502." "SUB" is a SUB instruction that subtracts 8-bit data, "A" is the A register 101b, and "0BH" is one byte of numerical information indicating "11," the minimum value in the first lottery range ("11" to "15"). By executing the instruction "SUB A, 0BH" in line number "1502," an operation is performed to subtract "11" from the value in A register 101b, and the result of this operation is written to A register 101b. If a borrow to the most significant bit (the seventh bit) occurs in this operation, the carry flag CF is set to "1." If a borrow to the most significant bit (the seventh bit) does not occur in this operation, the value of the carry flag CF is set to "0." As already explained in the first embodiment with reference to FIG. 69(a), when the value of the index value counter 74f is any of "11" to "15", the value of the A register 101b will be less than "5", and when the value of the index value counter 74f is any of "0" to "10" or "16" to "17", which are not included in "11" to "15", the value of the A register 101b will be "5" or greater.

The instruction "CP A, 05H" is set in line number "1503." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "05H" is one byte of numerical information indicating a value ("5") that is "1" greater than "4," which is the value calculated by subtracting "11" from "15," the maximum value in the first lottery target range ("11" to "15"). Execution of the instruction "CP A, 05H" in line number "1503" subtracts "5" from the value in A register 101b. As already explained in the first embodiment above, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. If the value of the A register 101b before the subtraction of "5" is less than "5," i.e., if the value of the index value counter 74f is any of "11" to "15," a borrow occurs to the most significant bit (the seventh bit) in the operation, causing the carry flag CF to become "1" and the jump flag JF to become "1." On the other hand, if the value of the A register 101b before the subtraction of "5" is greater than or equal to "5," i.e., if the value of the index value counter 74f is any of "0" to "10" or "16" to "17" that are not included in the range of "11" to "15," a borrow does not occur to the most significant bit (the seventh bit), causing the carry flag CF to become "0" and the jump flag JF to become "0." The result of the operation to subtract "5" from the value of the A register 101b is not written to the A register 101b. The value of the A register 101b remains unchanged even when the instruction "CP A, 05H" is executed. Therefore, the calculation to subtract "11" is performed on line number "1502", and the data stored in A register 101b can also be used on line number "1506", which will be described later.

The instruction "RET NC" is set in line number "1504." "RET" is a RET instruction to return from a subroutine, and "NC" sets the condition for returning from a subroutine, that is, the value of the carry flag CF be "0." By executing the instruction "RET NC" in line number "1504," the start-of-game bonus processing called in step S2310 of the advantageous state processing at the start of the game (Figure 40) is terminated, provided that the value of the carry flag CF is "0," and the process returns to step S2311, the next step after step S2310. As described above, if the value of the index value counter 74f is "0" through "10" or "16" through "17," which are not included in the ranges "11" through "15," the instruction in line number "1503" is executed, and the value of the carry flag CF is set to "0." Therefore, by executing the command "RET NC" in line number "1504", the start-time addition process ends and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). On the other hand, as mentioned above, if the value of the index value counter 74f is any of "11" to "15", the value of the carry flag CF becomes "1" when the command in line number "1503" is executed. Therefore, even if the command "RET NC" is set in line number "1504", the start-time addition process does not end and the process proceeds to the next line number "1505".

The command in row number "1505" is executed when the AT state ST5 is reached and the winning combination lottery process (FIG. 18) has selected any of the index values IV "11" to "15". The command "LD HL, KSADD01" is set in row number "1505". "LD" is the LD command as a 16-bit transfer command, "HL" is the content that sets the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first additional lottery table 73d in the main ROM 73. In row number "1505", "LD
When the command "HL, KSADD01" is executed, the start address of the first add-on lottery table 73d is transferred to the HL register 104. This allows the first add-on lottery table 73d to be set as the lottery table to be referenced in the add-on lottery. In this way, when the AT state ST5 is reached and the role lottery process (Figure 18) has selected an index value IV of "11" to "15", the first add-on lottery table 73d is first set as the lottery table to be referenced.

The instruction "CP A, 02H" is set in row number "1506." "CP" is a CP instruction as a comparison instruction for 8-bit data, and "A" is the A register 101b. "02H" is one byte of numerical information representing "2," a number other than the minimum value ("0") and the maximum value ("4") in the range of "0" to "4," obtained by shifting the range of "11" to "15" downward by "11." As described above, the A register 101b stores one byte of numerical information calculated by subtracting "11" from row number "1502." The instruction in row number "1506" is executed when the winning combination results in an index value IV of any of "11" to "15" during the winning combination lottery process (Figure 18). Therefore, the value of A register 101b is one of "0" to "4." Execution of the instruction "CP A,02H" on line number "1506" results in an operation to subtract "2" from the value of the A register 101b. As already explained with reference to FIG. 101(d), when the value of the index value counter 74f is "11" or "12," an operation to subtract "2" from the "0" or "1" stored in the A register 101b is executed. During execution of this operation, a borrow occurs to the most significant bit (the seventh bit of the zeroth to seventh bits). Therefore, after execution of this operation, the value of the zero flag ZF becomes "0" and the value of the carry flag CF becomes "1." When the value of the index value counter 74f is "13," an operation to subtract "2" from the "2" stored in the A register 101b is executed. The result of this operation is "0," and no borrow occurs to the most significant bit (the seventh bit) during execution of this operation. Therefore, after the execution of this operation, the value of the zero flag ZF becomes "1" and the value of the carry flag CF becomes "0." If the value of the index value counter 74f is "14" or "15," an operation is executed to subtract "2" from "3" or "4" stored in the A register 101b. The result of this operation is "1" or "2," and no carry to the most significant bit (the seventh bit) occurs during the execution of this operation. Therefore, the value of the zero flag ZF and the value of the carry flag CF become "0" after the execution of this operation. As described above, by using the value after changing the index value IV by "11" to the smaller side to determine whether the index value before the change is "11" to "12," whether the index value IV before the change is "13," or whether the index value IV before the change is "14" to "15," the number of bits required to represent the value ("2") to be subtracted in the operation for making this determination can be reduced. This reduces the amount of data required to store the value.

The instruction "JR NZ, ADR152" is set on line number "1507." "JR" is a conditional jump instruction with a word length of 2 bytes, "NZ" sets the jump condition to a zero flag ZF value of "0," and "ADR152" sets the program address "ADR152" on line number "1509" as the jump destination. The instruction on line number "1507" is set to program address "ADR151." As previously explained, the range that can be jumped with the JR instruction is from "(the program address where the JR instruction is set) + 2 - 128" to "(the program address where the JR instruction is set) + 2 + 127." As shown in Figure 102(a), the instruction set at a program address between program addresses "ADR151" and "ADR152" (the LD instruction on line number "1508") has a word length of 3 bytes. "ADR152" is "(ADR151) + 2 + 3", and is a program address that can be specified as the jump destination program address for the JR instruction, based on the program address (ADR151) where the JR instruction at line number "1507" is set.

As mentioned above, if the value of the index value counter 74f is "11," "12," "14," or "15," the instruction at line number "1506" is executed, causing the value of the zero flag ZF to be set to "0." Therefore, the instruction "JR NZ, ADR152" is executed at line number "1507," causing a jump to the program address "ADR152" at line number "1509." On the other hand, as mentioned above, if the value of the index value counter 74f is "13," the instruction at line number "1506" is executed, causing the value of the zero flag ZF to be set to "1." Therefore, even if the instruction "JR NZ, ADR152" is set at line number "1507," the program address does not jump, and the program proceeds to the next line number "1508."

The command in row number "1508" is executed when the AT state ST5 is reached and the index value IV of "13" is reached in the lottery process (FIG. 18). The command "LD HL, KSADD03" is set in row number "1508". "LD" is the LD command as a 16-bit transfer command, "HL" is the content that sets the HL register 104 as the transfer destination, and "KSADD03" is the start address of the third additional lottery table 73h (FIG. 101(b)) in the main ROM 73. In row number "1508", "LD
By executing the command "HL, KSADD03", the start address of the third add-on lottery table 73h is transferred to the HL register 104. This allows the lottery table to be referenced to be changed from the first add-on lottery table 73d to the third add-on lottery table 73h. As already explained, the third add-on lottery table 73h is a lottery table that is more advantageous to the player than the first add-on lottery table 73d and the second add-on lottery table 73e. In this way, when the AT state ST5 is reached and the index value IV of "13" is won in the role lottery process (Figure 18), the third add-on lottery table 73h is set as the lottery table to be referenced in the add-on lottery.

The instruction set in line number "1509" is executed when a jump to line number "1509" is made by the JR instruction in line number "1507," or when the LD instruction in line number "1508" is executed to proceed to line number "1509." Specifically, in AT state ST5, if the index value IV of "11," "12," "14," or "15" is selected in the role selection process (Figure 18), the JR instruction in line number "1507" jumps to the program address of line number "1509," and the instruction in line number "1509" is executed. As explained above, the value of the carry flag CF does not change when the JR instruction is executed as a conditional jump instruction with a word length of 2 bytes. Therefore, when the CP instruction in line number "1506" is executed, the instruction in line number "1509" is executed while maintaining the value set in the carry flag CF. As described above, if the index value IV of "11" or "12" is selected, the instruction of line number "1506" is executed, causing the value of the carry flag CF to become "1." Also, if the index value IV of "14" or "15" is selected, the instruction of line number "1506" is executed, causing the value of the carry flag CF to become "0." Also, in the AT state ST5, if the index value IV of "13" is selected in the winning combination lottery process (FIG. 18), the LD instruction of line number "1508" is executed, and then the instruction of line number "1509" is executed. As already explained, the value of the carry flag CF is maintained when the jump condition set in the JR instruction as a conditional jump instruction with a word length of 2 bytes is not satisfied and the instruction set next to the JR instruction is executed, and is also maintained when the LD instruction as a 16-bit transfer instruction is executed. Therefore, when the CP instruction on line number "1506" is executed, the value set in the carry flag CF is maintained and the instruction on line number "1509" is executed. As mentioned above, if the index value IV is "13", the value of the carry flag CF becomes "0" when the instruction on line number "1506" is executed.

The instruction "JR NC, ADR153" is set on line number "1509." "JR" is a conditional jump instruction with a word length of 2 bytes, "NC" sets the jump condition to the carry flag CF being set to "0," and "ADR153" sets the program address "ADR153" at line number "1511" as the jump destination. As mentioned above, the instruction on line number "1509" is set to program address "ADR152." As already explained, the range that can be jumped to with the JR instruction is from "(the program address where the JR instruction is set) +2 - 128" to "(the program address where the JR instruction is set) +2 + 127." As shown in Figure 102 (a), the word length of the instruction set at the program address between program addresses "ADR152" and "ADR153" (the LD instruction on line number "1510") is 3 bytes. "ADR153" is "(ADR152) + 2 + 3", and is a program address that can be specified as the jump destination program address for the JR instruction, based on the program address (ADR152) where the JR instruction on line number "1509" is set.

As mentioned above, when the value of the index value counter 74f is any value between "13" and "15," the value of the carry flag CF remains "0." Therefore, executing the instruction "JR NZ, ADR153" on line number "1509" causes a jump to the program address "ADR153" on line number "1511." On the other hand, as mentioned above, when the value of the index value counter 74f is "11" or "12," the value of the carry flag CF remains "1." Therefore, even if the instruction "JR NZ, ADR153" is set on line number "1509," the program address does not jump, and the program proceeds to the next line number "1510."

The command in row number "1510" is executed when the AT state is ST5 and the index value IV of "14" or "15" is won in the role lottery process (Figure 18). The command "LD HL, KSADD02" is set in row number "1510." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second add-on lottery table 73e in the main ROM 73. By executing the command "LD HL, KSADD02" in row number "1510," the start address of the second add-on lottery table 73e is transferred to HL register 104. This allows the referenced lottery table to be changed from the first add-on lottery table 73d to the second add-on lottery table 73e. As already explained, the second additional lottery table 73e is a lottery table that is more advantageous to the player than the first additional lottery table 73d, and is a lottery table that is less advantageous to the player than the third additional lottery table 73h. Thus, when the AT state ST5 is reached and the index value IV of "11" or "12" is selected in the role lottery process (Figure 18), the second additional lottery table 73e is set as the lottery table to be referenced in the additional lottery.

The instruction at line number "1511" is executed when a jump is made to the program address at line number "1511" by the JR instruction at line number "1509," or when the LD instruction at line number "1510" is executed to proceed to line number "1511." Line number "1511" contains the instruction "JP ADR133," similar to line number "1309" in the start-up addition process (Figure 69(b)) in the first embodiment described above. "JP" is a JP instruction serving as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is a program address (2 bytes) containing an instruction for executing step S1802 in the release game number lottery process (Figure 35(b)). Execution of the instruction "JP ADR133" at line number "1511" causes a jump to the program address "ADR133." Then, by executing steps S1802 to S1807 of the release game number lottery process (FIG. 35(b)), one of the first to third additional lotteries is executed. As already explained, in AT state ST5, if the index value IV of "14" or "15" is won in the role lottery process (FIG. 18), the first additional lottery is executed based on the first additional lottery table 73d; if the index value IV of "11" or "12" is won in the role lottery process (FIG. 18), the second additional lottery is executed based on the second additional lottery table 73e; and if the index value IV of "13" is won in the role lottery process (FIG. 18), the third additional lottery is executed based on the third additional lottery table 73h.

Figure 102(b) is an explanatory diagram illustrating the program contents in the fourth comparative example of start-time additional processing. As shown in Figure 102(b), this program has line numbers "8201" to "8212" set. Program instructions are executed in order from lowest to highest line number, except when a call or jump instruction is executed.

The fourth comparative example of the start-up add-on processing is a processing configuration in which, to select the first to third add-on lottery tables 73d, 73e, and 73h, the start address of the second add-on lottery table 73e is set in the HL register 104 on the condition that an index value IV of "11" to "15" is selected, and then, if it is determined that the selected index value IV is "13" or greater, the referenced lottery table is changed from the second add-on lottery table 73e to the third add-on lottery table 73h, and if it is determined that the selected index value IV is "14" or greater, the referenced lottery table is changed from the third add-on lottery table 73h to the first add-on lottery table 73d.

As shown in FIG. 102(b), in line numbers "8201" to "8204" in the fourth comparative example of the start-up addition process, the same instructions are set as in line numbers "1501" to "1504" of the start-up addition process already described with reference to FIG. 102(a). By executing the instruction "LD A, (INDXCNT)" in line number "8201," the data of the index value counter 74f is transferred to the A register 101b. As a result, if any of the index values IV of "1" to "17" is selected in the winning combination lottery process (FIG. 18), the index value IV is set in the A register 101b. If no index value IV is selected in the winning combination lottery process (FIG. 18), "0" is set in the A register 101b. By executing the instruction "SUB A,0BH" on line number "8202", an operation is performed to subtract "11" from the value of the A register 101b, and the result of this operation is written to the A register 101b. If the value of the index value counter 74f is any of "11" to "15", the value of the A register 101b will be less than "5", and if the value of the index value counter 74f is any of "0" to "10" or "16" to "17" that are not included in "11" to "15", the value of the A register 101b will be "5" or more.
Execution of the instruction "A, 05H" performs an operation to subtract "5" from the value of the A register 101b. If the value of the A register 101b before the subtraction of "5" is less than "5," i.e., if the value of the index value counter 74f is any of "11" to "15," a borrow to the most significant bit (the seventh bit) occurs in the operation, causing the value of the carry flag CF to become "1" and the value of the jump flag JF to become "1." On the other hand, if the value of the A register 101b before the subtraction of "5" is greater than or equal to "5," i.e., if the value of the index value counter 74f is any of "0" to "10" or "16" to "17," which are not included in the range of "11" to "15," no borrow to the most significant bit (the seventh bit) occurs in the operation, causing the value of the carry flag CF to become "0" and the value of the jump flag JF to become "0."

By executing the command "RET NC" on line number "8204," the start-time accrual processing called in step S2310 of the processing for advantageous states at the start of the game (Figure 40) is terminated, provided that the value of the carry flag CF is "0," and processing returns to step S2311, the next step after step S2310. As described above, if the value of the index value counter 74f is either "0" to "10" or "16" to "17," the command on line number "8203" is executed, causing the value of the carry flag CF to become "0." Therefore, by executing the command "RET NC" on line number "8204," the start-time accrual processing is terminated, and processing returns to step S2311 of the processing for advantageous states at the start of the game (Figure 40). On the other hand, as mentioned above, if the value of the index value counter 74f is any of "11" to "15," the instruction on line number "8203" is executed, causing the value of the carry flag CF to become "1." Therefore, even if the instruction "RET NC" is set on line number "8204," the start-up addition process does not end, and the program proceeds to the next line number "8205."

The command in row number "8205" is executed when the AT state ST5 is reached and the lottery process (FIG. 18) has selected any of the index values IV "11" to "15". The command "LD HL, KSADD02" is set in row number "8205". "LD" is the LD command as a 16-bit transfer command, "HL" is the content that sets the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second additional lottery table 73e in the main ROM 73. In row number "8205", "LD
By executing the command "HL, KSADD02", the start address of the second add-on lottery table 73e is transferred to the HL register 104. As a result, the second add-on lottery table 73e is set as the lottery table to be referenced in the add-on lottery.

Line number "8206" has the command "CP A, 02H", similar to line number "1506" in the initial addition process (Figure 102(a)). The command in line number "8206" is executed when the index value IV is any of "11" to "15" in the role selection process (Figure 18), so the value of A register 101b is any of "0" to "4". When the command "CP A, 02H" is executed in line number "8206", an operation is performed to subtract "2" from the value of A register 101b. If the value of index value counter 74f is "11" or "12", an operation is performed to subtract "2" from the "0" or "1" stored in A register 101b. During the execution of this operation, a borrow occurs to the most significant bit (7th bit). Therefore, the value of the carry flag CF after this operation is executed will be "1". On the other hand, if the value of the index value counter 74f is any of "13" to "15", an operation is executed to subtract "2" from any of "2" to "4" stored in the A register 101b. The result of this operation will be any of "0" to "2", and no carry to the most significant bit (seventh bit) occurs during the execution of this operation. Therefore, the value of the carry flag CF after this operation is executed will be "0".

The instruction "JR C, ADR823" is set in line number "8207." "JR" is a conditional jump instruction with a word length of 2 bytes, "C" sets the jump condition to a carry flag CF value of "1," and "ADR823" sets the program address "ADR823" at line number "8212" as the jump destination. The instruction in line number "8207" is set to program address "ADR821." "ADR823" is a program address that can be specified as the jump destination program address for the JR instruction, based on the program address (ADR821) where the JR instruction in line number "8207" is set. As mentioned above, when the value of index value counter 74f is "11" or "12," the value of carry flag CF is set to "1" when the instruction in line number "8206" is executed. Therefore, when the instruction "JR C, ADR823" is executed on line number "8207," a jump occurs to the program address "ADR823" on line number "8212." On the other hand, as mentioned above, if the value of the index value counter 74f is any of "13" to "15," the value of the carry flag CF becomes "0" when the instruction on line number "8206" is executed. Therefore, even if the instruction "JR C, ADR823" is set on line number "8207," the program address does not jump, and proceeds to the next line number "8208."

The command in row number "8208" is executed when the AT state ST5 is reached and the lottery process (FIG. 18) has selected any of the index values IV "13" to "15". The command "LD HL, KSADD03" is set in row number "8208". "LD" is the LD command as a 16-bit transfer command, "HL" is the content that sets the HL register 104 as the transfer destination, and "KSADD03" is the start address of the third additional lottery table 73h in the main ROM 73. In row number "8208", "LD
By executing the command "HL, KSADD03", the start address of the third add-on lottery table 73h is transferred to the HL register 104. As a result, the lottery table to be referenced in the add-on lottery is changed from the second add-on lottery table 73e to the third add-on lottery table 73h.

The instruction "CP A, 03H" is set in line number "8209." "CP" is a CP instruction that compares 8-bit data, "A" is the A register 101b, and "03H" is one byte of numerical information indicating "3." The instruction in line number "8209" is executed when the winning combination lottery process (Figure 18) results in an index value IV of "13" through "15." Therefore, the value of A register 101b is either "2" through "4." Executing the instruction "CP A, 03H" in line number "8209" subtracts "3" from the value of A register 101b. If the value of index value counter 74f is "13," an operation is performed to subtract "3" from the "2" stored in A register 101b. During this operation, a borrow occurs to the most significant bit (the seventh bit). Therefore, the value of the carry flag CF after this operation is executed will be "1". On the other hand, if the value of the index value counter 74f is either "14" or "15", an operation is executed to subtract "3" from the "3" or "4" stored in the A register 101b. The result of this operation is "0" or "1", and no carry to the most significant bit (seventh bit) occurs during the execution of this operation. Therefore, the value of the carry flag CF after this operation is executed will be "0".

The instruction "JR C, ADR823" is set in line number "8210," just like line number "8207" described above. The instruction in line number "8210" is set to program address "ADR822." "ADR823" is a program address that can be specified as the jump destination program address for the JR instruction, based on the program address (ADR822) where the JR instruction in line number "8210" is set. As described above, when the value of index value counter 74f is "13," the value of carry flag CF becomes "1" when the instruction in line number "8209" is executed. Therefore, when the instruction "JR C, ADR823" is executed in line number "8210," a jump occurs to the program address "ADR823" in line number "8212." On the other hand, as mentioned above, if the value of the index value counter 74f is "14" or "15", the instruction on line number "8209" is executed, causing the value of the carry flag CF to become "0". Therefore, even if the instruction "JR C, ADR823" is set on line number "8209", the program address does not jump and proceeds to the next line number "8211".

The command in line number "8211" is executed when the AT state is ST5 and the index value IV of "14" or "15" is won in the role lottery process (Figure 18). The command "LD HL, KSADD01" is set in line number "8211", similar to line number "1505" in the start-up add-on process (Figure 102(a)) already explained. By executing the command "LD HL, KSADD01" in line number "8211", the start address of the first add-on lottery table 73d is transferred to HL register 104. As a result, the lottery table referenced in the add-on lottery is changed from the third add-on lottery table 73h to the first add-on lottery table 73d.

The command at line number "8212" is executed when a jump to the program address at line number "8212" is made by the JR command at line number "8207," when a jump to the program address at line number "8212" is made by the JR command at line number "8210," or when the LD command at line number "8211" is executed to proceed to line number "8212." Line number "8212" contains the command "JP ADR133," similar to line number "1511" in the start-up bonus processing (FIG. 102(a)) already described. Executing the command "JP ADR133" at line number "8212" jumps to the program address "ADR133." Then, steps S1802 to S1807 of the release game number lottery processing (FIG. 35(b)) are executed, resulting in one of the first, second, and third bonus lotteries being executed.

Figure 102(c) is an explanatory diagram illustrating the commands set for selecting the first to third add-on lottery tables 73d, 73e, and 73h in the start-up add-on process and the fourth comparative example of the start-up add-on process. In the start-up add-on process (Figure 102(a)), the commands for selecting the first to third add-on lottery tables 73d, 73e, and 73h are set in row numbers "1505" to "1510." In addition, in the fourth comparative example of the start-up add-on process (Figure 102(b)), the commands for selecting the first to third add-on lottery tables 73d, 73e, and 73h are set in row numbers "8205" to "8211."

As shown in Figure 102(c), in the fourth comparative example of start-up addition processing (Figure 102(b)), three 3-byte LD instructions, two 2-byte CP instructions, and two 2-byte JR instructions are set on lines "8205" to "8211". The total word length of the instructions set on lines "8205" to "8211" is 17 bytes. In contrast, in the start-up addition processing (Figure 102(a)), three 3-byte LD instructions, one 2-byte CP instruction, and two 2-byte JR instructions are set on lines "1505" to "1510". The total word length of the instructions set on lines "1505" to "1510" is 15 bytes.

As already explained, the initial top-up processing (Figure 102 (a)) is a processing configuration in which, when numerical information between "0" and "4" is set in A register 101b, a process is performed to set the first top-up lottery table 73d as the referenced lottery table and to subtract "2" from the value of A register 101b, and based on the combination of values set in the zero flag ZF and the carry flag CF by the operation to subtract "2", the referenced lottery table is changed to the third top-up lottery table 73h, the referenced lottery table is changed to the second top-up lottery table 73e, or the referenced lottery table remains the first top-up lottery table 73d. This reduces the total word length of the instructions set to select the first to third add-on lottery tables 73d, 73e, and 73h compared to the fourth comparative example of the start-up add-on process (FIG. 102(b)). When numerical information between "0" and "4" is set in the A register 101b, the second add-on lottery table 73e is set as the reference lottery table. If a positive judgment is made in the process of determining whether the value of the A register 101b is "2" or greater, the reference lottery table is changed from the second add-on lottery table 73e to the third add-on lottery table 73h. If a positive judgment is made in the process of determining whether the value of the A register 101b is "3" or greater, the reference lottery table is changed from the third add-on lottery table 73h to the first add-on lottery table 73d. This reduces the data capacity of the program stored in the main ROM 73 for executing the start-up add-on process (FIG. 102(a)).

The value of the carry flag CF is maintained before and after the execution of the JR instruction, and is also maintained before and after the execution of the LD instruction. Therefore, in the start-up addition process (Figure 102(a)), by executing the CP instruction on line number "1506," the values set in the zero flag ZF and carry flag CF can be used to execute a process to change the referenced lottery table to the third add-on lottery table 73h when the value of the zero flag ZF is "1," and to execute a process to change the referenced lottery table to the second add-on lottery table 73e when the value of the carry flag CF is "1." This allows for a reduction in the number of CP instructions compared to the fourth comparative example of the start-up addition process (Figure 102 (b)), in which the first CP instruction (line number "8206") is executed to use the value set in the carry flag CF to change the referenced lottery table to the third add-on lottery table 73h when the value of the carry flag CF is "0", and the second CP instruction (line number "8209") is executed to use the value set in the carry flag CF to change the referenced lottery table to the first add-on lottery table 73d when the value of the carry flag CF is "0".

The present embodiment described above provides the following excellent effects:

The initial top-up processing (Figure 102 (a)) is a processing configuration that, when numerical information between "0" and "4" is set in A register 101b, sets the first top-up lottery table 73d as the reference lottery table and executes an operation to subtract "2" from the value of A register 101b, and, based on the combination of values set in the zero flag ZF and the carry flag CF by the operation to subtract "2", causes the reference lottery table to be changed to the third top-up lottery table 73h, the reference lottery table to be changed to the second top-up lottery table 73e, or the reference lottery table to remain as the first top-up lottery table 73d. This reduces the total word length of the instructions set to select the first to third add-on lottery tables 73d, 73e, and 73h compared to the fourth comparative example of the start-up add-on process (FIG. 102(b)). When numerical information between "0" and "4" is set in the A register 101b, the second add-on lottery table 73e is set as the reference lottery table. If a positive judgment is made in the process of determining whether the value of the A register 101b is "2" or greater, the reference lottery table is changed from the second add-on lottery table 73e to the third add-on lottery table 73h. If a positive judgment is made in the process of determining whether the value of the A register 101b is "3" or greater, the reference lottery table is changed from the third add-on lottery table 73h to the first add-on lottery table 73d. This reduces the data capacity of the program stored in the main ROM 73 for executing the start-up add-on process (FIG. 102(a)).

The value of the carry flag CF is maintained before and after the execution of the JR instruction, and is also maintained before and after the execution of the LD instruction. Therefore, in the start-up addition process (Figure 102(a)), by executing the CP instruction on line number "1506," the values set in the zero flag ZF and carry flag CF can be used to execute a process to change the referenced lottery table to the third add-on lottery table 73h when the value of the zero flag ZF is "1," and to execute a process to change the referenced lottery table to the second add-on lottery table 73e when the value of the carry flag CF is "1." This allows for a reduction in the number of CP instructions compared to the fourth comparative example of the start-up addition process (Figure 102 (b)), in which the first CP instruction (line number "8206") is executed to use the value set in the carry flag CF to change the referenced lottery table to the third add-on lottery table 73h when the value of the carry flag CF is "0", and the second CP instruction (line number "8209") is executed to use the value set in the carry flag CF to change the referenced lottery table to the first add-on lottery table 73d when the value of the carry flag CF is "0".

In a configuration in which an operation to subtract "11" from the index value IV is performed to determine whether the index value IV is within the range of "11" to "15," a determination is made using the value after shifting the index value IV downward by "11" to determine whether the pre-shift index value IV is between "11" and "12," whether the pre-shift index value IV is "13," or whether the pre-shift index value IV is between "14" and "15." After performing an operation to shift the range of "11" to "15" downward by "11" (an operation to subtract "11"), an operation is performed to subtract "2," which is the value obtained by shifting "13" downward by "11," from the value after the operation, thereby making it possible to set the subtracted value to "2," a value smaller than "13." To determine whether the winning index value IV is between "11" and "12," the winning index value IV is "13," or the winning index value IV is between "14" and "15," the number of bits required to represent the value "2" subtracted from the value obtained by shifting the index value IV downward by "11" is "2," which is smaller than the number of bits ("4") required to represent the value "13." This reduces the number of bits required to represent the value subtracted in the calculation used to make this determination, thereby reducing the data capacity required to store this value.

Twelfth Embodiment
In this embodiment, when an additional lottery is executed, a lottery effect is executed on the image display device 63, which makes the player expect that the remaining number of continued games in the AT state ST5 will be added. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will be basically omitted.

The bonus lottery is executed in AT state ST5 on the condition that an index value IV of any one of "11" to "15" is won in the lottery process (Figure 18) for a game role where the bet amount is "3". Figure 103(a) is an explanatory diagram for explaining the configuration of the main ROM 73 for executing the bonus lottery in this embodiment. As shown in Figure 103(a), the main ROM 73 stores a first bonus lottery table 73d, a second bonus lottery table 73e, and a third bonus lottery table 73h.

In this embodiment, if an index value IV of "11," "12," "14," or "15" is selected in the role selection process (FIG. 18), a first additional lottery is executed with the first additional lottery table 73d as the reference lottery table. Furthermore, if an index value IV of "13" is selected in the role selection process (FIG. 18), a second additional lottery is executed with the second additional lottery table 73e as the reference lottery table, provided that the number of games with a bet number of "3" played in the AT state ST5 is other than "10." Furthermore, a third additional lottery is executed with the third additional lottery table 73h as the reference lottery table, provided that the number of games with a bet number of "3" played in the AT state ST5 is "10."

As already explained in the first embodiment with reference to Figures 43(a) and (b), the first additional lottery table 73d and the second additional lottery table 73e are set with the number of additional games set to 10, 20, and 50. Furthermore, the first additional lottery table 73d has a judgment value of "16" set, and the second additional lottery table 73e has a judgment value of "32." As in the first embodiment, when the first additional lottery is executed using the first additional lottery table 73d as the reference lottery table, 10 games are selected with a probability of 1/16, 20 games are selected with a probability of 1/16, 50 games are selected with a probability of 1/16, and there is a 13/16 probability of a miss. Also, as in the first embodiment above, when a second additional lottery is executed using the second additional lottery table 73e as the reference lottery table, 10 games are selected with a 1/8 probability, 20 games are selected with a 1/8 probability, 50 games are selected with a 1/8 probability, and there is a 5/8 probability of a loss. As in the first embodiment above, the probability of winning 10, 20, or 50 additional games in the second additional lottery table 73e is set higher than the probability of winning 10, 20, or 50 additional games in the first additional lottery table 73d. The second additional lottery table 73e is a lottery table that is more advantageous to players than the first additional lottery table 73d.

As already explained in the eleventh embodiment with reference to Figure 101 (c), the third additional lottery table 73h has 20, 40, and 80 additional game numbers set, and a judgment value of "32." When the third additional lottery is executed using the third additional lottery table 73h as the reference lottery table, 20 games are selected with a 1/8 probability, 40 games are selected with a 1/8 probability, 80 games are selected with a 1/8 probability, and there is a 5/8 probability of a loss. The probability of winning 20, 40, or 80 additional games in the third additional lottery table 73h is the same as the probability of winning 10, 20, or 50 additional games in the second additional lottery table 73e. As mentioned above, the second additional lottery table 73e is a lottery table that is more advantageous to players than the first additional lottery table 73d, but the third additional lottery table 73h is a lottery table that is even more advantageous to players than the second additional lottery table 73e.

As described above, when an additional lottery is executed, a lottery effect is executed on the image display device 63, which creates an expectation that an additional bonus will be awarded to the remaining number of continued games in the AT state ST5. When a first additional lottery is executed, the first lottery effect is executed. In the first lottery effect, a cut-in image indicating the possibility of an additional bonus being awarded is displayed on the image display device 63. When a second additional lottery, which is more advantageous to the player than the first additional lottery, is executed, the second lottery effect is executed. In the second lottery effect, a cut-in image indicating the possibility of an additional bonus being awarded is displayed on the image display device 63. When a third additional lottery, which is more advantageous to the player than the second additional lottery, is executed, the third lottery effect is executed. In the third lottery effect, similar to the second lottery effect, a cut-in image indicating the possibility of an additional bonus being awarded is displayed on the image display device 63. Furthermore, in the third lottery effect, a lottery sound is output from the speaker 62, which creates an expectation that an additional bonus will be awarded.

Figure 103(b) is an explanatory diagram illustrating the configuration of the main RAM 74 for executing the lottery effects. As shown in Figure 103(b), the main RAM 74 is provided with an AT game number counter 141, an image type counter 142, and a sound type counter 143. The AT game number counter 141 is a 2-byte counter that allows the main MPU 72 to keep track of the number of games played with a bet number of "3" in the AT state ST5. The value of the AT game number counter 141 is incremented by 1 each time a game with a bet number of "3" is played in the AT state ST5, and is cleared to "0" when the AT state ST5 ends.

The image type counter 142 is a one-byte counter that is set with an image type number indicating the type of cut-in image displayed on the image display device 63 in the first to third lottery effects. The image type counter 142 is set with an image type number of "1" when the first lottery effect is executed, and is set with an image type number between "2" and "6" when the second lottery effect or the third lottery effect is executed. The sound type counter 143 is a one-byte counter that is set with a sound type number indicating the type of lottery sound output from the speaker 62 in the third lottery effect. The sound type counter 143 is set with a sound type number between "1" and "5" when the third lottery effect is executed.

The image type number set in the image type counter 142 and the sound type number set in the sound type counter 143 are set in a lottery effect command sent to the effect-side MPU 92. When the effect-side MPU 92 receives a lottery effect command, it controls the display of the image display device 63 so that a cut-in image corresponding to the image type number set in the lottery effect command is displayed. Furthermore, if a sound type number from "1" to "5" is set in the lottery effect command, it controls the sound output of the speaker 62 so that a lottery sound corresponding to the sound type number is output. As in the first embodiment, when the effect-side MPU 92 determines that an addition has been made to the remaining number of continued games in the AT state ST5 based on the start command received from the main MPU 72, it executes an addition effect after the first to third lottery effects. In the addition effect, a cut-in image corresponding to the number of added games is displayed on the image display device 63. This notifies the player of the number of added games.

Next, the AT processing executed by the main MPU 72 will be described with reference to the flowchart in Figure 103 (c). As already explained in the first embodiment above, the AT processing is executed in step S1506 of the response processing at the end of play (Figure 32). Since the response processing at the end of play is executed after all rotations of reels 32L, 32M, and 32R in one game have stopped, the AT processing is also executed after all rotations of reels 32L, 32M, and 32R in one game have stopped.

In the AT processing, first, similar to step S2501 in the AT processing (Figure 42) in the first embodiment described above, the bet number setting counter 74b in the main RAM 74 is referenced to determine whether the number of bets for the current game is "3" (step S5901). If the number of bets for the current game is "3" (step S5901: YES), the value of the AT game number counter 141 in the main RAM 74 is incremented by 1 (step S5902). This enables the main MPU 72 to grasp the number of games with a bet number of "3" played in the AT state ST5.

Then, in steps S5903 and S5904, the same processing as steps S2502 and S2503 of the AT processing (FIG. 42) in the first embodiment is executed. Specifically, the value of the AT continuation counter 74u in the main RAM 74 is decremented by 1 (step S5903), and it is determined whether the value of the AT continuation counter 74u after decrementing by 1 is "0" (step S5904). If the value of the AT continuation counter 74u is "0" (step S5904: YES), the value of the AT game number counter 141 in the main RAM 74 is cleared to "0" (step S5905). This allows the value of the AT game number counter 141 to be cleared to "0" when the AT state ST5 ends.

Then, in steps S5906 to S5912, processing similar to steps S2504 to S2510 of the AT processing (Figure 42) in the first embodiment is executed. Specifically, if the values of the first ending flag 76b and the second ending flag 76c in the game status area 77 of the main RAM 74 are both "0" (step S5906: NO), the AT status flag 77d in the game status area 77 of the main RAM 74 is cleared to "0" (step S5907). This allows the main MPU 72 to determine that the AT status ST5 has ended. Then, the release game number lottery process is executed by calling a subroutine program called the release game number lottery process using a CALL command (step S5908). Then, the release game number counter setting process is executed (step S5909). In the process of setting the release game number counter, the release game number lottery table 73c (Figure 35(a)) is referenced, and the release game number corresponding to the value of the counter to be judged is set in the release game number counter in the main RAM 74. After that, the value of the counter to be judged is cleared to "0" (step S5910), and the processing for this AT is terminated.

If either the first ending flag 76b or the second ending flag 76c is set to "1" (step S5906: YES), the process for setting the end preparation state ST6 is executed (step S5911). In the process for setting the end preparation state ST6, the AT state flag 77d in the game status area 77 of the main RAM 74 is cleared to "0". In addition, in the process for setting the end preparation state ST6, the end preparation state flag 77e in the game status area 77 of the main RAM 74 is set to "1". Thereafter, the end preparation complete flag in the main RAM 74 is cleared to "0" (step S5912), and the AT process is terminated.

Next, the start-time addition processing executed by the main MPU 72 will be explained with reference to the flowchart in Figure 104. As already explained in the first embodiment above, the start-time addition processing is executed in step S2310 of the advantageous state processing at the start of the game (Figure 40). As with the first embodiment above, the start-time addition processing is executed in AT state ST5.

In the start-up addition process, the image type counter 142 and sound type counter 143 in the main RAM 74 are first cleared to "0" (step S6001). Then, in steps S6002 through S6006, the same instructions as those set in line numbers "1301" through "1305" of the start-up addition process (Figure 69(b)) in the first embodiment are executed. Specifically, the instruction "LD A, (INDXCNT)" is first executed (step S6001). "LD" is the LD instruction as an 8-bit data transfer instruction, "A" is the A register 101b, and "(INDXCNT)" specifies the index value counter 74f in the main RAM 74 as the transfer source. By executing the instruction "LD A, (INDXCNT)" in step S6001, the data in the index value counter 74f is transferred to the A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in A register 101b, and if no index value IV is selected in the role selection process (Figure 18), "0" is set in A register 101b.

Then, the instruction "SUB A, 0BH" is executed (step S6002). "SUB" is the SUB instruction as a subtraction instruction for 8-bit data, "A" is the A register 101b, and "0BH" is one byte of numerical information indicating "11," the minimum value in the first lottery target range ("11" to "15"). By executing the instruction "SUB A, 0BH" in step S6002, an operation is performed to subtract "11" from the value in the A register 101b, and the result of this operation is written to the A register 101b. If a borrow to the most significant bit (the seventh bit) occurs in this operation, the carry flag CF is set to "1." If a borrow to the most significant bit (the seventh bit) does not occur in this operation, the value of the carry flag CF is set to "0." As already explained in the first embodiment with reference to FIG. 69(a), if the value of the index value counter 74f is within the first selection range ("11" to "15"), the value of the A register 101b will be less than "5", and if the value of the index value counter 74f is any of "0" to "10" or "16" to "17", which are not within the first selection range ("11" to "15"), the value of the A register 101b will be "5" or greater.

Then, the instruction "CP A, 05H" is executed (step S6004). "CP" is the CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "05H" is one-byte numerical information indicating a value ("5") that is one greater than "4," which is the value calculated by subtracting "11" from "15," the maximum value in the first selection range ("11" to "15"). By executing the instruction "CP A, 05H" in step S6004, an operation is performed to subtract "5" from the value in the A register 101b. If the value in the A register 101b before the subtraction of "5" is less than "5," i.e., if the value of the index value counter 74f is within the first selection range ("11" to "15"), a borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) in the operation, and the value of the carry flag CF becomes "1." On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or greater, i.e., if the value of the index value counter 74f is "0" to "10" or "16" to "17," which are not included in the first selection range ("11" to "15"), no borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) in the operation, and the value of the carry flag CF becomes "0." The result of the operation to subtract "5" from the value of the A register 101b is not written to the A register 101b. Execution of the instruction "CP A, 05H" does not change the value of the A register 101b. Therefore, the data stored in the A register 101b after the operation to subtract "11" in step S6003 can also be used in step S6008, described below.

Then, the command "RET NC" is executed (step S6005). "RET" is a RET command to return from a subroutine, and "NC" sets the condition for returning from a subroutine, that is, the value of the carry flag CF be "0." By executing the command "RET NC" in step S6005, the start-time bonus processing called in step S2310 of the advantageous state processing at the start of the game (FIG. 40) is terminated, provided that the value of the carry flag CF is "0," and the process returns to step S2311, the next step after step S2310. As described above, if the value of the index value counter 74f is either "0" to "10" or "16" to "17," the process of step S6004 is executed, and the value of the carry flag CF is set to "0." Therefore, by executing the command "RET NC" in step S6005, the start-time addition process ends and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). On the other hand, as described above, if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), the process of step S6004 is executed and the value of the carry flag CF becomes "1". For this reason, even if the command "RET NC" is set in step S6005, the start-time addition process does not end and the process proceeds to the next step S6006.

The command in step S6006 is executed when the AT state ST5 is reached and the role lottery process (Figure 18) has selected an index value IV of any of "11" to "15". In step S6006, the command "LD HL, KSADD01" is executed. "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first add-on lottery table 73d in the main ROM 73. By executing the command "LD HL, KSADD01" in step S6006, the start address of the first add-on lottery table 73d is transferred to the HL register 104. This allows the first add-on lottery table 73d to be set as the lottery table to be referenced in the add-on lottery. In this way, when the AT state ST5 is reached and an index value IV of any of "11" to "15" is selected in the role selection process (Figure 18), the first additional selection table 73d is set as the selection table to be referenced.

Then, the image type counter 142 in the main RAM 74 is set to "1" (step S6007). Then, the command "CP A, 02H" is executed (step S6008). "CP" is a CP command as a comparison command for 8-bit data, "A" is the A register 101b, and "02H" is one byte of numerical information indicating "2," which is the value calculated by subtracting "11" from the index value IV of "13," which is the target of the second or third add-on lottery. By executing the command "CP A, 02H" in step S6008, an operation is performed to subtract "2" from the value in the A register 101b. If the value in the A register 101b before the subtraction of "2" is "2," i.e., if the second or third add-on lottery is the target of the execution, the result of this operation is "0," and the value of the zero flag ZF becomes "1." On the other hand, if the value of A register 101b before subtracting "2" is "0," "1," "3," or "4," i.e., if the first additional lottery is to be executed, the result of the operation will not be "0," and the value of the zero flag ZF will be "0." The result of the operation to subtract "2" from the value of A register 101b is not written to A register 101b. Even if the instruction "CP A, 02H" is executed, the value of A register 101b does not change. For this reason, the operation to subtract "11" is executed in step S6003, and the data stored in A register 101b can also be used in step S6014, described below.

The instruction "JR NZ, ADR162" is then executed (step S6009). "JR" is a two-byte conditional jump instruction, "NZ" specifies the condition for the jump—that the value of the zero flag ZF be "0"—and "ADR162" specifies the program address "ADR162" of step S6015 as the jump destination. The instruction of step S6009 is set to the program address "ADR161." The JR instruction of step S6009 relatively identifies the two-byte jump destination program address (ADR162) based on the program address (ADR161) where the JR instruction is set and the difference information (8 bits) set in the JR instruction. Because the two-byte JR instruction is used to jump to the jump destination program address, the machine code data size of the jump instruction for jumping to the jump destination program address is reduced compared to a configuration using a three-byte JP instruction. "ADR162" is a program address that exists within the range that can be specified as a jump destination program address for the JR command in step S6009, based on the program address (ADR161) where the JR command is set in step S6009. As described above, if the first add-on lottery is to be executed, the zero flag ZF is set to "0" when step S6008 is executed. Therefore, the command "JR NZ, ADR162" is executed in step S6009, causing a jump to the program address "ADR162" in step S6015. On the other hand, as described above, if the second or third add-on lottery is to be executed, the zero flag ZF is set to "1" when step S6008 is executed. Therefore, even if the command "JR NZ, ADR162" is set in step S6009, the program address does not jump, and the program proceeds to the next step, S6010.

In step S6010, the command "LD HL, KSADD02" is executed. "LD" is the LD command as a 16-bit transfer command, "HL" is the content that sets the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second add-on lottery table 73e in the main ROM 73. By executing the command "LD HL, KSADD02" in step S6010, the start address of the second add-on lottery table 73e is transferred to the HL register 104. As a result, the lottery table to be referenced is changed from the first add-on lottery table 73d to the second add-on lottery table 73e.

Then, an image type lottery process is executed (step S6011). In the image type lottery process, the type of cut-in image in the second lottery effect or the third lottery effect is determined using an image type lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74. In the image type lottery process, an image type number of "2" is selected with a probability of 5/16, an image type number of "3" is selected with a probability of 1/4, an image type number of "4" is selected with a probability of 3/16, an image type number of "5" is selected with a probability of 1/8, and an image type number of "6" is selected with a probability of 1/8. Then, a setting process for the image type counter 142 is executed (step S6012). In the image type counter 142 setting process, one of the image type numbers "2" to "6" selected in the image type lottery process (step S6011) is set in the image type counter 142 in the main RAM 74.

Then, the data of the AT game number counter 141 in the main RAM 74 is set in the A register 101b (step S6013). As a result, the number of games with a bet of "3" executed in the AT state ST5 is set in the A register 101b. Then, the instruction "CP A, 0AH" is executed (step S6014). "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "0AH" is one byte of numerical information indicating "10." By executing the instruction "CP A, 0AH" in step S6014, an operation is performed to subtract "10" from the value of the A register 101b. If the value of the A register 101b before the subtraction of "10" is "10," i.e., if the number of games with a bet of "3" executed in the AT state ST5 is "10," the result of this operation is "0," and the value of the zero flag ZF becomes "1." On the other hand, if the value of the A register 101b before the subtraction of "10" is numerical information other than "10," that is, if the number of games with the bet number of "3" played in the AT state ST5 is other than "10," the result of the calculation will not be "0," and the value of the zero flag ZF will be "0."

The processing of step S6015 is executed when a jump to the program address of step S6015 is made by the JR command of step S6009, or when the processing of step S6014 is executed and step S6015 is proceeded to. First, we will explain what happens when a jump to the program address of step S6015 is made by the JR command of step S6009. As described above, in step S6009, if the first additional lottery is to be executed, a jump to the program address of step S6015 is made. In step S6015, the instruction "JR NZ, ADR163" is executed. "JR" is a conditional jump instruction with a word length of 2 bytes, "NZ" specifies the condition that the value of the zero flag ZF is "0" as the jump condition, and "ADR163" specifies the program address "ADR163" of step S6019 as the program address to jump to. The instruction of step S6015 is set to the program address "ADR162." The JR instruction in step S6015 relatively identifies a two-byte jump destination program address (ADR163) based on the program address (ADR162) in which the JR instruction is set and the difference information (8 bits) set in the JR instruction. Because the JR instruction, which has a two-byte word length, is used to jump to the jump destination program address, the machine language data size of the jump instruction for jumping to the jump destination program address is reduced compared to a configuration in which a JP instruction, which has a three-byte word length, is used. As already explained, the value of the zero flag ZF is maintained even when the JR instruction, which is a two-byte conditional jump instruction, is executed. Therefore, if a jump is made from the program address (ADR161) in step S6009 to the program address (ADR162) in step S6015 on the condition that the value of the zero flag ZF is "0," the jump condition of the JR instruction in step S6015 is always satisfied, and a jump is made to the program address (ADR163) in step S6019. "ADR163" is a program address that exists within the range that can be specified as a jump destination program address for the JR instruction based on the program address (ADR162) where the JR instruction is set in step S6015, but is also a program address that does not exist within the range that can be specified as a jump destination program address for the JR instruction based on the program address (ADR161) where the JR instruction is set in step S6009.

Next, we will explain what happens when the processing of step S6014 is executed and the process proceeds to step S6015. As mentioned above, if the number of times a game with a bet of "3" has been executed in AT state ST5 is other than "10," the processing of step S6015 is executed, and the value of the zero flag ZF is set to "0." Therefore, the command "JR NZ, ADR163" is executed in step S6016, and a jump is made to the program address of step S6019, "ADR163." On the other hand, as mentioned above, if the number of times a game with a bet of "3" has been executed in AT state ST5 is "10," the processing of step S6015 is executed, and the zero flag ZF is set to "1." Therefore, even if the command "JR NZ, ADR163" is set in step S6016, the program address does not jump, and the process proceeds to the next step, S6016.

In step S6016, the command "LD HL, KSADD03" is executed. "LD" is the LD command as a 16-bit transfer command, "HL" is the content that sets the HL register 104 as the transfer destination, and "KSADD03" is the start address of the third add-on lottery table 73h in the main ROM 73. By executing the command "LD HL, KSADD03" in step S6016, the start address of the third add-on lottery table 73h is transferred to the HL register 104. As a result, the lottery table to be referenced is changed from the second add-on lottery table 73e to the third add-on lottery table 73h.

Then, a sound type lottery process is executed (step S6017). In the sound type lottery process, the type of lottery sound for the third lottery effect is determined using a sound type lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74. In the sound type lottery process, the sound type number "1" is selected with a probability of 5/16, the sound type number "2" is selected with a probability of 1/4, the sound type number "3" is selected with a probability of 3/16, the sound type number "4" is selected with a probability of 1/8, and the sound type number "5" is selected with a probability of 1/8. Then, a setting process for the sound type counter 143 is executed (step S6018). In the setting process for the sound type counter 143, one of the sound type numbers "1" to "5" selected in the sound type lottery process (step S6017) is set in the sound type counter 143 in the main RAM 74.

When a jump to the program address (ADR163) of step S6019 is made by the JR command of step S6015, or when the processing of step S6018 is executed, a lottery effect command transmission setting process is executed (step S6019). In the lottery effect command transmission setting process, the lottery effect command flag stored in the main RAM 74 is set to "1." The lottery effect command flag is a flag that enables the main MPU 72 to know that a lottery effect command should be sent to the production side MPU 92. By setting the lottery effect command flag to "1," the command output process of step S210 of the timer interrupt processing (Figure 11) executes a process to send the lottery effect command to the production side MPU 92. As already explained, when the production side MPU 92 receives a lottery effect command, it executes display control of the image display device 63 so that a cut-in image corresponding to the image type number set in the lottery effect command is displayed. Additionally, if a sound type number between "1" and "5" is set in the lottery effect command, sound output control of the speaker 62 is executed so that the lottery sound corresponding to that sound type number is output.

Then, similar to line number "1309" in the start-up surcharge processing (Figure 69(b)) in the first embodiment described above, the instruction "JP ADR133" is executed (step S6020). "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is a program address (2 bytes) at which an instruction for executing the processing of step S1802 in the release game number lottery processing (Figure 35(b)) is set. By executing the instruction "JP ADR133" in step S6020, a jump is made to the program address "ADR133." Then, by executing the processing of steps S1802 to S1807 in the release game number lottery processing (Figure 35(b)), one of the first to third surcharge lotteries is executed. As already explained, if the index value IV of "11," "12," "14," or "15" is won in the role lottery process (FIG. 18), a first additional lottery is executed based on the first additional lottery table 73d. Also, if the index value IV of "13" is won in the role lottery process (FIG. 18), a second additional lottery is executed with the second additional lottery table 73e as the reference lottery table, provided that the number of times a game with a bet number of "3" has been executed in the AT state ST5 is other than "10," and a third additional lottery is executed with the third additional lottery table 73h as the reference lottery table, provided that the number of times a game with a bet number of "3" has been executed in the AT state ST5 is "10."

Figure 105 (a) is an explanatory diagram illustrating jump instructions set to jump from program addresses "ADR161" and "ADR162" to program address "ADR163" in the start-time increment processing (Figure 104). As already explained, the range that can be jumped with a JR instruction is the range from "(the program address where the JR instruction is set) + 2 - 128" to "(the program address where the JR instruction is set) + 2 + 127." As mentioned above, "ADR163" is a program address that exists within the range that can be specified as a jump destination program address for the JR instruction based on the program address (ADR162) where the JR instruction is set in step S6015, but is not within the range that can be specified as a jump destination program address for the JR instruction based on the program address (ADR161) where the JR instruction is set in step S6009.

As already explained, the value of the zero flag ZF is maintained even when the JR instruction, a conditional jump instruction with a word length of 2 bytes, is executed. In the start-time increment process (Figure 104), if the value of the zero flag ZF is set to "0" and a jump is made from the program address (ADR161) of step S6009 to the program address (ADR162) of step S6015, the jump condition of the JR instruction in step S6015 is always satisfied, and a jump is made to the program address (ADR163) of step S6019.

Figure 105(b) is an explanatory diagram illustrating jump instructions set to jump from program addresses "ADR161" and "ADR162" to program address "ADR163" in the fifth comparative example of start-up addition processing. In the fifth comparative example of start-up addition processing (Figure 105(b)), the instruction "JP NZ, ADR163" is set for the program address of step S6009, "ADR161." "JP" is a jump instruction with a word length of 3 bytes, "NZ" specifies the condition that the value of the zero flag ZF is "0" as the jump condition, and "ADR163" specifies the program address "ADR163" as the jump destination program address. In the fifth comparative example of start-up addition processing (Fig. 105(b)), the instruction "JP NZ, ADR163" is set to program address "ADR161", so if the value of the zero flag ZF is "0", a jump will occur directly from "ADR161" to program address "ADR163" without passing through program address "ADR162".

As mentioned above, the JR command in step S6015 is a command to jump from program address "ADR162" to program address "ADR163" if the third lottery effect is not to be executed. For this reason, the JR command in step S6015 cannot be omitted even in a configuration in which a direct jump is made from program address "ADR161" to program address "ADR163."

As shown in Figure 105(b), in the fifth comparative example of start-up addition processing (Figure 105(b)), the total word length of the jump instructions set to jump from program addresses "ADR161" and "ADR162" to program address "ADR163" is 5 bytes. In contrast, as shown in Figure 105(a), in the start-up addition processing (Figure 104), the total word length of the jump instructions set to jump from program addresses "ADR161" and "ADR162" to program address "ADR163" is 4 bytes.

As described above, the start-time increment process (Fig. 104) is configured to jump to the program address of step S6015 using a two-byte JR instruction if the value of the zero flag ZF is "0" in step S6009, and then, taking advantage of the fact that the value of the zero flag ZF is maintained even when the JR instruction is executed, jump to the program address "ADR163" using the JR instruction set in the jump destination step S6015. This reduces the total word length of the jump instructions set to jump from program addresses "ADR161" and "ADR162" to program address "ADR163," compared to the fifth comparative example of start-time increment process (Fig. 105(b)), which jumps directly to program address "ADR163" using a three-byte JP instruction if the value of the zero flag ZF is "0" in step S6009. This reduces the data size of the program stored in the main ROM 73 to execute the start-up top-up process (Figure 104).

The present embodiment described above provides the following excellent effects:

The value of the zero flag ZF is maintained even when a JR instruction is executed as a conditional jump instruction with a word length of 2 bytes. The start-time increment process (Fig. 104) jumps to the program address of step S6015 using a JR instruction with a word length of 2 bytes, on the condition that the value of the zero flag ZF is "0" in step S6009. Taking advantage of the fact that the value of the zero flag ZF is maintained even when a JR instruction is executed, the process jumps to the program address "ADR163" using the JR instruction set in the jump destination step S6015. This reduces the total word length of the jump instructions set to jump from program addresses "ADR161" and "ADR162" to program address "ADR163," compared to the processing configuration in the fifth comparative example of start-up top-up processing (FIG. 105(b)), in which a 3-byte word-length JP instruction is used to jump directly to program address "ADR163" on the condition that the value of the zero flag ZF is "0" in step S6009. Therefore, the data size of the program stored in main ROM 73 for executing start-up top-up processing (FIG. 104) can be reduced.

<Thirteenth embodiment>
This embodiment differs from the first embodiment in that the lottery execution process is called by a CALL command. The following describes the configuration that differs from the first embodiment. Note that the description of the same configuration as the first embodiment will be omitted.

In this embodiment, the start-up bonus processing is configured to call the processing of steps S1802 to S1807 of the release game number lottery processing (Figure 35(b)) as processing of a subroutine called lottery execution processing. In this embodiment, even in the release game number lottery processing (Figure 35(b)), after processing of step S1801 is executed, processing of the subroutine called lottery execution processing is called.

Figure 106(a) is an explanatory diagram for explaining the program contents of the start-up addition processing in this embodiment. As already explained in the first embodiment above, the start-up addition processing is executed in step S2310 of the advantageous state processing at the start of the game (Figure 40). As in the first embodiment above, the start-up addition processing is executed in AT state ST5. As shown in Figure 106(a), this program has line numbers set to "1601" to "1609". Program instructions are executed in order from lowest to highest line number, except when a call instruction or jump instruction is executed.

Lines "1601" to "1608" execute the same processing as lines "1301" to "1308" of the start-up addition processing (Figure 69(b)) in the first embodiment described above. The instruction "LD A, (INDXCNT)" is set in line "1601." "LD" is the LD instruction as an instruction to transfer 8-bit data, "A" is the A register 101b, and "(INDXCNT)" specifies the index value counter 74f in the main RAM 74 as the transfer source. Execution of the instruction "LD A, (INDXCNT)" in line "1601" transfers the data in the index value counter 74f to the A register 101b. As a result, if any of the index values IV "1" to "17" is selected in the role selection process (Figure 18), that index value IV is set in A register 101b, and if no index value IV is selected in the role selection process (Figure 18), "0" is set in A register 101b.

The instruction "SUB A, 0BH" is set in line number "1602." "SUB" is a SUB instruction that subtracts 8-bit data, "A" is the A register 101b, and "0BH" is one byte of numerical information indicating "11," the minimum value in the first lottery range ("11" to "15"). By executing the instruction "SUB A, 0BH" in line number "1602," an operation is performed to subtract "11" from the value in A register 101b, and the result of this operation is written to A register 101b. If a borrow to the most significant bit (the seventh bit) occurs in this operation, the carry flag CF is set to "1." If a borrow to the most significant bit (the seventh bit) does not occur in this operation, the value of the carry flag CF is set to "0." As already explained with reference to Figure 69 (a) in the first embodiment above, if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), the value of the A register 101b will be less than "5", and if the value of the index value counter 74f is any of "0" to "10" or "16" to "17", which are not within the first lottery target range ("11" to "15"), the value of the A register 101b will be "5" or greater. Furthermore, as already explained in the first embodiment with reference to FIG. 69(a), if the value of the index value counter 74f is any of "11" to "13", which is included in the first selection target range ("11" to "15") but not included in the second selection target range ("14" to "15"), the value of the A register 101b will be less than "3", and if the value of the index value counter 74f is "14" or "15", which is included in the first selection target range ("11" to "15") and also included in the second selection target range, the value of the A register 101b will be a value of "3" or greater.

The instruction "CP A, 05H" is set on line number "1603." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "05H" is one byte of numerical information indicating a value ("5") that is "1" greater than "4," which is the value calculated by subtracting "11" from "15," the maximum value in the first lottery target range ("11" to "15"). Executing the instruction "CP A, 05H" on line number "1603" performs an operation to subtract "5" from the value in A register 101b. If the value of the A register 101b before the subtraction of "5" is less than "5," i.e., if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), a borrow occurs to the most significant bit (the seventh bit of the zeroth to seventh bits) in the operation, and the value of the carry flag CF becomes "1." On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or greater, i.e., if the value of the index value counter 74f is one of "0" to "10" or "16" to "17," which are not within the first lottery target range ("11" to "15"), a borrow does not occur to the most significant bit (the seventh bit of the zeroth to seventh bits) in the operation, and the value of the carry flag CF becomes "0." The result of the operation of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even when the instruction "CP A, 05H" is executed, the value of A register 101b does not change. Therefore, the operation to subtract "11" is performed on line number "1602", and the data stored in A register 101b can be used on line number "1606", which will be described later.

The instruction "RET NC" is set in line number "1604." "RET" is a RET instruction to return from a subroutine, and "NC" sets the condition for returning from a subroutine, that is, the value of the carry flag CF be "0." Execution of the instruction "RET NC" in line number "1604" terminates the start-time bonus processing called in step S2310 of the advantageous state processing at the start of the game (FIG. 40), provided that the value of the carry flag CF is "0," and returns to step S2311, the next step after step S2310. As described above, if the value of the index value counter 74f is "0" to "10" or "16" to "17," which are not included in the first lottery target range ("11" to "15"), the instruction in line number "1603" is executed, and the value of the carry flag CF becomes "0." Therefore, by executing the command "RET NC" in line number "1604", the start-time addition process ends and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). On the other hand, as described above, if the value of the index value counter 74f is within the first lottery target range ("11" to "15"), the command in line number "1603" is executed and the value of the carry flag CF becomes "1". Therefore, even if the command "RET NC" is set in line number "1604", the start-time addition process does not end and the process proceeds to the next line number "1605".

The command in line number "1605" is executed when the AT state is ST5 and the index value IV in the first selection range ("11" to "15") is selected in the role selection process (Figure 18). The command "LD HL, KSADD01" is set in line number "1605." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first additional selection table 73d in the main ROM 73. By executing the command "LD HL, KSADD01" in line number "1605," the start address of the first additional selection table 73d is transferred to HL register 104. This allows the first additional selection table 73d to be set as the selection table to be referenced in the additional selection. In this way, when the AT state ST5 is active and the index value IV in the first selection range ("11" to "15") is selected in the role selection process (Figure 18), the first additional selection table 73d is set as the selection table to be referenced.

The instruction "CP A, 03H" is set in row number "1606." "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is A register 101b, and "03H" is one byte of numerical information indicating the value ("3") calculated by subtracting "11" from "14," the minimum value in the second lottery target range ("14" to "15"). As described above, A register 101b stores one byte of numerical information calculated by subtracting "11" in row number "1602." The instruction in row number "1606" is executed when the index value IV in the first lottery target range ("11" to "15") is selected in the role selection process (Figure 18), and therefore the value in A register 101b is either "0" to "4." Execution of the instruction "CP A, 03H" on line number "1606" performs an operation to subtract "3" from the value of the A register 101b. As already explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. If the value of the A register 101b before the subtraction of "3" is less than "3," that is, if the value of the index value counter 74f is one of "11" to "13," which is not included in the second lottery target range ("14" to "15"), a borrow occurs to the most significant bit (the seventh bit of the 0th to 7th bits) in the operation, causing the value of the carry flag CF to become "1," and the value of the jump flag JF also to become "1." On the other hand, if the value of the A register 101b before the subtraction of "3" is "3" or greater, that is, if the value of the index value counter 74f is "14" or "15", which is included in the second lottery target range, no borrow occurs to the most significant bit (the seventh bit of bits 0 to 7) in the calculation, so the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0".

The instruction "JRS 1, ADR172" is set at line number "1607." "JRS" is a conditional jump instruction with a word length of 1 byte, "1" sets the jump condition to a value of "1" for the jump flag JF, and "ADR172" sets the program address "ADR172" at line number "1609" as the jump destination. The instruction at line number "1607" is set to program address "ADR171." As already explained, the range that can be jumped with the JRS instruction is from "(the program address where the JRS instruction is set) + 1 - 16" to "(the program address where the JRS instruction is set) + 1 + 15." As shown in Figure 106 (a), the word length of the instruction set at the program address between program addresses "ADR171" and "ADR172" (the LD instruction on line number "1608") is 3 bytes. "ADR172" is "(ADR171) + 1 + 3", and is a program address that can be specified as the program address to jump to in the JRS instruction based on the program address (ADR171) where the JRS instruction on line number "1607" is set.

As described above, if the value of the index value counter 74f is any of "11" to "13," which is within the first lottery target range ("11" to "15") but not within the second lottery target range ("14" to "15"), the instruction at line number "1606" is executed, causing the value of the jump flag JF to be set to "1." Therefore, the instruction "JRS 1, ADR172" is executed at line number "1607," causing a jump to the program address "ADR172" at line number "1609." On the other hand, as described above, if the value of the index value counter 74f is "14" or "15," which is within the first lottery target range ("11" to "15") and also within the second lottery target range ("14" to "15"), the instruction at line number "1606" is executed, causing the value of the jump flag JF to be set to "0." Therefore, even if the instruction "JRS 1, ADR172" is set on line number "1607", the program address will not jump and will proceed to the next line number "1608".

The command at line number "1608" is executed when the AT state is ST5 and the index value IV in the second lottery target range ("14" to "15") is selected in the role lottery process (Figure 18). The command "LD HL, KSADD02" is set in line number "1608." "LD" is the LD command as a 16-bit transfer command, "HL" sets the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second additional lottery table 73e (Figure 43 (b)) in the main ROM 73. When the command "LD HL, KSADD02" is executed in line number "1608," the start address of the second additional lottery table 73e is transferred to the HL register 104. This allows the reference lottery table to be changed from the first add-on lottery table 73d to the second add-on lottery table 73e, which is more advantageous to the player than the first add-on lottery table 73d. In this way, when the AT state ST5 is reached and the index value IV in the second lottery target range ("14" to "15") is won in the role lottery process (Figure 18), the second add-on lottery table 73e is set as the reference lottery table in the add-on lottery.

The command set in line number "1609" is executed when a jump to line number "1609" is made by the JRS command in line number "1607," or when the LD command in line number "1608" is executed and the program proceeds to line number "1609." Specifically, in AT state ST5, if the role selection process (Figure 18) selects an index value IV that is included in the first selection target range ("11" to "15") but not included in the second selection target range ("14" to "15"), the JRS command in line number "1607" jumps to the program address of line number "1609," and the command in line number "1609" is executed. Also, in AT state ST5, if the index value IV is selected in the role selection process (Figure 18) and is included in both the first selection target range ("11" to "15") and the second selection target range ("14" to "15"), the LD command in line number "1608" is executed, and then the command in line number "1609" is executed.

The command "CALL TYSJSR" is set in line number "1609." "TYSJSR" is the lottery execution process (the number of games to be unlocked lottery process (steps S1802 to S1807 in Figure 35(b))), and "CALL" is a CALL command that calls the subroutine of the lottery execution process. Executing the command "CALL TYSJSR" in line number "1609" calls the subroutine of the lottery execution process. By executing the lottery execution process, if the index value IV of any of "11" to "13" is won in the role lottery process (Figure 18), an additional lottery is executed based on the first additional lottery table 73d, and if the index value IV of "14" or "15" is won in the role lottery process (Figure 18), an additional lottery is executed based on the second additional lottery table 73e.

Figure 106(b) is an explanatory diagram illustrating the instructions set to call the lottery execution process in the start-time addition process ( Figure 106(a)). As shown in Figure 106(b), in the start-time addition process ( Figure 106(a)), on the condition that the value of the jump flag JF is "1", a conditional jump instruction with a word length of 1 byte, JRS instruction set on line number "1607", jumps to the program address (ADR172) on line number "1609", and the lottery execution process is called by a CALL instruction with a word length of 3 bytes set on line number "1609" at the jump destination. The total word length of the instructions set on line numbers "1607" and "1609" to call the lottery execution process is 4 bytes.

Figure 106 (c) is an explanatory diagram illustrating the command set to call the lottery execution process in the sixth comparative example of the start-time surcharge process. As shown in Figure 106 (c), in the sixth comparative example of the start-time surcharge process, the command "CALL TYSJSR" is set in line number "1607", just like in line number "1609". In the sixth comparative example of the start-time surcharge process, the total word length of the commands set in line numbers "1607" and "1609" to call the lottery execution process is 6 bytes.

The start-time addition process (Fig. 106(a)) is configured to jump to the program address (ADR172) at line number "1609" using the JRS instruction, a conditional jump instruction with a word length of 1 byte set at line number "1607," on the condition that the value of the jump flag JF is "1," and then call the lottery execution process using a CALL instruction with a word length of 3 bytes set at the jump destination, line number "1609." This reduces the total word length of the instructions set to call the lottery execution process, compared to the sixth comparative example of start-time addition process (Fig. 106(c)), in which a CALL instruction with a word length of 3 bytes is also set at line number "1607" to call the lottery execution process.

The present embodiment described above provides the following excellent effects:

The start-up surcharge process (Fig. 106(a)) is configured to jump to the program address (ADR172) at line number "1609" using the JRS instruction, a conditional jump instruction with a word length of 1 byte set at line number "1607," on the condition that the value of the jump flag JF is "1," and then call the lottery execution process using a CALL instruction with a word length of 3 bytes set at the jump destination, line number "1609." This reduces the total word length of the instructions set to call the lottery execution process compared to the sixth comparative example of the start-up surcharge process (Fig. 106(c)), in which a CALL instruction with a word length of 3 bytes is also set at line number "1607" to call the lottery execution process. This reduces the data size of the program stored in main ROM 73 to execute the start-up surcharge process.

<Other Embodiments>
The present invention is not limited to the contents of the above-described embodiments, and various modifications and improvements are possible within the scope of the spirit of the present invention. For example, the following changes may be made. The configurations of the following alternative embodiments may be applied individually to the configurations of the above-described embodiments, or may be applied in combination. The configurations of the above-described embodiments may be applied in combination with each other, and the configurations of the following alternative embodiments may be applied individually or in combination with a configuration obtained by combining the configurations of the above-described embodiments with each other.

(1) In each of the above embodiments, the stay ratio for the second section SC2 may be calculated for each set value, and the dual-purpose display unit 66 may display a ratio corresponding to the calculation result data of the stay ratio for the second section SC2 at each set value. The main RAM 74 is provided with a total game counter corresponding to set values of "1" to "6" and a second section game counter corresponding to set values of "1" to "6." When an operation to start the ratio display is performed, a calculation is first performed to calculate the stay ratio for the second section SC2 at the set value of "1" by referencing the total game counter corresponding to the set value of "1" and the second section game counter corresponding to the set value of "1," and the calculation result data is set in the ratio display counter 74n. This starts the ratio display corresponding to the set value of "1" on the dual-purpose display unit 66. If an operation to update the ratio display is then performed (e.g., by operating one of the stop buttons 42 to 44), the referenced total game counter and second section game counter are updated. Then, by referencing the total game count counter and second interval game count counter that are referenced after the update, a calculation is performed to calculate the stay ratio for the second interval SC2 at the set value "n" (n is an integer between 1 and 6), and the calculation result data is set in the ratio display counter 74n. This causes the dual-purpose display unit 66 to begin displaying the ratio corresponding to the set value "n." Each time the ratio display update operation is performed, the dual-purpose display unit 66 updates the set value that is the target of the ratio display in the following order: "1" → "2" → "3" → "4" → "5" → "6" → "1." This makes it possible to check the stay ratio for the second interval SC2 at each set value based on the ratio display on the dual-purpose display unit 66.

(2) In each of the above embodiments, the most significant bit of data in a memory area set in the address range of "0001H" to "0006H" in the main RAM 74 may be aggregated in a register (e.g., B register 102a) of the main MPU 72, and the aggregated data in that register may be set in the transmission standby buffer 112. This makes it possible to set the most significant aggregated frame SF in the start command and end command without having to provide a memory area in the main RAM 74 for aggregating the most significant bit of data in a memory area set in the address range of "0001H" to "0006H."

(3) In the first embodiment, the number of data transfers may be determined by referencing the bit designation counter 117 during the top-level aggregation process (Figure 51). Specifically, during the top-level aggregation process, after the most significant bit of data in the source memory area is transferred to the destination bit, it is determined whether the value of the bit designation counter 117 is "5." If the value of the bit designation counter 117 is "5," the top-level aggregation process is terminated. As already explained in the first embodiment, the value of the bit designation counter 117 is incremented by one and updated each time the process of transferring the most significant bit of data in the source memory area to the destination bit is executed. Therefore, if the value of the bit designation counter 117 is "5" after the process of transferring the most significant bit of data in the source memory area to the destination bit is executed, this means that the most significant bit of data in the memory area set in the address range of "0001H" to "0006H" in the main RAM 74 is set to bits 0 to 5 of the top-level aggregation area 74v. In this way, by configuring the number of data transfers to be known by referencing the bit designation counter 117, the processing configuration for the top-level aggregation process can be simplified.

(4) In the first embodiment described above, the process of transferring data stored in the most significant bit of a storage area included in the transfer target range in the top-level aggregation process may be configured to be executed using information previously set in a general-purpose register. Specifically, the address of the source storage area is set in the BC register 102, and information on the number of transfers is set in the E register 103b. The address of the destination storage area is set in the HL register 104, and information on the destination bit is set in the D register 103a. The main RAM 74 does not have a dedicated storage area for setting the address of the source storage area, information on the number of transfers, the address of the destination storage area, and information on the destination bit. In the process of transferring data stored in the most significant bit of a storage area included in the transfer target range in the top-level aggregation process, the main MPU 72 can determine the address of the source storage area based on the data set in the BC register 102, and can determine information on the number of transfers based on the data set in the E register 103b. Furthermore, the address of the destination storage area can be determined based on the data set in the HL register 104, and the destination bit information can be determined based on the data set in the D register 103a. In this way, the address of the source storage area, information on the number of transfers, the address of the destination storage area, and the destination bit information are set in general-purpose registers, and by not providing a dedicated storage area in the main RAM 74 for setting this information, the amount of storage space required for the main RAM 74 can be reduced.

(5) In the first embodiment described above, the process of transferring data stored in a storage area included in the transfer range in the common command transmission process to the transmission standby buffer 112 may be performed using information previously set in a general-purpose register. Specifically, the address of the source storage area is set in the BC register 102, and the number of transfers is set in the E register 103b. The main RAM 74 does not have a dedicated storage area for setting the address of the source storage area and the number of transfers. In the process of transferring data stored in a storage area included in the transfer range in the common command transmission process to the transmission standby buffer 112, the main MPU 72 can determine the address of the source storage area based on the data set in the BC register 102 and the number of transfers based on the data set in the E register 103b. In this way, by setting the address of the source storage area and the number of transfers in a general-purpose register and not providing a dedicated storage area in the main RAM 74 for setting this information, the storage capacity required for the main RAM 74 can be reduced.

(6) In the fifth embodiment described above, in addition to the data stored in the memory area of the primary RAM 74 identified by the addresses set in the first setting range and second setting range of the common data table 73f (Figure 79(a)), data stored in the memory area of the primary RAM 74 identified by the addresses set in the first exclusion range may also be set in the start command. This allows the address range in the common data table 73f, in which addresses specifying the memory area of the primary RAM 74 in which data is set in the start command, to be part of the address range ("9101H" to "911AH") in which the common data table 73f is set, and also the continuous address range of "9101H" to "9114H". This simplifies the processing configuration for setting data stored in the memory area of the primary RAM 74 in the start command. Furthermore, in addition to the data stored in the memory area of the main RAM 74 specified by the addresses set in the third and fourth setting ranges of the common data table 73f (FIG. 79(a)), data stored in the memory area of the main RAM 74 specified by the addresses set in the fourth exclusion range may also be set in the termination command. This allows the address range in the common data table 73f, in which addresses specifying the memory area of the main RAM 74 in which data is set in the termination command, to be part of the address range ("9101H" to "911AH") in which the common data table 73f is set, and also the continuous address range "9105H" to "911AH". This simplifies the processing configuration for setting data stored in the memory area of the main RAM 74 in the termination command.

(7) In the sixth embodiment described above, the first aggregation range and the second aggregation range in the common data table 73g (Figure 84 (a)) may be configured to be set in consecutive address ranges. Specifically, the data stored in the lower and upper areas of the AT continuation counter 74u are also configured to be set in the end command, and the performance side MPU 92 uses the data stored in the lower and upper areas of the AT continuation counter 74u in the end reception response processing. In this configuration, in the common data table 73g, the address of the bet number setting counter 74b is set in the address range of "9101H" to "9102H", the address of the stop order type counter 74m is set in the address range of "9103H" to "9104H", the address of the game status area 77 is set in the address range of "9105H" to "9106H", the address of the top-level aggregation area 74v is set in the address range of "9107H" to "9108H", the address of the lower area of the AT continuation counter 74u is set in the address range of "9109H" to "910AH", and the address of the upper area of the AT continuation counter 74u is set in the address range of "910BH" to "910CH". In this configuration, the address of the memory area of the main RAM 74 where the data to be set in the start command is stored is set in the consecutive address range of "9101H" to "910CH". Of the storage areas in the main RAM 74 where data to be set in the start command is stored, the addresses of the storage areas where the most significant bit of data is set in the top-level aggregation area 74v are set in the consecutive address range of "9109H" to "910CH". This simplifies the processing configuration for setting the data stored in the storage areas of the main RAM 74 in the start command. The addresses of the storage areas in the main RAM 74 where data to be set in the end command is stored are set in the consecutive address range of "9105H" to "911AH". Of the storage areas in the main RAM 74 where data to be set in the end command is stored, the addresses of the storage areas where the most significant bit of data is set in the top-level aggregation area 74v are set in the consecutive address range of "9109H" to "9114H". This simplifies the processing configuration for setting the data stored in the storage areas of the main RAM 74 in the end command. In this way, by setting the first aggregation range, in which the addresses of the lower and upper areas of the AT continuation counter 74u are set, to the address range of "9109H" to "910CH," the first aggregation range and second aggregation range can be set to the continuous address range of "9109H" to "9114H." This simplifies the processing configuration for aggregating the most significant bit of data in the storage areas of the main RAM 74 included in the first and second aggregation ranges into the most significant aggregation area 74v.

(8) In the first to fourth embodiments described above, when the production-side MPU 92 receives an end command, it may be configured to execute end-time reception-related processing using all of the information set in the end command, and when the production-side MPU 92 receives a start command, it may be configured to execute start-time reception-related processing using only a portion of the information set in the start command.

(9) In the first to fourth embodiments described above, even if the received start command contains data that is not used in the start reception processing, the production side MPU 92 may store the received start command as is in the command storage buffer 126 of the production side RAM 94 without performing the process of extracting only the data necessary for the start reception processing from the start command. Furthermore, even if the received end command contains data that is not used in the end reception processing, the production side MPU 92 may store the received end command as is in the command storage buffer 126 of the production side RAM 94 without performing the process of extracting only the data necessary for the end reception processing from the end command. This reduces the processing load on the production side MPU 92 until the received start command is stored in the command storage buffer 126, and shortens the time required from when the start command is received until the start command is stored in the command storage buffer 126 and becomes available for use by the production side MPU 92. It is also possible to reduce the processing load on the production-side MPU 92 until the received termination command is stored in the command storage buffer 126, and to shorten the time required from when the termination command is received until the termination command is stored in the command storage buffer 126 and becomes available for use by the production-side MPU 92.

(10) In the first to fourth embodiments described above, a converted start command including the first to fifteenth frames FR1 to FR15 of the start command may be generated, or a converted end command including the first to fifteenth frames FR1 to FR15 of the end command may be generated. When the production-side MPU 92 receives a start command, it generates a converted start command by setting the data of bits 0 to 5 in the most significant aggregated frame SF included in the start command to the most significant bits of the corresponding second to seventh frames FR2 to FR7, and stores the generated converted start command in the command storage buffer 126. This reduces the processing load on the production-side MPU 92 for converting the start command into a converted start command, while making the converted start command available to the production-side MPU 92, in which the most significant bits of the second to seventh frames FR2 to FR7 may be set to "1."

When the production side MPU 92 receives an end command, it generates a converted end command by setting the data in bits 0 through 5 of the most significant aggregated frame SF included in the end command to the most significant bit of the corresponding second through seventh frames FR2 through FR7, and stores the generated converted end command in the command storage buffer 126. This reduces the processing load on the production side MPU 92 for converting the end command into a converted end command, while making the converted end command, in which the most significant bit of the second through seventh frames FR2 through FR7 may be set to "1," available to the production side MPU 92.

(11) In the common command transmission process in the first to third embodiments, a process may be executed in which data stored in a storage area included in the transfer target range in the common command transmission process is set in the transmission standby buffer 112 based on the end address of the transfer target range and information on the number of transfers in the common command transmission process. Specifically, in the first embodiment, the end address of the transfer target range ("0001H" to "000DH") in the common command transmission process (Figure 50) is set to "000DH" in the transfer source counter 116 of the primary RAM 74, and "13", the number of storage areas included in the transfer target range, is set to the transfer count counter 114 of the primary RAM 74. Steps S2811 to S2816 are then repeatedly executed until the value of the transfer count counter 114 becomes "0". In this configuration, when the transfer source storage area is updated in step S2816, the value of the transfer source counter 116 is decremented by 1. As a result, in step S2816, the address of the storage area that serves as the transfer source area can be updated in the following order: "000DH" → "000CH" → "000BH" → ... → "0002H" → "0001H." In this way, when the end address of the transfer range and information on the number of transfers in the common command transmission process are set, the processing of steps S2811 to S2816 can be repeatedly executed until the value of the transfer count counter 114 reaches "0." This also allows the data stored in the storage area included in the transfer range to be set in the transmission standby buffer 112.

(12) In the top-level aggregation process in the first to third embodiments, a process may be performed to aggregate data stored in the most significant bits of the storage areas included in the transfer target range in the top-level aggregation process into the top-level aggregation area 74v based on the end address of the transfer target range and the number of transfers. Specifically, in the first embodiment, the end address of the transfer target range (0001H to 0006H) in the top-level aggregation process (Figure 51) is set to "0006H" in the transfer source counter 116 of the primary RAM 74, and the number of storage areas included in the transfer target range, "6," is set in the transfer count counter 114 of the primary RAM 74. Steps S2906 to S2910 are then repeatedly executed until the value of the transfer count counter 114 becomes "0." In this configuration, when the source storage area is updated in step S2909, the value of the transfer source counter 116 is decremented by 1. As a result, in step S2909, the address of the storage area that will be the transfer source area can be updated in the following order: "0006H" → "0005H" → "0004H" → ... → "0002H" → "0001H." In this way, with the end address of the transfer target range and information on the number of transfers in the top-level aggregation process set, the processing of steps S2906 to S2910 can be repeatedly executed until the value of the transfer count counter 114 reaches "0." This also allows the data stored in the storage area included in the transfer target range to be set in the send standby buffer 112.

(13) In the common command transmission process (Figure 86) in the sixth embodiment described above, when a start command is transmitted, a process is executed to set the data stored in the memory area of the main RAM 74 included in the 11th setting target range in the transmission standby buffer 112 based on the start address of the memory area at the end of the 11th setting range in the common data table 73g and information on the number of transfers; and when an end command is transmitted, a process is executed to set the data stored in the memory area of the main RAM 74 included in the 12th setting target range in the transmission standby buffer 112 based on the start address of the memory area at the end of the 12th setting range in the common data table 73g and information on the number of transfers. Specifically, when sending a start command, "910BH," which is the start address of the storage area at the end ("910BH" to "910CH") of the eleventh setting range ("9101H" to "910CH"), is set in the transfer source address counter 132 of the primary RAM 74, and "6," which is the number of storage areas in the primary RAM 74 included in the eleventh setting range, is set in the transfer count counter 114 of the primary RAM 74. Then, the processes of steps S4915 to S4920 are repeatedly executed until the value of the transfer count counter 114 becomes "0." In this configuration, when the transfer source storage area is updated in step S4920, the value of the transfer source address counter 132 is decremented by 2. As a result, in step S4920, when a start command is sent, the addresses stored in the transfer source address counter 132 are updated in the order of "910BH" → "9109H" → ... → "9103H" → "9101H." In this way, when the start address of the storage area at the end of the eleventh setting range and the information on the number of transfers are set, the processing of steps S4915 to S4920 is repeatedly executed until the value of the transfer number counter 114 becomes "0," so that the data stored in the storage area of the main RAM 74 included in the eleventh setting range can be set in the transmission standby buffer 112. Furthermore, when sending a termination command, "9119H," which is the start address of the storage area at the end ("9119H" to "911AH") of the twelfth setting range ("9109H" to "911AH"), is set in the transfer source address counter 132 of the primary RAM 74, and "9," which is the number of storage areas in the primary RAM 74 included in the twelfth setting range, is set in the transfer count counter 114 of the primary RAM 74. Then, the processes of steps S4915 to S4920 are repeatedly executed until the value of the transfer count counter 114 becomes "0." As described above, in this configuration, when the transfer source storage area is updated in step S4920, the value of the transfer source address counter 132 is decremented by 2. As a result, in step S4920, when sending the termination command, the addresses stored in the transfer source address counter 132 are updated in the following order: "9119H" → "9117H" → ... → "910BH" → "9109H." In this way, when the start address of the storage area at the end of the 12th setting range and information on the number of transfers are set, the processing of steps S4915 to S4920 is repeatedly executed until the value of the transfer count counter 114 becomes "0." This also makes it possible to set the data stored in the storage area of the main RAM 74 included in the 12th setting range in the transmission standby buffer 112.

(14) In the top-level aggregation process (Figure 87) in the sixth embodiment described above, when a start command is sent, a process is executed to set the data stored in the most significant bit of the memory area of the main RAM 74 included in the first aggregation range to the top-level aggregation area 74v based on the start address of the memory area at the end of the first aggregation range in the common data table 73g and information on the number of transfers; and when an end command is sent, a process is executed to set the data stored in the most significant bit of the memory area of the main RAM 74 included in the second aggregation range to the top-level aggregation area 74v based on the start address of the memory area at the end of the second aggregation range in the common data table 73g and information on the number of transfers. Specifically, when a start command is sent, "9103H," which is the start address of the storage area at the end ("9103H" to "9104H") of the first aggregation range ("9101H" to "9104H"), is set in the transfer source address counter 132 of the primary RAM 74, and "2," which is the number of storage areas in the primary RAM 74 included in the first aggregation range, is set in the transfer count counter 114 of the primary RAM 74. Then, steps S5009 to S5013 are repeatedly executed until the value of the transfer count counter 114 becomes "0." In this configuration, when the transfer source storage area is updated in step S5012, the value of the transfer source address counter 132 is decremented by 2. As a result, in step S5012, when a start command is sent, the addresses stored in the transfer source address counter 132 are updated in the order of "9103H" → "9101H." In this way, when the start address and transfer count information of the storage area at the end of the first aggregation range are set, the processing of steps S5009 to S5013 is repeatedly executed until the value of the transfer count counter 114 reaches "0." This also allows data stored in the storage area of the primary RAM 74 included in the first aggregation range to be set in the transmission standby buffer 112. Furthermore, when sending a termination command, the start address of the storage area at the end ("9113H" to "9114H") of the second aggregation range ("910DH" to "9114H"), "9113H," is set in the transfer source address counter 132 of the primary RAM 74, and the number of storage areas of the primary RAM 74 included in the second aggregation range, "4," is set in the transfer count counter 114 of the primary RAM 74. The processing of steps S5009 to S5013 is then repeatedly executed until the value of the transfer count counter 114 reaches "0." As described above, in this configuration, when the source storage area is updated in step S5012, the value of the source address counter 132 is decremented by 2. As a result, when sending the termination command in step S5012, the addresses stored in the source address counter 132 are updated in the following order: "9113H" → "9111H" → "910FH" → "910DH." In this way, when the start address of the storage area at the end of the second aggregation range and information on the number of transfers are set, the processing of steps S5009 to S5013 is repeatedly executed until the value of the transfer count counter 114 becomes "0." This also allows the data stored in the storage area of the primary RAM 74 included in the second aggregation range to be set in the transmission standby buffer 112.

(15) In each of the above embodiments, a command (e.g., a start command and an end command) sent from the master MPU 72 to the production MPU 92 may have the most significant bit of the frame (first frame FR1) in which header HD data is set set to "0," and the most significant bit of frames other than the frame in which header HD data is set set to "1." Even in this configuration, it is possible to distinguish between frames in which header HD data is set and frames other than frames in which header HD data is set based on the most significant bit data in the frame.

(16) In each of the above embodiments, a command (e.g., a start command and an end command) sent from the master MPU 72 to the production MPU 92 may be configured such that a bit set to "0" or "1" that enables distinction between a frame in which Header HD data is set (first frame FR1) and a frame other than a frame in which Header HD data is set is set in any of bits 0 through 6. Specifically, the least significant bit (bit 0) of a frame in which Header HD data is set is set to "1," and the least significant bit (bit 0) of a frame other than a frame in which Header HD data is set is set to "0." Even with this configuration, it is possible to distinguish between a frame in which Header HD data is set and a frame other than a frame in which Header HD data is set based on the data in the least significant bit of the frame.

(17) In each of the above embodiments, the configuration is not limited to one in which an address is set for each 1-byte storage area in the main RAM 74, and an address may be set for each multi-byte storage area. Specifically, the main RAM 74 is provided with multiple 2-byte storage areas, and an address is set for each 2-byte storage area in the main RAM 74. As already explained in the first embodiment above, the commands (specifically, start commands and end commands) sent from the main MPU 72 to the performance MPU 92 include multiple 1-byte frames FRm. The information stored in the 2-byte storage area in the main RAM 74 is set across two consecutive frames in the command. Note that the main RAM 74 may be provided with multiple storage areas each consisting of a predetermined number of bytes, 3 or more bytes, and an address may be set for each storage area of the predetermined number of bytes in the main RAM 74.

(18) In each of the above embodiments, the data capacity of the address set for each 1-byte storage area in the main RAM 74 is not limited to 2 bytes; the data capacity of the address may be smaller than 2 bytes, or may be larger than 2 bytes. By setting an address with a number of bytes greater than 2 (e.g., 3 bytes) for each 1-byte storage area in the main RAM 74, the number of 1-byte storage areas that can be provided in the main RAM 74 can be increased. Furthermore, by setting an address with a number of bytes less than 2 (e.g., 1 byte) for each 1-byte storage area in the main RAM 74, the data capacity of the addresses set in the common data tables 73f, 73g that are referenced when sending start commands and end commands can be reduced, and the data capacity of the common data tables 73f, 73g can also be reduced.

(19) In each of the above embodiments, a configuration may be adopted in which bits other than the most significant bit in a one-byte storage area provided in the main RAM 74 are aggregated. Specifically, the main RAM 74 is provided with the following one-byte storage areas: a second section area in which the second section flag 76a is set in the least significant bit (bit 0 of bits 0 to 7); a first ending area in which the first ending flag 76b is set in the least significant bit; and a second ending area in which the second ending flag 76c is set in the least significant bit. These three areas are provided in consecutive address ranges in the main RAM 74. When the main MPU 72 sets the data stored in the second section flag 76a, the first ending flag 76b, and the second ending flag 76c in a command to be sent to the production MPU 92, the main MPU 72 generates one-byte aggregated data that aggregates the information stored in the least significant bits of the three areas provided in consecutive address ranges in the main RAM 74, and sets the aggregated data in the command. This reduces the data volume of the command sent to the production side MPU 92 compared to when the total of three bytes of data stored in these three areas is set as the command.

(20) In each of the above embodiments, information indicating the type of command sent from the master MPU 72 to the production MPU 92 (data in the header HD) may be set in a frame other than the first frame. Specifically, information indicating that it is a start command may be set in the last frame of the start command. In this configuration, too, by setting the most significant bit of the first frame of the start command to "1" and the most significant bit of frames other than the first to "0," it is possible to identify whether or not a frame is the first frame based on the information stored in the most significant bit.

(21) In the seventh embodiment, the trigger for initiating the all-off state of the dual-purpose display unit 66 is not limited to the event of the game starting. Specifically, the all-off state may be initiated by the event of the start of the winning combination lottery process (FIG. 18). In a configuration in which the dual-purpose display unit 66 is temporarily in the all-off state regardless of whether or not the winning combination lottery process (FIG. 18) is displayed, the all-off state can be initiated at a timing when the presence or absence of the winning combination lottery display is determined, i.e., before the timing when the result of the winning combination lottery process (FIG. 18) is determined. This makes it possible to extend the duration of the all-off state without delaying the end timing of the all-off state relative to the timing when the operation of the stop buttons 42 to 44 is enabled, compared to a configuration in which the all-off state is initiated at the timing when the result of the winning combination lottery process (FIG. 18) is determined or later.

(22) In the eighth embodiment, the duration of the all-lights-off state in the dual-purpose display unit 66 may be varied. Specifically, the all-lights-off state may end when the first stop command is issued. In the eighth embodiment, as already explained, when it is determined that the game does not involve stop order display on the dual-purpose display unit 66, the dual-purpose display unit 66 temporarily enters the all-lights-off state. The timing at which the first stop command is issued varies depending on the timing at which the player operates the stop buttons 42 to 44. By configuring the all-lights-off state to end when the first stop command is issued, it is possible to end the all-lights-off state after the operation of the stop buttons 42 to 44 is enabled, without providing a counter for measuring the duration of the all-lights-off state, and to display the number of awards of "00" between the time the first stop command is issued and the time all reels have stopped.

(23) In the eighth embodiment, the trigger for the initiation of the fully-off state of the dual-purpose display unit 66 is not limited to the event of the start of acceleration control of reels 32L, 32M, and 32R. Specifically, in a configuration in which acceleration control of reels 32L, 32M, and 32R is performed during a first half acceleration period of approximately 150 milliseconds and a second half acceleration period of approximately 150 milliseconds following the first half acceleration period, the dual-purpose display unit 66 may be configured to enter the fully-off state in response to the end of the first half acceleration period. In a configuration in which the dual-purpose display unit 66 is temporarily placed in the fully-off state only in games in which stop order corresponding display is not performed on the dual-purpose display unit 66, the fully-off state may also be configured to end at a timing after the operation of stop buttons 42 to 44 is enabled. Therefore, even if the fully off state is initiated by an event that occurs after the timing at which acceleration control of reels 32L, 32M, and 32R is initiated, the dual-purpose display unit 66 can be turned off in a manner that is recognizable by players and amusement hall managers.

(24) In the eighth embodiment described above, the dual-purpose display unit 66 may be configured to end its fully unlit state at the timing when the operation of the stop buttons 42 to 44 is enabled, or at a timing earlier than that timing. If the dual-purpose display unit 66 is configured to be fully unlit in a manner that can be recognized by players and amusement hall managers, it is possible to prevent the dual-purpose display unit 66 from continuing to display "00" as the number of wins awarded from before the game starts until the game ends.

(25) In each of the above embodiments, the operation to start the ratio display may be configured to be something other than the operation of the reset button 56. Specifically, the main MPU 72 may be configured to recognize that the operation to start the ratio display has been performed when the front door 12 is open and any of the stop buttons 42-44 is operated while the slot machine 10 is receiving operating power and the setting value update process in step S107 of the main process (FIG. 10) is not being executed. This makes it easier to distinguish between the operation of the reset button 56 to execute the all clear process (step S106) and the operation of the reset button 56 to update the setting value in the setting value update process (step S107) and the operation to start the ratio display.

(26) In each of the above embodiments, the receiving circuit 87 may be configured to determine that a communication error has occurred if it receives a header HD and then the next header HD without receiving a footer FT. When the receiving circuit 87 identifies the occurrence of a communication error, it outputs a resend request signal to the transmitting circuit. If the transmitting circuit does not receive a resend request signal after completing command transmission, it deletes the data of the command whose transmission has been completed from the transmission standby buffer 112. Then, if the next command is set in the transmission standby buffer 112, it begins transmitting that next command. On the other hand, if a resend request signal is received after completing command transmission, it resends the command stored in the transmission standby buffer 112. The receiving circuit 87 is provided with a communication error counter that counts the number of consecutive communication errors that have occurred. The communication error counter stores numerical information ranging from "0" to "3." When the receiving circuit 87 outputs a resend request signal, it increments the value of the communication error counter by 1. If no communication error is confirmed for the command received after the output of the resend request signal, it clears the communication error counter to "0." When the value of the communication error counter reaches "3," the production side MPU 92 controls the illumination of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63 to issue a communication error alert. This allows the amusement hall manager to be notified that commands are not being sent normally from the main side MPU 72 to the production side MPU 92. In this way, by configuring the receiving circuit 87 to recognize that a communication error has occurred when it receives a header HD and then receives the next header HD without receiving a footer FT, it is possible to prevent the production side MPU 92 from using data different from the data included in the command set by the main side MPU 72 in the transmission standby buffer 112.

(27) In a game in which the image display device 63 notifies the reels 32L, 32M, and 32R of their stop order and the dual-purpose display unit 66 displays the corresponding stop order for the reels 32L, 32M, and 32R, the stop order notification on the image display device 63 may be terminated when a stop command is issued for all reels 32L, 32M, and 32R in the game, and the stop order display on the dual-purpose display unit 66 may be terminated when the in-game flag in the main RAM 74 is cleared to "0" in step S1510 of the end-of-game response processing (FIG. 32). Also, the stop order display on the dual-purpose display unit 66 may be terminated when a stop command is issued for all reels 32L, 32M, and 32R in the game, and the stop order notification on the image display device 63 may be terminated when the in-game flag in the main RAM 74 is cleared to "0" in step S1510 of the end-of-game response processing (FIG. 32).

(28) In each of the above embodiments, the range that can be jumped by a JRS instruction may be configured to be the range from "the program address where the JRS instruction is set + 1 - p (p is an integer between 2 and 16)" to "the program address where the JRS instruction is set + 1 + q (q is an integer between 1 and 15)." Of these, "+1" corresponds to the word length (1 byte) of the JRS instruction itself. Furthermore, "-p to q" is a numerical range that can be specified using a total of 5 bits, including 1 sign bit and 4 numeric bits.

(29) In each of the above embodiments, only program addresses greater in value than the program address at which the JRS instruction is set may be set as addresses that can be specified as jump destinations for a JRS instruction. Specifically, as already explained in the first embodiment, a JRS instruction relatively identifies a jump destination program address (2 bytes) based on the program address at which the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. In this configuration, the difference information (5 bits) set in the JRS instruction does not include a sign bit, and the difference information is 5-bit numerical information (any of "0" to "31"). This allows the range that can be jumped by a JRS instruction to be set from "(the program address at which the JRS instruction is set) + 1 + 0" to "(the program address at which the JRS instruction is set) + 1 + 31." Furthermore, in each of the above embodiments, only program addresses less in value than the program address at which the JRS instruction is set may be set as addresses that can be specified as jump destinations for a JRS instruction. In this configuration, the difference information (5 bits) set in the JRS instruction does not include a sign bit, and the difference information is 5-bit numerical information (any value from "0" to "31"). This allows the range that can be jumped by the JRS instruction to be set between "(the program address where the JRS instruction is set) - 1 - 0" and "(the program address where the JRS instruction is set) - 1 - 31."

(30) In each of the above embodiments, the range that can be jumped by a JR instruction may be configured to range from "the program address where the JR instruction is set + 2 - s (where s is an integer between 3 and 128)" to "the program address where the JRS instruction is set + 2 + t (where t is an integer between 1 and 127)." Of these, "+2" corresponds to the word length (2 bytes) of the JR instruction itself. Furthermore, "-s to t" is a numerical range that can be specified using a total of 8 bits, including 1 sign bit and 7 numeric bits.

(31) In each of the above embodiments, only program addresses greater in value than the program address at which the JR instruction is set may be set as addresses that can be specified as jump destinations for the JR instruction. Specifically, as already explained in the first embodiment, the JR instruction relatively identifies the jump destination program address (2 bytes) based on the program address at which the JR instruction is set and the difference information (8 bits) set in the JR instruction. In this configuration, the difference information (8 bits) set in the JR instruction does not include a sign bit, and the difference information is 8-bit numerical information (any value from "0" to "255"). This allows the range that can be jumped by the JR instruction to be set between "(the program address at which the JR instruction is set) + 2 + 0" and "(the program address at which the JRS instruction is set) + 2 + 255." Furthermore, in each of the above embodiments, only program addresses less in value than the program address at which the JR instruction is set may be set as addresses that can be specified as jump destinations for the JR instruction. In this configuration, the difference information (8 bits) set in the JR instruction does not include a sign bit, and the difference information is 8-bit numerical information (any value from "0" to "255"). This allows the range that can be jumped with the JR instruction to be set between "(the program address where the JR instruction is set) - 2 - 0" and "(the program address where the JR instruction is set) - 2 - 255."

(32) In each of the above embodiments, the termination condition of the pseudo bonus state ST4 is not limited to a configuration in which the number of games played is determined, and the termination condition of the pseudo bonus state ST4 may be a configuration in which the termination condition of the pseudo bonus state ST4 is determined by the number of payouts, a configuration in which the termination condition of the pseudo bonus state ST4 is determined by the number of net increases, or a configuration in which the termination condition of the pseudo bonus state ST4 is determined by the number of conditional net increases. In a configuration in which the termination condition of the pseudo bonus state ST4 is determined by the number of payouts, the pseudo bonus state ST4 ends when the total number of gaming media awarded by games played while the pseudo bonus state ST4 is continuing reaches the termination criteria payout number (e.g., "100"), or when the ending condition of the second section SC2 is met. In a configuration in which the termination condition of the pseudo bonus state ST4 is defined by the net increase in number of coins, the pseudo bonus state ST4 terminates when the value obtained by subtracting the "total number of gaming media consumed to execute games while the pseudo bonus state ST4 is continuing ("0" when no games are being executed)" from the "total number of gaming media awarded by games executed while the pseudo bonus state ST4 is continuing ("0" when no gaming media are being awarded)" (the total net increase in number of coins in the pseudo bonus state ST4) reaches the termination criterion net increase in number (e.g., "50"), or when the ending condition of the second section SC2 is met. In a configuration in which the termination condition of the pseudo bonus state ST4 is defined by the conditional net increase in number of coins, the pseudo bonus state ST4 terminates when the conditional net increase in number of gaming media in the pseudo bonus state ST4 reaches the termination criterion conditional net increase in number (e.g., "50"), or when the ending condition of the second section SC2 is met. The conditional net increase in the number of gaming media in pseudo bonus state ST4 is the increase in the difference in the number of gaming media in pseudo bonus state ST4 from the reference value, where the difference in the number of gaming media in pseudo bonus state ST4 is the minimum value of the difference in the number of gaming media in pseudo bonus state ST4, when the difference in the number of gaming media in pseudo bonus state ST4 is calculated by subtracting the total number of gaming media consumed to play games in a situation in which pseudo bonus state ST4 is continuing (0 when no gaming media are being played) from the total number of gaming media awarded by games played while pseudo bonus state ST4 is continuing (0 when no gaming media are being awarded).

(33) In each of the above embodiments, the termination condition of AT state ST5 is not limited to a configuration in which the number of games is defined, and may be a configuration in which the termination condition of AT state ST5 is defined by the number of payouts, a configuration in which the termination condition of AT state ST5 is defined by the number of net increases, or a configuration in which the termination condition of AT state ST5 is defined by the number of conditional net increases. In a configuration in which the termination condition of AT state ST5 is defined by the number of payouts, AT state ST5 ends when the total number of gaming media awarded by games executed while AT state ST5 is continuing reaches the termination standard payout number (e.g., "100"), or when the ending condition of the second section SC2 is met. In a configuration in which the termination condition of AT state ST5 is defined by the net increase in number of coins, AT state ST5 terminates when the value (total net increase in number of coins in AT state ST5) obtained by subtracting the "total number of gaming media consumed to execute games in a situation in which AT state ST5 is continuing ("0" when games are not being executed)" from the "total number of gaming media awarded by games executed in a situation in which AT state ST5 is continuing ("0" when gaming media are not being awarded)" reaches the termination criterion net increase in number (e.g., "50"), or when the ending condition of the second section SC2 is met. In a configuration in which the termination condition of AT state ST5 is defined by the conditional net increase in number of coins, AT state ST5 terminates when the conditional net increase in number of gaming media in the AT state ST5 reaches the termination criterion conditional net increase in number (e.g., "50"), or when the ending condition of the second section SC2 is met. The conditional net increase in the number of gaming media in AT state ST5 is the difference in the number of gaming media in AT state ST5, where the difference in the number of gaming media in AT state ST5 is the total number of gaming media awarded by games played while AT state ST5 is continuing (0 when no gaming media are awarded) minus the total number of gaming media consumed to play games while AT state ST5 is continuing (0 when no games are being played). The minimum difference in the number of gaming media in AT state ST5 is used as the reference value, and the increase in the difference in the number of gaming media in AT state ST5 from this reference value is the number of gaming media.

In a configuration in which the termination condition of AT state ST5 is specified by the number of payout coins, an additional lottery is executed to determine whether or not to increase the number of payout coins for the termination criteria, and if an additional lottery is won, a predetermined number (e.g., 10) may be added to the number of payout coins for the termination criteria. In a configuration in which the termination condition of AT state ST5 is specified by the net increase in coins, an additional lottery is executed to determine whether or not to increase the number of net increase in coins for the termination criteria, and if an additional lottery is won, a predetermined number (e.g., 10) may be added to the number of net increase in coins for the termination criteria. Furthermore, in a configuration in which the termination condition of AT state ST5 is specified by the conditional net increase in coins, an additional lottery is executed to determine whether or not to increase the number of conditional payout coins for the termination criteria, and if an additional lottery is won, a predetermined number (e.g., 10) may be added to the number of conditional net increase in coins for the termination criteria.

(34) In each of the above embodiments, the data configuration of the main ROM 73 is not limited to a configuration in which a 2-byte address is set for each 1-byte storage area. For example, it may be a configuration in which a 2-byte address is set for each 2-byte storage area, or a configuration in which a 1-byte address is set for each 1-byte storage area.

(35) The number of active lines is not limited to one, the main line ML, and may be two, three, four, or more. In this case, the number of active lines may increase as the number of gaming media bets increases, or the maximum number of active lines may be set regardless of the number of gaming media bets.

(36) The types of information transmitted from the main MPU 72 to the presentation MPU 92 are not limited to those described in the above embodiments. For example, when a winning combination corresponding to the awarding of game media is achieved, information regarding the number of game media awarded as a result of the winning combination may be transmitted from the main MPU 72 to the presentation MPU 92. In this case, information regarding the number of game media awarded as a result of the winning combination can be displayed on the image display device 63 or the like. Furthermore, even when all reels 32L, 32M, and 32R are not stopped, when some of the reels 32L, 32M, and 32R have stopped spinning or have stopped, corresponding information may be transmitted from the main MPU 72 to the presentation MPU 92. In this case, it is possible to display presentations corresponding to the spinning status of the reels 32L, 32M, and 32R on the image display device 63 or the like.

(37) In each of the above embodiments, a bonus of medals being paid out is awarded when a small winning combination is achieved, but the invention is not limited to such a configuration and may be configured to award some kind of bonus to the player. For example, a prize other than medals may be paid out when a small winning combination is achieved. Furthermore, in slot machines that do not have the function of inserting actual medals or paying out medals, but instead manage medals owned by the player as credits, an increase in the number of credited medals corresponds to the awarding of a bonus.

(38) The present invention may be applied to so-called B-type slot machines, or to any type of slot machine, such as C-type, a combination of A-type and C-type, a combination of B-type and C-type, or even a type equipped with an RT game, CT game, or AT game. It may also be configured to have a bonus state that is advantageous to the player.

(39) The symbols on each reel 32L, 32M, 32R are not limited to pictures, numbers, letters, etc., but may also be geometric lines, figures, etc. Furthermore, symbols may be formed using light, color, etc., or three-dimensional shapes, etc., or may be a combination of these. In other words, symbols may function as distinguishable information.

(40) In the above embodiments, specific examples of a slot machine 10 were shown, but the present invention may also be applied to pachinko machines in which games are played using gaming balls as the gaming medium, or to gaming machines that combine slot machines and pachinko machines.

<Inventions extracted from the above embodiments>
The following describes the features of the inventions extracted from the above-described embodiments, while indicating, as necessary, their effects, etc. Note that, for ease of understanding, the following will appropriately indicate corresponding configurations in the above-described embodiments in parentheses, etc. However, the present invention is not limited to the specific configurations indicated in parentheses, etc.

<Features Group A>
Feature A1. A predetermined storage means (main ROM 73 or main RAM 74) having a plurality of storage regions (storage areas) set in correspondence with addresses;
A predetermined range of a plurality of storage areas provided in the predetermined storage means (an address range of "0001H" to "000DH" in the main RAM 74 when a start command or an end command is transmitted in the first to third embodiments, an address range of "0021H" to "0028H" in the main RAM 74 when a BB transition command is transmitted in the third embodiment, an address range of "9101H" to "911AH" in the common data table 73f when a start command or an end command is transmitted in the fourth embodiment) a predetermined transmitting means (a function for executing the common command transmitting process of the main MPU 72) for transmitting a predetermined information group (start command, end command, BB transition command) set using various information including information stored in the memory area of the common data table 73g (address range, the address range of "9101H" to "910CH" in the case of transmitting a start command in the sixth embodiment, and the address range of "9109H" to "911AH" in the common data table 73g in the case of transmitting an end command);
Equipped with
A gaming machine characterized in that the specified range of memory area is set to a continuous address range.

According to Feature A1, the specified range of storage areas is set as a contiguous address range, making it easier to grasp the specified range of storage areas. This simplifies the processing configuration for setting information in the specified information group when sending the specified information group using the information stored in the specified range of storage areas.

Feature A2: The predetermined information group has a plurality of unit data (1-byte frames FRm) including predetermined unit data (the second to seventh frames FR2 to FR7 and the ninth to fourteenth frames FR9 to FR14 of the start command and the end command in the first to fourth embodiments, the second to sixth frames FR2 to FR6 of the start command, and the second frame FR2 and the fourth to tenth frames FR4 to FR10 of the end command in the sixth embodiment) that are set in the predetermined information group using information stored in the storage area of the predetermined range,
the information of the bit (most significant bit) at a predetermined position in the first unit data in the predetermined information group is specific bit information (information of "1");
A gaming machine described in feature A1, characterized in that the information of the bit at the specified position in the unit data other than the first in the specified information group is information other than the specific bit information (information ``0'').

Feature A2 makes it possible to distinguish between the first unit data in a specified information group and the other units of data based on the information of the bit at a specified position. This makes it possible to determine the boundary between the specified information group and other information groups.

Feature A3. A gaming machine according to Feature A2, wherein the bit at the predetermined position in the unit data is the most significant bit in the unit data (the 7th bit of bits 0 to 7).

Feature A3 makes it possible to distinguish between the first unit data and the other unit data in a specified information group based on the information in the most significant bit. By making the bit in the specified position the most significant bit, the position of the bit referenced to distinguish between the first unit data and the other unit data can be made easier to grasp. This simplifies the processing configuration for distinguishing between the first unit data and the other unit data.

Feature A4. A gaming machine according to any one of Features A1 to A3, wherein the predetermined transmission means includes predetermined information setting means (a function that executes the common command transmission process of the main MPU 72 in the first to third embodiments) that sets information stored in the predetermined range of memory area to the predetermined information group.

Feature A4 enables the transmission of a predetermined information group including information stored in a predetermined range of memory areas set in a range of consecutive addresses.

Feature A5. A gaming machine according to Feature A4, characterized in that the predetermined information setting means includes aggregation setting means (a function for executing the top-level aggregation process of the main MPU 72 in the first to third embodiments) that sets aggregated information (information set in the top-level aggregation area 74v, information set in the BB top-level aggregation area 74β) into the predetermined information group, the aggregated information being information stored in bits at predetermined positions in multiple memory areas included in an aggregation target range (the address range of "0001H" to "0006H" in the main RAM 74 in the first to third embodiments, the address range of "0021H" to "0027H" in the main RAM 74 in the third embodiment) that includes at least some of the multiple memory areas included in the predetermined range.

According to Feature A5, when a specified group of information is received, it is possible to ascertain the information stored in bits at specified positions in multiple storage areas included in the aggregation target range based on the aggregation information set in the specified group of information. In a configuration with the configuration of Feature A1 above, in which the specified range of storage areas is set to a contiguous address range, the aggregation target range is a range that includes at least some of the multiple storage areas included in the specified range. This makes it easier to ascertain the storage areas included in the aggregation target range. This simplifies the processing configuration for generating aggregate information.

Feature A6. A gaming machine as described in Feature A5, characterized in that the information stored in the bits at the specified positions in the memory areas within the specified range that are not included in the aggregation target range (in the first to third embodiments, the memory areas of the main RAM 74 included in the address range of "0008H" to "000DH") is information ("0") other than specific bit information ("1"), and aggregation of information other than the specific bit information stored in the bits at the specified positions is not performed.

According to Feature A6, by configuring the system so that information stored in bits at specified positions is not aggregated for storage areas within a specified range that are not included in the aggregation target range, the processing load for aggregating information stored in bits at specified positions can be reduced compared to a configuration in which information stored in bits at specified positions is aggregated for all storage areas included in the specified range.

Feature A7. A gaming machine as described in Feature A5 or A6, characterized in that the aggregation target range includes memory areas (lower areas of the AT continuation counter 74u, lower areas of the continued game number counter 74r, and lower areas of the total win number counter 74s) in which specific bit information (information "1") can be stored in the bit at the specified position.

According to Feature A7, by defining the aggregation target range as a range that includes a storage area in which specific bit information can be stored in a bit at a specified position, it is possible to determine whether specific bit information has been stored in a bit at a specified position in a storage area included in the aggregation target range after receiving a specified group of information.

Feature A8. A gaming machine described in any one of Features A5 to A7, wherein the specified range of memory area includes a memory area (top-level aggregation area 74v, BB top-level aggregation area 74β) in which the aggregation information is set.

According to Feature A8, in a configuration having the configuration of Feature A1 above, in which a predetermined range of storage areas is set to a contiguous address range, the predetermined range of storage areas includes a storage area in which aggregated information is set. Therefore, by executing a process to set the information stored in the predetermined range of storage areas to a predetermined information group, the aggregated information can be set to the predetermined information group. This simplifies the processing configuration for setting aggregated information to a predetermined information group.

Feature A9: The predetermined range of memory area stores address information for identifying a memory area in which the information set in the predetermined information group is stored (address information for identifying a memory area of the main RAM 74),
A gaming machine described in any one of features A1 to A3, characterized in that the specified transmission means is equipped with a specific information setting means (a function of executing the common command transmission process of the main MPU 72 in the fourth to sixth embodiments) that sets information stored in a memory area (memory area of the main RAM 74) identified by the address information stored in the memory area within the specified range to the specified information group.

Feature A9 allows for the transmission of a predetermined information group that includes information stored in a storage area identified by address information set in a predetermined range of storage areas. Even if the addresses used to identify the storage areas storing the information set in the predetermined information group are not consecutive, the storage areas storing the information set in the predetermined information group can be identified using address information stored in consecutive storage areas in a predetermined range, making it easier to identify the storage areas storing the information set in the predetermined information group. This simplifies the processing configuration for setting information in the predetermined information group.

Feature A10. The gaming machine described in Feature A9 is characterized in that the specific information setting means includes aggregation setting means (a function for executing the highest-level aggregation process of the main MPU 72 in the fourth and sixth embodiments) that sets, to the predetermined information group, aggregated information (information set in the highest-level aggregation area 74v) obtained by aggregating information stored in bits at predetermined positions (most significant bits) in memory areas identified by the address information stored in multiple memory areas included in an aggregation target range ("9101H" to "910CH" in the common data table 73f in the fourth embodiment, the first aggregation range in the common data table 73g when a start command is sent in the sixth embodiment, and the second aggregation range in the common data table 73g when an end command is sent) that includes at least some of the multiple memory areas included in the predetermined range.

According to Feature A10, when a specified group of information is received, it is possible to determine, based on the aggregation information set in the specified group of information, the information stored in a bit at a specified position in a storage area identified by address information stored in multiple storage areas included in the aggregation target range. In a configuration with the configuration of Feature A1 above, in which the specified range of storage areas is set to a contiguous address range, the aggregation target range is a range that includes at least some of the multiple storage areas included in the specified range. This makes it easier to determine the storage areas included in the aggregation target range. This simplifies the processing configuration for generating aggregate information.

Feature A11. The gaming machine described in Feature A10, wherein the information stored in the bit at the predetermined position in the memory area identified by address information stored in the memory area within the predetermined range that is not included in the range to be aggregated (in the fourth embodiment, a memory area identified by address information stored in the address range of "910FH" to "911AH"; in the sixth embodiment, a memory area identified by address information stored in the address range of "9105H" to "910CH" when sending a start command; and a memory area identified by address information stored in the address ranges of "9109H" to "910CH" and "9115H" to "911AH" when sending an end command) is information ("0") other than specific bit information ("1"), and aggregation of information other than the specific bit information stored in the bit at the predetermined position is not performed.

According to Feature A11, by configuring the system so that information stored in bits at predetermined positions is not aggregated for storage areas identified by address information stored in storage areas within a predetermined range that are not included in the aggregation target range, the processing load for aggregating information stored in bits at predetermined positions can be reduced compared to a configuration in which information stored in bits at predetermined positions is aggregated for all storage areas identified by address information stored in storage areas included in the predetermined range.

Feature A12. A gaming machine as described in Feature A10 or A11, characterized in that the aggregation target range includes a memory area in which address information is stored for identifying a memory area (the lower area of the AT continuation counter 74u, the lower area of the continued game number counter 74r, and the lower area of the total win number counter 74s) in which specific bit information (information "1") can be stored in the bit at the specified position.

According to Feature A12, by defining the aggregation target range as a range that includes a storage area in which address information is stored for identifying a storage area in which specific bit information can be stored in a bit at a specific position, after receiving a specific information group, it becomes possible to determine whether specific bit information has been stored in a bit at a specific position in a storage area identified by the address information stored in a storage area in the aggregation target range.

Feature A13. A gaming machine described in any one of Features A10 to A12, wherein the specified range of memory area includes a memory area storing address information for identifying the memory area (top-level memory area 74v, BB top-level memory area 74β) in which the aggregation information is set.

According to Feature A13, in a configuration having the configuration of Feature A1 above, in which a predetermined range of storage areas is set to a contiguous address range, the predetermined range of storage areas includes a storage area in which address information for identifying the storage area in which aggregated information is set is stored. Therefore, aggregated information can be set to a predetermined information group by executing a process to set information stored in a storage area identified by the address information stored in the predetermined range of storage areas to the predetermined information group. This simplifies the processing configuration for setting aggregated information to a predetermined information group.

Feature A14. The predetermined transmission means is
a first predetermined transmission means (a function for executing the processing of step S1107 of the main MPU 72 in the first embodiment, a function for executing the common command transmission processing of the main MPU 72 in the first to fourth and sixth embodiments) for transmitting a first predetermined information group (start command) set using various information including information stored in the storage area of the predetermined range as the predetermined information group based on the occurrence of a first transmission trigger (operation of the start lever 41 with gaming media betted);
a second predetermined transmission means (a function for executing the processing of step S1508 of the main MPU 72 in the first embodiment, a function for executing the common command transmission processing of the main MPU 72 in the first to fourth and sixth embodiments) for transmitting a second predetermined information group (end command) set using various information including information stored in a memory area of the predetermined range, which is the same range as the predetermined range when transmitting the first predetermined information group, based on the occurrence of a second transmission trigger (the end of stop control of all reels 32L, 32M, 32R);
Equipped with
The aggregation setting means
a first aggregation setting means for setting the aggregation information to the first predetermined information group (a function for executing the processing of steps S2811 to S2816 of the main MPU 72 in the first embodiment, a function for executing the processing of steps S4011 to S4015 of the main MPU 72 in the second embodiment, a function for executing the processing of steps S4207 to S4212 of the main MPU 72 in the third embodiment, and a function for executing the processing of steps S4412 to S4416 of the main MPU 72 in the fourth embodiment);
a second aggregation setting means for setting the same aggregated information as the aggregated information set in the first predetermined information group in the second predetermined information group (a function for executing the processes of steps S2811 to S2816 of the main MPU 72 in the first embodiment, a function for executing the processes of steps S4011 to S4015 of the main MPU 72 in the second embodiment, a function for executing the processes of steps S4207 to S4212 of the main MPU 72 in the third embodiment, and a function for executing the processes of steps S4412 to S4416 of the main MPU 72 in the fourth embodiment);
A gaming machine according to any one of features A5 to A8 and features A10 to A13, characterized in that it is provided with:

According to Feature A14, the specified range when the second predetermined information group is transmitted in response to the occurrence of the second transmission trigger is the same as the specified range when the first predetermined information group is transmitted in response to the occurrence of the first transmission trigger. Therefore, a common program can be used to perform the process of setting information to the first predetermined information group using information stored in a storage area within a specified range, and the process of setting information to the second predetermined information group using information stored in the storage area within that specified range. This reduces the data size of the program used to transmit the first predetermined information group and the second predetermined information group.

The aggregated information set in the second predetermined information group is the same as the aggregated information set in the first predetermined information group. Therefore, the process of generating aggregated information when transmitting the first predetermined information group and the process of generating aggregated information when transmitting the second predetermined information group can be executed using a common program. This reduces the data size of the programs used to execute the process of transmitting the first predetermined information group and the process of transmitting the second predetermined information group.

Feature A15: Each of the first predetermined information group and the second predetermined information group has a plurality of unit data (1-byte frames FRm) including predetermined unit data (the second to seventh frames FR2 to FR7 and the ninth to fourteenth frames FR9 to FR14 of the start command and the end command in the first to third embodiments) set using information stored in the storage area of the predetermined range and aggregation unit data (top-level aggregated frame SF) in which the aggregation information is set,
a first predetermined processing execution means (a function of executing the processing of steps S3301 to S3320 in the performance-side MPU 92) for executing a first predetermined processing (start-time reception corresponding processing) using some of the predetermined unit data among the plurality of predetermined unit data included in the first predetermined information group when the first predetermined information group is received;
a second predetermined processing execution means (a function of executing the processing of steps S3501 to S3521 in the performance-side MPU 92) for executing a second predetermined processing (end-time reception corresponding processing) using a part of the predetermined unit data among the plurality of predetermined unit data included in the second predetermined information group when the second predetermined information group is received;
The gaming machine described in feature A14 is characterized by comprising:

Feature A15 includes the configuration of feature A14, and is configured such that the predetermined range when the second predetermined information group is transmitted in response to the occurrence of a second transmission trigger is the same as the predetermined range when the first predetermined information group is transmitted in response to the occurrence of a first transmission trigger. However, when the first transmission trigger occurs, the first predetermined process can be executed based on the first predetermined information group, and when the second transmission trigger occurs, the second predetermined process can be executed based on the second predetermined information group.

Feature A16: The predetermined unit data used when the first predetermined process execution means executes the first predetermined process includes first use target information (information stored in the AT continuation counter 74u) set using information stored in a portion of the multiple storage areas included in the aggregation target range,
A gaming machine described in feature A15, characterized in that the predetermined unit data used when the second predetermined processing execution means executes the second predetermined processing includes second target information to be used (information stored in the continued game number counter 74r, information stored in the total number of wins counter 74s) set using information stored in some of the multiple memory areas included in the aggregation target range.

Feature A16 includes the configuration of feature A14, and is configured such that the predetermined range when a second predetermined information group is sent in response to the occurrence of a second transmission trigger is the same as the predetermined range when a first predetermined information group is sent in response to the occurrence of a first transmission trigger. However, when a first transmission trigger occurs, the first predetermined process can be executed using first target usage information set using information stored in a portion of the multiple storage areas included in the aggregation target range, and when a second transmission trigger occurs, the second predetermined process can be executed using second target usage information set using information stored in a portion of the multiple storage areas included in the aggregation target range.

Feature A17. The predetermined transmission means is
a first predetermined transmission means (a function of executing a common command transmission process of the main MPU 72 in the sixth embodiment) for transmitting the first predetermined information group set using various information including information stored in a memory area of a first predetermined range (a memory area of the main RAM 74 specified by address information stored in a memory area included in the address range of "9101H" to "910CH" in the common data table 73g in the sixth embodiment), which is the predetermined range when transmitting a first predetermined information group (a start command in the sixth embodiment) among a plurality of memory areas provided in the predetermined storage means, based on the occurrence of a first transmission trigger (the operation of the start lever 41 when gaming media are bet);
a second predetermined transmission means (a function for executing a common command transmission process of the main MPU 72 in the sixth embodiment) for transmitting the second predetermined information group set using various information including information stored in a memory area of a second predetermined range (a memory area of the main RAM 74 specified by address information stored in a memory area included in the address range of "910DH" to "911AH" in the common data table 73g in the sixth embodiment), which is the predetermined range when transmitting a second predetermined information group (an end command in the sixth embodiment) among the multiple memory areas provided in the predetermined storage means, based on the occurrence of a second transmission trigger (the end of stop control of all reels 32L, 32M, 32R);
It is equipped with
A part of the storage areas included in the first predetermined range is also included in the second predetermined range,
A gaming machine described in any one of features A1 to A16, characterized in that the first predetermined range of memory area and the second predetermined range of memory area are each set to a continuous address range.

According to Feature A17, in a configuration in which some of the multiple storage areas included in a first predetermined range are also included in a second predetermined range, the storage areas in the first predetermined range are set to a contiguous address range, making it easier to grasp the storage areas in the first predetermined range, and the storage areas in the second predetermined range are set to a contiguous address range, making it easier to grasp the storage areas in the second predetermined range. This simplifies the processing configuration for setting information in the first predetermined information group using information stored in the storage areas in the first predetermined range when transmitting the first predetermined information group, and also simplifies the processing configuration for setting information in the second predetermined information group using information stored in the storage areas in the second predetermined range when transmitting the second predetermined information group.

Feature A18. The predetermined transmission means is
a predetermined reference address setting means (a function for executing the process of step S2809 of the primary MPU 72 in the first embodiment, a function for executing the process of step S4009 of the primary MPU 72 in the second embodiment, a function for executing the process of step S4205 of the primary MPU 72 in the third embodiment, a function for executing the process of step S4410 of the primary MPU 72 in the fourth embodiment, and a function for executing the process of steps S4907 and S4912 of the primary MPU 72 in the sixth embodiment) that sets a predetermined reference address, which is an address for specifying one storage area included in the predetermined range (a start address of a storage area to be transferred in the common command transmission process in the first to fourth embodiments, "9101H" when a start command is transmitted in the sixth embodiment, and "9109H" when a termination command is transmitted), to a predetermined setting target address (a storage area of the transfer source in the first to third embodiments, and a storage area in which address information for specifying the storage area of the transfer source is set)
a predetermined unit data setting means (a function for executing the process of step S2811 of the primary MPU 72 in the first embodiment, a function for executing the process of step S4011 of the primary MPU 72 in the second embodiment, a function for executing the process of step S4207 of the primary MPU 72 in the third embodiment, a function for executing the process of step S4412 of the primary MPU 72 in the fourth embodiment, and a function for executing the process of step S4915 of the primary MPU 72 in the sixth embodiment) that sets predetermined unit data (data of the frame FRm) to the predetermined information group by using information stored in a storage area specified by the predetermined setting target address;
a predetermined updating means (a function of executing the processing of step S2816 of the primary MPU 72 in the first embodiment, a function of executing the processing of step S4015 of the primary MPU 72 in the second embodiment, a function of executing the processing of step S4212 of the primary MPU 72 in the third embodiment, a function of executing the processing of step S4416 of the primary MPU 72 in the fourth embodiment, and a function of executing the processing of step S4920 of the primary MPU 72 in the sixth embodiment) that executes a predetermined updating process for updating the predetermined setting target address (the processing of step S2816 of the first embodiment, the processing of step S4015 of the primary MPU 72 in the second embodiment, the processing of step S4212 of the primary MPU 72 in the third embodiment, the processing of step S4416 of the primary MPU 72 in the fourth embodiment, and the processing of step S4920 of the primary MPU 72 in the sixth embodiment) every time the predetermined unit data setting process is executed;
It is equipped with
A gaming machine described in any one of features A1 to A17, characterized in that the predetermined unit data setting means executes the predetermined unit data setting process a number of times corresponding to the number of memory areas included in the predetermined range after the predetermined reference address is set to the predetermined setting target address (13 times in the first to fourth embodiments, 6 times when sending a start command in the sixth embodiment, and 9 times when sending an end command).

According to Feature A18, after the predetermined base address is set to the predetermined setting target address, the predetermined unit data can be set to the predetermined information group by executing the predetermined unit data setting process a number of times corresponding to the number of storage areas included in the predetermined range. By repeatedly executing the predetermined unit data setting process, the processing configuration for setting the predetermined unit data to the predetermined information group can be simplified.

Feature A19. The predetermined transmission means is
a first predetermined transmission means (a function of executing a common command transmission process of the main MPU 72 in the sixth embodiment) for transmitting the first predetermined information group set using various information including information stored in a memory area of a first predetermined range (a memory area of the main RAM 74 specified by address information stored in a memory area included in the address range of "9101H" to "910CH" in the common data table 73g in the sixth embodiment), which is the predetermined range when transmitting a first predetermined information group (a start command in the sixth embodiment) among a plurality of memory areas provided in the predetermined storage means, based on the occurrence of a first transmission trigger (the operation of the start lever 41 when gaming media are bet);
a second predetermined transmission means (a function for executing a common command transmission process of the main MPU 72 in the sixth embodiment) for transmitting the second predetermined information group set using various information including information stored in a memory area of a second predetermined range (a memory area of the main RAM 74 specified by address information stored in a memory area included in the address range of "910DH" to "911AH" in the common data table 73g in the sixth embodiment), which is the predetermined range when transmitting a second predetermined information group (an end command in the sixth embodiment) among the multiple memory areas provided in the predetermined storage means, based on the occurrence of a second transmission trigger (the end of stop control of all reels 32L, 32M, 32R);
It is equipped with
The predetermined reference address setting means
a first predetermined reference address setting means (a function for executing the process of step S4907 of the main MPU 72 in the sixth embodiment) that sets a first predetermined reference address ("9101H" in the case of transmitting a start command in the sixth embodiment), which is an address for identifying one storage area included in the first predetermined range, as the predetermined setting target address;
a second predetermined reference address setting means (a function for executing the process of step S4912 of the main MPU 72 in the sixth embodiment) that sets a second predetermined reference address ("9109H" in the sixth embodiment when sending a termination command) that is an address for identifying one storage area included in the second predetermined range as the predetermined setting target address;
It is equipped with
The predetermined unit data setting means
a first predetermined unit data setting means (a function of executing the processing of step S4915 of the main MPU 72 in the sixth embodiment) that executes a first predetermined unit data setting processing (the processing of step S4915 in the sixth embodiment) that sets the predetermined unit data to the first predetermined information group using information stored in a storage area identified by the predetermined setting target address as the predetermined unit data setting processing;
a second predetermined unit data setting means (a function of executing the processing of step S4915 of the main MPU 72 in the sixth embodiment) that executes a second predetermined unit data setting processing (the processing of step S4915 in the sixth embodiment) that sets the predetermined unit data to the second predetermined information group using information stored in a storage area identified by the predetermined setting target address as the predetermined unit data setting processing;
It is equipped with
The predetermined update means
A first predetermined update means (a function of executing the process of step S4920 of the main MPU 72 in the sixth embodiment) that executes the predetermined update process every time the first predetermined unit data setting process is executed;
A second predetermined update means (a function of executing the process of step S4920 of the main MPU 72 in the sixth embodiment) that executes the predetermined update process every time the second predetermined unit data setting process is executed;
It is equipped with
the first predetermined unit data setting means, after the first predetermined reference address is set as the predetermined setting target address, executes the first predetermined unit data setting process a number of times corresponding to the number of storage areas included in the first predetermined range (six times in the case of transmitting a start command in the sixth embodiment);
the second predetermined unit data setting means, after the second predetermined reference address is set as the predetermined setting target address, executes the second predetermined unit data setting process a number of times corresponding to the number of storage areas included in the second predetermined range (nine times in the case of transmitting an end command in the sixth embodiment);
the second predetermined unit data setting process is executed by utilizing a program for executing the first predetermined unit data setting process,
A gaming machine described in feature A18, characterized in that the predetermined update processing by the second predetermined update means is executed using a program for the first predetermined update means to execute the predetermined update processing.

According to Feature A19, after a first predetermined reference address is set to a predetermined setting target address, the first predetermined unit data setting process is executed a number of times corresponding to the number of storage areas included in the first predetermined range, thereby setting the predetermined unit data to the first predetermined information group. By repeatedly executing the first predetermined unit data setting process, the processing configuration for setting the predetermined unit data to the first predetermined information group can be simplified. Furthermore, after a second predetermined reference address is set to a predetermined setting target address, the second predetermined unit data setting process is executed a number of times corresponding to the number of storage areas included in the second predetermined range, thereby setting the predetermined unit data to the second predetermined information group. By repeatedly executing the second predetermined unit data setting process, the processing configuration for setting the predetermined unit data to the second predetermined information group can be simplified.

By using a program for executing the first predetermined unit data setting process to execute the second predetermined unit data setting process, the data size of the programs for executing these two processes can be reduced compared to a configuration in which a program for executing the second predetermined unit data setting process is provided as a separate program from the program for executing the first predetermined unit data setting process. By using a program for executing the predetermined update process by the first predetermined update means and having the second predetermined update means execute the predetermined update process, the data size of the programs for executing the predetermined update process can be reduced compared to a configuration in which a program for executing the predetermined update process by the second predetermined update means is provided as a separate program from the program for executing the predetermined update process by the first predetermined update means.

Note that any one or more of Features A1 to A19, Features B1 to B9, Features C1 to C13, Features D1 to D7, Features E1 to E6, Features F1 to F9, and Features G1 to G7 may be applied to the configurations of Features A1 to A19. This makes it possible to achieve a synergistic effect through the combined configurations.

<Features Group B>
Feature B1: A first transmitting means (a function of executing the common command transmitting process of the main MPU 72 in the fourth to sixth embodiments) that transmits a first information group (start command) having a plurality of unit data based on the occurrence of a first transmission trigger (operation of the start lever 41 with gaming media betted),
A second transmission means (a function of executing the common command transmission process of the main MPU 72 in the fourth to sixth embodiments) transmits a second information group (end command) having a plurality of unit data based on the occurrence of a second transmission trigger (the end of stop control of all reels 32L, 32M, 32R);
Equipped with
The first transmitting means refers to a predetermined reference information group ("9101H" to "911AH" of the common data table 73f in the fourth embodiment, "910DH" to "910EH" and "9113H" to "9114H" of the common data table 73f in the fifth embodiment, and "9109H" to "910CH" of the common data table 73g in the sixth embodiment) to transmit unit data to be transmitted as the first information group (information stored in a storage area of the main RAM 74 specified by address information set in the address range of "9101H" to "911AH" in the fourth embodiment, information stored in a storage area of the main RAM 74 specified by address information set in the address range of "910DH" to "910EH" and "9113H" to "9114H" in the fifth embodiment). a first specifying means (a function for executing the processing of steps S4410 to S4416 of the main MPU 72 in the fourth embodiment, a function for executing the processing of steps S4610 to S4618 of the main MPU 72 in the fifth embodiment, and a function for executing the processing of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment) for specifying information stored in a storage area of the main RAM 74 specified by set address information, or information stored in a storage area of the main RAM 74 specified by address information set in the address range of "9109H" to "910CH" in the sixth embodiment;
The second transmitting means transmits unit data to be transmitted as the second information group by referring to the predetermined reference information group (information stored in a storage area of the main RAM 74 specified by address information set in the address range of "9101H" to "911AH" in the fourth embodiment, information stored in a storage area of the main RAM 74 specified by address information set in the address range of "910DH" to "910EH" and "9113H" to "9114H" in the fifth embodiment, information stored in a storage area of the main RAM 74 specified by address information set in the address range of "9109H" to "910CH" in the sixth embodiment, A gaming machine characterized by being equipped with a second identification means (a function of executing the processing of steps S4410 to S4416 of the main MPU 72 in the fourth embodiment, a function of executing the processing of steps S4610 to S4618 of the main MPU 72 in the fifth embodiment, and a function of executing the processing of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment) for identifying information stored in a memory area of the main RAM 74 identified by address information set in the address range.

According to Feature B1, the predetermined reference information group is referenced to identify the unit data to be transmitted as the first information group, and is also referenced to identify the unit data to be transmitted as the second information group. Therefore, compared to a configuration in which the information group referenced to identify the unit data to be transmitted as the second information group is stored as a separate information group from the predetermined reference information group referenced to identify the unit data to be transmitted as the first information group, it is possible to reduce the data volume of the information group stored to enable identification of the unit data to be transmitted as the first information group and the unit data to be transmitted as the second information group.

Feature B2: The information storage means (main ROM 73) has a plurality of storage areas (storage areas of the main ROM 73) set in correspondence with addresses,
A gaming machine described in feature B1, characterized in that the specified reference information group is stored in a memory area of a consecutive specified address range (in the fourth embodiment, "9101H" to "911AH") in the information storage means.

Feature B2 simplifies the processing configuration for identifying unit data to be transmitted as the first information group by referencing a predetermined reference information group, and also simplifies the processing configuration for identifying unit data to be transmitted as the second information group by referencing a predetermined reference information group.

Feature B3: The first specifying means
a predetermined reference address setting means (a function for executing the process of step S4410 of the main MPU 72 in the fourth embodiment) for setting a predetermined reference address (a start address of the common data table 73f in the fourth embodiment), which is one address in the predetermined address range, to a predetermined setting target address (a storage area of the transfer source);
A specific processing execution means (a function of executing the processing of step S4412 of the main MPU 72 in the fourth embodiment) that executes a predetermined data specific processing (the processing of step S4412 in the fourth embodiment) that specifies unit data to be transmitted as the first information group based on the predetermined setting target address;
A predetermined update means (a function of executing the process of step S4416 of the main MPU 72 in the fourth embodiment) that executes a predetermined update process that updates the predetermined setting target address (the process of step S4416 in the fourth embodiment) every time the predetermined data identification process is executed;
It is equipped with
The gaming machine described in feature B2 is characterized in that the specific processing execution means executes the specified data specific processing a number of times (13 times in the fourth embodiment) corresponding to the number of memory areas included in the specified address range after the specified reference address is set as the specified setting target address.

According to Feature B3, when a first transmission trigger occurs, a predetermined reference address is set to a predetermined setting target address, and then the predetermined data identification process is executed a number of times corresponding to the number of storage areas included in the predetermined address range, thereby identifying the unit data to be transmitted as the first information group. By repeatedly executing the predetermined data identification process, the processing configuration for identifying the unit data to be transmitted as the first information group can be simplified.

Feature B4. A gaming machine according to either Feature B2 or B3, wherein the first transmission means includes predetermined aggregated information identification means (a function for executing the processing of steps S4412 to S4416 of the main MPU 72 in the fourth embodiment) that identifies, as unit data to be transmitted as the first information group, predetermined aggregated information (data stored in the highest aggregation area 74v) that aggregates information on bits at predetermined positions (most significant bits) in information identified by referencing multiple storage areas included in a predetermined aggregation target range ("9101H" to "910CH" in the fourth embodiment) that includes at least some of the multiple storage areas in which the predetermined reference information group is stored in the information storage means.

Feature B4 enables the first information group to be transmitted in a manner that makes it possible to ascertain information about bits at specific positions in information identified by referencing multiple storage areas included in the specified aggregation target range. In a configuration with the configuration of Feature B2 above, in which the specified reference information group is stored in storage areas in a contiguous address range in the information storage means, the specified aggregation target range is a range that includes at least some of the storage areas in the information storage means where the specified reference information group is stored. This makes it easier to ascertain the storage areas included in the specified aggregation target range. This simplifies the processing configuration for generating the specified aggregation information.

Feature B5: A predetermined storage means (main RAM 74) is provided that has a plurality of storage areas (storage areas of the main RAM 74) that are set in correspondence with addresses,
In the predetermined reference information group, address information corresponding to a part of a plurality of storage areas in the predetermined storage means (address information of the main RAM 74 set in the common data table 73 f) is set as information to be referenced for identifying the unit data to be transmitted as the first information group and the unit data to be transmitted as the second information group,
the first transmitting means identifies, as unit data to be transmitted as the first information group, information stored in a storage area of the predetermined storage means corresponding to information of the address set in the predetermined reference information group;
A gaming machine described in any one of features B1 to B4, characterized in that the second transmitting means identifies information stored in a memory area of the specified memory means corresponding to the address information set in the specified reference information group as unit data to be transmitted as the second information group.

According to feature B5, it is possible to identify, as unit data to be transmitted as a first information group, information stored in a portion of the multiple storage areas in the specified storage means at the time the first information group is transmitted, and it is possible to identify, as unit data to be transmitted as a second information group, information stored in a portion of the multiple storage areas in the specified storage means at the time the second information group is transmitted.

Feature B6: The first transmission means includes a third identification means (a function of executing the processes of steps S4610 to S4618 of the main MPU 72 in the fifth embodiment, and a function of executing the processes of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment) that identifies unit data to be transmitted as the first information group by referring to a first predetermined reference information group ("9101H" to "9104H", "910FH" to "9112H", and "9113H" to "9114H" of the common data table 73f in the fifth embodiment, and "9101H" to "9108H" of the common data table 73g in the sixth embodiment),
The second transmission means includes a fourth identification means (a function of executing the processes of steps S4610 to S4618 of the main MPU 72 in the fifth embodiment, and a function of executing the processes of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment) that identifies unit data to be transmitted as the second information group by referring to a second predetermined reference information group ("9105H" to "910CH" and "9115H" to "911AH" of the common data table 73f in the fifth embodiment, and "910DH" to "911AH" of the common data table 73g in the sixth embodiment),
the first information group includes unit data identified by the first identification means and unit data identified by the third identification means,
A gaming machine described in feature B1, characterized in that the second information group has unit data identified by the second identification means and unit data identified by the fourth identification means.

According to Feature B6, in addition to unit data identified by referencing a predetermined reference information group, unit data identified by referencing the first predetermined reference information group can be identified as unit data to be transmitted as the first information group. Furthermore, in addition to unit data identified by referencing a predetermined reference information group, unit data identified by referencing the second predetermined reference information group can be identified as unit data to be transmitted as the second information group. Because the predetermined reference information group is commonly referenced when identifying unit data to be transmitted as the first information group and when identifying unit data to be transmitted as the second information group, the data volume of the information groups stored to enable identification of unit data to be transmitted as the first information group and the second information group can be reduced compared to a configuration in which there is no overlap between the information groups referenced when identifying unit data to be transmitted as the first information group and the information groups referenced when identifying unit data to be transmitted as the second information group.

Feature B7: The information storage means (main ROM 73) has a plurality of storage areas (storage areas of the main ROM 73) set in correspondence with addresses,
The predetermined reference information group is stored in a storage area of a predetermined consecutive address range ("9109H" to "910CH" of the common data table 73g in the sixth embodiment) in the information storage means,
The first predetermined reference information group is stored in a storage area of a first predetermined consecutive address range ("9101H" to "9108H" of the common data table 73g) in the information storage means,
the second predetermined reference information group is stored in a storage area of a continuous second predetermined address range ("910DH" to "911AH" of the common data table 73g) in the information storage means,
the predetermined address range and the first predetermined address range are consecutive address ranges (an eleventh set range in the common data table 73g),
A gaming machine described in feature B6, characterized in that the specified address range and the second specified address range are consecutive address ranges (the 12th set range of the common data table 73g).

According to feature B7, because the specified address range and the first specified address range are contiguous address ranges, the processing configuration for identifying unit data to be transmitted as the first information group can be simplified by referencing the specified reference information group and the first specified reference information group. Furthermore, because the specified address range and the second specified address range are contiguous address ranges, the processing configuration for identifying unit data to be transmitted as the second information group can be simplified by referencing the specified reference information group and the second specified reference information group.

Feature B8: The first specifying means
a first predetermined reference address setting means (a function for executing the process of step S4907 of the main MPU 72 in the sixth embodiment) for setting a first predetermined reference address ("9101H" in the common data table 73g in the sixth embodiment), which is one address in the consecutive predetermined address range and the first predetermined address range, as a predetermined setting target address (an address for identifying the storage area of the transfer source);
a first identification process execution means (a function of executing the process of step S4915 of the main MPU 72 in the sixth embodiment) that executes a first predetermined data identification process (the process of step S4915 in the sixth embodiment) that identifies unit data to be transmitted as the first information group based on the predetermined setting target address;
a first predetermined update means (a function of executing the process of step S4920 of the main MPU 72 in the sixth embodiment) that executes a predetermined update process that updates the predetermined setting target address (the process of step S4920 in the sixth embodiment) every time the first predetermined data identification process is executed;
It is equipped with
The second specifying means
a second predetermined reference address setting means (a function for executing the process of step S4912 of the main MPU 72 in the sixth embodiment) for setting a second predetermined reference address ("9109H" in the common data table 73g in the sixth embodiment), which is one address in the consecutive predetermined address range and the second predetermined address range, as the predetermined setting target address;
a second identification process execution means (a function of executing the process of step S4915 of the main MPU 72 in the sixth embodiment) that executes a second predetermined data identification process (the process of step S4915 in the sixth embodiment) that identifies unit data to be transmitted as the second information group based on the predetermined setting target address;
A second predetermined update means (a function of executing the process of step S4920 of the main MPU 72 in the sixth embodiment) that executes the predetermined update process every time the second predetermined data identification process is executed;
It is equipped with
the first specifying process execution means, after the first predetermined reference address is set as the predetermined setting target address, executes the first predetermined data specifying process a number of times corresponding to the number of storage areas included in the first predetermined address range (six times in the case of transmitting a start command in the sixth embodiment);
the second specifying process execution means, after the second predetermined reference address is set as the predetermined setting target address, executes the second predetermined data specifying process a number of times corresponding to the number of storage areas included in the second predetermined address range (nine times in the case of transmitting an end command in the sixth embodiment);
the second predetermined data identification process is executed using a program for executing the first predetermined data identification process,
The gaming machine described in feature B7 is characterized in that the predetermined update processing by the second predetermined update means is executed using a program for the first predetermined update means to execute the predetermined update processing.

According to Feature B8, after the first predetermined reference address is set as the predetermined setting target address, the first predetermined data identification process is executed a number of times corresponding to the number of storage areas included in the predetermined address range and the first predetermined address range, thereby identifying the unit data to be transmitted as the first information group. By repeatedly executing the first predetermined data identification process, the processing configuration for identifying the unit data to be transmitted as the first information group can be simplified. Furthermore, after the second predetermined reference address is set as the predetermined setting target address, the second predetermined data identification process is executed a number of times corresponding to the number of storage areas included in the predetermined address range and the second predetermined address range, thereby identifying the unit data to be transmitted as the second information group. By repeatedly executing the second predetermined data identification process, the processing configuration for identifying the unit data to be transmitted as the second information group can be simplified.

By using a program for executing the first predetermined data identification process to execute the second predetermined data identification process, the data size of the programs for executing these two processes can be reduced compared to a configuration in which a program for executing the second predetermined data identification process is provided as a separate program from the program for executing the first predetermined data identification process. By using a program for executing the first predetermined update means to execute the predetermined update process and the second predetermined update means to execute the predetermined update process, the data size of the programs for executing the predetermined update process can be reduced compared to a configuration in which a program for executing the second predetermined update means to execute the predetermined update process is provided as a separate program from the program for executing the first predetermined update means.

Feature B9: A first predetermined processing execution means (a function of executing the processing of steps S3301 to S3320 in the production-side MPU 92) that executes a first predetermined processing (start-time reception corresponding processing) using some of the unit data among the plurality of unit data included in the first information group when the first information group is received;
a second predetermined processing execution means (a function of executing the processing of steps S3501 to S3521 in the production-side MPU 92) for executing a second predetermined processing (end-time reception corresponding processing) using some of the unit data among the plurality of unit data included in the second information group when the second information group is received;
A gaming machine according to any one of features B1 to B8, characterized in that it is provided with:

According to Feature B9, in a configuration having the configuration of Feature B1 above, in which unit data to be transmitted as a first information group is identified by referencing a predetermined reference information group, and unit data to be transmitted as a second information group is identified by referencing the predetermined reference information group, when the first information group is received, a first predetermined process can be performed using some of the unit data included in the first information group, and when the second information group is received, a second predetermined process can be performed using some of the unit data included in the second information group.

Note that one or more of the following configurations may be applied to the configurations of Features B1 to B9: Features A1 to A19, Features B1 to B9, Features C1 to C13, Features D1 to D7, Features E1 to E6, Features F1 to F9, and Features G1 to G7. This allows for a synergistic effect to be achieved through the combined configurations.

The invention relating to the features of Feature Group A and Feature Group B above can solve the following problems:

Pachinko machines and slot machines are well-known gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls. The gaming balls stored in the storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Furthermore, when the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning. If the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result after the reels have stopped spinning corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the transmission of information groups needs to be carried out appropriately, and there is still room for improvement in this regard.

<Feature Group C>
Feature C1. A display control means for controlling the display of the display means (combined display unit 66) (a function for executing the processing of steps S1401 to S1409 of the main MPU 72 in the first embodiment, a function for executing the processing of steps S5401 to S5411 of the main MPU 72 in the seventh embodiment, and a function for executing the processing of steps S5801 to S5810 of the main MPU 72 in the ninth embodiment),
a first storage execution means (a function for executing the processing of steps S1101 to S1105 of the main MPU 72 in the first embodiment, a function for executing the processing of steps S5501 to S5505 of the main MPU 72 in the eighth embodiment, and a function for executing the processing of steps S5701 to S5705 of the main MPU 72 in the ninth embodiment) for storing predetermined display information (a stop order type number from "1" to "9") in a first storage means (the stop order type counter 74m) that enables the display means to perform a predetermined display (a stop order corresponding display that corresponds to the value of the stop order type counter 74m);
a second storage execution means (function to execute the processing of steps S604 to S612 of the main MPU 72 in the first embodiment, function to execute the processing of steps S1204 to S1205 of the main MPU 72 in the seventh embodiment, function to execute the processing of steps S5303 to S5304 of the main MPU 72 in the eighth embodiment) for storing specific display information ("0", "1", "2", "5", or "15") in a second storage means (the award number counter 74e) that enables the display means to perform a specific display (a display of the award number corresponding to the value of the award number counter 74e); and
Equipped with
The display control means
a first display control means for causing the display means to perform the predetermined display when the predetermined display information is stored in the first storage means (a function for executing the processes of steps S1401 to S1403 and S1409 of the main MPU 72 in the first embodiment, a function for executing the processes of steps S5403 to S5405 and S5411 of the main MPU 72 in the seventh embodiment, and a function for executing the processes of steps S5801, S5803, S5804 and S5810 of the main MPU 72 in the ninth embodiment);
A gaming machine characterized by comprising: a second display control means (a function of executing the processing of steps S1407 to S1409 of the main MPU 72 in the first embodiment, a function of executing the processing of steps S5409 to S5411 of the main MPU 72 in the seventh embodiment, and a function of executing the processing of steps S5808 to S5810 of the main MPU 72 in the ninth embodiment) that causes the display means to perform the specific display based on the specific display information stored in the second storage means when the specified display information is not stored in the first storage means.

Feature C1 makes it possible to recognize that a situation in which a predetermined display should be performed on the display means is present based on the fact that predetermined display information is stored in the first storage means, and to recognize that a specific display should be performed on the display means based on the fact that predetermined display information is not stored in the first storage means. This makes it possible to switch between states in which a predetermined display is being performed on the display means and states in which a specific display is being performed without the need for a dedicated flag or other storage means for setting information for switching between these states, and simplifies the processing configuration for switching between these states.

Feature C2: The first storage execution means includes a predetermined display information setting means (a function for executing the processing of steps S1101 to S1105 of the main MPU 72 in the first embodiment, a function for executing the processing of steps S5501 to S5505 of the main MPU 72 in the eighth embodiment, and a function for executing the processing of steps S5701 to S5705 of the main MPU 72 in the ninth embodiment) that stores the predetermined display information in the first storage means in a predetermined situation (a situation in which the in-game flag of the main RAM 74 is set to "1"), thereby causing the predetermined display to be performed on the display means,
a third display execution means (a function of executing the processes of steps S1407 to S1409 of the main MPU 72 in the first embodiment, a function of executing the processes of steps S5409 to S5411 of the main MPU 72 in the seventh embodiment, and a function of executing the processes of steps S5808 to S5810 of the main MPU 72 in the ninth embodiment) that causes the display means to perform the specific display based on the specific display information stored in the second storage means when an end trigger for the predetermined situation (the generation of a third stop command) occurs,
The gaming machine described in Feature C1 is characterized in that the second display control means is equipped with a specific display execution means (a function of executing the processing of steps S1407 to S1409 of the main MPU 72 in the first embodiment, a function of executing the processing of steps S5409 to S5411 of the main MPU 72 in the seventh embodiment, and a function of executing the processing of steps S5808 to S5810 of the main MPU 72 in the ninth embodiment) that causes the display means to perform the specific display based on the specific display information stored in the second storage means when the specific display information is not stored in the first storage means in the specified situation.

According to feature C2, in a configuration in which a specific display is displayed on the display means when a trigger for ending a specific situation occurs, and the display means displays the specific display if the specific display is not displayed in the specific situation, the specific display may be displayed by setting specific display information in the first storage means in the specific situation. By displaying the specific display in the specific situation, it is possible to prevent the state in which the specific display is displayed on the display means from continuing for a long period of time.

Feature C3: A predetermined state generating means (a function for executing the processes of steps S5401, S5402, and S5411 of the main MPU 72 in the seventh embodiment, and a function for executing the processes of steps S5801 to S5804 and S5810 of the main MPU 72 in the ninth embodiment) is provided to set the display means to a predetermined state (a completely off state in the seventh and eighth embodiments, and a state in which a non-guiding display is being performed on the dual-purpose display unit 66 in the ninth embodiment),
The gaming machine described in Feature C2 is characterized in that the predetermined state generating means is equipped with predetermined state execution means (a function of executing the processing of step S5201 of the main MPU 72 in the seventh embodiment, a function of executing the processing of steps S5401, S5402, and S5411 of the main MPU 72, a function of executing the processing of step S5507 of the main MPU 72 in the eighth embodiment, a function of executing the processing of step S5706 of the main MPU 72 in the ninth embodiment, and a function of executing the processing of steps S5801 to S5804 and S5810 of the main MPU 72) that sets the display means to the predetermined state if the predetermined display is not performed in the predetermined situation started after the predetermined situation has been triggered after the predetermined situation has been triggered.

According to feature C3, in a configuration in which a specific display is made on the display means when a trigger for ending a specific situation occurs, and the specific display is made on the display means if the specific display is not made on the display means in a specific situation that starts after the specific situation, by setting the display means to a specific state between the specific display made on the trigger for ending a specific situation and the specific display made in the specific situation that starts after the specific situation, it is possible to prevent the state in which the specific display is made on the display means from continuing for a long period of time before and after the start of a specific situation in which the specific display is not made.

Feature C4: The predetermined state generating means includes a predetermined storage executing means (a function for executing the process of step S5201 of the main MPU 72 in the seventh embodiment, a function for executing the process of step S5507 of the main MPU 72 in the eighth embodiment) that stores predetermined state information for setting the display means to the predetermined state (the extinguishing data "255" set in the display number counter 74e in the eighth embodiment) in the second storage means,
The gaming machine described in feature C3 is characterized in that the predetermined state execution means sets the display means to the predetermined state based on the predetermined state information being stored in the second storage means.

According to feature C4, by storing the predetermined state information in the second storage means, it is possible to set the display means to a predetermined state without the need to provide a dedicated storage means for setting the predetermined state information in addition to the first and second storage means. Furthermore, it is possible to simplify the processing configuration for switching from a state in which a specific display is being displayed on the display means to a state in which the display means is in a predetermined state, and for switching from a state in which the display means is in a predetermined state to a state in which a specific display is being displayed on the display means.

Feature C5. A symbol display means (reels 32L, 32M, 32R) that displays symbols in a variable manner;
a start operation means (start lever 41) that is operated to start the variable display of the symbols on the symbol display means;
A predetermined acceleration control means (a function of executing the processing of steps S1001 to S1002 of the main MPU 72 in the first embodiment, a function of executing the processing of steps S5301 to S5305 of the main MPU 72 in the seventh embodiment) that executes acceleration control of the picture display means (the processing of steps S1001 to S1002 of the main MPU 72 in the first embodiment, and the processing of steps S5301 to S5305 of the main MPU 72 in the seventh embodiment) based on the operation of the start operation means;
Equipped with
the predetermined situation is a situation that starts at a timing before a timing at which acceleration control of the symbol display means is started based on an operation of the start operation means,
The gaming machine according to feature C3 or C4, wherein the predetermined state ends before the acceleration control of the picture display means is completed in the next started predetermined situation.

According to feature C5, by ending the state in which the display means is in a predetermined state before the acceleration control of the picture display means is completed, it is possible to make the display means capable of performing a specific display before the acceleration control of the picture display means is completed.

Feature C6: The device is provided with a stop operation means (stop buttons 42 to 44) that is operated to stop the variable display of the patterns in the pattern display means,
The predetermined display information is information indicating the type of operation mode of the stop operation means (the order in which the stop buttons 42 to 44 are operated),
the predetermined display is a display that notifies the operation mode of the stop operation means,
The gaming machine described in feature C5 is characterized in that the specific display execution means causes the display means to display the specific display when the operation mode of the stop operation means is not notified in the specified situation.

According to feature C6, the operation mode of the stop operation means can be notified by displaying a predetermined display on the display means. In addition, a specific display is also displayed on the display means. With feature C5 above, the predetermined state ends before the acceleration control of the pattern display means is completed. Therefore, if the operation mode of the stop operation means is not notified in a predetermined situation, the acceleration control of the pattern display means can be completed with the specific display being displayed on the display means.

Feature C7: A predetermined state generating means is provided for setting the display means to a predetermined state (a completely turned off state in the seventh and eighth embodiments, and a state in which a non-guiding display is being performed on the dual-purpose display unit 66 in the ninth embodiment),
The predetermined state generating means includes a predetermined state switching means (a function of executing the process of step S5201 of the main MPU 72 in the seventh embodiment, a function of executing the process of step S5507 of the main MPU 72 in the eighth embodiment, and a function of executing the process of step S5706 of the main MPU 72 in the ninth embodiment) that switches from a state in which the specific display is being performed on the display means to a state in which the display means is in a predetermined state,
A gaming machine described in any one of features C1 to C6, characterized in that the second storage execution means is equipped with a specific display information setting means (a function for executing the processing of step S1208 of the main MPU 72 in the first embodiment, a function for executing the processing of step S5304 of the main MPU 72 in the seventh embodiment, and a function for executing the processing of step S5604 of the main MPU 72 in the eighth embodiment) that stores the specific display information in the second storage means when the display means is in the specified state, thereby switching from the state in which the display means is in the specified state to a state in which the specific display is being performed on the display means.

Feature C7 prevents the display means from continuing to display a specific display for a long period of time by setting the display means to a predetermined state while the display means is displaying a specific display.

Feature C8. The gaming machine described in Feature C7 is characterized in that the predetermined state switching means includes means for setting the display means to the predetermined state (a function for executing the processes of steps S5401, S5402, and S5411 in the main MPU 72) based on the second storage means storing predetermined state information ("255," which is the light-off data set in the award number counter 74e in the eighth embodiment), or means for setting the display means to the predetermined state (a function for executing the processes of steps S5802 to S5804 and S5810 in the main MPU 72) based on the first storage means storing predetermined state information ("10," which is the non-guiding data set in the stop order type counter 74m in the ninth embodiment).

According to feature C8, in both a configuration in which the predetermined state information is stored in the first storage means and a configuration in which the predetermined state information is stored in the second storage means, the display means can be set to a predetermined state without the need to provide a dedicated storage means for setting the predetermined state information in addition to the first and second storage means. In a configuration in which the predetermined state information is stored in the second storage means, the processing configuration for switching from a state in which a specific display is being performed on the display means to a state in which the display means is in a predetermined state, and switching from a state in which the display means is in a predetermined state to a state in which a specific display is being performed on the display means, can be simplified.

Feature C9: A predetermined display determination means (a function for executing the processing of steps S5501 to S5503 of the main MPU 72 in the eighth embodiment, a function for executing the processing of steps S5701 to S5703 of the main MPU 72 in the ninth embodiment) is provided that executes predetermined display determination processing (the processing of steps S5501 to S5503 of the eighth embodiment, the processing of steps S5701 to S5703 of the main MPU 72 in the ninth embodiment) that determines whether or not the execution condition for the predetermined display is met when the specific display is being displayed on the display means,
the first storage execution means, when it is determined in the predetermined display determination process that the execution condition for the predetermined display is satisfied, stores the predetermined display information in the first storage means, thereby switching from a state in which the specific display is being performed on the display means to a state in which the predetermined display is being performed on the display means;
The gaming machine described in feature C7 or C8 is characterized in that the predetermined state switching means switches from a state in which the specific display is being performed on the display means to a state in which the display means is in the predetermined state when it is determined in the predetermined display determination process that the execution conditions for the predetermined display are not met.

According to feature C9, a predetermined determination process is executed while a specific display is being displayed on the display means, and if the predetermined determination process determines that the conditions for executing the specific display are met, the display means switches from a state where the specific display is being displayed on the display means to a state where the specific display is being displayed on the display means. This prevents the specific display from continuing for a long period of time on the display means. Furthermore, if the predetermined determination process determines that the conditions for executing the specific display are not met, the display means switches from a state where the specific display is being displayed on the display means to a state where the display means is in a predetermined state. This prevents the specific display from continuing for a long period of time on the display means, even if it is determined that the conditions for executing the specific display are not met and the specific display is not executed on the display means.

Feature C10. A symbol display means (reels 32L, 32M, 32R) that displays symbols in a variable manner;
a start operation means (start lever 41) that is operated to start the variable display of the symbols on the symbol display means;
stop operation means (stop buttons 42 to 44) that are operated to stop the variable display of the patterns in the pattern display means;
A specific situation initiation means (a function of executing the processing of steps S1002 to S1003 of the main MPU 72 in the first embodiment) that initiates a specific situation in which the variable display of the pattern can be stopped by operating the stop operation means after the variable display of the pattern has started (a situation in which the operation of the stop buttons 42 to 44 is enabled);
Equipped with
The gaming machine described in feature C9 is characterized in that, when it is determined in the predetermined display determination process that the conditions for executing the predetermined display have not been met, the specific display information setting means stores the specific display information in the second storage means at a timing later than the timing at which the specific situation begins (in the eighth embodiment, the timing at which the duration of the all-off state has elapsed and the value of the off time counter 74δ becomes "0"), thereby switching from a state in which the display means is in the predetermined state to a state in which the specific display is being performed on the display means.

According to feature C10, by configuring the display means to switch from a predetermined state to a state in which a specific display is being displayed on the display means at a timing after the timing at which the specific situation begins, the display means can be kept in the predetermined state for a longer period of time compared to a configuration in which the display means switches from a predetermined state to a state in which a specific display is being displayed on the display means at the timing at which the specific situation begins or at a timing before that timing. This makes it easier for players and amusement hall managers to recognize that the display means is in the predetermined state.

Feature C11. A symbol display means (reels 32L, 32M, 32R) that displays symbols in a variable manner;
a start operation means (start lever 41) that is operated to start the variable display of the symbols on the symbol display means;
stop operation means (stop buttons 42 to 44) that are operated to stop the variable display of the patterns in the pattern display means;
Equipped with
The predetermined display information is information indicating the type of operation mode of the stop operation means (the order in which the stop buttons 42 to 44 are operated),
A gaming machine according to any one of features C1 to C10, wherein the predetermined display is a display that notifies the operation mode of the stop operation means.

Feature C11 makes it possible to understand the operation mode of the stop operation means based on the content of the predetermined display displayed on the display means.

Feature C12: The specific display information is information indicating the number of game values (medals, virtual medals, game media) awarded to the player,
A gaming machine according to any one of features C1 to C11, wherein the specific display is a display that notifies the player of the number of gaming values that have been awarded to the player.

Feature C12 makes it possible to ascertain the number of game values awarded to a player based on the content of the specific display displayed on the display means.

Feature C13. The second storage execution means includes a first specific display information setting means (a function of executing the processes of steps S607 and S612 of the main MPU 72 in the first embodiment) that stores, as the specific display information, first specific display information (information of "0" set in the award number counter 74e) indicating that the game value has not been awarded to the player in the second storage means,
The gaming machine described in feature C12 is characterized in that, when the specified display information is not stored in the first storage means and the first specific display information is stored in the second storage means, the second display control means causes the display means to display the first specific display (displaying the number of awards of ``00'') as the specific display based on the first specific display information, indicating that the game value has not been awarded to the player.

Feature C13 allows the player to know that no gaming value has been awarded to the player by checking the first specific display displayed on the display means. In a configuration including features C1 and C12 above, in which, when predetermined display information is not stored in the first storage means, a specific display is displayed on the display means to notify the player of the number of gaming values awarded to the player based on the specific display information stored in the second storage means, the first specific display is displayed on the display means based on the first specific display information stored in the second storage means even when no gaming value has been awarded to the player. This simplifies the processing configuration for displaying a specific display on the display means based on the specific display information stored in the second storage means when predetermined display information is not stored in the first storage means.

Note that one or more of the following configurations may be applied to the configurations of Features C1 to C13: Features A1 to A19, Features B1 to B9, Features C1 to C13, Features D1 to D7, Features E1 to E6, Features F1 to F9, and Features G1 to G7. This allows for a synergistic effect to be achieved through the combined configurations.

The invention relating to the features of Feature Group C above can solve the following problems:

Pachinko machines and slot machines are well-known gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls. The gaming balls stored in the storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Furthermore, when the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning. If the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result after the reels have stopped spinning corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary for the display control of the display means to be executed appropriately, and there is still room for improvement in this regard.

<Feature Group D>
Feature D1. Numerical value specifying means (row numbers "1213" to "1215" of the main MPU 72 in the first embodiment) for specifying whether the numerical information to be determined (the value of the index value counter 74f) is within a reference numerical range (a numerical range of "1" to "9" in the lottery result corresponding process in the first embodiment, and a numerical range of "11" to "15" in the start-time additional process in the first, tenth to thirteenth embodiments) that does not include both the predetermined minimum value ("0" in the first, tenth to thirteenth embodiments) and the predetermined maximum value ("255" in the first, tenth to thirteenth embodiments) of the numerical range between the predetermined minimum value ("0" in the first, tenth to thirteenth embodiments) and the predetermined maximum value ("255" in the first, tenth to thirteenth embodiments) a function to execute the command with line number "1215", a function to execute the command with line number "1302" to line number "1304" of the primary MPU 72, a function to execute the command with line number "1402" to line number "1404" of the primary MPU 72 in the tenth embodiment, a function to execute the command with line number "1502" to line number "1504" of the primary MPU 72 in the eleventh embodiment, a function to execute the processing of steps S6003 to S6005 of the primary MPU 72 in the twelfth embodiment, and a function to execute the command with line number "1602" to line number "1604" of the primary MPU 72 in the thirteenth embodiment);
Based on the fact that the numerical value specifying means has specified that the numerical information to be judged is included in the reference numerical range, a predetermined process (a process of executing the instructions from line number "1216" to line number "1217" in the first embodiment, a process of executing the instructions from line number "1305" to line number "1309" in the tenth embodiment, a process of executing the instructions from line number "1405" to line number "1409" in the eleventh embodiment, a process of executing the instructions from line number "1505" to line number "1511" in the twelfth embodiment, the process of steps S6006 to S6020 in the twelfth embodiment, and a process of executing the instructions from line number "1605" to line number "1609" in the thirteenth embodiment) is executed. a predetermined processing execution means (a function for executing the instructions of line numbers "1216" to "1217" of the primary MPU 72 in the first embodiment, a function for executing the instructions of line numbers "1305" to "1309" of the primary MPU 72, a function for executing the instructions of line numbers "1405" to "1409" of the primary MPU 72 in the tenth embodiment, a function for executing the instructions of line numbers "1505" to "1511" of the primary MPU 72 in the eleventh embodiment, a function for executing the processing of steps S6006 to S6020 of the primary MPU 72 in the twelfth embodiment, and a function for executing the instructions of line numbers "1605" to "1609" of the primary MPU 72 in the thirteenth embodiment);
Equipped with
The numerical value specifying means
A predetermined calculation (a process of executing a SUB command of line number "1302" in the first embodiment, a process of executing an ADD command of line number "1213", a process of executing a SUB command of line number "1402" in the tenth embodiment) that enables the first boundary value, which is one of the minimum and maximum values of the reference numerical range ("9" in the lottery result corresponding processing, "11" in the start-up additional processing), to become the corresponding value of the predetermined minimum and maximum values in the magnitude relationship ("255" in the lottery result corresponding processing, "0" in the start-up additional processing), and the second boundary value, which is the other of the minimum and maximum values of the reference numerical range ("1" in the lottery result corresponding processing, "15" in the start-up additional processing), to become the changed boundary value ("247" in the lottery result corresponding processing, "4" in the start-up additional processing) that is changed by the amount of change required to make the first boundary value the corresponding value. a predetermined calculation execution means for executing the following operations on the numerical information to be determined (a function for executing the SUB command of line number "1302" of the master MPU 72 in the first embodiment, a function for executing the ADD command of line number "1213" of the master MPU 72, a function for executing the SUB command of line number "1402" of the master MPU 72 in the tenth embodiment, a function for executing the SUB command of line number "1502" of the master MPU 72 in the eleventh embodiment, a function for executing the processing of step S6003 of the master MPU 72 in the twelfth embodiment, and a function for executing the SUB command of line number "1602" of the master MPU 72 in the thirteenth embodiment);
A specific execution means (a function of executing the instructions of line numbers "1214" to "1215" of the main MPU 72 in the first embodiment, a function of executing the instructions of line numbers "1303" to "1304" of the main MPU 72 in the first embodiment) for determining whether or not the numerical information to be determined is included in the reference numerical range by determining the magnitude relationship between the calculation result after the execution of the predetermined calculation on the numerical information to be determined (the numerical information stored in the A register 101b after the calculation) and the post-variation boundary value. a function of executing the instructions of line numbers "1403" to "1404" of the primary MPU 72 in the tenth embodiment, a function of executing the instructions of line numbers "1503" to "1504" of the primary MPU 72 in the eleventh embodiment, a function of executing the processing of steps S6004 to S6005 of the primary MPU 72 in the twelfth embodiment, and a function of executing the instructions of line numbers "1603" to "1604" of the primary MPU 72 in the thirteenth embodiment)
A gaming machine characterized by comprising:

Feature D1 performs a predetermined calculation on the numerical information to be determined, and determines whether the numerical information to be determined is within a reference numerical range by determining whether the calculation result after performing the predetermined calculation is larger or smaller than the post-variation boundary value. This simplifies the processing configuration for determining whether the numerical information to be determined is within the reference numerical range, compared to a configuration that performs a process to determine whether the numerical information to be determined is equal to or greater than the minimum value of the reference numerical range, and a process to determine whether the numerical information to be determined is equal to or smaller than the maximum value of the reference numerical range, in order to determine whether the numerical information to be determined is within the reference numerical range.

Feature D2: The predetermined operation execution means executes, as the predetermined operation, a predetermined arithmetic operation (the SUB instruction at line number "1302" in the first embodiment, the SUB instruction at line number "1402" in the tenth embodiment, the SUB instruction at line number "1502" in the eleventh embodiment, the process of step S6003 in the twelfth embodiment, and the SUB instruction at line number "1602" in the thirteenth embodiment) of subtracting the first boundary value, which is the minimum value of the reference numerical range, from the numerical information of the determination target. a arithmetic operation execution means (a function for executing the instruction of line number "1302" of the primary MPU 72 in the first embodiment, a function for executing the instruction of line number "1402" of the primary MPU 72 in the tenth embodiment, a function for executing the instruction of line number "1502" of the primary MPU 72 in the eleventh embodiment, a function for executing the processing of step S6003 of the primary MPU 72 in the twelfth embodiment, and a function for executing the instruction of line number "1602" of the primary MPU 72 in the thirteenth embodiment),
The predetermined arithmetic operation is an operation in which, when the numerical information to be judged is numerical information equal to or greater than the first boundary value, numerical information smaller than the numerical information to be judged by the first boundary value becomes the operation result after execution of the predetermined arithmetic operation; when the numerical information to be judged is the second boundary value which is the maximum value of the reference numerical range, the changed boundary value smaller than the second boundary value by the first boundary value becomes the operation result after execution of the predetermined arithmetic operation; and when the numerical information to be judged is numerical information smaller than the first boundary value, numerical information larger than the changed boundary value becomes the operation result after execution of the predetermined arithmetic operation
The gaming machine described in Feature D1 is characterized in that the identification execution means is equipped with a numerical range identification means (a function for executing instructions from line number "1303" to line number "1304" of the main MPU 72 in the first embodiment, a function for executing instructions from line number "1403" to line number "1404" of the main MPU 72 in the tenth embodiment, a function for executing instructions from line number "1503" to line number "1504" of the main MPU 72 in the eleventh embodiment, a function for executing processing from step S6004 to step S6005 of the main MPU 72 in the twelfth embodiment, and a function for executing instructions from line number "1603" to line number "1604" of the main MPU 72 in the thirteenth embodiment) that identifies that the numerical range of the object to be determined is included in the reference numerical range by determining that the calculation result after execution of the specified arithmetic operation on the numerical information of the object to be determined is equal to or less than the post-fluctuation boundary value.

According to feature D2, if the numerical information to be evaluated is greater than the second boundary value, which is the maximum value of the reference numerical range, the numerical information greater than the post-variation boundary value becomes the calculation result after the execution of the specified arithmetic operation. Furthermore, if the numerical information to be evaluated is less than the minimum value of the reference numerical range, the numerical information greater than the post-variation boundary value becomes the calculation result after the execution of the specified arithmetic operation. Therefore, if the numerical information to be evaluated is not included in the reference numerical range, the numerical information greater than the post-variation boundary value can be used as the calculation result after the execution of the specified arithmetic operation. On the other hand, if the numerical information to be evaluated is included in the reference numerical range (numerical information greater than or equal to the first boundary value and less than or equal to the second boundary value), the numerical information less than or equal to the post-variation boundary value becomes the calculation result after the execution of the specified arithmetic operation. Therefore, by determining whether the calculation result after the execution of the specified arithmetic operation is less than or equal to the post-variation boundary in this determination, it is possible to determine whether the numerical range to be evaluated is included in the reference numerical range. This reduces the number of determination processes required to determine whether the numerical information being determined is within the reference numerical range, and simplifies the processing configuration for determining whether the numerical information being determined is within the reference numerical range, compared to a configuration that performs two determinations: first, determining whether the numerical information being determined is equal to or greater than the minimum value of the reference numerical range, and then determining whether the numerical information being determined is equal to or less than the maximum value of the reference numerical range.

Feature D3. The gaming machine described in Feature D2 is characterized by including a predetermined numerical value determination means (a function of executing the instructions of line numbers "1306" and "1307" of the main MPU 72 in the first embodiment) that determines whether the numerical information to be determined falls within the first reference numerical range, which includes the first boundary value (a numerical range of "11" to "13" in the start-up addition processing in the first embodiment), or a second reference numerical range, which includes the second boundary value (a numerical range of "14" to "15" in the start-up addition processing in the first embodiment), based on the magnitude relationship between the calculation result after execution of the predetermined arithmetic operation and a predetermined boundary value ("3" in the start-up addition processing in the first embodiment) that is greater than the predetermined minimum value and less than the post-fluctuation boundary value.

Feature D3 determines whether the numerical information to be determined falls within a reference numerical range based on the result of a predetermined arithmetic operation, and then determines whether the numerical information to be determined falls within the first or second reference numerical range based on the magnitude relationship between the result of the predetermined arithmetic operation and a predetermined boundary value. This simplifies the processing configuration for determining whether the numerical information to be determined falls within the first or second reference numerical range, compared to a configuration that performs two determinations: one determining whether the numerical information to be determined is equal to or greater than the minimum value of the predetermined reference numerical range, and the other determining whether the numerical information to be determined is equal to or less than the maximum value of the predetermined reference numerical range.

Feature D4. A gaming machine as described in Feature D3, characterized in that the number of bits required to represent the predetermined boundary value (2 bits in the start-up addition process in the first embodiment) is fewer than the number of bits (4 bits) required to represent the boundary value ("14") between the first reference numerical range and the second reference numerical range.

According to Feature D4, the configuration of Feature D2 is included, and the predetermined arithmetic operation is an operation that subtracts the minimum value of the reference numerical range from the numerical information to be determined. This makes it possible to use fewer bits to represent the predetermined boundary value than the number of bits required to represent the boundary value between the first reference numerical range and the second reference numerical range. By reducing the number of bits in the information indicating the predetermined boundary value, it is possible to reduce the data volume of the information stored for performing the process of determining whether the result of the predetermined arithmetic operation is greater than or equal to the predetermined boundary value.

Feature D5: A specific arithmetic operation means (a function of executing the instruction of the main MPU 72 of the eleventh embodiment with the line number "1506") that executes a specific arithmetic operation (a CP instruction of the line number "1506" in the eleventh embodiment) that subtracts a specific boundary value ("2" in the eleventh embodiment) that is greater than the predetermined minimum value and less than the fluctuating boundary value from the operation result after the execution of the predetermined arithmetic operation;
A specific processing execution means (a function of executing the instructions of line numbers "1505" to "1511" of the main MPU 72 in the 11th embodiment) that uses the result of the specific arithmetic operation to execute a specific processing (a processing for executing the first additional lottery, the second additional lottery, or the third additional lottery in the 11th embodiment);
A gaming machine according to feature D2, characterized by comprising:

According to feature D5, by generating information (the result of the specific arithmetic operation) to be used to execute a specific process using the calculation result after execution of the specific arithmetic operation, the processing configuration for generating information to be used to execute a specific process can be simplified compared to a configuration in which information to be used to execute a specific process is generated using numerical information to be judged, regardless of the specific arithmetic operation.

Feature D6: A first information storage area (zero flag ZF) in which specific information (information "1") is set based on the occurrence of a first event (an event in which the result of the CP instruction at line number "1506" becomes "0") that occurs in the specific arithmetic operation when the result of the execution of the predetermined arithmetic operation is the same numerical information as the specific boundary value;
a second information storage area (carry flag CF) in which the specific information is set based on the occurrence of a second event (an event in which a carry to the most significant bit occurs during execution of the CP instruction in line number "1506") that occurs in the specific arithmetic operation when the calculation result after execution of the predetermined arithmetic operation is numerical information less than the specific boundary value; and
Equipped with
The specific process execution means
a first specific processing execution means (a function of executing the instructions of line numbers "1508", "1509" and "1511" of the main MPU 72 in the 11th embodiment) that executes a first specific processing (a processing for executing a third additional lottery in the 11th embodiment) when the specific information is set in the first information storage area after the specific arithmetic operation is executed;
a second specific processing execution means (a function of executing the instructions of line numbers "1510" and "1511" of the main MPU 72 in the 11th embodiment) that executes a second specific processing (a processing for executing a second additional lottery in the 11th embodiment) when the specific information is set in the second information storage area after the specific arithmetic operation is executed;
a third specific processing execution means (a function of executing the instructions of line numbers "1505", "1507", "1509" and "1511" of the main MPU 72 in the 11th embodiment) that executes a third specific processing (a processing for executing the first additional lottery processing in the 11th embodiment) when the specific information is not set in either the first information storage area or the second information storage area after the specific arithmetic operation is executed;
A gaming machine according to feature D5, characterized by being equipped with:

Feature D6 enables the first, second, and third specific processing to be performed in a manner corresponding to the numerical information of the target object. When it is determined based on the result of a predetermined arithmetic operation that the numerical information of the target object falls within a reference numerical range, the result of the predetermined arithmetic operation is used to perform a specific arithmetic operation, and one of the first, second, and third specific processing is performed based on the state of the first information storage area and the second information storage area after the specific arithmetic operation is performed. Therefore, compared to a configuration that performs two operations—one to determine whether the numerical information of the target object is less than a value greater than the minimum value of the reference numerical range by a specific boundary value, and another to determine whether the numerical information of the target object is a value greater than the minimum value of the reference numerical range by the specific boundary value—the number of operations required to perform the first, second, and third specific processing in a manner corresponding to the numerical information of the target object when the numerical information of the target object falls within the reference numerical range can be reduced. This simplifies the processing configuration for executing the first identification process, the second identification process, and the third identification process in a manner corresponding to the numerical information of the object of judgment when the numerical information of the object of judgment is within the reference numerical range.

Feature D7. A gaming machine described in Feature D5 or D6, characterized in that the number of bits required to represent the specific boundary value (2 bits in the 11th embodiment) is fewer than the number of bits (4 bits) required to represent a value ("11" in the 11th embodiment) that is greater than the minimum value of the reference numerical range by the specific boundary value.

Feature D7 has the configuration of feature D2, and the predetermined arithmetic operation is an operation of subtracting the minimum value of the reference numerical range from the numerical information to be determined. This makes it possible to reduce the number of bits required to represent the specific boundary value compared to the number of bits required to represent a value that is greater than the minimum value of the reference numerical range by the specific boundary value. By reducing the number of bits of the information indicating the specific boundary value, it is possible to reduce the data volume of the information stored to perform the specific arithmetic operation.

Note that one or more of the features A1 to A19, B1 to B9, C1 to C13, D1 to D7, E1 to E6, F1 to F9, and G1 to G7 may be applied to the features D1 to D7. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group E>
Feature E1: A predetermined storage area (jump flag JF) that takes either a first state (a state in which the value of the jump flag JF is "1" in the power-off standby process in the first embodiment, and a state in which the value of the jump flag JF is "0" in the AT state signal setting process) or a second state (a state in which the value of the jump flag JF is "0" in the power-off standby process, and a state in which the value of the jump flag JF is "1" in the AT state signal setting process) depending on the content of the command to be executed;
a predetermined jump instruction execution means (JRS execution circuit 107, a function to execute the JRS instruction of line number "1002" in the main MPU 72, a function to execute the JRS instruction of line number "1110" in the main MPU 72) which, when a predetermined jump instruction (the JRS instruction of line number "1002" in the first embodiment, the JRS instruction of line number "1110"), becomes an instruction to be executed, jumps to a predetermined program address set as a jump destination for the predetermined jump instruction ("ADR101" in the power cutoff standby process, and "ADR114" in the AT state signal setting process) and, when the predetermined jump instruction becomes an instruction to be executed, proceeds to a program address set as a next instruction of the predetermined jump instruction without jumping to the predetermined program address set as a jump destination for the predetermined jump instruction, when the predetermined storage area is in the second state;
Equipped with
In the predetermined programs (power cutoff standby processing program, AT status signal setting processing program) in which the predetermined jump command is set, predetermined commands (an OUT command at line number "1001" and an XOR command at line number "1109" executed by the main MPU 72 in the first embodiment) for executing predetermined processes (a process for executing the command at line number "1001" and a process for executing the command at line number "1109" in the first embodiment) are set as commands to be executed before the predetermined jump command,
A gaming machine characterized in that the specified memory area enters the first state when the specified command is executed.

According to Feature E1, in a configuration in which a jump to a predetermined program address occurs when a predetermined jump instruction is executed while a predetermined storage area is in a first state, the predetermined storage area enters the first state when the predetermined instruction is executed. Furthermore, in the predetermined program, the predetermined instruction becomes the execution target before the predetermined jump instruction. Therefore, when a predetermined jump instruction becomes the execution target in the predetermined program, a jump to the jump destination predetermined program address can be performed. The predetermined instruction is an instruction for executing a predetermined process, and also an instruction for placing the predetermined storage area in the first state before the predetermined jump instruction becomes the execution target. Therefore, compared to a configuration in which an instruction for placing the predetermined storage area in the first state before the predetermined jump instruction becomes the execution target is provided as a separate instruction from the instruction for executing the predetermined process, the data size of the program for executing the predetermined process and placing the predetermined storage area in the first state before the predetermined jump instruction becomes the execution target can be reduced.

Feature E2. A gaming machine as described in Feature E1, characterized in that when the predetermined command is executed, the predetermined memory area enters the first state, regardless of the state of the predetermined memory area before the execution of the predetermined command.

Feature E2 allows a jump to a specified program address when a specified jump instruction is executed, regardless of whether the state of the specified memory area before the execution of the specified instruction is in the first state or the second state.

Feature E3: The predetermined program address is a program address at which an instruction to be executed prior to the predetermined jump instruction is set when the predetermined program is executed from the first program address in the predetermined program,
A gaming machine according to feature E1 or E2, characterized in that the instructions set between the specified program address and the program address where the specified jump instruction is set are repeatedly executed.

Feature E3 allows for the repeated execution of instructions set between a predetermined program address and the program address where the predetermined jump instruction is set, using one predetermined jump instruction. This configuration includes feature E1, in which a predetermined instruction is set in the predetermined program as the instruction to be executed before the predetermined jump instruction, and the predetermined memory area is configured to enter the first state when the predetermined instruction is executed. This prevents situations where, when instructions set between a predetermined program address and the program address where the predetermined jump instruction is set are being repeatedly executed, the predetermined jump instruction becomes the execution target but does not result in a jump to the predetermined program address.

Feature E4. A gaming machine as described in Feature E3, characterized in that the instructions set between the predetermined program address and the program address where the predetermined jump instruction is set are repeatedly executed until the supply of operating power is stopped.

Feature E4 allows a state in which, by using one predetermined jump instruction, instructions set between a predetermined program address and the program address where the predetermined jump instruction is set are repeatedly executed until the supply of operating power is stopped. This allows the supply of operating power to be stopped in a manner that does not cause an abnormality when the supply of operating power is resumed, regardless of the timing at which the supply of operating power is stopped.

Feature E5: A specific state generating means (abnormality monitoring circuit 86) is provided that sets a specific state (a state in which the program is reset) when a state in which a predetermined event (an event in which an initial value is set in the watchdog timer 86a) does not occur continues for a predetermined period (240 milliseconds),
A gaming machine described in feature E4, characterized in that the instructions set between the specified program address and the program address where the specified jump instruction is set include an instruction for causing the specified event (the instruction with line number "1001" in the first embodiment).

Feature E5 prevents a state in which a specified event does not occur from continuing for a specified period of time when instructions set between a specified program address and a program address where a specified jump instruction is set are repeatedly executed. This prevents a specific state from occurring before the supply of operating power is stopped after instructions set between a specified program address and a program address where a specified jump instruction is set are repeatedly executed.

Feature E6. A gaming machine described in any one of Features E1 to E5, wherein the predetermined command is a command for generating information (a value of "0") to be set in a predetermined storage means (AT status signal counter 74w) after jumping to the predetermined program address.

According to feature E6, the specified instruction is an instruction for generating information to be set in the specified storage means, and an instruction for setting the specified storage area to the first state before the specified jump instruction is executed. Therefore, compared to a configuration in which an instruction for setting the specified storage area to the first state before the specified jump instruction is executed is provided as a separate instruction from the instruction for generating information to be set in the specified storage means, the data size of the program for generating information to be set in the specified storage means and setting the specified storage area to the first state before the specified jump instruction is executed can be reduced.

Note that one or more of the features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 may be applied to the features E1 to E6. This allows for a synergistic effect to be achieved through the combined features.

<Feature Group F>
Feature F1. In a specific program (a program for start-time addition processing), a first predetermined program address ("ADR131" in the first embodiment, "ADR141" in the tenth embodiment, "ADR152" in the eleventh embodiment, and "ADR171" in the thirteenth embodiment) is set to a first predetermined jump instruction (a JRS instruction at line number "1307" in the first embodiment, a JR instruction at line number "1407" in the tenth embodiment, a JR instruction at line number "1509" in the eleventh embodiment, and a JRS instruction at line number "1607" in the thirteenth embodiment) that sets a second predetermined program address ("ADR132" in the first embodiment, "ADR142" in the tenth embodiment, "ADR153" in the eleventh embodiment, and "ADR172" in the thirteenth embodiment) as a jump destination,
A gaming machine characterized in that a second predetermined jump command (a JP command at line number "1309" in the first embodiment, a JP command at line number "1409" in the tenth embodiment, a JP command at line number "1511" in the eleventh embodiment, and a CALL command at line number "1609" in the thirteenth embodiment) is set as the second predetermined program address, with a third predetermined program address ("ADR133" in the first, tenth, and eleventh embodiments, and the start address of the program for lottery execution processing in the thirteenth embodiment) as the jump destination.

According to Feature F1, in a configuration in which a second predetermined jump instruction with a third predetermined program address as the jump destination is set at the second predetermined program address, by setting a first predetermined jump instruction with the second predetermined program address as the jump destination at the first predetermined program address, it is possible to jump from the first predetermined program address via the second predetermined program address to the third predetermined program address without setting a jump instruction with the third predetermined program address as the jump destination at the first predetermined program address, in a manner in which no processing other than processing to change the program address is executed until the jump to the third predetermined program address. This makes it possible to select a jump instruction that can set the second predetermined program address as the jump destination but cannot set the third predetermined program address as the jump destination as the first predetermined program address to be set at the first predetermined program address to jump from the first predetermined program address to the third predetermined program address.

Feature F2. A gaming machine as described in Feature F1, characterized in that when the first predetermined jump command set in the first predetermined program address is executed, a jump to the second predetermined program address occurs, and the second predetermined jump command becomes the target for execution, a jump to the third predetermined program address occurs.

According to Feature F2, in a configuration having the configuration of Feature F1 described above, in which a first predetermined jump instruction is set at the first predetermined program address, which jumps to the second predetermined program address instead of the third predetermined program address, when a jump to the second predetermined program address is made by the first predetermined jump instruction, it is possible to jump to the third predetermined program address without causing a case in which a jump to the third predetermined program address is not made.

Feature F3. A gaming machine described in Feature F1 or F2, wherein the second predetermined jump instruction is an instruction (a JP instruction as an unconditional jump instruction) that unconditionally jumps to the third predetermined program address when the second predetermined jump instruction is executed.

Feature F3 makes it possible to unconditionally jump to the third predetermined program address when the second predetermined jump instruction is executed, without requiring a specific program to set an instruction for creating a situation in which a jump to the third predetermined program address can be made without causing a jump to the third predetermined program address when the second predetermined jump instruction is executed. This simplifies the processing configuration for jumping to the third predetermined program address without causing a jump to the third predetermined program address when a first predetermined jump instruction is used to jump from the first predetermined program address to the second predetermined program address and the second predetermined jump instruction set at the second predetermined program address is executed. Furthermore, even when a second predetermined jump instruction set at the second predetermined program address is executed without jumping to the second predetermined program address using the first predetermined jump instruction, a jump to the third predetermined program address can be made without causing a jump to the third predetermined program address.

Feature F4. A gaming machine described in any one of Features F1 to F3, characterized in that the second predetermined jump instruction is executed even in cases other than when the first predetermined jump instruction is executed to jump to the second predetermined program address.

According to feature F4, the second predetermined jump instruction is not an instruction set solely for jumping to a third predetermined program address when a jump from a first predetermined program address to a second predetermined program address is made by the first predetermined jump instruction. By using an instruction to be executed in cases other than when a jump from the first predetermined program address to a second predetermined program address is made by the first predetermined jump instruction, and by configuring a jump to a third predetermined program address when a jump from the first predetermined program address to a second predetermined program address is made by the first predetermined jump instruction, it is possible to jump to the third predetermined program address by the second predetermined jump instruction set at the second predetermined program address while limiting the number of jump instructions set in a specific program.

Feature F5. A gaming machine described in any one of Features F1 to F4, wherein the first predetermined jump instruction includes information (difference information including a 1-bit code and 4-bit numerical information) for specifying the second predetermined program address to jump to based on the first predetermined program address at which the first predetermined jump instruction is set.

Feature F5 allows for a reduction in the data size of the information set in the first predetermined jump instruction to identify the second predetermined program address, compared to a configuration in which information indicating the entire second predetermined program address is set in the first predetermined jump instruction. This reduces the data size of the first predetermined jump instruction and also reduces the data size of the specific program in which the first predetermined jump instruction is set.

Feature F6. The first predetermined jump instruction is an instruction that can set a program address existing in a predetermined program address range (a range from "the program address where the JRS instruction is set + 1-16" to "the program address where the JRS instruction is set + 1 + 15") as a jump destination based on the first predetermined program address where the first predetermined jump instruction is set,
A gaming machine described in any one of features F1 to F5, characterized in that the third predetermined program address is a program address that does not exist within the predetermined program address range based on the first predetermined program address.

According to Feature F6, in a configuration in which the program addresses that can be set as the jump destination of a first predetermined jump instruction are program addresses that exist within a predetermined program address range based on the first predetermined program address, and the third predetermined program address does not exist within that predetermined program address range, a first predetermined jump instruction set at the first predetermined program address can jump to a second predetermined program address, and a second predetermined jump instruction set at the second predetermined program address can jump to a third predetermined program address. This eliminates the need to set a jump instruction at the first predetermined program address that can jump directly from the first predetermined program address to the third predetermined program address without passing through another program address. This reduces the data size of the jump instruction set at the first predetermined program address.

Feature F7. A gaming machine described in any one of Features F1 to F6, wherein the second predetermined jump command includes information indicating the entire third predetermined program address to which the jump is to be made.

According to Feature F7, by using a second predetermined jump instruction, it is possible to specify a jump destination program address (third predetermined program address) regardless of the program address (second predetermined program address) at which the second predetermined jump instruction is set. Therefore, even if there is a program address (third predetermined program address) that cannot be specified as a jump destination from the first predetermined program address using the first predetermined jump instruction, by jumping to the second predetermined program address using the first predetermined jump instruction set at the first predetermined program address, it is possible to jump from the first predetermined program address to the program address that cannot be specified as a jump destination using the first predetermined jump instruction using the second predetermined jump instruction. This reduces the data size of the jump instruction set at the first predetermined program address compared to a configuration in which a jump instruction that sets information indicating the entire third predetermined program address as information for specifying the jump destination is set at the first predetermined program address.

Feature F8: A predetermined storage area (a jump flag JF in the first and thirteenth embodiments, a zero flag ZF in the tenth embodiment, and a carry flag CF in the eleventh embodiment) is provided that takes one of a predetermined state (a state in which the jump flag JF has a value of "1" in the first and thirteenth embodiments, a state in which the zero flag ZF has a value of "1" in the tenth embodiment, and a state in which the carry flag CF has a value of "1" in the eleventh embodiment) and a specific state (a state in which the jump flag JF has a value of "0" in the first and thirteenth embodiments, a state in which the zero flag ZF has a value of "0" in the tenth embodiment, and a state in which the carry flag CF has a value of "0" in the eleventh embodiment) depending on the content of the instruction to be executed,
A gaming machine described in any one of features F1 to F7, characterized in that the first predetermined jump command is an command to jump to the second predetermined program address as a jump destination when a jump condition that the state of the predetermined memory area is the predetermined state is satisfied.

According to feature F8, when the first predetermined jump instruction is executed while the state of the predetermined storage area is in a predetermined state due to an instruction executed before the first predetermined jump instruction, a jump to a second predetermined program address can be performed, and the second predetermined jump instruction set at the second predetermined program address can be used to jump to a third predetermined program address. Furthermore, when the first predetermined jump instruction is executed while the state of the predetermined storage area is in a specific state due to an instruction executed before the first predetermined jump instruction, a jump to the second predetermined program address can be prevented. Depending on the state of the predetermined storage area when the first predetermined jump instruction is executed, it is possible to jump from the first predetermined program address via the second predetermined program address to the third predetermined program address, or not jump to the second predetermined program address. This allows different processing to be performed depending on the state of the predetermined storage area when the first predetermined jump instruction is executed.

Feature F9. A gaming machine described in any one of Features F1 to F8, characterized in that if the jump condition set in the first predetermined jump instruction is not met when the first predetermined jump instruction is the instruction to be executed in the specific program, the game machine executes a predetermined setting process (the LD instruction at line number "1308") based on the instruction set after the first predetermined jump instruction, and then proceeds to the second predetermined program address where the second predetermined jump instruction is set.

Feature F9 allows for a jump to the second program address without executing the predetermined setting process, or for a jump to the second program address after executing the predetermined setting process, depending on the situation in which the first predetermined jump instruction is executed. This allows for a jump to the third predetermined program address without executing the predetermined setting process, or for a jump to the third predetermined program address after executing the predetermined setting process.

Note that one or more of the features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 may be applied to the features F1 to F9. This allows for a synergistic effect to be achieved by combining these features.

<Feature Group G>
Feature G1. In a predetermined program (a program for executing the lottery result corresponding process in the first embodiment, and a program for executing the start-time addition process in the eleventh and twelfth embodiments), a predetermined first program address ("ADR122" in the first embodiment, "ADR151" in the eleventh embodiment, "ADR161" in the twelfth embodiment) is set to a predetermined first jump command (a JRS command at line number "1208" in the first embodiment, a JR command at line number "1507" in the eleventh embodiment, and a JR command in step S6009 in the twelfth embodiment) that jumps to a predetermined second program address ("ADR125" in the first embodiment, "ADR162" in the eleventh embodiment, and "ADR162" in the twelfth embodiment),
A predetermined second jump instruction (a JRS instruction at line number "1215" in the first embodiment, a JR instruction at line number "1509" in the eleventh embodiment, and a JR instruction at step S6015 in the twelfth embodiment) is set as a jump destination to a predetermined third program address ("ADR126" in the first embodiment, "ADR153" in the eleventh embodiment, and "ADR163" in the twelfth embodiment) as a program address to be executed after the predetermined second program address or the instruction set at the predetermined second program address has become an execution target,
a predetermined reference storage area (a zero flag ZF, a carry flag CF, a jump flag JF) that is referenced to determine whether a jump condition is satisfied when the predetermined first jump instruction becomes an instruction to be executed and when the predetermined second jump instruction becomes an instruction to be executed;
A gaming machine characterized in that the state of the specified reference memory area is maintained before and after execution of the specified first jump command.

According to Feature G1, in a configuration in which a predetermined second jump instruction with a predetermined third program address as the jump destination is set at a predetermined second program address, by setting a predetermined first jump instruction with a predetermined second program address as the jump destination at a predetermined first program address, it is possible to jump from the predetermined first program address to the predetermined third program address via the predetermined second program address, without setting a jump instruction with a predetermined third program address as the jump destination at the predetermined first program address, in a manner in which no processing other than processing to change the program address is performed until the jump to the predetermined third program address. This makes it possible to select a jump instruction that can set the predetermined second program address as the jump destination but cannot set the predetermined third program address as the jump destination as the predetermined first jump instruction set at the predetermined first program address to jump from the predetermined first program address to the predetermined third program address.

By configuring the state of the specified reference memory area to be maintained before and after the execution of the specified first jump instruction, whether the jump condition of the specified second jump instruction is met when the specified second jump instruction becomes the target of execution is determined based on the state of the specified reference memory area at the time the specified first jump instruction becomes the target of execution. This simplifies the processing configuration so that when the jump condition of the specified first jump instruction is met at the specified first program address and a jump is made to the specified second program address, the jump condition of the specified second jump instruction is met and a jump is made to the specified third program address.

In a configuration in which a predetermined second jump instruction specifying a predetermined third program address as the jump destination is set at the program address to be executed after a predetermined second program address becomes the execution target, it is possible to jump from the predetermined first program address to the predetermined second program address, execute the instructions set from the predetermined second program address to the program address immediately preceding the program address where the predetermined second jump instruction is set, and then jump to the predetermined third program address. Because the state of the predetermined reference memory area is maintained before and after execution of the predetermined first jump instruction, if the state of the predetermined reference memory area is maintained before and after execution of the instructions set from the predetermined second program address to the program address immediately preceding the program address where the predetermined second jump instruction is set, whether or not the jump condition for the predetermined second jump instruction is met when the predetermined second jump instruction becomes the execution target can be determined based on the state of the predetermined reference memory area at the time the predetermined first jump instruction becomes the execution target. This simplifies the processing configuration so that when the jump condition in the predetermined first jump instruction is satisfied at a predetermined first program address, a jump is made to a predetermined second program address, and after executing the instructions set from the predetermined second program address to the program address immediately before the program address where the predetermined second jump instruction is set, the jump condition of the predetermined second jump instruction is satisfied and a jump is made to a predetermined third program address.

Feature G2: When the predetermined second jump instruction is executed, the predetermined reference memory area that is referenced is the same as the predetermined reference memory area that is referenced when the predetermined first jump instruction is executed;
A gaming machine described in feature G1, characterized in that the state of the specified reference memory area in which the jump condition is satisfied in the specified second jump command (the state in which the value of the jump flag JF is "1") is the same state as the state of the specified reference memory area in which the jump condition is satisfied in the specified first jump command (the state in which the value of the jump flag JF is "1").

According to feature G2, the predetermined reference memory area referenced when a predetermined second jump instruction is to be executed is the same predetermined reference memory area as the predetermined reference memory area referenced when a predetermined first jump instruction is to be executed. Therefore, the data capacity of the predetermined reference memory area can be reduced compared to a configuration in which the predetermined reference memory area referenced when a predetermined second jump instruction is to be executed is set as a predetermined reference memory area separate from the predetermined reference memory area referenced when a predetermined first jump instruction is to be executed.

In a configuration in which a predetermined second jump instruction is set at a predetermined second program address, a predetermined first jump instruction with the predetermined second program address as the jump destination is set at a predetermined first program address. When the jump condition of the predetermined first jump instruction is satisfied and a jump to the predetermined second program address occurs, the jump condition of the predetermined second jump instruction is also satisfied, resulting in a jump to the predetermined third program address, without causing a situation in which the jump condition of the predetermined second jump instruction is not satisfied. This allows the data size of the jump instruction set at the predetermined first program address to be reduced if the data size of the predetermined first jump instruction that jumps from the predetermined first program address to the predetermined second program address is smaller than the data size of a jump instruction that can jump from the predetermined first program address directly to the predetermined third program address without passing through another program address.

Feature G3. A gaming machine according to Feature G1 or G2, characterized in that the state of the predetermined reference memory area referenced when the predetermined first jump instruction becomes the target of execution changes depending on the content of an instruction executed before the predetermined first jump instruction becomes the target of execution.

Feature G3 allows for a jump from a predetermined first program address via a predetermined second program address to a predetermined third program address, or no jump to the predetermined second program address, depending on the state of a predetermined reference memory area, which changes depending on the content of an instruction executed before the predetermined first jump instruction becomes the target of execution. This simplifies the processing configuration for creating the cases of a jump from a predetermined first program address via a predetermined second program address to a predetermined third program address, or no jump to the predetermined second program address, compared to a configuration that requires an instruction that changes the state of the predetermined reference memory area as a separate instruction from the instruction executed before the predetermined first jump instruction becomes the target of execution, and also reduces the data size of the predetermined program.

Feature G4. A gaming machine according to any one of Features G1 to G3, characterized in that if the predetermined first jump command is executed and the jump condition of the predetermined first jump command is not satisfied, the machine executes a predetermined process (a process that executes the commands set in line numbers "1209" to "1214") and then proceeds to the predetermined second program address.

Feature G4 allows for two cases to occur when a predetermined first jump instruction is executed: a jump from the predetermined first program address to the predetermined second program address without executing the predetermined processing, and a jump to the predetermined second program address after executing the predetermined processing. This allows for processing to be executed corresponding to the situation in which the predetermined first jump instruction is executed. The jump instruction to be executed after executing the predetermined processing (predetermined second jump instruction) is the same jump instruction to be executed when jumping from the predetermined first program address to the predetermined second program address without executing the predetermined processing (predetermined second jump instruction). Therefore, compared to a configuration in which a jump instruction to be executed after executing the predetermined processing is set as a different jump instruction from the jump instruction to be executed when jumping from the predetermined first program address to the predetermined second program address without executing the predetermined processing, the number of jump instructions can be reduced and the data size of the predetermined program can be reduced.

Feature G5. A gaming machine described in any one of Features G1 to G4, characterized in that the predetermined first jump instruction contains information for specifying the predetermined second program address, which is the jump destination, based on the predetermined first program address at which the predetermined first jump instruction is set (for a JRS instruction, difference information including a 1-bit code and 4-bit numerical information; for a JR instruction, difference information including a 1-bit code and 7-bit numerical information).

According to Feature G5, the predetermined first jump instruction is configured to set information for identifying the predetermined second program address based on the predetermined first program address. This reduces the data size of the information set in the predetermined first jump instruction to specify the jump destination program address, compared to a configuration in which information indicating the entire predetermined second program address is set. This reduces the data size of the predetermined first jump instruction and also reduces the data size of the predetermined program in which the predetermined first jump instruction is set.

Feature G6: The predetermined first jump instruction is an instruction that can set, as a jump destination, a program address existing in a predetermined program address range (a range from "the program address where the JRS instruction is set +1-16" to "the program address where the JRS instruction is set +1+15", or a range from "the program address where the JR instruction is set +2-128" to "the program address where the JR instruction is set +2+127") based on the predetermined first program address where the predetermined first jump instruction is set,
A gaming machine described in feature G5, characterized in that the predetermined third program address set as the jump destination of the predetermined second jump command is a program address that does not exist within the predetermined program address range based on the predetermined first program address at which the predetermined first jump command is set.

According to Feature G6, even if a jump instruction capable of jumping directly from a predetermined first program address to a predetermined third program address without passing through other program addresses is not set at the predetermined first program address, by setting a predetermined first jump instruction with a predetermined second program address as the jump destination at the predetermined first program address, it is possible to use the predetermined second jump instruction set at the predetermined second program address to jump from the predetermined first program address to a third predetermined program address that does not exist within the predetermined program address range based on the predetermined first program address. Therefore, if the data size of the predetermined first jump instruction that jumps from the predetermined first program address to the predetermined second program address is smaller than the data size of a jump instruction that can jump directly from the predetermined first program address to a predetermined third program address without passing through other program addresses, the data size of the jump instruction set at the predetermined first program address can be reduced.

Feature G7. A gaming machine described in any one of Features G1 to G6, characterized in that the predetermined second jump instruction contains information for identifying the predetermined third program address, which is the jump destination, based on the program address at which the predetermined second jump instruction is set (for a JRS instruction, difference information including a 1-bit code and 4-bit numerical information; for a JR instruction, difference information including a 1-bit code and 7-bit numerical information).

According to feature G7, the predetermined second jump instruction is configured to have information set therein for identifying the predetermined third program address based on the predetermined second program address. This reduces the data size of the information set in the predetermined second jump instruction to specify the jump destination program address, compared to a configuration in which information indicating the entire predetermined third program address is set therein. This reduces the data size of the predetermined second jump instruction and also reduces the data size of the predetermined program in which the predetermined second jump instruction is set.

Note that one or more of the features A1 to A19, B1 to B9, C1 to C13, D1 to D7, E1 to E6, F1 to F9, and G1 to G7 may be applied to the features G1 to G7. This allows for a synergistic effect to be achieved by combining these features.

The invention relating to the features of Feature Group D, Feature Group E, Feature Group F, and Feature Group G can solve the following problems.

Pachinko machines and slot machines are well-known gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls. The gaming balls stored in the storage section are guided to a gaming ball launcher and launched toward the gaming area in response to the player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Furthermore, when the lottery process is executed, the control means executes rotation start control, causing the reels to start spinning. If the stop button is operated while the reels are spinning, the control means executes rotation stop control, causing the reels to stop spinning. If the result after the reels have stopped spinning corresponds to a winning combination in the lottery process, a bonus corresponding to that winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, processing needs to be executed appropriately, and there is still room for improvement in this regard.

Below is the basic configuration of a gaming machine to which the above features can be applied.

Pachinko gaming machine: A gaming machine that has an operating means operated by the player, a gaming ball launching means that launches gaming balls based on the operation of the operating means, a ball passage that guides the launched gaming balls to a specified gaming area, and various gaming components arranged within the gaming area, and that awards a bonus to the player when the gaming ball passes through a specified passage section of each of the gaming components.

Slot machines and other reel-type gaming machines: A gaming machine that starts the rotation of a rotating body based on the operation of a start operation means, stops the rotation of the rotating body based on the operation of a stop operation means, and awards a bonus to the player based on the image that appears after the rotation has stopped.

10...Slot machine, 32L...Left reel, 32M...Middle reel, 32R...Right reel, 41...Start lever, 42-44...Stop buttons, 66...Dual-purpose display unit, 72...Main MPU, 73...Main ROM, 73f...Common data table, 73g...Common data table, 74...Main RAM, 74e...Award number counter, 74f...Index value counter, 74m...Stop order type counter, 74r...Continued game number counter, 74s...Total Acquisition number counter, 74u...AT continuation counter, 74v...highest level aggregation area, 74w...AT status signal counter, 74β...BB highest level aggregation area, 74δ...lights-out time counter, 86...abnormality monitoring circuit, 86a...watchdog timer, 92...performance side MPU, 101b...A register, 107...JRS execution circuit, CF...carry flag, FRm...mth frame, JF...jump flag, SF...highest level frame, ZF...zero flag.

Claims (1)

a predetermined storage area that takes either a first state or a second state depending on the content of an executed command;
a predetermined jump instruction executing means for jumping to a predetermined program address set as a jump destination for the predetermined jump instruction when the predetermined storage area is in the first state and the predetermined jump instruction is an instruction to be executed, and for proceeding to a program address set as a jump destination for the predetermined jump instruction when the predetermined storage area is in the second state and the predetermined jump instruction is an instruction to be executed, without jumping to the predetermined program address set as a jump destination for the predetermined jump instruction;
Equipped with
In the predetermined program in which the predetermined jump instruction is set, a predetermined instruction for executing a predetermined process is set as an instruction to be executed before the predetermined jump instruction,
the predetermined storage area is configured to be in the first state when the predetermined command is executed,
the predetermined program address is a program address at which an instruction to be executed prior to the predetermined jump instruction is set when the predetermined program is executed from the first program address in the predetermined program,
an instruction set between the predetermined program address and the program address where the predetermined jump instruction is set is repeatedly executed until the supply of operating power is stopped;
In the predetermined jump instruction, the predetermined program address is not set as information on a jump destination by the predetermined jump instruction, but information corresponding to an address difference between a program address at which the predetermined jump instruction is set and the predetermined program address is set,
The gaming machine is provided with a specific jump instruction execution means for making it possible to jump to a specific program address when a specific jump instruction is an instruction to be executed,
In the specific jump instruction, the specific program address is not set as information on the jump destination of the specific jump instruction, but information corresponding to the address difference between the program address at which the specific jump instruction is set and the specific program address is set,
A gaming machine characterized in that the information corresponding to the address difference set in the specified jump command has a smaller amount of information than the information of the address difference set in the specific jump command.