JP7741666B2 - Inrush current prevention circuit - Google Patents

Description

This disclosure relates to an inrush current prevention circuit that prevents inrush current from flowing into a primary-side capacitor on the power supply circuit side of a load circuit when the power supply circuit is started up or restored to power.

Patent documents 1 and 2, among others, disclose inrush current prevention circuits that prevent inrush current from flowing into the primary-side capacitor on the power supply circuit side of a load circuit when the power supply circuit is started.

First, we will explain the inrush current prevention circuit of the first prior art (Patent Document 1). Figure 1 shows the circuit configuration of the inrush current prevention circuit of the first prior art. Figure 2 shows example circuit characteristics of the inrush current prevention circuit of the first prior art. The inrush current prevention circuit 3 includes an integrating circuit resistor R1, a power supply voltage dividing resistor R2, an integrating circuit capacitor C3, a feedback circuit resistor R4, a feedback circuit capacitor C5, an oscillation prevention resistor R6, and a current limiting element FET. The load circuit 2 includes a primary-side capacitor CL. In Figure 2, the input voltage Vin from the power supply circuit 1 is DC 48 V, the equivalent resistance RL of the load circuit 2 is 48 Ω, the current IL of the equivalent resistance RL of the load circuit 2 is 1 A, the primary-side capacitor CL is 100 μF, the gate ON/OFF threshold voltage Vth of the current limiting element FET is 2 V, and the gate upper limit voltage VGSmax of the current limiting element FET is 12 V.

The current limiting element FET gradually increases its gate voltage during startup of the power supply circuit 1, preventing inrush current to the primary-side capacitor CL. The integrator capacitor C3, integrator resistor R1, and power supply voltage divider resistor R2 gradually increase the gate voltage of the current limiting element FET during startup of the power supply circuit 1. The integrator resistor R1 and power supply voltage divider resistor R2 set the upper limit of the gate voltage of the current limiting element FET lower than the input voltage from the power supply circuit 1. In the left column of Figure 2, the voltage across the power supply voltage divider resistor R2 reaches the gate ON/OFF threshold voltage Vth = 2V of the current limiting element FET 2 ms after startup of the power supply circuit 1 and reaches a stable state 200 ms after startup of the power supply circuit 1. During startup of the power supply circuit 1, the power consumption of the current limiting element FET is 26 W 10 ms after startup of the power supply circuit 1, and the accumulated heat of the current limiting element FET is 340 mJ 20 ms after startup of the power supply circuit 1. When the power supply circuit 1 starts up, these characteristics of the current limiting element FET are equivalent to an allowable loss of 6 W for the current limiting element FET.

Next, we will explain the inrush current prevention circuit of the second prior art (Patent Document 2). Figure 3 shows the circuit configuration of the inrush current prevention circuit of the second prior art. Figure 4 shows example circuit characteristics of the inrush current prevention circuit of the second prior art. The inrush current prevention circuit 4 includes an integrating circuit resistor R1, a clamping element D1, a power supply voltage dividing resistor R2, a switching element D2, an integrating circuit capacitor C3, a rapid discharge resistor R9, a current limiting element FET, and a transistor TR. The load circuit 2 includes a primary-side capacitor CL. In Figure 4, the input voltage Vin from the power supply circuit 1 is DC 48 V, the equivalent resistance RL of the load circuit 2 is 48 Ω, the current IL of the equivalent resistance RL of the load circuit 2 is 1 A, the primary-side capacitor CL is 100 μF, the gate ON/OFF threshold voltage Vth of the current limiting element FET is 2 V, and the gate upper limit voltage VGSmax of the current limiting element FET is 12 V.

When the power supply circuit 1 starts up, the gate voltage of the current limiting element FET gradually increases, preventing inrush current to the primary-side capacitor CL. The integrator circuit capacitor C3, integrator circuit resistor R1, and power supply voltage divider resistor R2 gradually increase the gate voltage of the current limiting element FET when the power supply circuit 1 starts up. The switch element D2 provides conduction between the integrator circuit capacitor C3 and the integrator circuit resistor R1. The integrator circuit resistor R1 and power supply voltage divider resistor R2 set the upper limit of the gate voltage of the current limiting element FET lower than the input voltage from the power supply circuit 1. In the left column of Figure 4, the voltage across the power supply voltage divider resistor R2 reaches the gate ON/OFF threshold voltage Vth = 2V of the current limiting element FET 2 ms after the power supply circuit 1 starts up, and reaches a stable state 200 ms after the power supply circuit 1 starts up. When the power supply circuit 1 starts up, the power consumption of the current limiting element FET is 26 W 10 ms after the power supply circuit 1 starts up, and the amount of heat accumulated in the current limiting element FET is 340 mJ 20 ms after the power supply circuit 1 starts up. When the power supply circuit 1 starts up, these characteristics of the current limiting element FET are converted into an allowable loss of the current limiting element FET, equivalent to 6 W.

Japanese Patent Application Laid-Open No. 2005-045957 Japanese Patent Application Publication No. 05-336737

First, we will explain the problem solved by the first prior art (Patent Document 1). During a momentary interruption or voltage drop in the power supply circuit 1, the integrator circuit capacitor C3, integrator circuit resistor R1, and power supply voltage divider resistor R2 gradually decrease the gate voltage of the current limiting element FET as the primary-side capacitor CL discharges. The time constant of the CR discharge circuit composed of the integrator circuit capacitor C3, integrator circuit resistor R1, and power supply voltage divider resistor R2 is several tens of times larger than the time constant of the discharge circuit for the primary-side capacitor CL. Furthermore, the voltage drop across the integrator circuit capacitor C3 is only R2/(R1 + R2) times the voltage drop across the primary-side capacitor CL. Therefore, in the first row of the middle column of Figure 2, the gate voltage of the current limiting element FET remains at 11 V even 10 ms after a momentary interruption or deep voltage drop in the power supply circuit 1, and does not decrease to the gate ON/OFF threshold voltage Vth = 2 V. In the second row of the middle column of Figure 2, the terminal voltage of the primary-side capacitor CL remains at only 5 V as a residual voltage 10 ms after the power supply circuit 1 experiences a momentary interruption and a deep momentary sag.

Here, the power supply circuit 1 may transition from a momentary interruption or deep voltage drop to a power recovery state before the gate voltage of the current limiting element FET drops to the gate ON/OFF threshold voltage Vth = 2V. In this case, in the first stage in the right column of Figure 2, the drain current of the current limiting element FET (which remains in the barely ON state) reaches a re-inrush current of 160A immediately after power is restored to the power supply circuit 1. In the second stage in the right column of Figure 2, the power consumption of the current limiting element FET reaches a maximum of 2.5kW within 20μs after power is restored to the power supply circuit 1. Furthermore, in the third stage in the right column of Figure 2, the accumulated heat of the current limiting element FET reaches 39mJ 20μs after power is restored to the power supply circuit 1. Therefore, when power is rapidly restored to the power supply circuit 1, these characteristics of the current limiting element FET are equivalent to an allowable loss of 24 W in terms of the current limiting element FET, which is four times the allowable loss of the current limiting element FET when the power supply circuit 1 is started up. This requires a larger model of current limiting element FET.

Next, we will explain the problem solved by the second prior art (Patent Document 2). During a momentary interruption or drop in the power supply circuit 1, the integrator circuit capacitor C3 and the rapid discharge resistor R9 gradually decrease the gate voltage of the current limiting element FET as the primary-side capacitor CL discharges. When the voltage across the integrator circuit capacitor C3 becomes higher than the voltage across the power supply voltage divider resistor R2, the switch element D2 turns on the transistor TR, thereby establishing conduction between the integrator circuit capacitor C3 and the rapid discharge resistor R9. The time constant of the CR discharge circuit composed of the integrator circuit capacitor C3 and the rapid discharge resistor R9 is approximately equal to the time constant of the discharge circuit for the primary-side capacitor CL. The voltage drop across the integrator circuit capacitor C3 is only R2/(R1 + R2) times the voltage drop across the primary-side capacitor CL. Therefore, in the first stage in the middle column of Figure 4, the gate voltage of the current limiting element FET drops to the gate ON/OFF threshold voltage Vth = 2V 8ms after the power supply circuit 1 experiences a momentary interruption and a deep momentary drop. Then, in the second stage in the middle column of Figure 4, the voltage across the primary side capacitor CL remains at a residual voltage of only 8V 8ms after the power supply circuit 1 experiences a momentary interruption and a deep momentary drop.

Here, the power supply circuit 1 may transition from a momentary interruption or deep voltage drop to a power recovery state before the gate voltage of the current limiting element FET drops to the gate ON/OFF threshold voltage Vth = 2V. In this case, in the first stage in the right column of Figure 4, the drain current of the current limiting element FET (which remains in the barely ON state) reaches 130A as a re-inrush current immediately after power is restored to the power supply circuit 1. In the second stage in the right column of Figure 4, the power consumption of the current limiting element FET reaches a maximum of 1.8kW within 20μs after power is restored to the power supply circuit 1. Furthermore, in the third stage in the right column of Figure 4, the accumulated heat of the current limiting element FET reaches 27mJ 20μs after power is restored to the power supply circuit 1. Therefore, when power is rapidly restored to the power supply circuit 1, these characteristics of the current limiting element FET are equivalent to 18 W in terms of the allowable loss of the current limiting element FET, which is three times the allowable loss of the current limiting element FET when the power supply circuit 1 is started up. This requires a larger model of current limiting element FET.

To solve the above problem, the present disclosure aims to reduce the power applied to the current limiting element to the same level as at startup, even when power is rapidly restored after a momentary power outage or deep voltage drop in the power supply circuit, while maintaining the same level of inrush current prevention functionality at startup as in the prior art.

To solve the above problem, the integrating circuit capacitor and the rapid discharge capacitor are connected in series with each other and in parallel with the primary side capacitor. Then, during a momentary power interruption or voltage drop in the power circuit, the integrating circuit capacitor and the rapid discharge capacitor discharge in conjunction with the discharge of the primary side capacitor. Here, the discharge circuit consisting of the integrating circuit capacitor and the rapid discharge capacitor is not a CR discharge circuit, and discharges without a CR time constant, integrated with the discharge of the primary side capacitor.

Specifically, the present disclosure provides an inrush current prevention circuit that prevents inrush current from flowing to a primary-side capacitor on the power supply circuit side of a load circuit when the power supply circuit is started up and when power is restored. The inrush current prevention circuit includes: a current limiting element that is disposed on a power supply line and whose control voltage gradually increases when the power supply circuit is started up and when power is restored, thereby preventing inrush current from flowing to the primary-side capacitor; an integrating circuit capacitor and integrating circuit resistor that are connected in parallel with the power supply circuit and gradually increase the control voltage of the current limiting element when the power supply circuit is started up and when power is restored; and a rapid discharge capacitor that is connected in series with the integrating circuit capacitor and in parallel with the integrating circuit resistor and that discharges in conjunction with the discharge of the primary-side capacitor when the power supply circuit is momentarily interrupted or dips.

With this configuration, when the power supply circuit experiences a momentary interruption or deep drop, the control voltage of the current limiting element can be rapidly reduced to below the control ON/OFF threshold voltage Vth, and the inrush current prevention circuit can be stopped at a point when the residual voltage of the primary-side capacitor is higher. Therefore, even when the power supply circuit subsequently rapidly recovers, the power applied to the current limiting element can be reduced to the same level as at startup or lower.

The present disclosure also provides an inrush current prevention circuit in which, during a momentary interruption or deep momentary drop in the power supply circuit, the amount of voltage drop in the integrating circuit capacitor becomes larger than the amount of voltage drop in the rapid discharge capacitor, and the capacitance of the integrating circuit capacitor is set smaller than the capacitance of the rapid discharge capacitor so that the control voltage of the current limiting element accelerates the timing at which the current limiting element switches from an on state to an off state.

With this configuration, when the power supply circuit experiences a momentary interruption or deep momentary sag, the control voltage of the current limiting element can be rapidly reduced below the control ON/OFF threshold voltage Vth in a short period of time, allowing the inrush current prevention circuit to be shut down at a point when the residual voltage of the primary-side capacitor is higher. Even if the power supply circuit is restored just before the inrush current prevention circuit is shut down, the maximum value of the re-inrush current to the current limiting element can be kept low.

The present disclosure also provides an inrush current prevention circuit that further includes a switch element connected between the integrating circuit capacitor and the rapid discharge capacitor, which disconnects the control terminal of the current limiting element and the integrating circuit capacitor and the rapid discharge capacitor when the power supply circuit is started up or restored to power, and which connects the integrating circuit capacitor and the rapid discharge capacitor when the power supply circuit is momentarily interrupted or dips.

With this configuration, by isolating the integrating circuit capacitor and the rapid discharge capacitor when the power supply circuit is started up or restored to power, it is possible to prevent inrush current into the series circuit of these capacitors. At the same time, the control voltage of the current limiting element is not rapidly increased, thereby maintaining the inrush current prevention function of the current limiting element.

The present disclosure also provides an inrush current prevention circuit further comprising a power supply voltage dividing resistor connected in series with the rapid discharge capacitor without the switch element and connected in parallel with the integrating circuit capacitor via the switch element, and a bleeder resistor connected in parallel with the rapid discharge capacitor without the switch element and connected in parallel with the integrating circuit resistor via the switch element, wherein the rapid discharge capacitor, the power supply voltage dividing resistor, and the bleeder resistor constitute a CR charging circuit for the rapid discharge capacitor when the power supply circuit is started up and when power is restored.

This configuration allows the rapid discharge capacitor to be charged when the power supply circuit is started up and when power is restored, and prepares for the rapid discharge capacitor to discharge in the event of a momentary power interruption or voltage drop in the power supply circuit. Furthermore, the CR charging circuit for the rapid discharge capacitor and the CR charging circuit for the integrator circuit capacitor can be designed independently when the switch element is in the off state.

The present disclosure also provides an inrush current prevention circuit in which, upon startup and power recovery of the power supply circuit, CR charging of the rapid discharge capacitor is completed and the terminal voltage of the integrator circuit capacitor becomes equal to the input voltage from the power supply circuit * the power supply voltage dividing resistance / (the power supply voltage dividing resistance + the bleeder resistance), and the switch element establishes conduction between the integrator circuit capacitor and the rapid discharge capacitor.

With this configuration, the upper limit of the control voltage of the current limiting element can be set lower than the input voltage from the power supply circuit when the power supply circuit is started up and when power is restored.

The present disclosure also provides an inrush current prevention circuit, characterized in that, when the power supply circuit is started up and when power is restored, the time constant of the CR charging circuit consisting of the rapid discharge capacitor, the power supply voltage dividing resistor, and the bleeder resistor is set to be smaller than the time constant of the CR charging circuit consisting of the integrating circuit capacitor and the integrating circuit resistor.

This configuration ensures that the control voltage of the current limiting element does not become higher than the set upper limit voltage when the power supply circuit is started up or restored to power.

In this way, the present disclosure can reduce the power applied to the current limiting element to the same level as at startup, even when power is rapidly restored after a momentary power outage or deep voltage drop in the power circuit, while maintaining the same level of inrush current prevention functionality at startup as in the prior art.

FIG. 1 is a diagram showing a circuit configuration of a first prior art inrush current prevention circuit. FIG. 10 is a diagram illustrating an example of circuit characteristics of a first conventional inrush current prevention circuit. FIG. 10 is a diagram showing a circuit configuration of a second prior art inrush current prevention circuit. FIG. 10 is a diagram illustrating an example of circuit characteristics of a second conventional inrush current prevention circuit. FIG. 1 is a diagram illustrating a circuit configuration of an inrush current prevention circuit according to the present disclosure. 1A and 1B are diagrams illustrating the inrush current prevention circuit of the present disclosure at startup and power recovery. 1A and 1B are diagrams illustrating the inrush current prevention circuit of the present disclosure during an instantaneous interruption and a deep instantaneous sag. 10A and 10B are diagrams illustrating an example of circuit characteristics of an inrush current prevention circuit according to the present disclosure.

Embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments described below are examples of implementations of the present disclosure, and the present disclosure is not limited to the following embodiments.

(Circuit configuration of the inrush current prevention circuit of the present disclosure)
First, the circuit configuration of the inrush current prevention circuit of the present disclosure will be described. The circuit configuration of the inrush current prevention circuit of the present disclosure is shown in Fig. 5. The inrush current prevention circuit 5 includes an integrating circuit resistor R1, a power supply voltage dividing resistor R2, an integrating circuit capacitor C3, a feedback circuit resistor R4, a feedback circuit capacitor C5, an oscillation prevention resistor R6, a bleeder resistor R7, a rapid discharge capacitor C8, a current limiting element FET, and a switch element D. The load circuit 2 includes a primary-side capacitor CL.

The inrush current prevention circuit 5 prevents inrush current from flowing to the primary-side capacitor CL on the power supply circuit 1 side of the load circuit 2 when the power supply circuit 1 is started up or restored to power. In other words, the current limiting element FET is located on the power supply line, and when the power supply circuit 1 is started up or restored to power, the control voltage gradually increases, preventing inrush current from flowing to the primary-side capacitor CL. The integrating circuit capacitor C3 and integrating circuit resistor R1 are connected in parallel with the power supply circuit 1, and when the power supply circuit 1 is started up or restored to power, the control voltage of the current limiting element FET gradually increases.

In this embodiment, the current limiting element FET is a MOSFET, but as a modification, it may be a bipolar transistor or the like. In this embodiment, the current limiting element FET is placed on the power supply line from -IN to -OUT, but as a modification, the current limiting element FET may be placed on the power supply line from +IN to +OUT. If the power supply circuit 1 outputs AC rather than DC, a rectifying element (not shown in FIG. 5) can be inserted before the input terminals (+IN terminal and -IN terminal) of the inrush current prevention circuit 5.

Feedback circuit resistor R4 and feedback circuit capacitor C5 stabilize the charging current of primary-side capacitor CL when power supply circuit 1 is started up or restored to power. Oscillation prevention resistor R6 prevents oscillation of the current limiting element FET when power supply circuit 1 is started up or restored to power.

The rapid discharge capacitor C8 is connected in series with the integrator circuit capacitor C3 and in parallel with the integrator circuit resistor R1. When the power supply circuit 1 experiences a momentary interruption or voltage drop, it discharges in conjunction with the discharge of the primary side capacitor CL and the discharge of the integrator circuit capacitor C3.

Here, the discharge circuit consisting of the integrating circuit capacitor C3 and the rapid discharge capacitor C8 is not a CR discharge circuit further comprising an integrating circuit resistor R1, a power supply voltage dividing resistor R2, and a bleeder resistor R7, and can perform discharge integrally with the discharge of the primary side capacitor CL without a CR time constant.

As a result, when the power supply circuit 1 experiences a momentary interruption or deep momentary drop, the gate voltage of the current limiting element FET can be rapidly reduced to below the ON/OFF threshold voltage Vth, and the inrush current prevention circuit 5 can be stopped at a point when the residual voltage of the primary-side capacitor CL is higher. Furthermore, even when the power supply circuit 1 subsequently rapidly recovers, the power applied to the current limiting element FET can be reduced to the same level as at startup or lower.

During a momentary interruption or deep voltage drop in the power supply circuit 1, the voltage drop across the integrator circuit capacitor C3 is greater than the voltage drop across the rapid discharge capacitor C8, and the capacitance of the integrator circuit capacitor C3 is set smaller than the capacitance of the rapid discharge capacitor C8 so that the gate voltage of the current limiting element FET accelerates the timing at which the current limiting element FET switches from the ON state to the OFF state.

If the capacitance of integrator circuit capacitor C3 is set larger than the capacitance of rapid discharge capacitor C8, then during a momentary interruption or deep voltage drop in power supply circuit 1, the amount of voltage drop across integrator circuit capacitor C3 will be smaller than the amount of voltage drop across rapid discharge capacitor C8, and the time it takes for the gate voltage of the current limiting element FET to switch the current limiting element FET from the ON state to the OFF state will be longer.

On the other hand, with this disclosure, when the power supply circuit 1 experiences a momentary interruption or deep momentary drop, the gate voltage of the current limiting element FET can be rapidly reduced to below the ON/OFF threshold voltage Vth in a short period of time, and the inrush current prevention circuit 5 can be stopped at a point when the residual voltage of the primary-side capacitor CL is higher. Even if the power supply circuit 1 is restored just before the inrush current prevention circuit 5 is stopped, the maximum value of the re-inrush current to the current limiting element FET can be kept low.

Switch element D is connected between integrator circuit capacitor C3 and rapid discharge capacitor C8, and when power supply circuit 1 starts up or is restored, it disconnects the gate terminal of the current limiting element FET and integrator circuit capacitor C3 from rapid discharge capacitor C8, and when power supply circuit 1 experiences a momentary interruption or momentary drop, it connects integrator circuit capacitor C3 to rapid discharge capacitor C8.

If switch element D conducts current between the gate terminal of the current limiting element FET and between the integrating circuit capacitor C3 and the rapid discharge capacitor C8 when power supply circuit 1 is started up or restored, it will not be possible to prevent inrush currents in the integrating circuit capacitor C3 and the rapid discharge capacitor C8, and at the same time, the gate voltage of the current limiting element FET will rise rapidly, making it impossible to maintain the inrush current prevention function of the current limiting element FET.

On the other hand, in the present disclosure, by isolating the integrator circuit capacitor C3 and the rapid discharge capacitor C8 when the power supply circuit 1 is started up or restored to power, it is possible to prevent inrush current into the series circuit of these capacitors, and at the same time, the gate voltage of the current limiting element FET is not rapidly increased, thereby maintaining the inrush current prevention function of the current limiting element FET. Furthermore, as described above, during a momentary interruption or deep momentary sag in the power supply circuit 1, the gate voltage of the current limiting element FET can be rapidly reduced to below the ON/OFF threshold voltage Vth, allowing the inrush current prevention circuit 5 to be stopped at a point when the residual voltage of the primary-side capacitor CL is higher.

Power supply voltage dividing resistor R2 is connected in series with rapid discharge capacitor C8 without switching element D, and is connected in parallel with integrating circuit capacitor C3 via switching element D. Bleeder resistor R7 is connected in parallel with rapid discharge capacitor C8 without switching element D, and is connected in parallel with integrating circuit resistor R1 via switching element D.

Here, when the power supply circuit 1 is started up or restored to power, the rapid discharge capacitor C8, the power supply voltage dividing resistor R2, and the bleeder resistor R7 form a CR charging circuit for the rapid discharge capacitor C8. Meanwhile, when the power supply circuit 1 is started up or restored to power, the integrating circuit capacitor C3 and the integrating circuit resistor R1 form a CR charging circuit for the integrating circuit capacitor C3. And when the power supply circuit 1 is started up or restored to power, the CR charging circuit for the rapid discharge capacitor C8 and the CR charging circuit for the integrating circuit capacitor C3 can operate independently when the switch element D is in the OFF state.

As a result, rapid discharge capacitor C8 can be charged when power supply circuit 1 is started up or restored, and rapid discharge capacitor C8 can be prepared for discharge in the event of a momentary power outage or voltage drop in power supply circuit 1. Furthermore, the CR charging circuit for rapid discharge capacitor C8 and the CR charging circuit for integrator circuit capacitor C3 can be designed independently when switch element D is in the cut-off state.

When power supply circuit 1 is started up or restored, CR charging of rapid discharge capacitor C8 is completed and the voltage across integrator circuit capacitor C3 becomes equal to input voltage Vin from power supply circuit 1 * power supply voltage divider resistor R2 / (power supply voltage divider resistor R2 + bleeder resistor R7), and switch element D establishes conduction between integrator circuit capacitor C3 and rapid discharge capacitor C8. When bleeder resistor R7 and integrator circuit resistor R1 are connected in parallel after switch element D becomes conductive, the voltage across integrator circuit capacitor C3 eventually rises to input voltage Vin from power supply circuit 1 * power supply voltage divider resistor R2 / (power supply voltage divider resistor R2 + bleeder resistor R7 // integrator circuit resistor R1) and stabilizes (here, "//" indicates a parallel connection).

As a result, when power supply circuit 1 is started up and power is restored, the upper limit of the gate voltage of the current limiting element FET (= input voltage Vin from power supply circuit 1 * power supply voltage dividing resistor R2 / (power supply voltage dividing resistor R2 + bleeder resistor R7 // integrator circuit resistor R1)) can be set lower than the input voltage from power supply circuit 1.

When power supply circuit 1 is started up or restored to power, the time constant of the CR charging circuit consisting of rapid discharge capacitor C8, power supply voltage dividing resistor R2, and bleeder resistor R7 is set to be smaller than the time constant of the CR charging circuit consisting of integrating circuit capacitor C3 and integrating circuit resistor R1.

As a result, when the power supply circuit 1 is started up or restored to power, the gate voltage of the current limiting element FET can be prevented from becoming higher than the set upper limit voltage (= input voltage Vin from the power supply circuit 1 * power supply voltage dividing resistor R2 / (power supply voltage dividing resistor R2 + bleeder resistor R7 // integrator circuit resistor R1)).

(When the inrush current prevention circuit of the present disclosure is started up and when power is restored)
Taking into account the circuit configuration of the inrush current prevention circuit of the present disclosure, Fig. 6 shows the start-up and power restoration from a stopped state of the inrush current prevention circuit of the present disclosure. The upper part of Fig. 6 shows the initial start-up and power restoration from a stopped state of the inrush current prevention circuit 5. The lower part of Fig. 6 shows the final start-up and power restoration from a stopped state of the inrush current prevention circuit 5.

First, we will explain the initial startup and power recovery periods from a stopped state of the inrush current prevention circuit 5. The voltage VR2 across the power supply voltage divider resistor R2 is equal to the input voltage Vin from the power supply circuit 1, and the voltage VGS across the integrator circuit capacitor C3 (= the gate voltage of the current limiting element FET) is 0 or below the ON/OFF threshold voltage Vth. The current limiting element FET is set to the OFF state, and the switch element D cuts off communication between the integrator circuit capacitor C3 and the rapid discharge capacitor C8. The voltage across the primary side capacitor CL is 0 or a residual voltage Vres.

The CR charging circuit, consisting of the primary-side capacitor CL and load circuit 2, charges the primary-side capacitor CL with a time constant of CL * Rin. Here, Rin is the sum of the internal resistance of the power supply circuit 1 and the Ron of the current limiting element FET. The CR charging circuit, consisting of the rapid discharge capacitor C8, power supply voltage dividing resistor R2, and bleeder resistor R7, charges the rapid discharge capacitor C8 with a time constant of C8 * (R2//R7). The CR charging circuit, consisting of the integrating circuit capacitor C3 and integrating circuit resistor R1, charges the integrating circuit capacitor C3 with a time constant of C3 * R1.

Next, we will explain the final stages of startup and power recovery from a state in which the inrush current prevention circuit 5 is stopped. Initially, the voltage VR2 across the power supply voltage divider resistor R2 becomes equal to the input voltage Vin from the power supply circuit 1 * power supply voltage divider resistor R2 / (power supply voltage divider resistor R2 + bleeder resistor R7). After that, the voltage VGS across the integrator circuit capacitor C3 (= gate voltage of the current limiting element FET) becomes equal to the voltage VR2 across the power supply voltage divider resistor R2. The current limiting element FET is switched ON, and the switch element D conducts current between the integrator circuit capacitor C3 and the rapid discharge capacitor C8. The voltage across the primary-side capacitor CL becomes equal to the input voltage Vin from the power supply circuit 1.

(Inrush current prevention circuit of the present disclosure during momentary interruption and deep momentary sag)
Taking into account the circuit configuration of the inrush current prevention circuit of the present disclosure, Fig. 7 shows the time of an instantaneous interruption and a deep instantaneous sag when the inrush current prevention circuit of the present disclosure is in a steady state. The upper part of Fig. 7 shows the beginning of an instantaneous interruption and an early part of a deep instantaneous sag when the inrush current prevention circuit 5 is in a steady state. The lower part of Fig. 7 shows the end of an instantaneous interruption and an end of a deep instantaneous sag when the inrush current prevention circuit 5 is in a steady state.

First, we will explain the initial stage of a momentary interruption and the initial stage of a deep momentary sag when the inrush current prevention circuit 5 is in a steady state. The voltage VR2 across the power supply voltage divider resistor R2 remains equal to the steady-state input voltage Vin from the power supply circuit 1 * power supply voltage divider resistor R2 / (power supply voltage divider resistor R2 + bleeder resistor R7 // integrator circuit resistor R1), and the voltage VGS across the integrator circuit capacitor C3 (= gate voltage of the current limiting element FET) remains equal to the steady-state voltage VR2 across the power supply voltage divider resistor R2. The current limiting element FET remains ON, and the switch element D conducts current between the integrator circuit capacitor C3 and the rapid discharge capacitor C8. The voltage across the primary-side capacitor CL is equal to the steady-state input voltage Vin from the power supply circuit 1.

The CR discharge circuit, consisting of the primary-side capacitor CL and the equivalent resistance RL of the load circuit 2, discharges the primary-side capacitor CL with a time constant CL * RL. The discharge circuit, consisting of the integrating circuit capacitor C3 and the rapid discharge capacitor C8, discharges the integrating circuit capacitor C3 and the rapid discharge capacitor C8 in conjunction with the discharge of the primary-side capacitor CL, without a CR time constant. The voltage drop across the integrating circuit capacitor C3 (= C8/(C3 + C8) times the voltage drop across the primary-side capacitor CL, where C8 > C3) is greater than the voltage drop across the rapid discharge capacitor C8 (= C3/(C3 + C8) times the voltage drop across the primary-side capacitor CL, where C3 < C8).

Next, we will explain the end of a momentary interruption and a deep momentary sag from a steady state of the inrush current prevention circuit 5. First, the terminal voltage VGS of the integrator capacitor C3 (= the gate voltage of the current limiting element FET) becomes equal to the ON/OFF threshold voltage Vth of the current limiting element FET, and the terminal voltage VR2 of the power supply voltage dividing resistor R2 becomes equal to the terminal voltage VGS of the integrator capacitor C3. The current limiting element FET is switched to the OFF state, and the switch element D conducts current between the integrator capacitor C3 and the rapid discharge capacitor C8. A sufficient residual voltage Vres remains in the terminal voltage of the primary-side capacitor CL. Thereafter, the CR discharge circuit consisting of the integrator circuit capacitor C3 and the power supply voltage divider resistor R2 additionally discharges the integrator circuit capacitor C3 with a time constant of C3 * R2, and the CR discharge circuit consisting of the rapid discharge capacitor C8 and the bleeder resistor R7 additionally discharges the rapid discharge capacitor C8 with a time constant of C8 * R7.

(Example of circuit characteristics of the inrush current prevention circuit of the present disclosure)
Taking into account the circuit configuration of the inrush current prevention circuit of the present disclosure, an example of circuit characteristics of the inrush current prevention circuit of the present disclosure is shown in Fig. 8. In Fig. 8, the input voltage Vin from the power supply circuit 1 is DC 48 V, the equivalent resistance RL of the load circuit 2 is 48 Ω, the current IL of the equivalent resistance RL of the load circuit 2 is 1 A, the primary-side capacitor CL is 100 µF, the gate ON/OFF threshold voltage Vth of the current limiting element FET is 2 V, and the gate upper limit voltage VGSmax of the current limiting element FET is 12 V. The circuit constants of the inrush current prevention circuit 5 are set as follows:

The integrator circuit resistor R1 must pass a current that is sufficiently larger than the gate leakage current Igss of the current limiting element FET when the power supply circuit 1 is stable: (Vin - VGS)/R1 >> Igss. The power supply voltage divider resistor R2 must pass a current that is sufficiently larger than the current flowing through the integrator circuit resistor R1 when the power supply circuit 1 is stable: VGS/R2 >> (Vin - VGS)/R1. The integrator circuit capacitor C3 must be set to the startup delay period of the current limiting element FET, where T3 is the longer of the chattering period when the power supply circuit 1 starts up or the stabilization period of the input voltage Vin from the power supply circuit 1: C3 * R1 * Vth/Vin = T3.

After setting the integrator circuit resistor R1, power supply voltage dividing resistor R2, and integrator circuit capacitor C3, the circuit constants of the inrush current prevention circuit 5 must be set to satisfy the following conditions, as explained in the circuit configuration of the inrush current prevention circuit disclosed herein: C3 < C8, Vin * R2 / (R2 + R7 // R1) = VGS, Vth < VGS < VGSmax, C8 * (R2 // R7) < C3 * R1.

In the left column of Figure 8, the voltage across power supply voltage divider resistor R2 is equal to the 48V input voltage from power supply circuit 1 immediately after power supply circuit 1 is started, and reaches a stable state 100 ms after power supply circuit 1 is started. The gate voltage of the current limiting element FET reaches the ON/OFF threshold voltage Vth = 2V of the current limiting element FET 2 ms after power supply circuit 1 is started, and reaches a stable state 100 ms after power supply circuit 1 is started. When power supply circuit 1 is started, the power consumption of the current limiting element FET is 26 W 10 ms after power supply circuit 1 is started, and the accumulated heat of the current limiting element FET is 340 mJ 20 ms after power supply circuit 1 is started. When power supply circuit 1 is started, these characteristics of the current limiting element FET are equivalent to an allowable loss of 6 W.

In the first stage in the middle column of Figure 8, the gate voltage of the current limiting element FET drops to the ON/OFF threshold voltage Vth = 2V 2ms after the power supply circuit 1 experiences a momentary interruption and a deep momentary drop. In the second stage in the middle column of Figure 8, the terminal voltage of the primary-side capacitor CL remains at a sufficiently high residual voltage of 32V 2ms after the power supply circuit 1 experiences a momentary interruption and a deep momentary drop. Assume that the power supply circuit 1 returns to its power-restored state with the current limiting element FET in the barely ON state.

In the first row in the right column of Figure 8, the drain current of the current limiter FET is limited to 30 A as a re-inrush current immediately after power is restored to the power supply circuit 1. In the second row in the right column of Figure 8, the power consumption of the current limiter FET is limited to 0.3 kW at maximum within 20 μs after power is restored to the power supply circuit 1. In the third row in the right column of Figure 8, the amount of accumulated heat in the current limiter FET is limited to 4.3 mJ within 20 μs after power is restored to the power supply circuit 1. Therefore, when power is rapidly restored to the power supply circuit 1, these characteristics of the current limiter FET are converted into an allowable loss of 3 W, which is smaller than the allowable loss of the current limiter FET when the power supply circuit 1 is started up. This means that a small current limiter FET may be used, taking into account only the allowable loss of the current limiter FET when the power supply circuit 1 is started up.

The inrush current prevention circuit disclosed herein can ensure that the power applied to the current limiting element during a momentary interruption or deep sag is equal to or less than the power applied to the current limiting element during startup when AC or DC power is supplied to the internal circuitry of a device that is connected to an AC or DC power source and operates (the device's use is not limited to any specific application).

1: Power supply circuit 2: Load circuit 3, 4, 5: Inrush current prevention circuit R1: Integration circuit resistor D1: Clamp element R2: Power supply voltage dividing resistor D2: Switch element C3: Integration circuit capacitor R4: Feedback circuit resistor C5: Feedback circuit capacitor R6: Oscillation prevention resistor R7: Bleeder resistor C8: Rapid discharge capacitor R9: Rapid discharge resistor FET: Current limiting element TR: Transistor D: Switch element CL: Primary side capacitor

Claims (5)

An inrush current prevention circuit that prevents an inrush current from flowing into a primary-side capacitor on a power supply circuit side of a load circuit when the power supply circuit is started up or restored to power,
a current limiting element disposed on a power supply line, the control voltage of which gradually increases when the power supply circuit is started up and when power is restored, thereby preventing an inrush current from flowing into the primary-side capacitor;
an integrating circuit capacitor and an integrating circuit resistor connected in parallel with the power supply circuit, which gradually increase the control voltage of the current limiting element when the power supply circuit is started up and when power is restored;
a rapid discharge capacitor connected in series with the integrating circuit capacitor and in parallel with the integrating circuit resistor, which discharges together with the integrating circuit capacitor in response to the discharge of the primary side capacitor when the power supply circuit is momentarily interrupted or drops ,
In an inrush current prevention circuit, the capacitance of the integrating circuit capacitor is set smaller than the capacitance of the rapid discharge capacitor so that, during an instantaneous interruption or deep instantaneous drop of the power supply circuit, the voltage drop of the integrating circuit capacitor becomes larger than the voltage drop of the rapid discharge capacitor, and the control voltage of the current limiting element accelerates the timing at which the current limiting element switches from an on state to an off state . 2. The inrush current prevention circuit according to claim 1, further comprising a switch element connected between the integrating circuit capacitor and the rapid discharge capacitor, which disconnects the control terminal of the current limiting element and the integrating circuit capacitor from the rapid discharge capacitor when the power supply circuit is started up or restored to power, and which connects the integrating circuit capacitor to the rapid discharge capacitor when the power supply circuit is momentarily interrupted or dips. a power supply voltage dividing resistor connected in series with the rapid discharge capacitor without passing through the switch element and connected in parallel with the integrating circuit capacitor via the switch element;
a bleeder resistor connected in parallel to the rapid discharge capacitor without the switch element and connected in parallel to the integrating circuit resistor via the switch element;
3. The inrush current prevention circuit according to claim 2 , wherein the rapid discharge capacitor, the power supply voltage dividing resistor, and the bleeder resistor form a CR charging circuit for the rapid discharge capacitor when the power supply circuit is started up and when power is restored. 4. The inrush current prevention circuit according to claim 3, wherein, when the power supply circuit is started up or when power is restored, CR charging of the rapid discharge capacitor is completed and the voltage across the integrating circuit capacitor becomes equal to (input voltage from the power supply circuit*the power supply voltage dividing resistance)/(the power supply voltage dividing resistance+the bleeder resistance), the switch element establishes conduction between the integrating circuit capacitor and the rapid discharge capacitor. 5. The inrush current prevention circuit according to claim 3, wherein, at the time of startup and power recovery of the power supply circuit, a time constant of a CR charging circuit constituted by the rapid discharge capacitor, the power supply voltage dividing resistor, and the bleeder resistor is set to be smaller than a time constant of a CR charging circuit constituted by the integrating circuit capacitor and the integrating circuit resistor.