JP7742763B2 - Design condition calculation system and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a design condition calculation system that supports the design of semiconductor devices, and in particular to technology that supports the design of manufacturing parameters for power semiconductor devices.

Power semiconductor devices require high breakdown voltage, low on-resistance, and low switching loss, but the current mainstream silicon (Si) power devices are approaching their theoretical performance limits. Silicon carbide (SiC) has a breakdown field strength approximately one order of magnitude greater than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce device resistance by more than three orders of magnitude. Furthermore, because its band gap is approximately three times larger than that of Si, high-temperature operation is also possible. As such, SiC semiconductor devices are expected to surpass the performance of Si semiconductor devices, and development of SiC power semiconductor devices is underway.

The following prior art exists as background art in this technical field. Patent Document 1 (JP 2020-184123 A) describes a circuit design device that includes an operation unit and a storage unit for inputting the circuit configuration of a circuit to be designed, the names of circuit characteristic items of the circuit to be designed, and the names of elements that make up the circuit to be designed; a simulation unit that generates element values of each circuit element and corresponding characteristic values of each circuit characteristic item by simulating the circuit to be designed while changing the element values of each circuit element; and a design processing unit that performs deep learning using the element values of the circuit elements and the characteristic values of the corresponding circuit characteristic items in a learning mode, and that generates at least one of element values corresponding to the characteristic values and characteristic values corresponding to the element values through regression analysis in a design mode.

Patent document 2 (JP 2012-150574 A) describes a simulation collaboration method that includes a semiconductor device equivalent circuit model setting process for obtaining device characteristics from the output of a semiconductor device simulation, at least the device characteristics required for a semiconductor device equivalent circuit model used in circuit simulation, in order to perform simulation collaboration; and an information feedback process that includes a knowledge database for evaluating the output of the circuit simulation and, if there is a problem with product performance, estimating information for optimizing at least the semiconductor device structure from the output of the circuit simulation and feeding this information back to the semiconductor device simulation.

Japanese Patent Application Laid-Open No. 2020-184123 JP 2012-150574 A

To control large amounts of power, power semiconductor devices must satisfy a wide range of performance requirements, including on-resistance, short-circuit time, threshold voltage, breakdown voltage, switching loss, and dielectric film reliability. Many of these parameters are in a trade-off relationship, and a design that is appropriate for the application in which they will be used must be sought within that trade-off. Furthermore, in recent years, device structures, processes, and circuit structures have become more complex, resulting in a large number of parameters being involved in the design. Therefore, it is necessary to optimize the design, materials, and fabrication conditions of the circuit in which the device is installed, taking into account the characteristics of the semiconductor device and the application in which it is installed, such as on-resistance, short-circuit time, threshold voltage, breakdown voltage, switching loss, and dielectric film reliability, by comprehensively considering the device design, materials, and fabrication conditions, as well as the system. Establishing such an optimization system requires the creation of highly accurate regression models of devices and circuits through simulation.

However, the power semiconductor devices targeted by this invention cannot predict their characteristics with high accuracy using existing simulations alone. This is because, while a large amount of data has been accumulated for Si, making it possible to predict physical properties by manual calculation, SiC has a short history, making it difficult to predict physical properties such as scattering cross section and mobility. Furthermore, because the simulations used in regression models calculate the relationship between unobservable parameters, it is necessary to construct a model that can be calculated using observable data.

The present invention aims to quickly and inexpensively provide suitable design values for power devices that meet the numerous characteristics required for specific applications, even for SiC semiconductor devices.

A representative example of the invention disclosed in this application is as follows: That is, a design condition calculation system comprising an arithmetic unit that executes predetermined processing, an input unit to which data is input, and a storage device accessible by the arithmetic unit, wherein the input unit receives input of a first parameter representing at least one of the material, manufacturing process, and design of a semiconductor device, a second parameter representing at least one of the material, manufacturing process, and design of a circuit incorporating the semiconductor device, and a third parameter representing at least one characteristic of the semiconductor device and the circuit incorporating the semiconductor device, and the design condition calculation system comprises an optimization calculation unit in which the arithmetic unit calculates the first parameter and the second parameter using a model constructed by a model construction unit so as to satisfy predetermined conditions, and the models constructed by the model construction unit include a first conversion model provided in a preceding stage, a second conversion model provided in a succeeding stage, and a combination of the first conversion model and the second conversion model. The optimization calculation unit includes a characteristic regression model interposed between the first and second parameters, and correlates the first and second parameters by using the first and second parameters as inputs and the third parameter as an output. The first conversion model converts at least one of the first and second parameters into a physical property value to be input to the characteristic regression model. The characteristic regression model converts unobservable physical property values into unobservable theoretical property values, and the second conversion model converts theoretical property values into actual property values. The optimization calculation unit uses the constructed model to calculate the first and second parameters that are not constraint conditions, using fixed values set for some of the first and second parameters as constraint conditions, so as to satisfy one or a combination of the value and range of the third parameter, and outputs the calculated first and second parameters.

One aspect of the present invention makes it possible to quickly and inexpensively provide appropriate design values for power devices that meet the numerous characteristics required for an application. Other issues, configurations, and advantages will become clearer from the description of the following examples.

1 is a diagram illustrating a configuration of a design condition calculation system according to an embodiment of the present invention. 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. 1 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the embodiment of the present invention. FIG. 10 is a diagram illustrating an example of an input screen according to the embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of a model construction unit according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a calculation method executed by an optimization calculation unit according to an embodiment of the present invention. 1 is a flowchart of a manufacturing process of a trench MISFET. FIG. 10 is a diagram illustrating an example of an input screen according to the first embodiment. FIG. 10 is a diagram illustrating an example of an input screen according to the first embodiment. FIG. 10 is a diagram illustrating an example of a corrector 1 constituting the front stage of the model construction unit of the second embodiment. FIG. 11 is a diagram illustrating an example of a corrector 1 that constitutes the front stage of the model construction unit of the third embodiment. FIG. 11 is a diagram illustrating an example of a corrector 1 that constitutes the front stage of the model construction unit of the third embodiment. FIG. 10 is a diagram illustrating an example of a model construction unit according to a fourth embodiment. FIG. 13 is a diagram illustrating cooperation between a design condition calculation system and a semiconductor manufacturing apparatus according to a fifth embodiment. 13 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the sixth embodiment. 13 is a flowchart of a process for calculating design conditions by the design condition calculation system according to the sixth embodiment.

The power semiconductor device design condition calculation system 100 according to an embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 1A shows the configuration of the design condition calculation system 100.

The design condition calculation system 100 of this embodiment has a characteristic regression model constructed by simulation in the middle layer, and constructs a highly accurate regression model using a model construction unit 102 that has a physical property calculation model (corrector 1) in the previous stage and a physical quantity calculation model (corrector 2) in the subsequent stage.

The design condition calculation system 100 is composed of a computer having a calculation unit 101, a data storage unit 104, a communication unit 105, an operation unit 106, an output unit 107, and an input/output unit 108. The calculation unit 101, the data storage unit 104, the communication unit 105, and the input/output unit 108 are connected via a bus.

The calculation unit 101 is a computing device (CPU) that executes programs stored in memory (not shown). The calculation unit 101 executes various programs to realize the functions of each functional unit of the design condition calculation system 100 (e.g., model construction unit 102, optimization calculation unit 103, etc.). Note that some of the processing performed by the calculation unit 101 by executing the programs may be executed by a hardware calculation device such as an ASIC or FPGA.

Memory includes ROM, a non-volatile storage element, and RAM, a volatile storage element. ROM stores unchanging programs (e.g., BIOS). RAM is a high-speed, volatile storage element such as DRAM (Dynamic Random Access Memory), and temporarily stores programs executed by the computing unit 101 and data used when executing the programs.

The data storage unit 104 is a large-capacity, non-volatile storage device composed of, for example, a magnetic storage device (HDD), flash memory (SSD), or the like. The data storage unit 104 also stores data used by the calculation unit 101 when executing programs, and the programs executed by the calculation unit 101. In other words, programs are read from the data storage unit 104, loaded into memory, and executed by the calculation unit 101 to realize each function of the design condition calculation system 100.

The communication unit 105 is a network interface device that controls communication with other devices according to a specified protocol.

The operation unit 106 is made up of input devices such as a keyboard, mouse, and touch panel, and provides an input interface that receives operations from an operator. The output unit 107 is made up of output devices such as a display device and printer, and provides an output interface that outputs the results of program execution in a format that can be viewed by the operator. The input/output unit 108 is an interface that passes data input to the operation unit 106 to the bus. Note that a user terminal connected to the design condition calculation system 100 via a network may provide the operation unit and output unit. In this case, the design condition calculation system 100 may have web server functionality, and the user terminal may access the design condition calculation system 100 using a specified protocol (e.g., http).

The program executed by the calculation unit 101 is provided to the design condition calculation system 100 via removable media (CD-ROM, flash memory, etc.) or a network, and is stored in the non-volatile data storage unit 104, which is a non-temporary storage medium. For this reason, the design condition calculation system 100 should preferably have an interface for reading data from removable media.

The design condition calculation system 100 is a computer system configured on a single physical computer, or on multiple logically or physically configured computers, and may operate on a virtual computer constructed on multiple physical computer resources. For example, the model construction unit 102 and the optimization calculation unit 103 may each operate on separate physical or logical computers, or multiple units may be combined to operate on a single physical or logical computer.

Figures 1B-1, 1B-2, 1C-1, and 1C-2 are flowcharts of the process by which the design condition calculation system 100 calculates design conditions. Figures 1B-1 and 1C-1 show the process when the model construction unit 102 is inside the design condition calculation system 100, while Figures 1B-2 and 1C-2 show the process when the model construction unit 102 is outside the design condition calculation system 100.

First, in step 1, explanatory variables and objective variables are input into the operation unit 106, and in step 2, the operation details are displayed on the output unit 107. The input explanatory variables include values or value ranges of device materials, device fabrication conditions, device structure, circuit materials, circuit fabrication conditions, and circuit structure. Objective variables include values or value ranges of device characteristics and circuit characteristics. Then, in step 3, the data storage unit 104 stores the input data.

Next, in step 4, the model construction unit 102 creates a regression model for the power semiconductor device and the power semiconductor device mounted circuit using explanatory variables and target variables based on the data stored in the data storage unit 104. In the example shown in Figures 1B-1 and 1C-1, the model construction unit 102 is provided within the design condition calculation system 100. The model construction unit 102 creates a regression model each time input is made to the operation unit 106 in accordance with the input content, and stores the created regression model in the data storage unit 104. The created regression model may also be input directly to the calculation unit 101 without being stored in the data storage unit 104.

Next, in step 5, the calculation unit 101 uses a regression model to calculate the relationship between the explanatory variables stored in the data storage unit 104 and the objective variable multiple times, with the values of the explanatory variables stored in the data storage unit 104 as constraint conditions and the value of the objective variable as the target, to find the optimal value of the explanatory variable for which a value that satisfies the condition of the objective variable is not specified. Then, in step 6, the calculation unit 101 stores the optimal value of the explanatory variable and the value of the objective variable at that time in the data storage unit 104. The processing of steps 5 and 6 is repeatedly executed until a predetermined termination condition is met. The termination condition is preferably that the objective variable has reached its target value, but may also be that the number of calculations or the calculation time has reached an upper limit. Then, in step 7, the output unit 107 outputs the optimal value of the explanatory variable stored in the data storage unit 104 and the value of the objective variable at that time.

In the examples shown in Figures 1B-2 and 1C-2, one or more regression models created in advance by a model construction unit 102 provided outside the design condition calculation system 100 are registered in a database outside the design condition calculation system 100, such as a cloud database. Because regression models differ depending on the device type, it is preferable to create multiple regression models in advance and store them outside the design condition calculation system 100. In step 5, the calculation unit 101 acquires the regression model from the database via the communication unit 105 and stores it in the data storage unit 104. The calculation unit 101 uses the regression model stored in the data storage unit 104 to find the optimal value of the explanatory variable that satisfies the condition of the target variable. The calculation unit 101 may acquire the regression model directly from the database without storing it in the data storage unit 104. The design condition calculation system 100 is capable of communicating with external parties via a network.

As mentioned above, the regression model and optimal calculation results may be stored in the data storage unit 104 each time a calculation is performed, but as the amount of calculation increases, the amount of data becomes enormous, so it is not necessary to store them in the data storage unit 104 each time. On the other hand, retrieving the regression model from the database via the communication unit 105 each time increases the amount of communication and reduces speed, so access to the data storage unit 104 should be determined based on the amount of data being handled.

Figure 2 shows an example of an input screen displayed on the output unit to allow input of explanatory variables and target variables into the operation unit 106 in steps 1 and 2.

In the input screen shown in Figure 2, the type of explanatory variable to be specified can be selected in pull-down input field 8 in the input section. If further conditions need to be narrowed down, lower-level conditions can be specified in pull-down input field 9 below pull-down input field 8. The number of pull-down input fields for specifying the type of explanatory variable may be three or more. Pull-down input fields 8 and 9 preferably allow selection from the device material, device fabrication conditions, device structure, circuit material, circuit fabrication conditions, and circuit structure of the semiconductor device, as well as the device material, device fabrication conditions, device structure, circuit material, circuit fabrication conditions, and circuit structure of the circuit on which the semiconductor device is mounted. For example, if device fabrication conditions are selected as the explanatory variable, the process to be specified within the device fabrication process can be selected. If device structure is selected as the explanatory variable, the type of structure can be specified. In this way, when conditions are specified in pull-down input field 8 or pull-down input fields 8 and 9, pre-registered variables are displayed on the input screen, and fixed values or ranges for the variables can be specified by operating the fix checkboxes. Variables for which fixed values or value ranges (maximization, minimization, or both) are specified become constraints during optimization. On the other hand, it is not necessary to enter values for variables; if no values are entered, the optimization calculation will find the optimal value for the target variable.

In addition, the type of objective variable to be specified can be selected in the pull-down input field 11 in the output section, and a target value or target value range (maximization, minimization, or both) or a combination thereof can be entered on the input screen. The pull-down input field 11 preferably allows selection from device characteristics, circuit characteristics, etc. If a target value, range, maximum/minimum, or other condition or combination thereof is not entered, the variable will be calculated at an arbitrary value in the optimization calculation. If a target value, range, maximum/minimum, or other condition or combination thereof is entered, this becomes the condition for deriving an objective variable for which a fixed value is not specified in the input section.

When the parameters are input, the optimization calculation unit 103 uses the input parameter values or ranges as constraints and the parameter values and ranges input to the output section as objective variables to perform optimization calculations to determine parameters for which values are not specified among the parameters input to the input section. For example, when values are specified as shown in Figure 2, the optimization calculation unit 103 determines optimal values for the JFET length and channel length that minimize the on-resistance while maintaining the drift layer concentration in the input section at 1 x ¹⁰ and setting the output section's breakdown voltage to 1200 V or higher, the threshold voltage to 3 V to 8 V, and the gate breakdown voltage to 25 V or higher.

The left area of the input screen should display information about the conditions specified in pull-down input field 8 or pull-down input fields 8 and 9. For example, in the input screen shown in the figure, the device structure TED-MOS has been selected, so the structure of a TED-MOS FET is displayed.

Figure 3 shows the configuration of the model construction unit 102.

The model construction unit 102 constructs a regression model using explanatory variables and target variables input to the operation unit 106. The model construction unit 102 is configured with multiple layers, broadly divided into a front-stage, middle layer, and back-stage. Note that while Figure 3 illustrates a model construction unit 102 configured with three layers (front-stage, middle layer, and back-stage), the model construction unit 102 may be configured with four or more layers. The model construction unit 102 takes parameters input to the input section (parameters of the semiconductor device, parameters of the circuit mounted on the semiconductor device) as input, and correlates each parameter by outputting selectable parameters in the output section.

The first stage, the physical property calculation model (corrector 1), converts the parameters entered in the input section into physical property values used in the simulation. For example, the physical property values used in the simulation are unobservable physical property values, such as the trap amount and mobility at the oxide film interface, relative to the oxide film fabrication conditions (such as the oxide film quality, thickness, and annealing amount) as input values. In addition to the aforementioned, unobservable physical property values converted by the physical property calculation model include hole and electron mobility, scattering cross section, trap density in the oxide film, interface state density, Auger and SRH recombination rate, lifetime, saturated drift velocity, thermal conductivity, defect density, impurity concentration considering activation rate, design value considering mask misalignment, shape (trench angle, oxide film thickness, etc.) that changes depending on fabrication conditions, and material (material of the source contact portion). In particular, since theoretical formulas cannot be used to predict mobility, interface traps, and activation rate for SiC, the physical property calculation model by corrector 1 in the first stage is extremely effective. Furthermore, the input values to be corrected do not necessarily have to be unobservable physical property values; they can also be observable physical property values. For example, if a design value is input, the aperture width actually created using a mask in the photolithography process may be used as the corrected variable.

Furthermore, in power semiconductor devices using non-Si compounds, traps form at the interface with the oxide film, causing threshold voltage fluctuations and reduced switching speed. Because power semiconductor devices control high voltages, threshold voltage fluctuations reduce switching speed, posing problems from the perspectives of safety and loss. Furthermore, mobility is important because resistance must be reduced to reduce loss. However, mobility within a device is lower than bulk mobility, making it difficult to predict mobility based on theoretical characteristics. Furthermore, power semiconductor devices tend to have high electric fields within the device, and the presence of traps in the oxide film significantly reduces the reliability of the oxide film. Furthermore, there is no established model for the diffusion mechanism when impurities are implanted into a device. In particular, in power devices, the impurity concentration is increased to reduce on-resistance, resulting in a significant difference between the actual impurity concentration and the activated impurity concentration.

Variables corrected in the physical property calculation model in the previous stage are related to theoretical properties in the middle layer. For example, the middle layer creates data by performing numerous physical simulations, and then uses the created data to efficiently build a characteristic regression model through spiral learning. By modeling the middle layer rather than simply simulating it, backpropagation from the input in the previous stage to the output in the subsequent stage is possible, enabling the physical property calculation model to be trained.

The theoretical characteristics obtained in the intermediate layer are converted into measurable physical quantities in a physical quantity calculation model (corrector 2) in the subsequent stage. For example, the corrector 2 performs the following conversion to calculate observable physical quantities.
・Converts the internal temperature of a semiconductor into short-circuit resistance. ・Adds the offset resistance measured to the on-resistance. ・Corrects the effect of contact resistance caused by the measurement to the theoretically derived on-resistance of a semiconductor device. ・In particular, for MIS FETs (Metal-Insulator-Semiconductor FETs) with trenches, calculates the reliability of the gate insulating film from the electric field strength applied to the corners of the trench. ・Calculates switching loss and switching time from the external resistance of the semiconductor device's circuit and the capacitance inside the semiconductor device. ・Calculates short-circuit time from the saturation current characteristics during a short circuit.

In particular, measurable physical quantities may include on-resistance, threshold voltage, breakdown voltage, and insulating film reliability as output characteristics of the power semiconductor device, and short-circuit resistance and switching loss as characteristics of the circuit on which the semiconductor device is mounted. These measurable physical quantities may be derived from the characteristic regression model in the middle stage, but deriving them using corrector 2 allows for the construction of a faster regression model.

In this way, the corrector 2 can convert a given physical quantity into an actual physical quantity that is the same physical quantity, and can also derive a different physical quantity from a given physical quantity. In particular, in a MISFET structure having an oxide film, the dielectric breakdown strength of SiC is about one order of magnitude higher than that of Si, resulting in a high electric field strength in the oxide film, making the reliability of the oxide film important. However, since there are various indicators of oxide film reliability and they affect yield, it is difficult to derive them through theoretical calculations, and derivation using the corrector 2 is essential. Furthermore, depending on the quality of the insulating film, phenomena such as positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) , which cause threshold shifts, can occur. However, the causes of these phenomena have not been precisely elucidated, and accurate theoretical models are not available, making derivation using the corrector 2 necessary.

The front stage (corrector 1 based on a physical property calculation model), middle layer (characteristic regression model), and back stage (corrector 2 based on a physical quantity calculation model) should all be learning models constructed through learning.

The simulations used in the regression model in the intermediate layer of the model construction unit 102 involve unobservable parameters, but the front-stage corrector 1 and rear-stage corrector 2 make it possible to construct a highly accurate model that can input and output observable data.

Note that Figure 3 is described as a diagram showing the configuration of the model construction unit 102, but since the model construction unit 102 and the model constructed by the model construction unit 102 realize the same input and output, if the model constructed by the model construction unit 102 is configured as a neural network, it can also be considered a diagram showing the configuration of this neural network. In this respect, Figures 7 to 10, described below, can also be considered diagrams showing the configuration of a model.

Figure 4 shows the calculation method performed by the optimization calculation unit 103.

The optimization calculation unit 103 uses the regression model constructed by the model construction unit 102 to perform optimization calculations to determine optimal values for parameters that have not been specified among the parameters entered in the input section of the input screen, with the parameters entered in the output section of the input screen as objective variables, so as to satisfy the conditions of the objective variables. In the optimization calculations, the relationship between the explanatory variables and the objective variables is calculated multiple times from the regression model so that the parameters entered in the multiple input sections satisfy the conditions of the multiple parameters specified in the output section, and explanatory variables that optimize the objective variables are determined. By repeating such calculations, it is possible to derive complex conditions for the design, materials, and manufacturing conditions of semiconductor devices and semiconductor device-mounted circuits that humans would never think of.

There are many different optimization calculation methods that can be adopted by the optimization calculation unit 103, and the present invention does not require any particular optimization method to be limited. Therefore, an example using the Newton method, a common optimization calculation method described below in Figures 12A and 12B, will be described.

12A and 12B, in step 2, an arbitrary objective variable is designated as a minimum value on the input screen (FIG. 2), and the minimum value is calculated using Newton's method. The objective variable and explanatory variables are related by a regression model created by the model construction unit 102. In FIGS. 12A and 12B, the explanatory variable corresponding to the inputs α1, α2, ... in FIG. 3 is denoted as x (x may be a vector of multiple variables), and the objective variable corresponding to the output β in FIG. 3 is denoted as y, and one of the regression models created by the model construction unit 102 is y = g(x). In other words, using a regression model, it is possible to calculate objective variable y for any explanatory variable x, and by sequential calculation, y for a certain x can be calculated, and an explanatory variable x can be derived such that objective variable y more closely matches the conditions of the objective variable entered on the input screen. When using Newton's method to find the explanatory variable x that minimizes the response variable y, the tangent of the function at a certain search point xk is found for the regression model y = g(x), and the direction in which y decreases based on the slope of the tangent is set as the search direction. Next, the value of y at point xk+1 where the tangent intersects the x-axis is derived from the regression model y = g(x), and the tangent of the function at xk+1 is found to determine the search direction. This process is repeated until the condition for y is met. In the example shown in Figure 4, the point where the slope of the tangent changes from positive to negative is the point where the value of the response variable y is minimized, and the value of x at this time is the optimal calculation result, which represents the desired materials, manufacturing conditions, and design of the power semiconductor device and the circuit equipped with the power semiconductor device.

Next, the manufacturing process for a trench MIS FET will be explained with reference to Figure 5.

First, in step A, a SiC bulk substrate (e.g., 4H-SiC, 1e18, Si-face, 4° off) is prepared. The SiC bulk substrate may be fabricated using a sublimation method, a solution method, a gas growth method, or a substrate already having an epitaxially grown layer. Chemical mechanical polishing (CMP) may be performed before the epitaxial layer is grown. The substrate concentration may be 1e18 to 1e21. The crystal type may be 4H-SiC, 6H, or 3C. The surface may be Si-face, C-face, or any other surface orientation. Preferably, a substrate with an off-angle is used, but a just-oriented substrate may also be used. The type, concentration, surface, off-angle, etc. of the substrate prepared in step A may be optimized for the semiconductor material using the design condition calculation system 100 of this embodiment.

Next, in step B, an epitaxial growth layer is formed. For example, SiH4 and C3H8 are heated to a temperature of 1500°C or higher using H2 as the carrier gas, and epitaxial growth is performed to form an epitaxial layer. The concentration and thickness of the epitaxial layer formed vary depending on the device being fabricated, but a concentration of approximately 1e14 to 1e18 and a thickness of several microns to several tens of microns are recommended. A highly concentrated buffer layer may also be formed before forming the epitaxial layer. The concentration of the buffer layer is preferably approximately 1e18. The epitaxial layer is also referred to as a drift layer. The growth conditions (temperature, carrier gas, purge gas, other device conditions), concentration, thickness, etc. of the epitaxial layer and buffer layer may be optimized for the semiconductor material using the design condition calculation system 100 of this embodiment.

Next, in step C, ion implantation regions are formed. Step C is a necessary step for the SiC power semiconductor device described later in Example 5. For example, P-type implanted ions may be aluminum or boron, and N-type implanted ions may be nitrogen or phosphorus. A P-type body region (p), potential clamping region (p++), and guard region (p), as well as an N-type source region (n++), current diffusion region (n+), and JFET region (n- to n+) are formed in the drift layer by ion implantation. The body region may be formed by P-type epitaxial growth. Note that the polarity may be reversed between P-type and N-type. "-" and "+" are symbols that indicate the relative impurity concentration of n-type or p-type conductivity. For example, the concentration of n-type impurities increases in the order of "n--", "n-", "n", "n+", and "n++".

The source region and potential clamping region are formed in contact with the wafer surface. The body region is in contact with the source region and is formed deeper than the source region. Furthermore, the body region is electrically connected to the potential clamping region. The current spreading region is in contact with the body region and is formed deeper than the body region. The guard region is in contact with the current spreading region and is formed deeper than the current spreading region. Furthermore, the guard region is electrically connected to the potential clamping region. The JFET region is a region sandwiched between the guard regions that connects the current spreading region and drift region, and ion implantation may be performed to reduce resistance. Note that the example shown in Figure 5 has the minimum configuration necessary for MOS operation, so a structure that adds functions such as a termination region may also be created.

The mask conditions (type, thickness, fabrication conditions, mask removal conditions, etc.) and implantation conditions (ion species, implantation energy, number of implantation stages, implantation angle, etc.) used during ion implantation may be optimized for fabrication conditions using the system of the present invention, and the implantation depth, implantation region, impurity concentration, etc. may be optimized for design and structure using the design condition calculation system 100 of this embodiment.

Next, in step D, a carbon film of cap material for impurity activation annealing is deposited around the silicon carbide substrate and the silicon carbide epitaxial layer, and impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. The carbon layer of the cap material is then removed by oxygen plasma ashing. A thermal oxide film may then be formed, and the thermal oxide film may be removed using a diluted hydrofluoric acid solution to clean the surface. The type of cap material, annealing temperature, annealing time, conditions for the cap material removal method, and the type, shape, thickness, and other formation and removal conditions of the thermal oxide film may be optimized for the manufacturing conditions using the design condition calculation system 100 of this embodiment.

Next, in step E, a trench is formed. For example, a trench is formed by etching, which penetrates the source region, the body region, and the current diffusion region and has a bottom that fits within the guard region.
Thereafter, a thermal oxide film may be formed, and the thermal oxide film may be removed using a diluted hydrofluoric acid solution to clean the etched surface. The mask conditions (type, thickness, fabrication conditions, mask removal conditions) used in the etching, the etching conditions (etching time, etching gas type, applied voltage, etc.), and the post-etching treatment (type, shape, thickness, other fabrication conditions and removal conditions, etc.) may be optimized in terms of fabrication conditions by the design condition calculation system 100 of this embodiment. Furthermore, the depth, width, shape, etc. of the trench may be optimized in terms of design and structure by the design condition calculation system 100 of this embodiment.

Next, in step F, a gate insulating film is formed on the semiconductor. For example, the gate insulating film is formed from a SiO2 film by thermal CVD. The thickness of the gate insulating film is, for example, approximately 0.005 to 0.15 μm. After depositing a gate electrode made of an n-type polycrystalline silicon film approximately 100 to 300 nm thick, an interlayer film is preferably formed to cover the gate electrode. The types of gate insulating film, gate electrode, and interlayer film, their fabrication conditions (fabrication method, etc.), annealing temperature, annealing time, conditions for the capping material removal method, type of thermal oxide film, and other formation and removal conditions may be optimized for fabrication conditions using the design condition calculation system 100 of this embodiment. The shape and thickness of the gate insulating film and thermal oxide film may be optimized for design and structure using the design condition calculation system 100 of this embodiment.

Next, in step G, various electrodes are formed. For example, to make contact between the source region and the potential fixing region, the interlayer film is etched using a resist as a mask to form contact holes, silicide metal is deposited, and then annealed at 700°C to 1000°C to form a silicide, forming a common source-base contact. After that, to make contact with the gate electrode, the interlayer film is etched and a gate contact hole is formed.

Then, a source electrode is formed. At the same time, the drain region on the back surface is silicided to form a drain contact, and then a drain contact electrode is formed. Metal materials such as Ni and Al are preferably used for the silicide metal, source electrode, and drain contact electrode. After that, a surface protection film made of an insulator is formed to cover the entire surface to protect the device, and wiring to the electrodes is performed, completing the semiconductor device.

Interlayer film etching conditions (etching time, etching gas type, applied voltage, etc.), contact and electrode conditions (metal material, silicide annealing temperature, etc.), and insulating film and wiring fabrication conditions may be optimized for fabrication conditions using the design condition calculation system 100 of this embodiment, and electrode and contact regions and ranges may be optimized for design and structure using the design condition calculation system 100 of this embodiment.

Next, we will explain a specific example in which the design condition calculation system 100 of the above-mentioned embodiment is applied.

Example 1
The design condition calculation system 100 of this embodiment calculates the optimum conditions for a trench MIS FET, which has a structure that allows the channel structure and JFET structure to be designed independently, as a power semiconductor device, and an inverter circuit equipped with a trench MIS FET.

An example of the input screen for this embodiment is described using Figures 6A and 6B. The semiconductor device to be optimized in this embodiment is a silicon carbide semiconductor device with a trench MISFET structure. For example, on the input screen, variables that do not need to be changed in the design, such as trench depth and drift concentration, can be specified as fixed values of 0 or 1 or greater. Meanwhile, variables that are not set as fixed values, such as the design of the JFET region in the n-type epitaxial layer between the trenches and the channel design corresponding to the trench width and depth, are optimized. In particular, the trench MISFET structure optimized in this embodiment uses the trench as the channel, and the JFET region is formed separately from the trench. This allows the channel and JFET to be designed independently, enabling a design that avoids the commonly problematic trade-off between on-resistance and short-circuit withstand capability. Therefore, in the example shown in Figures 6A and 6B, the values of the objective variables are set to minimize on-resistance and ensure short-circuit withstand capability for a sufficient time (3 μs) for the application circuit. The types and number of variables and other conditions are not limited to those shown in Figures 6A and 6B.

As described above, the design condition calculation system 100 of Example 1 makes it possible to optimize the trench MIS FET structure of the semiconductor device to be optimized, as shown in Example 1, and easily enables a design that meets the requirements for both short circuit time and on-resistance.

Example 2
The design condition calculation system 100 of this embodiment calculates the optimum conditions for heat and noise, which are particular problems when a power semiconductor device made of a material other than SiC is used for power conversion.

In this embodiment, power semiconductor devices made of Si, SiC, or other materials are optimized. Power semiconductor devices are used for power conversion and handle large amounts of power, so heat and noise are important from the perspective of safety, such as preventing malfunctions, and from the perspective of operating life. In particular, it is difficult to identify the source of noise, whether it is the device or the circuit, and identifying the cause relies on the experience and knowledge of engineers. Therefore, the present invention is highly effective in the design of power semiconductor devices and the design of applications that incorporate power semiconductor devices.

Figure 7 is a diagram showing an example of the corrector 1 that constitutes the front stage of the model construction unit 102 in this embodiment. The corrector 1 is composed of one or more multi-layers. While Figure 7 illustrates a four-layer configuration, other numbers of layers may be used. Of these layers, in this embodiment, one or more layers include a thermal characteristic regression model created by spiral learning using thermal simulation. For example, when variables defining the module structure are input into the design and structure of the semiconductor device-mounted circuit in the input, the variables defining the module structure are converted into circuit components such as heat capacity and thermal resistance by the thermal characteristic regression model layer. In this embodiment, in addition to the parameters shown in Figure 7, parameters that cause heat and noise, and parameters that are affected by heat and noise, may be input or output.

Example 3
In this embodiment, the corrector 1 is configured with one or more multilayers, and at least one layer is configured with an encoder that extracts features using a physical formula that represents the physical properties of a semiconductor and reduces dimensions. This enables correction based on the physical formula and prevents overfitting.

8 is a diagram showing an example of the corrector 1 constituting the front stage of the model construction unit 102 in this embodiment. As an example of input dimension reduction by the encoder, application to the design value of a device structure will be described. In the drain current equation for a MOS FET, the channel width W and channel length L may differ from the design values due to mask misalignment in the photolithography process, but since they contribute to the current in the following equation, the channel width W and channel length L correlate with the output on-resistance and the feature quantity W/L.
I _ds = μ _eff C _ox W/L(V _g -V _th )V _ds

Therefore, by calculating the above equation using an encoder present in one or more layers of the previous-stage corrector 1, the feature W/L can be extracted and the feature W/L can be corrected to obtain the correct output. Such an encoder is not limited to physical equations; it can also be extracted using an autoencoder that trains by inputting the same values for input and output, as shown in Figure 9. Also, as mentioned above, encoders that use physical equations and encoders constructed by training can also be applied to the subsequent-stage corrector 2.

Example 4
In this embodiment, the actual characteristics of the semiconductor device corrected by the corrector 2 are treated as an intermediate layer.

Figure 10 shows an example of the model construction unit 102 in this embodiment.

In Example 4, the intermediate layer is composed of a characteristic regression model, a corrector 2A, and a circuit characteristic model.

The parameters of the semiconductor device and the parameters of the circuit on which the semiconductor device is mounted entered on the input screen are input separately to corrector 1A and corrector 1B, respectively. Corrector 1A converts parameters representing at least one of the semiconductor device's material, manufacturing process, and design into unobservable physical property values. As shown in Figure 3, the characteristic regression model converts the unobservable physical property values of the semiconductor device into unobservable theoretical characteristic values, and corrector 2A converts the unobservable theoretical characteristic values of the semiconductor device into measurable physical quantities.

Because the actual characteristics of the semiconductor device corrected by corrector 2 are treated as an intermediate layer, the device characteristics are not correlated with the materials, manufacturing process, design, or structure of the mounted circuit, but are related only to variables converted from device input values that clearly relate to the device characteristics. Furthermore, the circuit characteristics are not directly related to device-related variables, but are associated with the characteristics β1, β2, ... of the mounted semiconductor device. Therefore, the characteristic regression model is created primarily by learning through device simulation, and the circuit characteristic model is created primarily by learning through circuit simulation in which the device characteristics are replaced with an equivalent circuit, and parameters representing at least one of the materials, manufacturing process, and design of the circuit mounted with the semiconductor device are converted into theoretical characteristic values of the circuit mounted with the semiconductor device. The circuit characteristic model may correlate the output values of the characteristic regression model with observed quantities of the semiconductor device characteristics. For example, if on-resistance is considered as an observable quantity of a semiconductor device characteristic, the values entered as design and structural conditions of the semiconductor device mounted circuit are converted by corrector 1 to obtain the semiconductor device characteristics into on-resistance, resistance caused by the module structure, and circuit resistance, which are then converted by corrector 2B into characteristics of the semiconductor device mounted circuit, and then converted into actual measured values of the semiconductor device mounted circuit using a circuit characteristic model.

The corrector 2B converts the theoretical characteristic values of a circuit incorporating a semiconductor device into observable characteristic values of that circuit.

In this way, by ignoring correlations that do not have a direct correlation and only taking into account some correlations, a model can be created that is easier to learn and avoids overfitting.

Example 5
In this embodiment, a method for manufacturing a SiC power semiconductor device and a circuit equipped with the SiC power semiconductor device will be described. As described above with reference to Fig. 5 for the manufacturing process of the trench MISFET, the semiconductor device manufacturing method of this embodiment manufactures a semiconductor device using manufacturing conditions optimized for design and structure by the design condition calculation system 100 of the above-described embodiment.

The input values on the input screen can be optimized by inputting process conditions such as the etching time and voltage for creating trenches, the type of oxide film, and the pressure during oxide film creation. Furthermore, if the corrector 1 of the model construction unit 102 created through learning is installed in semiconductor manufacturing equipment, physical property values such as mobility can be calculated from manufacturing conditions such as the amount of mask misalignment in the photolithography process and the conditions of the oxide film creation process, and the learning results of the corrector 1 can be fed back to the manufacturing equipment that creates semiconductor devices.

In this way, by using the design condition calculation system 100 of this embodiment, as shown in Figure 11, semiconductor manufacturing equipment can be linked to the design condition calculation system 100, enabling manufacturing under optimal conditions for various device conditions.

Example 6
In the above-described first to fifth embodiments, the model construction unit 102 constructs a regression model in advance based on a pre-trained learning model. On the other hand, in this embodiment, even if the regression model constructed by pre-training does not have sufficient accuracy, the results of the optimization calculation are fed back to reconstruct the regression model, and the optimization calculation is repeated while increasing the accuracy of the regression model.

Figures 12A and 12B are flowcharts of the process by which the design condition calculation system 100 of this embodiment calculates design conditions.

In this embodiment, if the objective variable obtained after the optimization calculation does not satisfy a certain standard, a physical simulation related to the optimized design is redone, and the result is fed back to the characteristic regression model in the intermediate layer of the model construction unit 102 for re-learning, thereby constructing a more accurate regression model and performing the optimization calculation. In the example shown in Figures 12A and 12B, optimization is performed so that the difference between the objective variable βi and the target value ans, which is the condition for the objective variable entered on the input screen, is smaller than a predetermined threshold ε. That is, in step 8, it is determined whether the difference between the objective variable βi and the target value ans is greater than a predetermined threshold ε. If the difference between the objective variable βi and the target value ans is greater than the predetermined threshold ε, the input values optimized in the optimization calculation are fed back to the model construction unit 102, the fed-back input values are converted by the corrector 1 in the upstream stage of the model construction unit 102, a physical simulation is performed near the physical property values converted from the fed-back input values, and the physical property values and the theoretical property values obtained in the physical simulation are fed back to the characteristic regression model in the model construction unit 102 to construct a new characteristic regression model. The optimization calculation is then performed again using the new characteristic regression model. The results of the optimization calculation are evaluated again in step 8, and if the difference between the objective variable βi and the target value ans is greater than the predetermined threshold ε, the calculation process is repeated. If the difference between the calculated objective variable βi and the target value ans is less than the predetermined threshold ε, the iterative process is terminated and the optimal calculation result is displayed.

As shown in the sequence diagram of FIG. 12B, the optimization calculation, physical simulation, and model construction may be repeated the same number of times, but as long as the optimization calculation is performed one or more times, the regression model and conditions for the optimization calculation may be retrieved multiple times. For example, if the number of optimization calculations or time are specified in advance, and an explanatory variable that can derive a target variable βi whose difference from the target value ans is smaller than ε cannot be found within that number of calculations or time, the model may be reconstructed. Also, in this embodiment, as in Example 1, the number of times data is saved to the data storage unit 104 is not limited to the number described above. Furthermore, the processing (step 4) of the model construction unit 102 and the physical simulation (step 9) may be performed outside the design condition calculation system 100 (e.g., on the cloud).

As explained above, the feedback to the optimization calculation model construction allows the pre-trained characteristic regression model in the intermediate layer of the model construction unit 102 to be added through feedback in a range close to the desired design, even if the number of pre-trained simulation data is small and the accuracy of the characteristic regression model is low. This improves the accuracy of the regression model in a range close to the optimization calculation results, and also improves the calculation accuracy of the explanatory variables that derive the desired objective variable. In Figure 12A, the condition for the iterative calculation is that the difference between the objective variable βi and the target value ans is smaller than a predetermined threshold ε, but the condition for the iterative calculation is not limited to this, and the minimum, maximum, one value, or value range can be specified on the input screen.

As described above, the design condition calculation system 100 according to an embodiment of the present invention comprises a calculation device (calculation unit 101) that executes predetermined processing, an input unit (input/output unit 108) to which data is input, and a storage device (data storage unit 104) accessible by the calculation device. The input unit receives input of a first parameter representing at least one of the material, manufacturing process, and design of a semiconductor device, a second parameter representing at least one of the material, manufacturing process, and design of a circuit incorporating the semiconductor device, and a third parameter representing at least one characteristic of the semiconductor device and the circuit incorporating the semiconductor device. The design condition calculation system 100 includes an optimization calculation unit 103 in which the calculation device calculates the first parameter and the second parameter using a model constructed by a model construction unit so as to satisfy predetermined conditions. The model constructed by the model construction unit 102 comprises a first conversion model (corrector 1, which is a physical property calculation model) provided in the preceding stage, a second conversion model (corrector 2, which is a physical quantity calculation model) provided in the succeeding stage, and the The optimization calculation unit 103 uses the constructed model to calculate the first and second parameters that are not constraint conditions, using fixed values set for some of the first and second parameters as constraint conditions, so as to satisfy one or a combination of the value and range of the third parameter, and outputs the calculated first and second parameters, thereby making it possible to provide an optimized design that satisfies numerous characteristics in power devices tailored to application requirements quickly and at low cost. Furthermore, while the simulations used in characteristic regression models can only calculate the relationship between unobservable parameters, a highly accurate model of observable data can be constructed using the front-stage corrector 1 and rear-stage corrector 2. Furthermore, by creating a model, characteristics can be predicted with high accuracy without having to perform time-consuming simulations each time.

The present invention is not limited to the above-described embodiments, and includes various modifications and equivalent configurations within the spirit of the appended claims. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to configurations that include all of the described configurations. Furthermore, part of the configuration of one embodiment may be replaced with the configuration of another embodiment. Furthermore, the configuration of another embodiment may be added to the configuration of one embodiment. Furthermore, part of the configuration of each embodiment may be added to, deleted from, or replaced with other configurations.

Furthermore, the aforementioned configurations, functions, processing units, processing means, etc. may be realized in part or in whole in hardware, for example by designing them as integrated circuits, or in software, by a processor interpreting and executing a program that realizes each function.

Information such as programs, tables, and files that implement each function can be stored in storage devices such as memory, hard disks, and solid-state drives (SSDs), or in recording media such as IC cards, SD cards, and DVDs.

Furthermore, the control lines and information lines shown are those considered necessary for explanation, and do not necessarily represent all control lines and information lines necessary for implementation. In reality, it is safe to assume that almost all components are interconnected.

100 Design condition calculation system 101 Calculation unit 102 Model construction unit 103 Optimization calculation unit 104 Data storage unit 105 Communication unit 106 Operation unit 107 Output unit 108 Input/output unit

Claims (13)

A design condition calculation system,
The system includes a computing device that executes predetermined processing, an input unit to which data is input, and a storage device that can be accessed by the computing device,
the input unit receives input of a first parameter representing at least one of a material, a manufacturing process, and a design of the semiconductor device, a second parameter representing at least one of a material, a manufacturing process, and a design of a circuit on which the semiconductor device is mounted, and a third parameter representing at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted;
the design condition calculation system includes an optimization calculation unit configured to calculate the first parameters and the second parameters using a model constructed by a model construction unit so as to satisfy predetermined conditions;
The model constructed by the model construction unit is
a first conversion model provided in a preceding stage, a second conversion model provided in a succeeding stage, and a characteristic regression model provided between the first conversion model and the second conversion model;
the first parameter and the second parameter are input, and the third parameter is output, thereby relating the respective parameters;
the first conversion model converts at least one of the first parameter and the second parameter into a physical property value to be input to the characteristic regression model;
The property regression model converts unobservable physical property values into unobservable theoretical property values;
the second conversion model converts theoretical characteristic values into actual characteristic values;
The optimization calculation unit
using the constructed model, calculating the first parameters and the second parameters that are not constraint conditions so as to satisfy a condition based on one or a combination of the value and range of the third parameter, with fixed values set as part of the first parameters and the second parameters as constraint conditions;
A design condition calculation system that outputs the calculated first and second parameters. 2. The design condition calculation system according to claim 1,
a design condition calculation system characterized in that the optimization calculation unit calculates the first parameter and the second parameter which are not the constraint conditions by using a regression model created by the model construction unit provided outside the design condition calculation system. 2. The design condition calculation system according to claim 1,
The design condition calculation system is characterized in that the first parameter includes at least one of the physical property values of the semiconductor device, that is, mobility, effective impurity concentration, interface state, and oxide film trap density. 2. The design condition calculation system according to claim 1,
The design condition calculation system is characterized in that the third parameter includes at least one of on-resistance, short-circuit withstand capability, threshold voltage, frequency band, withstand voltage, switching loss, and insulating film reliability, which are characteristics related to a power semiconductor device or a power semiconductor device mounted circuit. 5. The design condition calculation system according to claim 4,
the third parameter includes an on-resistance and a short-circuit withstand capability,
The optimization calculation unit calculates the first parameter and the second parameter that improve the trade-off between the on-resistance and the short-circuit tolerance in a silicon carbide semiconductor device that allows the structure of a JFET region and the structure of a channel region to be designed independently. 2. The design condition calculation system according to claim 1,
the first transformation model includes one or more layers;
A design condition calculation system, characterized in that one or more layers included in the first conversion model are thermal characteristic regression models learned by thermal simulation. 2. The design condition calculation system according to claim 1,
the first transformation model includes one or more layers;
A design condition calculation system characterized in that one or more layers included in the first transformation model are encoders that extract features of at least some of the first parameters and the second parameters and reduce the dimensions of the input parameters. 8. The design condition calculation system according to claim 7,
The design condition calculation system is characterized in that the encoder extracts feature quantities using physical formulas that represent physical properties of semiconductors. 8. The design condition calculation system according to claim 7,
A design condition calculation system characterized in that the encoder is an autoencoder that learns using the same values for input and output values. 2. The design condition calculation system according to claim 1,
the front stage of the model construction unit includes the first transformation model and a third transformation model;
an intermediate layer of the model building unit includes the characteristic regression model, the second transformation model, and a circuit characteristic model;
the latter stage of the model building unit includes a fourth transformation model;
the first conversion model converts the first parameter into an unobservable physical property value of the semiconductor device to be input to the characteristic regression model;
the characteristic regression model converts unobservable physical property values of the semiconductor device into unobservable theoretical characteristic values;
the second conversion model converts unobservable theoretical characteristic values of the semiconductor device into actual characteristic values;
the circuit characteristic model converts the actual characteristic values of the semiconductor device output by the second conversion model and the second parameters into theoretical characteristic values of a circuit mounted on the semiconductor device;
the third conversion model converts the second parameters into unobservable physical property values of a circuit mounted on the semiconductor device to be input to the circuit characteristic model;
The design condition calculation system is characterized in that the fourth conversion model converts theoretical characteristic values of a circuit mounted on a semiconductor device outputted by the circuit characteristic model into actual characteristic values. 2. The design condition calculation system according to claim 1,
the first conversion model is implemented in a semiconductor manufacturing device connected to the design condition calculation system,
The semiconductor manufacturing device calculates processing conditions using the first conversion model. 2. The design condition calculation system according to claim 1,
The computing device
After the first parameter and the second parameter that are not constraints are calculated,
comparing the third parameter with a target value;
a design condition calculation system characterized in that, when the third parameter does not satisfy a predetermined condition for the target value, the input value and output value of the optimization calculation unit are fed back to learn and reconstruct the characteristic regression model. A manufacturing method for manufacturing a semiconductor device under conditions of first parameters output by a design condition calculation system, comprising:
The design condition calculation system is configured by a computer having an arithmetic unit that executes predetermined processing, an input unit to which data is input, and a storage device that can be accessed by the arithmetic unit,
the input unit receives input of a first parameter representing at least one of a material, a manufacturing process, and a design of the semiconductor device, a second parameter representing at least one of a material, a manufacturing process, and a design of a circuit on which the semiconductor device is mounted, and a third parameter representing at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted;
the design condition calculation system includes an optimization calculation unit configured to calculate the first parameters and the second parameters using a model constructed by a model construction unit so as to satisfy predetermined conditions;
The regression model constructed by the model construction unit is
a first conversion model provided in a preceding stage, a second conversion model provided in a succeeding stage, and a characteristic regression model provided between the first conversion model and the second conversion model;
the first parameter and the second parameter are input, and the third parameter is output, thereby relating the respective parameters;
the first conversion model converts at least one of the first parameter and the second parameter into a physical property value to be input to the characteristic regression model;
The regression model converts unobservable physical property values into unobservable theoretical property values;
the second conversion model converts theoretical characteristic values into actual characteristic values;
The optimization calculation unit
using the constructed model, calculating the first parameters and the second parameters that are not constraint conditions so as to satisfy a condition based on one or a combination of the value and range of the third parameter, with fixed values set as part of the first parameters and the second parameters as constraint conditions;
A method for manufacturing a semiconductor device, comprising: outputting the calculated first parameter and second parameter.