JP7743873B2 - Method for fabricating field-effect transistors - Google Patents

Description

The present invention relates to a method for fabricating a field effect transistor .

A heterojunction field effect transistor (HFET), or high electron mobility transistor (HEMT), is a transistor that switches on and off by changing the carrier density in the channel layer using an electric field generated by a gate voltage.

When the above-mentioned transistors are constructed from nitride semiconductors such as GaN, for example, in an AlGaN/GaN heterojunction, a two-dimensional electron gas (2DEG) is often used, where electrons gather at the interface to compensate for the difference in polarization between the AlGaN layer and the GaN layer. In a typical Ga-polarity GaN HEMT (GaN-based HEMT), a gate electrode is formed on an AlGaN layer several nanometers to several tens of nanometers thick to control the 2DEG concentration at the AlGaN/GaN interface.

When considering high-frequency applications of GaN-based HEMTs, it is important to confine carriers to the thin region at the AlGaN/GaN interface and eliminate other leakage paths. This speeds up the response to voltage applied to the gate electrode and achieves stable operation.

HEMTs using GaN are being developed for use in high-frequency devices, taking advantage of the high mobility of 2DEG. However, Ga-polar HEMTs have AlGaN, which has a large band gap, placed on the device surface, which presents challenges such as (1) high contact resistance and (2) the AlGaN layer cannot be made thin to maintain carrier density, leading to short-channel effects.

These issues are hindering improvements to the high-frequency characteristics of GaN HEMTs. Techniques being considered to address these issues include (1) regrowing the regions directly under ohmic electrodes, such as source and drain electrodes, to reduce contact resistance, and (2) increasing the Al composition to thin the AlGaN layer to suppress short-channel effects. However, there are limitations to how much ohmic contact resistance can be reduced.

N-polar GaN is a crystal formed by inverting Ga-polar GaN, and offers the following three advantages when fabricating HEMTs. First, it requires a high Al composition and a thickness of approximately 20 nm to supply carriers. The highly resistive AlGaN layer is located below the GaN channel layer and is not positioned between the ohmic electrode and the channel, thereby reducing contact resistance. Second, the thickness of the surface GaN layer does not significantly affect carrier density, so it can be made thin to suppress short-channel effects. Third, the AlGaN layer directly below the channel acts as a back barrier, suppressing short-channel effects. Due to these advantages, fabricating HEMTs using N-polar GaN is expected to further improve the high-frequency characteristics of GaN HEMTs (Non-Patent Document 3).

Compared to Ga-polar GaN-based HEMTs, N-polar GaN-based HEMTs have the advantage of reduced contact resistance due to their epitaxial structure, but research is underway to further reduce contact resistance through processes. One such technique is to regrow n-type doped GaN in the region below the ohmic electrode. The GaN channel layer is not doped because impurities reduce the mobility of the 2DEG and degrade the performance of the electronic device.

The bandgap of GaN is smaller than that of AlGaN, but is still large among semiconductor materials, meaning that the resistance of undoped GaN is higher than that of other semiconductor materials. Therefore, to reduce contact resistance without causing degradation of electronic device characteristics due to impurities, one technique involves etching only the region below the ohmic electrode in an undoped GaN channel layer, and then regrowing n-type doped GaN in this area to form a regrowth layer. This technique reduces contact resistance with the doped regrowth layer, while achieving a device structure that maintains high mobility in the channel portion below the gate electrode without being affected by doping.

The above-mentioned technology can reduce ohmic resistance, but there are two challenges to be overcome in order to further improve device characteristics:

First, there are issues associated with using GaN. Although the regrown GaN is doped n-type, the fact remains that GaN with a large band gap is used, and therefore the contact resistance is higher than that of other n-type semiconductors with similar doping concentrations. For example, it has been reported that the contact resistance of n-type GaN doped with Si at 1.5×10 ¹⁸ cm ⁻³ is approximately 1×10 ⁻⁵ Ωcm ² (Non-Patent Document 1). It has also been reported that the contact resistance of n-type GaAs doped with Si at 1×10 ¹⁸ cm ⁻³ is 5×10 ⁻⁷ Ωcm ² (Non-Patent Document 2).

There is a limit to the Si doping concentration, and the Si doping concentration of the regrown GaN layer is often on the order of ^{10 cm} (Non-Patent Document 4). Therefore, the large band gap results in high contact resistance for similar doping concentrations, which can be said to be an issue when using GaN as a material for the regrown layer.

The second issue is the process. Regrowth requires etching the GaN channel layer once it has been grown. In this process, it is desirable to leave the 2DEG without completely etching the GaN, in order to ensure good contact between the 2DEG in the channel region and the regrowth layer. The 2DEG is located approximately 1 to 2 nm from the GaN/AlGaN interface at the bottom of the channel layer. Therefore, in order to leave the 2DEG, etching is required to leave a thickness of approximately 5 nm of the channel layer. The channel layer is a thin layer, approximately 20 nm or less thick, and the required etching depth (thickness) is several nm to several tens of nm.

A large etching depth significantly reduces the carrier density of the 2DEG, while a small etching depth leaves too much distance between the 2DEG and the regrowth layer. In either case, contact resistance increases, so controlling the etching depth is important. Methods for controlling the etching depth include using selective etching and controlling the etching time. However, in N-polarity GaN-based HEMTs, it is undesirable for the channel layer to contain layers composed of materials other than GaN in the region under the gate electrode that is not etched, so selective etching, which requires an etching stop layer, cannot be used. For this reason, etching depth control is primarily achieved by controlling the etching time.

However, the etching rate of reactive ion etching (ICP-RIE) using a chlorine-based gas plasma generated by inductive coupling, which is used to etch GaN, is generally high, ranging from several dozen to several tens of nm/min. Therefore, a deviation in processing time of a few seconds in this etching process can lead to an etching depth error of 1 nm or more, making it insufficient as a technology for reproducibly achieving the precision required for etching the regrowth layer described above.

In addition, the etched thin film must be exposed to the atmosphere before it can be introduced into a crystal growth furnace where regrowth will occur. This exposure causes a large number of impurities from the atmosphere to be adsorbed onto the surface prior to regrowth. These impurities are then incorporated into the interface and regrowth layer, causing unintended effects on device characteristics, such as variations in doping concentration and the resulting fluctuations in contact resistance.

In recent years, atomic layer etching (ALE) technology using chlorine gas for etching GaN has been researched, and progress has been made in improving the controllability of etching depth. However, even in this case, exposure to the atmosphere after etching is unavoidable, and while wafer cleaning methods have been actively investigated, it is not possible to completely eliminate impurities from the atmosphere, and it is impossible to avoid unintended effects of atmospheric impurities on device characteristics.

K. Hotta et al., "Annealing temperature dependence of alloy contact for N-polar GaN HEMT structure", Japanese Journal of Applied Physics, vol. 58, SCCD14, 2019. K. S. Chen et al., "A Cu-based alloyed Ohmic contact system on n-type GaAs", Applied Physics Letters, vol. 91, no. 23, 233511, 2007. M. H. Wong et al., "INVITED REVIEW N-polar GaN epitaxy and high electron mobility transistors", Semiconductor Science and Technology, vol. 28, 074009, 2013. S. Kolluri et al., "N-Polar GaN MIS-HEMTs With a 12.1-W/mm Continuous-Wave Output Power Density at 4 GHz on Sapphire Substrate", IEEE Electron Device Letters, vol. 32, no. 5, pp. 635-637, 2111.

As mentioned above, reducing the contact resistance of ohmic electrodes in N-polar GaN-based HEMTs has the following problems. First, regrowth of n-type GaN alone is limited by the physical properties of GaN, restricting improvements in device characteristics. Furthermore, regrowth inevitably exposes the regrowth interface to the atmosphere, which affects device characteristics due to impurity incorporation into the regrowth interface and regrowth layer. Thus, in the past, there was a problem in that reducing the contact resistance of ohmic electrodes in N-polar GaN-based HEMTs was not easily achieved.

The present invention has been made to solve the above problems, and aims to make it easy to reduce the contact resistance of ohmic electrodes in N-polar GaN-based HEMTs.

The method for fabricating a field-effect transistor according to the present invention comprises the following steps: a first step of forming a barrier layer made of a nitride semiconductor on a substrate, the main surface of which is N-polar; a second step of forming a channel layer made of a nitride semiconductor on the barrier layer, the main surface of which is N-polar; a third step of forming an arsenic-doped layer by converting the channel layer to As at a location where an ohmic electrode will be located, the ohmic electrode being electrically connected to a two-dimensional electron gas channel formed in the channel layer near the interface between the heterojunction barrier layer and the channel layer, and then heating and removing the formed arsenic-doped layer to form a recess in the channel layer; a fourth step of growing an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element so as to fill the recess, thereby forming a contact layer; and a fifth step of forming an ohmic electrode on the contact layer.

The field- effect transistor also includes: a barrier layer made of a nitride semiconductor and having an N-polarity main surface formed on a substrate; a channel layer made of a nitride semiconductor and having an N-polarity main surface formed on the barrier layer and forming a heterojunction with the barrier layer; a recess formed in the channel layer at a location where an ohmic electrode is to be disposed, the ohmic electrode being electrically connected to a channel formed by two-dimensional electron gas formed in the channel layer near the interface between the barrier layer and the channel layer; a contact layer made of an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element, formed so as to fill the recess; and an ohmic electrode formed in contact with the contact layer.

As explained above, according to the present invention, it is possible to easily reduce the contact resistance of ohmic electrodes in N-polar GaN-based HEMTs.

FIG. 1A is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1C is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1D is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1E is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1F is a flowchart illustrating a method for fabricating a portion of a field effect transistor according to an embodiment of the present invention. FIG. 1G is a timing chart for explaining a method for manufacturing a part of a field effect transistor according to an embodiment of the present invention. FIG. 1H is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1I is a cross-sectional view showing the state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1J is a cross-sectional view showing a state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1K is a cross-sectional view showing the configuration of a field effect transistor according to an embodiment of the present invention.

Below, a method for manufacturing a field effect transistor according to an embodiment of the present invention will be described with reference to Figures 1A to 1J.

First, as shown in Figure 1A, a buffer layer 102 is formed on a substrate 101, and a barrier layer 103 made of a nitride semiconductor is formed on this, with its main surface being N-polar (group V polarity) (step 1). Subsequently, a channel layer 104 made of a nitride semiconductor is formed on the barrier layer 103, with its main surface being N-polar (step 2). Subsequently, a gate insulating layer 105 is formed on the channel layer 104.

The substrate 101 may be made of, for example, sapphire, silicon carbide, silicon, GaN, etc. The buffer layer 102 may be made of, for example, GaN. The barrier layer 103 may be made of, for example, AlGaN. The channel layer 104 may be made of, for example, GaN. The gate insulating layer 105 may be made of, for example, an insulating material such as SiN.

For example, if the substrate 101 is a sapphire substrate, the surface of the substrate 101 is nitrided by high-temperature heat treatment in a source gas atmosphere such as ammonia, and then a nucleation layer is grown to a thickness of approximately 20 nm. After this, a buffer layer 102 is grown to a thickness of approximately several hundred nm to sufficiently reduce defects. The buffer layer 102 is formed with its main surface being N-polar. A nitride semiconductor (such as GaN or AlGaN) with an N-polarity as its main surface orientation can be grown on the buffer layer 102 thus formed. On the other hand, if the substrate 101 is a GaN single crystal substrate or an AlN single crystal substrate with an N-polarity as its main surface orientation, a nitride semiconductor with an N-polarity as its main surface orientation can be grown without the above-mentioned nitriding or nucleation layer growth.

In addition, by bonding a layered structure of a channel layer and a barrier layer crystal-grown on a growth substrate with a group III plane as the primary surface orientation to the substrate 101 and then removing the growth substrate, it is possible to obtain a state in which a barrier layer 103 and a channel layer 104 with an N plane as the primary surface orientation are layered in this order on the substrate 101.

When the gate insulating layer 105 is made of, for example, SiN, it can be formed by deposition using, for example, a sputtering method.

Next, as shown in FIG. 1B, a mask pattern 121 having an opening area in the electrode formation region 151 is formed. The electrode formation region 151 is where an ohmic electrode is disposed that electrically connects to a channel formed by two-dimensional electron gas in the channel layer 104 near the interface between the barrier layer 103 and the channel layer 104, which are heterojunctions. As described below, the mask pattern 121 will be exposed to high temperatures in subsequent processes, and therefore can be made of a heat-resistant material such as silicon oxide.

Next, the gate insulating layer 105 is patterned by selective etching using the mask pattern 121, exposing the upper surface of the channel layer 104 in the electrode formation region 151, as shown in Figure 1C. For example, the gate insulating layer 105 made of SiN can be etched by RIE using an F-based gas.

Next, as shown in Figure 1D, a portion of the channel layer 104 in the electrode formation region 151 in the thickness direction is converted to As to form an As-doped layer 122, and then the As-doped layer 122 is heated and removed to form a recess 123 in the channel layer 104a as shown in Figure 1E (third step). The recess 123 is formed by repeatedly forming the As-doped layer 122 and removing the As-doped layer 122.

The formation of the recess 123 will now be described in more detail with reference to FIGS. 1F and 1G. First, in step S101, the substrate 101 is loaded into a growth chamber of a processing apparatus with the channel layer 104 exposed. The processing apparatus may be any apparatus capable of introducing _AsH and _H into the growth chamber and heating the sample loaded into the processing chamber to 700° C. or higher. For example, an MOCVD furnace capable of growing GaAs crystals may be used, but the present invention is not limited thereto, and a dedicated processing apparatus may also be used.

Next, in step S102, the temperature inside the growth chamber is raised to a predetermined processing temperature, for example, 700° C. It is desirable to raise the temperature in an _N atmosphere, which can suppress thermal decomposition reactions using hydrogen. However, since GaN hardly decomposes at about 700° C. even in an _H atmosphere, an _H atmosphere or an _N / _H atmosphere can also be used.

Once the growth chamber reaches the set temperature (step S103: yes), the growth chamber is set to an _H atmosphere. In step S104, _AsH is supplied into the growth chamber along with _H to maintain the _AsH -containing _H atmosphere. In this manner, in the channel layer 104 heated to approximately 700° _C in an atmosphere containing As, the N element, a group V element, replaces the As in the atmosphere, forming an As-doped layer 122 ( FIG. 1D ). The thickness of the As-doped layer 122 varies depending on the temperature inside the growth chamber and the time for which _AsH is flowed (supplied), but is typically approximately 1 to 2 nm. The As-doped layer 122 formed on the surface of the GaN channel layer 104 is composed of GaAs.

After the As-containing layer 122 is heated for a set time (step S105: yes), the supply of _AsH3 to the growth chamber is stopped and the growth chamber is maintained in a _H2 atmosphere for a set time (step S106). The As-containing layer 122 is heated in this state and is removed by a thermal decomposition reaction caused by _H2 (FIG. 1E).

When the time for maintaining the _H atmosphere in the growth chamber reaches a set time (step S107), steps S104 to S107 are repeated until the As formation and removal of the As formation layer are repeated a set number of times (until step S108 returns "yes"). After the set number of times has been performed (step S108 returns "yes"), the temperature inside the processing chamber is lowered and the gas inside the processing chamber is evacuated in step S109, and then the substrate 101 to be processed is carried out of the processing chamber in step S110.

The GaN that constitutes the channel layer 104 below the As layer 122 hardly undergoes thermal decomposition at temperatures of around 700°C, so etching proceeds only through the thickness of the As layer 122 on the surface, and the etching stops when the As layer 122 is completely removed and the surface of the channel layer 104a is exposed.

In this way, by repeating the process (steps S104 to S106) of forming an As-layer 122 by assimilating the surface in an AsH ₃ /H ₂ atmosphere, and then thermally decomposing the As-layer 122 in an H ₂ atmosphere after stopping the supply of AsH ₃ , it is possible to etch the electrode formation region 151 of the channel layer 104 by 1 to 2 nm at a time.

In this etching technique, the etching amount per cycle is determined by the thickness of the As-doped layer that is formed. The thickness of the As-doped layer can be controlled by the temperature in the processing chamber and the time for which _AsH3 is flowed. Furthermore, the thermal decomposition reaction of the As-doped layer is a self-limiting reaction due to the difference in thermal decomposition temperature between the As-doped layer and nitride semiconductors such as GaN. This allows for highly reproducible etching by precisely controlling the etching amount for each cycle.

Another advantage of this etching method is that it hardly forms a damaged layer on the thin film surface during etching. In etching methods such as RIE, which are commonly used for etching GaN, ions and other particles are irradiated onto the etching surface, which creates a damaged layer containing many defects on the surface after etching.

The etching method using As formation and thermal decomposition of the As formation layer described above does not involve physical particle irradiation, which reduces the factors that create defects on the surface of the channel layer 104a after etching, thereby reducing damage.

As described above, by performing the As conversion and thermal decomposition of the As layer a set number of times, a channel layer 104a is formed in the electrode formation region 151, with a recess 123 of a predetermined depth, as shown in Figure 1H. The thickness of the channel layer 104a with the recess 123 formed in the electrode formation region 151 can be, for example, approximately 5 nm. In this way, leaving a thin channel layer 104a in the electrode formation region 151 is intended to leave a 2DEG formed near the interface between the channel layer 104a and the barrier layer 103 in the electrode formation region 151.

As the thin portion of the channel layer 104a in the electrode formation region 151 described above becomes thinner, the carrier density of the 2DEG decreases, and as it becomes thicker, the distance between the 2DEG and the contact layer described below increases, so variations in the thickness of the thin portion described above affect the contact resistance. For this reason, etching of the recess 123 must be a highly reproducible process. The etching by As formation and thermal decomposition of the As formation layer described above is an extremely reproducible process and is suitable for forming the recess 123.

Next, an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element is grown (regrown) to fill the recess 123, thereby forming contact layers 106 and 107 in the electrode formation region 151, as shown in FIG. 1I (Step 4). The contact layers 106 and 107 can be made of, for example, GaAs, InAs, InGaAs, or a multilayer structure formed by stacking these elements. After this, a source electrode 108 and a drain electrode 109 are formed on the contact layers 106 and 107 (Step 5). A gate electrode 110 is also formed on the channel layer 104 (Step 6). In this example, the source electrode 108 and the drain electrode 109, which are disposed on either side of the gate electrode 110, serve as ohmic electrodes.

As shown in Figure 1J, the field-effect transistor obtained by the above-described fabrication method includes a barrier layer 103 made of a nitride semiconductor with its main surface being N-polar and formed on a substrate 101; a channel layer 104 made of a nitride semiconductor with its main surface being N-polar and formed on the barrier layer 103, forming a heterojunction with the barrier layer 103; a recess 123 formed in the channel layer 104 at a location where an ohmic electrode is to be located, the ohmic electrode electrically connecting to a two-dimensional electron gas channel formed in the channel layer 104 near the interface between the barrier layer 103 and the channel layer 104; contact layers 106 and 107 made of an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element, formed to fill the recess 123; and ohmic electrodes formed on and in contact with the contact layers 106 and 107. In this example, a gate electrode 110 is formed on the channel layer 104, and the ohmic electrodes are a source electrode 108 and a drain electrode 109 disposed on either side of the gate electrode 110.

As shown in Figure 1K, a recess can be formed through the channel layer 104b so that the channel layer 104b is completely removed below the source electrode 108 and drain electrode 109. In this configuration, there is no channel layer below the contact layers 106 and 107, and no 2DEG is formed. In this configuration, the contact layers 106 and 107 contact (connect) with the 2DEG formed in the channel layer 104b near the interface between the barrier layer 103 and the channel layer 104b in the direction in which they are arranged (the direction parallel to the plane of the substrate 101). In other words, the contact layers 106 and 107 contact (connect) with the 2DEG on the side surfaces of the channel layer 104b.

In this configuration, the side surfaces of the channel layer 104b where the 2DEG is formed are exposed during the fabrication process, making it important to minimize damage to these surfaces. If damage is introduced to the side surfaces of the channel layer 104b where the 2DEG is formed, for example, by an etching process, this can significantly affect the electrical characteristics of the device, such as through carrier trapping due to defects formed by the damage. However, etching using the aforementioned As conversion and thermal decomposition of the As conversion layer does not, in principle, introduce damage due to particle irradiation such as reactive ions, making it possible to perform etching with low damage.

As explained above, according to the present invention, a contact layer is formed by forming a recess in a channel layer that forms a heterojunction on a barrier layer formed on a substrate with an N-polar main surface, for example, by etching using As-conversion and thermal decomposition of the As-conversion layer, and filling the recess with an n-type III-V compound semiconductor. This makes it easy to reduce the contact resistance of the ohmic electrode in an N-polarity GaN-based HEMT.

It is to be understood that the present invention is not limited to the embodiments described above, and that many modifications and combinations can be made by a person skilled in the art within the technical spirit of the present invention.

101...substrate, 102...buffer layer, 103...barrier layer, 104, 104a...channel layer, 105...gate insulating layer, 106...contact layer, 107...contact layer, 108...source electrode, 109...drain electrode, 110...gate electrode, 121...mask pattern, 122...As layer, 123...recess, 151...electrode formation area.

Claims (4)

a first step of forming a barrier layer made of a nitride semiconductor on a substrate, the barrier layer having an N-polar main surface;
a second step of forming a channel layer made of a nitride semiconductor on the barrier layer, the channel layer having an N-polarity main surface;
a third step of forming an As-doped layer by converting the channel layer to As at a location where an ohmic electrode electrically connected to a channel of two-dimensional electron gas formed in the channel layer near an interface between the barrier layer and the channel layer, which are heterojunction with each other, is to be disposed, and removing the As-doped layer by heating, thereby forming a recess in the channel layer;
a fourth step of growing an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a V-group element so as to fill the recess to form a contact layer;
and a fifth step of forming the ohmic electrode on the contact layer. 2. The method for fabricating a field effect transistor according to claim 1,
The method for producing a field effect transistor is characterized in that the recess is formed by repeating the steps of forming the As-doped layer and removing the As-doped layer. 3. The method for fabricating a field effect transistor according to claim 1,
The method for manufacturing a field effect transistor, wherein the recess is formed so as to penetrate the channel layer. The method for producing a field effect transistor according to any one of claims 1 to 3,
a sixth step of forming a gate electrode on the channel layer;
a source electrode and a drain electrode disposed on either side of the gate electrode;