JP7744006B2 - Acoustic Wave Devices - Google Patents

Description

This disclosure relates to an acoustic wave device having a device chip.

Patent Document 1 discloses an acoustic wave device in which an acoustic wave device chip is sealed with a metal sealing portion. In this acoustic wave device, the metal sealing portion is brought into contact with the metal pattern of the wiring substrate to prevent insufficient grounding of the metal sealing portion.

JP 2015-41680 A

Further quality improvements are required for acoustic wave devices in which the device chip is covered with a metal layer. For example, there is a demand for smaller packages, improved airtightness, improved shielding from external noise, improved heat dissipation, and improved isolation characteristics through strengthened grounding.

The present disclosure has been made to solve the above-mentioned problems. The purpose of the present disclosure is to improve the quality of acoustic wave devices having metal layers.

The acoustic wave device according to the present disclosure includes:
a package substrate having a die-attach surface wiring pattern and an internal wiring pattern;
a device chip electrically connected to the package substrate;
a metal layer covering the device chip and bonded to the internal wiring pattern ;
the metal layer is bonded to the die-attach surface wiring pattern;
the metal layer contacts a side surface of the package substrate and is bonded to a side surface of the internal wiring pattern;
In a cross-sectional view, the length of the portion where the metal layer contacts the side surface of the package substrate is equal to or greater than half the thickness of the package substrate .

One aspect of the present disclosure is that the internal wiring pattern is a grounding pattern.

One aspect of the present disclosure is to have an insulating layer disposed between the device chip and the metal layer.

the insulator layer contacts the die-attach surface of the package substrate;
In one aspect of the present disclosure, the metal layer is in contact with the die-attach surface via the insulator layer and is bonded to a side surface of the die-attach surface wiring pattern.

In one aspect of the present disclosure, the die-attach surface wiring pattern is made of gold or an alloy containing gold, and the internal wiring pattern is made of copper or an alloy containing copper.

In one aspect of the present disclosure, the substrate of the device chip is a substrate in which a piezoelectric substrate is bonded to a support substrate made of sapphire, silicon, alumina, spinel, quartz, or glass.

One aspect of the present disclosure is to have passive components mounted on the package substrate and an integrated circuit mounted on the package substrate.

This disclosure makes it possible to provide acoustic wave devices of improved quality.

1 is a cross-sectional view of an acoustic wave device according to a first embodiment. FIG. 10 is a cross-sectional view of an acoustic wave device according to a comparative example. FIG. 10 is a cross-sectional view of an acoustic wave device according to a second embodiment. FIG. 1 is a comparison diagram of device sizes. FIG. 10 is a cross-sectional view of an acoustic wave device according to a third embodiment.

Embodiments will be described with reference to the accompanying drawings. In each drawing, identical or corresponding parts are designated by the same reference numerals. Duplicate descriptions of such parts may be simplified or omitted.

Embodiment 1.
1 is a longitudinal cross-sectional view of an acoustic wave device 10 according to a first embodiment. The acoustic wave device 10 includes a package substrate 12. The upper surface of the package substrate 12 is a die-attach surface. Die-attach surface wiring patterns 12a, 12f, and 12h are formed on this die-attach surface. The die-attach surface wiring patterns 12a, 12f, and 12h are wiring patterns exposed on the upper surface of the package substrate 12. According to one example, the die-attach surface wiring patterns 12a, 12f, and 12h can be formed of gold or an alloy containing gold.

The package substrate 12 can include multiple wiring structures. In the example of Figure 1, the wiring structures include a first structure 12A, a second structure 12B, and a third structure 12C. The first structure 12A has a via 12b that contacts the die-attach surface wiring pattern 12a described above. This via 12b electrically connects the die-attach surface wiring pattern 12a above the via 12b to the internal wiring pattern 12c below the via 12b. The internal wiring pattern 12c is a wiring pattern embedded inside the base material of the package substrate 12. The base material is an insulator such as ceramic or resin.

The first structure 12A has a via 12d that contacts the internal wiring pattern 12c. This via 12d electrically connects the internal wiring pattern 12c above the via 12d to the bottom wiring pattern 12e below the via 12b. The bottom wiring pattern 12e is a wiring pattern exposed on the bottom surface of the package substrate 12.

The package substrate 12 has a second structure 12B next to the first structure 12A. The second structure 12B has a die-attach surface wiring pattern 12f, a bottom surface wiring pattern 12g, and vias and internal wiring patterns that electrically connect these.

The package substrate 12 includes a third structure 12C next to the second structure 12B. The third structure includes, from top to bottom, a die-attach surface wiring pattern 12h, a via 12i, an internal wiring pattern 12j, a via 12k, and a bottom wiring pattern 12m. According to one example, the internal wiring patterns in the first to third structures can be made of copper or a copper-containing alloy. According to one example, the die-attach surface wiring patterns 12a, 12f, and 12h are gold-plated patterns, and the portions of the first structure 12A, the second structure 12B, and the third structure 12C other than the die-attach surface wiring patterns 12a, 12f, and 12h can be made of copper or a copper-containing alloy.

As another example, a multilayer wiring board or PCB having a different configuration can be used as the package substrate 12. For example, the total number of wiring patterns can be changed, or the number of wiring structures exemplified as the first to third structures can be increased or decreased.

The device chip 20 is flip-chip mounted on the die-attach surface of this package substrate 12 using bumps 40, 42. The bumps 40, 42 are made of, for example, Au. The device chip 20 is, for example, a surface acoustic wave (SAW) device chip in which a comb-shaped electrode that excites acoustic waves is provided on one surface of a piezoelectric substrate. The piezoelectric substrate may be, for example, a lithium tantalate substrate or a lithium niobate substrate. In another example, the substrate of the device chip 20 is a substrate in which a piezoelectric substrate is bonded to a support substrate made of sapphire, silicon, alumina, spinel, quartz, or glass.

In one example, bump 40 connects the terminal of the device chip 20 to die-attach surface wiring pattern 12a. Bump 42 connects the terminal of the device chip 20 to die-attach surface wiring pattern 12h. Any of the first, second, and third structures 12A, 12B, and 12C can be used as ground wiring. For example, second structure 12B can be used as ground wiring. In this case, the internal wiring pattern of second structure 12B becomes a ground pattern. In another example, first structure 12A can be used as ground wiring. In this case, the internal wiring pattern 12c of first structure 12A becomes a ground pattern. In this way, bumps 40 and 42 can electrically connect the device chip 20 to the package substrate 12.

The device chip 20 is covered by an insulator layer 22 and a metal layer 24. In the example of FIG. 1, the insulator layer 22 contacts the device chip 20, and the metal layer 24 contacts the device chip 20 via the insulator layer 22. By covering the device chip 20 with the insulator layer 22 and the metal layer 24, an airtight space is provided between the device chip 20 and the package substrate 12. According to one example, the material of the metal layer 24 is Ni or an alloy containing Ni.

In the example of Figure 1, the insulator layer 22 is in direct contact with the die-attach surface wiring patterns 12a and 12h, so it can be said that the insulator layer 22 is in contact with the die-attach surface of the package substrate 12. On the other hand, the metal layer 24 is not bonded to the die-attach surface wiring patterns 12a and 12h. In other words, the metal layer 24 is in contact with the die-attach surface via the insulator layer 22 and is not bonded to the die-attach surface wiring patterns. The metal layer 24 is bonded to the internal wiring patterns 12c and 12j. By providing a stepped structure in the package substrate 12 and exposing the top surfaces of the internal wiring patterns 12c and 12j in the stepped portions, the metal layer 24 can be bonded to these top surfaces. In Figure 1, the bonded portion between the metal layer 24 and the internal wiring pattern 12c is represented as bond 30. Furthermore, the bonded portion between the metal layer 24 and the internal wiring pattern 12j is represented as bond 32. According to one example, the bonded portions 30 and 32 are an alloy between the metal layer 24 and the internal wiring pattern 23c. In another example, the joints 30, 32 are part of the metal layer 24 or the internal wiring patterns 12c, 12j.

Figure 2 is a cross-sectional view of an acoustic wave device according to a comparative example. The acoustic wave device according to the comparative example differs from the acoustic wave device 10 of Figure 1 in the method of bonding the metal layer 24 to the package substrate 12. In the acoustic wave device according to the comparative example, the metal layer 24 is bonded to the die-attach surface wiring patterns 12a and 12h. These bonded portions are illustrated as bonding portions 38 and 39. The metal layer 24 of the comparative example is not bonded to the internal wiring patterns 12c and 12j.

In one example, the insulator layer 22 of the acoustic wave device of Figures 1 and 2 is formed by the following process. First, a resin sheet is placed on the device chip 20. The resin sheet is, for example, a sheet of liquid epoxy resin. In another example, the resin sheet can be made of a synthetic resin other than epoxy resin, such as polyimide. A protective film made of polyethylene terephthalate (PET) can be provided on the upper surface of the resin sheet, or a base film made of polyester can be provided on the lower surface of the resin sheet. By placing the resin sheet on the device chip 20, the resin sheet is temporarily fixed to one or more device chips.

Next, resin is applied to the sides of the chip using vacuum lamination. For example, resin is applied to the areas on the sides of the chip while applying pressure to the resin sheet in the direction of the package substrate 12 under vacuum. Pressure can be applied to the resin sheet in the direction of the package substrate 12 using silicone rubber inflated with compressed air, or pressure can be applied to the resin sheet in the direction of the package substrate 12 using a rubber plate. If there are multiple chips, resin is applied between the chips.

Instead of vacuum lamination, resin may be provided on the sides of or between chips using other methods. For example, a method known as hot roller lamination may be used. In hot roller lamination, the workpiece is passed between upper and lower rollers that are heated to at least the softening temperature of the resin sheet. This provides the resin sheet to the top surfaces of one or more device chips, and fills the sides of the device chips and the top surface of the package substrate 12.

As described above, the insulator layer 22 is formed by thermally curing the resin while it is still covering the device chip. If the resin is thermally cured while only in contact with the top surface of the package substrate 12, as in the comparative example, the resin may seep into the area between the device chip 20 and the package substrate 12, depending on the distribution of the die-attach surface wiring pattern. In contrast, by providing a step in the package substrate 12 as shown in FIG. 1 and allowing the resin to reach the side of the step before thermally curing the resin, the shape of the resin wall around the device chip 20 can be stabilized. In other words, the resin can be prevented from seeping into the area between the device chip 20 and the package substrate 12.

If the die-attach surface wiring pattern were gold-plated, the adhesion between the gold plating and the resin would be poor. Therefore, if the insulator layer 22 were primarily in contact with the die-attach surface wiring pattern of the package substrate 12, as in the comparative example, the adhesion of the insulator layer 22 would be poor. However, as shown in Figure 1, if the insulator layer 22 is in contact not only with the die-attach surface wiring pattern but also with the base material of the package substrate 12 and the internal wiring patterns 12c and 12j, the insulator layer 22 can be adhered to the package substrate 12. According to one example, contacting the insulator layer 22 with the internal wiring pattern containing Cu, the metal layer 24 containing Ni, and the insulator layer 22 improves their connectivity.

In this way, by strengthening the connection between the insulator layer 22 and metal layer 24 and the package substrate 12, the airtightness of the acoustic wave device is improved, the shielding effect from external noise is enhanced, and the ground connection is strengthened (i.e., isolation characteristics are improved).

Embodiment 2.
3 is a cross-sectional view of an acoustic wave device according to a second embodiment. The metal layer 24 in the second embodiment is bonded to both the die-attach surface wiring patterns 12a and 12h and the internal wiring patterns 12c and 12j. In the example of FIG. 3, the metal layer 24 is bonded to the side surfaces of the die-attach surface wiring patterns 12a and 12h and the internal wiring patterns 12c and 12j. Bonds 50, 52, 54, and 56 are located on the side surfaces of the die-attach surface wiring pattern 12a, the internal wiring pattern 12c, the die-attach surface wiring pattern 12h, and the internal wiring pattern 12j, respectively.

By bonding the metal layer 24 to both the die-attach surface wiring patterns 12a, 12h and the internal wiring patterns 12c, 12j, the connection between the metal layer 24 and the package substrate 12 can be strengthened.

According to one example, in a cross-sectional view, the length of the portion where the metal layer 24 and the side of the package substrate 12 contact can be made equal to or greater than half the thickness of the package substrate 12. In other words, the vertical length of the portion where the metal layer 24 and the package substrate 12 contact is equal to or greater than half the thickness of the package substrate 12. In this way, by ensuring a sufficient contact length between the side of the package substrate 12 and the metal layer 24, the connectivity between them can be improved.

Furthermore, by providing a step in the package substrate 12 and extending the metal layer 24 up to that step, the position of the metal layer 24 can be stabilized.

Figure 4 is a diagram comparing the device sizes of an acoustic wave device according to embodiment 2 and an acoustic wave device according to a comparative example. The upper row shows the acoustic wave device according to the comparative example, and the lower row shows the acoustic wave device according to embodiment 2. In the comparative example, junctions 38 and 39 are formed horizontally, whereas in embodiment 2, junctions 50, 52, 54, and 56 are formed vertically. Therefore, compared to the comparative example, the acoustic wave device according to embodiment 2 is more suitable for miniaturization.

Embodiment 3.
5 is a cross-sectional view of an acoustic wave device according to embodiment 3. In addition to the device chip 20, this acoustic wave device includes passive components 60 mounted on a package substrate 12 and an integrated circuit 62 mounted on the package substrate 12. According to one example, the passive components 60 are bonded to the die-attach surface wiring pattern 12n by solder 61. The integrated circuit 62 is electrically connected to the die-attach surface wiring pattern 12n by solder balls 63.

The insulator layer 22 and metal layer 24 cover the device chip 20, passive components 60, and integrated circuit 62. The metal layer 24 is bonded to the die-attach surface wiring pattern 12n at many points. Furthermore, the metal layer 24 is bonded to the internal wiring pattern 12p between the passive components 60 and the integrated circuit 62. The bonding position between the metal layer 24 and the internal wiring pattern can be any position. There can also be multiple such bonding positions. By bonding the metal layer 24 to the internal wiring pattern, the above-mentioned effects can be achieved. A resin layer 70 is provided on the metal layer 24 for the purposes of protecting the device and improving handling.

In this way, even in acoustic wave devices that incorporate multiple components, the quality of the acoustic wave device can be improved by joining the metal layer to the internal wiring pattern.

While several aspects of at least one embodiment have been described, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the scope of this disclosure.

It should be understood that the embodiments of the methods and apparatus described herein are not limited in their application to the details of construction and arrangement of components set forth in the foregoing description or illustrated in the accompanying drawings. The methods and apparatus may be implemented in other embodiments and practiced or carried out in various ways.

Specific implementation examples are provided here for illustrative purposes only and are not intended to be limiting.

The phraseology and terminology used in this disclosure are for purposes of description and should not be regarded as limiting. The use herein of "including," "comprising," "having," "including," and variations thereof means the inclusion of the items listed thereafter and equivalents thereof and additional items.

References to "or" may be construed as meaning that any term described with "or" refers to one, more than one, and all of the described terms.

All references to front, back, left, right, top, bottom, top, bottom, width, length, and front and back are intended for convenience of description. Such references do not limit the components of this disclosure to any one positional or spatial orientation. Accordingly, the above description and drawings are by way of example only.

REFERENCE SIGNS LIST 10 Acoustic wave device 12 Package substrate 12a, 12f, 12h Die attach surface wiring pattern 12c, 12j Internal wiring pattern 22 Insulator layer 24 Metal layer 30, 32, 50, 52, 54, 56 Joint

Claims (7)

a package substrate having a die-attach surface wiring pattern and an internal wiring pattern;
a device chip electrically connected to the package substrate;
a metal layer covering the device chip and bonded to the internal wiring pattern ;
the metal layer is bonded to the die-attach surface wiring pattern;
the metal layer contacts a side surface of the package substrate and is bonded to a side surface of the internal wiring pattern;
An acoustic wave device in which, in a cross-sectional view, the length of a portion where the metal layer contacts the side surface of the package substrate is equal to or greater than half the thickness of the package substrate . The acoustic wave device according to claim 1 , wherein the internal wiring pattern is a grounding pattern. The acoustic wave device of claim 1, further comprising an insulating layer disposed between the device chip and the metal layer. the insulator layer contacts the die-attach surface of the package substrate;
The acoustic wave device according to claim 3 , wherein the metal layer is in contact with the die-attach surface via the insulator layer and is bonded to a side surface of the die-attach surface wiring pattern. the die-attach surface wiring pattern is made of gold or an alloy containing gold,
The acoustic wave device according to claim 1 , wherein the internal wiring pattern is made of copper or an alloy containing copper. 6. The acoustic wave device according to claim 1, wherein the substrate of the device chip is a substrate in which a piezoelectric substrate and a support substrate made of sapphire, silicon, alumina, spinel, quartz crystal, or glass are bonded together. a passive component mounted on the package substrate;
The acoustic wave device according to claim 1 , further comprising: an integrated circuit mounted on the package substrate.